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x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
a65babc9
L		 284 };
285
252b5132
RH		 286struct _i386_insn
287 {
47926f60 288 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 289 insn_template tm;
252b5132 290
7d5e4556
L		 291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
252b5132
RH		 293 char suffix;
294
47926f60 295 /* OPERANDS gives the number of given operands. */
252b5132
RH		 296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
47926f60 300 operands. */
252b5132
RH		 301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 304 use OP[i] for the corresponding operand. */
40fb9820 305 i386_operand_type types[MAX_OPERANDS];
252b5132 306
520dc8e8
AM		 307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
252b5132 310
3e73aa7c
JH		 311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313#define Operand_PCrel 1
314
252b5132 315 /* Relocation type for operand */
f86103b7 316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 317
252b5132
RH		 318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 325 explicit segment overrides are given. */
ce8a8b2f 326 const seg_entry *seg[2];
252b5132 327
8325cc63
JB		 328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
252b5132
RH		 331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 337 addressing modes of this insn are encoded. */
252b5132 338 modrm_byte rm;
3e73aa7c 339 rex_byte rex;
43234a1e 340 rex_byte vrex;
252b5132 341 sib_byte sib;
c0f3af97 342 vex_prefix vex;
b6169b20 343
43234a1e
L		 344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
86fa6981
L		 356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
891edac4 363
a501d77e
L		 364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
f8a5c266 371
6b6b6807
L		 372 /* Prefer the REX byte in encoding. */
373 bfd_boolean rex_encoding;
374
b6f8c7c4
L		 375 /* Disable instruction size optimization. */
376 bfd_boolean no_optimize;
377
86fa6981
L		 378 /* How to encode vector instructions. */
379 enum
380 {
381 vex_encoding_default = 0,
382 vex_encoding_vex2,
383 vex_encoding_vex3,
384 vex_encoding_evex
385 } vec_encoding;
386
d5de92cf
L		 387 /* REP prefix. */
388 const char *rep_prefix;
389
165de32a
L		 390 /* HLE prefix. */
391 const char *hle_prefix;
42164a71 392
7e8b059b
L		 393 /* Have BND prefix. */
394 const char *bnd_prefix;
395
04ef582a
L		 396 /* Have NOTRACK prefix. */
397 const char *notrack_prefix;
398
891edac4 399 /* Error message. */
a65babc9 400 enum i386_error error;
252b5132
RH		 401 };
402
403typedef struct _i386_insn i386_insn;
404
43234a1e
L		 405/* Link RC type with corresponding string, that'll be looked for in
406 asm. */
407struct RC_name
408{
409 enum rc_type type;
410 const char *name;
411 unsigned int len;
412};
413
414static const struct RC_name RC_NamesTable[] =
415{
416 { rne, STRING_COMMA_LEN ("rn-sae") },
417 { rd, STRING_COMMA_LEN ("rd-sae") },
418 { ru, STRING_COMMA_LEN ("ru-sae") },
419 { rz, STRING_COMMA_LEN ("rz-sae") },
420 { saeonly, STRING_COMMA_LEN ("sae") },
421};
422
252b5132
RH		 423/* List of chars besides those in app.c:symbol_chars that can start an
424 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 425const char extra_symbol_chars[] = "*%-([{}"
252b5132 426#ifdef LEX_AT
32137342
NC		 427 "@"
428#endif
429#ifdef LEX_QM
430 "?"
252b5132 431#endif
32137342 432 ;
252b5132 433
29b0f896
AM		 434#if (defined (TE_I386AIX) \
435 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 436 && !defined (TE_GNU) \
29b0f896 437 && !defined (TE_LINUX) \
8d63c93e
RM		 438 && !defined (TE_NACL) \
439 && !defined (TE_NETWARE) \
29b0f896 440 && !defined (TE_FreeBSD) \
5b806d27 441 && !defined (TE_DragonFly) \
29b0f896 442 && !defined (TE_NetBSD)))
252b5132 443/* This array holds the chars that always start a comment. If the
b3b91714
AM		 444 pre-processor is disabled, these aren't very useful. The option
445 --divide will remove '/' from this list. */
446const char *i386_comment_chars = "#/";
447#define SVR4_COMMENT_CHARS 1
252b5132 448#define PREFIX_SEPARATOR '\\'
252b5132 449
b3b91714
AM		 450#else
451const char *i386_comment_chars = "#";
452#define PREFIX_SEPARATOR '/'
453#endif
454
252b5132
RH		 455/* This array holds the chars that only start a comment at the beginning of
456 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 457 .line and .file directives will appear in the pre-processed output.
458 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 459 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 460 #NO_APP at the beginning of its output.
461 Also note that comments started like this one will always work if
252b5132 462 '/' isn't otherwise defined. */
b3b91714 463const char line_comment_chars[] = "#/";
252b5132 464
63a0b638 465const char line_separator_chars[] = ";";
252b5132 466
ce8a8b2f
AM		 467/* Chars that can be used to separate mant from exp in floating point
468 nums. */
252b5132
RH		 469const char EXP_CHARS[] = "eE";
470
ce8a8b2f
AM		 471/* Chars that mean this number is a floating point constant
472 As in 0f12.456
473 or 0d1.2345e12. */
252b5132
RH		 474const char FLT_CHARS[] = "fFdDxX";
475
ce8a8b2f 476/* Tables for lexical analysis. */
252b5132
RH		 477static char mnemonic_chars[256];
478static char register_chars[256];
479static char operand_chars[256];
480static char identifier_chars[256];
481static char digit_chars[256];
482
ce8a8b2f 483/* Lexical macros. */
252b5132
RH		 484#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
485#define is_operand_char(x) (operand_chars[(unsigned char) x])
486#define is_register_char(x) (register_chars[(unsigned char) x])
487#define is_space_char(x) ((x) == ' ')
488#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
489#define is_digit_char(x) (digit_chars[(unsigned char) x])
490
0234cb7c 491/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 492static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
493
494/* md_assemble() always leaves the strings it's passed unaltered. To
495 effect this we maintain a stack of saved characters that we've smashed
496 with '\0's (indicating end of strings for various sub-fields of the
47926f60 497 assembler instruction). */
252b5132 498static char save_stack[32];
ce8a8b2f 499static char *save_stack_p;
252b5132
RH		 500#define END_STRING_AND_SAVE(s) \
501 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
502#define RESTORE_END_STRING(s) \
503 do { *(s) = *--save_stack_p; } while (0)
504
47926f60 505/* The instruction we're assembling. */
252b5132
RH		 506static i386_insn i;
507
508/* Possible templates for current insn. */
509static const templates *current_templates;
510
31b2323c
L		 511/* Per instruction expressionS buffers: max displacements & immediates. */
512static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
513static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 514
47926f60 515/* Current operand we are working on. */
ee86248c 516static int this_operand = -1;
252b5132 517
3e73aa7c
JH		 518/* We support four different modes. FLAG_CODE variable is used to distinguish
519 these. */
520
521enum flag_code {
522 CODE_32BIT,
523 CODE_16BIT,
524 CODE_64BIT };
525
526static enum flag_code flag_code;
4fa24527 527static unsigned int object_64bit;
862be3fb 528static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 529static int use_rela_relocations = 0;
530
7af8ed2d
NC		 531#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
532 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
533 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
534
351f65ca
L		 535/* The ELF ABI to use. */
536enum x86_elf_abi
537{
538 I386_ABI,
7f56bc95
L		 539 X86_64_ABI,
540 X86_64_X32_ABI
351f65ca
L		 541};
542
543static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 544#endif
351f65ca 545
167ad85b
TG		 546#if defined (TE_PE) || defined (TE_PEP)
547/* Use big object file format. */
548static int use_big_obj = 0;
549#endif
550
8dcea932
L		 551#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
552/* 1 if generating code for a shared library. */
553static int shared = 0;
554#endif
555
47926f60
KH		 556/* 1 for intel syntax,
557 0 if att syntax. */
558static int intel_syntax = 0;
252b5132 559
e89c5eaa
L		 560/* 1 for Intel64 ISA,
561 0 if AMD64 ISA. */
562static int intel64;
563
1efbbeb4
L		 564/* 1 for intel mnemonic,
565 0 if att mnemonic. */
566static int intel_mnemonic = !SYSV386_COMPAT;
567
5209009a 568/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 569static int old_gcc = OLDGCC_COMPAT;
570
a60de03c
JB		 571/* 1 if pseudo registers are permitted. */
572static int allow_pseudo_reg = 0;
573
47926f60
KH		 574/* 1 if register prefix % not required. */
575static int allow_naked_reg = 0;
252b5132 576
33eaf5de 577/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 578 instructions supporting it, even if this prefix wasn't specified
579 explicitly. */
580static int add_bnd_prefix = 0;
581
ba104c83 582/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 583static int allow_index_reg = 0;
584
d022bddd
IT		 585/* 1 if the assembler should ignore LOCK prefix, even if it was
586 specified explicitly. */
587static int omit_lock_prefix = 0;
588
e4e00185
AS		 589/* 1 if the assembler should encode lfence, mfence, and sfence as
590 "lock addl $0, (%{re}sp)". */
591static int avoid_fence = 0;
592
0cb4071e
L		 593/* 1 if the assembler should generate relax relocations. */
594
595static int generate_relax_relocations
596 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
597
7bab8ab5 598static enum check_kind
daf50ae7 599 {
7bab8ab5
JB		 600 check_none = 0,
601 check_warning,
602 check_error
daf50ae7 603 }
7bab8ab5 604sse_check, operand_check = check_warning;
daf50ae7 605
b6f8c7c4
L		 606/* Optimization:
607 1. Clear the REX_W bit with register operand if possible.
608 2. Above plus use 128bit vector instruction to clear the full vector
609 register.
610 */
611static int optimize = 0;
612
613/* Optimization:
614 1. Clear the REX_W bit with register operand if possible.
615 2. Above plus use 128bit vector instruction to clear the full vector
616 register.
617 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
618 "testb $imm7,%r8".
619 */
620static int optimize_for_space = 0;
621
2ca3ace5
L		 622/* Register prefix used for error message. */
623static const char *register_prefix = "%";
624
47926f60
KH		 625/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
626 leave, push, and pop instructions so that gcc has the same stack
627 frame as in 32 bit mode. */
628static char stackop_size = '\0';
eecb386c 629
12b55ccc
L		 630/* Non-zero to optimize code alignment. */
631int optimize_align_code = 1;
632
47926f60
KH		 633/* Non-zero to quieten some warnings. */
634static int quiet_warnings = 0;
a38cf1db 635
47926f60
KH		 636/* CPU name. */
637static const char *cpu_arch_name = NULL;
6305a203 638static char *cpu_sub_arch_name = NULL;
a38cf1db 639
47926f60 640/* CPU feature flags. */
40fb9820
L		 641static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
642
ccc9c027
L		 643/* If we have selected a cpu we are generating instructions for. */
644static int cpu_arch_tune_set = 0;
645
9103f4f4 646/* Cpu we are generating instructions for. */
fbf3f584 647enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 648
649/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 650static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 651
ccc9c027 652/* CPU instruction set architecture used. */
fbf3f584 653enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 654
9103f4f4 655/* CPU feature flags of instruction set architecture used. */
fbf3f584 656i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 657
fddf5b5b
AM		 658/* If set, conditional jumps are not automatically promoted to handle
659 larger than a byte offset. */
660static unsigned int no_cond_jump_promotion = 0;
661
c0f3af97
L		 662/* Encode SSE instructions with VEX prefix. */
663static unsigned int sse2avx;
664
539f890d
L		 665/* Encode scalar AVX instructions with specific vector length. */
666static enum
667 {
668 vex128 = 0,
669 vex256
670 } avxscalar;
671
43234a1e
L		 672/* Encode scalar EVEX LIG instructions with specific vector length. */
673static enum
674 {
675 evexl128 = 0,
676 evexl256,
677 evexl512
678 } evexlig;
679
680/* Encode EVEX WIG instructions with specific evex.w. */
681static enum
682 {
683 evexw0 = 0,
684 evexw1
685 } evexwig;
686
d3d3c6db
IT		 687/* Value to encode in EVEX RC bits, for SAE-only instructions. */
688static enum rc_type evexrcig = rne;
689
29b0f896 690/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 691static symbolS *GOT_symbol;
29b0f896 692
a4447b93
RH		 693/* The dwarf2 return column, adjusted for 32 or 64 bit. */
694unsigned int x86_dwarf2_return_column;
695
696/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
697int x86_cie_data_alignment;
698
252b5132 699/* Interface to relax_segment.
fddf5b5b
AM		 700 There are 3 major relax states for 386 jump insns because the
701 different types of jumps add different sizes to frags when we're
702 figuring out what sort of jump to choose to reach a given label. */
252b5132 703
47926f60 704/* Types. */
93c2a809
AM		 705#define UNCOND_JUMP 0
706#define COND_JUMP 1
707#define COND_JUMP86 2
fddf5b5b 708
47926f60 709/* Sizes. */
252b5132
RH		 710#define CODE16 1
711#define SMALL 0
29b0f896 712#define SMALL16 (SMALL | CODE16)
252b5132 713#define BIG 2
29b0f896 714#define BIG16 (BIG | CODE16)
252b5132
RH		 715
716#ifndef INLINE
717#ifdef __GNUC__
718#define INLINE __inline__
719#else
720#define INLINE
721#endif
722#endif
723
fddf5b5b
AM		 724#define ENCODE_RELAX_STATE(type, size) \
725 ((relax_substateT) (((type) << 2) | (size)))
726#define TYPE_FROM_RELAX_STATE(s) \
727 ((s) >> 2)
728#define DISP_SIZE_FROM_RELAX_STATE(s) \
729 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 730
731/* This table is used by relax_frag to promote short jumps to long
732 ones where necessary. SMALL (short) jumps may be promoted to BIG
733 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
734 don't allow a short jump in a 32 bit code segment to be promoted to
735 a 16 bit offset jump because it's slower (requires data size
736 prefix), and doesn't work, unless the destination is in the bottom
737 64k of the code segment (The top 16 bits of eip are zeroed). */
738
739const relax_typeS md_relax_table[] =
740{
24eab124
AM		 741 /* The fields are:
742 1) most positive reach of this state,
743 2) most negative reach of this state,
93c2a809 744 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 745 4) which index into the table to try if we can't fit into this one. */
252b5132 746
fddf5b5b 747 /* UNCOND_JUMP states. */
93c2a809
AM		 748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
749 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
750 /* dword jmp adds 4 bytes to frag:
751 0 extra opcode bytes, 4 displacement bytes. */
252b5132 752 {0, 0, 4, 0},
93c2a809
AM		 753 /* word jmp adds 2 byte2 to frag:
754 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 755 {0, 0, 2, 0},
756
93c2a809
AM		 757 /* COND_JUMP states. */
758 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
759 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
760 /* dword conditionals adds 5 bytes to frag:
761 1 extra opcode byte, 4 displacement bytes. */
762 {0, 0, 5, 0},
fddf5b5b 763 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 764 1 extra opcode byte, 2 displacement bytes. */
765 {0, 0, 3, 0},
766
767 /* COND_JUMP86 states. */
768 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
769 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
770 /* dword conditionals adds 5 bytes to frag:
771 1 extra opcode byte, 4 displacement bytes. */
772 {0, 0, 5, 0},
773 /* word conditionals add 4 bytes to frag:
774 1 displacement byte and a 3 byte long branch insn. */
775 {0, 0, 4, 0}
252b5132
RH		 776};
777
9103f4f4
L		 778static const arch_entry cpu_arch[] =
779{
89507696
JB		 780 /* Do not replace the first two entries - i386_target_format()
781 relies on them being there in this order. */
8a2c8fef 782 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 783 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 785 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 787 CPU_NONE_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 789 CPU_I186_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 791 CPU_I286_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 793 CPU_I386_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 795 CPU_I486_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 797 CPU_I586_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 799 CPU_I686_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 801 CPU_I586_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 803 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 805 CPU_P2_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 807 CPU_P3_FLAGS, 0 },
8a2c8fef 808 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 809 CPU_P4_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 811 CPU_CORE_FLAGS, 0 },
8a2c8fef 812 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 813 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 815 CPU_CORE_FLAGS, 1 },
8a2c8fef 816 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 817 CPU_CORE_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 819 CPU_CORE2_FLAGS, 1 },
8a2c8fef 820 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 821 CPU_CORE2_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 823 CPU_COREI7_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 825 CPU_L1OM_FLAGS, 0 },
7a9068fe 826 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 827 CPU_K1OM_FLAGS, 0 },
81486035 828 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 829 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 830 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 831 CPU_K6_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 833 CPU_K6_2_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 835 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 837 CPU_K8_FLAGS, 1 },
8a2c8fef 838 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 839 CPU_K8_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 841 CPU_K8_FLAGS, 0 },
8a2c8fef 842 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 843 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 844 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 845 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 846 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 847 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 848 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 849 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 850 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 851 CPU_BDVER4_FLAGS, 0 },
029f3522 852 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 853 CPU_ZNVER1_FLAGS, 0 },
7b458c12 854 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 855 CPU_BTVER1_FLAGS, 0 },
7b458c12 856 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 857 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_8087_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_287_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_387_FLAGS, 0 },
1848e567
L		 864 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
865 CPU_687_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_MMX_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_SSE_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_SSE2_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_SSE3_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 880 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_AVX_FLAGS, 0 },
6c30d220 884 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_AVX2_FLAGS, 0 },
43234a1e 886 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_AVX512F_FLAGS, 0 },
43234a1e 888 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_AVX512CD_FLAGS, 0 },
43234a1e 890 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_AVX512ER_FLAGS, 0 },
43234a1e 892 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 894 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 896 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 898 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_VMX_FLAGS, 0 },
8729a6f6 902 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 904 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_SMX_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 908 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 910 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 912 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_AES_FLAGS, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 920 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 922 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 924 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_F16C_FLAGS, 0 },
6c30d220 926 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_BMI2_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_FMA_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_FMA4_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_XOP_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_LWP_FLAGS, 0 },
8a2c8fef 936 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_MOVBE_FLAGS, 0 },
60aa667e 938 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_CX16_FLAGS, 0 },
8a2c8fef 940 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_EPT_FLAGS, 0 },
6c30d220 942 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_LZCNT_FLAGS, 0 },
42164a71 944 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_HLE_FLAGS, 0 },
42164a71 946 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_RTM_FLAGS, 0 },
6c30d220 948 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 950 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_CLFLUSH_FLAGS, 0 },
22109423 952 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_NOP_FLAGS, 0 },
8a2c8fef 954 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 956 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 958 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 960 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 962 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 964 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_SVME_FLAGS, 1 },
8a2c8fef 966 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_SVME_FLAGS, 0 },
8a2c8fef 968 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 970 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_ABM_FLAGS, 0 },
87973e9f 972 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_BMI_FLAGS, 0 },
2a2a0f38 974 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_TBM_FLAGS, 0 },
e2e1fcde 976 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_ADX_FLAGS, 0 },
e2e1fcde 978 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 979 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 980 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 981 CPU_PRFCHW_FLAGS, 0 },
5c111e37 982 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_SMAP_FLAGS, 0 },
7e8b059b 984 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_MPX_FLAGS, 0 },
a0046408 986 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_SHA_FLAGS, 0 },
963f3586 988 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 990 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 992 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_SE1_FLAGS, 0 },
c5e7287a 994 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 995 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 996 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 997 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 998 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 999 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 1000 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 1002 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 1004 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 1006 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1007 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1008 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1009 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1010 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1011 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1012 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1013 CPU_CLZERO_FLAGS, 0 },
9916071f 1014 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1015 CPU_MWAITX_FLAGS, 0 },
8eab4136 1016 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1017 CPU_OSPKE_FLAGS, 0 },
8bc52696 1018 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1019 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1020 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1021 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1022 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1023 CPU_IBT_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1025 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1026 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1027 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1028 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1029 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1030 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1031 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1032 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1033 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1034 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1035 CPU_PCONFIG_FLAGS, 0 },
293f5f65
L		 1036};
1037
1038static const noarch_entry cpu_noarch[] =
1039{
1040 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1041 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1042 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1043 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1044 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1045 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1046 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1048 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1049 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1050 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1052 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1053 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1054 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1063 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1064 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1065 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1066 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1067 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1068 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1069 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1070 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
e413e4e9
AM		 1071};
1072
704209c0 1073#ifdef I386COFF
a6c24e68
NC		 1074/* Like s_lcomm_internal in gas/read.c but the alignment string
1075 is allowed to be optional. */
1076
1077static symbolS *
1078pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1079{
1080 addressT align = 0;
1081
1082 SKIP_WHITESPACE ();
1083
7ab9ffdd 1084 if (needs_align
a6c24e68
NC		 1085 && *input_line_pointer == ',')
1086 {
1087 align = parse_align (needs_align - 1);
7ab9ffdd 1088
a6c24e68
NC		 1089 if (align == (addressT) -1)
1090 return NULL;
1091 }
1092 else
1093 {
1094 if (size >= 8)
1095 align = 3;
1096 else if (size >= 4)
1097 align = 2;
1098 else if (size >= 2)
1099 align = 1;
1100 else
1101 align = 0;
1102 }
1103
1104 bss_alloc (symbolP, size, align);
1105 return symbolP;
1106}
1107
704209c0 1108static void
a6c24e68
NC		 1109pe_lcomm (int needs_align)
1110{
1111 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1112}
704209c0 1113#endif
a6c24e68 1114
29b0f896
AM		 1115const pseudo_typeS md_pseudo_table[] =
1116{
1117#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1118 {"align", s_align_bytes, 0},
1119#else
1120 {"align", s_align_ptwo, 0},
1121#endif
1122 {"arch", set_cpu_arch, 0},
1123#ifndef I386COFF
1124 {"bss", s_bss, 0},
a6c24e68
NC		 1125#else
1126 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1127#endif
1128 {"ffloat", float_cons, 'f'},
1129 {"dfloat", float_cons, 'd'},
1130 {"tfloat", float_cons, 'x'},
1131 {"value", cons, 2},
d182319b 1132 {"slong", signed_cons, 4},
29b0f896
AM		 1133 {"noopt", s_ignore, 0},
1134 {"optim", s_ignore, 0},
1135 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1136 {"code16", set_code_flag, CODE_16BIT},
1137 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1138#ifdef BFD64
29b0f896 1139 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1140#endif
29b0f896
AM		 1141 {"intel_syntax", set_intel_syntax, 1},
1142 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1143 {"intel_mnemonic", set_intel_mnemonic, 1},
1144 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1145 {"allow_index_reg", set_allow_index_reg, 1},
1146 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1147 {"sse_check", set_check, 0},
1148 {"operand_check", set_check, 1},
3b22753a
L		 1149#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1150 {"largecomm", handle_large_common, 0},
07a53e5c 1151#else
68d20676 1152 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1153 {"loc", dwarf2_directive_loc, 0},
1154 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1155#endif
6482c264
NC		 1156#ifdef TE_PE
1157 {"secrel32", pe_directive_secrel, 0},
1158#endif
29b0f896
AM		 1159 {0, 0, 0}
1160};
1161
1162/* For interface with expression (). */
1163extern char *input_line_pointer;
1164
1165/* Hash table for instruction mnemonic lookup. */
1166static struct hash_control *op_hash;
1167
1168/* Hash table for register lookup. */
1169static struct hash_control *reg_hash;
1170\f
ce8a8b2f
AM		 1171 /* Various efficient no-op patterns for aligning code labels.
1172 Note: Don't try to assemble the instructions in the comments.
1173 0L and 0w are not legal. */
62a02d25
L		 1174static const unsigned char f32_1[] =
1175 {0x90}; /* nop */
1176static const unsigned char f32_2[] =
1177 {0x66,0x90}; /* xchg %ax,%ax */
1178static const unsigned char f32_3[] =
1179 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1180static const unsigned char f32_4[] =
1181 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1182static const unsigned char f32_6[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1184static const unsigned char f32_7[] =
1185 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1186static const unsigned char f16_3[] =
3ae729d5 1187 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1188static const unsigned char f16_4[] =
3ae729d5
L		 1189 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1190static const unsigned char jump_disp8[] =
1191 {0xeb}; /* jmp disp8 */
1192static const unsigned char jump32_disp32[] =
1193 {0xe9}; /* jmp disp32 */
1194static const unsigned char jump16_disp32[] =
1195 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1196/* 32-bit NOPs patterns. */
1197static const unsigned char *const f32_patt[] = {
3ae729d5 1198 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1199};
1200/* 16-bit NOPs patterns. */
1201static const unsigned char *const f16_patt[] = {
3ae729d5 1202 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1203};
1204/* nopl (%[re]ax) */
1205static const unsigned char alt_3[] =
1206 {0x0f,0x1f,0x00};
1207/* nopl 0(%[re]ax) */
1208static const unsigned char alt_4[] =
1209 {0x0f,0x1f,0x40,0x00};
1210/* nopl 0(%[re]ax,%[re]ax,1) */
1211static const unsigned char alt_5[] =
1212 {0x0f,0x1f,0x44,0x00,0x00};
1213/* nopw 0(%[re]ax,%[re]ax,1) */
1214static const unsigned char alt_6[] =
1215 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1216/* nopl 0L(%[re]ax) */
1217static const unsigned char alt_7[] =
1218 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1219/* nopl 0L(%[re]ax,%[re]ax,1) */
1220static const unsigned char alt_8[] =
1221 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1222/* nopw 0L(%[re]ax,%[re]ax,1) */
1223static const unsigned char alt_9[] =
1224 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1226static const unsigned char alt_10[] =
1227 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1228/* data16 nopw %cs:0L(%eax,%eax,1) */
1229static const unsigned char alt_11[] =
1230 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1231/* 32-bit and 64-bit NOPs patterns. */
1232static const unsigned char *const alt_patt[] = {
1233 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1234 alt_9, alt_10, alt_11
62a02d25
L		 1235};
1236
1237/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1238 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1239
1240static void
1241i386_output_nops (char *where, const unsigned char *const *patt,
1242 int count, int max_single_nop_size)
1243
1244{
3ae729d5
L		 1245 /* Place the longer NOP first. */
1246 int last;
1247 int offset;
1248 const unsigned char *nops = patt[max_single_nop_size - 1];
1249
1250 /* Use the smaller one if the requsted one isn't available. */
1251 if (nops == NULL)
62a02d25 1252 {
3ae729d5
L		 1253 max_single_nop_size--;
1254 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1255 }
1256
3ae729d5
L		 1257 last = count % max_single_nop_size;
1258
1259 count -= last;
1260 for (offset = 0; offset < count; offset += max_single_nop_size)
1261 memcpy (where + offset, nops, max_single_nop_size);
1262
1263 if (last)
1264 {
1265 nops = patt[last - 1];
1266 if (nops == NULL)
1267 {
1268 /* Use the smaller one plus one-byte NOP if the needed one
1269 isn't available. */
1270 last--;
1271 nops = patt[last - 1];
1272 memcpy (where + offset, nops, last);
1273 where[offset + last] = *patt[0];
1274 }
1275 else
1276 memcpy (where + offset, nops, last);
1277 }
62a02d25
L		 1278}
1279
3ae729d5
L		 1280static INLINE int
1281fits_in_imm7 (offsetT num)
1282{
1283 return (num & 0x7f) == num;
1284}
1285
1286static INLINE int
1287fits_in_imm31 (offsetT num)
1288{
1289 return (num & 0x7fffffff) == num;
1290}
62a02d25
L		 1291
1292/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1293 single NOP instruction LIMIT. */
1294
1295void
3ae729d5 1296i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1297{
3ae729d5 1298 const unsigned char *const *patt = NULL;
62a02d25 1299 int max_single_nop_size;
3ae729d5
L		 1300 /* Maximum number of NOPs before switching to jump over NOPs. */
1301 int max_number_of_nops;
62a02d25 1302
3ae729d5 1303 switch (fragP->fr_type)
62a02d25 1304 {
3ae729d5
L		 1305 case rs_fill_nop:
1306 case rs_align_code:
1307 break;
1308 default:
62a02d25
L		 1309 return;
1310 }
1311
ccc9c027
L		 1312 /* We need to decide which NOP sequence to use for 32bit and
1313 64bit. When -mtune= is used:
4eed87de 1314
76bc74dc
L		 1315 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1316 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1317 2. For the rest, alt_patt will be used.
1318
1319 When -mtune= isn't used, alt_patt will be used if
22109423 1320 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1321 be used.
ccc9c027
L		 1322
1323 When -march= or .arch is used, we can't use anything beyond
1324 cpu_arch_isa_flags. */
1325
1326 if (flag_code == CODE_16BIT)
1327 {
3ae729d5
L		 1328 patt = f16_patt;
1329 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1330 /* Limit number of NOPs to 2 in 16-bit mode. */
1331 max_number_of_nops = 2;
252b5132 1332 }
33fef721 1333 else
ccc9c027 1334 {
fbf3f584 1335 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1336 {
1337 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1338 switch (cpu_arch_tune)
1339 {
1340 case PROCESSOR_UNKNOWN:
1341 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1342 optimize with nops. */
1343 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1344 patt = alt_patt;
ccc9c027
L		 1345 else
1346 patt = f32_patt;
1347 break;
ccc9c027
L		 1348 case PROCESSOR_PENTIUM4:
1349 case PROCESSOR_NOCONA:
ef05d495 1350 case PROCESSOR_CORE:
76bc74dc 1351 case PROCESSOR_CORE2:
bd5295b2 1352 case PROCESSOR_COREI7:
3632d14b 1353 case PROCESSOR_L1OM:
7a9068fe 1354 case PROCESSOR_K1OM:
76bc74dc 1355 case PROCESSOR_GENERIC64:
ccc9c027
L		 1356 case PROCESSOR_K6:
1357 case PROCESSOR_ATHLON:
1358 case PROCESSOR_K8:
4eed87de 1359 case PROCESSOR_AMDFAM10:
8aedb9fe 1360 case PROCESSOR_BD:
029f3522 1361 case PROCESSOR_ZNVER:
7b458c12 1362 case PROCESSOR_BT:
80b8656c 1363 patt = alt_patt;
ccc9c027 1364 break;
76bc74dc 1365 case PROCESSOR_I386:
ccc9c027
L		 1366 case PROCESSOR_I486:
1367 case PROCESSOR_PENTIUM:
2dde1948 1368 case PROCESSOR_PENTIUMPRO:
81486035 1369 case PROCESSOR_IAMCU:
ccc9c027
L		 1370 case PROCESSOR_GENERIC32:
1371 patt = f32_patt;
1372 break;
4eed87de 1373 }
ccc9c027
L		 1374 }
1375 else
1376 {
fbf3f584 1377 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1378 {
1379 case PROCESSOR_UNKNOWN:
e6a14101 1380 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1381 PROCESSOR_UNKNOWN. */
1382 abort ();
1383 break;
1384
76bc74dc 1385 case PROCESSOR_I386:
ccc9c027
L		 1386 case PROCESSOR_I486:
1387 case PROCESSOR_PENTIUM:
81486035 1388 case PROCESSOR_IAMCU:
ccc9c027
L		 1389 case PROCESSOR_K6:
1390 case PROCESSOR_ATHLON:
1391 case PROCESSOR_K8:
4eed87de 1392 case PROCESSOR_AMDFAM10:
8aedb9fe 1393 case PROCESSOR_BD:
029f3522 1394 case PROCESSOR_ZNVER:
7b458c12 1395 case PROCESSOR_BT:
ccc9c027
L		 1396 case PROCESSOR_GENERIC32:
1397 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1398 with nops. */
1399 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1400 patt = alt_patt;
ccc9c027
L		 1401 else
1402 patt = f32_patt;
1403 break;
76bc74dc
L		 1404 case PROCESSOR_PENTIUMPRO:
1405 case PROCESSOR_PENTIUM4:
1406 case PROCESSOR_NOCONA:
1407 case PROCESSOR_CORE:
ef05d495 1408 case PROCESSOR_CORE2:
bd5295b2 1409 case PROCESSOR_COREI7:
3632d14b 1410 case PROCESSOR_L1OM:
7a9068fe 1411 case PROCESSOR_K1OM:
22109423 1412 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1413 patt = alt_patt;
ccc9c027
L		 1414 else
1415 patt = f32_patt;
1416 break;
1417 case PROCESSOR_GENERIC64:
80b8656c 1418 patt = alt_patt;
ccc9c027 1419 break;
4eed87de 1420 }
ccc9c027
L		 1421 }
1422
76bc74dc
L		 1423 if (patt == f32_patt)
1424 {
3ae729d5
L		 1425 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1426 /* Limit number of NOPs to 2 for older processors. */
1427 max_number_of_nops = 2;
76bc74dc
L		 1428 }
1429 else
1430 {
3ae729d5
L		 1431 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1432 /* Limit number of NOPs to 7 for newer processors. */
1433 max_number_of_nops = 7;
1434 }
1435 }
1436
1437 if (limit == 0)
1438 limit = max_single_nop_size;
1439
1440 if (fragP->fr_type == rs_fill_nop)
1441 {
1442 /* Output NOPs for .nop directive. */
1443 if (limit > max_single_nop_size)
1444 {
1445 as_bad_where (fragP->fr_file, fragP->fr_line,
1446 _("invalid single nop size: %d "
1447 "(expect within [0, %d])"),
1448 limit, max_single_nop_size);
1449 return;
1450 }
1451 }
1452 else
1453 fragP->fr_var = count;
1454
1455 if ((count / max_single_nop_size) > max_number_of_nops)
1456 {
1457 /* Generate jump over NOPs. */
1458 offsetT disp = count - 2;
1459 if (fits_in_imm7 (disp))
1460 {
1461 /* Use "jmp disp8" if possible. */
1462 count = disp;
1463 where[0] = jump_disp8[0];
1464 where[1] = count;
1465 where += 2;
1466 }
1467 else
1468 {
1469 unsigned int size_of_jump;
1470
1471 if (flag_code == CODE_16BIT)
1472 {
1473 where[0] = jump16_disp32[0];
1474 where[1] = jump16_disp32[1];
1475 size_of_jump = 2;
1476 }
1477 else
1478 {
1479 where[0] = jump32_disp32[0];
1480 size_of_jump = 1;
1481 }
1482
1483 count -= size_of_jump + 4;
1484 if (!fits_in_imm31 (count))
1485 {
1486 as_bad_where (fragP->fr_file, fragP->fr_line,
1487 _("jump over nop padding out of range"));
1488 return;
1489 }
1490
1491 md_number_to_chars (where + size_of_jump, count, 4);
1492 where += size_of_jump + 4;
76bc74dc 1493 }
ccc9c027 1494 }
3ae729d5
L		 1495
1496 /* Generate multiple NOPs. */
1497 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1498}
1499
c6fb90c8 1500static INLINE int
0dfbf9d7 1501operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1502{
0dfbf9d7 1503 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1504 {
1505 case 3:
0dfbf9d7 1506 if (x->array[2])
c6fb90c8 1507 return 0;
1a0670f3 1508 /* Fall through. */
c6fb90c8 1509 case 2:
0dfbf9d7 1510 if (x->array[1])
c6fb90c8 1511 return 0;
1a0670f3 1512 /* Fall through. */
c6fb90c8 1513 case 1:
0dfbf9d7 1514 return !x->array[0];
c6fb90c8
L		 1515 default:
1516 abort ();
1517 }
40fb9820
L		 1518}
1519
c6fb90c8 1520static INLINE void
0dfbf9d7 1521operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1522{
0dfbf9d7 1523 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1524 {
1525 case 3:
0dfbf9d7 1526 x->array[2] = v;
1a0670f3 1527 /* Fall through. */
c6fb90c8 1528 case 2:
0dfbf9d7 1529 x->array[1] = v;
1a0670f3 1530 /* Fall through. */
c6fb90c8 1531 case 1:
0dfbf9d7 1532 x->array[0] = v;
1a0670f3 1533 /* Fall through. */
c6fb90c8
L		 1534 break;
1535 default:
1536 abort ();
1537 }
1538}
40fb9820 1539
c6fb90c8 1540static INLINE int
0dfbf9d7
L		 1541operand_type_equal (const union i386_operand_type *x,
1542 const union i386_operand_type *y)
c6fb90c8 1543{
0dfbf9d7 1544 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1545 {
1546 case 3:
0dfbf9d7 1547 if (x->array[2] != y->array[2])
c6fb90c8 1548 return 0;
1a0670f3 1549 /* Fall through. */
c6fb90c8 1550 case 2:
0dfbf9d7 1551 if (x->array[1] != y->array[1])
c6fb90c8 1552 return 0;
1a0670f3 1553 /* Fall through. */
c6fb90c8 1554 case 1:
0dfbf9d7 1555 return x->array[0] == y->array[0];
c6fb90c8
L		 1556 break;
1557 default:
1558 abort ();
1559 }
1560}
40fb9820 1561
0dfbf9d7
L		 1562static INLINE int
1563cpu_flags_all_zero (const union i386_cpu_flags *x)
1564{
1565 switch (ARRAY_SIZE(x->array))
1566 {
53467f57
IT		 1567 case 4:
1568 if (x->array[3])
1569 return 0;
1570 /* Fall through. */
0dfbf9d7
L		 1571 case 3:
1572 if (x->array[2])
1573 return 0;
1a0670f3 1574 /* Fall through. */
0dfbf9d7
L		 1575 case 2:
1576 if (x->array[1])
1577 return 0;
1a0670f3 1578 /* Fall through. */
0dfbf9d7
L		 1579 case 1:
1580 return !x->array[0];
1581 default:
1582 abort ();
1583 }
1584}
1585
0dfbf9d7
L		 1586static INLINE int
1587cpu_flags_equal (const union i386_cpu_flags *x,
1588 const union i386_cpu_flags *y)
1589{
1590 switch (ARRAY_SIZE(x->array))
1591 {
53467f57
IT		 1592 case 4:
1593 if (x->array[3] != y->array[3])
1594 return 0;
1595 /* Fall through. */
0dfbf9d7
L		 1596 case 3:
1597 if (x->array[2] != y->array[2])
1598 return 0;
1a0670f3 1599 /* Fall through. */
0dfbf9d7
L		 1600 case 2:
1601 if (x->array[1] != y->array[1])
1602 return 0;
1a0670f3 1603 /* Fall through. */
0dfbf9d7
L		 1604 case 1:
1605 return x->array[0] == y->array[0];
1606 break;
1607 default:
1608 abort ();
1609 }
1610}
c6fb90c8
L		 1611
1612static INLINE int
1613cpu_flags_check_cpu64 (i386_cpu_flags f)
1614{
1615 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1616 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1617}
1618
c6fb90c8
L		 1619static INLINE i386_cpu_flags
1620cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1621{
c6fb90c8
L		 1622 switch (ARRAY_SIZE (x.array))
1623 {
53467f57
IT		 1624 case 4:
1625 x.array [3] &= y.array [3];
1626 /* Fall through. */
c6fb90c8
L		 1627 case 3:
1628 x.array [2] &= y.array [2];
1a0670f3 1629 /* Fall through. */
c6fb90c8
L		 1630 case 2:
1631 x.array [1] &= y.array [1];
1a0670f3 1632 /* Fall through. */
c6fb90c8
L		 1633 case 1:
1634 x.array [0] &= y.array [0];
1635 break;
1636 default:
1637 abort ();
1638 }
1639 return x;
1640}
40fb9820 1641
c6fb90c8
L		 1642static INLINE i386_cpu_flags
1643cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1644{
c6fb90c8 1645 switch (ARRAY_SIZE (x.array))
40fb9820 1646 {
53467f57
IT		 1647 case 4:
1648 x.array [3] |= y.array [3];
1649 /* Fall through. */
c6fb90c8
L		 1650 case 3:
1651 x.array [2] |= y.array [2];
1a0670f3 1652 /* Fall through. */
c6fb90c8
L		 1653 case 2:
1654 x.array [1] |= y.array [1];
1a0670f3 1655 /* Fall through. */
c6fb90c8
L		 1656 case 1:
1657 x.array [0] |= y.array [0];
40fb9820
L		 1658 break;
1659 default:
1660 abort ();
1661 }
40fb9820
L		 1662 return x;
1663}
1664
309d3373
JB		 1665static INLINE i386_cpu_flags
1666cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1667{
1668 switch (ARRAY_SIZE (x.array))
1669 {
53467f57
IT		 1670 case 4:
1671 x.array [3] &= ~y.array [3];
1672 /* Fall through. */
309d3373
JB		 1673 case 3:
1674 x.array [2] &= ~y.array [2];
1a0670f3 1675 /* Fall through. */
309d3373
JB		 1676 case 2:
1677 x.array [1] &= ~y.array [1];
1a0670f3 1678 /* Fall through. */
309d3373
JB		 1679 case 1:
1680 x.array [0] &= ~y.array [0];
1681 break;
1682 default:
1683 abort ();
1684 }
1685 return x;
1686}
1687
c0f3af97
L		 1688#define CPU_FLAGS_ARCH_MATCH 0x1
1689#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1690#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1691#define CPU_FLAGS_PCLMUL_MATCH 0x8
1692#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1693
a5ff0eb2 1694#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1695 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1696 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1697#define CPU_FLAGS_PERFECT_MATCH \
1698 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1699
1700/* Return CPU flags match bits. */
3629bb00 1701
40fb9820 1702static int
d3ce72d0 1703cpu_flags_match (const insn_template *t)
40fb9820 1704{
c0f3af97
L		 1705 i386_cpu_flags x = t->cpu_flags;
1706 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1707
1708 x.bitfield.cpu64 = 0;
1709 x.bitfield.cpuno64 = 0;
1710
0dfbf9d7 1711 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1712 {
1713 /* This instruction is available on all archs. */
1714 match |= CPU_FLAGS_32BIT_MATCH;
1715 }
3629bb00
L		 1716 else
1717 {
c0f3af97 1718 /* This instruction is available only on some archs. */
3629bb00
L		 1719 i386_cpu_flags cpu = cpu_arch_flags;
1720
3629bb00 1721 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1722 if (!cpu_flags_all_zero (&cpu))
1723 {
a5ff0eb2
L		 1724 if (x.bitfield.cpuavx)
1725 {
ce2f5b3c 1726 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1727 if (cpu.bitfield.cpuavx)
1728 {
1729 /* Check SSE2AVX. */
1730 if (!t->opcode_modifier.sse2avx|| sse2avx)
1731 {
1732 match |= (CPU_FLAGS_ARCH_MATCH
1733 | CPU_FLAGS_AVX_MATCH);
1734 /* Check AES. */
1735 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1736 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1737 /* Check PCLMUL. */
1738 if (!x.bitfield.cpupclmul
1739 || cpu.bitfield.cpupclmul)
1740 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1741 }
1742 }
1743 else
1744 match |= CPU_FLAGS_ARCH_MATCH;
1745 }
73b090a9
L		 1746 else if (x.bitfield.cpuavx512vl)
1747 {
1748 /* Match AVX512VL. */
1749 if (cpu.bitfield.cpuavx512vl)
1750 {
1751 /* Need another match. */
1752 cpu.bitfield.cpuavx512vl = 0;
1753 if (!cpu_flags_all_zero (&cpu))
1754 match |= CPU_FLAGS_32BIT_MATCH;
1755 else
1756 match |= CPU_FLAGS_ARCH_MATCH;
1757 }
1758 else
1759 match |= CPU_FLAGS_ARCH_MATCH;
1760 }
a5ff0eb2 1761 else
c0f3af97
L		 1762 match |= CPU_FLAGS_32BIT_MATCH;
1763 }
3629bb00 1764 }
c0f3af97 1765 return match;
40fb9820
L		 1766}
1767
c6fb90c8
L		 1768static INLINE i386_operand_type
1769operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1770{
c6fb90c8
L		 1771 switch (ARRAY_SIZE (x.array))
1772 {
1773 case 3:
1774 x.array [2] &= y.array [2];
1a0670f3 1775 /* Fall through. */
c6fb90c8
L		 1776 case 2:
1777 x.array [1] &= y.array [1];
1a0670f3 1778 /* Fall through. */
c6fb90c8
L		 1779 case 1:
1780 x.array [0] &= y.array [0];
1781 break;
1782 default:
1783 abort ();
1784 }
1785 return x;
40fb9820
L		 1786}
1787
73053c1f
JB		 1788static INLINE i386_operand_type
1789operand_type_and_not (i386_operand_type x, i386_operand_type y)
1790{
1791 switch (ARRAY_SIZE (x.array))
1792 {
1793 case 3:
1794 x.array [2] &= ~y.array [2];
1795 /* Fall through. */
1796 case 2:
1797 x.array [1] &= ~y.array [1];
1798 /* Fall through. */
1799 case 1:
1800 x.array [0] &= ~y.array [0];
1801 break;
1802 default:
1803 abort ();
1804 }
1805 return x;
1806}
1807
c6fb90c8
L		 1808static INLINE i386_operand_type
1809operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1810{
c6fb90c8 1811 switch (ARRAY_SIZE (x.array))
40fb9820 1812 {
c6fb90c8
L		 1813 case 3:
1814 x.array [2] |= y.array [2];
1a0670f3 1815 /* Fall through. */
c6fb90c8
L		 1816 case 2:
1817 x.array [1] |= y.array [1];
1a0670f3 1818 /* Fall through. */
c6fb90c8
L		 1819 case 1:
1820 x.array [0] |= y.array [0];
40fb9820
L		 1821 break;
1822 default:
1823 abort ();
1824 }
c6fb90c8
L		 1825 return x;
1826}
40fb9820 1827
c6fb90c8
L		 1828static INLINE i386_operand_type
1829operand_type_xor (i386_operand_type x, i386_operand_type y)
1830{
1831 switch (ARRAY_SIZE (x.array))
1832 {
1833 case 3:
1834 x.array [2] ^= y.array [2];
1a0670f3 1835 /* Fall through. */
c6fb90c8
L		 1836 case 2:
1837 x.array [1] ^= y.array [1];
1a0670f3 1838 /* Fall through. */
c6fb90c8
L		 1839 case 1:
1840 x.array [0] ^= y.array [0];
1841 break;
1842 default:
1843 abort ();
1844 }
40fb9820
L		 1845 return x;
1846}
1847
1848static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1849static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1850static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1851static const i386_operand_type inoutportreg
1852 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1853static const i386_operand_type reg16_inoutportreg
1854 = OPERAND_TYPE_REG16_INOUTPORTREG;
1855static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1856static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1857static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1858static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1859static const i386_operand_type anydisp
1860 = OPERAND_TYPE_ANYDISP;
40fb9820 1861static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1862static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1863static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1864static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1865static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1866static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1867static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1868static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1869static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1870static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1871static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1872static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1873
1874enum operand_type
1875{
1876 reg,
40fb9820
L		 1877 imm,
1878 disp,
1879 anymem
1880};
1881
c6fb90c8 1882static INLINE int
40fb9820
L		 1883operand_type_check (i386_operand_type t, enum operand_type c)
1884{
1885 switch (c)
1886 {
1887 case reg:
dc821c5f 1888 return t.bitfield.reg;
40fb9820 1889
40fb9820
L		 1890 case imm:
1891 return (t.bitfield.imm8
1892 || t.bitfield.imm8s
1893 || t.bitfield.imm16
1894 || t.bitfield.imm32
1895 || t.bitfield.imm32s
1896 || t.bitfield.imm64);
1897
1898 case disp:
1899 return (t.bitfield.disp8
1900 || t.bitfield.disp16
1901 || t.bitfield.disp32
1902 || t.bitfield.disp32s
1903 || t.bitfield.disp64);
1904
1905 case anymem:
1906 return (t.bitfield.disp8
1907 || t.bitfield.disp16
1908 || t.bitfield.disp32
1909 || t.bitfield.disp32s
1910 || t.bitfield.disp64
1911 || t.bitfield.baseindex);
1912
1913 default:
1914 abort ();
1915 }
2cfe26b6
AM		 1916
1917 return 0;
40fb9820
L		 1918}
1919
ca0d63fe 1920/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1921 operand J for instruction template T. */
1922
1923static INLINE int
d3ce72d0 1924match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1925{
1926 return !((i.types[j].bitfield.byte
1927 && !t->operand_types[j].bitfield.byte)
1928 || (i.types[j].bitfield.word
1929 && !t->operand_types[j].bitfield.word)
1930 || (i.types[j].bitfield.dword
1931 && !t->operand_types[j].bitfield.dword)
1932 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1933 && !t->operand_types[j].bitfield.qword)
1934 || (i.types[j].bitfield.tbyte
1935 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1936}
1937
1b54b8d7
JB		 1938/* Return 1 if there is no conflict in SIMD register on
1939 operand J for instruction template T. */
1940
1941static INLINE int
1942match_simd_size (const insn_template *t, unsigned int j)
1943{
1944 return !((i.types[j].bitfield.xmmword
1945 && !t->operand_types[j].bitfield.xmmword)
1946 || (i.types[j].bitfield.ymmword
1947 && !t->operand_types[j].bitfield.ymmword)
1948 || (i.types[j].bitfield.zmmword
1949 && !t->operand_types[j].bitfield.zmmword));
1950}
1951
5c07affc
L		 1952/* Return 1 if there is no conflict in any size on operand J for
1953 instruction template T. */
1954
1955static INLINE int
d3ce72d0 1956match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1957{
1958 return (match_reg_size (t, j)
1959 && !((i.types[j].bitfield.unspecified
af508cb9 1960 && !i.broadcast
5c07affc
L		 1961 && !t->operand_types[j].bitfield.unspecified)
1962 || (i.types[j].bitfield.fword
1963 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1964 /* For scalar opcode templates to allow register and memory
1965 operands at the same time, some special casing is needed
1966 here. */
1967 || ((t->operand_types[j].bitfield.regsimd
1968 && !t->opcode_modifier.broadcast
1969 && (t->operand_types[j].bitfield.dword
1970 || t->operand_types[j].bitfield.qword))
1971 ? (i.types[j].bitfield.xmmword
1972 || i.types[j].bitfield.ymmword
1973 || i.types[j].bitfield.zmmword)
1974 : !match_simd_size(t, j))));
5c07affc
L		 1975}
1976
1977/* Return 1 if there is no size conflict on any operands for
1978 instruction template T. */
1979
1980static INLINE int
d3ce72d0 1981operand_size_match (const insn_template *t)
5c07affc
L		 1982{
1983 unsigned int j;
1984 int match = 1;
1985
1986 /* Don't check jump instructions. */
1987 if (t->opcode_modifier.jump
1988 || t->opcode_modifier.jumpbyte
1989 || t->opcode_modifier.jumpdword
1990 || t->opcode_modifier.jumpintersegment)
1991 return match;
1992
1993 /* Check memory and accumulator operand size. */
1994 for (j = 0; j < i.operands; j++)
1995 {
1b54b8d7
JB		 1996 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1997 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1998 continue;
1999
1b54b8d7 2000 if (t->operand_types[j].bitfield.reg
dc821c5f 2001 && !match_reg_size (t, j))
5c07affc
L		 2002 {
2003 match = 0;
2004 break;
2005 }
2006
1b54b8d7
JB		 2007 if (t->operand_types[j].bitfield.regsimd
2008 && !match_simd_size (t, j))
2009 {
2010 match = 0;
2011 break;
2012 }
2013
2014 if (t->operand_types[j].bitfield.acc
2015 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
2016 {
2017 match = 0;
2018 break;
2019 }
2020
5c07affc
L		 2021 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2022 {
2023 match = 0;
2024 break;
2025 }
2026 }
2027
891edac4 2028 if (match)
5c07affc 2029 return match;
38e314eb 2030 else if (!t->opcode_modifier.d)
891edac4
L		 2031 {
2032mismatch:
86e026a4 2033 i.error = operand_size_mismatch;
891edac4
L		 2034 return 0;
2035 }
5c07affc
L		 2036
2037 /* Check reverse. */
9c2799c2 2038 gas_assert (i.operands == 2);
5c07affc
L		 2039
2040 match = 1;
2041 for (j = 0; j < 2; j++)
2042 {
dc821c5f
JB		 2043 if ((t->operand_types[j].bitfield.reg
2044 || t->operand_types[j].bitfield.acc)
5c07affc 2045 && !match_reg_size (t, j ? 0 : 1))
891edac4 2046 goto mismatch;
5c07affc
L		 2047
2048 if (i.types[j].bitfield.mem
2049 && !match_mem_size (t, j ? 0 : 1))
891edac4 2050 goto mismatch;
5c07affc
L		 2051 }
2052
2053 return match;
2054}
2055
c6fb90c8 2056static INLINE int
40fb9820
L		 2057operand_type_match (i386_operand_type overlap,
2058 i386_operand_type given)
2059{
2060 i386_operand_type temp = overlap;
2061
2062 temp.bitfield.jumpabsolute = 0;
7d5e4556 2063 temp.bitfield.unspecified = 0;
5c07affc
L		 2064 temp.bitfield.byte = 0;
2065 temp.bitfield.word = 0;
2066 temp.bitfield.dword = 0;
2067 temp.bitfield.fword = 0;
2068 temp.bitfield.qword = 0;
2069 temp.bitfield.tbyte = 0;
2070 temp.bitfield.xmmword = 0;
c0f3af97 2071 temp.bitfield.ymmword = 0;
43234a1e 2072 temp.bitfield.zmmword = 0;
0dfbf9d7 2073 if (operand_type_all_zero (&temp))
891edac4 2074 goto mismatch;
40fb9820 2075
891edac4
L		 2076 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2077 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2078 return 1;
2079
2080mismatch:
a65babc9 2081 i.error = operand_type_mismatch;
891edac4 2082 return 0;
40fb9820
L		 2083}
2084
7d5e4556 2085/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2086 unless the expected operand type register overlap is null.
2087 Memory operand size of certain SIMD instructions is also being checked
2088 here. */
40fb9820 2089
c6fb90c8 2090static INLINE int
dc821c5f 2091operand_type_register_match (i386_operand_type g0,
40fb9820 2092 i386_operand_type t0,
40fb9820
L		 2093 i386_operand_type g1,
2094 i386_operand_type t1)
2095{
10c17abd
JB		 2096 if (!g0.bitfield.reg
2097 && !g0.bitfield.regsimd
2098 && (!operand_type_check (g0, anymem)
2099 || g0.bitfield.unspecified
2100 || !t0.bitfield.regsimd))
40fb9820
L		 2101 return 1;
2102
10c17abd
JB		 2103 if (!g1.bitfield.reg
2104 && !g1.bitfield.regsimd
2105 && (!operand_type_check (g1, anymem)
2106 || g1.bitfield.unspecified
2107 || !t1.bitfield.regsimd))
40fb9820
L		 2108 return 1;
2109
dc821c5f
JB		 2110 if (g0.bitfield.byte == g1.bitfield.byte
2111 && g0.bitfield.word == g1.bitfield.word
2112 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2113 && g0.bitfield.qword == g1.bitfield.qword
2114 && g0.bitfield.xmmword == g1.bitfield.xmmword
2115 && g0.bitfield.ymmword == g1.bitfield.ymmword
2116 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2117 return 1;
2118
dc821c5f
JB		 2119 if (!(t0.bitfield.byte & t1.bitfield.byte)
2120 && !(t0.bitfield.word & t1.bitfield.word)
2121 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2122 && !(t0.bitfield.qword & t1.bitfield.qword)
2123 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2124 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2125 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2126 return 1;
2127
a65babc9 2128 i.error = register_type_mismatch;
891edac4
L		 2129
2130 return 0;
40fb9820
L		 2131}
2132
4c692bc7
JB		 2133static INLINE unsigned int
2134register_number (const reg_entry *r)
2135{
2136 unsigned int nr = r->reg_num;
2137
2138 if (r->reg_flags & RegRex)
2139 nr += 8;
2140
200cbe0f
L		 2141 if (r->reg_flags & RegVRex)
2142 nr += 16;
2143
4c692bc7
JB		 2144 return nr;
2145}
2146
252b5132 2147static INLINE unsigned int
40fb9820 2148mode_from_disp_size (i386_operand_type t)
252b5132 2149{
b5014f7a 2150 if (t.bitfield.disp8)
40fb9820
L		 2151 return 1;
2152 else if (t.bitfield.disp16
2153 || t.bitfield.disp32
2154 || t.bitfield.disp32s)
2155 return 2;
2156 else
2157 return 0;
252b5132
RH		 2158}
2159
2160static INLINE int
65879393 2161fits_in_signed_byte (addressT num)
252b5132 2162{
65879393 2163 return num + 0x80 <= 0xff;
47926f60 2164}
252b5132
RH		 2165
2166static INLINE int
65879393 2167fits_in_unsigned_byte (addressT num)
252b5132 2168{
65879393 2169 return num <= 0xff;
47926f60 2170}
252b5132
RH		 2171
2172static INLINE int
65879393 2173fits_in_unsigned_word (addressT num)
252b5132 2174{
65879393 2175 return num <= 0xffff;
47926f60 2176}
252b5132
RH		 2177
2178static INLINE int
65879393 2179fits_in_signed_word (addressT num)
252b5132 2180{
65879393 2181 return num + 0x8000 <= 0xffff;
47926f60 2182}
2a962e6d 2183
3e73aa7c 2184static INLINE int
65879393 2185fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2186{
2187#ifndef BFD64
2188 return 1;
2189#else
65879393 2190 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2191#endif
2192} /* fits_in_signed_long() */
2a962e6d 2193
3e73aa7c 2194static INLINE int
65879393 2195fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2196{
2197#ifndef BFD64
2198 return 1;
2199#else
65879393 2200 return num <= 0xffffffff;
3e73aa7c
JH		 2201#endif
2202} /* fits_in_unsigned_long() */
252b5132 2203
43234a1e 2204static INLINE int
b5014f7a 2205fits_in_disp8 (offsetT num)
43234a1e
L		 2206{
2207 int shift = i.memshift;
2208 unsigned int mask;
2209
2210 if (shift == -1)
2211 abort ();
2212
2213 mask = (1 << shift) - 1;
2214
2215 /* Return 0 if NUM isn't properly aligned. */
2216 if ((num & mask))
2217 return 0;
2218
2219 /* Check if NUM will fit in 8bit after shift. */
2220 return fits_in_signed_byte (num >> shift);
2221}
2222
a683cc34
SP		 2223static INLINE int
2224fits_in_imm4 (offsetT num)
2225{
2226 return (num & 0xf) == num;
2227}
2228
40fb9820 2229static i386_operand_type
e3bb37b5 2230smallest_imm_type (offsetT num)
252b5132 2231{
40fb9820 2232 i386_operand_type t;
7ab9ffdd 2233
0dfbf9d7 2234 operand_type_set (&t, 0);
40fb9820
L		 2235 t.bitfield.imm64 = 1;
2236
2237 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2238 {
2239 /* This code is disabled on the 486 because all the Imm1 forms
2240 in the opcode table are slower on the i486. They're the
2241 versions with the implicitly specified single-position
2242 displacement, which has another syntax if you really want to
2243 use that form. */
40fb9820
L		 2244 t.bitfield.imm1 = 1;
2245 t.bitfield.imm8 = 1;
2246 t.bitfield.imm8s = 1;
2247 t.bitfield.imm16 = 1;
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2250 }
2251 else if (fits_in_signed_byte (num))
2252 {
2253 t.bitfield.imm8 = 1;
2254 t.bitfield.imm8s = 1;
2255 t.bitfield.imm16 = 1;
2256 t.bitfield.imm32 = 1;
2257 t.bitfield.imm32s = 1;
2258 }
2259 else if (fits_in_unsigned_byte (num))
2260 {
2261 t.bitfield.imm8 = 1;
2262 t.bitfield.imm16 = 1;
2263 t.bitfield.imm32 = 1;
2264 t.bitfield.imm32s = 1;
2265 }
2266 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2267 {
2268 t.bitfield.imm16 = 1;
2269 t.bitfield.imm32 = 1;
2270 t.bitfield.imm32s = 1;
2271 }
2272 else if (fits_in_signed_long (num))
2273 {
2274 t.bitfield.imm32 = 1;
2275 t.bitfield.imm32s = 1;
2276 }
2277 else if (fits_in_unsigned_long (num))
2278 t.bitfield.imm32 = 1;
2279
2280 return t;
47926f60 2281}
252b5132 2282
847f7ad4 2283static offsetT
e3bb37b5 2284offset_in_range (offsetT val, int size)
847f7ad4 2285{
508866be 2286 addressT mask;
ba2adb93 2287
847f7ad4
AM		 2288 switch (size)
2289 {
508866be
L		 2290 case 1: mask = ((addressT) 1 << 8) - 1; break;
2291 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2292 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2293#ifdef BFD64
2294 case 8: mask = ((addressT) 2 << 63) - 1; break;
2295#endif
47926f60 2296 default: abort ();
847f7ad4
AM		 2297 }
2298
9de868bf
L		 2299#ifdef BFD64
2300 /* If BFD64, sign extend val for 32bit address mode. */
2301 if (flag_code != CODE_64BIT
2302 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2303 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2304 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2305#endif
ba2adb93 2306
47926f60 2307 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2308 {
2309 char buf1[40], buf2[40];
2310
2311 sprint_value (buf1, val);
2312 sprint_value (buf2, val & mask);
2313 as_warn (_("%s shortened to %s"), buf1, buf2);
2314 }
2315 return val & mask;
2316}
2317
c32fa91d
L		 2318enum PREFIX_GROUP
2319{
2320 PREFIX_EXIST = 0,
2321 PREFIX_LOCK,
2322 PREFIX_REP,
04ef582a 2323 PREFIX_DS,
c32fa91d
L		 2324 PREFIX_OTHER
2325};
2326
2327/* Returns
2328 a. PREFIX_EXIST if attempting to add a prefix where one from the
2329 same class already exists.
2330 b. PREFIX_LOCK if lock prefix is added.
2331 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2332 d. PREFIX_DS if ds prefix is added.
2333 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2334 */
2335
2336static enum PREFIX_GROUP
e3bb37b5 2337add_prefix (unsigned int prefix)
252b5132 2338{
c32fa91d 2339 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2340 unsigned int q;
252b5132 2341
29b0f896
AM		 2342 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2343 && flag_code == CODE_64BIT)
b1905489 2344 {
161a04f6
L		 2345 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2346 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2347 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2348 ret = PREFIX_EXIST;
b1905489
JB		 2349 q = REX_PREFIX;
2350 }
3e73aa7c 2351 else
b1905489
JB		 2352 {
2353 switch (prefix)
2354 {
2355 default:
2356 abort ();
2357
b1905489 2358 case DS_PREFIX_OPCODE:
04ef582a
L		 2359 ret = PREFIX_DS;
2360 /* Fall through. */
2361 case CS_PREFIX_OPCODE:
b1905489
JB		 2362 case ES_PREFIX_OPCODE:
2363 case FS_PREFIX_OPCODE:
2364 case GS_PREFIX_OPCODE:
2365 case SS_PREFIX_OPCODE:
2366 q = SEG_PREFIX;
2367 break;
2368
2369 case REPNE_PREFIX_OPCODE:
2370 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2371 q = REP_PREFIX;
2372 ret = PREFIX_REP;
2373 break;
2374
b1905489 2375 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2376 q = LOCK_PREFIX;
2377 ret = PREFIX_LOCK;
b1905489
JB		 2378 break;
2379
2380 case FWAIT_OPCODE:
2381 q = WAIT_PREFIX;
2382 break;
2383
2384 case ADDR_PREFIX_OPCODE:
2385 q = ADDR_PREFIX;
2386 break;
2387
2388 case DATA_PREFIX_OPCODE:
2389 q = DATA_PREFIX;
2390 break;
2391 }
2392 if (i.prefix[q] != 0)
c32fa91d 2393 ret = PREFIX_EXIST;
b1905489 2394 }
252b5132 2395
b1905489 2396 if (ret)
252b5132 2397 {
b1905489
JB		 2398 if (!i.prefix[q])
2399 ++i.prefixes;
2400 i.prefix[q] |= prefix;
252b5132 2401 }
b1905489
JB		 2402 else
2403 as_bad (_("same type of prefix used twice"));
252b5132 2404
252b5132
RH		 2405 return ret;
2406}
2407
2408static void
78f12dd3 2409update_code_flag (int value, int check)
eecb386c 2410{
78f12dd3
L		 2411 PRINTF_LIKE ((*as_error));
2412
1e9cc1c2 2413 flag_code = (enum flag_code) value;
40fb9820
L		 2414 if (flag_code == CODE_64BIT)
2415 {
2416 cpu_arch_flags.bitfield.cpu64 = 1;
2417 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2418 }
2419 else
2420 {
2421 cpu_arch_flags.bitfield.cpu64 = 0;
2422 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2423 }
2424 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2425 {
78f12dd3
L		 2426 if (check)
2427 as_error = as_fatal;
2428 else
2429 as_error = as_bad;
2430 (*as_error) (_("64bit mode not supported on `%s'."),
2431 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2432 }
40fb9820 2433 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2434 {
78f12dd3
L		 2435 if (check)
2436 as_error = as_fatal;
2437 else
2438 as_error = as_bad;
2439 (*as_error) (_("32bit mode not supported on `%s'."),
2440 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2441 }
eecb386c
AM		 2442 stackop_size = '\0';
2443}
2444
78f12dd3
L		 2445static void
2446set_code_flag (int value)
2447{
2448 update_code_flag (value, 0);
2449}
2450
eecb386c 2451static void
e3bb37b5 2452set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2453{
1e9cc1c2 2454 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2455 if (flag_code != CODE_16BIT)
2456 abort ();
2457 cpu_arch_flags.bitfield.cpu64 = 0;
2458 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2459 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2460}
2461
2462static void
e3bb37b5 2463set_intel_syntax (int syntax_flag)
252b5132
RH		 2464{
2465 /* Find out if register prefixing is specified. */
2466 int ask_naked_reg = 0;
2467
2468 SKIP_WHITESPACE ();
29b0f896 2469 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2470 {
d02603dc
NC		 2471 char *string;
2472 int e = get_symbol_name (&string);
252b5132 2473
47926f60 2474 if (strcmp (string, "prefix") == 0)
252b5132 2475 ask_naked_reg = 1;
47926f60 2476 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2477 ask_naked_reg = -1;
2478 else
d0b47220 2479 as_bad (_("bad argument to syntax directive."));
d02603dc 2480 (void) restore_line_pointer (e);
252b5132
RH		 2481 }
2482 demand_empty_rest_of_line ();
c3332e24 2483
252b5132
RH		 2484 intel_syntax = syntax_flag;
2485
2486 if (ask_naked_reg == 0)
f86103b7
AM		 2487 allow_naked_reg = (intel_syntax
2488 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2489 else
2490 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2491
ee86248c 2492 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2493
e4a3b5a4 2494 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2495 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2496 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2497}
2498
1efbbeb4
L		 2499static void
2500set_intel_mnemonic (int mnemonic_flag)
2501{
e1d4d893 2502 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2503}
2504
db51cc60
L		 2505static void
2506set_allow_index_reg (int flag)
2507{
2508 allow_index_reg = flag;
2509}
2510
cb19c032 2511static void
7bab8ab5 2512set_check (int what)
cb19c032 2513{
7bab8ab5
JB		 2514 enum check_kind *kind;
2515 const char *str;
2516
2517 if (what)
2518 {
2519 kind = &operand_check;
2520 str = "operand";
2521 }
2522 else
2523 {
2524 kind = &sse_check;
2525 str = "sse";
2526 }
2527
cb19c032
L		 2528 SKIP_WHITESPACE ();
2529
2530 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2531 {
d02603dc
NC		 2532 char *string;
2533 int e = get_symbol_name (&string);
cb19c032
L		 2534
2535 if (strcmp (string, "none") == 0)
7bab8ab5 2536 *kind = check_none;
cb19c032 2537 else if (strcmp (string, "warning") == 0)
7bab8ab5 2538 *kind = check_warning;
cb19c032 2539 else if (strcmp (string, "error") == 0)
7bab8ab5 2540 *kind = check_error;
cb19c032 2541 else
7bab8ab5 2542 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2543 (void) restore_line_pointer (e);
cb19c032
L		 2544 }
2545 else
7bab8ab5 2546 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2547
2548 demand_empty_rest_of_line ();
2549}
2550
8a9036a4
L		 2551static void
2552check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2553 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2554{
2555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2556 static const char *arch;
2557
2558 /* Intel LIOM is only supported on ELF. */
2559 if (!IS_ELF)
2560 return;
2561
2562 if (!arch)
2563 {
2564 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2565 use default_arch. */
2566 arch = cpu_arch_name;
2567 if (!arch)
2568 arch = default_arch;
2569 }
2570
81486035
L		 2571 /* If we are targeting Intel MCU, we must enable it. */
2572 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2573 || new_flag.bitfield.cpuiamcu)
2574 return;
2575
3632d14b 2576 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2577 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2578 || new_flag.bitfield.cpul1om)
8a9036a4 2579 return;
76ba9986 2580
7a9068fe
L		 2581 /* If we are targeting Intel K1OM, we must enable it. */
2582 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2583 || new_flag.bitfield.cpuk1om)
2584 return;
2585
8a9036a4
L		 2586 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2587#endif
2588}
2589
e413e4e9 2590static void
e3bb37b5 2591set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2592{
47926f60 2593 SKIP_WHITESPACE ();
e413e4e9 2594
29b0f896 2595 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2596 {
d02603dc
NC		 2597 char *string;
2598 int e = get_symbol_name (&string);
91d6fa6a 2599 unsigned int j;
40fb9820 2600 i386_cpu_flags flags;
e413e4e9 2601
91d6fa6a 2602 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2603 {
91d6fa6a 2604 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2605 {
91d6fa6a 2606 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2607
5c6af06e
JB		 2608 if (*string != '.')
2609 {
91d6fa6a 2610 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2611 cpu_sub_arch_name = NULL;
91d6fa6a 2612 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2613 if (flag_code == CODE_64BIT)
2614 {
2615 cpu_arch_flags.bitfield.cpu64 = 1;
2616 cpu_arch_flags.bitfield.cpuno64 = 0;
2617 }
2618 else
2619 {
2620 cpu_arch_flags.bitfield.cpu64 = 0;
2621 cpu_arch_flags.bitfield.cpuno64 = 1;
2622 }
91d6fa6a
NC		 2623 cpu_arch_isa = cpu_arch[j].type;
2624 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2625 if (!cpu_arch_tune_set)
2626 {
2627 cpu_arch_tune = cpu_arch_isa;
2628 cpu_arch_tune_flags = cpu_arch_isa_flags;
2629 }
5c6af06e
JB		 2630 break;
2631 }
40fb9820 2632
293f5f65
L		 2633 flags = cpu_flags_or (cpu_arch_flags,
2634 cpu_arch[j].flags);
81486035 2635
5b64d091 2636 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2637 {
6305a203
L		 2638 if (cpu_sub_arch_name)
2639 {
2640 char *name = cpu_sub_arch_name;
2641 cpu_sub_arch_name = concat (name,
91d6fa6a 2642 cpu_arch[j].name,
1bf57e9f 2643 (const char *) NULL);
6305a203
L		 2644 free (name);
2645 }
2646 else
91d6fa6a 2647 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2648 cpu_arch_flags = flags;
a586129e 2649 cpu_arch_isa_flags = flags;
5c6af06e 2650 }
d02603dc 2651 (void) restore_line_pointer (e);
5c6af06e
JB		 2652 demand_empty_rest_of_line ();
2653 return;
e413e4e9
AM		 2654 }
2655 }
293f5f65
L		 2656
2657 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2658 {
33eaf5de 2659 /* Disable an ISA extension. */
293f5f65
L		 2660 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2661 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2662 {
2663 flags = cpu_flags_and_not (cpu_arch_flags,
2664 cpu_noarch[j].flags);
2665 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2666 {
2667 if (cpu_sub_arch_name)
2668 {
2669 char *name = cpu_sub_arch_name;
2670 cpu_sub_arch_name = concat (name, string,
2671 (const char *) NULL);
2672 free (name);
2673 }
2674 else
2675 cpu_sub_arch_name = xstrdup (string);
2676 cpu_arch_flags = flags;
2677 cpu_arch_isa_flags = flags;
2678 }
2679 (void) restore_line_pointer (e);
2680 demand_empty_rest_of_line ();
2681 return;
2682 }
2683
2684 j = ARRAY_SIZE (cpu_arch);
2685 }
2686
91d6fa6a 2687 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2688 as_bad (_("no such architecture: `%s'"), string);
2689
2690 *input_line_pointer = e;
2691 }
2692 else
2693 as_bad (_("missing cpu architecture"));
2694
fddf5b5b
AM		 2695 no_cond_jump_promotion = 0;
2696 if (*input_line_pointer == ','
29b0f896 2697 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2698 {
d02603dc
NC		 2699 char *string;
2700 char e;
2701
2702 ++input_line_pointer;
2703 e = get_symbol_name (&string);
fddf5b5b
AM		 2704
2705 if (strcmp (string, "nojumps") == 0)
2706 no_cond_jump_promotion = 1;
2707 else if (strcmp (string, "jumps") == 0)
2708 ;
2709 else
2710 as_bad (_("no such architecture modifier: `%s'"), string);
2711
d02603dc 2712 (void) restore_line_pointer (e);
fddf5b5b
AM		 2713 }
2714
e413e4e9
AM		 2715 demand_empty_rest_of_line ();
2716}
2717
8a9036a4
L		 2718enum bfd_architecture
2719i386_arch (void)
2720{
3632d14b 2721 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2722 {
2723 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2724 || flag_code != CODE_64BIT)
2725 as_fatal (_("Intel L1OM is 64bit ELF only"));
2726 return bfd_arch_l1om;
2727 }
7a9068fe
L		 2728 else if (cpu_arch_isa == PROCESSOR_K1OM)
2729 {
2730 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2731 || flag_code != CODE_64BIT)
2732 as_fatal (_("Intel K1OM is 64bit ELF only"));
2733 return bfd_arch_k1om;
2734 }
81486035
L		 2735 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2736 {
2737 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2738 || flag_code == CODE_64BIT)
2739 as_fatal (_("Intel MCU is 32bit ELF only"));
2740 return bfd_arch_iamcu;
2741 }
8a9036a4
L		 2742 else
2743 return bfd_arch_i386;
2744}
2745
b9d79e03 2746unsigned long
7016a5d5 2747i386_mach (void)
b9d79e03 2748{
351f65ca 2749 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2750 {
3632d14b 2751 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2752 {
351f65ca
L		 2753 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2754 || default_arch[6] != '\0')
8a9036a4
L		 2755 as_fatal (_("Intel L1OM is 64bit ELF only"));
2756 return bfd_mach_l1om;
2757 }
7a9068fe
L		 2758 else if (cpu_arch_isa == PROCESSOR_K1OM)
2759 {
2760 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2761 || default_arch[6] != '\0')
2762 as_fatal (_("Intel K1OM is 64bit ELF only"));
2763 return bfd_mach_k1om;
2764 }
351f65ca 2765 else if (default_arch[6] == '\0')
8a9036a4 2766 return bfd_mach_x86_64;
351f65ca
L		 2767 else
2768 return bfd_mach_x64_32;
8a9036a4 2769 }
5197d474
L		 2770 else if (!strcmp (default_arch, "i386")
2771 || !strcmp (default_arch, "iamcu"))
81486035
L		 2772 {
2773 if (cpu_arch_isa == PROCESSOR_IAMCU)
2774 {
2775 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2776 as_fatal (_("Intel MCU is 32bit ELF only"));
2777 return bfd_mach_i386_iamcu;
2778 }
2779 else
2780 return bfd_mach_i386_i386;
2781 }
b9d79e03 2782 else
2b5d6a91 2783 as_fatal (_("unknown architecture"));
b9d79e03 2784}
b9d79e03 2785\f
252b5132 2786void
7016a5d5 2787md_begin (void)
252b5132
RH		 2788{
2789 const char *hash_err;
2790
86fa6981
L		 2791 /* Support pseudo prefixes like {disp32}. */
2792 lex_type ['{'] = LEX_BEGIN_NAME;
2793
47926f60 2794 /* Initialize op_hash hash table. */
252b5132
RH		 2795 op_hash = hash_new ();
2796
2797 {
d3ce72d0 2798 const insn_template *optab;
29b0f896 2799 templates *core_optab;
252b5132 2800
47926f60
KH		 2801 /* Setup for loop. */
2802 optab = i386_optab;
add39d23 2803 core_optab = XNEW (templates);
252b5132
RH		 2804 core_optab->start = optab;
2805
2806 while (1)
2807 {
2808 ++optab;
2809 if (optab->name == NULL
2810 || strcmp (optab->name, (optab - 1)->name) != 0)
2811 {
2812 /* different name --> ship out current template list;
47926f60 2813 add to hash table; & begin anew. */
252b5132
RH		 2814 core_optab->end = optab;
2815 hash_err = hash_insert (op_hash,
2816 (optab - 1)->name,
5a49b8ac 2817 (void *) core_optab);
252b5132
RH		 2818 if (hash_err)
2819 {
b37df7c4 2820 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2821 (optab - 1)->name,
2822 hash_err);
2823 }
2824 if (optab->name == NULL)
2825 break;
add39d23 2826 core_optab = XNEW (templates);
252b5132
RH		 2827 core_optab->start = optab;
2828 }
2829 }
2830 }
2831
47926f60 2832 /* Initialize reg_hash hash table. */
252b5132
RH		 2833 reg_hash = hash_new ();
2834 {
29b0f896 2835 const reg_entry *regtab;
c3fe08fa 2836 unsigned int regtab_size = i386_regtab_size;
252b5132 2837
c3fe08fa 2838 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2839 {
5a49b8ac 2840 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2841 if (hash_err)
b37df7c4 2842 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2843 regtab->reg_name,
2844 hash_err);
252b5132
RH		 2845 }
2846 }
2847
47926f60 2848 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2849 {
29b0f896
AM		 2850 int c;
2851 char *p;
252b5132
RH		 2852
2853 for (c = 0; c < 256; c++)
2854 {
3882b010 2855 if (ISDIGIT (c))
252b5132
RH		 2856 {
2857 digit_chars[c] = c;
2858 mnemonic_chars[c] = c;
2859 register_chars[c] = c;
2860 operand_chars[c] = c;
2861 }
3882b010 2862 else if (ISLOWER (c))
252b5132
RH		 2863 {
2864 mnemonic_chars[c] = c;
2865 register_chars[c] = c;
2866 operand_chars[c] = c;
2867 }
3882b010 2868 else if (ISUPPER (c))
252b5132 2869 {
3882b010 2870 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2871 register_chars[c] = mnemonic_chars[c];
2872 operand_chars[c] = c;
2873 }
43234a1e 2874 else if (c == '{' || c == '}')
86fa6981
L		 2875 {
2876 mnemonic_chars[c] = c;
2877 operand_chars[c] = c;
2878 }
252b5132 2879
3882b010 2880 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2881 identifier_chars[c] = c;
2882 else if (c >= 128)
2883 {
2884 identifier_chars[c] = c;
2885 operand_chars[c] = c;
2886 }
2887 }
2888
2889#ifdef LEX_AT
2890 identifier_chars['@'] = '@';
32137342
NC		 2891#endif
2892#ifdef LEX_QM
2893 identifier_chars['?'] = '?';
2894 operand_chars['?'] = '?';
252b5132 2895#endif
252b5132 2896 digit_chars['-'] = '-';
c0f3af97 2897 mnemonic_chars['_'] = '_';
791fe849 2898 mnemonic_chars['-'] = '-';
0003779b 2899 mnemonic_chars['.'] = '.';
252b5132
RH		 2900 identifier_chars['_'] = '_';
2901 identifier_chars['.'] = '.';
2902
2903 for (p = operand_special_chars; *p != '\0'; p++)
2904 operand_chars[(unsigned char) *p] = *p;
2905 }
2906
a4447b93
RH		 2907 if (flag_code == CODE_64BIT)
2908 {
ca19b261
KT		 2909#if defined (OBJ_COFF) && defined (TE_PE)
2910 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2911 ? 32 : 16);
2912#else
a4447b93 2913 x86_dwarf2_return_column = 16;
ca19b261 2914#endif
61ff971f 2915 x86_cie_data_alignment = -8;
a4447b93
RH		 2916 }
2917 else
2918 {
2919 x86_dwarf2_return_column = 8;
2920 x86_cie_data_alignment = -4;
2921 }
252b5132
RH		 2922}
2923
2924void
e3bb37b5 2925i386_print_statistics (FILE *file)
252b5132
RH		 2926{
2927 hash_print_statistics (file, "i386 opcode", op_hash);
2928 hash_print_statistics (file, "i386 register", reg_hash);
2929}
2930\f
252b5132
RH		 2931#ifdef DEBUG386
2932
ce8a8b2f 2933/* Debugging routines for md_assemble. */
d3ce72d0 2934static void pte (insn_template *);
40fb9820 2935static void pt (i386_operand_type);
e3bb37b5
L		 2936static void pe (expressionS *);
2937static void ps (symbolS *);
252b5132
RH		 2938
2939static void
e3bb37b5 2940pi (char *line, i386_insn *x)
252b5132 2941{
09137c09 2942 unsigned int j;
252b5132
RH		 2943
2944 fprintf (stdout, "%s: template ", line);
2945 pte (&x->tm);
09f131f2
JH		 2946 fprintf (stdout, " address: base %s index %s scale %x\n",
2947 x->base_reg ? x->base_reg->reg_name : "none",
2948 x->index_reg ? x->index_reg->reg_name : "none",
2949 x->log2_scale_factor);
2950 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2951 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2952 fprintf (stdout, " sib: base %x index %x scale %x\n",
2953 x->sib.base, x->sib.index, x->sib.scale);
2954 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2955 (x->rex & REX_W) != 0,
2956 (x->rex & REX_R) != 0,
2957 (x->rex & REX_X) != 0,
2958 (x->rex & REX_B) != 0);
09137c09 2959 for (j = 0; j < x->operands; j++)
252b5132 2960 {
09137c09
SP		 2961 fprintf (stdout, " #%d: ", j + 1);
2962 pt (x->types[j]);
252b5132 2963 fprintf (stdout, "\n");
dc821c5f 2964 if (x->types[j].bitfield.reg
09137c09 2965 || x->types[j].bitfield.regmmx
1b54b8d7 2966 || x->types[j].bitfield.regsimd
09137c09
SP		 2967 || x->types[j].bitfield.sreg2
2968 || x->types[j].bitfield.sreg3
2969 || x->types[j].bitfield.control
2970 || x->types[j].bitfield.debug
2971 || x->types[j].bitfield.test)
2972 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2973 if (operand_type_check (x->types[j], imm))
2974 pe (x->op[j].imms);
2975 if (operand_type_check (x->types[j], disp))
2976 pe (x->op[j].disps);
252b5132
RH		 2977 }
2978}
2979
2980static void
d3ce72d0 2981pte (insn_template *t)
252b5132 2982{
09137c09 2983 unsigned int j;
252b5132 2984 fprintf (stdout, " %d operands ", t->operands);
47926f60 2985 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2986 if (t->extension_opcode != None)
2987 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2988 if (t->opcode_modifier.d)
252b5132 2989 fprintf (stdout, "D");
40fb9820 2990 if (t->opcode_modifier.w)
252b5132
RH		 2991 fprintf (stdout, "W");
2992 fprintf (stdout, "\n");
09137c09 2993 for (j = 0; j < t->operands; j++)
252b5132 2994 {
09137c09
SP		 2995 fprintf (stdout, " #%d type ", j + 1);
2996 pt (t->operand_types[j]);
252b5132
RH		 2997 fprintf (stdout, "\n");
2998 }
2999}
3000
3001static void
e3bb37b5 3002pe (expressionS *e)
252b5132 3003{
24eab124 3004 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 3005 fprintf (stdout, " add_number %ld (%lx)\n",
3006 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 3007 if (e->X_add_symbol)
3008 {
3009 fprintf (stdout, " add_symbol ");
3010 ps (e->X_add_symbol);
3011 fprintf (stdout, "\n");
3012 }
3013 if (e->X_op_symbol)
3014 {
3015 fprintf (stdout, " op_symbol ");
3016 ps (e->X_op_symbol);
3017 fprintf (stdout, "\n");
3018 }
3019}
3020
3021static void
e3bb37b5 3022ps (symbolS *s)
252b5132
RH		 3023{
3024 fprintf (stdout, "%s type %s%s",
3025 S_GET_NAME (s),
3026 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3027 segment_name (S_GET_SEGMENT (s)));
3028}
3029
7b81dfbb 3030static struct type_name
252b5132 3031 {
40fb9820
L		 3032 i386_operand_type mask;
3033 const char *name;
252b5132 3034 }
7b81dfbb 3035const type_names[] =
252b5132 3036{
40fb9820
L		 3037 { OPERAND_TYPE_REG8, "r8" },
3038 { OPERAND_TYPE_REG16, "r16" },
3039 { OPERAND_TYPE_REG32, "r32" },
3040 { OPERAND_TYPE_REG64, "r64" },
3041 { OPERAND_TYPE_IMM8, "i8" },
3042 { OPERAND_TYPE_IMM8, "i8s" },
3043 { OPERAND_TYPE_IMM16, "i16" },
3044 { OPERAND_TYPE_IMM32, "i32" },
3045 { OPERAND_TYPE_IMM32S, "i32s" },
3046 { OPERAND_TYPE_IMM64, "i64" },
3047 { OPERAND_TYPE_IMM1, "i1" },
3048 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3049 { OPERAND_TYPE_DISP8, "d8" },
3050 { OPERAND_TYPE_DISP16, "d16" },
3051 { OPERAND_TYPE_DISP32, "d32" },
3052 { OPERAND_TYPE_DISP32S, "d32s" },
3053 { OPERAND_TYPE_DISP64, "d64" },
3054 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3055 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3056 { OPERAND_TYPE_CONTROL, "control reg" },
3057 { OPERAND_TYPE_TEST, "test reg" },
3058 { OPERAND_TYPE_DEBUG, "debug reg" },
3059 { OPERAND_TYPE_FLOATREG, "FReg" },
3060 { OPERAND_TYPE_FLOATACC, "FAcc" },
3061 { OPERAND_TYPE_SREG2, "SReg2" },
3062 { OPERAND_TYPE_SREG3, "SReg3" },
3063 { OPERAND_TYPE_ACC, "Acc" },
3064 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3065 { OPERAND_TYPE_REGMMX, "rMMX" },
3066 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3067 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3068 { OPERAND_TYPE_REGZMM, "rZMM" },
3069 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3070 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3071};
3072
3073static void
40fb9820 3074pt (i386_operand_type t)
252b5132 3075{
40fb9820 3076 unsigned int j;
c6fb90c8 3077 i386_operand_type a;
252b5132 3078
40fb9820 3079 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3080 {
3081 a = operand_type_and (t, type_names[j].mask);
0349dc08 3082 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3083 fprintf (stdout, "%s, ", type_names[j].name);
3084 }
252b5132
RH		 3085 fflush (stdout);
3086}
3087
3088#endif /* DEBUG386 */
3089\f
252b5132 3090static bfd_reloc_code_real_type
3956db08 3091reloc (unsigned int size,
64e74474
AM		 3092 int pcrel,
3093 int sign,
3094 bfd_reloc_code_real_type other)
252b5132 3095{
47926f60 3096 if (other != NO_RELOC)
3956db08 3097 {
91d6fa6a 3098 reloc_howto_type *rel;
3956db08
JB		 3099
3100 if (size == 8)
3101 switch (other)
3102 {
64e74474
AM		 3103 case BFD_RELOC_X86_64_GOT32:
3104 return BFD_RELOC_X86_64_GOT64;
3105 break;
553d1284
L		 3106 case BFD_RELOC_X86_64_GOTPLT64:
3107 return BFD_RELOC_X86_64_GOTPLT64;
3108 break;
64e74474
AM		 3109 case BFD_RELOC_X86_64_PLTOFF64:
3110 return BFD_RELOC_X86_64_PLTOFF64;
3111 break;
3112 case BFD_RELOC_X86_64_GOTPC32:
3113 other = BFD_RELOC_X86_64_GOTPC64;
3114 break;
3115 case BFD_RELOC_X86_64_GOTPCREL:
3116 other = BFD_RELOC_X86_64_GOTPCREL64;
3117 break;
3118 case BFD_RELOC_X86_64_TPOFF32:
3119 other = BFD_RELOC_X86_64_TPOFF64;
3120 break;
3121 case BFD_RELOC_X86_64_DTPOFF32:
3122 other = BFD_RELOC_X86_64_DTPOFF64;
3123 break;
3124 default:
3125 break;
3956db08 3126 }
e05278af 3127
8ce3d284 3128#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3129 if (other == BFD_RELOC_SIZE32)
3130 {
3131 if (size == 8)
1ab668bf 3132 other = BFD_RELOC_SIZE64;
8fd4256d 3133 if (pcrel)
1ab668bf
AM		 3134 {
3135 as_bad (_("there are no pc-relative size relocations"));
3136 return NO_RELOC;
3137 }
8fd4256d 3138 }
8ce3d284 3139#endif
8fd4256d 3140
e05278af 3141 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3142 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3143 sign = -1;
3144
91d6fa6a
NC		 3145 rel = bfd_reloc_type_lookup (stdoutput, other);
3146 if (!rel)
3956db08 3147 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3148 else if (size != bfd_get_reloc_size (rel))
3956db08 3149 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3150 bfd_get_reloc_size (rel),
3956db08 3151 size);
91d6fa6a 3152 else if (pcrel && !rel->pc_relative)
3956db08 3153 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3154 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3155 && !sign)
91d6fa6a 3156 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3157 && sign > 0))
3956db08
JB		 3158 as_bad (_("relocated field and relocation type differ in signedness"));
3159 else
3160 return other;
3161 return NO_RELOC;
3162 }
252b5132
RH		 3163
3164 if (pcrel)
3165 {
3e73aa7c 3166 if (!sign)
3956db08 3167 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3168 switch (size)
3169 {
3170 case 1: return BFD_RELOC_8_PCREL;
3171 case 2: return BFD_RELOC_16_PCREL;
d258b828 3172 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3173 case 8: return BFD_RELOC_64_PCREL;
252b5132 3174 }
3956db08 3175 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3176 }
3177 else
3178 {
3956db08 3179 if (sign > 0)
e5cb08ac 3180 switch (size)
3e73aa7c
JH		 3181 {
3182 case 4: return BFD_RELOC_X86_64_32S;
3183 }
3184 else
3185 switch (size)
3186 {
3187 case 1: return BFD_RELOC_8;
3188 case 2: return BFD_RELOC_16;
3189 case 4: return BFD_RELOC_32;
3190 case 8: return BFD_RELOC_64;
3191 }
3956db08
JB		 3192 as_bad (_("cannot do %s %u byte relocation"),
3193 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3194 }
3195
0cc9e1d3 3196 return NO_RELOC;
252b5132
RH		 3197}
3198
47926f60
KH		 3199/* Here we decide which fixups can be adjusted to make them relative to
3200 the beginning of the section instead of the symbol. Basically we need
3201 to make sure that the dynamic relocations are done correctly, so in
3202 some cases we force the original symbol to be used. */
3203
252b5132 3204int
e3bb37b5 3205tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3206{
6d249963 3207#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3208 if (!IS_ELF)
31312f95
AM		 3209 return 1;
3210
a161fe53
AM		 3211 /* Don't adjust pc-relative references to merge sections in 64-bit
3212 mode. */
3213 if (use_rela_relocations
3214 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3215 && fixP->fx_pcrel)
252b5132 3216 return 0;
31312f95 3217
8d01d9a9
AJ		 3218 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3219 and changed later by validate_fix. */
3220 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3221 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3222 return 0;
3223
8fd4256d
L		 3224 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3225 for size relocations. */
3226 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3227 || fixP->fx_r_type == BFD_RELOC_SIZE64
3228 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3229 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3230 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3231 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3233 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3234 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3235 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3236 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3237 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3238 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3239 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3240 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3241 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3242 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3243 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3247 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3248 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3249 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3250 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3251 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3252 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3253 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3254 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3255 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3256 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3257 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3258 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3259 return 0;
31312f95 3260#endif
252b5132
RH		 3261 return 1;
3262}
252b5132 3263
b4cac588 3264static int
e3bb37b5 3265intel_float_operand (const char *mnemonic)
252b5132 3266{
9306ca4a
JB		 3267 /* Note that the value returned is meaningful only for opcodes with (memory)
3268 operands, hence the code here is free to improperly handle opcodes that
3269 have no operands (for better performance and smaller code). */
3270
3271 if (mnemonic[0] != 'f')
3272 return 0; /* non-math */
3273
3274 switch (mnemonic[1])
3275 {
3276 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3277 the fs segment override prefix not currently handled because no
3278 call path can make opcodes without operands get here */
3279 case 'i':
3280 return 2 /* integer op */;
3281 case 'l':
3282 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3283 return 3; /* fldcw/fldenv */
3284 break;
3285 case 'n':
3286 if (mnemonic[2] != 'o' /* fnop */)
3287 return 3; /* non-waiting control op */
3288 break;
3289 case 'r':
3290 if (mnemonic[2] == 's')
3291 return 3; /* frstor/frstpm */
3292 break;
3293 case 's':
3294 if (mnemonic[2] == 'a')
3295 return 3; /* fsave */
3296 if (mnemonic[2] == 't')
3297 {
3298 switch (mnemonic[3])
3299 {
3300 case 'c': /* fstcw */
3301 case 'd': /* fstdw */
3302 case 'e': /* fstenv */
3303 case 's': /* fsts[gw] */
3304 return 3;
3305 }
3306 }
3307 break;
3308 case 'x':
3309 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3310 return 0; /* fxsave/fxrstor are not really math ops */
3311 break;
3312 }
252b5132 3313
9306ca4a 3314 return 1;
252b5132
RH		 3315}
3316
c0f3af97
L		 3317/* Build the VEX prefix. */
3318
3319static void
d3ce72d0 3320build_vex_prefix (const insn_template *t)
c0f3af97
L		 3321{
3322 unsigned int register_specifier;
3323 unsigned int implied_prefix;
3324 unsigned int vector_length;
3325
3326 /* Check register specifier. */
3327 if (i.vex.register_specifier)
43234a1e
L		 3328 {
3329 register_specifier =
3330 ~register_number (i.vex.register_specifier) & 0xf;
3331 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3332 }
c0f3af97
L		 3333 else
3334 register_specifier = 0xf;
3335
33eaf5de 3336 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3337 operand. */
86fa6981
L		 3338 if (i.vec_encoding != vex_encoding_vex3
3339 && i.dir_encoding == dir_encoding_default
fa99fab2 3340 && i.operands == i.reg_operands
7f399153 3341 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3342 && i.tm.opcode_modifier.load
fa99fab2
L		 3343 && i.rex == REX_B)
3344 {
3345 unsigned int xchg = i.operands - 1;
3346 union i386_op temp_op;
3347 i386_operand_type temp_type;
3348
3349 temp_type = i.types[xchg];
3350 i.types[xchg] = i.types[0];
3351 i.types[0] = temp_type;
3352 temp_op = i.op[xchg];
3353 i.op[xchg] = i.op[0];
3354 i.op[0] = temp_op;
3355
9c2799c2 3356 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3357
3358 i.rex = REX_R;
3359 xchg = i.rm.regmem;
3360 i.rm.regmem = i.rm.reg;
3361 i.rm.reg = xchg;
3362
3363 /* Use the next insn. */
3364 i.tm = t[1];
3365 }
3366
539f890d
L		 3367 if (i.tm.opcode_modifier.vex == VEXScalar)
3368 vector_length = avxscalar;
10c17abd
JB		 3369 else if (i.tm.opcode_modifier.vex == VEX256)
3370 vector_length = 1;
539f890d 3371 else
10c17abd
JB		 3372 {
3373 unsigned int op;
3374
3375 vector_length = 0;
3376 for (op = 0; op < t->operands; ++op)
3377 if (t->operand_types[op].bitfield.xmmword
3378 && t->operand_types[op].bitfield.ymmword
3379 && i.types[op].bitfield.ymmword)
3380 {
3381 vector_length = 1;
3382 break;
3383 }
3384 }
c0f3af97
L		 3385
3386 switch ((i.tm.base_opcode >> 8) & 0xff)
3387 {
3388 case 0:
3389 implied_prefix = 0;
3390 break;
3391 case DATA_PREFIX_OPCODE:
3392 implied_prefix = 1;
3393 break;
3394 case REPE_PREFIX_OPCODE:
3395 implied_prefix = 2;
3396 break;
3397 case REPNE_PREFIX_OPCODE:
3398 implied_prefix = 3;
3399 break;
3400 default:
3401 abort ();
3402 }
3403
3404 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3405 if (i.vec_encoding != vex_encoding_vex3
3406 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3407 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3408 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3409 {
3410 /* 2-byte VEX prefix. */
3411 unsigned int r;
3412
3413 i.vex.length = 2;
3414 i.vex.bytes[0] = 0xc5;
3415
3416 /* Check the REX.R bit. */
3417 r = (i.rex & REX_R) ? 0 : 1;
3418 i.vex.bytes[1] = (r << 7
3419 | register_specifier << 3
3420 | vector_length << 2
3421 | implied_prefix);
3422 }
3423 else
3424 {
3425 /* 3-byte VEX prefix. */
3426 unsigned int m, w;
3427
f88c9eb0 3428 i.vex.length = 3;
f88c9eb0 3429
7f399153 3430 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3431 {
7f399153
L		 3432 case VEX0F:
3433 m = 0x1;
80de6e00 3434 i.vex.bytes[0] = 0xc4;
7f399153
L		 3435 break;
3436 case VEX0F38:
3437 m = 0x2;
80de6e00 3438 i.vex.bytes[0] = 0xc4;
7f399153
L		 3439 break;
3440 case VEX0F3A:
3441 m = 0x3;
80de6e00 3442 i.vex.bytes[0] = 0xc4;
7f399153
L		 3443 break;
3444 case XOP08:
5dd85c99
SP		 3445 m = 0x8;
3446 i.vex.bytes[0] = 0x8f;
7f399153
L		 3447 break;
3448 case XOP09:
f88c9eb0
SP		 3449 m = 0x9;
3450 i.vex.bytes[0] = 0x8f;
7f399153
L		 3451 break;
3452 case XOP0A:
f88c9eb0
SP		 3453 m = 0xa;
3454 i.vex.bytes[0] = 0x8f;
7f399153
L		 3455 break;
3456 default:
3457 abort ();
f88c9eb0 3458 }
c0f3af97 3459
c0f3af97
L		 3460 /* The high 3 bits of the second VEX byte are 1's compliment
3461 of RXB bits from REX. */
3462 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3463
3464 /* Check the REX.W bit. */
3465 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3466 if (i.tm.opcode_modifier.vexw == VEXW1)
3467 w = 1;
c0f3af97
L		 3468
3469 i.vex.bytes[2] = (w << 7
3470 | register_specifier << 3
3471 | vector_length << 2
3472 | implied_prefix);
3473 }
3474}
3475
43234a1e
L		 3476/* Build the EVEX prefix. */
3477
3478static void
3479build_evex_prefix (void)
3480{
3481 unsigned int register_specifier;
3482 unsigned int implied_prefix;
3483 unsigned int m, w;
3484 rex_byte vrex_used = 0;
3485
3486 /* Check register specifier. */
3487 if (i.vex.register_specifier)
3488 {
3489 gas_assert ((i.vrex & REX_X) == 0);
3490
3491 register_specifier = i.vex.register_specifier->reg_num;
3492 if ((i.vex.register_specifier->reg_flags & RegRex))
3493 register_specifier += 8;
3494 /* The upper 16 registers are encoded in the fourth byte of the
3495 EVEX prefix. */
3496 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3497 i.vex.bytes[3] = 0x8;
3498 register_specifier = ~register_specifier & 0xf;
3499 }
3500 else
3501 {
3502 register_specifier = 0xf;
3503
3504 /* Encode upper 16 vector index register in the fourth byte of
3505 the EVEX prefix. */
3506 if (!(i.vrex & REX_X))
3507 i.vex.bytes[3] = 0x8;
3508 else
3509 vrex_used |= REX_X;
3510 }
3511
3512 switch ((i.tm.base_opcode >> 8) & 0xff)
3513 {
3514 case 0:
3515 implied_prefix = 0;
3516 break;
3517 case DATA_PREFIX_OPCODE:
3518 implied_prefix = 1;
3519 break;
3520 case REPE_PREFIX_OPCODE:
3521 implied_prefix = 2;
3522 break;
3523 case REPNE_PREFIX_OPCODE:
3524 implied_prefix = 3;
3525 break;
3526 default:
3527 abort ();
3528 }
3529
3530 /* 4 byte EVEX prefix. */
3531 i.vex.length = 4;
3532 i.vex.bytes[0] = 0x62;
3533
3534 /* mmmm bits. */
3535 switch (i.tm.opcode_modifier.vexopcode)
3536 {
3537 case VEX0F:
3538 m = 1;
3539 break;
3540 case VEX0F38:
3541 m = 2;
3542 break;
3543 case VEX0F3A:
3544 m = 3;
3545 break;
3546 default:
3547 abort ();
3548 break;
3549 }
3550
3551 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3552 bits from REX. */
3553 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3554
3555 /* The fifth bit of the second EVEX byte is 1's compliment of the
3556 REX_R bit in VREX. */
3557 if (!(i.vrex & REX_R))
3558 i.vex.bytes[1] |= 0x10;
3559 else
3560 vrex_used |= REX_R;
3561
3562 if ((i.reg_operands + i.imm_operands) == i.operands)
3563 {
3564 /* When all operands are registers, the REX_X bit in REX is not
3565 used. We reuse it to encode the upper 16 registers, which is
3566 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3567 as 1's compliment. */
3568 if ((i.vrex & REX_B))
3569 {
3570 vrex_used |= REX_B;
3571 i.vex.bytes[1] &= ~0x40;
3572 }
3573 }
3574
3575 /* EVEX instructions shouldn't need the REX prefix. */
3576 i.vrex &= ~vrex_used;
3577 gas_assert (i.vrex == 0);
3578
3579 /* Check the REX.W bit. */
3580 w = (i.rex & REX_W) ? 1 : 0;
3581 if (i.tm.opcode_modifier.vexw)
3582 {
3583 if (i.tm.opcode_modifier.vexw == VEXW1)
3584 w = 1;
3585 }
3586 /* If w is not set it means we are dealing with WIG instruction. */
3587 else if (!w)
3588 {
3589 if (evexwig == evexw1)
3590 w = 1;
3591 }
3592
3593 /* Encode the U bit. */
3594 implied_prefix |= 0x4;
3595
3596 /* The third byte of the EVEX prefix. */
3597 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3598
3599 /* The fourth byte of the EVEX prefix. */
3600 /* The zeroing-masking bit. */
3601 if (i.mask && i.mask->zeroing)
3602 i.vex.bytes[3] |= 0x80;
3603
3604 /* Don't always set the broadcast bit if there is no RC. */
3605 if (!i.rounding)
3606 {
3607 /* Encode the vector length. */
3608 unsigned int vec_length;
3609
3610 switch (i.tm.opcode_modifier.evex)
3611 {
3612 case EVEXLIG: /* LL' is ignored */
3613 vec_length = evexlig << 5;
3614 break;
3615 case EVEX128:
3616 vec_length = 0 << 5;
3617 break;
3618 case EVEX256:
3619 vec_length = 1 << 5;
3620 break;
3621 case EVEX512:
3622 vec_length = 2 << 5;
3623 break;
3624 default:
3625 abort ();
3626 break;
3627 }
3628 i.vex.bytes[3] |= vec_length;
3629 /* Encode the broadcast bit. */
3630 if (i.broadcast)
3631 i.vex.bytes[3] |= 0x10;
3632 }
3633 else
3634 {
3635 if (i.rounding->type != saeonly)
3636 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3637 else
d3d3c6db 3638 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3639 }
3640
3641 if (i.mask && i.mask->mask)
3642 i.vex.bytes[3] |= i.mask->mask->reg_num;
3643}
3644
65da13b5
L		 3645static void
3646process_immext (void)
3647{
3648 expressionS *exp;
3649
4c692bc7
JB		 3650 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3651 && i.operands > 0)
65da13b5 3652 {
4c692bc7
JB		 3653 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3654 with an opcode suffix which is coded in the same place as an
3655 8-bit immediate field would be.
3656 Here we check those operands and remove them afterwards. */
65da13b5
L		 3657 unsigned int x;
3658
3659 for (x = 0; x < i.operands; x++)
4c692bc7 3660 if (register_number (i.op[x].regs) != x)
65da13b5 3661 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3662 register_prefix, i.op[x].regs->reg_name, x + 1,
3663 i.tm.name);
3664
3665 i.operands = 0;
65da13b5
L		 3666 }
3667
9916071f
AP		 3668 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3669 {
3670 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3671 suffix which is coded in the same place as an 8-bit immediate
3672 field would be.
3673 Here we check those operands and remove them afterwards. */
3674 unsigned int x;
3675
3676 if (i.operands != 3)
3677 abort();
3678
3679 for (x = 0; x < 2; x++)
3680 if (register_number (i.op[x].regs) != x)
3681 goto bad_register_operand;
3682
3683 /* Check for third operand for mwaitx/monitorx insn. */
3684 if (register_number (i.op[x].regs)
3685 != (x + (i.tm.extension_opcode == 0xfb)))
3686 {
3687bad_register_operand:
3688 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3689 register_prefix, i.op[x].regs->reg_name, x+1,
3690 i.tm.name);
3691 }
3692
3693 i.operands = 0;
3694 }
3695
c0f3af97 3696 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3697 which is coded in the same place as an 8-bit immediate field
3698 would be. Here we fake an 8-bit immediate operand from the
3699 opcode suffix stored in tm.extension_opcode.
3700
c1e679ec 3701 AVX instructions also use this encoding, for some of
c0f3af97 3702 3 argument instructions. */
65da13b5 3703
43234a1e 3704 gas_assert (i.imm_operands <= 1
7ab9ffdd 3705 && (i.operands <= 2
43234a1e
L		 3706 || ((i.tm.opcode_modifier.vex
3707 || i.tm.opcode_modifier.evex)
7ab9ffdd 3708 && i.operands <= 4)));
65da13b5
L		 3709
3710 exp = &im_expressions[i.imm_operands++];
3711 i.op[i.operands].imms = exp;
3712 i.types[i.operands] = imm8;
3713 i.operands++;
3714 exp->X_op = O_constant;
3715 exp->X_add_number = i.tm.extension_opcode;
3716 i.tm.extension_opcode = None;
3717}
3718
42164a71
L		 3719
3720static int
3721check_hle (void)
3722{
3723 switch (i.tm.opcode_modifier.hleprefixok)
3724 {
3725 default:
3726 abort ();
82c2def5 3727 case HLEPrefixNone:
165de32a
L		 3728 as_bad (_("invalid instruction `%s' after `%s'"),
3729 i.tm.name, i.hle_prefix);
42164a71 3730 return 0;
82c2def5 3731 case HLEPrefixLock:
42164a71
L		 3732 if (i.prefix[LOCK_PREFIX])
3733 return 1;
165de32a 3734 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3735 return 0;
82c2def5 3736 case HLEPrefixAny:
42164a71 3737 return 1;
82c2def5 3738 case HLEPrefixRelease:
42164a71
L		 3739 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3740 {
3741 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3742 i.tm.name);
3743 return 0;
3744 }
3745 if (i.mem_operands == 0
3746 || !operand_type_check (i.types[i.operands - 1], anymem))
3747 {
3748 as_bad (_("memory destination needed for instruction `%s'"
3749 " after `xrelease'"), i.tm.name);
3750 return 0;
3751 }
3752 return 1;
3753 }
3754}
3755
b6f8c7c4
L		 3756/* Try the shortest encoding by shortening operand size. */
3757
3758static void
3759optimize_encoding (void)
3760{
3761 int j;
3762
3763 if (optimize_for_space
3764 && i.reg_operands == 1
3765 && i.imm_operands == 1
3766 && !i.types[1].bitfield.byte
3767 && i.op[0].imms->X_op == O_constant
3768 && fits_in_imm7 (i.op[0].imms->X_add_number)
3769 && ((i.tm.base_opcode == 0xa8
3770 && i.tm.extension_opcode == None)
3771 || (i.tm.base_opcode == 0xf6
3772 && i.tm.extension_opcode == 0x0)))
3773 {
3774 /* Optimize: -Os:
3775 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3776 */
3777 unsigned int base_regnum = i.op[1].regs->reg_num;
3778 if (flag_code == CODE_64BIT || base_regnum < 4)
3779 {
3780 i.types[1].bitfield.byte = 1;
3781 /* Ignore the suffix. */
3782 i.suffix = 0;
3783 if (base_regnum >= 4
3784 && !(i.op[1].regs->reg_flags & RegRex))
3785 {
3786 /* Handle SP, BP, SI and DI registers. */
3787 if (i.types[1].bitfield.word)
3788 j = 16;
3789 else if (i.types[1].bitfield.dword)
3790 j = 32;
3791 else
3792 j = 48;
3793 i.op[1].regs -= j;
3794 }
3795 }
3796 }
3797 else if (flag_code == CODE_64BIT
3798 && ((i.reg_operands == 1
3799 && i.imm_operands == 1
3800 && i.op[0].imms->X_op == O_constant
3801 && ((i.tm.base_opcode == 0xb0
3802 && i.tm.extension_opcode == None
3803 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3804 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3805 && (((i.tm.base_opcode == 0x24
3806 || i.tm.base_opcode == 0xa8)
3807 && i.tm.extension_opcode == None)
3808 || (i.tm.base_opcode == 0x80
3809 && i.tm.extension_opcode == 0x4)
3810 || ((i.tm.base_opcode == 0xf6
3811 || i.tm.base_opcode == 0xc6)
3812 && i.tm.extension_opcode == 0x0)))))
3813 || (i.reg_operands == 2
3814 && i.op[0].regs == i.op[1].regs
3815 && ((i.tm.base_opcode == 0x30
3816 || i.tm.base_opcode == 0x28)
3817 && i.tm.extension_opcode == None)))
3818 && i.types[1].bitfield.qword)
3819 {
3820 /* Optimize: -O:
3821 andq $imm31, %r64 -> andl $imm31, %r32
3822 testq $imm31, %r64 -> testl $imm31, %r32
3823 xorq %r64, %r64 -> xorl %r32, %r32
3824 subq %r64, %r64 -> subl %r32, %r32
3825 movq $imm31, %r64 -> movl $imm31, %r32
3826 movq $imm32, %r64 -> movl $imm32, %r32
3827 */
3828 i.tm.opcode_modifier.norex64 = 1;
3829 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3830 {
3831 /* Handle
3832 movq $imm31, %r64 -> movl $imm31, %r32
3833 movq $imm32, %r64 -> movl $imm32, %r32
3834 */
3835 i.tm.operand_types[0].bitfield.imm32 = 1;
3836 i.tm.operand_types[0].bitfield.imm32s = 0;
3837 i.tm.operand_types[0].bitfield.imm64 = 0;
3838 i.types[0].bitfield.imm32 = 1;
3839 i.types[0].bitfield.imm32s = 0;
3840 i.types[0].bitfield.imm64 = 0;
3841 i.types[1].bitfield.dword = 1;
3842 i.types[1].bitfield.qword = 0;
3843 if (i.tm.base_opcode == 0xc6)
3844 {
3845 /* Handle
3846 movq $imm31, %r64 -> movl $imm31, %r32
3847 */
3848 i.tm.base_opcode = 0xb0;
3849 i.tm.extension_opcode = None;
3850 i.tm.opcode_modifier.shortform = 1;
3851 i.tm.opcode_modifier.modrm = 0;
3852 }
3853 }
3854 }
3855 else if (optimize > 1
3856 && i.reg_operands == 3
3857 && i.op[0].regs == i.op[1].regs
3858 && !i.types[2].bitfield.xmmword
3859 && (i.tm.opcode_modifier.vex
3860 || (!i.mask
3861 && !i.rounding
3862 && i.tm.opcode_modifier.evex
3863 && cpu_arch_flags.bitfield.cpuavx512vl))
3864 && ((i.tm.base_opcode == 0x55
3865 || i.tm.base_opcode == 0x6655
3866 || i.tm.base_opcode == 0x66df
3867 || i.tm.base_opcode == 0x57
3868 || i.tm.base_opcode == 0x6657
8305403a
L		 3869 || i.tm.base_opcode == 0x66ef
3870 || i.tm.base_opcode == 0x66f8
3871 || i.tm.base_opcode == 0x66f9
3872 || i.tm.base_opcode == 0x66fa
3873 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3874 && i.tm.extension_opcode == None))
3875 {
3876 /* Optimize: -O2:
8305403a
L		 3877 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3878 vpsubq and vpsubw:
b6f8c7c4
L		 3879 EVEX VOP %zmmM, %zmmM, %zmmN
3880 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3881 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3882 EVEX VOP %ymmM, %ymmM, %ymmN
3883 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3884 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3885 VEX VOP %ymmM, %ymmM, %ymmN
3886 -> VEX VOP %xmmM, %xmmM, %xmmN
3887 VOP, one of vpandn and vpxor:
3888 VEX VOP %ymmM, %ymmM, %ymmN
3889 -> VEX VOP %xmmM, %xmmM, %xmmN
3890 VOP, one of vpandnd and vpandnq:
3891 EVEX VOP %zmmM, %zmmM, %zmmN
3892 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3893 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3894 EVEX VOP %ymmM, %ymmM, %ymmN
3895 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3896 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3897 VOP, one of vpxord and vpxorq:
3898 EVEX VOP %zmmM, %zmmM, %zmmN
3899 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3900 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3901 EVEX VOP %ymmM, %ymmM, %ymmN
3902 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3903 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3904 */
3905 if (i.tm.opcode_modifier.evex)
3906 {
3907 /* If only lower 16 vector registers are used, we can use
3908 VEX encoding. */
3909 for (j = 0; j < 3; j++)
3910 if (register_number (i.op[j].regs) > 15)
3911 break;
3912
3913 if (j < 3)
3914 i.tm.opcode_modifier.evex = EVEX128;
3915 else
3916 {
3917 i.tm.opcode_modifier.vex = VEX128;
3918 i.tm.opcode_modifier.vexw = VEXW0;
3919 i.tm.opcode_modifier.evex = 0;
3920 }
3921 }
3922 else
3923 i.tm.opcode_modifier.vex = VEX128;
3924
3925 if (i.tm.opcode_modifier.vex)
3926 for (j = 0; j < 3; j++)
3927 {
3928 i.types[j].bitfield.xmmword = 1;
3929 i.types[j].bitfield.ymmword = 0;
3930 }
3931 }
3932}
3933
252b5132
RH		 3934/* This is the guts of the machine-dependent assembler. LINE points to a
3935 machine dependent instruction. This function is supposed to emit
3936 the frags/bytes it assembles to. */
3937
3938void
65da13b5 3939md_assemble (char *line)
252b5132 3940{
40fb9820 3941 unsigned int j;
83b16ac6 3942 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3943 const insn_template *t;
252b5132 3944
47926f60 3945 /* Initialize globals. */
252b5132
RH		 3946 memset (&i, '\0', sizeof (i));
3947 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3948 i.reloc[j] = NO_RELOC;
252b5132
RH		 3949 memset (disp_expressions, '\0', sizeof (disp_expressions));
3950 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3951 save_stack_p = save_stack;
252b5132
RH		 3952
3953 /* First parse an instruction mnemonic & call i386_operand for the operands.
3954 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3955 start of a (possibly prefixed) mnemonic. */
252b5132 3956
29b0f896
AM		 3957 line = parse_insn (line, mnemonic);
3958 if (line == NULL)
3959 return;
83b16ac6 3960 mnem_suffix = i.suffix;
252b5132 3961
29b0f896 3962 line = parse_operands (line, mnemonic);
ee86248c 3963 this_operand = -1;
8325cc63
JB		 3964 xfree (i.memop1_string);
3965 i.memop1_string = NULL;
29b0f896
AM		 3966 if (line == NULL)
3967 return;
252b5132 3968
29b0f896
AM		 3969 /* Now we've parsed the mnemonic into a set of templates, and have the
3970 operands at hand. */
3971
3972 /* All intel opcodes have reversed operands except for "bound" and
3973 "enter". We also don't reverse intersegment "jmp" and "call"
3974 instructions with 2 immediate operands so that the immediate segment
050dfa73 3975 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3976 if (intel_syntax
3977 && i.operands > 1
29b0f896 3978 && (strcmp (mnemonic, "bound") != 0)
30123838 3979 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3980 && !(operand_type_check (i.types[0], imm)
3981 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3982 swap_operands ();
3983
ec56d5c0
JB		 3984 /* The order of the immediates should be reversed
3985 for 2 immediates extrq and insertq instructions */
3986 if (i.imm_operands == 2
3987 && (strcmp (mnemonic, "extrq") == 0
3988 || strcmp (mnemonic, "insertq") == 0))
3989 swap_2_operands (0, 1);
3990
29b0f896
AM		 3991 if (i.imm_operands)
3992 optimize_imm ();
3993
b300c311
L		 3994 /* Don't optimize displacement for movabs since it only takes 64bit
3995 displacement. */
3996 if (i.disp_operands
a501d77e 3997 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3998 && (flag_code != CODE_64BIT
3999 || strcmp (mnemonic, "movabs") != 0))
4000 optimize_disp ();
29b0f896
AM		 4001
4002 /* Next, we find a template that matches the given insn,
4003 making sure the overlap of the given operands types is consistent
4004 with the template operand types. */
252b5132 4005
83b16ac6 4006 if (!(t = match_template (mnem_suffix)))
29b0f896 4007 return;
252b5132 4008
7bab8ab5 4009 if (sse_check != check_none
81f8a913 4010 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4011 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4012 && (i.tm.cpu_flags.bitfield.cpusse
4013 || i.tm.cpu_flags.bitfield.cpusse2
4014 || i.tm.cpu_flags.bitfield.cpusse3
4015 || i.tm.cpu_flags.bitfield.cpussse3
4016 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4017 || i.tm.cpu_flags.bitfield.cpusse4_2
4018 || i.tm.cpu_flags.bitfield.cpupclmul
4019 || i.tm.cpu_flags.bitfield.cpuaes
4020 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4021 {
7bab8ab5 4022 (sse_check == check_warning
daf50ae7
L		 4023 ? as_warn
4024 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4025 }
4026
321fd21e
L		 4027 /* Zap movzx and movsx suffix. The suffix has been set from
4028 "word ptr" or "byte ptr" on the source operand in Intel syntax
4029 or extracted from mnemonic in AT&T syntax. But we'll use
4030 the destination register to choose the suffix for encoding. */
4031 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4032 {
321fd21e
L		 4033 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4034 there is no suffix, the default will be byte extension. */
4035 if (i.reg_operands != 2
4036 && !i.suffix
7ab9ffdd 4037 && intel_syntax)
321fd21e
L		 4038 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4039
4040 i.suffix = 0;
cd61ebfe 4041 }
24eab124 4042
40fb9820 4043 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4044 if (!add_prefix (FWAIT_OPCODE))
4045 return;
252b5132 4046
d5de92cf
L		 4047 /* Check if REP prefix is OK. */
4048 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4049 {
4050 as_bad (_("invalid instruction `%s' after `%s'"),
4051 i.tm.name, i.rep_prefix);
4052 return;
4053 }
4054
c1ba0266
L		 4055 /* Check for lock without a lockable instruction. Destination operand
4056 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4057 if (i.prefix[LOCK_PREFIX]
4058 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4059 || i.mem_operands == 0
4060 || (i.tm.base_opcode != 0x86
4061 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4062 {
4063 as_bad (_("expecting lockable instruction after `lock'"));
4064 return;
4065 }
4066
42164a71 4067 /* Check if HLE prefix is OK. */
165de32a 4068 if (i.hle_prefix && !check_hle ())
42164a71
L		 4069 return;
4070
7e8b059b
L		 4071 /* Check BND prefix. */
4072 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4073 as_bad (_("expecting valid branch instruction after `bnd'"));
4074
04ef582a 4075 /* Check NOTRACK prefix. */
9fef80d6
L		 4076 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4077 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4078
327e8c42
JB		 4079 if (i.tm.cpu_flags.bitfield.cpumpx)
4080 {
4081 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4082 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4083 else if (flag_code != CODE_16BIT
4084 ? i.prefix[ADDR_PREFIX]
4085 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4086 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4087 }
7e8b059b
L		 4088
4089 /* Insert BND prefix. */
4090 if (add_bnd_prefix
4091 && i.tm.opcode_modifier.bndprefixok
4092 && !i.prefix[BND_PREFIX])
4093 add_prefix (BND_PREFIX_OPCODE);
4094
29b0f896 4095 /* Check string instruction segment overrides. */
40fb9820 4096 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4097 {
4098 if (!check_string ())
5dd0794d 4099 return;
fc0763e6 4100 i.disp_operands = 0;
29b0f896 4101 }
5dd0794d 4102
b6f8c7c4
L		 4103 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4104 optimize_encoding ();
4105
29b0f896
AM		 4106 if (!process_suffix ())
4107 return;
e413e4e9 4108
bc0844ae
L		 4109 /* Update operand types. */
4110 for (j = 0; j < i.operands; j++)
4111 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4112
29b0f896
AM		 4113 /* Make still unresolved immediate matches conform to size of immediate
4114 given in i.suffix. */
4115 if (!finalize_imm ())
4116 return;
252b5132 4117
40fb9820 4118 if (i.types[0].bitfield.imm1)
29b0f896 4119 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4120
9afe6eb8
L		 4121 /* We only need to check those implicit registers for instructions
4122 with 3 operands or less. */
4123 if (i.operands <= 3)
4124 for (j = 0; j < i.operands; j++)
4125 if (i.types[j].bitfield.inoutportreg
4126 || i.types[j].bitfield.shiftcount
1b54b8d7 4127 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4128 i.reg_operands--;
40fb9820 4129
c0f3af97
L		 4130 /* ImmExt should be processed after SSE2AVX. */
4131 if (!i.tm.opcode_modifier.sse2avx
4132 && i.tm.opcode_modifier.immext)
65da13b5 4133 process_immext ();
252b5132 4134
29b0f896
AM		 4135 /* For insns with operands there are more diddles to do to the opcode. */
4136 if (i.operands)
4137 {
4138 if (!process_operands ())
4139 return;
4140 }
40fb9820 4141 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4142 {
4143 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4144 as_warn (_("translating to `%sp'"), i.tm.name);
4145 }
252b5132 4146
9e5e5283
L		 4147 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
4148 {
4149 if (flag_code == CODE_16BIT)
4150 {
4151 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4152 i.tm.name);
4153 return;
4154 }
c0f3af97 4155
9e5e5283
L		 4156 if (i.tm.opcode_modifier.vex)
4157 build_vex_prefix (t);
4158 else
4159 build_evex_prefix ();
4160 }
43234a1e 4161
5dd85c99
SP		 4162 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4163 instructions may define INT_OPCODE as well, so avoid this corner
4164 case for those instructions that use MODRM. */
4165 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4166 && !i.tm.opcode_modifier.modrm
4167 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4168 {
4169 i.tm.base_opcode = INT3_OPCODE;
4170 i.imm_operands = 0;
4171 }
252b5132 4172
40fb9820
L		 4173 if ((i.tm.opcode_modifier.jump
4174 || i.tm.opcode_modifier.jumpbyte
4175 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4176 && i.op[0].disps->X_op == O_constant)
4177 {
4178 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4179 the absolute address given by the constant. Since ix86 jumps and
4180 calls are pc relative, we need to generate a reloc. */
4181 i.op[0].disps->X_add_symbol = &abs_symbol;
4182 i.op[0].disps->X_op = O_symbol;
4183 }
252b5132 4184
40fb9820 4185 if (i.tm.opcode_modifier.rex64)
161a04f6 4186 i.rex |= REX_W;
252b5132 4187
29b0f896
AM		 4188 /* For 8 bit registers we need an empty rex prefix. Also if the
4189 instruction already has a prefix, we need to convert old
4190 registers to new ones. */
773f551c 4191
dc821c5f 4192 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4193 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4194 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4195 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4196 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4197 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4198 && i.rex != 0))
4199 {
4200 int x;
726c5dcd 4201
29b0f896
AM		 4202 i.rex |= REX_OPCODE;
4203 for (x = 0; x < 2; x++)
4204 {
4205 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4206 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4207 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4208 {
29b0f896
AM		 4209 /* In case it is "hi" register, give up. */
4210 if (i.op[x].regs->reg_num > 3)
a540244d 4211 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4212 "instruction requiring REX prefix."),
a540244d 4213 register_prefix, i.op[x].regs->reg_name);
773f551c 4214
29b0f896
AM		 4215 /* Otherwise it is equivalent to the extended register.
4216 Since the encoding doesn't change this is merely
4217 cosmetic cleanup for debug output. */
4218
4219 i.op[x].regs = i.op[x].regs + 8;
773f551c 4220 }
29b0f896
AM		 4221 }
4222 }
773f551c 4223
6b6b6807
L		 4224 if (i.rex == 0 && i.rex_encoding)
4225 {
4226 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4227 that uses legacy register. If it is "hi" register, don't add
4228 the REX_OPCODE byte. */
4229 int x;
4230 for (x = 0; x < 2; x++)
4231 if (i.types[x].bitfield.reg
4232 && i.types[x].bitfield.byte
4233 && (i.op[x].regs->reg_flags & RegRex64) == 0
4234 && i.op[x].regs->reg_num > 3)
4235 {
4236 i.rex_encoding = FALSE;
4237 break;
4238 }
4239
4240 if (i.rex_encoding)
4241 i.rex = REX_OPCODE;
4242 }
4243
7ab9ffdd 4244 if (i.rex != 0)
29b0f896
AM		 4245 add_prefix (REX_OPCODE | i.rex);
4246
4247 /* We are ready to output the insn. */
4248 output_insn ();
4249}
4250
4251static char *
e3bb37b5 4252parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4253{
4254 char *l = line;
4255 char *token_start = l;
4256 char *mnem_p;
5c6af06e 4257 int supported;
d3ce72d0 4258 const insn_template *t;
b6169b20 4259 char *dot_p = NULL;
29b0f896 4260
29b0f896
AM		 4261 while (1)
4262 {
4263 mnem_p = mnemonic;
4264 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4265 {
b6169b20
L		 4266 if (*mnem_p == '.')
4267 dot_p = mnem_p;
29b0f896
AM		 4268 mnem_p++;
4269 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4270 {
29b0f896
AM		 4271 as_bad (_("no such instruction: `%s'"), token_start);
4272 return NULL;
4273 }
4274 l++;
4275 }
4276 if (!is_space_char (*l)
4277 && *l != END_OF_INSN
e44823cf
JB		 4278 && (intel_syntax
4279 || (*l != PREFIX_SEPARATOR
4280 && *l != ',')))
29b0f896
AM		 4281 {
4282 as_bad (_("invalid character %s in mnemonic"),
4283 output_invalid (*l));
4284 return NULL;
4285 }
4286 if (token_start == l)
4287 {
e44823cf 4288 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4289 as_bad (_("expecting prefix; got nothing"));
4290 else
4291 as_bad (_("expecting mnemonic; got nothing"));
4292 return NULL;
4293 }
45288df1 4294
29b0f896 4295 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4296 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4297
29b0f896
AM		 4298 if (*l != END_OF_INSN
4299 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4300 && current_templates
40fb9820 4301 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4302 {
c6fb90c8 4303 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4304 {
4305 as_bad ((flag_code != CODE_64BIT
4306 ? _("`%s' is only supported in 64-bit mode")
4307 : _("`%s' is not supported in 64-bit mode")),
4308 current_templates->start->name);
4309 return NULL;
4310 }
29b0f896
AM		 4311 /* If we are in 16-bit mode, do not allow addr16 or data16.
4312 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4313 if ((current_templates->start->opcode_modifier.size16
4314 || current_templates->start->opcode_modifier.size32)
29b0f896 4315 && flag_code != CODE_64BIT
40fb9820 4316 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4317 ^ (flag_code == CODE_16BIT)))
4318 {
4319 as_bad (_("redundant %s prefix"),
4320 current_templates->start->name);
4321 return NULL;
45288df1 4322 }
86fa6981 4323 if (current_templates->start->opcode_length == 0)
29b0f896 4324 {
86fa6981
L		 4325 /* Handle pseudo prefixes. */
4326 switch (current_templates->start->base_opcode)
4327 {
4328 case 0x0:
4329 /* {disp8} */
4330 i.disp_encoding = disp_encoding_8bit;
4331 break;
4332 case 0x1:
4333 /* {disp32} */
4334 i.disp_encoding = disp_encoding_32bit;
4335 break;
4336 case 0x2:
4337 /* {load} */
4338 i.dir_encoding = dir_encoding_load;
4339 break;
4340 case 0x3:
4341 /* {store} */
4342 i.dir_encoding = dir_encoding_store;
4343 break;
4344 case 0x4:
4345 /* {vex2} */
4346 i.vec_encoding = vex_encoding_vex2;
4347 break;
4348 case 0x5:
4349 /* {vex3} */
4350 i.vec_encoding = vex_encoding_vex3;
4351 break;
4352 case 0x6:
4353 /* {evex} */
4354 i.vec_encoding = vex_encoding_evex;
4355 break;
6b6b6807
L		 4356 case 0x7:
4357 /* {rex} */
4358 i.rex_encoding = TRUE;
4359 break;
b6f8c7c4
L		 4360 case 0x8:
4361 /* {nooptimize} */
4362 i.no_optimize = TRUE;
4363 break;
86fa6981
L		 4364 default:
4365 abort ();
4366 }
4367 }
4368 else
4369 {
4370 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4371 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4372 {
4e9ac44a
L		 4373 case PREFIX_EXIST:
4374 return NULL;
4375 case PREFIX_DS:
d777820b 4376 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4377 i.notrack_prefix = current_templates->start->name;
4378 break;
4379 case PREFIX_REP:
4380 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4381 i.hle_prefix = current_templates->start->name;
4382 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4383 i.bnd_prefix = current_templates->start->name;
4384 else
4385 i.rep_prefix = current_templates->start->name;
4386 break;
4387 default:
4388 break;
86fa6981 4389 }
29b0f896
AM		 4390 }
4391 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4392 token_start = ++l;
4393 }
4394 else
4395 break;
4396 }
45288df1 4397
30a55f88 4398 if (!current_templates)
b6169b20 4399 {
f8a5c266
L		 4400 /* Check if we should swap operand or force 32bit displacement in
4401 encoding. */
30a55f88 4402 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4403 i.dir_encoding = dir_encoding_store;
8d63c93e 4404 else if (mnem_p - 3 == dot_p
a501d77e
L		 4405 && dot_p[1] == 'd'
4406 && dot_p[2] == '8')
4407 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4408 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4409 && dot_p[1] == 'd'
4410 && dot_p[2] == '3'
4411 && dot_p[3] == '2')
a501d77e 4412 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4413 else
4414 goto check_suffix;
4415 mnem_p = dot_p;
4416 *dot_p = '\0';
d3ce72d0 4417 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4418 }
4419
29b0f896
AM		 4420 if (!current_templates)
4421 {
b6169b20 4422check_suffix:
29b0f896
AM		 4423 /* See if we can get a match by trimming off a suffix. */
4424 switch (mnem_p[-1])
4425 {
4426 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4427 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4428 i.suffix = SHORT_MNEM_SUFFIX;
4429 else
1a0670f3 4430 /* Fall through. */
29b0f896
AM		 4431 case BYTE_MNEM_SUFFIX:
4432 case QWORD_MNEM_SUFFIX:
4433 i.suffix = mnem_p[-1];
4434 mnem_p[-1] = '\0';
d3ce72d0
NC		 4435 current_templates = (const templates *) hash_find (op_hash,
4436 mnemonic);
29b0f896
AM		 4437 break;
4438 case SHORT_MNEM_SUFFIX:
4439 case LONG_MNEM_SUFFIX:
4440 if (!intel_syntax)
4441 {
4442 i.suffix = mnem_p[-1];
4443 mnem_p[-1] = '\0';
d3ce72d0
NC		 4444 current_templates = (const templates *) hash_find (op_hash,
4445 mnemonic);
29b0f896
AM		 4446 }
4447 break;
252b5132 4448
29b0f896
AM		 4449 /* Intel Syntax. */
4450 case 'd':
4451 if (intel_syntax)
4452 {
9306ca4a 4453 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4454 i.suffix = SHORT_MNEM_SUFFIX;
4455 else
4456 i.suffix = LONG_MNEM_SUFFIX;
4457 mnem_p[-1] = '\0';
d3ce72d0
NC		 4458 current_templates = (const templates *) hash_find (op_hash,
4459 mnemonic);
29b0f896
AM		 4460 }
4461 break;
4462 }
4463 if (!current_templates)
4464 {
4465 as_bad (_("no such instruction: `%s'"), token_start);
4466 return NULL;
4467 }
4468 }
252b5132 4469
40fb9820
L		 4470 if (current_templates->start->opcode_modifier.jump
4471 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4472 {
4473 /* Check for a branch hint. We allow ",pt" and ",pn" for
4474 predict taken and predict not taken respectively.
4475 I'm not sure that branch hints actually do anything on loop
4476 and jcxz insns (JumpByte) for current Pentium4 chips. They
4477 may work in the future and it doesn't hurt to accept them
4478 now. */
4479 if (l[0] == ',' && l[1] == 'p')
4480 {
4481 if (l[2] == 't')
4482 {
4483 if (!add_prefix (DS_PREFIX_OPCODE))
4484 return NULL;
4485 l += 3;
4486 }
4487 else if (l[2] == 'n')
4488 {
4489 if (!add_prefix (CS_PREFIX_OPCODE))
4490 return NULL;
4491 l += 3;
4492 }
4493 }
4494 }
4495 /* Any other comma loses. */
4496 if (*l == ',')
4497 {
4498 as_bad (_("invalid character %s in mnemonic"),
4499 output_invalid (*l));
4500 return NULL;
4501 }
252b5132 4502
29b0f896 4503 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4504 supported = 0;
4505 for (t = current_templates->start; t < current_templates->end; ++t)
4506 {
c0f3af97
L		 4507 supported |= cpu_flags_match (t);
4508 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4509 goto skip;
5c6af06e 4510 }
3629bb00 4511
c0f3af97 4512 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4513 {
4514 as_bad (flag_code == CODE_64BIT
4515 ? _("`%s' is not supported in 64-bit mode")
4516 : _("`%s' is only supported in 64-bit mode"),
4517 current_templates->start->name);
4518 return NULL;
4519 }
c0f3af97 4520 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4521 {
3629bb00 4522 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4523 current_templates->start->name,
41aacd83 4524 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4525 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4526 return NULL;
29b0f896 4527 }
3629bb00
L		 4528
4529skip:
4530 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4531 && (flag_code != CODE_16BIT))
29b0f896
AM		 4532 {
4533 as_warn (_("use .code16 to ensure correct addressing mode"));
4534 }
252b5132 4535
29b0f896
AM		 4536 return l;
4537}
252b5132 4538
29b0f896 4539static char *
e3bb37b5 4540parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4541{
4542 char *token_start;
3138f287 4543
29b0f896
AM		 4544 /* 1 if operand is pending after ','. */
4545 unsigned int expecting_operand = 0;
252b5132 4546
29b0f896
AM		 4547 /* Non-zero if operand parens not balanced. */
4548 unsigned int paren_not_balanced;
4549
4550 while (*l != END_OF_INSN)
4551 {
4552 /* Skip optional white space before operand. */
4553 if (is_space_char (*l))
4554 ++l;
d02603dc 4555 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4556 {
4557 as_bad (_("invalid character %s before operand %d"),
4558 output_invalid (*l),
4559 i.operands + 1);
4560 return NULL;
4561 }
d02603dc 4562 token_start = l; /* After white space. */
29b0f896
AM		 4563 paren_not_balanced = 0;
4564 while (paren_not_balanced || *l != ',')
4565 {
4566 if (*l == END_OF_INSN)
4567 {
4568 if (paren_not_balanced)
4569 {
4570 if (!intel_syntax)
4571 as_bad (_("unbalanced parenthesis in operand %d."),
4572 i.operands + 1);
4573 else
4574 as_bad (_("unbalanced brackets in operand %d."),
4575 i.operands + 1);
4576 return NULL;
4577 }
4578 else
4579 break; /* we are done */
4580 }
d02603dc 4581 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4582 {
4583 as_bad (_("invalid character %s in operand %d"),
4584 output_invalid (*l),
4585 i.operands + 1);
4586 return NULL;
4587 }
4588 if (!intel_syntax)
4589 {
4590 if (*l == '(')
4591 ++paren_not_balanced;
4592 if (*l == ')')
4593 --paren_not_balanced;
4594 }
4595 else
4596 {
4597 if (*l == '[')
4598 ++paren_not_balanced;
4599 if (*l == ']')
4600 --paren_not_balanced;
4601 }
4602 l++;
4603 }
4604 if (l != token_start)
4605 { /* Yes, we've read in another operand. */
4606 unsigned int operand_ok;
4607 this_operand = i.operands++;
4608 if (i.operands > MAX_OPERANDS)
4609 {
4610 as_bad (_("spurious operands; (%d operands/instruction max)"),
4611 MAX_OPERANDS);
4612 return NULL;
4613 }
9d46ce34 4614 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4615 /* Now parse operand adding info to 'i' as we go along. */
4616 END_STRING_AND_SAVE (l);
4617
4618 if (intel_syntax)
4619 operand_ok =
4620 i386_intel_operand (token_start,
4621 intel_float_operand (mnemonic));
4622 else
a7619375 4623 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4624
4625 RESTORE_END_STRING (l);
4626 if (!operand_ok)
4627 return NULL;
4628 }
4629 else
4630 {
4631 if (expecting_operand)
4632 {
4633 expecting_operand_after_comma:
4634 as_bad (_("expecting operand after ','; got nothing"));
4635 return NULL;
4636 }
4637 if (*l == ',')
4638 {
4639 as_bad (_("expecting operand before ','; got nothing"));
4640 return NULL;
4641 }
4642 }
7f3f1ea2 4643
29b0f896
AM		 4644 /* Now *l must be either ',' or END_OF_INSN. */
4645 if (*l == ',')
4646 {
4647 if (*++l == END_OF_INSN)
4648 {
4649 /* Just skip it, if it's \n complain. */
4650 goto expecting_operand_after_comma;
4651 }
4652 expecting_operand = 1;
4653 }
4654 }
4655 return l;
4656}
7f3f1ea2 4657
050dfa73 4658static void
4d456e3d 4659swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4660{
4661 union i386_op temp_op;
40fb9820 4662 i386_operand_type temp_type;
050dfa73 4663 enum bfd_reloc_code_real temp_reloc;
4eed87de 4664
050dfa73
MM		 4665 temp_type = i.types[xchg2];
4666 i.types[xchg2] = i.types[xchg1];
4667 i.types[xchg1] = temp_type;
4668 temp_op = i.op[xchg2];
4669 i.op[xchg2] = i.op[xchg1];
4670 i.op[xchg1] = temp_op;
4671 temp_reloc = i.reloc[xchg2];
4672 i.reloc[xchg2] = i.reloc[xchg1];
4673 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4674
4675 if (i.mask)
4676 {
4677 if (i.mask->operand == xchg1)
4678 i.mask->operand = xchg2;
4679 else if (i.mask->operand == xchg2)
4680 i.mask->operand = xchg1;
4681 }
4682 if (i.broadcast)
4683 {
4684 if (i.broadcast->operand == xchg1)
4685 i.broadcast->operand = xchg2;
4686 else if (i.broadcast->operand == xchg2)
4687 i.broadcast->operand = xchg1;
4688 }
4689 if (i.rounding)
4690 {
4691 if (i.rounding->operand == xchg1)
4692 i.rounding->operand = xchg2;
4693 else if (i.rounding->operand == xchg2)
4694 i.rounding->operand = xchg1;
4695 }
050dfa73
MM		 4696}
4697
29b0f896 4698static void
e3bb37b5 4699swap_operands (void)
29b0f896 4700{
b7c61d9a 4701 switch (i.operands)
050dfa73 4702 {
c0f3af97 4703 case 5:
b7c61d9a 4704 case 4:
4d456e3d 4705 swap_2_operands (1, i.operands - 2);
1a0670f3 4706 /* Fall through. */
b7c61d9a
L		 4707 case 3:
4708 case 2:
4d456e3d 4709 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4710 break;
4711 default:
4712 abort ();
29b0f896 4713 }
29b0f896
AM		 4714
4715 if (i.mem_operands == 2)
4716 {
4717 const seg_entry *temp_seg;
4718 temp_seg = i.seg[0];
4719 i.seg[0] = i.seg[1];
4720 i.seg[1] = temp_seg;
4721 }
4722}
252b5132 4723
29b0f896
AM		 4724/* Try to ensure constant immediates are represented in the smallest
4725 opcode possible. */
4726static void
e3bb37b5 4727optimize_imm (void)
29b0f896
AM		 4728{
4729 char guess_suffix = 0;
4730 int op;
252b5132 4731
29b0f896
AM		 4732 if (i.suffix)
4733 guess_suffix = i.suffix;
4734 else if (i.reg_operands)
4735 {
4736 /* Figure out a suffix from the last register operand specified.
4737 We can't do this properly yet, ie. excluding InOutPortReg,
4738 but the following works for instructions with immediates.
4739 In any case, we can't set i.suffix yet. */
4740 for (op = i.operands; --op >= 0;)
dc821c5f 4741 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4742 {
40fb9820
L		 4743 guess_suffix = BYTE_MNEM_SUFFIX;
4744 break;
4745 }
dc821c5f 4746 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4747 {
40fb9820
L		 4748 guess_suffix = WORD_MNEM_SUFFIX;
4749 break;
4750 }
dc821c5f 4751 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4752 {
4753 guess_suffix = LONG_MNEM_SUFFIX;
4754 break;
4755 }
dc821c5f 4756 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4757 {
4758 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4759 break;
252b5132 4760 }
29b0f896
AM		 4761 }
4762 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4763 guess_suffix = WORD_MNEM_SUFFIX;
4764
4765 for (op = i.operands; --op >= 0;)
40fb9820 4766 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4767 {
4768 switch (i.op[op].imms->X_op)
252b5132 4769 {
29b0f896
AM		 4770 case O_constant:
4771 /* If a suffix is given, this operand may be shortened. */
4772 switch (guess_suffix)
252b5132 4773 {
29b0f896 4774 case LONG_MNEM_SUFFIX:
40fb9820
L		 4775 i.types[op].bitfield.imm32 = 1;
4776 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4777 break;
4778 case WORD_MNEM_SUFFIX:
40fb9820
L		 4779 i.types[op].bitfield.imm16 = 1;
4780 i.types[op].bitfield.imm32 = 1;
4781 i.types[op].bitfield.imm32s = 1;
4782 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4783 break;
4784 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4785 i.types[op].bitfield.imm8 = 1;
4786 i.types[op].bitfield.imm8s = 1;
4787 i.types[op].bitfield.imm16 = 1;
4788 i.types[op].bitfield.imm32 = 1;
4789 i.types[op].bitfield.imm32s = 1;
4790 i.types[op].bitfield.imm64 = 1;
29b0f896 4791 break;
252b5132 4792 }
252b5132 4793
29b0f896
AM		 4794 /* If this operand is at most 16 bits, convert it
4795 to a signed 16 bit number before trying to see
4796 whether it will fit in an even smaller size.
4797 This allows a 16-bit operand such as $0xffe0 to
4798 be recognised as within Imm8S range. */
40fb9820 4799 if ((i.types[op].bitfield.imm16)
29b0f896 4800 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4801 {
29b0f896
AM		 4802 i.op[op].imms->X_add_number =
4803 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4804 }
a28def75
L		 4805#ifdef BFD64
4806 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4807 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4808 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4809 == 0))
4810 {
4811 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4812 ^ ((offsetT) 1 << 31))
4813 - ((offsetT) 1 << 31));
4814 }
a28def75 4815#endif
40fb9820 4816 i.types[op]
c6fb90c8
L		 4817 = operand_type_or (i.types[op],
4818 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4819
29b0f896
AM		 4820 /* We must avoid matching of Imm32 templates when 64bit
4821 only immediate is available. */
4822 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4823 i.types[op].bitfield.imm32 = 0;
29b0f896 4824 break;
252b5132 4825
29b0f896
AM		 4826 case O_absent:
4827 case O_register:
4828 abort ();
4829
4830 /* Symbols and expressions. */
4831 default:
9cd96992
JB		 4832 /* Convert symbolic operand to proper sizes for matching, but don't
4833 prevent matching a set of insns that only supports sizes other
4834 than those matching the insn suffix. */
4835 {
40fb9820 4836 i386_operand_type mask, allowed;
d3ce72d0 4837 const insn_template *t;
9cd96992 4838
0dfbf9d7
L		 4839 operand_type_set (&mask, 0);
4840 operand_type_set (&allowed, 0);
40fb9820 4841
4eed87de
AM		 4842 for (t = current_templates->start;
4843 t < current_templates->end;
4844 ++t)
c6fb90c8
L		 4845 allowed = operand_type_or (allowed,
4846 t->operand_types[op]);
9cd96992
JB		 4847 switch (guess_suffix)
4848 {
4849 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4850 mask.bitfield.imm64 = 1;
4851 mask.bitfield.imm32s = 1;
9cd96992
JB		 4852 break;
4853 case LONG_MNEM_SUFFIX:
40fb9820 4854 mask.bitfield.imm32 = 1;
9cd96992
JB		 4855 break;
4856 case WORD_MNEM_SUFFIX:
40fb9820 4857 mask.bitfield.imm16 = 1;
9cd96992
JB		 4858 break;
4859 case BYTE_MNEM_SUFFIX:
40fb9820 4860 mask.bitfield.imm8 = 1;
9cd96992
JB		 4861 break;
4862 default:
9cd96992
JB		 4863 break;
4864 }
c6fb90c8 4865 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4866 if (!operand_type_all_zero (&allowed))
c6fb90c8 4867 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4868 }
29b0f896 4869 break;
252b5132 4870 }
29b0f896
AM		 4871 }
4872}
47926f60 4873
29b0f896
AM		 4874/* Try to use the smallest displacement type too. */
4875static void
e3bb37b5 4876optimize_disp (void)
29b0f896
AM		 4877{
4878 int op;
3e73aa7c 4879
29b0f896 4880 for (op = i.operands; --op >= 0;)
40fb9820 4881 if (operand_type_check (i.types[op], disp))
252b5132 4882 {
b300c311 4883 if (i.op[op].disps->X_op == O_constant)
252b5132 4884 {
91d6fa6a 4885 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4886
40fb9820 4887 if (i.types[op].bitfield.disp16
91d6fa6a 4888 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4889 {
4890 /* If this operand is at most 16 bits, convert
4891 to a signed 16 bit number and don't use 64bit
4892 displacement. */
91d6fa6a 4893 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4894 i.types[op].bitfield.disp64 = 0;
b300c311 4895 }
a28def75
L		 4896#ifdef BFD64
4897 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4898 if (i.types[op].bitfield.disp32
91d6fa6a 4899 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4900 {
4901 /* If this operand is at most 32 bits, convert
4902 to a signed 32 bit number and don't use 64bit
4903 displacement. */
91d6fa6a
NC		 4904 op_disp &= (((offsetT) 2 << 31) - 1);
4905 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4906 i.types[op].bitfield.disp64 = 0;
b300c311 4907 }
a28def75 4908#endif
91d6fa6a 4909 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4910 {
40fb9820
L		 4911 i.types[op].bitfield.disp8 = 0;
4912 i.types[op].bitfield.disp16 = 0;
4913 i.types[op].bitfield.disp32 = 0;
4914 i.types[op].bitfield.disp32s = 0;
4915 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4916 i.op[op].disps = 0;
4917 i.disp_operands--;
4918 }
4919 else if (flag_code == CODE_64BIT)
4920 {
91d6fa6a 4921 if (fits_in_signed_long (op_disp))
28a9d8f5 4922 {
40fb9820
L		 4923 i.types[op].bitfield.disp64 = 0;
4924 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4925 }
0e1147d9 4926 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4927 && fits_in_unsigned_long (op_disp))
40fb9820 4928 i.types[op].bitfield.disp32 = 1;
b300c311 4929 }
40fb9820
L		 4930 if ((i.types[op].bitfield.disp32
4931 || i.types[op].bitfield.disp32s
4932 || i.types[op].bitfield.disp16)
b5014f7a 4933 && fits_in_disp8 (op_disp))
40fb9820 4934 i.types[op].bitfield.disp8 = 1;
252b5132 4935 }
67a4f2b7
AO		 4936 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4937 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4938 {
4939 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4940 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4941 i.types[op].bitfield.disp8 = 0;
4942 i.types[op].bitfield.disp16 = 0;
4943 i.types[op].bitfield.disp32 = 0;
4944 i.types[op].bitfield.disp32s = 0;
4945 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4946 }
4947 else
b300c311 4948 /* We only support 64bit displacement on constants. */
40fb9820 4949 i.types[op].bitfield.disp64 = 0;
252b5132 4950 }
29b0f896
AM		 4951}
4952
6c30d220
L		 4953/* Check if operands are valid for the instruction. */
4954
4955static int
4956check_VecOperands (const insn_template *t)
4957{
43234a1e
L		 4958 unsigned int op;
4959
6c30d220
L		 4960 /* Without VSIB byte, we can't have a vector register for index. */
4961 if (!t->opcode_modifier.vecsib
4962 && i.index_reg
1b54b8d7
JB		 4963 && (i.index_reg->reg_type.bitfield.xmmword
4964 || i.index_reg->reg_type.bitfield.ymmword
4965 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4966 {
4967 i.error = unsupported_vector_index_register;
4968 return 1;
4969 }
4970
ad8ecc81
MZ		 4971 /* Check if default mask is allowed. */
4972 if (t->opcode_modifier.nodefmask
4973 && (!i.mask || i.mask->mask->reg_num == 0))
4974 {
4975 i.error = no_default_mask;
4976 return 1;
4977 }
4978
7bab8ab5
JB		 4979 /* For VSIB byte, we need a vector register for index, and all vector
4980 registers must be distinct. */
4981 if (t->opcode_modifier.vecsib)
4982 {
4983 if (!i.index_reg
6c30d220 4984 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4985 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4986 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4987 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4988 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4989 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4990 {
4991 i.error = invalid_vsib_address;
4992 return 1;
4993 }
4994
43234a1e
L		 4995 gas_assert (i.reg_operands == 2 || i.mask);
4996 if (i.reg_operands == 2 && !i.mask)
4997 {
1b54b8d7
JB		 4998 gas_assert (i.types[0].bitfield.regsimd);
4999 gas_assert (i.types[0].bitfield.xmmword
5000 || i.types[0].bitfield.ymmword);
5001 gas_assert (i.types[2].bitfield.regsimd);
5002 gas_assert (i.types[2].bitfield.xmmword
5003 || i.types[2].bitfield.ymmword);
43234a1e
L		 5004 if (operand_check == check_none)
5005 return 0;
5006 if (register_number (i.op[0].regs)
5007 != register_number (i.index_reg)
5008 && register_number (i.op[2].regs)
5009 != register_number (i.index_reg)
5010 && register_number (i.op[0].regs)
5011 != register_number (i.op[2].regs))
5012 return 0;
5013 if (operand_check == check_error)
5014 {
5015 i.error = invalid_vector_register_set;
5016 return 1;
5017 }
5018 as_warn (_("mask, index, and destination registers should be distinct"));
5019 }
8444f82a
MZ		 5020 else if (i.reg_operands == 1 && i.mask)
5021 {
1b54b8d7
JB		 5022 if (i.types[1].bitfield.regsimd
5023 && (i.types[1].bitfield.xmmword
5024 || i.types[1].bitfield.ymmword
5025 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5026 && (register_number (i.op[1].regs)
5027 == register_number (i.index_reg)))
5028 {
5029 if (operand_check == check_error)
5030 {
5031 i.error = invalid_vector_register_set;
5032 return 1;
5033 }
5034 if (operand_check != check_none)
5035 as_warn (_("index and destination registers should be distinct"));
5036 }
5037 }
43234a1e 5038 }
7bab8ab5 5039
43234a1e
L		 5040 /* Check if broadcast is supported by the instruction and is applied
5041 to the memory operand. */
5042 if (i.broadcast)
5043 {
5044 int broadcasted_opnd_size;
5045
5046 /* Check if specified broadcast is supported in this instruction,
5047 and it's applied to memory operand of DWORD or QWORD type,
5048 depending on VecESize. */
5049 if (i.broadcast->type != t->opcode_modifier.broadcast
5050 || !i.types[i.broadcast->operand].bitfield.mem
5051 || (t->opcode_modifier.vecesize == 0
5052 && !i.types[i.broadcast->operand].bitfield.dword
5053 && !i.types[i.broadcast->operand].bitfield.unspecified)
5054 || (t->opcode_modifier.vecesize == 1
5055 && !i.types[i.broadcast->operand].bitfield.qword
5056 && !i.types[i.broadcast->operand].bitfield.unspecified))
5057 goto bad_broadcast;
5058
5059 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
5060 if (i.broadcast->type == BROADCAST_1TO16)
5061 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
5062 else if (i.broadcast->type == BROADCAST_1TO8)
5063 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 5064 else if (i.broadcast->type == BROADCAST_1TO4)
5065 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
5066 else if (i.broadcast->type == BROADCAST_1TO2)
5067 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 5068 else
5069 goto bad_broadcast;
5070
5071 if ((broadcasted_opnd_size == 256
5072 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
5073 || (broadcasted_opnd_size == 512
5074 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
5075 {
5076 bad_broadcast:
5077 i.error = unsupported_broadcast;
5078 return 1;
5079 }
5080 }
5081 /* If broadcast is supported in this instruction, we need to check if
5082 operand of one-element size isn't specified without broadcast. */
5083 else if (t->opcode_modifier.broadcast && i.mem_operands)
5084 {
5085 /* Find memory operand. */
5086 for (op = 0; op < i.operands; op++)
5087 if (operand_type_check (i.types[op], anymem))
5088 break;
5089 gas_assert (op < i.operands);
5090 /* Check size of the memory operand. */
5091 if ((t->opcode_modifier.vecesize == 0
5092 && i.types[op].bitfield.dword)
5093 || (t->opcode_modifier.vecesize == 1
5094 && i.types[op].bitfield.qword))
5095 {
5096 i.error = broadcast_needed;
5097 return 1;
5098 }
5099 }
5100
5101 /* Check if requested masking is supported. */
5102 if (i.mask
5103 && (!t->opcode_modifier.masking
5104 || (i.mask->zeroing
5105 && t->opcode_modifier.masking == MERGING_MASKING)))
5106 {
5107 i.error = unsupported_masking;
5108 return 1;
5109 }
5110
5111 /* Check if masking is applied to dest operand. */
5112 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5113 {
5114 i.error = mask_not_on_destination;
5115 return 1;
5116 }
5117
43234a1e
L		 5118 /* Check RC/SAE. */
5119 if (i.rounding)
5120 {
5121 if ((i.rounding->type != saeonly
5122 && !t->opcode_modifier.staticrounding)
5123 || (i.rounding->type == saeonly
5124 && (t->opcode_modifier.staticrounding
5125 || !t->opcode_modifier.sae)))
5126 {
5127 i.error = unsupported_rc_sae;
5128 return 1;
5129 }
5130 /* If the instruction has several immediate operands and one of
5131 them is rounding, the rounding operand should be the last
5132 immediate operand. */
5133 if (i.imm_operands > 1
5134 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5135 {
43234a1e 5136 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5137 return 1;
5138 }
6c30d220
L		 5139 }
5140
43234a1e 5141 /* Check vector Disp8 operand. */
b5014f7a
JB		 5142 if (t->opcode_modifier.disp8memshift
5143 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5144 {
5145 if (i.broadcast)
5146 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
5147 else
5148 i.memshift = t->opcode_modifier.disp8memshift;
5149
5150 for (op = 0; op < i.operands; op++)
5151 if (operand_type_check (i.types[op], disp)
5152 && i.op[op].disps->X_op == O_constant)
5153 {
b5014f7a 5154 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5155 {
b5014f7a
JB		 5156 i.types[op].bitfield.disp8 = 1;
5157 return 0;
43234a1e 5158 }
b5014f7a 5159 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5160 }
5161 }
b5014f7a
JB		 5162
5163 i.memshift = 0;
43234a1e 5164
6c30d220
L		 5165 return 0;
5166}
5167
43f3e2ee 5168/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5169 operand types. */
5170
5171static int
5172VEX_check_operands (const insn_template *t)
5173{
86fa6981 5174 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5175 {
86fa6981
L		 5176 /* This instruction must be encoded with EVEX prefix. */
5177 if (!t->opcode_modifier.evex)
5178 {
5179 i.error = unsupported;
5180 return 1;
5181 }
5182 return 0;
43234a1e
L		 5183 }
5184
a683cc34 5185 if (!t->opcode_modifier.vex)
86fa6981
L		 5186 {
5187 /* This instruction template doesn't have VEX prefix. */
5188 if (i.vec_encoding != vex_encoding_default)
5189 {
5190 i.error = unsupported;
5191 return 1;
5192 }
5193 return 0;
5194 }
a683cc34
SP		 5195
5196 /* Only check VEX_Imm4, which must be the first operand. */
5197 if (t->operand_types[0].bitfield.vec_imm4)
5198 {
5199 if (i.op[0].imms->X_op != O_constant
5200 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5201 {
a65babc9 5202 i.error = bad_imm4;
891edac4
L		 5203 return 1;
5204 }
a683cc34
SP		 5205
5206 /* Turn off Imm8 so that update_imm won't complain. */
5207 i.types[0] = vec_imm4;
5208 }
5209
5210 return 0;
5211}
5212
d3ce72d0 5213static const insn_template *
83b16ac6 5214match_template (char mnem_suffix)
29b0f896
AM		 5215{
5216 /* Points to template once we've found it. */
d3ce72d0 5217 const insn_template *t;
40fb9820 5218 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5219 i386_operand_type overlap4;
29b0f896 5220 unsigned int found_reverse_match;
83b16ac6 5221 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5222 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5223 int addr_prefix_disp;
a5c311ca 5224 unsigned int j;
3629bb00 5225 unsigned int found_cpu_match;
45664ddb 5226 unsigned int check_register;
5614d22c 5227 enum i386_error specific_error = 0;
29b0f896 5228
c0f3af97
L		 5229#if MAX_OPERANDS != 5
5230# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5231#endif
5232
29b0f896 5233 found_reverse_match = 0;
539e75ad 5234 addr_prefix_disp = -1;
40fb9820
L		 5235
5236 memset (&suffix_check, 0, sizeof (suffix_check));
5237 if (i.suffix == BYTE_MNEM_SUFFIX)
5238 suffix_check.no_bsuf = 1;
5239 else if (i.suffix == WORD_MNEM_SUFFIX)
5240 suffix_check.no_wsuf = 1;
5241 else if (i.suffix == SHORT_MNEM_SUFFIX)
5242 suffix_check.no_ssuf = 1;
5243 else if (i.suffix == LONG_MNEM_SUFFIX)
5244 suffix_check.no_lsuf = 1;
5245 else if (i.suffix == QWORD_MNEM_SUFFIX)
5246 suffix_check.no_qsuf = 1;
5247 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5248 suffix_check.no_ldsuf = 1;
29b0f896 5249
83b16ac6
JB		 5250 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5251 if (intel_syntax)
5252 {
5253 switch (mnem_suffix)
5254 {
5255 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5256 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5257 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5258 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5259 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5260 }
5261 }
5262
01559ecc
L		 5263 /* Must have right number of operands. */
5264 i.error = number_of_operands_mismatch;
5265
45aa61fe 5266 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5267 {
539e75ad
L		 5268 addr_prefix_disp = -1;
5269
29b0f896
AM		 5270 if (i.operands != t->operands)
5271 continue;
5272
50aecf8c 5273 /* Check processor support. */
a65babc9 5274 i.error = unsupported;
c0f3af97
L		 5275 found_cpu_match = (cpu_flags_match (t)
5276 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5277 if (!found_cpu_match)
5278 continue;
5279
e1d4d893 5280 /* Check old gcc support. */
a65babc9 5281 i.error = old_gcc_only;
e1d4d893
L		 5282 if (!old_gcc && t->opcode_modifier.oldgcc)
5283 continue;
5284
5285 /* Check AT&T mnemonic. */
a65babc9 5286 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5287 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5288 continue;
5289
e92bae62 5290 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5291 i.error = unsupported_syntax;
5c07affc 5292 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5293 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5294 || (intel64 && t->opcode_modifier.amd64)
5295 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5296 continue;
5297
20592a94 5298 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5299 i.error = invalid_instruction_suffix;
567e4e96
L		 5300 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5301 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5302 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5303 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5304 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5305 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5306 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5307 continue;
83b16ac6
JB		 5308 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5309 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5310 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5311 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5312 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5313 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5314 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5315 continue;
29b0f896 5316
5c07affc 5317 if (!operand_size_match (t))
7d5e4556 5318 continue;
539e75ad 5319
5c07affc
L		 5320 for (j = 0; j < MAX_OPERANDS; j++)
5321 operand_types[j] = t->operand_types[j];
5322
45aa61fe
AM		 5323 /* In general, don't allow 64-bit operands in 32-bit mode. */
5324 if (i.suffix == QWORD_MNEM_SUFFIX
5325 && flag_code != CODE_64BIT
5326 && (intel_syntax
40fb9820 5327 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5328 && !intel_float_operand (t->name))
5329 : intel_float_operand (t->name) != 2)
40fb9820 5330 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5331 && !operand_types[0].bitfield.regsimd)
40fb9820 5332 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5333 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5334 && (t->base_opcode != 0x0fc7
5335 || t->extension_opcode != 1 /* cmpxchg8b */))
5336 continue;
5337
192dc9c6
JB		 5338 /* In general, don't allow 32-bit operands on pre-386. */
5339 else if (i.suffix == LONG_MNEM_SUFFIX
5340 && !cpu_arch_flags.bitfield.cpui386
5341 && (intel_syntax
5342 ? (!t->opcode_modifier.ignoresize
5343 && !intel_float_operand (t->name))
5344 : intel_float_operand (t->name) != 2)
5345 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5346 && !operand_types[0].bitfield.regsimd)
192dc9c6 5347 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5348 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5349 continue;
5350
29b0f896 5351 /* Do not verify operands when there are none. */
50aecf8c 5352 else
29b0f896 5353 {
c6fb90c8 5354 if (!t->operands)
2dbab7d5
L		 5355 /* We've found a match; break out of loop. */
5356 break;
29b0f896 5357 }
252b5132 5358
539e75ad
L		 5359 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5360 into Disp32/Disp16/Disp32 operand. */
5361 if (i.prefix[ADDR_PREFIX] != 0)
5362 {
40fb9820 5363 /* There should be only one Disp operand. */
539e75ad
L		 5364 switch (flag_code)
5365 {
5366 case CODE_16BIT:
40fb9820
L		 5367 for (j = 0; j < MAX_OPERANDS; j++)
5368 {
5369 if (operand_types[j].bitfield.disp16)
5370 {
5371 addr_prefix_disp = j;
5372 operand_types[j].bitfield.disp32 = 1;
5373 operand_types[j].bitfield.disp16 = 0;
5374 break;
5375 }
5376 }
539e75ad
L		 5377 break;
5378 case CODE_32BIT:
40fb9820
L		 5379 for (j = 0; j < MAX_OPERANDS; j++)
5380 {
5381 if (operand_types[j].bitfield.disp32)
5382 {
5383 addr_prefix_disp = j;
5384 operand_types[j].bitfield.disp32 = 0;
5385 operand_types[j].bitfield.disp16 = 1;
5386 break;
5387 }
5388 }
539e75ad
L		 5389 break;
5390 case CODE_64BIT:
40fb9820
L		 5391 for (j = 0; j < MAX_OPERANDS; j++)
5392 {
5393 if (operand_types[j].bitfield.disp64)
5394 {
5395 addr_prefix_disp = j;
5396 operand_types[j].bitfield.disp64 = 0;
5397 operand_types[j].bitfield.disp32 = 1;
5398 break;
5399 }
5400 }
539e75ad
L		 5401 break;
5402 }
539e75ad
L		 5403 }
5404
02a86693
L		 5405 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5406 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5407 continue;
5408
56ffb741
L		 5409 /* We check register size if needed. */
5410 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5411 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5412 switch (t->operands)
5413 {
5414 case 1:
40fb9820 5415 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5416 continue;
5417 break;
5418 case 2:
33eaf5de 5419 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5420 only in 32bit mode and we can use opcode 0x90. In 64bit
5421 mode, we can't use 0x90 for xchg %eax, %eax since it should
5422 zero-extend %eax to %rax. */
5423 if (flag_code == CODE_64BIT
5424 && t->base_opcode == 0x90
0dfbf9d7
L		 5425 && operand_type_equal (&i.types [0], &acc32)
5426 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5427 continue;
86fa6981
L		 5428 /* If we want store form, we reverse direction of operands. */
5429 if (i.dir_encoding == dir_encoding_store
5430 && t->opcode_modifier.d)
5431 goto check_reverse;
1a0670f3 5432 /* Fall through. */
b6169b20 5433
29b0f896 5434 case 3:
86fa6981
L		 5435 /* If we want store form, we skip the current load. */
5436 if (i.dir_encoding == dir_encoding_store
5437 && i.mem_operands == 0
5438 && t->opcode_modifier.load)
fa99fab2 5439 continue;
1a0670f3 5440 /* Fall through. */
f48ff2ae 5441 case 4:
c0f3af97 5442 case 5:
c6fb90c8 5443 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5444 if (!operand_type_match (overlap0, i.types[0])
5445 || !operand_type_match (overlap1, i.types[1])
45664ddb 5446 || (check_register
dc821c5f 5447 && !operand_type_register_match (i.types[0],
40fb9820 5448 operand_types[0],
dc821c5f 5449 i.types[1],
40fb9820 5450 operand_types[1])))
29b0f896
AM		 5451 {
5452 /* Check if other direction is valid ... */
38e314eb 5453 if (!t->opcode_modifier.d)
29b0f896
AM		 5454 continue;
5455
b6169b20 5456check_reverse:
29b0f896 5457 /* Try reversing direction of operands. */
c6fb90c8
L		 5458 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5459 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5460 if (!operand_type_match (overlap0, i.types[0])
5461 || !operand_type_match (overlap1, i.types[1])
45664ddb 5462 || (check_register
dc821c5f 5463 && !operand_type_register_match (i.types[0],
45664ddb 5464 operand_types[1],
45664ddb
L		 5465 i.types[1],
5466 operand_types[0])))
29b0f896
AM		 5467 {
5468 /* Does not match either direction. */
5469 continue;
5470 }
38e314eb 5471 /* found_reverse_match holds which of D or FloatR
29b0f896 5472 we've found. */
38e314eb
JB		 5473 if (!t->opcode_modifier.d)
5474 found_reverse_match = 0;
5475 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5476 found_reverse_match = Opcode_FloatD;
5477 else
38e314eb 5478 found_reverse_match = Opcode_D;
40fb9820 5479 if (t->opcode_modifier.floatr)
8a2ed489 5480 found_reverse_match |= Opcode_FloatR;
29b0f896 5481 }
f48ff2ae 5482 else
29b0f896 5483 {
f48ff2ae 5484 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5485 switch (t->operands)
5486 {
c0f3af97
L		 5487 case 5:
5488 overlap4 = operand_type_and (i.types[4],
5489 operand_types[4]);
1a0670f3 5490 /* Fall through. */
d1cbb4db 5491 case 4:
c6fb90c8
L		 5492 overlap3 = operand_type_and (i.types[3],
5493 operand_types[3]);
1a0670f3 5494 /* Fall through. */
d1cbb4db 5495 case 3:
c6fb90c8
L		 5496 overlap2 = operand_type_and (i.types[2],
5497 operand_types[2]);
d1cbb4db
L		 5498 break;
5499 }
29b0f896 5500
f48ff2ae
L		 5501 switch (t->operands)
5502 {
c0f3af97
L		 5503 case 5:
5504 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5505 || !operand_type_register_match (i.types[3],
c0f3af97 5506 operand_types[3],
c0f3af97
L		 5507 i.types[4],
5508 operand_types[4]))
5509 continue;
1a0670f3 5510 /* Fall through. */
f48ff2ae 5511 case 4:
40fb9820 5512 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5513 || (check_register
dc821c5f 5514 && !operand_type_register_match (i.types[2],
45664ddb 5515 operand_types[2],
45664ddb
L		 5516 i.types[3],
5517 operand_types[3])))
f48ff2ae 5518 continue;
1a0670f3 5519 /* Fall through. */
f48ff2ae
L		 5520 case 3:
5521 /* Here we make use of the fact that there are no
5522 reverse match 3 operand instructions, and all 3
5523 operand instructions only need to be checked for
5524 register consistency between operands 2 and 3. */
40fb9820 5525 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5526 || (check_register
dc821c5f 5527 && !operand_type_register_match (i.types[1],
45664ddb 5528 operand_types[1],
45664ddb
L		 5529 i.types[2],
5530 operand_types[2])))
f48ff2ae
L		 5531 continue;
5532 break;
5533 }
29b0f896 5534 }
f48ff2ae 5535 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5536 slip through to break. */
5537 }
3629bb00 5538 if (!found_cpu_match)
29b0f896
AM		 5539 {
5540 found_reverse_match = 0;
5541 continue;
5542 }
c0f3af97 5543
5614d22c
JB		 5544 /* Check if vector and VEX operands are valid. */
5545 if (check_VecOperands (t) || VEX_check_operands (t))
5546 {
5547 specific_error = i.error;
5548 continue;
5549 }
a683cc34 5550
29b0f896
AM		 5551 /* We've found a match; break out of loop. */
5552 break;
5553 }
5554
5555 if (t == current_templates->end)
5556 {
5557 /* We found no match. */
a65babc9 5558 const char *err_msg;
5614d22c 5559 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5560 {
5561 default:
5562 abort ();
86e026a4 5563 case operand_size_mismatch:
a65babc9
L		 5564 err_msg = _("operand size mismatch");
5565 break;
5566 case operand_type_mismatch:
5567 err_msg = _("operand type mismatch");
5568 break;
5569 case register_type_mismatch:
5570 err_msg = _("register type mismatch");
5571 break;
5572 case number_of_operands_mismatch:
5573 err_msg = _("number of operands mismatch");
5574 break;
5575 case invalid_instruction_suffix:
5576 err_msg = _("invalid instruction suffix");
5577 break;
5578 case bad_imm4:
4a2608e3 5579 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5580 break;
5581 case old_gcc_only:
5582 err_msg = _("only supported with old gcc");
5583 break;
5584 case unsupported_with_intel_mnemonic:
5585 err_msg = _("unsupported with Intel mnemonic");
5586 break;
5587 case unsupported_syntax:
5588 err_msg = _("unsupported syntax");
5589 break;
5590 case unsupported:
35262a23 5591 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5592 current_templates->start->name);
5593 return NULL;
6c30d220
L		 5594 case invalid_vsib_address:
5595 err_msg = _("invalid VSIB address");
5596 break;
7bab8ab5
JB		 5597 case invalid_vector_register_set:
5598 err_msg = _("mask, index, and destination registers must be distinct");
5599 break;
6c30d220
L		 5600 case unsupported_vector_index_register:
5601 err_msg = _("unsupported vector index register");
5602 break;
43234a1e
L		 5603 case unsupported_broadcast:
5604 err_msg = _("unsupported broadcast");
5605 break;
5606 case broadcast_not_on_src_operand:
5607 err_msg = _("broadcast not on source memory operand");
5608 break;
5609 case broadcast_needed:
5610 err_msg = _("broadcast is needed for operand of such type");
5611 break;
5612 case unsupported_masking:
5613 err_msg = _("unsupported masking");
5614 break;
5615 case mask_not_on_destination:
5616 err_msg = _("mask not on destination operand");
5617 break;
5618 case no_default_mask:
5619 err_msg = _("default mask isn't allowed");
5620 break;
5621 case unsupported_rc_sae:
5622 err_msg = _("unsupported static rounding/sae");
5623 break;
5624 case rc_sae_operand_not_last_imm:
5625 if (intel_syntax)
5626 err_msg = _("RC/SAE operand must precede immediate operands");
5627 else
5628 err_msg = _("RC/SAE operand must follow immediate operands");
5629 break;
5630 case invalid_register_operand:
5631 err_msg = _("invalid register operand");
5632 break;
a65babc9
L		 5633 }
5634 as_bad (_("%s for `%s'"), err_msg,
891edac4 5635 current_templates->start->name);
fa99fab2 5636 return NULL;
29b0f896 5637 }
252b5132 5638
29b0f896
AM		 5639 if (!quiet_warnings)
5640 {
5641 if (!intel_syntax
40fb9820
L		 5642 && (i.types[0].bitfield.jumpabsolute
5643 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5644 {
5645 as_warn (_("indirect %s without `*'"), t->name);
5646 }
5647
40fb9820
L		 5648 if (t->opcode_modifier.isprefix
5649 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5650 {
5651 /* Warn them that a data or address size prefix doesn't
5652 affect assembly of the next line of code. */
5653 as_warn (_("stand-alone `%s' prefix"), t->name);
5654 }
5655 }
5656
5657 /* Copy the template we found. */
5658 i.tm = *t;
539e75ad
L		 5659
5660 if (addr_prefix_disp != -1)
5661 i.tm.operand_types[addr_prefix_disp]
5662 = operand_types[addr_prefix_disp];
5663
29b0f896
AM		 5664 if (found_reverse_match)
5665 {
5666 /* If we found a reverse match we must alter the opcode
5667 direction bit. found_reverse_match holds bits to change
5668 (different for int & float insns). */
5669
5670 i.tm.base_opcode ^= found_reverse_match;
5671
539e75ad
L		 5672 i.tm.operand_types[0] = operand_types[1];
5673 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5674 }
5675
fa99fab2 5676 return t;
29b0f896
AM		 5677}
5678
5679static int
e3bb37b5 5680check_string (void)
29b0f896 5681{
40fb9820
L		 5682 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5683 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5684 {
5685 if (i.seg[0] != NULL && i.seg[0] != &es)
5686 {
a87af027 5687 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5688 i.tm.name,
a87af027
JB		 5689 mem_op + 1,
5690 register_prefix);
29b0f896
AM		 5691 return 0;
5692 }
5693 /* There's only ever one segment override allowed per instruction.
5694 This instruction possibly has a legal segment override on the
5695 second operand, so copy the segment to where non-string
5696 instructions store it, allowing common code. */
5697 i.seg[0] = i.seg[1];
5698 }
40fb9820 5699 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5700 {
5701 if (i.seg[1] != NULL && i.seg[1] != &es)
5702 {
a87af027 5703 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5704 i.tm.name,
a87af027
JB		 5705 mem_op + 2,
5706 register_prefix);
29b0f896
AM		 5707 return 0;
5708 }
5709 }
5710 return 1;
5711}
5712
5713static int
543613e9 5714process_suffix (void)
29b0f896
AM		 5715{
5716 /* If matched instruction specifies an explicit instruction mnemonic
5717 suffix, use it. */
40fb9820
L		 5718 if (i.tm.opcode_modifier.size16)
5719 i.suffix = WORD_MNEM_SUFFIX;
5720 else if (i.tm.opcode_modifier.size32)
5721 i.suffix = LONG_MNEM_SUFFIX;
5722 else if (i.tm.opcode_modifier.size64)
5723 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5724 else if (i.reg_operands)
5725 {
5726 /* If there's no instruction mnemonic suffix we try to invent one
5727 based on register operands. */
5728 if (!i.suffix)
5729 {
5730 /* We take i.suffix from the last register operand specified,
5731 Destination register type is more significant than source
381d071f
L		 5732 register type. crc32 in SSE4.2 prefers source register
5733 type. */
5734 if (i.tm.base_opcode == 0xf20f38f1)
5735 {
dc821c5f 5736 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5737 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5738 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5739 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5740 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5741 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5742 }
9344ff29 5743 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5744 {
dc821c5f 5745 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5746 i.suffix = BYTE_MNEM_SUFFIX;
5747 }
381d071f
L		 5748
5749 if (!i.suffix)
5750 {
5751 int op;
5752
20592a94
L		 5753 if (i.tm.base_opcode == 0xf20f38f1
5754 || i.tm.base_opcode == 0xf20f38f0)
5755 {
5756 /* We have to know the operand size for crc32. */
5757 as_bad (_("ambiguous memory operand size for `%s`"),
5758 i.tm.name);
5759 return 0;
5760 }
5761
381d071f 5762 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5763 if (!i.tm.operand_types[op].bitfield.inoutportreg
5764 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5765 {
dc821c5f 5766 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
40fb9820
L		 5767 {
5768 i.suffix = BYTE_MNEM_SUFFIX;
5769 break;
5770 }
dc821c5f 5771 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
40fb9820
L		 5772 {
5773 i.suffix = WORD_MNEM_SUFFIX;
5774 break;
5775 }
dc821c5f 5776 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 5777 {
5778 i.suffix = LONG_MNEM_SUFFIX;
5779 break;
5780 }
dc821c5f 5781 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 5782 {
5783 i.suffix = QWORD_MNEM_SUFFIX;
5784 break;
5785 }
381d071f
L		 5786 }
5787 }
29b0f896
AM		 5788 }
5789 else if (i.suffix == BYTE_MNEM_SUFFIX)
5790 {
2eb952a4
L		 5791 if (intel_syntax
5792 && i.tm.opcode_modifier.ignoresize
5793 && i.tm.opcode_modifier.no_bsuf)
5794 i.suffix = 0;
5795 else if (!check_byte_reg ())
29b0f896
AM		 5796 return 0;
5797 }
5798 else if (i.suffix == LONG_MNEM_SUFFIX)
5799 {
2eb952a4
L		 5800 if (intel_syntax
5801 && i.tm.opcode_modifier.ignoresize
5802 && i.tm.opcode_modifier.no_lsuf)
5803 i.suffix = 0;
5804 else if (!check_long_reg ())
29b0f896
AM		 5805 return 0;
5806 }
5807 else if (i.suffix == QWORD_MNEM_SUFFIX)
5808 {
955e1e6a
L		 5809 if (intel_syntax
5810 && i.tm.opcode_modifier.ignoresize
5811 && i.tm.opcode_modifier.no_qsuf)
5812 i.suffix = 0;
5813 else if (!check_qword_reg ())
29b0f896
AM		 5814 return 0;
5815 }
5816 else if (i.suffix == WORD_MNEM_SUFFIX)
5817 {
2eb952a4
L		 5818 if (intel_syntax
5819 && i.tm.opcode_modifier.ignoresize
5820 && i.tm.opcode_modifier.no_wsuf)
5821 i.suffix = 0;
5822 else if (!check_word_reg ())
29b0f896
AM		 5823 return 0;
5824 }
c0f3af97 5825 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5826 || i.suffix == YMMWORD_MNEM_SUFFIX
5827 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5828 {
43234a1e 5829 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5830 should check if it is a valid suffix. */
5831 }
40fb9820 5832 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5833 /* Do nothing if the instruction is going to ignore the prefix. */
5834 ;
5835 else
5836 abort ();
5837 }
40fb9820 5838 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5839 && !i.suffix
5840 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5841 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5842 {
5843 i.suffix = stackop_size;
5844 }
9306ca4a
JB		 5845 else if (intel_syntax
5846 && !i.suffix
40fb9820
L		 5847 && (i.tm.operand_types[0].bitfield.jumpabsolute
5848 || i.tm.opcode_modifier.jumpbyte
5849 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5850 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5851 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5852 {
5853 switch (flag_code)
5854 {
5855 case CODE_64BIT:
40fb9820 5856 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5857 {
5858 i.suffix = QWORD_MNEM_SUFFIX;
5859 break;
5860 }
1a0670f3 5861 /* Fall through. */
9306ca4a 5862 case CODE_32BIT:
40fb9820 5863 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5864 i.suffix = LONG_MNEM_SUFFIX;
5865 break;
5866 case CODE_16BIT:
40fb9820 5867 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5868 i.suffix = WORD_MNEM_SUFFIX;
5869 break;
5870 }
5871 }
252b5132 5872
9306ca4a 5873 if (!i.suffix)
29b0f896 5874 {
9306ca4a
JB		 5875 if (!intel_syntax)
5876 {
40fb9820 5877 if (i.tm.opcode_modifier.w)
9306ca4a 5878 {
4eed87de
AM		 5879 as_bad (_("no instruction mnemonic suffix given and "
5880 "no register operands; can't size instruction"));
9306ca4a
JB		 5881 return 0;
5882 }
5883 }
5884 else
5885 {
40fb9820 5886 unsigned int suffixes;
7ab9ffdd 5887
40fb9820
L		 5888 suffixes = !i.tm.opcode_modifier.no_bsuf;
5889 if (!i.tm.opcode_modifier.no_wsuf)
5890 suffixes |= 1 << 1;
5891 if (!i.tm.opcode_modifier.no_lsuf)
5892 suffixes |= 1 << 2;
fc4adea1 5893 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5894 suffixes |= 1 << 3;
5895 if (!i.tm.opcode_modifier.no_ssuf)
5896 suffixes |= 1 << 4;
c2b9da16 5897 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5898 suffixes |= 1 << 5;
5899
5900 /* There are more than suffix matches. */
5901 if (i.tm.opcode_modifier.w
9306ca4a 5902 || ((suffixes & (suffixes - 1))
40fb9820
L		 5903 && !i.tm.opcode_modifier.defaultsize
5904 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5905 {
5906 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5907 return 0;
5908 }
5909 }
29b0f896 5910 }
252b5132 5911
9306ca4a
JB		 5912 /* Change the opcode based on the operand size given by i.suffix;
5913 We don't need to change things for byte insns. */
5914
582d5edd
L		 5915 if (i.suffix
5916 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5917 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5918 && i.suffix != YMMWORD_MNEM_SUFFIX
5919 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5920 {
5921 /* It's not a byte, select word/dword operation. */
40fb9820 5922 if (i.tm.opcode_modifier.w)
29b0f896 5923 {
40fb9820 5924 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5925 i.tm.base_opcode |= 8;
5926 else
5927 i.tm.base_opcode |= 1;
5928 }
0f3f3d8b 5929
29b0f896
AM		 5930 /* Now select between word & dword operations via the operand
5931 size prefix, except for instructions that will ignore this
5932 prefix anyway. */
ca61edf2 5933 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5934 {
ca61edf2
L		 5935 /* The address size override prefix changes the size of the
5936 first operand. */
40fb9820 5937 if ((flag_code == CODE_32BIT
dc821c5f 5938 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5939 || (flag_code != CODE_32BIT
dc821c5f 5940 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5941 if (!add_prefix (ADDR_PREFIX_OPCODE))
5942 return 0;
5943 }
5944 else if (i.suffix != QWORD_MNEM_SUFFIX
5945 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5946 && !i.tm.opcode_modifier.ignoresize
5947 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5948 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5949 || (flag_code == CODE_64BIT
40fb9820 5950 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5951 {
5952 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5953
40fb9820 5954 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5955 prefix = ADDR_PREFIX_OPCODE;
252b5132 5956
29b0f896
AM		 5957 if (!add_prefix (prefix))
5958 return 0;
24eab124 5959 }
252b5132 5960
29b0f896
AM		 5961 /* Set mode64 for an operand. */
5962 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5963 && flag_code == CODE_64BIT
40fb9820 5964 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5965 {
5966 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5967 need rex64. cmpxchg8b is also a special case. */
5968 if (! (i.operands == 2
5969 && i.tm.base_opcode == 0x90
5970 && i.tm.extension_opcode == None
0dfbf9d7
L		 5971 && operand_type_equal (&i.types [0], &acc64)
5972 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5973 && ! (i.operands == 1
5974 && i.tm.base_opcode == 0xfc7
5975 && i.tm.extension_opcode == 1
40fb9820
L		 5976 && !operand_type_check (i.types [0], reg)
5977 && operand_type_check (i.types [0], anymem)))
f6bee062 5978 i.rex |= REX_W;
46e883c5 5979 }
3e73aa7c 5980
29b0f896
AM		 5981 /* Size floating point instruction. */
5982 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5983 if (i.tm.opcode_modifier.floatmf)
543613e9 5984 i.tm.base_opcode ^= 4;
29b0f896 5985 }
7ecd2f8b 5986
29b0f896
AM		 5987 return 1;
5988}
3e73aa7c 5989
29b0f896 5990static int
543613e9 5991check_byte_reg (void)
29b0f896
AM		 5992{
5993 int op;
543613e9 5994
29b0f896
AM		 5995 for (op = i.operands; --op >= 0;)
5996 {
dc821c5f
JB		 5997 /* Skip non-register operands. */
5998 if (!i.types[op].bitfield.reg)
5999 continue;
6000
29b0f896
AM		 6001 /* If this is an eight bit register, it's OK. If it's the 16 or
6002 32 bit version of an eight bit register, we will just use the
6003 low portion, and that's OK too. */
dc821c5f 6004 if (i.types[op].bitfield.byte)
29b0f896
AM		 6005 continue;
6006
5a819eb9
JB		 6007 /* I/O port address operands are OK too. */
6008 if (i.tm.operand_types[op].bitfield.inoutportreg)
6009 continue;
6010
9344ff29
L		 6011 /* crc32 doesn't generate this warning. */
6012 if (i.tm.base_opcode == 0xf20f38f0)
6013 continue;
6014
dc821c5f
JB		 6015 if ((i.types[op].bitfield.word
6016 || i.types[op].bitfield.dword
6017 || i.types[op].bitfield.qword)
5a819eb9
JB		 6018 && i.op[op].regs->reg_num < 4
6019 /* Prohibit these changes in 64bit mode, since the lowering
6020 would be more complicated. */
6021 && flag_code != CODE_64BIT)
29b0f896 6022 {
29b0f896 6023#if REGISTER_WARNINGS
5a819eb9 6024 if (!quiet_warnings)
a540244d
L		 6025 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6026 register_prefix,
dc821c5f 6027 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6028 ? REGNAM_AL - REGNAM_AX
6029 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6030 register_prefix,
29b0f896
AM		 6031 i.op[op].regs->reg_name,
6032 i.suffix);
6033#endif
6034 continue;
6035 }
6036 /* Any other register is bad. */
dc821c5f 6037 if (i.types[op].bitfield.reg
40fb9820 6038 || i.types[op].bitfield.regmmx
1b54b8d7 6039 || i.types[op].bitfield.regsimd
40fb9820
L		 6040 || i.types[op].bitfield.sreg2
6041 || i.types[op].bitfield.sreg3
6042 || i.types[op].bitfield.control
6043 || i.types[op].bitfield.debug
ca0d63fe 6044 || i.types[op].bitfield.test)
29b0f896 6045 {
a540244d
L		 6046 as_bad (_("`%s%s' not allowed with `%s%c'"),
6047 register_prefix,
29b0f896
AM		 6048 i.op[op].regs->reg_name,
6049 i.tm.name,
6050 i.suffix);
6051 return 0;
6052 }
6053 }
6054 return 1;
6055}
6056
6057static int
e3bb37b5 6058check_long_reg (void)
29b0f896
AM		 6059{
6060 int op;
6061
6062 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6063 /* Skip non-register operands. */
6064 if (!i.types[op].bitfield.reg)
6065 continue;
29b0f896
AM		 6066 /* Reject eight bit registers, except where the template requires
6067 them. (eg. movzb) */
dc821c5f
JB		 6068 else if (i.types[op].bitfield.byte
6069 && (i.tm.operand_types[op].bitfield.reg
6070 || i.tm.operand_types[op].bitfield.acc)
6071 && (i.tm.operand_types[op].bitfield.word
6072 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6073 {
a540244d
L		 6074 as_bad (_("`%s%s' not allowed with `%s%c'"),
6075 register_prefix,
29b0f896
AM		 6076 i.op[op].regs->reg_name,
6077 i.tm.name,
6078 i.suffix);
6079 return 0;
6080 }
e4630f71 6081 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6082 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6083 && i.types[op].bitfield.word
6084 && (i.tm.operand_types[op].bitfield.reg
6085 || i.tm.operand_types[op].bitfield.acc)
6086 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6087 {
6088 /* Prohibit these changes in the 64bit mode, since the
6089 lowering is more complicated. */
6090 if (flag_code == CODE_64BIT)
252b5132 6091 {
2b5d6a91 6092 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6093 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6094 i.suffix);
6095 return 0;
252b5132 6096 }
29b0f896 6097#if REGISTER_WARNINGS
cecf1424
JB		 6098 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6099 register_prefix,
6100 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6101 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6102#endif
252b5132 6103 }
e4630f71 6104 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6105 else if (i.types[op].bitfield.qword
6106 && (i.tm.operand_types[op].bitfield.reg
6107 || i.tm.operand_types[op].bitfield.acc)
6108 && i.tm.operand_types[op].bitfield.dword)
252b5132 6109 {
34828aad 6110 if (intel_syntax
ca61edf2 6111 && i.tm.opcode_modifier.toqword
1b54b8d7 6112 && !i.types[0].bitfield.regsimd)
34828aad 6113 {
ca61edf2 6114 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6115 i.suffix = QWORD_MNEM_SUFFIX;
6116 }
6117 else
6118 {
2b5d6a91 6119 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6120 register_prefix, i.op[op].regs->reg_name,
6121 i.suffix);
6122 return 0;
6123 }
29b0f896
AM		 6124 }
6125 return 1;
6126}
252b5132 6127
29b0f896 6128static int
e3bb37b5 6129check_qword_reg (void)
29b0f896
AM		 6130{
6131 int op;
252b5132 6132
29b0f896 6133 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6134 /* Skip non-register operands. */
6135 if (!i.types[op].bitfield.reg)
6136 continue;
29b0f896
AM		 6137 /* Reject eight bit registers, except where the template requires
6138 them. (eg. movzb) */
dc821c5f
JB		 6139 else if (i.types[op].bitfield.byte
6140 && (i.tm.operand_types[op].bitfield.reg
6141 || i.tm.operand_types[op].bitfield.acc)
6142 && (i.tm.operand_types[op].bitfield.word
6143 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6144 {
a540244d
L		 6145 as_bad (_("`%s%s' not allowed with `%s%c'"),
6146 register_prefix,
29b0f896
AM		 6147 i.op[op].regs->reg_name,
6148 i.tm.name,
6149 i.suffix);
6150 return 0;
6151 }
e4630f71 6152 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6153 else if ((i.types[op].bitfield.word
6154 || i.types[op].bitfield.dword)
6155 && (i.tm.operand_types[op].bitfield.reg
6156 || i.tm.operand_types[op].bitfield.acc)
6157 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6158 {
6159 /* Prohibit these changes in the 64bit mode, since the
6160 lowering is more complicated. */
34828aad 6161 if (intel_syntax
ca61edf2 6162 && i.tm.opcode_modifier.todword
1b54b8d7 6163 && !i.types[0].bitfield.regsimd)
34828aad 6164 {
ca61edf2 6165 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6166 i.suffix = LONG_MNEM_SUFFIX;
6167 }
6168 else
6169 {
2b5d6a91 6170 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6171 register_prefix, i.op[op].regs->reg_name,
6172 i.suffix);
6173 return 0;
6174 }
252b5132 6175 }
29b0f896
AM		 6176 return 1;
6177}
252b5132 6178
29b0f896 6179static int
e3bb37b5 6180check_word_reg (void)
29b0f896
AM		 6181{
6182 int op;
6183 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6184 /* Skip non-register operands. */
6185 if (!i.types[op].bitfield.reg)
6186 continue;
29b0f896
AM		 6187 /* Reject eight bit registers, except where the template requires
6188 them. (eg. movzb) */
dc821c5f
JB		 6189 else if (i.types[op].bitfield.byte
6190 && (i.tm.operand_types[op].bitfield.reg
6191 || i.tm.operand_types[op].bitfield.acc)
6192 && (i.tm.operand_types[op].bitfield.word
6193 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6194 {
a540244d
L		 6195 as_bad (_("`%s%s' not allowed with `%s%c'"),
6196 register_prefix,
29b0f896
AM		 6197 i.op[op].regs->reg_name,
6198 i.tm.name,
6199 i.suffix);
6200 return 0;
6201 }
e4630f71 6202 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6203 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6204 && (i.types[op].bitfield.dword
6205 || i.types[op].bitfield.qword)
6206 && (i.tm.operand_types[op].bitfield.reg
6207 || i.tm.operand_types[op].bitfield.acc)
6208 && i.tm.operand_types[op].bitfield.word)
252b5132 6209 {
29b0f896
AM		 6210 /* Prohibit these changes in the 64bit mode, since the
6211 lowering is more complicated. */
6212 if (flag_code == CODE_64BIT)
252b5132 6213 {
2b5d6a91 6214 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6215 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6216 i.suffix);
6217 return 0;
252b5132 6218 }
29b0f896 6219#if REGISTER_WARNINGS
cecf1424
JB		 6220 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6221 register_prefix,
6222 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6223 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6224#endif
6225 }
6226 return 1;
6227}
252b5132 6228
29b0f896 6229static int
40fb9820 6230update_imm (unsigned int j)
29b0f896 6231{
bc0844ae 6232 i386_operand_type overlap = i.types[j];
40fb9820
L		 6233 if ((overlap.bitfield.imm8
6234 || overlap.bitfield.imm8s
6235 || overlap.bitfield.imm16
6236 || overlap.bitfield.imm32
6237 || overlap.bitfield.imm32s
6238 || overlap.bitfield.imm64)
0dfbf9d7
L		 6239 && !operand_type_equal (&overlap, &imm8)
6240 && !operand_type_equal (&overlap, &imm8s)
6241 && !operand_type_equal (&overlap, &imm16)
6242 && !operand_type_equal (&overlap, &imm32)
6243 && !operand_type_equal (&overlap, &imm32s)
6244 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6245 {
6246 if (i.suffix)
6247 {
40fb9820
L		 6248 i386_operand_type temp;
6249
0dfbf9d7 6250 operand_type_set (&temp, 0);
7ab9ffdd 6251 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6252 {
6253 temp.bitfield.imm8 = overlap.bitfield.imm8;
6254 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6255 }
6256 else if (i.suffix == WORD_MNEM_SUFFIX)
6257 temp.bitfield.imm16 = overlap.bitfield.imm16;
6258 else if (i.suffix == QWORD_MNEM_SUFFIX)
6259 {
6260 temp.bitfield.imm64 = overlap.bitfield.imm64;
6261 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6262 }
6263 else
6264 temp.bitfield.imm32 = overlap.bitfield.imm32;
6265 overlap = temp;
29b0f896 6266 }
0dfbf9d7
L		 6267 else if (operand_type_equal (&overlap, &imm16_32_32s)
6268 || operand_type_equal (&overlap, &imm16_32)
6269 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6270 {
40fb9820 6271 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6272 overlap = imm16;
40fb9820 6273 else
65da13b5 6274 overlap = imm32s;
29b0f896 6275 }
0dfbf9d7
L		 6276 if (!operand_type_equal (&overlap, &imm8)
6277 && !operand_type_equal (&overlap, &imm8s)
6278 && !operand_type_equal (&overlap, &imm16)
6279 && !operand_type_equal (&overlap, &imm32)
6280 && !operand_type_equal (&overlap, &imm32s)
6281 && !operand_type_equal (&overlap, &imm64))
29b0f896 6282 {
4eed87de
AM		 6283 as_bad (_("no instruction mnemonic suffix given; "
6284 "can't determine immediate size"));
29b0f896
AM		 6285 return 0;
6286 }
6287 }
40fb9820 6288 i.types[j] = overlap;
29b0f896 6289
40fb9820
L		 6290 return 1;
6291}
6292
6293static int
6294finalize_imm (void)
6295{
bc0844ae 6296 unsigned int j, n;
29b0f896 6297
bc0844ae
L		 6298 /* Update the first 2 immediate operands. */
6299 n = i.operands > 2 ? 2 : i.operands;
6300 if (n)
6301 {
6302 for (j = 0; j < n; j++)
6303 if (update_imm (j) == 0)
6304 return 0;
40fb9820 6305
bc0844ae
L		 6306 /* The 3rd operand can't be immediate operand. */
6307 gas_assert (operand_type_check (i.types[2], imm) == 0);
6308 }
29b0f896
AM		 6309
6310 return 1;
6311}
6312
6313static int
e3bb37b5 6314process_operands (void)
29b0f896
AM		 6315{
6316 /* Default segment register this instruction will use for memory
6317 accesses. 0 means unknown. This is only for optimizing out
6318 unnecessary segment overrides. */
6319 const seg_entry *default_seg = 0;
6320
2426c15f 6321 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6322 {
91d6fa6a
NC		 6323 unsigned int dupl = i.operands;
6324 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6325 unsigned int j;
6326
c0f3af97 6327 /* The destination must be an xmm register. */
9c2799c2 6328 gas_assert (i.reg_operands
91d6fa6a 6329 && MAX_OPERANDS > dupl
7ab9ffdd 6330 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6331
1b54b8d7
JB		 6332 if (i.tm.operand_types[0].bitfield.acc
6333 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6334 {
8cd7925b 6335 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6336 {
6337 /* Keep xmm0 for instructions with VEX prefix and 3
6338 sources. */
1b54b8d7
JB		 6339 i.tm.operand_types[0].bitfield.acc = 0;
6340 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6341 goto duplicate;
6342 }
e2ec9d29 6343 else
c0f3af97
L		 6344 {
6345 /* We remove the first xmm0 and keep the number of
6346 operands unchanged, which in fact duplicates the
6347 destination. */
6348 for (j = 1; j < i.operands; j++)
6349 {
6350 i.op[j - 1] = i.op[j];
6351 i.types[j - 1] = i.types[j];
6352 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6353 }
6354 }
6355 }
6356 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6357 {
91d6fa6a 6358 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6359 && (i.tm.opcode_modifier.vexsources
6360 == VEX3SOURCES));
c0f3af97
L		 6361
6362 /* Add the implicit xmm0 for instructions with VEX prefix
6363 and 3 sources. */
6364 for (j = i.operands; j > 0; j--)
6365 {
6366 i.op[j] = i.op[j - 1];
6367 i.types[j] = i.types[j - 1];
6368 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6369 }
6370 i.op[0].regs
6371 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6372 i.types[0] = regxmm;
c0f3af97
L		 6373 i.tm.operand_types[0] = regxmm;
6374
6375 i.operands += 2;
6376 i.reg_operands += 2;
6377 i.tm.operands += 2;
6378
91d6fa6a 6379 dupl++;
c0f3af97 6380 dest++;
91d6fa6a
NC		 6381 i.op[dupl] = i.op[dest];
6382 i.types[dupl] = i.types[dest];
6383 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6384 }
c0f3af97
L		 6385 else
6386 {
6387duplicate:
6388 i.operands++;
6389 i.reg_operands++;
6390 i.tm.operands++;
6391
91d6fa6a
NC		 6392 i.op[dupl] = i.op[dest];
6393 i.types[dupl] = i.types[dest];
6394 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6395 }
6396
6397 if (i.tm.opcode_modifier.immext)
6398 process_immext ();
6399 }
1b54b8d7
JB		 6400 else if (i.tm.operand_types[0].bitfield.acc
6401 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6402 {
6403 unsigned int j;
6404
9fcfb3d7
L		 6405 for (j = 1; j < i.operands; j++)
6406 {
6407 i.op[j - 1] = i.op[j];
6408 i.types[j - 1] = i.types[j];
6409
6410 /* We need to adjust fields in i.tm since they are used by
6411 build_modrm_byte. */
6412 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6413 }
6414
e2ec9d29
L		 6415 i.operands--;
6416 i.reg_operands--;
e2ec9d29
L		 6417 i.tm.operands--;
6418 }
920d2ddc
IT		 6419 else if (i.tm.opcode_modifier.implicitquadgroup)
6420 {
a477a8c4
JB		 6421 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6422
920d2ddc 6423 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6424 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6425 regnum = register_number (i.op[1].regs);
6426 first_reg_in_group = regnum & ~3;
6427 last_reg_in_group = first_reg_in_group + 3;
6428 if (regnum != first_reg_in_group)
6429 as_warn (_("source register `%s%s' implicitly denotes"
6430 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6431 register_prefix, i.op[1].regs->reg_name,
6432 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6433 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6434 i.tm.name);
6435 }
e2ec9d29
L		 6436 else if (i.tm.opcode_modifier.regkludge)
6437 {
6438 /* The imul $imm, %reg instruction is converted into
6439 imul $imm, %reg, %reg, and the clr %reg instruction
6440 is converted into xor %reg, %reg. */
6441
6442 unsigned int first_reg_op;
6443
6444 if (operand_type_check (i.types[0], reg))
6445 first_reg_op = 0;
6446 else
6447 first_reg_op = 1;
6448 /* Pretend we saw the extra register operand. */
9c2799c2 6449 gas_assert (i.reg_operands == 1
7ab9ffdd 6450 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6451 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6452 i.types[first_reg_op + 1] = i.types[first_reg_op];
6453 i.operands++;
6454 i.reg_operands++;
29b0f896
AM		 6455 }
6456
40fb9820 6457 if (i.tm.opcode_modifier.shortform)
29b0f896 6458 {
40fb9820
L		 6459 if (i.types[0].bitfield.sreg2
6460 || i.types[0].bitfield.sreg3)
29b0f896 6461 {
4eed87de
AM		 6462 if (i.tm.base_opcode == POP_SEG_SHORT
6463 && i.op[0].regs->reg_num == 1)
29b0f896 6464 {
a87af027 6465 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6466 return 0;
29b0f896 6467 }
4eed87de
AM		 6468 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6469 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6470 i.rex |= REX_B;
4eed87de
AM		 6471 }
6472 else
6473 {
7ab9ffdd 6474 /* The register or float register operand is in operand
85f10a01 6475 0 or 1. */
40fb9820 6476 unsigned int op;
7ab9ffdd 6477
ca0d63fe 6478 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6479 || operand_type_check (i.types[0], reg))
6480 op = 0;
6481 else
6482 op = 1;
4eed87de
AM		 6483 /* Register goes in low 3 bits of opcode. */
6484 i.tm.base_opcode |= i.op[op].regs->reg_num;
6485 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6486 i.rex |= REX_B;
40fb9820 6487 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6488 {
4eed87de
AM		 6489 /* Warn about some common errors, but press on regardless.
6490 The first case can be generated by gcc (<= 2.8.1). */
6491 if (i.operands == 2)
6492 {
6493 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6494 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6495 register_prefix, i.op[!intel_syntax].regs->reg_name,
6496 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6497 }
6498 else
6499 {
6500 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6501 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6502 register_prefix, i.op[0].regs->reg_name);
4eed87de 6503 }
29b0f896
AM		 6504 }
6505 }
6506 }
40fb9820 6507 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6508 {
6509 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6510 must be put into the modrm byte). Now, we make the modrm and
6511 index base bytes based on all the info we've collected. */
29b0f896
AM		 6512
6513 default_seg = build_modrm_byte ();
6514 }
8a2ed489 6515 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6516 {
6517 default_seg = &ds;
6518 }
40fb9820 6519 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6520 {
6521 /* For the string instructions that allow a segment override
6522 on one of their operands, the default segment is ds. */
6523 default_seg = &ds;
6524 }
6525
75178d9d
L		 6526 if (i.tm.base_opcode == 0x8d /* lea */
6527 && i.seg[0]
6528 && !quiet_warnings)
30123838 6529 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6530
6531 /* If a segment was explicitly specified, and the specified segment
6532 is not the default, use an opcode prefix to select it. If we
6533 never figured out what the default segment is, then default_seg
6534 will be zero at this point, and the specified segment prefix will
6535 always be used. */
29b0f896
AM		 6536 if ((i.seg[0]) && (i.seg[0] != default_seg))
6537 {
6538 if (!add_prefix (i.seg[0]->seg_prefix))
6539 return 0;
6540 }
6541 return 1;
6542}
6543
6544static const seg_entry *
e3bb37b5 6545build_modrm_byte (void)
29b0f896
AM		 6546{
6547 const seg_entry *default_seg = 0;
c0f3af97 6548 unsigned int source, dest;
8cd7925b 6549 int vex_3_sources;
c0f3af97
L		 6550
6551 /* The first operand of instructions with VEX prefix and 3 sources
6552 must be VEX_Imm4. */
8cd7925b 6553 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6554 if (vex_3_sources)
6555 {
91d6fa6a 6556 unsigned int nds, reg_slot;
4c2c6516 6557 expressionS *exp;
c0f3af97 6558
922d8de8 6559 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6560 && i.tm.opcode_modifier.immext)
6561 {
6562 dest = i.operands - 2;
6563 gas_assert (dest == 3);
6564 }
922d8de8 6565 else
a683cc34 6566 dest = i.operands - 1;
c0f3af97 6567 nds = dest - 1;
922d8de8 6568
a683cc34
SP		 6569 /* There are 2 kinds of instructions:
6570 1. 5 operands: 4 register operands or 3 register operands
6571 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6572 VexW0 or VexW1. The destination must be either XMM, YMM or
6573 ZMM register.
a683cc34
SP		 6574 2. 4 operands: 4 register operands or 3 register operands
6575 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6576 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6577 || (i.reg_operands == 3 && i.mem_operands == 1))
6578 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6579 && (i.tm.opcode_modifier.veximmext
6580 || (i.imm_operands == 1
6581 && i.types[0].bitfield.vec_imm4
6582 && (i.tm.opcode_modifier.vexw == VEXW0
6583 || i.tm.opcode_modifier.vexw == VEXW1)
10c17abd 6584 && i.tm.operand_types[dest].bitfield.regsimd)));
a683cc34
SP		 6585
6586 if (i.imm_operands == 0)
6587 {
6588 /* When there is no immediate operand, generate an 8bit
6589 immediate operand to encode the first operand. */
6590 exp = &im_expressions[i.imm_operands++];
6591 i.op[i.operands].imms = exp;
6592 i.types[i.operands] = imm8;
6593 i.operands++;
6594 /* If VexW1 is set, the first operand is the source and
6595 the second operand is encoded in the immediate operand. */
6596 if (i.tm.opcode_modifier.vexw == VEXW1)
6597 {
6598 source = 0;
6599 reg_slot = 1;
6600 }
6601 else
6602 {
6603 source = 1;
6604 reg_slot = 0;
6605 }
6606
6607 /* FMA swaps REG and NDS. */
6608 if (i.tm.cpu_flags.bitfield.cpufma)
6609 {
6610 unsigned int tmp;
6611 tmp = reg_slot;
6612 reg_slot = nds;
6613 nds = tmp;
6614 }
6615
10c17abd 6616 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6617 exp->X_op = O_constant;
4c692bc7 6618 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6619 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6620 }
922d8de8 6621 else
a683cc34
SP		 6622 {
6623 unsigned int imm_slot;
6624
6625 if (i.tm.opcode_modifier.vexw == VEXW0)
6626 {
6627 /* If VexW0 is set, the third operand is the source and
6628 the second operand is encoded in the immediate
6629 operand. */
6630 source = 2;
6631 reg_slot = 1;
6632 }
6633 else
6634 {
6635 /* VexW1 is set, the second operand is the source and
6636 the third operand is encoded in the immediate
6637 operand. */
6638 source = 1;
6639 reg_slot = 2;
6640 }
6641
6642 if (i.tm.opcode_modifier.immext)
6643 {
33eaf5de 6644 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6645 operand. */
6646 imm_slot = i.operands - 1;
6647 source--;
6648 reg_slot--;
6649 }
6650 else
6651 {
6652 imm_slot = 0;
6653
6654 /* Turn on Imm8 so that output_imm will generate it. */
6655 i.types[imm_slot].bitfield.imm8 = 1;
6656 }
6657
10c17abd 6658 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6659 i.op[imm_slot].imms->X_add_number
4c692bc7 6660 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6661 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6662 }
6663
10c17abd 6664 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6665 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6666 }
6667 else
6668 source = dest = 0;
29b0f896
AM		 6669
6670 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6671 implicit registers do not count. If there are 3 register
6672 operands, it must be a instruction with VexNDS. For a
6673 instruction with VexNDD, the destination register is encoded
6674 in VEX prefix. If there are 4 register operands, it must be
6675 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6676 if (i.mem_operands == 0
6677 && ((i.reg_operands == 2
2426c15f 6678 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6679 || (i.reg_operands == 3
2426c15f 6680 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6681 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6682 {
cab737b9
L		 6683 switch (i.operands)
6684 {
6685 case 2:
6686 source = 0;
6687 break;
6688 case 3:
c81128dc
L		 6689 /* When there are 3 operands, one of them may be immediate,
6690 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6691 the first operand must be shift count register (cl) or it
6692 is an instruction with VexNDS. */
9c2799c2 6693 gas_assert (i.imm_operands == 1
7ab9ffdd 6694 || (i.imm_operands == 0
2426c15f 6695 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6696 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6697 if (operand_type_check (i.types[0], imm)
6698 || i.types[0].bitfield.shiftcount)
6699 source = 1;
6700 else
6701 source = 0;
cab737b9
L		 6702 break;
6703 case 4:
368d64cc
L		 6704 /* When there are 4 operands, the first two must be 8bit
6705 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6706 one.
6707
6708 For instructions with VexNDS, if the first operand
6709 an imm8, the source operand is the 2nd one. If the last
6710 operand is imm8, the source operand is the first one. */
9c2799c2 6711 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6712 && i.types[0].bitfield.imm8
6713 && i.types[1].bitfield.imm8)
2426c15f 6714 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6715 && i.imm_operands == 1
6716 && (i.types[0].bitfield.imm8
43234a1e
L		 6717 || i.types[i.operands - 1].bitfield.imm8
6718 || i.rounding)));
9f2670f2
L		 6719 if (i.imm_operands == 2)
6720 source = 2;
6721 else
c0f3af97
L		 6722 {
6723 if (i.types[0].bitfield.imm8)
6724 source = 1;
6725 else
6726 source = 0;
6727 }
c0f3af97
L		 6728 break;
6729 case 5:
43234a1e
L		 6730 if (i.tm.opcode_modifier.evex)
6731 {
6732 /* For EVEX instructions, when there are 5 operands, the
6733 first one must be immediate operand. If the second one
6734 is immediate operand, the source operand is the 3th
6735 one. If the last one is immediate operand, the source
6736 operand is the 2nd one. */
6737 gas_assert (i.imm_operands == 2
6738 && i.tm.opcode_modifier.sae
6739 && operand_type_check (i.types[0], imm));
6740 if (operand_type_check (i.types[1], imm))
6741 source = 2;
6742 else if (operand_type_check (i.types[4], imm))
6743 source = 1;
6744 else
6745 abort ();
6746 }
cab737b9
L		 6747 break;
6748 default:
6749 abort ();
6750 }
6751
c0f3af97
L		 6752 if (!vex_3_sources)
6753 {
6754 dest = source + 1;
6755
43234a1e
L		 6756 /* RC/SAE operand could be between DEST and SRC. That happens
6757 when one operand is GPR and the other one is XMM/YMM/ZMM
6758 register. */
6759 if (i.rounding && i.rounding->operand == (int) dest)
6760 dest++;
6761
2426c15f 6762 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6763 {
43234a1e 6764 /* For instructions with VexNDS, the register-only source
c5d0745b 6765 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6766 register. It is encoded in VEX prefix. We need to
6767 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6768
6769 i386_operand_type op;
6770 unsigned int vvvv;
6771
6772 /* Check register-only source operand when two source
6773 operands are swapped. */
6774 if (!i.tm.operand_types[source].bitfield.baseindex
6775 && i.tm.operand_types[dest].bitfield.baseindex)
6776 {
6777 vvvv = source;
6778 source = dest;
6779 }
6780 else
6781 vvvv = dest;
6782
6783 op = i.tm.operand_types[vvvv];
fa99fab2 6784 op.bitfield.regmem = 0;
c0f3af97 6785 if ((dest + 1) >= i.operands
dc821c5f
JB		 6786 || ((!op.bitfield.reg
6787 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6788 && !op.bitfield.regsimd
43234a1e 6789 && !operand_type_equal (&op, &regmask)))
c0f3af97 6790 abort ();
f12dc422 6791 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6792 dest++;
6793 }
6794 }
29b0f896
AM		 6795
6796 i.rm.mode = 3;
6797 /* One of the register operands will be encoded in the i.tm.reg
6798 field, the other in the combined i.tm.mode and i.tm.regmem
6799 fields. If no form of this instruction supports a memory
6800 destination operand, then we assume the source operand may
6801 sometimes be a memory operand and so we need to store the
6802 destination in the i.rm.reg field. */
40fb9820
L		 6803 if (!i.tm.operand_types[dest].bitfield.regmem
6804 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6805 {
6806 i.rm.reg = i.op[dest].regs->reg_num;
6807 i.rm.regmem = i.op[source].regs->reg_num;
6808 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6809 i.rex |= REX_R;
43234a1e
L		 6810 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6811 i.vrex |= REX_R;
29b0f896 6812 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6813 i.rex |= REX_B;
43234a1e
L		 6814 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6815 i.vrex |= REX_B;
29b0f896
AM		 6816 }
6817 else
6818 {
6819 i.rm.reg = i.op[source].regs->reg_num;
6820 i.rm.regmem = i.op[dest].regs->reg_num;
6821 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6822 i.rex |= REX_B;
43234a1e
L		 6823 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6824 i.vrex |= REX_B;
29b0f896 6825 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6826 i.rex |= REX_R;
43234a1e
L		 6827 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6828 i.vrex |= REX_R;
29b0f896 6829 }
161a04f6 6830 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6831 {
40fb9820
L		 6832 if (!i.types[0].bitfield.control
6833 && !i.types[1].bitfield.control)
c4a530c5 6834 abort ();
161a04f6 6835 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6836 add_prefix (LOCK_PREFIX_OPCODE);
6837 }
29b0f896
AM		 6838 }
6839 else
6840 { /* If it's not 2 reg operands... */
c0f3af97
L		 6841 unsigned int mem;
6842
29b0f896
AM		 6843 if (i.mem_operands)
6844 {
6845 unsigned int fake_zero_displacement = 0;
99018f42 6846 unsigned int op;
4eed87de 6847
7ab9ffdd
L		 6848 for (op = 0; op < i.operands; op++)
6849 if (operand_type_check (i.types[op], anymem))
6850 break;
7ab9ffdd 6851 gas_assert (op < i.operands);
29b0f896 6852
6c30d220
L		 6853 if (i.tm.opcode_modifier.vecsib)
6854 {
6855 if (i.index_reg->reg_num == RegEiz
6856 || i.index_reg->reg_num == RegRiz)
6857 abort ();
6858
6859 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6860 if (!i.base_reg)
6861 {
6862 i.sib.base = NO_BASE_REGISTER;
6863 i.sib.scale = i.log2_scale_factor;
6864 i.types[op].bitfield.disp8 = 0;
6865 i.types[op].bitfield.disp16 = 0;
6866 i.types[op].bitfield.disp64 = 0;
43083a50 6867 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6868 {
6869 /* Must be 32 bit */
6870 i.types[op].bitfield.disp32 = 1;
6871 i.types[op].bitfield.disp32s = 0;
6872 }
6873 else
6874 {
6875 i.types[op].bitfield.disp32 = 0;
6876 i.types[op].bitfield.disp32s = 1;
6877 }
6878 }
6879 i.sib.index = i.index_reg->reg_num;
6880 if ((i.index_reg->reg_flags & RegRex) != 0)
6881 i.rex |= REX_X;
43234a1e
L		 6882 if ((i.index_reg->reg_flags & RegVRex) != 0)
6883 i.vrex |= REX_X;
6c30d220
L		 6884 }
6885
29b0f896
AM		 6886 default_seg = &ds;
6887
6888 if (i.base_reg == 0)
6889 {
6890 i.rm.mode = 0;
6891 if (!i.disp_operands)
9bb129e8 6892 fake_zero_displacement = 1;
29b0f896
AM		 6893 if (i.index_reg == 0)
6894 {
73053c1f
JB		 6895 i386_operand_type newdisp;
6896
6c30d220 6897 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6898 /* Operand is just <disp> */
20f0a1fc 6899 if (flag_code == CODE_64BIT)
29b0f896
AM		 6900 {
6901 /* 64bit mode overwrites the 32bit absolute
6902 addressing by RIP relative addressing and
6903 absolute addressing is encoded by one of the
6904 redundant SIB forms. */
6905 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6906 i.sib.base = NO_BASE_REGISTER;
6907 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6908 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6909 }
fc225355
L		 6910 else if ((flag_code == CODE_16BIT)
6911 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6912 {
6913 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6914 newdisp = disp16;
20f0a1fc
NC		 6915 }
6916 else
6917 {
6918 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6919 newdisp = disp32;
29b0f896 6920 }
73053c1f
JB		 6921 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6922 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6923 }
6c30d220 6924 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6925 {
6c30d220 6926 /* !i.base_reg && i.index_reg */
db51cc60
L		 6927 if (i.index_reg->reg_num == RegEiz
6928 || i.index_reg->reg_num == RegRiz)
6929 i.sib.index = NO_INDEX_REGISTER;
6930 else
6931 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6932 i.sib.base = NO_BASE_REGISTER;
6933 i.sib.scale = i.log2_scale_factor;
6934 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6935 i.types[op].bitfield.disp8 = 0;
6936 i.types[op].bitfield.disp16 = 0;
6937 i.types[op].bitfield.disp64 = 0;
43083a50 6938 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6939 {
6940 /* Must be 32 bit */
6941 i.types[op].bitfield.disp32 = 1;
6942 i.types[op].bitfield.disp32s = 0;
6943 }
29b0f896 6944 else
40fb9820
L		 6945 {
6946 i.types[op].bitfield.disp32 = 0;
6947 i.types[op].bitfield.disp32s = 1;
6948 }
29b0f896 6949 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6950 i.rex |= REX_X;
29b0f896
AM		 6951 }
6952 }
6953 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6954 else if (i.base_reg->reg_num == RegRip ||
6955 i.base_reg->reg_num == RegEip)
29b0f896 6956 {
6c30d220 6957 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6958 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6959 i.types[op].bitfield.disp8 = 0;
6960 i.types[op].bitfield.disp16 = 0;
6961 i.types[op].bitfield.disp32 = 0;
6962 i.types[op].bitfield.disp32s = 1;
6963 i.types[op].bitfield.disp64 = 0;
71903a11 6964 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6965 if (! i.disp_operands)
6966 fake_zero_displacement = 1;
29b0f896 6967 }
dc821c5f 6968 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6969 {
6c30d220 6970 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6971 switch (i.base_reg->reg_num)
6972 {
6973 case 3: /* (%bx) */
6974 if (i.index_reg == 0)
6975 i.rm.regmem = 7;
6976 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6977 i.rm.regmem = i.index_reg->reg_num - 6;
6978 break;
6979 case 5: /* (%bp) */
6980 default_seg = &ss;
6981 if (i.index_reg == 0)
6982 {
6983 i.rm.regmem = 6;
40fb9820 6984 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6985 {
6986 /* fake (%bp) into 0(%bp) */
b5014f7a 6987 i.types[op].bitfield.disp8 = 1;
252b5132 6988 fake_zero_displacement = 1;
29b0f896
AM		 6989 }
6990 }
6991 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6992 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6993 break;
6994 default: /* (%si) -> 4 or (%di) -> 5 */
6995 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6996 }
6997 i.rm.mode = mode_from_disp_size (i.types[op]);
6998 }
6999 else /* i.base_reg and 32/64 bit mode */
7000 {
7001 if (flag_code == CODE_64BIT
40fb9820
L		 7002 && operand_type_check (i.types[op], disp))
7003 {
73053c1f
JB		 7004 i.types[op].bitfield.disp16 = 0;
7005 i.types[op].bitfield.disp64 = 0;
40fb9820 7006 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7007 {
7008 i.types[op].bitfield.disp32 = 0;
7009 i.types[op].bitfield.disp32s = 1;
7010 }
40fb9820 7011 else
73053c1f
JB		 7012 {
7013 i.types[op].bitfield.disp32 = 1;
7014 i.types[op].bitfield.disp32s = 0;
7015 }
40fb9820 7016 }
20f0a1fc 7017
6c30d220
L		 7018 if (!i.tm.opcode_modifier.vecsib)
7019 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7020 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7021 i.rex |= REX_B;
29b0f896
AM		 7022 i.sib.base = i.base_reg->reg_num;
7023 /* x86-64 ignores REX prefix bit here to avoid decoder
7024 complications. */
848930b2
JB		 7025 if (!(i.base_reg->reg_flags & RegRex)
7026 && (i.base_reg->reg_num == EBP_REG_NUM
7027 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7028 default_seg = &ss;
848930b2 7029 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7030 {
848930b2 7031 fake_zero_displacement = 1;
b5014f7a 7032 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7033 }
7034 i.sib.scale = i.log2_scale_factor;
7035 if (i.index_reg == 0)
7036 {
6c30d220 7037 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7038 /* <disp>(%esp) becomes two byte modrm with no index
7039 register. We've already stored the code for esp
7040 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7041 Any base register besides %esp will not use the
7042 extra modrm byte. */
7043 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7044 }
6c30d220 7045 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7046 {
db51cc60
L		 7047 if (i.index_reg->reg_num == RegEiz
7048 || i.index_reg->reg_num == RegRiz)
7049 i.sib.index = NO_INDEX_REGISTER;
7050 else
7051 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7052 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7053 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7054 i.rex |= REX_X;
29b0f896 7055 }
67a4f2b7
AO		 7056
7057 if (i.disp_operands
7058 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7059 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7060 i.rm.mode = 0;
7061 else
a501d77e
L		 7062 {
7063 if (!fake_zero_displacement
7064 && !i.disp_operands
7065 && i.disp_encoding)
7066 {
7067 fake_zero_displacement = 1;
7068 if (i.disp_encoding == disp_encoding_8bit)
7069 i.types[op].bitfield.disp8 = 1;
7070 else
7071 i.types[op].bitfield.disp32 = 1;
7072 }
7073 i.rm.mode = mode_from_disp_size (i.types[op]);
7074 }
29b0f896 7075 }
252b5132 7076
29b0f896
AM		 7077 if (fake_zero_displacement)
7078 {
7079 /* Fakes a zero displacement assuming that i.types[op]
7080 holds the correct displacement size. */
7081 expressionS *exp;
7082
9c2799c2 7083 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7084 exp = &disp_expressions[i.disp_operands++];
7085 i.op[op].disps = exp;
7086 exp->X_op = O_constant;
7087 exp->X_add_number = 0;
7088 exp->X_add_symbol = (symbolS *) 0;
7089 exp->X_op_symbol = (symbolS *) 0;
7090 }
c0f3af97
L		 7091
7092 mem = op;
29b0f896 7093 }
c0f3af97
L		 7094 else
7095 mem = ~0;
252b5132 7096
8c43a48b 7097 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7098 {
7099 if (operand_type_check (i.types[0], imm))
7100 i.vex.register_specifier = NULL;
7101 else
7102 {
7103 /* VEX.vvvv encodes one of the sources when the first
7104 operand is not an immediate. */
1ef99a7b 7105 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7106 i.vex.register_specifier = i.op[0].regs;
7107 else
7108 i.vex.register_specifier = i.op[1].regs;
7109 }
7110
7111 /* Destination is a XMM register encoded in the ModRM.reg
7112 and VEX.R bit. */
7113 i.rm.reg = i.op[2].regs->reg_num;
7114 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7115 i.rex |= REX_R;
7116
7117 /* ModRM.rm and VEX.B encodes the other source. */
7118 if (!i.mem_operands)
7119 {
7120 i.rm.mode = 3;
7121
1ef99a7b 7122 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7123 i.rm.regmem = i.op[1].regs->reg_num;
7124 else
7125 i.rm.regmem = i.op[0].regs->reg_num;
7126
7127 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7128 i.rex |= REX_B;
7129 }
7130 }
2426c15f 7131 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7132 {
7133 i.vex.register_specifier = i.op[2].regs;
7134 if (!i.mem_operands)
7135 {
7136 i.rm.mode = 3;
7137 i.rm.regmem = i.op[1].regs->reg_num;
7138 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7139 i.rex |= REX_B;
7140 }
7141 }
29b0f896
AM		 7142 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7143 (if any) based on i.tm.extension_opcode. Again, we must be
7144 careful to make sure that segment/control/debug/test/MMX
7145 registers are coded into the i.rm.reg field. */
f88c9eb0 7146 else if (i.reg_operands)
29b0f896 7147 {
99018f42 7148 unsigned int op;
7ab9ffdd
L		 7149 unsigned int vex_reg = ~0;
7150
7151 for (op = 0; op < i.operands; op++)
dc821c5f 7152 if (i.types[op].bitfield.reg
7ab9ffdd 7153 || i.types[op].bitfield.regmmx
1b54b8d7 7154 || i.types[op].bitfield.regsimd
7e8b059b 7155 || i.types[op].bitfield.regbnd
43234a1e 7156 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7157 || i.types[op].bitfield.sreg2
7158 || i.types[op].bitfield.sreg3
7159 || i.types[op].bitfield.control
7160 || i.types[op].bitfield.debug
7161 || i.types[op].bitfield.test)
7162 break;
c0209578 7163
7ab9ffdd
L		 7164 if (vex_3_sources)
7165 op = dest;
2426c15f 7166 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7167 {
7168 /* For instructions with VexNDS, the register-only
7169 source operand is encoded in VEX prefix. */
7170 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7171
7ab9ffdd 7172 if (op > mem)
c0f3af97 7173 {
7ab9ffdd
L		 7174 vex_reg = op++;
7175 gas_assert (op < i.operands);
c0f3af97
L		 7176 }
7177 else
c0f3af97 7178 {
f12dc422
L		 7179 /* Check register-only source operand when two source
7180 operands are swapped. */
7181 if (!i.tm.operand_types[op].bitfield.baseindex
7182 && i.tm.operand_types[op + 1].bitfield.baseindex)
7183 {
7184 vex_reg = op;
7185 op += 2;
7186 gas_assert (mem == (vex_reg + 1)
7187 && op < i.operands);
7188 }
7189 else
7190 {
7191 vex_reg = op + 1;
7192 gas_assert (vex_reg < i.operands);
7193 }
c0f3af97 7194 }
7ab9ffdd 7195 }
2426c15f 7196 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7197 {
f12dc422 7198 /* For instructions with VexNDD, the register destination
7ab9ffdd 7199 is encoded in VEX prefix. */
f12dc422
L		 7200 if (i.mem_operands == 0)
7201 {
7202 /* There is no memory operand. */
7203 gas_assert ((op + 2) == i.operands);
7204 vex_reg = op + 1;
7205 }
7206 else
8d63c93e 7207 {
f12dc422
L		 7208 /* There are only 2 operands. */
7209 gas_assert (op < 2 && i.operands == 2);
7210 vex_reg = 1;
7211 }
7ab9ffdd
L		 7212 }
7213 else
7214 gas_assert (op < i.operands);
99018f42 7215
7ab9ffdd
L		 7216 if (vex_reg != (unsigned int) ~0)
7217 {
f12dc422 7218 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7219
dc821c5f
JB		 7220 if ((!type->bitfield.reg
7221 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7222 && !type->bitfield.regsimd
43234a1e 7223 && !operand_type_equal (type, &regmask))
7ab9ffdd 7224 abort ();
f88c9eb0 7225
7ab9ffdd
L		 7226 i.vex.register_specifier = i.op[vex_reg].regs;
7227 }
7228
1b9f0c97
L		 7229 /* Don't set OP operand twice. */
7230 if (vex_reg != op)
7ab9ffdd 7231 {
1b9f0c97
L		 7232 /* If there is an extension opcode to put here, the
7233 register number must be put into the regmem field. */
7234 if (i.tm.extension_opcode != None)
7235 {
7236 i.rm.regmem = i.op[op].regs->reg_num;
7237 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7238 i.rex |= REX_B;
43234a1e
L		 7239 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7240 i.vrex |= REX_B;
1b9f0c97
L		 7241 }
7242 else
7243 {
7244 i.rm.reg = i.op[op].regs->reg_num;
7245 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7246 i.rex |= REX_R;
43234a1e
L		 7247 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7248 i.vrex |= REX_R;
1b9f0c97 7249 }
7ab9ffdd 7250 }
252b5132 7251
29b0f896
AM		 7252 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7253 must set it to 3 to indicate this is a register operand
7254 in the regmem field. */
7255 if (!i.mem_operands)
7256 i.rm.mode = 3;
7257 }
252b5132 7258
29b0f896 7259 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7260 if (i.tm.extension_opcode != None)
29b0f896
AM		 7261 i.rm.reg = i.tm.extension_opcode;
7262 }
7263 return default_seg;
7264}
252b5132 7265
29b0f896 7266static void
e3bb37b5 7267output_branch (void)
29b0f896
AM		 7268{
7269 char *p;
f8a5c266 7270 int size;
29b0f896
AM		 7271 int code16;
7272 int prefix;
7273 relax_substateT subtype;
7274 symbolS *sym;
7275 offsetT off;
7276
f8a5c266 7277 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7278 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7279
7280 prefix = 0;
7281 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7282 {
29b0f896
AM		 7283 prefix = 1;
7284 i.prefixes -= 1;
7285 code16 ^= CODE16;
252b5132 7286 }
29b0f896
AM		 7287 /* Pentium4 branch hints. */
7288 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7289 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7290 {
29b0f896
AM		 7291 prefix++;
7292 i.prefixes--;
7293 }
7294 if (i.prefix[REX_PREFIX] != 0)
7295 {
7296 prefix++;
7297 i.prefixes--;
2f66722d
AM		 7298 }
7299
7e8b059b
L		 7300 /* BND prefixed jump. */
7301 if (i.prefix[BND_PREFIX] != 0)
7302 {
7303 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7304 i.prefixes -= 1;
7305 }
7306
29b0f896
AM		 7307 if (i.prefixes != 0 && !intel_syntax)
7308 as_warn (_("skipping prefixes on this instruction"));
7309
7310 /* It's always a symbol; End frag & setup for relax.
7311 Make sure there is enough room in this frag for the largest
7312 instruction we may generate in md_convert_frag. This is 2
7313 bytes for the opcode and room for the prefix and largest
7314 displacement. */
7315 frag_grow (prefix + 2 + 4);
7316 /* Prefix and 1 opcode byte go in fr_fix. */
7317 p = frag_more (prefix + 1);
7318 if (i.prefix[DATA_PREFIX] != 0)
7319 *p++ = DATA_PREFIX_OPCODE;
7320 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7321 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7322 *p++ = i.prefix[SEG_PREFIX];
7323 if (i.prefix[REX_PREFIX] != 0)
7324 *p++ = i.prefix[REX_PREFIX];
7325 *p = i.tm.base_opcode;
7326
7327 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7328 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7329 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7330 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7331 else
f8a5c266 7332 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7333 subtype |= code16;
3e73aa7c 7334
29b0f896
AM		 7335 sym = i.op[0].disps->X_add_symbol;
7336 off = i.op[0].disps->X_add_number;
3e73aa7c 7337
29b0f896
AM		 7338 if (i.op[0].disps->X_op != O_constant
7339 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7340 {
29b0f896
AM		 7341 /* Handle complex expressions. */
7342 sym = make_expr_symbol (i.op[0].disps);
7343 off = 0;
7344 }
3e73aa7c 7345
29b0f896
AM		 7346 /* 1 possible extra opcode + 4 byte displacement go in var part.
7347 Pass reloc in fr_var. */
d258b828 7348 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7349}
3e73aa7c 7350
bd7ab16b
L		 7351#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7352/* Return TRUE iff PLT32 relocation should be used for branching to
7353 symbol S. */
7354
7355static bfd_boolean
7356need_plt32_p (symbolS *s)
7357{
7358 /* PLT32 relocation is ELF only. */
7359 if (!IS_ELF)
7360 return FALSE;
7361
7362 /* Since there is no need to prepare for PLT branch on x86-64, we
7363 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7364 be used as a marker for 32-bit PC-relative branches. */
7365 if (!object_64bit)
7366 return FALSE;
7367
7368 /* Weak or undefined symbol need PLT32 relocation. */
7369 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7370 return TRUE;
7371
7372 /* Non-global symbol doesn't need PLT32 relocation. */
7373 if (! S_IS_EXTERNAL (s))
7374 return FALSE;
7375
7376 /* Other global symbols need PLT32 relocation. NB: Symbol with
7377 non-default visibilities are treated as normal global symbol
7378 so that PLT32 relocation can be used as a marker for 32-bit
7379 PC-relative branches. It is useful for linker relaxation. */
7380 return TRUE;
7381}
7382#endif
7383
29b0f896 7384static void
e3bb37b5 7385output_jump (void)
29b0f896
AM		 7386{
7387 char *p;
7388 int size;
3e02c1cc 7389 fixS *fixP;
bd7ab16b 7390 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7391
40fb9820 7392 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7393 {
7394 /* This is a loop or jecxz type instruction. */
7395 size = 1;
7396 if (i.prefix[ADDR_PREFIX] != 0)
7397 {
7398 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7399 i.prefixes -= 1;
7400 }
7401 /* Pentium4 branch hints. */
7402 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7403 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7404 {
7405 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7406 i.prefixes--;
3e73aa7c
JH		 7407 }
7408 }
29b0f896
AM		 7409 else
7410 {
7411 int code16;
3e73aa7c 7412
29b0f896
AM		 7413 code16 = 0;
7414 if (flag_code == CODE_16BIT)
7415 code16 = CODE16;
3e73aa7c 7416
29b0f896
AM		 7417 if (i.prefix[DATA_PREFIX] != 0)
7418 {
7419 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7420 i.prefixes -= 1;
7421 code16 ^= CODE16;
7422 }
252b5132 7423
29b0f896
AM		 7424 size = 4;
7425 if (code16)
7426 size = 2;
7427 }
9fcc94b6 7428
29b0f896
AM		 7429 if (i.prefix[REX_PREFIX] != 0)
7430 {
7431 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7432 i.prefixes -= 1;
7433 }
252b5132 7434
7e8b059b
L		 7435 /* BND prefixed jump. */
7436 if (i.prefix[BND_PREFIX] != 0)
7437 {
7438 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7439 i.prefixes -= 1;
7440 }
7441
29b0f896
AM		 7442 if (i.prefixes != 0 && !intel_syntax)
7443 as_warn (_("skipping prefixes on this instruction"));
e0890092 7444
42164a71
L		 7445 p = frag_more (i.tm.opcode_length + size);
7446 switch (i.tm.opcode_length)
7447 {
7448 case 2:
7449 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7450 /* Fall through. */
42164a71
L		 7451 case 1:
7452 *p++ = i.tm.base_opcode;
7453 break;
7454 default:
7455 abort ();
7456 }
e0890092 7457
bd7ab16b
L		 7458#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7459 if (size == 4
7460 && jump_reloc == NO_RELOC
7461 && need_plt32_p (i.op[0].disps->X_add_symbol))
7462 jump_reloc = BFD_RELOC_X86_64_PLT32;
7463#endif
7464
7465 jump_reloc = reloc (size, 1, 1, jump_reloc);
7466
3e02c1cc 7467 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7468 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7469
7470 /* All jumps handled here are signed, but don't use a signed limit
7471 check for 32 and 16 bit jumps as we want to allow wrap around at
7472 4G and 64k respectively. */
7473 if (size == 1)
7474 fixP->fx_signed = 1;
29b0f896 7475}
e0890092 7476
29b0f896 7477static void
e3bb37b5 7478output_interseg_jump (void)
29b0f896
AM		 7479{
7480 char *p;
7481 int size;
7482 int prefix;
7483 int code16;
252b5132 7484
29b0f896
AM		 7485 code16 = 0;
7486 if (flag_code == CODE_16BIT)
7487 code16 = CODE16;
a217f122 7488
29b0f896
AM		 7489 prefix = 0;
7490 if (i.prefix[DATA_PREFIX] != 0)
7491 {
7492 prefix = 1;
7493 i.prefixes -= 1;
7494 code16 ^= CODE16;
7495 }
7496 if (i.prefix[REX_PREFIX] != 0)
7497 {
7498 prefix++;
7499 i.prefixes -= 1;
7500 }
252b5132 7501
29b0f896
AM		 7502 size = 4;
7503 if (code16)
7504 size = 2;
252b5132 7505
29b0f896
AM		 7506 if (i.prefixes != 0 && !intel_syntax)
7507 as_warn (_("skipping prefixes on this instruction"));
252b5132 7508
29b0f896
AM		 7509 /* 1 opcode; 2 segment; offset */
7510 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7511
29b0f896
AM		 7512 if (i.prefix[DATA_PREFIX] != 0)
7513 *p++ = DATA_PREFIX_OPCODE;
252b5132 7514
29b0f896
AM		 7515 if (i.prefix[REX_PREFIX] != 0)
7516 *p++ = i.prefix[REX_PREFIX];
252b5132 7517
29b0f896
AM		 7518 *p++ = i.tm.base_opcode;
7519 if (i.op[1].imms->X_op == O_constant)
7520 {
7521 offsetT n = i.op[1].imms->X_add_number;
252b5132 7522
29b0f896
AM		 7523 if (size == 2
7524 && !fits_in_unsigned_word (n)
7525 && !fits_in_signed_word (n))
7526 {
7527 as_bad (_("16-bit jump out of range"));
7528 return;
7529 }
7530 md_number_to_chars (p, n, size);
7531 }
7532 else
7533 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7534 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7535 if (i.op[0].imms->X_op != O_constant)
7536 as_bad (_("can't handle non absolute segment in `%s'"),
7537 i.tm.name);
7538 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7539}
a217f122 7540
29b0f896 7541static void
e3bb37b5 7542output_insn (void)
29b0f896 7543{
2bbd9c25
JJ		 7544 fragS *insn_start_frag;
7545 offsetT insn_start_off;
7546
29b0f896
AM		 7547 /* Tie dwarf2 debug info to the address at the start of the insn.
7548 We can't do this after the insn has been output as the current
7549 frag may have been closed off. eg. by frag_var. */
7550 dwarf2_emit_insn (0);
7551
2bbd9c25
JJ		 7552 insn_start_frag = frag_now;
7553 insn_start_off = frag_now_fix ();
7554
29b0f896 7555 /* Output jumps. */
40fb9820 7556 if (i.tm.opcode_modifier.jump)
29b0f896 7557 output_branch ();
40fb9820
L		 7558 else if (i.tm.opcode_modifier.jumpbyte
7559 || i.tm.opcode_modifier.jumpdword)
29b0f896 7560 output_jump ();
40fb9820 7561 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7562 output_interseg_jump ();
7563 else
7564 {
7565 /* Output normal instructions here. */
7566 char *p;
7567 unsigned char *q;
47465058 7568 unsigned int j;
331d2d0d 7569 unsigned int prefix;
4dffcebc 7570
e4e00185
AS		 7571 if (avoid_fence
7572 && i.tm.base_opcode == 0xfae
7573 && i.operands == 1
7574 && i.imm_operands == 1
7575 && (i.op[0].imms->X_add_number == 0xe8
7576 || i.op[0].imms->X_add_number == 0xf0
7577 || i.op[0].imms->X_add_number == 0xf8))
7578 {
7579 /* Encode lfence, mfence, and sfence as
7580 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7581 offsetT val = 0x240483f0ULL;
7582 p = frag_more (5);
7583 md_number_to_chars (p, val, 5);
7584 return;
7585 }
7586
d022bddd
IT		 7587 /* Some processors fail on LOCK prefix. This options makes
7588 assembler ignore LOCK prefix and serves as a workaround. */
7589 if (omit_lock_prefix)
7590 {
7591 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7592 return;
7593 i.prefix[LOCK_PREFIX] = 0;
7594 }
7595
43234a1e
L		 7596 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7597 don't need the explicit prefix. */
7598 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7599 {
c0f3af97 7600 switch (i.tm.opcode_length)
bc4bd9ab 7601 {
c0f3af97
L		 7602 case 3:
7603 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7604 {
c0f3af97
L		 7605 prefix = (i.tm.base_opcode >> 24) & 0xff;
7606 goto check_prefix;
7607 }
7608 break;
7609 case 2:
7610 if ((i.tm.base_opcode & 0xff0000) != 0)
7611 {
7612 prefix = (i.tm.base_opcode >> 16) & 0xff;
7613 if (i.tm.cpu_flags.bitfield.cpupadlock)
7614 {
4dffcebc 7615check_prefix:
c0f3af97 7616 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7617 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7618 != REPE_PREFIX_OPCODE))
7619 add_prefix (prefix);
7620 }
7621 else
4dffcebc
L		 7622 add_prefix (prefix);
7623 }
c0f3af97
L		 7624 break;
7625 case 1:
7626 break;
390c91cf
L		 7627 case 0:
7628 /* Check for pseudo prefixes. */
7629 as_bad_where (insn_start_frag->fr_file,
7630 insn_start_frag->fr_line,
7631 _("pseudo prefix without instruction"));
7632 return;
c0f3af97
L		 7633 default:
7634 abort ();
bc4bd9ab 7635 }
c0f3af97 7636
6d19a37a 7637#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7638 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7639 R_X86_64_GOTTPOFF relocation so that linker can safely
7640 perform IE->LE optimization. */
7641 if (x86_elf_abi == X86_64_X32_ABI
7642 && i.operands == 2
7643 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7644 && i.prefix[REX_PREFIX] == 0)
7645 add_prefix (REX_OPCODE);
6d19a37a 7646#endif
cf61b747 7647
c0f3af97
L		 7648 /* The prefix bytes. */
7649 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7650 if (*q)
7651 FRAG_APPEND_1_CHAR (*q);
0f10071e 7652 }
ae5c1c7b 7653 else
c0f3af97
L		 7654 {
7655 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7656 if (*q)
7657 switch (j)
7658 {
7659 case REX_PREFIX:
7660 /* REX byte is encoded in VEX prefix. */
7661 break;
7662 case SEG_PREFIX:
7663 case ADDR_PREFIX:
7664 FRAG_APPEND_1_CHAR (*q);
7665 break;
7666 default:
7667 /* There should be no other prefixes for instructions
7668 with VEX prefix. */
7669 abort ();
7670 }
7671
43234a1e
L		 7672 /* For EVEX instructions i.vrex should become 0 after
7673 build_evex_prefix. For VEX instructions upper 16 registers
7674 aren't available, so VREX should be 0. */
7675 if (i.vrex)
7676 abort ();
c0f3af97
L		 7677 /* Now the VEX prefix. */
7678 p = frag_more (i.vex.length);
7679 for (j = 0; j < i.vex.length; j++)
7680 p[j] = i.vex.bytes[j];
7681 }
252b5132 7682
29b0f896 7683 /* Now the opcode; be careful about word order here! */
4dffcebc 7684 if (i.tm.opcode_length == 1)
29b0f896
AM		 7685 {
7686 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7687 }
7688 else
7689 {
4dffcebc 7690 switch (i.tm.opcode_length)
331d2d0d 7691 {
43234a1e
L		 7692 case 4:
7693 p = frag_more (4);
7694 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7695 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7696 break;
4dffcebc 7697 case 3:
331d2d0d
L		 7698 p = frag_more (3);
7699 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7700 break;
7701 case 2:
7702 p = frag_more (2);
7703 break;
7704 default:
7705 abort ();
7706 break;
331d2d0d 7707 }
0f10071e 7708
29b0f896
AM		 7709 /* Put out high byte first: can't use md_number_to_chars! */
7710 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7711 *p = i.tm.base_opcode & 0xff;
7712 }
3e73aa7c 7713
29b0f896 7714 /* Now the modrm byte and sib byte (if present). */
40fb9820 7715 if (i.tm.opcode_modifier.modrm)
29b0f896 7716 {
4a3523fa
L		 7717 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7718 | i.rm.reg << 3
7719 | i.rm.mode << 6));
29b0f896
AM		 7720 /* If i.rm.regmem == ESP (4)
7721 && i.rm.mode != (Register mode)
7722 && not 16 bit
7723 ==> need second modrm byte. */
7724 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7725 && i.rm.mode != 3
dc821c5f 7726 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7727 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7728 | i.sib.index << 3
7729 | i.sib.scale << 6));
29b0f896 7730 }
3e73aa7c 7731
29b0f896 7732 if (i.disp_operands)
2bbd9c25 7733 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7734
29b0f896 7735 if (i.imm_operands)
2bbd9c25 7736 output_imm (insn_start_frag, insn_start_off);
29b0f896 7737 }
252b5132 7738
29b0f896
AM		 7739#ifdef DEBUG386
7740 if (flag_debug)
7741 {
7b81dfbb 7742 pi ("" /*line*/, &i);
29b0f896
AM		 7743 }
7744#endif /* DEBUG386 */
7745}
252b5132 7746
e205caa7
L		 7747/* Return the size of the displacement operand N. */
7748
7749static int
7750disp_size (unsigned int n)
7751{
7752 int size = 4;
43234a1e 7753
b5014f7a 7754 if (i.types[n].bitfield.disp64)
40fb9820
L		 7755 size = 8;
7756 else if (i.types[n].bitfield.disp8)
7757 size = 1;
7758 else if (i.types[n].bitfield.disp16)
7759 size = 2;
e205caa7
L		 7760 return size;
7761}
7762
7763/* Return the size of the immediate operand N. */
7764
7765static int
7766imm_size (unsigned int n)
7767{
7768 int size = 4;
40fb9820
L		 7769 if (i.types[n].bitfield.imm64)
7770 size = 8;
7771 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7772 size = 1;
7773 else if (i.types[n].bitfield.imm16)
7774 size = 2;
e205caa7
L		 7775 return size;
7776}
7777
29b0f896 7778static void
64e74474 7779output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7780{
7781 char *p;
7782 unsigned int n;
252b5132 7783
29b0f896
AM		 7784 for (n = 0; n < i.operands; n++)
7785 {
b5014f7a 7786 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7787 {
7788 if (i.op[n].disps->X_op == O_constant)
7789 {
e205caa7 7790 int size = disp_size (n);
43234a1e 7791 offsetT val = i.op[n].disps->X_add_number;
252b5132 7792
b5014f7a 7793 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7794 p = frag_more (size);
7795 md_number_to_chars (p, val, size);
7796 }
7797 else
7798 {
f86103b7 7799 enum bfd_reloc_code_real reloc_type;
e205caa7 7800 int size = disp_size (n);
40fb9820 7801 int sign = i.types[n].bitfield.disp32s;
29b0f896 7802 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7803 fixS *fixP;
29b0f896 7804
e205caa7 7805 /* We can't have 8 bit displacement here. */
9c2799c2 7806 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7807
29b0f896
AM		 7808 /* The PC relative address is computed relative
7809 to the instruction boundary, so in case immediate
7810 fields follows, we need to adjust the value. */
7811 if (pcrel && i.imm_operands)
7812 {
29b0f896 7813 unsigned int n1;
e205caa7 7814 int sz = 0;
252b5132 7815
29b0f896 7816 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7817 if (operand_type_check (i.types[n1], imm))
252b5132 7818 {
e205caa7
L		 7819 /* Only one immediate is allowed for PC
7820 relative address. */
9c2799c2 7821 gas_assert (sz == 0);
e205caa7
L		 7822 sz = imm_size (n1);
7823 i.op[n].disps->X_add_number -= sz;
252b5132 7824 }
29b0f896 7825 /* We should find the immediate. */
9c2799c2 7826 gas_assert (sz != 0);
29b0f896 7827 }
520dc8e8 7828
29b0f896 7829 p = frag_more (size);
d258b828 7830 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7831 if (GOT_symbol
2bbd9c25 7832 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7833 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7834 || reloc_type == BFD_RELOC_X86_64_32S
7835 || (reloc_type == BFD_RELOC_64
7836 && object_64bit))
d6ab8113
JB		 7837 && (i.op[n].disps->X_op == O_symbol
7838 || (i.op[n].disps->X_op == O_add
7839 && ((symbol_get_value_expression
7840 (i.op[n].disps->X_op_symbol)->X_op)
7841 == O_subtract))))
7842 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7843 {
7844 offsetT add;
7845
7846 if (insn_start_frag == frag_now)
7847 add = (p - frag_now->fr_literal) - insn_start_off;
7848 else
7849 {
7850 fragS *fr;
7851
7852 add = insn_start_frag->fr_fix - insn_start_off;
7853 for (fr = insn_start_frag->fr_next;
7854 fr && fr != frag_now; fr = fr->fr_next)
7855 add += fr->fr_fix;
7856 add += p - frag_now->fr_literal;
7857 }
7858
4fa24527 7859 if (!object_64bit)
7b81dfbb
AJ		 7860 {
7861 reloc_type = BFD_RELOC_386_GOTPC;
7862 i.op[n].imms->X_add_number += add;
7863 }
7864 else if (reloc_type == BFD_RELOC_64)
7865 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7866 else
7b81dfbb
AJ		 7867 /* Don't do the adjustment for x86-64, as there
7868 the pcrel addressing is relative to the _next_
7869 insn, and that is taken care of in other code. */
d6ab8113 7870 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7871 }
02a86693
L		 7872 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7873 size, i.op[n].disps, pcrel,
7874 reloc_type);
7875 /* Check for "call/jmp *mem", "mov mem, %reg",
7876 "test %reg, mem" and "binop mem, %reg" where binop
7877 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7878 instructions. Always generate R_386_GOT32X for
7879 "sym*GOT" operand in 32-bit mode. */
7880 if ((generate_relax_relocations
7881 || (!object_64bit
7882 && i.rm.mode == 0
7883 && i.rm.regmem == 5))
7884 && (i.rm.mode == 2
7885 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7886 && ((i.operands == 1
7887 && i.tm.base_opcode == 0xff
7888 && (i.rm.reg == 2 || i.rm.reg == 4))
7889 || (i.operands == 2
7890 && (i.tm.base_opcode == 0x8b
7891 || i.tm.base_opcode == 0x85
7892 || (i.tm.base_opcode & 0xc7) == 0x03))))
7893 {
7894 if (object_64bit)
7895 {
7896 fixP->fx_tcbit = i.rex != 0;
7897 if (i.base_reg
7898 && (i.base_reg->reg_num == RegRip
7899 || i.base_reg->reg_num == RegEip))
7900 fixP->fx_tcbit2 = 1;
7901 }
7902 else
7903 fixP->fx_tcbit2 = 1;
7904 }
29b0f896
AM		 7905 }
7906 }
7907 }
7908}
252b5132 7909
29b0f896 7910static void
64e74474 7911output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7912{
7913 char *p;
7914 unsigned int n;
252b5132 7915
29b0f896
AM		 7916 for (n = 0; n < i.operands; n++)
7917 {
43234a1e
L		 7918 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7919 if (i.rounding && (int) n == i.rounding->operand)
7920 continue;
7921
40fb9820 7922 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7923 {
7924 if (i.op[n].imms->X_op == O_constant)
7925 {
e205caa7 7926 int size = imm_size (n);
29b0f896 7927 offsetT val;
b4cac588 7928
29b0f896
AM		 7929 val = offset_in_range (i.op[n].imms->X_add_number,
7930 size);
7931 p = frag_more (size);
7932 md_number_to_chars (p, val, size);
7933 }
7934 else
7935 {
7936 /* Not absolute_section.
7937 Need a 32-bit fixup (don't support 8bit
7938 non-absolute imms). Try to support other
7939 sizes ... */
f86103b7 7940 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7941 int size = imm_size (n);
7942 int sign;
29b0f896 7943
40fb9820 7944 if (i.types[n].bitfield.imm32s
a7d61044 7945 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7946 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7947 sign = 1;
e205caa7
L		 7948 else
7949 sign = 0;
520dc8e8 7950
29b0f896 7951 p = frag_more (size);
d258b828 7952 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7953
2bbd9c25
JJ		 7954 /* This is tough to explain. We end up with this one if we
7955 * have operands that look like
7956 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7957 * obtain the absolute address of the GOT, and it is strongly
7958 * preferable from a performance point of view to avoid using
7959 * a runtime relocation for this. The actual sequence of
7960 * instructions often look something like:
7961 *
7962 * call .L66
7963 * .L66:
7964 * popl %ebx
7965 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7966 *
7967 * The call and pop essentially return the absolute address
7968 * of the label .L66 and store it in %ebx. The linker itself
7969 * will ultimately change the first operand of the addl so
7970 * that %ebx points to the GOT, but to keep things simple, the
7971 * .o file must have this operand set so that it generates not
7972 * the absolute address of .L66, but the absolute address of
7973 * itself. This allows the linker itself simply treat a GOTPC
7974 * relocation as asking for a pcrel offset to the GOT to be
7975 * added in, and the addend of the relocation is stored in the
7976 * operand field for the instruction itself.
7977 *
7978 * Our job here is to fix the operand so that it would add
7979 * the correct offset so that %ebx would point to itself. The
7980 * thing that is tricky is that .-.L66 will point to the
7981 * beginning of the instruction, so we need to further modify
7982 * the operand so that it will point to itself. There are
7983 * other cases where you have something like:
7984 *
7985 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7986 *
7987 * and here no correction would be required. Internally in
7988 * the assembler we treat operands of this form as not being
7989 * pcrel since the '.' is explicitly mentioned, and I wonder
7990 * whether it would simplify matters to do it this way. Who
7991 * knows. In earlier versions of the PIC patches, the
7992 * pcrel_adjust field was used to store the correction, but
7993 * since the expression is not pcrel, I felt it would be
7994 * confusing to do it this way. */
7995
d6ab8113 7996 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7997 || reloc_type == BFD_RELOC_X86_64_32S
7998 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7999 && GOT_symbol
8000 && GOT_symbol == i.op[n].imms->X_add_symbol
8001 && (i.op[n].imms->X_op == O_symbol
8002 || (i.op[n].imms->X_op == O_add
8003 && ((symbol_get_value_expression
8004 (i.op[n].imms->X_op_symbol)->X_op)
8005 == O_subtract))))
8006 {
2bbd9c25
JJ		 8007 offsetT add;
8008
8009 if (insn_start_frag == frag_now)
8010 add = (p - frag_now->fr_literal) - insn_start_off;
8011 else
8012 {
8013 fragS *fr;
8014
8015 add = insn_start_frag->fr_fix - insn_start_off;
8016 for (fr = insn_start_frag->fr_next;
8017 fr && fr != frag_now; fr = fr->fr_next)
8018 add += fr->fr_fix;
8019 add += p - frag_now->fr_literal;
8020 }
8021
4fa24527 8022 if (!object_64bit)
d6ab8113 8023 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8024 else if (size == 4)
d6ab8113 8025 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8026 else if (size == 8)
8027 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8028 i.op[n].imms->X_add_number += add;
29b0f896 8029 }
29b0f896
AM		 8030 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8031 i.op[n].imms, 0, reloc_type);
8032 }
8033 }
8034 }
252b5132
RH		 8035}
8036\f
d182319b
JB		 8037/* x86_cons_fix_new is called via the expression parsing code when a
8038 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8039static int cons_sign = -1;
8040
8041void
e3bb37b5 8042x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8043 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8044{
d258b828 8045 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8046
8047#ifdef TE_PE
8048 if (exp->X_op == O_secrel)
8049 {
8050 exp->X_op = O_symbol;
8051 r = BFD_RELOC_32_SECREL;
8052 }
8053#endif
8054
8055 fix_new_exp (frag, off, len, exp, 0, r);
8056}
8057
357d1bd8
L		 8058/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8059 purpose of the `.dc.a' internal pseudo-op. */
8060
8061int
8062x86_address_bytes (void)
8063{
8064 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8065 return 4;
8066 return stdoutput->arch_info->bits_per_address / 8;
8067}
8068
d382c579
TG		 8069#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8070 || defined (LEX_AT)
d258b828 8071# define lex_got(reloc, adjust, types) NULL
718ddfc0 8072#else
f3c180ae
AM		 8073/* Parse operands of the form
8074 <symbol>@GOTOFF+<nnn>
8075 and similar .plt or .got references.
8076
8077 If we find one, set up the correct relocation in RELOC and copy the
8078 input string, minus the `@GOTOFF' into a malloc'd buffer for
8079 parsing by the calling routine. Return this buffer, and if ADJUST
8080 is non-null set it to the length of the string we removed from the
8081 input line. Otherwise return NULL. */
8082static char *
91d6fa6a 8083lex_got (enum bfd_reloc_code_real *rel,
64e74474 8084 int *adjust,
d258b828 8085 i386_operand_type *types)
f3c180ae 8086{
7b81dfbb
AJ		 8087 /* Some of the relocations depend on the size of what field is to
8088 be relocated. But in our callers i386_immediate and i386_displacement
8089 we don't yet know the operand size (this will be set by insn
8090 matching). Hence we record the word32 relocation here,
8091 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8092 static const struct {
8093 const char *str;
cff8d58a 8094 int len;
4fa24527 8095 const enum bfd_reloc_code_real rel[2];
40fb9820 8096 const i386_operand_type types64;
f3c180ae 8097 } gotrel[] = {
8ce3d284 8098#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8099 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8100 BFD_RELOC_SIZE32 },
8101 OPERAND_TYPE_IMM32_64 },
8ce3d284 8102#endif
cff8d58a
L		 8103 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8104 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8105 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8106 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8107 BFD_RELOC_X86_64_PLT32 },
40fb9820 8108 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8109 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8110 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8111 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8112 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8113 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8114 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8115 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8116 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8117 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8118 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8119 BFD_RELOC_X86_64_TLSGD },
40fb9820 8120 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8121 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8122 _dummy_first_bfd_reloc_code_real },
40fb9820 8123 OPERAND_TYPE_NONE },
cff8d58a
L		 8124 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8125 BFD_RELOC_X86_64_TLSLD },
40fb9820 8126 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8127 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8128 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8129 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8130 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8131 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8132 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8133 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8134 _dummy_first_bfd_reloc_code_real },
40fb9820 8135 OPERAND_TYPE_NONE },
cff8d58a
L		 8136 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8137 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8138 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8139 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8140 _dummy_first_bfd_reloc_code_real },
40fb9820 8141 OPERAND_TYPE_NONE },
cff8d58a
L		 8142 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8143 _dummy_first_bfd_reloc_code_real },
40fb9820 8144 OPERAND_TYPE_NONE },
cff8d58a
L		 8145 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8146 BFD_RELOC_X86_64_GOT32 },
40fb9820 8147 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8148 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8149 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8150 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8151 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8152 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8153 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8154 };
8155 char *cp;
8156 unsigned int j;
8157
d382c579 8158#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8159 if (!IS_ELF)
8160 return NULL;
d382c579 8161#endif
718ddfc0 8162
f3c180ae 8163 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8164 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8165 return NULL;
8166
47465058 8167 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8168 {
cff8d58a 8169 int len = gotrel[j].len;
28f81592 8170 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8171 {
4fa24527 8172 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8173 {
28f81592
AM		 8174 int first, second;
8175 char *tmpbuf, *past_reloc;
f3c180ae 8176
91d6fa6a 8177 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8178
3956db08
JB		 8179 if (types)
8180 {
8181 if (flag_code != CODE_64BIT)
40fb9820
L		 8182 {
8183 types->bitfield.imm32 = 1;
8184 types->bitfield.disp32 = 1;
8185 }
3956db08
JB		 8186 else
8187 *types = gotrel[j].types64;
8188 }
8189
8fd4256d 8190 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8191 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8192
28f81592 8193 /* The length of the first part of our input line. */
f3c180ae 8194 first = cp - input_line_pointer;
28f81592
AM		 8195
8196 /* The second part goes from after the reloc token until
67c11a9b 8197 (and including) an end_of_line char or comma. */
28f81592 8198 past_reloc = cp + 1 + len;
67c11a9b
AM		 8199 cp = past_reloc;
8200 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8201 ++cp;
8202 second = cp + 1 - past_reloc;
28f81592
AM		 8203
8204 /* Allocate and copy string. The trailing NUL shouldn't
8205 be necessary, but be safe. */
add39d23 8206 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8207 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8208 if (second != 0 && *past_reloc != ' ')
8209 /* Replace the relocation token with ' ', so that
8210 errors like foo@GOTOFF1 will be detected. */
8211 tmpbuf[first++] = ' ';
af89796a
L		 8212 else
8213 /* Increment length by 1 if the relocation token is
8214 removed. */
8215 len++;
8216 if (adjust)
8217 *adjust = len;
0787a12d
AM		 8218 memcpy (tmpbuf + first, past_reloc, second);
8219 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8220 return tmpbuf;
8221 }
8222
4fa24527
JB		 8223 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8224 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8225 return NULL;
8226 }
8227 }
8228
8229 /* Might be a symbol version string. Don't as_bad here. */
8230 return NULL;
8231}
4e4f7c87 8232#endif
f3c180ae 8233
a988325c
NC		 8234#ifdef TE_PE
8235#ifdef lex_got
8236#undef lex_got
8237#endif
8238/* Parse operands of the form
8239 <symbol>@SECREL32+<nnn>
8240
8241 If we find one, set up the correct relocation in RELOC and copy the
8242 input string, minus the `@SECREL32' into a malloc'd buffer for
8243 parsing by the calling routine. Return this buffer, and if ADJUST
8244 is non-null set it to the length of the string we removed from the
34bca508
L		 8245 input line. Otherwise return NULL.
8246
a988325c
NC		 8247 This function is copied from the ELF version above adjusted for PE targets. */
8248
8249static char *
8250lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8251 int *adjust ATTRIBUTE_UNUSED,
d258b828 8252 i386_operand_type *types)
a988325c
NC		 8253{
8254 static const struct
8255 {
8256 const char *str;
8257 int len;
8258 const enum bfd_reloc_code_real rel[2];
8259 const i386_operand_type types64;
8260 }
8261 gotrel[] =
8262 {
8263 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8264 BFD_RELOC_32_SECREL },
8265 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8266 };
8267
8268 char *cp;
8269 unsigned j;
8270
8271 for (cp = input_line_pointer; *cp != '@'; cp++)
8272 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8273 return NULL;
8274
8275 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8276 {
8277 int len = gotrel[j].len;
8278
8279 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8280 {
8281 if (gotrel[j].rel[object_64bit] != 0)
8282 {
8283 int first, second;
8284 char *tmpbuf, *past_reloc;
8285
8286 *rel = gotrel[j].rel[object_64bit];
8287 if (adjust)
8288 *adjust = len;
8289
8290 if (types)
8291 {
8292 if (flag_code != CODE_64BIT)
8293 {
8294 types->bitfield.imm32 = 1;
8295 types->bitfield.disp32 = 1;
8296 }
8297 else
8298 *types = gotrel[j].types64;
8299 }
8300
8301 /* The length of the first part of our input line. */
8302 first = cp - input_line_pointer;
8303
8304 /* The second part goes from after the reloc token until
8305 (and including) an end_of_line char or comma. */
8306 past_reloc = cp + 1 + len;
8307 cp = past_reloc;
8308 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8309 ++cp;
8310 second = cp + 1 - past_reloc;
8311
8312 /* Allocate and copy string. The trailing NUL shouldn't
8313 be necessary, but be safe. */
add39d23 8314 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8315 memcpy (tmpbuf, input_line_pointer, first);
8316 if (second != 0 && *past_reloc != ' ')
8317 /* Replace the relocation token with ' ', so that
8318 errors like foo@SECLREL321 will be detected. */
8319 tmpbuf[first++] = ' ';
8320 memcpy (tmpbuf + first, past_reloc, second);
8321 tmpbuf[first + second] = '\0';
8322 return tmpbuf;
8323 }
8324
8325 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8326 gotrel[j].str, 1 << (5 + object_64bit));
8327 return NULL;
8328 }
8329 }
8330
8331 /* Might be a symbol version string. Don't as_bad here. */
8332 return NULL;
8333}
8334
8335#endif /* TE_PE */
8336
62ebcb5c 8337bfd_reloc_code_real_type
e3bb37b5 8338x86_cons (expressionS *exp, int size)
f3c180ae 8339{
62ebcb5c
AM		 8340 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8341
ee86248c
JB		 8342 intel_syntax = -intel_syntax;
8343
3c7b9c2c 8344 exp->X_md = 0;
4fa24527 8345 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8346 {
8347 /* Handle @GOTOFF and the like in an expression. */
8348 char *save;
8349 char *gotfree_input_line;
4a57f2cf 8350 int adjust = 0;
f3c180ae
AM		 8351
8352 save = input_line_pointer;
d258b828 8353 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8354 if (gotfree_input_line)
8355 input_line_pointer = gotfree_input_line;
8356
8357 expression (exp);
8358
8359 if (gotfree_input_line)
8360 {
8361 /* expression () has merrily parsed up to the end of line,
8362 or a comma - in the wrong buffer. Transfer how far
8363 input_line_pointer has moved to the right buffer. */
8364 input_line_pointer = (save
8365 + (input_line_pointer - gotfree_input_line)
8366 + adjust);
8367 free (gotfree_input_line);
3992d3b7
AM		 8368 if (exp->X_op == O_constant
8369 || exp->X_op == O_absent
8370 || exp->X_op == O_illegal
0398aac5 8371 || exp->X_op == O_register
3992d3b7
AM		 8372 || exp->X_op == O_big)
8373 {
8374 char c = *input_line_pointer;
8375 *input_line_pointer = 0;
8376 as_bad (_("missing or invalid expression `%s'"), save);
8377 *input_line_pointer = c;
8378 }
f3c180ae
AM		 8379 }
8380 }
8381 else
8382 expression (exp);
ee86248c
JB		 8383
8384 intel_syntax = -intel_syntax;
8385
8386 if (intel_syntax)
8387 i386_intel_simplify (exp);
62ebcb5c
AM		 8388
8389 return got_reloc;
f3c180ae 8390}
f3c180ae 8391
9f32dd5b
L		 8392static void
8393signed_cons (int size)
6482c264 8394{
d182319b
JB		 8395 if (flag_code == CODE_64BIT)
8396 cons_sign = 1;
8397 cons (size);
8398 cons_sign = -1;
6482c264
NC		 8399}
8400
d182319b 8401#ifdef TE_PE
6482c264 8402static void
7016a5d5 8403pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8404{
8405 expressionS exp;
8406
8407 do
8408 {
8409 expression (&exp);
8410 if (exp.X_op == O_symbol)
8411 exp.X_op = O_secrel;
8412
8413 emit_expr (&exp, 4);
8414 }
8415 while (*input_line_pointer++ == ',');
8416
8417 input_line_pointer--;
8418 demand_empty_rest_of_line ();
8419}
6482c264
NC		 8420#endif
8421
43234a1e
L		 8422/* Handle Vector operations. */
8423
8424static char *
8425check_VecOperations (char *op_string, char *op_end)
8426{
8427 const reg_entry *mask;
8428 const char *saved;
8429 char *end_op;
8430
8431 while (*op_string
8432 && (op_end == NULL || op_string < op_end))
8433 {
8434 saved = op_string;
8435 if (*op_string == '{')
8436 {
8437 op_string++;
8438
8439 /* Check broadcasts. */
8440 if (strncmp (op_string, "1to", 3) == 0)
8441 {
8442 int bcst_type;
8443
8444 if (i.broadcast)
8445 goto duplicated_vec_op;
8446
8447 op_string += 3;
8448 if (*op_string == '8')
8449 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8450 else if (*op_string == '4')
8451 bcst_type = BROADCAST_1TO4;
8452 else if (*op_string == '2')
8453 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8454 else if (*op_string == '1'
8455 && *(op_string+1) == '6')
8456 {
8457 bcst_type = BROADCAST_1TO16;
8458 op_string++;
8459 }
8460 else
8461 {
8462 as_bad (_("Unsupported broadcast: `%s'"), saved);
8463 return NULL;
8464 }
8465 op_string++;
8466
8467 broadcast_op.type = bcst_type;
8468 broadcast_op.operand = this_operand;
8469 i.broadcast = &broadcast_op;
8470 }
8471 /* Check masking operation. */
8472 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8473 {
8474 /* k0 can't be used for write mask. */
6d2cd6b2 8475 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8476 {
6d2cd6b2
JB		 8477 as_bad (_("`%s%s' can't be used for write mask"),
8478 register_prefix, mask->reg_name);
43234a1e
L		 8479 return NULL;
8480 }
8481
8482 if (!i.mask)
8483 {
8484 mask_op.mask = mask;
8485 mask_op.zeroing = 0;
8486 mask_op.operand = this_operand;
8487 i.mask = &mask_op;
8488 }
8489 else
8490 {
8491 if (i.mask->mask)
8492 goto duplicated_vec_op;
8493
8494 i.mask->mask = mask;
8495
8496 /* Only "{z}" is allowed here. No need to check
8497 zeroing mask explicitly. */
8498 if (i.mask->operand != this_operand)
8499 {
8500 as_bad (_("invalid write mask `%s'"), saved);
8501 return NULL;
8502 }
8503 }
8504
8505 op_string = end_op;
8506 }
8507 /* Check zeroing-flag for masking operation. */
8508 else if (*op_string == 'z')
8509 {
8510 if (!i.mask)
8511 {
8512 mask_op.mask = NULL;
8513 mask_op.zeroing = 1;
8514 mask_op.operand = this_operand;
8515 i.mask = &mask_op;
8516 }
8517 else
8518 {
8519 if (i.mask->zeroing)
8520 {
8521 duplicated_vec_op:
8522 as_bad (_("duplicated `%s'"), saved);
8523 return NULL;
8524 }
8525
8526 i.mask->zeroing = 1;
8527
8528 /* Only "{%k}" is allowed here. No need to check mask
8529 register explicitly. */
8530 if (i.mask->operand != this_operand)
8531 {
8532 as_bad (_("invalid zeroing-masking `%s'"),
8533 saved);
8534 return NULL;
8535 }
8536 }
8537
8538 op_string++;
8539 }
8540 else
8541 goto unknown_vec_op;
8542
8543 if (*op_string != '}')
8544 {
8545 as_bad (_("missing `}' in `%s'"), saved);
8546 return NULL;
8547 }
8548 op_string++;
8549 continue;
8550 }
8551 unknown_vec_op:
8552 /* We don't know this one. */
8553 as_bad (_("unknown vector operation: `%s'"), saved);
8554 return NULL;
8555 }
8556
6d2cd6b2
JB		 8557 if (i.mask && i.mask->zeroing && !i.mask->mask)
8558 {
8559 as_bad (_("zeroing-masking only allowed with write mask"));
8560 return NULL;
8561 }
8562
43234a1e
L		 8563 return op_string;
8564}
8565
252b5132 8566static int
70e41ade 8567i386_immediate (char *imm_start)
252b5132
RH		 8568{
8569 char *save_input_line_pointer;
f3c180ae 8570 char *gotfree_input_line;
252b5132 8571 segT exp_seg = 0;
47926f60 8572 expressionS *exp;
40fb9820
L		 8573 i386_operand_type types;
8574
0dfbf9d7 8575 operand_type_set (&types, ~0);
252b5132
RH		 8576
8577 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8578 {
31b2323c
L		 8579 as_bad (_("at most %d immediate operands are allowed"),
8580 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8581 return 0;
8582 }
8583
8584 exp = &im_expressions[i.imm_operands++];
520dc8e8 8585 i.op[this_operand].imms = exp;
252b5132
RH		 8586
8587 if (is_space_char (*imm_start))
8588 ++imm_start;
8589
8590 save_input_line_pointer = input_line_pointer;
8591 input_line_pointer = imm_start;
8592
d258b828 8593 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8594 if (gotfree_input_line)
8595 input_line_pointer = gotfree_input_line;
252b5132
RH		 8596
8597 exp_seg = expression (exp);
8598
83183c0c 8599 SKIP_WHITESPACE ();
43234a1e
L		 8600
8601 /* Handle vector operations. */
8602 if (*input_line_pointer == '{')
8603 {
8604 input_line_pointer = check_VecOperations (input_line_pointer,
8605 NULL);
8606 if (input_line_pointer == NULL)
8607 return 0;
8608 }
8609
252b5132 8610 if (*input_line_pointer)
f3c180ae 8611 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8612
8613 input_line_pointer = save_input_line_pointer;
f3c180ae 8614 if (gotfree_input_line)
ee86248c
JB		 8615 {
8616 free (gotfree_input_line);
8617
8618 if (exp->X_op == O_constant || exp->X_op == O_register)
8619 exp->X_op = O_illegal;
8620 }
8621
8622 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8623}
252b5132 8624
ee86248c
JB		 8625static int
8626i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8627 i386_operand_type types, const char *imm_start)
8628{
8629 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8630 {
313c53d1
L		 8631 if (imm_start)
8632 as_bad (_("missing or invalid immediate expression `%s'"),
8633 imm_start);
3992d3b7 8634 return 0;
252b5132 8635 }
3e73aa7c 8636 else if (exp->X_op == O_constant)
252b5132 8637 {
47926f60 8638 /* Size it properly later. */
40fb9820 8639 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8640 /* If not 64bit, sign extend val. */
8641 if (flag_code != CODE_64BIT
4eed87de
AM		 8642 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8643 exp->X_add_number
8644 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8645 }
4c63da97 8646#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8647 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8648 && exp_seg != absolute_section
47926f60 8649 && exp_seg != text_section
24eab124
AM		 8650 && exp_seg != data_section
8651 && exp_seg != bss_section
8652 && exp_seg != undefined_section
f86103b7 8653 && !bfd_is_com_section (exp_seg))
252b5132 8654 {
d0b47220 8655 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8656 return 0;
8657 }
8658#endif
a841bdf5 8659 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8660 {
313c53d1
L		 8661 if (imm_start)
8662 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8663 return 0;
8664 }
252b5132
RH		 8665 else
8666 {
8667 /* This is an address. The size of the address will be
24eab124 8668 determined later, depending on destination register,
3e73aa7c 8669 suffix, or the default for the section. */
40fb9820
L		 8670 i.types[this_operand].bitfield.imm8 = 1;
8671 i.types[this_operand].bitfield.imm16 = 1;
8672 i.types[this_operand].bitfield.imm32 = 1;
8673 i.types[this_operand].bitfield.imm32s = 1;
8674 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8675 i.types[this_operand] = operand_type_and (i.types[this_operand],
8676 types);
252b5132
RH		 8677 }
8678
8679 return 1;
8680}
8681
551c1ca1 8682static char *
e3bb37b5 8683i386_scale (char *scale)
252b5132 8684{
551c1ca1
AM		 8685 offsetT val;
8686 char *save = input_line_pointer;
252b5132 8687
551c1ca1
AM		 8688 input_line_pointer = scale;
8689 val = get_absolute_expression ();
8690
8691 switch (val)
252b5132 8692 {
551c1ca1 8693 case 1:
252b5132
RH		 8694 i.log2_scale_factor = 0;
8695 break;
551c1ca1 8696 case 2:
252b5132
RH		 8697 i.log2_scale_factor = 1;
8698 break;
551c1ca1 8699 case 4:
252b5132
RH		 8700 i.log2_scale_factor = 2;
8701 break;
551c1ca1 8702 case 8:
252b5132
RH		 8703 i.log2_scale_factor = 3;
8704 break;
8705 default:
a724f0f4
JB		 8706 {
8707 char sep = *input_line_pointer;
8708
8709 *input_line_pointer = '\0';
8710 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8711 scale);
8712 *input_line_pointer = sep;
8713 input_line_pointer = save;
8714 return NULL;
8715 }
252b5132 8716 }
29b0f896 8717 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8718 {
8719 as_warn (_("scale factor of %d without an index register"),
24eab124 8720 1 << i.log2_scale_factor);
252b5132 8721 i.log2_scale_factor = 0;
252b5132 8722 }
551c1ca1
AM		 8723 scale = input_line_pointer;
8724 input_line_pointer = save;
8725 return scale;
252b5132
RH		 8726}
8727
252b5132 8728static int
e3bb37b5 8729i386_displacement (char *disp_start, char *disp_end)
252b5132 8730{
29b0f896 8731 expressionS *exp;
252b5132
RH		 8732 segT exp_seg = 0;
8733 char *save_input_line_pointer;
f3c180ae 8734 char *gotfree_input_line;
40fb9820
L		 8735 int override;
8736 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8737 int ret;
252b5132 8738
31b2323c
L		 8739 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8740 {
8741 as_bad (_("at most %d displacement operands are allowed"),
8742 MAX_MEMORY_OPERANDS);
8743 return 0;
8744 }
8745
0dfbf9d7 8746 operand_type_set (&bigdisp, 0);
40fb9820
L		 8747 if ((i.types[this_operand].bitfield.jumpabsolute)
8748 || (!current_templates->start->opcode_modifier.jump
8749 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8750 {
40fb9820 8751 bigdisp.bitfield.disp32 = 1;
e05278af 8752 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8753 if (flag_code == CODE_64BIT)
8754 {
8755 if (!override)
8756 {
8757 bigdisp.bitfield.disp32s = 1;
8758 bigdisp.bitfield.disp64 = 1;
8759 }
8760 }
8761 else if ((flag_code == CODE_16BIT) ^ override)
8762 {
8763 bigdisp.bitfield.disp32 = 0;
8764 bigdisp.bitfield.disp16 = 1;
8765 }
e05278af
JB		 8766 }
8767 else
8768 {
8769 /* For PC-relative branches, the width of the displacement
8770 is dependent upon data size, not address size. */
e05278af 8771 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8772 if (flag_code == CODE_64BIT)
8773 {
8774 if (override || i.suffix == WORD_MNEM_SUFFIX)
8775 bigdisp.bitfield.disp16 = 1;
8776 else
8777 {
8778 bigdisp.bitfield.disp32 = 1;
8779 bigdisp.bitfield.disp32s = 1;
8780 }
8781 }
8782 else
e05278af
JB		 8783 {
8784 if (!override)
8785 override = (i.suffix == (flag_code != CODE_16BIT
8786 ? WORD_MNEM_SUFFIX
8787 : LONG_MNEM_SUFFIX));
40fb9820
L		 8788 bigdisp.bitfield.disp32 = 1;
8789 if ((flag_code == CODE_16BIT) ^ override)
8790 {
8791 bigdisp.bitfield.disp32 = 0;
8792 bigdisp.bitfield.disp16 = 1;
8793 }
e05278af 8794 }
e05278af 8795 }
c6fb90c8
L		 8796 i.types[this_operand] = operand_type_or (i.types[this_operand],
8797 bigdisp);
252b5132
RH		 8798
8799 exp = &disp_expressions[i.disp_operands];
520dc8e8 8800 i.op[this_operand].disps = exp;
252b5132
RH		 8801 i.disp_operands++;
8802 save_input_line_pointer = input_line_pointer;
8803 input_line_pointer = disp_start;
8804 END_STRING_AND_SAVE (disp_end);
8805
8806#ifndef GCC_ASM_O_HACK
8807#define GCC_ASM_O_HACK 0
8808#endif
8809#if GCC_ASM_O_HACK
8810 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8811 if (i.types[this_operand].bitfield.baseIndex
24eab124 8812 && displacement_string_end[-1] == '+')
252b5132
RH		 8813 {
8814 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8815 constraint within gcc asm statements.
8816 For instance:
8817
8818 #define _set_tssldt_desc(n,addr,limit,type) \
8819 __asm__ __volatile__ ( \
8820 "movw %w2,%0\n\t" \
8821 "movw %w1,2+%0\n\t" \
8822 "rorl $16,%1\n\t" \
8823 "movb %b1,4+%0\n\t" \
8824 "movb %4,5+%0\n\t" \
8825 "movb $0,6+%0\n\t" \
8826 "movb %h1,7+%0\n\t" \
8827 "rorl $16,%1" \
8828 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8829
8830 This works great except that the output assembler ends
8831 up looking a bit weird if it turns out that there is
8832 no offset. You end up producing code that looks like:
8833
8834 #APP
8835 movw $235,(%eax)
8836 movw %dx,2+(%eax)
8837 rorl $16,%edx
8838 movb %dl,4+(%eax)
8839 movb $137,5+(%eax)
8840 movb $0,6+(%eax)
8841 movb %dh,7+(%eax)
8842 rorl $16,%edx
8843 #NO_APP
8844
47926f60 8845 So here we provide the missing zero. */
24eab124
AM		 8846
8847 *displacement_string_end = '0';
252b5132
RH		 8848 }
8849#endif
d258b828 8850 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8851 if (gotfree_input_line)
8852 input_line_pointer = gotfree_input_line;
252b5132 8853
24eab124 8854 exp_seg = expression (exp);
252b5132 8855
636c26b0
AM		 8856 SKIP_WHITESPACE ();
8857 if (*input_line_pointer)
8858 as_bad (_("junk `%s' after expression"), input_line_pointer);
8859#if GCC_ASM_O_HACK
8860 RESTORE_END_STRING (disp_end + 1);
8861#endif
636c26b0 8862 input_line_pointer = save_input_line_pointer;
636c26b0 8863 if (gotfree_input_line)
ee86248c
JB		 8864 {
8865 free (gotfree_input_line);
8866
8867 if (exp->X_op == O_constant || exp->X_op == O_register)
8868 exp->X_op = O_illegal;
8869 }
8870
8871 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8872
8873 RESTORE_END_STRING (disp_end);
8874
8875 return ret;
8876}
8877
8878static int
8879i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8880 i386_operand_type types, const char *disp_start)
8881{
8882 i386_operand_type bigdisp;
8883 int ret = 1;
636c26b0 8884
24eab124
AM		 8885 /* We do this to make sure that the section symbol is in
8886 the symbol table. We will ultimately change the relocation
47926f60 8887 to be relative to the beginning of the section. */
1ae12ab7 8888 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8889 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8890 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8891 {
636c26b0 8892 if (exp->X_op != O_symbol)
3992d3b7 8893 goto inv_disp;
636c26b0 8894
e5cb08ac 8895 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8896 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8897 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8898 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8899 exp->X_op = O_subtract;
8900 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8901 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8902 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8903 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8904 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8905 else
29b0f896 8906 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8907 }
252b5132 8908
3992d3b7
AM		 8909 else if (exp->X_op == O_absent
8910 || exp->X_op == O_illegal
ee86248c 8911 || exp->X_op == O_big)
2daf4fd8 8912 {
3992d3b7
AM		 8913 inv_disp:
8914 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8915 disp_start);
3992d3b7 8916 ret = 0;
2daf4fd8
AM		 8917 }
8918
0e1147d9
L		 8919 else if (flag_code == CODE_64BIT
8920 && !i.prefix[ADDR_PREFIX]
8921 && exp->X_op == O_constant)
8922 {
8923 /* Since displacement is signed extended to 64bit, don't allow
8924 disp32 and turn off disp32s if they are out of range. */
8925 i.types[this_operand].bitfield.disp32 = 0;
8926 if (!fits_in_signed_long (exp->X_add_number))
8927 {
8928 i.types[this_operand].bitfield.disp32s = 0;
8929 if (i.types[this_operand].bitfield.baseindex)
8930 {
8931 as_bad (_("0x%lx out range of signed 32bit displacement"),
8932 (long) exp->X_add_number);
8933 ret = 0;
8934 }
8935 }
8936 }
8937
4c63da97 8938#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8939 else if (exp->X_op != O_constant
8940 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8941 && exp_seg != absolute_section
8942 && exp_seg != text_section
8943 && exp_seg != data_section
8944 && exp_seg != bss_section
8945 && exp_seg != undefined_section
8946 && !bfd_is_com_section (exp_seg))
24eab124 8947 {
d0b47220 8948 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8949 ret = 0;
24eab124 8950 }
252b5132 8951#endif
3956db08 8952
40fb9820
L		 8953 /* Check if this is a displacement only operand. */
8954 bigdisp = i.types[this_operand];
8955 bigdisp.bitfield.disp8 = 0;
8956 bigdisp.bitfield.disp16 = 0;
8957 bigdisp.bitfield.disp32 = 0;
8958 bigdisp.bitfield.disp32s = 0;
8959 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8960 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8961 i.types[this_operand] = operand_type_and (i.types[this_operand],
8962 types);
3956db08 8963
3992d3b7 8964 return ret;
252b5132
RH		 8965}
8966
2abc2bec
JB		 8967/* Return the active addressing mode, taking address override and
8968 registers forming the address into consideration. Update the
8969 address override prefix if necessary. */
47926f60 8970
2abc2bec
JB		 8971static enum flag_code
8972i386_addressing_mode (void)
252b5132 8973{
be05d201
L		 8974 enum flag_code addr_mode;
8975
8976 if (i.prefix[ADDR_PREFIX])
8977 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8978 else
8979 {
8980 addr_mode = flag_code;
8981
24eab124 8982#if INFER_ADDR_PREFIX
be05d201
L		 8983 if (i.mem_operands == 0)
8984 {
8985 /* Infer address prefix from the first memory operand. */
8986 const reg_entry *addr_reg = i.base_reg;
8987
8988 if (addr_reg == NULL)
8989 addr_reg = i.index_reg;
eecb386c 8990
be05d201
L		 8991 if (addr_reg)
8992 {
8993 if (addr_reg->reg_num == RegEip
8994 || addr_reg->reg_num == RegEiz
dc821c5f 8995 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 8996 addr_mode = CODE_32BIT;
8997 else if (flag_code != CODE_64BIT
dc821c5f 8998 && addr_reg->reg_type.bitfield.word)
be05d201
L		 8999 addr_mode = CODE_16BIT;
9000
9001 if (addr_mode != flag_code)
9002 {
9003 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9004 i.prefixes += 1;
9005 /* Change the size of any displacement too. At most one
9006 of Disp16 or Disp32 is set.
9007 FIXME. There doesn't seem to be any real need for
9008 separate Disp16 and Disp32 flags. The same goes for
9009 Imm16 and Imm32. Removing them would probably clean
9010 up the code quite a lot. */
9011 if (flag_code != CODE_64BIT
9012 && (i.types[this_operand].bitfield.disp16
9013 || i.types[this_operand].bitfield.disp32))
9014 i.types[this_operand]
9015 = operand_type_xor (i.types[this_operand], disp16_32);
9016 }
9017 }
9018 }
24eab124 9019#endif
be05d201
L		 9020 }
9021
2abc2bec
JB		 9022 return addr_mode;
9023}
9024
9025/* Make sure the memory operand we've been dealt is valid.
9026 Return 1 on success, 0 on a failure. */
9027
9028static int
9029i386_index_check (const char *operand_string)
9030{
9031 const char *kind = "base/index";
9032 enum flag_code addr_mode = i386_addressing_mode ();
9033
fc0763e6
JB		 9034 if (current_templates->start->opcode_modifier.isstring
9035 && !current_templates->start->opcode_modifier.immext
9036 && (current_templates->end[-1].opcode_modifier.isstring
9037 || i.mem_operands))
9038 {
9039 /* Memory operands of string insns are special in that they only allow
9040 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9041 const reg_entry *expected_reg;
9042 static const char *di_si[][2] =
9043 {
9044 { "esi", "edi" },
9045 { "si", "di" },
9046 { "rsi", "rdi" }
9047 };
9048 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9049
9050 kind = "string address";
9051
8325cc63 9052 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9053 {
9054 i386_operand_type type = current_templates->end[-1].operand_types[0];
9055
9056 if (!type.bitfield.baseindex
9057 || ((!i.mem_operands != !intel_syntax)
9058 && current_templates->end[-1].operand_types[1]
9059 .bitfield.baseindex))
9060 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9061 expected_reg = hash_find (reg_hash,
9062 di_si[addr_mode][type.bitfield.esseg]);
9063
fc0763e6
JB		 9064 }
9065 else
be05d201 9066 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9067
be05d201
L		 9068 if (i.base_reg != expected_reg
9069 || i.index_reg
fc0763e6 9070 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9071 {
be05d201
L		 9072 /* The second memory operand must have the same size as
9073 the first one. */
9074 if (i.mem_operands
9075 && i.base_reg
9076 && !((addr_mode == CODE_64BIT
dc821c5f 9077 && i.base_reg->reg_type.bitfield.qword)
be05d201 9078 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9079 ? i.base_reg->reg_type.bitfield.dword
9080 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9081 goto bad_address;
9082
fc0763e6
JB		 9083 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9084 operand_string,
9085 intel_syntax ? '[' : '(',
9086 register_prefix,
be05d201 9087 expected_reg->reg_name,
fc0763e6 9088 intel_syntax ? ']' : ')');
be05d201 9089 return 1;
fc0763e6 9090 }
be05d201
L		 9091 else
9092 return 1;
9093
9094bad_address:
9095 as_bad (_("`%s' is not a valid %s expression"),
9096 operand_string, kind);
9097 return 0;
3e73aa7c
JH		 9098 }
9099 else
9100 {
be05d201
L		 9101 if (addr_mode != CODE_16BIT)
9102 {
9103 /* 32-bit/64-bit checks. */
9104 if ((i.base_reg
9105 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9106 ? !i.base_reg->reg_type.bitfield.qword
9107 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9108 && (i.index_reg
9109 || (i.base_reg->reg_num
9110 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9111 || (i.index_reg
1b54b8d7
JB		 9112 && !i.index_reg->reg_type.bitfield.xmmword
9113 && !i.index_reg->reg_type.bitfield.ymmword
9114 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9115 && ((addr_mode == CODE_64BIT
dc821c5f 9116 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9117 || i.index_reg->reg_num == RegRiz)
dc821c5f 9118 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9119 || i.index_reg->reg_num == RegEiz))
9120 || !i.index_reg->reg_type.bitfield.baseindex)))
9121 goto bad_address;
8178be5b
JB		 9122
9123 /* bndmk, bndldx, and bndstx have special restrictions. */
9124 if (current_templates->start->base_opcode == 0xf30f1b
9125 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9126 {
9127 /* They cannot use RIP-relative addressing. */
9128 if (i.base_reg && i.base_reg->reg_num == RegRip)
9129 {
9130 as_bad (_("`%s' cannot be used here"), operand_string);
9131 return 0;
9132 }
9133
9134 /* bndldx and bndstx ignore their scale factor. */
9135 if (current_templates->start->base_opcode != 0xf30f1b
9136 && i.log2_scale_factor)
9137 as_warn (_("register scaling is being ignored here"));
9138 }
be05d201
L		 9139 }
9140 else
3e73aa7c 9141 {
be05d201 9142 /* 16-bit checks. */
3e73aa7c 9143 if ((i.base_reg
dc821c5f 9144 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9145 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9146 || (i.index_reg
dc821c5f 9147 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9148 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9149 || !(i.base_reg
9150 && i.base_reg->reg_num < 6
9151 && i.index_reg->reg_num >= 6
9152 && i.log2_scale_factor == 0))))
be05d201 9153 goto bad_address;
3e73aa7c
JH		 9154 }
9155 }
be05d201 9156 return 1;
24eab124 9157}
252b5132 9158
43234a1e
L		 9159/* Handle vector immediates. */
9160
9161static int
9162RC_SAE_immediate (const char *imm_start)
9163{
9164 unsigned int match_found, j;
9165 const char *pstr = imm_start;
9166 expressionS *exp;
9167
9168 if (*pstr != '{')
9169 return 0;
9170
9171 pstr++;
9172 match_found = 0;
9173 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9174 {
9175 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9176 {
9177 if (!i.rounding)
9178 {
9179 rc_op.type = RC_NamesTable[j].type;
9180 rc_op.operand = this_operand;
9181 i.rounding = &rc_op;
9182 }
9183 else
9184 {
9185 as_bad (_("duplicated `%s'"), imm_start);
9186 return 0;
9187 }
9188 pstr += RC_NamesTable[j].len;
9189 match_found = 1;
9190 break;
9191 }
9192 }
9193 if (!match_found)
9194 return 0;
9195
9196 if (*pstr++ != '}')
9197 {
9198 as_bad (_("Missing '}': '%s'"), imm_start);
9199 return 0;
9200 }
9201 /* RC/SAE immediate string should contain nothing more. */;
9202 if (*pstr != 0)
9203 {
9204 as_bad (_("Junk after '}': '%s'"), imm_start);
9205 return 0;
9206 }
9207
9208 exp = &im_expressions[i.imm_operands++];
9209 i.op[this_operand].imms = exp;
9210
9211 exp->X_op = O_constant;
9212 exp->X_add_number = 0;
9213 exp->X_add_symbol = (symbolS *) 0;
9214 exp->X_op_symbol = (symbolS *) 0;
9215
9216 i.types[this_operand].bitfield.imm8 = 1;
9217 return 1;
9218}
9219
8325cc63
JB		 9220/* Only string instructions can have a second memory operand, so
9221 reduce current_templates to just those if it contains any. */
9222static int
9223maybe_adjust_templates (void)
9224{
9225 const insn_template *t;
9226
9227 gas_assert (i.mem_operands == 1);
9228
9229 for (t = current_templates->start; t < current_templates->end; ++t)
9230 if (t->opcode_modifier.isstring)
9231 break;
9232
9233 if (t < current_templates->end)
9234 {
9235 static templates aux_templates;
9236 bfd_boolean recheck;
9237
9238 aux_templates.start = t;
9239 for (; t < current_templates->end; ++t)
9240 if (!t->opcode_modifier.isstring)
9241 break;
9242 aux_templates.end = t;
9243
9244 /* Determine whether to re-check the first memory operand. */
9245 recheck = (aux_templates.start != current_templates->start
9246 || t != current_templates->end);
9247
9248 current_templates = &aux_templates;
9249
9250 if (recheck)
9251 {
9252 i.mem_operands = 0;
9253 if (i.memop1_string != NULL
9254 && i386_index_check (i.memop1_string) == 0)
9255 return 0;
9256 i.mem_operands = 1;
9257 }
9258 }
9259
9260 return 1;
9261}
9262
fc0763e6 9263/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9264 on error. */
252b5132 9265
252b5132 9266static int
a7619375 9267i386_att_operand (char *operand_string)
252b5132 9268{
af6bdddf
AM		 9269 const reg_entry *r;
9270 char *end_op;
24eab124 9271 char *op_string = operand_string;
252b5132 9272
24eab124 9273 if (is_space_char (*op_string))
252b5132
RH		 9274 ++op_string;
9275
24eab124 9276 /* We check for an absolute prefix (differentiating,
47926f60 9277 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9278 if (*op_string == ABSOLUTE_PREFIX)
9279 {
9280 ++op_string;
9281 if (is_space_char (*op_string))
9282 ++op_string;
40fb9820 9283 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9284 }
252b5132 9285
47926f60 9286 /* Check if operand is a register. */
4d1bb795 9287 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9288 {
40fb9820
L		 9289 i386_operand_type temp;
9290
24eab124
AM		 9291 /* Check for a segment override by searching for ':' after a
9292 segment register. */
9293 op_string = end_op;
9294 if (is_space_char (*op_string))
9295 ++op_string;
40fb9820
L		 9296 if (*op_string == ':'
9297 && (r->reg_type.bitfield.sreg2
9298 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9299 {
9300 switch (r->reg_num)
9301 {
9302 case 0:
9303 i.seg[i.mem_operands] = &es;
9304 break;
9305 case 1:
9306 i.seg[i.mem_operands] = &cs;
9307 break;
9308 case 2:
9309 i.seg[i.mem_operands] = &ss;
9310 break;
9311 case 3:
9312 i.seg[i.mem_operands] = &ds;
9313 break;
9314 case 4:
9315 i.seg[i.mem_operands] = &fs;
9316 break;
9317 case 5:
9318 i.seg[i.mem_operands] = &gs;
9319 break;
9320 }
252b5132 9321
24eab124 9322 /* Skip the ':' and whitespace. */
252b5132
RH		 9323 ++op_string;
9324 if (is_space_char (*op_string))
24eab124 9325 ++op_string;
252b5132 9326
24eab124
AM		 9327 if (!is_digit_char (*op_string)
9328 && !is_identifier_char (*op_string)
9329 && *op_string != '('
9330 && *op_string != ABSOLUTE_PREFIX)
9331 {
9332 as_bad (_("bad memory operand `%s'"), op_string);
9333 return 0;
9334 }
47926f60 9335 /* Handle case of %es:*foo. */
24eab124
AM		 9336 if (*op_string == ABSOLUTE_PREFIX)
9337 {
9338 ++op_string;
9339 if (is_space_char (*op_string))
9340 ++op_string;
40fb9820 9341 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9342 }
9343 goto do_memory_reference;
9344 }
43234a1e
L		 9345
9346 /* Handle vector operations. */
9347 if (*op_string == '{')
9348 {
9349 op_string = check_VecOperations (op_string, NULL);
9350 if (op_string == NULL)
9351 return 0;
9352 }
9353
24eab124
AM		 9354 if (*op_string)
9355 {
d0b47220 9356 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9357 return 0;
9358 }
40fb9820
L		 9359 temp = r->reg_type;
9360 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9361 i.types[this_operand] = operand_type_or (i.types[this_operand],
9362 temp);
7d5e4556 9363 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9364 i.op[this_operand].regs = r;
24eab124
AM		 9365 i.reg_operands++;
9366 }
af6bdddf
AM		 9367 else if (*op_string == REGISTER_PREFIX)
9368 {
9369 as_bad (_("bad register name `%s'"), op_string);
9370 return 0;
9371 }
24eab124 9372 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9373 {
24eab124 9374 ++op_string;
40fb9820 9375 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9376 {
d0b47220 9377 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9378 return 0;
9379 }
9380 if (!i386_immediate (op_string))
9381 return 0;
9382 }
43234a1e
L		 9383 else if (RC_SAE_immediate (operand_string))
9384 {
9385 /* If it is a RC or SAE immediate, do nothing. */
9386 ;
9387 }
24eab124
AM		 9388 else if (is_digit_char (*op_string)
9389 || is_identifier_char (*op_string)
d02603dc 9390 || *op_string == '"'
e5cb08ac 9391 || *op_string == '(')
24eab124 9392 {
47926f60 9393 /* This is a memory reference of some sort. */
af6bdddf 9394 char *base_string;
252b5132 9395
47926f60 9396 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9397 char *displacement_string_start;
9398 char *displacement_string_end;
43234a1e 9399 char *vop_start;
252b5132 9400
24eab124 9401 do_memory_reference:
8325cc63
JB		 9402 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9403 return 0;
24eab124 9404 if ((i.mem_operands == 1
40fb9820 9405 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9406 || i.mem_operands == 2)
9407 {
9408 as_bad (_("too many memory references for `%s'"),
9409 current_templates->start->name);
9410 return 0;
9411 }
252b5132 9412
24eab124
AM		 9413 /* Check for base index form. We detect the base index form by
9414 looking for an ')' at the end of the operand, searching
9415 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9416 after the '('. */
af6bdddf 9417 base_string = op_string + strlen (op_string);
c3332e24 9418
43234a1e
L		 9419 /* Handle vector operations. */
9420 vop_start = strchr (op_string, '{');
9421 if (vop_start && vop_start < base_string)
9422 {
9423 if (check_VecOperations (vop_start, base_string) == NULL)
9424 return 0;
9425 base_string = vop_start;
9426 }
9427
af6bdddf
AM		 9428 --base_string;
9429 if (is_space_char (*base_string))
9430 --base_string;
252b5132 9431
47926f60 9432 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9433 displacement_string_start = op_string;
9434 displacement_string_end = base_string + 1;
252b5132 9435
24eab124
AM		 9436 if (*base_string == ')')
9437 {
af6bdddf 9438 char *temp_string;
24eab124
AM		 9439 unsigned int parens_balanced = 1;
9440 /* We've already checked that the number of left & right ()'s are
47926f60 9441 equal, so this loop will not be infinite. */
24eab124
AM		 9442 do
9443 {
9444 base_string--;
9445 if (*base_string == ')')
9446 parens_balanced++;
9447 if (*base_string == '(')
9448 parens_balanced--;
9449 }
9450 while (parens_balanced);
c3332e24 9451
af6bdddf 9452 temp_string = base_string;
c3332e24 9453
24eab124 9454 /* Skip past '(' and whitespace. */
252b5132
RH		 9455 ++base_string;
9456 if (is_space_char (*base_string))
24eab124 9457 ++base_string;
252b5132 9458
af6bdddf 9459 if (*base_string == ','
4eed87de
AM		 9460 || ((i.base_reg = parse_register (base_string, &end_op))
9461 != NULL))
252b5132 9462 {
af6bdddf 9463 displacement_string_end = temp_string;
252b5132 9464
40fb9820 9465 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9466
af6bdddf 9467 if (i.base_reg)
24eab124 9468 {
24eab124
AM		 9469 base_string = end_op;
9470 if (is_space_char (*base_string))
9471 ++base_string;
af6bdddf
AM		 9472 }
9473
9474 /* There may be an index reg or scale factor here. */
9475 if (*base_string == ',')
9476 {
9477 ++base_string;
9478 if (is_space_char (*base_string))
9479 ++base_string;
9480
4eed87de
AM		 9481 if ((i.index_reg = parse_register (base_string, &end_op))
9482 != NULL)
24eab124 9483 {
af6bdddf 9484 base_string = end_op;
24eab124
AM		 9485 if (is_space_char (*base_string))
9486 ++base_string;
af6bdddf
AM		 9487 if (*base_string == ',')
9488 {
9489 ++base_string;
9490 if (is_space_char (*base_string))
9491 ++base_string;
9492 }
e5cb08ac 9493 else if (*base_string != ')')
af6bdddf 9494 {
4eed87de
AM		 9495 as_bad (_("expecting `,' or `)' "
9496 "after index register in `%s'"),
af6bdddf
AM		 9497 operand_string);
9498 return 0;
9499 }
24eab124 9500 }
af6bdddf 9501 else if (*base_string == REGISTER_PREFIX)
24eab124 9502 {
f76bf5e0
L		 9503 end_op = strchr (base_string, ',');
9504 if (end_op)
9505 *end_op = '\0';
af6bdddf 9506 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9507 return 0;
9508 }
252b5132 9509
47926f60 9510 /* Check for scale factor. */
551c1ca1 9511 if (*base_string != ')')
af6bdddf 9512 {
551c1ca1
AM		 9513 char *end_scale = i386_scale (base_string);
9514
9515 if (!end_scale)
af6bdddf 9516 return 0;
24eab124 9517
551c1ca1 9518 base_string = end_scale;
af6bdddf
AM		 9519 if (is_space_char (*base_string))
9520 ++base_string;
9521 if (*base_string != ')')
9522 {
4eed87de
AM		 9523 as_bad (_("expecting `)' "
9524 "after scale factor in `%s'"),
af6bdddf
AM		 9525 operand_string);
9526 return 0;
9527 }
9528 }
9529 else if (!i.index_reg)
24eab124 9530 {
4eed87de
AM		 9531 as_bad (_("expecting index register or scale factor "
9532 "after `,'; got '%c'"),
af6bdddf 9533 *base_string);
24eab124
AM		 9534 return 0;
9535 }
9536 }
af6bdddf 9537 else if (*base_string != ')')
24eab124 9538 {
4eed87de
AM		 9539 as_bad (_("expecting `,' or `)' "
9540 "after base register in `%s'"),
af6bdddf 9541 operand_string);
24eab124
AM		 9542 return 0;
9543 }
c3332e24 9544 }
af6bdddf 9545 else if (*base_string == REGISTER_PREFIX)
c3332e24 9546 {
f76bf5e0
L		 9547 end_op = strchr (base_string, ',');
9548 if (end_op)
9549 *end_op = '\0';
af6bdddf 9550 as_bad (_("bad register name `%s'"), base_string);
24eab124 9551 return 0;
c3332e24 9552 }
24eab124
AM		 9553 }
9554
9555 /* If there's an expression beginning the operand, parse it,
9556 assuming displacement_string_start and
9557 displacement_string_end are meaningful. */
9558 if (displacement_string_start != displacement_string_end)
9559 {
9560 if (!i386_displacement (displacement_string_start,
9561 displacement_string_end))
9562 return 0;
9563 }
9564
9565 /* Special case for (%dx) while doing input/output op. */
9566 if (i.base_reg
0dfbf9d7
L		 9567 && operand_type_equal (&i.base_reg->reg_type,
9568 &reg16_inoutportreg)
24eab124
AM		 9569 && i.index_reg == 0
9570 && i.log2_scale_factor == 0
9571 && i.seg[i.mem_operands] == 0
40fb9820 9572 && !operand_type_check (i.types[this_operand], disp))
24eab124 9573 {
65da13b5 9574 i.types[this_operand] = inoutportreg;
24eab124
AM		 9575 return 1;
9576 }
9577
eecb386c
AM		 9578 if (i386_index_check (operand_string) == 0)
9579 return 0;
5c07affc 9580 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9581 if (i.mem_operands == 0)
9582 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9583 i.mem_operands++;
9584 }
9585 else
ce8a8b2f
AM		 9586 {
9587 /* It's not a memory operand; argh! */
24eab124
AM		 9588 as_bad (_("invalid char %s beginning operand %d `%s'"),
9589 output_invalid (*op_string),
9590 this_operand + 1,
9591 op_string);
9592 return 0;
9593 }
47926f60 9594 return 1; /* Normal return. */
252b5132
RH		 9595}
9596\f
fa94de6b
RM		 9597/* Calculate the maximum variable size (i.e., excluding fr_fix)
9598 that an rs_machine_dependent frag may reach. */
9599
9600unsigned int
9601i386_frag_max_var (fragS *frag)
9602{
9603 /* The only relaxable frags are for jumps.
9604 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9605 gas_assert (frag->fr_type == rs_machine_dependent);
9606 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9607}
9608
b084df0b
L		 9609#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9610static int
8dcea932 9611elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9612{
9613 /* STT_GNU_IFUNC symbol must go through PLT. */
9614 if ((symbol_get_bfdsym (fr_symbol)->flags
9615 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9616 return 0;
9617
9618 if (!S_IS_EXTERNAL (fr_symbol))
9619 /* Symbol may be weak or local. */
9620 return !S_IS_WEAK (fr_symbol);
9621
8dcea932
L		 9622 /* Global symbols with non-default visibility can't be preempted. */
9623 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9624 return 1;
9625
9626 if (fr_var != NO_RELOC)
9627 switch ((enum bfd_reloc_code_real) fr_var)
9628 {
9629 case BFD_RELOC_386_PLT32:
9630 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9631 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9632 return 0;
9633 default:
9634 abort ();
9635 }
9636
b084df0b
L		 9637 /* Global symbols with default visibility in a shared library may be
9638 preempted by another definition. */
8dcea932 9639 return !shared;
b084df0b
L		 9640}
9641#endif
9642
ee7fcc42
AM		 9643/* md_estimate_size_before_relax()
9644
9645 Called just before relax() for rs_machine_dependent frags. The x86
9646 assembler uses these frags to handle variable size jump
9647 instructions.
9648
9649 Any symbol that is now undefined will not become defined.
9650 Return the correct fr_subtype in the frag.
9651 Return the initial "guess for variable size of frag" to caller.
9652 The guess is actually the growth beyond the fixed part. Whatever
9653 we do to grow the fixed or variable part contributes to our
9654 returned value. */
9655
252b5132 9656int
7016a5d5 9657md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9658{
252b5132 9659 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9660 check for un-relaxable symbols. On an ELF system, we can't relax
9661 an externally visible symbol, because it may be overridden by a
9662 shared library. */
9663 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9664#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9665 || (IS_ELF
8dcea932
L		 9666 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9667 fragP->fr_var))
fbeb56a4
DK		 9668#endif
9669#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9670 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9671 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9672#endif
9673 )
252b5132 9674 {
b98ef147
AM		 9675 /* Symbol is undefined in this segment, or we need to keep a
9676 reloc so that weak symbols can be overridden. */
9677 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9678 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9679 unsigned char *opcode;
9680 int old_fr_fix;
f6af82bd 9681
ee7fcc42 9682 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9683 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9684 else if (size == 2)
f6af82bd 9685 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9686#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9687 else if (need_plt32_p (fragP->fr_symbol))
9688 reloc_type = BFD_RELOC_X86_64_PLT32;
9689#endif
f6af82bd
AM		 9690 else
9691 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9692
ee7fcc42
AM		 9693 old_fr_fix = fragP->fr_fix;
9694 opcode = (unsigned char *) fragP->fr_opcode;
9695
fddf5b5b 9696 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9697 {
fddf5b5b
AM		 9698 case UNCOND_JUMP:
9699 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9700 opcode[0] = 0xe9;
252b5132 9701 fragP->fr_fix += size;
062cd5e7
AS		 9702 fix_new (fragP, old_fr_fix, size,
9703 fragP->fr_symbol,
9704 fragP->fr_offset, 1,
9705 reloc_type);
252b5132
RH		 9706 break;
9707
fddf5b5b 9708 case COND_JUMP86:
412167cb
AM		 9709 if (size == 2
9710 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9711 {
9712 /* Negate the condition, and branch past an
9713 unconditional jump. */
9714 opcode[0] ^= 1;
9715 opcode[1] = 3;
9716 /* Insert an unconditional jump. */
9717 opcode[2] = 0xe9;
9718 /* We added two extra opcode bytes, and have a two byte
9719 offset. */
9720 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9721 fix_new (fragP, old_fr_fix + 2, 2,
9722 fragP->fr_symbol,
9723 fragP->fr_offset, 1,
9724 reloc_type);
fddf5b5b
AM		 9725 break;
9726 }
9727 /* Fall through. */
9728
9729 case COND_JUMP:
412167cb
AM		 9730 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9731 {
3e02c1cc
AM		 9732 fixS *fixP;
9733
412167cb 9734 fragP->fr_fix += 1;
3e02c1cc
AM		 9735 fixP = fix_new (fragP, old_fr_fix, 1,
9736 fragP->fr_symbol,
9737 fragP->fr_offset, 1,
9738 BFD_RELOC_8_PCREL);
9739 fixP->fx_signed = 1;
412167cb
AM		 9740 break;
9741 }
93c2a809 9742
24eab124 9743 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9744 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9745 opcode[1] = opcode[0] + 0x10;
f6af82bd 9746 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9747 /* We've added an opcode byte. */
9748 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9749 fix_new (fragP, old_fr_fix + 1, size,
9750 fragP->fr_symbol,
9751 fragP->fr_offset, 1,
9752 reloc_type);
252b5132 9753 break;
fddf5b5b
AM		 9754
9755 default:
9756 BAD_CASE (fragP->fr_subtype);
9757 break;
252b5132
RH		 9758 }
9759 frag_wane (fragP);
ee7fcc42 9760 return fragP->fr_fix - old_fr_fix;
252b5132 9761 }
93c2a809 9762
93c2a809
AM		 9763 /* Guess size depending on current relax state. Initially the relax
9764 state will correspond to a short jump and we return 1, because
9765 the variable part of the frag (the branch offset) is one byte
9766 long. However, we can relax a section more than once and in that
9767 case we must either set fr_subtype back to the unrelaxed state,
9768 or return the value for the appropriate branch. */
9769 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9770}
9771
47926f60
KH		 9772/* Called after relax() is finished.
9773
9774 In: Address of frag.
9775 fr_type == rs_machine_dependent.
9776 fr_subtype is what the address relaxed to.
9777
9778 Out: Any fixSs and constants are set up.
9779 Caller will turn frag into a ".space 0". */
9780
252b5132 9781void
7016a5d5
TG		 9782md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9783 fragS *fragP)
252b5132 9784{
29b0f896 9785 unsigned char *opcode;
252b5132 9786 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9787 offsetT target_address;
9788 offsetT opcode_address;
252b5132 9789 unsigned int extension = 0;
847f7ad4 9790 offsetT displacement_from_opcode_start;
252b5132
RH		 9791
9792 opcode = (unsigned char *) fragP->fr_opcode;
9793
47926f60 9794 /* Address we want to reach in file space. */
252b5132 9795 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9796
47926f60 9797 /* Address opcode resides at in file space. */
252b5132
RH		 9798 opcode_address = fragP->fr_address + fragP->fr_fix;
9799
47926f60 9800 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9801 displacement_from_opcode_start = target_address - opcode_address;
9802
fddf5b5b 9803 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9804 {
47926f60
KH		 9805 /* Don't have to change opcode. */
9806 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9807 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9808 }
9809 else
9810 {
9811 if (no_cond_jump_promotion
9812 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9813 as_warn_where (fragP->fr_file, fragP->fr_line,
9814 _("long jump required"));
252b5132 9815
fddf5b5b
AM		 9816 switch (fragP->fr_subtype)
9817 {
9818 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9819 extension = 4; /* 1 opcode + 4 displacement */
9820 opcode[0] = 0xe9;
9821 where_to_put_displacement = &opcode[1];
9822 break;
252b5132 9823
fddf5b5b
AM		 9824 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9825 extension = 2; /* 1 opcode + 2 displacement */
9826 opcode[0] = 0xe9;
9827 where_to_put_displacement = &opcode[1];
9828 break;
252b5132 9829
fddf5b5b
AM		 9830 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9831 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9832 extension = 5; /* 2 opcode + 4 displacement */
9833 opcode[1] = opcode[0] + 0x10;
9834 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9835 where_to_put_displacement = &opcode[2];
9836 break;
252b5132 9837
fddf5b5b
AM		 9838 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9839 extension = 3; /* 2 opcode + 2 displacement */
9840 opcode[1] = opcode[0] + 0x10;
9841 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9842 where_to_put_displacement = &opcode[2];
9843 break;
252b5132 9844
fddf5b5b
AM		 9845 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9846 extension = 4;
9847 opcode[0] ^= 1;
9848 opcode[1] = 3;
9849 opcode[2] = 0xe9;
9850 where_to_put_displacement = &opcode[3];
9851 break;
9852
9853 default:
9854 BAD_CASE (fragP->fr_subtype);
9855 break;
9856 }
252b5132 9857 }
fddf5b5b 9858
7b81dfbb
AJ		 9859 /* If size if less then four we are sure that the operand fits,
9860 but if it's 4, then it could be that the displacement is larger
9861 then -/+ 2GB. */
9862 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9863 && object_64bit
9864 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9865 + ((addressT) 1 << 31))
9866 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9867 {
9868 as_bad_where (fragP->fr_file, fragP->fr_line,
9869 _("jump target out of range"));
9870 /* Make us emit 0. */
9871 displacement_from_opcode_start = extension;
9872 }
47926f60 9873 /* Now put displacement after opcode. */
252b5132
RH		 9874 md_number_to_chars ((char *) where_to_put_displacement,
9875 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9876 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9877 fragP->fr_fix += extension;
9878}
9879\f
7016a5d5 9880/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9881 by our caller that we have all the info we need to fix it up.
9882
7016a5d5
TG		 9883 Parameter valP is the pointer to the value of the bits.
9884
252b5132
RH		 9885 On the 386, immediates, displacements, and data pointers are all in
9886 the same (little-endian) format, so we don't need to care about which
9887 we are handling. */
9888
94f592af 9889void
7016a5d5 9890md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9891{
94f592af 9892 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9893 valueT value = *valP;
252b5132 9894
f86103b7 9895#if !defined (TE_Mach)
93382f6d
AM		 9896 if (fixP->fx_pcrel)
9897 {
9898 switch (fixP->fx_r_type)
9899 {
5865bb77
ILT		 9900 default:
9901 break;
9902
d6ab8113
JB		 9903 case BFD_RELOC_64:
9904 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9905 break;
93382f6d 9906 case BFD_RELOC_32:
ae8887b5 9907 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9908 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9909 break;
9910 case BFD_RELOC_16:
9911 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9912 break;
9913 case BFD_RELOC_8:
9914 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9915 break;
9916 }
9917 }
252b5132 9918
a161fe53 9919 if (fixP->fx_addsy != NULL
31312f95 9920 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9921 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9922 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9923 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9924 && !use_rela_relocations)
252b5132 9925 {
31312f95
AM		 9926 /* This is a hack. There should be a better way to handle this.
9927 This covers for the fact that bfd_install_relocation will
9928 subtract the current location (for partial_inplace, PC relative
9929 relocations); see more below. */
252b5132 9930#ifndef OBJ_AOUT
718ddfc0 9931 if (IS_ELF
252b5132
RH		 9932#ifdef TE_PE
9933 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9934#endif
9935 )
9936 value += fixP->fx_where + fixP->fx_frag->fr_address;
9937#endif
9938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9939 if (IS_ELF)
252b5132 9940 {
6539b54b 9941 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9942
6539b54b 9943 if ((sym_seg == seg
2f66722d 9944 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9945 && sym_seg != absolute_section))
af65af87 9946 && !generic_force_reloc (fixP))
2f66722d
AM		 9947 {
9948 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9949 bfd_install_relocation subtracts them out again. I think
9950 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9951 it. FIXME. */
9952 value += fixP->fx_where + fixP->fx_frag->fr_address;
9953 }
252b5132
RH		 9954 }
9955#endif
9956#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9957 /* For some reason, the PE format does not store a
9958 section address offset for a PC relative symbol. */
9959 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9960 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9961 value += md_pcrel_from (fixP);
9962#endif
9963 }
fbeb56a4 9964#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9965 if (fixP->fx_addsy != NULL
9966 && S_IS_WEAK (fixP->fx_addsy)
9967 /* PR 16858: Do not modify weak function references. */
9968 && ! fixP->fx_pcrel)
fbeb56a4 9969 {
296a8689
NC		 9970#if !defined (TE_PEP)
9971 /* For x86 PE weak function symbols are neither PC-relative
9972 nor do they set S_IS_FUNCTION. So the only reliable way
9973 to detect them is to check the flags of their containing
9974 section. */
9975 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9976 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9977 ;
9978 else
9979#endif
fbeb56a4
DK		 9980 value -= S_GET_VALUE (fixP->fx_addsy);
9981 }
9982#endif
252b5132
RH		 9983
9984 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9985 and we must not disappoint it. */
252b5132 9986#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9987 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9988 switch (fixP->fx_r_type)
9989 {
9990 case BFD_RELOC_386_PLT32:
3e73aa7c 9991 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9992 /* Make the jump instruction point to the address of the operand. At
9993 runtime we merely add the offset to the actual PLT entry. */
9994 value = -4;
9995 break;
31312f95 9996
13ae64f3
JJ		 9997 case BFD_RELOC_386_TLS_GD:
9998 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9999 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10000 case BFD_RELOC_386_TLS_IE:
10001 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10002 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10003 case BFD_RELOC_X86_64_TLSGD:
10004 case BFD_RELOC_X86_64_TLSLD:
10005 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10006 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10007 value = 0; /* Fully resolved at runtime. No addend. */
10008 /* Fallthrough */
10009 case BFD_RELOC_386_TLS_LE:
10010 case BFD_RELOC_386_TLS_LDO_32:
10011 case BFD_RELOC_386_TLS_LE_32:
10012 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10013 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10014 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10015 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10016 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10017 break;
10018
67a4f2b7
AO		 10019 case BFD_RELOC_386_TLS_DESC_CALL:
10020 case BFD_RELOC_X86_64_TLSDESC_CALL:
10021 value = 0; /* Fully resolved at runtime. No addend. */
10022 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10023 fixP->fx_done = 0;
10024 return;
10025
47926f60
KH		 10026 case BFD_RELOC_VTABLE_INHERIT:
10027 case BFD_RELOC_VTABLE_ENTRY:
10028 fixP->fx_done = 0;
94f592af 10029 return;
47926f60
KH		 10030
10031 default:
10032 break;
10033 }
10034#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10035 *valP = value;
f86103b7 10036#endif /* !defined (TE_Mach) */
3e73aa7c 10037
3e73aa7c 10038 /* Are we finished with this relocation now? */
c6682705 10039 if (fixP->fx_addsy == NULL)
3e73aa7c 10040 fixP->fx_done = 1;
fbeb56a4
DK		 10041#if defined (OBJ_COFF) && defined (TE_PE)
10042 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10043 {
10044 fixP->fx_done = 0;
10045 /* Remember value for tc_gen_reloc. */
10046 fixP->fx_addnumber = value;
10047 /* Clear out the frag for now. */
10048 value = 0;
10049 }
10050#endif
3e73aa7c
JH		 10051 else if (use_rela_relocations)
10052 {
10053 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10054 /* Remember value for tc_gen_reloc. */
10055 fixP->fx_addnumber = value;
3e73aa7c
JH		 10056 value = 0;
10057 }
f86103b7 10058
94f592af 10059 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10060}
252b5132 10061\f
6d4af3c2 10062const char *
499ac353 10063md_atof (int type, char *litP, int *sizeP)
252b5132 10064{
499ac353
NC		 10065 /* This outputs the LITTLENUMs in REVERSE order;
10066 in accord with the bigendian 386. */
10067 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10068}
10069\f
2d545b82 10070static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10071
252b5132 10072static char *
e3bb37b5 10073output_invalid (int c)
252b5132 10074{
3882b010 10075 if (ISPRINT (c))
f9f21a03
L		 10076 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10077 "'%c'", c);
252b5132 10078 else
f9f21a03 10079 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10080 "(0x%x)", (unsigned char) c);
252b5132
RH		 10081 return output_invalid_buf;
10082}
10083
af6bdddf 10084/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10085
10086static const reg_entry *
4d1bb795 10087parse_real_register (char *reg_string, char **end_op)
252b5132 10088{
af6bdddf
AM		 10089 char *s = reg_string;
10090 char *p;
252b5132
RH		 10091 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10092 const reg_entry *r;
10093
10094 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10095 if (*s == REGISTER_PREFIX)
10096 ++s;
10097
10098 if (is_space_char (*s))
10099 ++s;
10100
10101 p = reg_name_given;
af6bdddf 10102 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10103 {
10104 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10105 return (const reg_entry *) NULL;
10106 s++;
252b5132
RH		 10107 }
10108
6588847e
DN		 10109 /* For naked regs, make sure that we are not dealing with an identifier.
10110 This prevents confusing an identifier like `eax_var' with register
10111 `eax'. */
10112 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10113 return (const reg_entry *) NULL;
10114
af6bdddf 10115 *end_op = s;
252b5132
RH		 10116
10117 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10118
5f47d35b 10119 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10120 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10121 {
5f47d35b
AM		 10122 if (is_space_char (*s))
10123 ++s;
10124 if (*s == '(')
10125 {
af6bdddf 10126 ++s;
5f47d35b
AM		 10127 if (is_space_char (*s))
10128 ++s;
10129 if (*s >= '0' && *s <= '7')
10130 {
db557034 10131 int fpr = *s - '0';
af6bdddf 10132 ++s;
5f47d35b
AM		 10133 if (is_space_char (*s))
10134 ++s;
10135 if (*s == ')')
10136 {
10137 *end_op = s + 1;
1e9cc1c2 10138 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10139 know (r);
10140 return r + fpr;
5f47d35b 10141 }
5f47d35b 10142 }
47926f60 10143 /* We have "%st(" then garbage. */
5f47d35b
AM		 10144 return (const reg_entry *) NULL;
10145 }
10146 }
10147
a60de03c
JB		 10148 if (r == NULL || allow_pseudo_reg)
10149 return r;
10150
0dfbf9d7 10151 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10152 return (const reg_entry *) NULL;
10153
dc821c5f 10154 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10155 || r->reg_type.bitfield.sreg3
10156 || r->reg_type.bitfield.control
10157 || r->reg_type.bitfield.debug
10158 || r->reg_type.bitfield.test)
10159 && !cpu_arch_flags.bitfield.cpui386)
10160 return (const reg_entry *) NULL;
10161
ca0d63fe 10162 if (r->reg_type.bitfield.tbyte
309d3373
JB		 10163 && !cpu_arch_flags.bitfield.cpu8087
10164 && !cpu_arch_flags.bitfield.cpu287
10165 && !cpu_arch_flags.bitfield.cpu387)
10166 return (const reg_entry *) NULL;
10167
1848e567 10168 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 10169 return (const reg_entry *) NULL;
10170
1b54b8d7 10171 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 10172 return (const reg_entry *) NULL;
10173
1b54b8d7 10174 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 10175 return (const reg_entry *) NULL;
10176
1b54b8d7 10177 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 10178 return (const reg_entry *) NULL;
10179
10180 if (r->reg_type.bitfield.regmask
10181 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 10182 return (const reg_entry *) NULL;
10183
db51cc60 10184 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10185 if (!allow_index_reg
db51cc60
L		 10186 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10187 return (const reg_entry *) NULL;
10188
43234a1e
L		 10189 /* Upper 16 vector register is only available with VREX in 64bit
10190 mode. */
10191 if ((r->reg_flags & RegVRex))
10192 {
86fa6981
L		 10193 if (i.vec_encoding == vex_encoding_default)
10194 i.vec_encoding = vex_encoding_evex;
10195
43234a1e 10196 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 10197 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 10198 || flag_code != CODE_64BIT)
10199 return (const reg_entry *) NULL;
43234a1e
L		 10200 }
10201
a60de03c 10202 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10203 || r->reg_type.bitfield.qword)
40fb9820 10204 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10205 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10206 && flag_code != CODE_64BIT)
20f0a1fc 10207 return (const reg_entry *) NULL;
1ae00879 10208
b7240065
JB		 10209 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10210 return (const reg_entry *) NULL;
10211
252b5132
RH		 10212 return r;
10213}
4d1bb795
JB		 10214
10215/* REG_STRING starts *before* REGISTER_PREFIX. */
10216
10217static const reg_entry *
10218parse_register (char *reg_string, char **end_op)
10219{
10220 const reg_entry *r;
10221
10222 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10223 r = parse_real_register (reg_string, end_op);
10224 else
10225 r = NULL;
10226 if (!r)
10227 {
10228 char *save = input_line_pointer;
10229 char c;
10230 symbolS *symbolP;
10231
10232 input_line_pointer = reg_string;
d02603dc 10233 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10234 symbolP = symbol_find (reg_string);
10235 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10236 {
10237 const expressionS *e = symbol_get_value_expression (symbolP);
10238
0398aac5 10239 know (e->X_op == O_register);
4eed87de 10240 know (e->X_add_number >= 0
c3fe08fa 10241 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10242 r = i386_regtab + e->X_add_number;
d3bb6b49 10243 if ((r->reg_flags & RegVRex))
86fa6981 10244 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10245 *end_op = input_line_pointer;
10246 }
10247 *input_line_pointer = c;
10248 input_line_pointer = save;
10249 }
10250 return r;
10251}
10252
10253int
10254i386_parse_name (char *name, expressionS *e, char *nextcharP)
10255{
10256 const reg_entry *r;
10257 char *end = input_line_pointer;
10258
10259 *end = *nextcharP;
10260 r = parse_register (name, &input_line_pointer);
10261 if (r && end <= input_line_pointer)
10262 {
10263 *nextcharP = *input_line_pointer;
10264 *input_line_pointer = 0;
10265 e->X_op = O_register;
10266 e->X_add_number = r - i386_regtab;
10267 return 1;
10268 }
10269 input_line_pointer = end;
10270 *end = 0;
ee86248c 10271 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10272}
10273
10274void
10275md_operand (expressionS *e)
10276{
ee86248c
JB		 10277 char *end;
10278 const reg_entry *r;
4d1bb795 10279
ee86248c
JB		 10280 switch (*input_line_pointer)
10281 {
10282 case REGISTER_PREFIX:
10283 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10284 if (r)
10285 {
10286 e->X_op = O_register;
10287 e->X_add_number = r - i386_regtab;
10288 input_line_pointer = end;
10289 }
ee86248c
JB		 10290 break;
10291
10292 case '[':
9c2799c2 10293 gas_assert (intel_syntax);
ee86248c
JB		 10294 end = input_line_pointer++;
10295 expression (e);
10296 if (*input_line_pointer == ']')
10297 {
10298 ++input_line_pointer;
10299 e->X_op_symbol = make_expr_symbol (e);
10300 e->X_add_symbol = NULL;
10301 e->X_add_number = 0;
10302 e->X_op = O_index;
10303 }
10304 else
10305 {
10306 e->X_op = O_absent;
10307 input_line_pointer = end;
10308 }
10309 break;
4d1bb795
JB		 10310 }
10311}
10312
252b5132 10313\f
4cc782b5 10314#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10315const char *md_shortopts = "kVQ:sqnO::";
252b5132 10316#else
b6f8c7c4 10317const char *md_shortopts = "qnO::";
252b5132 10318#endif
6e0b89ee 10319
3e73aa7c 10320#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10321#define OPTION_64 (OPTION_MD_BASE + 1)
10322#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10323#define OPTION_MARCH (OPTION_MD_BASE + 3)
10324#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10325#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10326#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10327#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10328#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10329#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 10330#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10331#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10332#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10333#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10334#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10335#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10336#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10337#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10338#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10339#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10340#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10341#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10342#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10343#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10344#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 10345#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 10346
99ad8390
NC		 10347struct option md_longopts[] =
10348{
3e73aa7c 10349 {"32", no_argument, NULL, OPTION_32},
321098a5 10350#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10351 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10352 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10353#endif
10354#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10355 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10356 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10357#endif
b3b91714 10358 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10359 {"march", required_argument, NULL, OPTION_MARCH},
10360 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10361 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10362 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10363 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10364 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10365 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 10366 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10367 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10368 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10369 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10370 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10371 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10372 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10373# if defined (TE_PE) || defined (TE_PEP)
10374 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10375#endif
d1982f93 10376 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10377 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10378 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10379 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10380 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10381 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10382 {NULL, no_argument, NULL, 0}
10383};
10384size_t md_longopts_size = sizeof (md_longopts);
10385
10386int
17b9d67d 10387md_parse_option (int c, const char *arg)
252b5132 10388{
91d6fa6a 10389 unsigned int j;
293f5f65 10390 char *arch, *next, *saved;
9103f4f4 10391
252b5132
RH		 10392 switch (c)
10393 {
12b55ccc
L		 10394 case 'n':
10395 optimize_align_code = 0;
10396 break;
10397
a38cf1db
AM		 10398 case 'q':
10399 quiet_warnings = 1;
252b5132
RH		 10400 break;
10401
10402#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10403 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10404 should be emitted or not. FIXME: Not implemented. */
10405 case 'Q':
252b5132
RH		 10406 break;
10407
10408 /* -V: SVR4 argument to print version ID. */
10409 case 'V':
10410 print_version_id ();
10411 break;
10412
a38cf1db
AM		 10413 /* -k: Ignore for FreeBSD compatibility. */
10414 case 'k':
252b5132 10415 break;
4cc782b5
ILT		 10416
10417 case 's':
10418 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10419 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10420 break;
8dcea932
L		 10421
10422 case OPTION_MSHARED:
10423 shared = 1;
10424 break;
99ad8390 10425#endif
321098a5 10426#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10427 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10428 case OPTION_64:
10429 {
10430 const char **list, **l;
10431
3e73aa7c
JH		 10432 list = bfd_target_list ();
10433 for (l = list; *l != NULL; l++)
8620418b 10434 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10435 || strcmp (*l, "coff-x86-64") == 0
10436 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10437 || strcmp (*l, "pei-x86-64") == 0
10438 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10439 {
10440 default_arch = "x86_64";
10441 break;
10442 }
3e73aa7c 10443 if (*l == NULL)
2b5d6a91 10444 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10445 free (list);
10446 }
10447 break;
10448#endif
252b5132 10449
351f65ca 10450#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10451 case OPTION_X32:
351f65ca
L		 10452 if (IS_ELF)
10453 {
10454 const char **list, **l;
10455
10456 list = bfd_target_list ();
10457 for (l = list; *l != NULL; l++)
10458 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10459 {
10460 default_arch = "x86_64:32";
10461 break;
10462 }
10463 if (*l == NULL)
2b5d6a91 10464 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10465 free (list);
10466 }
10467 else
10468 as_fatal (_("32bit x86_64 is only supported for ELF"));
10469 break;
10470#endif
10471
6e0b89ee
AM		 10472 case OPTION_32:
10473 default_arch = "i386";
10474 break;
10475
b3b91714
AM		 10476 case OPTION_DIVIDE:
10477#ifdef SVR4_COMMENT_CHARS
10478 {
10479 char *n, *t;
10480 const char *s;
10481
add39d23 10482 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10483 t = n;
10484 for (s = i386_comment_chars; *s != '\0'; s++)
10485 if (*s != '/')
10486 *t++ = *s;
10487 *t = '\0';
10488 i386_comment_chars = n;
10489 }
10490#endif
10491 break;
10492
9103f4f4 10493 case OPTION_MARCH:
293f5f65
L		 10494 saved = xstrdup (arg);
10495 arch = saved;
10496 /* Allow -march=+nosse. */
10497 if (*arch == '+')
10498 arch++;
6305a203 10499 do
9103f4f4 10500 {
6305a203 10501 if (*arch == '.')
2b5d6a91 10502 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10503 next = strchr (arch, '+');
10504 if (next)
10505 *next++ = '\0';
91d6fa6a 10506 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10507 {
91d6fa6a 10508 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10509 {
6305a203 10510 /* Processor. */
1ded5609
JB		 10511 if (! cpu_arch[j].flags.bitfield.cpui386)
10512 continue;
10513
91d6fa6a 10514 cpu_arch_name = cpu_arch[j].name;
6305a203 10515 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10516 cpu_arch_flags = cpu_arch[j].flags;
10517 cpu_arch_isa = cpu_arch[j].type;
10518 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10519 if (!cpu_arch_tune_set)
10520 {
10521 cpu_arch_tune = cpu_arch_isa;
10522 cpu_arch_tune_flags = cpu_arch_isa_flags;
10523 }
10524 break;
10525 }
91d6fa6a
NC		 10526 else if (*cpu_arch [j].name == '.'
10527 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10528 {
33eaf5de 10529 /* ISA extension. */
6305a203 10530 i386_cpu_flags flags;
309d3373 10531
293f5f65
L		 10532 flags = cpu_flags_or (cpu_arch_flags,
10533 cpu_arch[j].flags);
81486035 10534
5b64d091 10535 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10536 {
10537 if (cpu_sub_arch_name)
10538 {
10539 char *name = cpu_sub_arch_name;
10540 cpu_sub_arch_name = concat (name,
91d6fa6a 10541 cpu_arch[j].name,
1bf57e9f 10542 (const char *) NULL);
6305a203
L		 10543 free (name);
10544 }
10545 else
91d6fa6a 10546 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10547 cpu_arch_flags = flags;
a586129e 10548 cpu_arch_isa_flags = flags;
6305a203
L		 10549 }
10550 break;
ccc9c027 10551 }
9103f4f4 10552 }
6305a203 10553
293f5f65
L		 10554 if (j >= ARRAY_SIZE (cpu_arch))
10555 {
33eaf5de 10556 /* Disable an ISA extension. */
293f5f65
L		 10557 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10558 if (strcmp (arch, cpu_noarch [j].name) == 0)
10559 {
10560 i386_cpu_flags flags;
10561
10562 flags = cpu_flags_and_not (cpu_arch_flags,
10563 cpu_noarch[j].flags);
10564 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10565 {
10566 if (cpu_sub_arch_name)
10567 {
10568 char *name = cpu_sub_arch_name;
10569 cpu_sub_arch_name = concat (arch,
10570 (const char *) NULL);
10571 free (name);
10572 }
10573 else
10574 cpu_sub_arch_name = xstrdup (arch);
10575 cpu_arch_flags = flags;
10576 cpu_arch_isa_flags = flags;
10577 }
10578 break;
10579 }
10580
10581 if (j >= ARRAY_SIZE (cpu_noarch))
10582 j = ARRAY_SIZE (cpu_arch);
10583 }
10584
91d6fa6a 10585 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10586 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10587
10588 arch = next;
9103f4f4 10589 }
293f5f65
L		 10590 while (next != NULL);
10591 free (saved);
9103f4f4
L		 10592 break;
10593
10594 case OPTION_MTUNE:
10595 if (*arg == '.')
2b5d6a91 10596 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10597 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10598 {
91d6fa6a 10599 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10600 {
ccc9c027 10601 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10602 cpu_arch_tune = cpu_arch [j].type;
10603 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10604 break;
10605 }
10606 }
91d6fa6a 10607 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10608 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10609 break;
10610
1efbbeb4
L		 10611 case OPTION_MMNEMONIC:
10612 if (strcasecmp (arg, "att") == 0)
10613 intel_mnemonic = 0;
10614 else if (strcasecmp (arg, "intel") == 0)
10615 intel_mnemonic = 1;
10616 else
2b5d6a91 10617 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10618 break;
10619
10620 case OPTION_MSYNTAX:
10621 if (strcasecmp (arg, "att") == 0)
10622 intel_syntax = 0;
10623 else if (strcasecmp (arg, "intel") == 0)
10624 intel_syntax = 1;
10625 else
2b5d6a91 10626 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10627 break;
10628
10629 case OPTION_MINDEX_REG:
10630 allow_index_reg = 1;
10631 break;
10632
10633 case OPTION_MNAKED_REG:
10634 allow_naked_reg = 1;
10635 break;
10636
10637 case OPTION_MOLD_GCC:
10638 old_gcc = 1;
1efbbeb4
L		 10639 break;
10640
c0f3af97
L		 10641 case OPTION_MSSE2AVX:
10642 sse2avx = 1;
10643 break;
10644
daf50ae7
L		 10645 case OPTION_MSSE_CHECK:
10646 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10647 sse_check = check_error;
daf50ae7 10648 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10649 sse_check = check_warning;
daf50ae7 10650 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10651 sse_check = check_none;
daf50ae7 10652 else
2b5d6a91 10653 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10654 break;
10655
7bab8ab5
JB		 10656 case OPTION_MOPERAND_CHECK:
10657 if (strcasecmp (arg, "error") == 0)
10658 operand_check = check_error;
10659 else if (strcasecmp (arg, "warning") == 0)
10660 operand_check = check_warning;
10661 else if (strcasecmp (arg, "none") == 0)
10662 operand_check = check_none;
10663 else
10664 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10665 break;
10666
539f890d
L		 10667 case OPTION_MAVXSCALAR:
10668 if (strcasecmp (arg, "128") == 0)
10669 avxscalar = vex128;
10670 else if (strcasecmp (arg, "256") == 0)
10671 avxscalar = vex256;
10672 else
2b5d6a91 10673 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10674 break;
10675
7e8b059b
L		 10676 case OPTION_MADD_BND_PREFIX:
10677 add_bnd_prefix = 1;
10678 break;
10679
43234a1e
L		 10680 case OPTION_MEVEXLIG:
10681 if (strcmp (arg, "128") == 0)
10682 evexlig = evexl128;
10683 else if (strcmp (arg, "256") == 0)
10684 evexlig = evexl256;
10685 else if (strcmp (arg, "512") == 0)
10686 evexlig = evexl512;
10687 else
10688 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10689 break;
10690
d3d3c6db
IT		 10691 case OPTION_MEVEXRCIG:
10692 if (strcmp (arg, "rne") == 0)
10693 evexrcig = rne;
10694 else if (strcmp (arg, "rd") == 0)
10695 evexrcig = rd;
10696 else if (strcmp (arg, "ru") == 0)
10697 evexrcig = ru;
10698 else if (strcmp (arg, "rz") == 0)
10699 evexrcig = rz;
10700 else
10701 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10702 break;
10703
43234a1e
L		 10704 case OPTION_MEVEXWIG:
10705 if (strcmp (arg, "0") == 0)
10706 evexwig = evexw0;
10707 else if (strcmp (arg, "1") == 0)
10708 evexwig = evexw1;
10709 else
10710 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10711 break;
10712
167ad85b
TG		 10713# if defined (TE_PE) || defined (TE_PEP)
10714 case OPTION_MBIG_OBJ:
10715 use_big_obj = 1;
10716 break;
10717#endif
10718
d1982f93 10719 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10720 if (strcasecmp (arg, "yes") == 0)
10721 omit_lock_prefix = 1;
10722 else if (strcasecmp (arg, "no") == 0)
10723 omit_lock_prefix = 0;
10724 else
10725 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10726 break;
10727
e4e00185
AS		 10728 case OPTION_MFENCE_AS_LOCK_ADD:
10729 if (strcasecmp (arg, "yes") == 0)
10730 avoid_fence = 1;
10731 else if (strcasecmp (arg, "no") == 0)
10732 avoid_fence = 0;
10733 else
10734 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10735 break;
10736
0cb4071e
L		 10737 case OPTION_MRELAX_RELOCATIONS:
10738 if (strcasecmp (arg, "yes") == 0)
10739 generate_relax_relocations = 1;
10740 else if (strcasecmp (arg, "no") == 0)
10741 generate_relax_relocations = 0;
10742 else
10743 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10744 break;
10745
5db04b09 10746 case OPTION_MAMD64:
e89c5eaa 10747 intel64 = 0;
5db04b09
L		 10748 break;
10749
10750 case OPTION_MINTEL64:
e89c5eaa 10751 intel64 = 1;
5db04b09
L		 10752 break;
10753
b6f8c7c4
L		 10754 case 'O':
10755 if (arg == NULL)
10756 {
10757 optimize = 1;
10758 /* Turn off -Os. */
10759 optimize_for_space = 0;
10760 }
10761 else if (*arg == 's')
10762 {
10763 optimize_for_space = 1;
10764 /* Turn on all encoding optimizations. */
10765 optimize = -1;
10766 }
10767 else
10768 {
10769 optimize = atoi (arg);
10770 /* Turn off -Os. */
10771 optimize_for_space = 0;
10772 }
10773 break;
10774
252b5132
RH		 10775 default:
10776 return 0;
10777 }
10778 return 1;
10779}
10780
8a2c8fef
L		 10781#define MESSAGE_TEMPLATE \
10782" "
10783
293f5f65
L		 10784static char *
10785output_message (FILE *stream, char *p, char *message, char *start,
10786 int *left_p, const char *name, int len)
10787{
10788 int size = sizeof (MESSAGE_TEMPLATE);
10789 int left = *left_p;
10790
10791 /* Reserve 2 spaces for ", " or ",\0" */
10792 left -= len + 2;
10793
10794 /* Check if there is any room. */
10795 if (left >= 0)
10796 {
10797 if (p != start)
10798 {
10799 *p++ = ',';
10800 *p++ = ' ';
10801 }
10802 p = mempcpy (p, name, len);
10803 }
10804 else
10805 {
10806 /* Output the current message now and start a new one. */
10807 *p++ = ',';
10808 *p = '\0';
10809 fprintf (stream, "%s\n", message);
10810 p = start;
10811 left = size - (start - message) - len - 2;
10812
10813 gas_assert (left >= 0);
10814
10815 p = mempcpy (p, name, len);
10816 }
10817
10818 *left_p = left;
10819 return p;
10820}
10821
8a2c8fef 10822static void
1ded5609 10823show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10824{
10825 static char message[] = MESSAGE_TEMPLATE;
10826 char *start = message + 27;
10827 char *p;
10828 int size = sizeof (MESSAGE_TEMPLATE);
10829 int left;
10830 const char *name;
10831 int len;
10832 unsigned int j;
10833
10834 p = start;
10835 left = size - (start - message);
10836 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10837 {
10838 /* Should it be skipped? */
10839 if (cpu_arch [j].skip)
10840 continue;
10841
10842 name = cpu_arch [j].name;
10843 len = cpu_arch [j].len;
10844 if (*name == '.')
10845 {
10846 /* It is an extension. Skip if we aren't asked to show it. */
10847 if (ext)
10848 {
10849 name++;
10850 len--;
10851 }
10852 else
10853 continue;
10854 }
10855 else if (ext)
10856 {
10857 /* It is an processor. Skip if we show only extension. */
10858 continue;
10859 }
1ded5609
JB		 10860 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10861 {
10862 /* It is an impossible processor - skip. */
10863 continue;
10864 }
8a2c8fef 10865
293f5f65 10866 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10867 }
10868
293f5f65
L		 10869 /* Display disabled extensions. */
10870 if (ext)
10871 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10872 {
10873 name = cpu_noarch [j].name;
10874 len = cpu_noarch [j].len;
10875 p = output_message (stream, p, message, start, &left, name,
10876 len);
10877 }
10878
8a2c8fef
L		 10879 *p = '\0';
10880 fprintf (stream, "%s\n", message);
10881}
10882
252b5132 10883void
8a2c8fef 10884md_show_usage (FILE *stream)
252b5132 10885{
4cc782b5
ILT		 10886#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10887 fprintf (stream, _("\
a38cf1db
AM		 10888 -Q ignored\n\
10889 -V print assembler version number\n\
b3b91714
AM		 10890 -k ignored\n"));
10891#endif
10892 fprintf (stream, _("\
12b55ccc 10893 -n Do not optimize code alignment\n\
b3b91714
AM		 10894 -q quieten some warnings\n"));
10895#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10896 fprintf (stream, _("\
a38cf1db 10897 -s ignored\n"));
b3b91714 10898#endif
321098a5
L		 10899#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10900 || defined (TE_PE) || defined (TE_PEP))
751d281c 10901 fprintf (stream, _("\
570561f7 10902 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10903#endif
b3b91714
AM		 10904#ifdef SVR4_COMMENT_CHARS
10905 fprintf (stream, _("\
10906 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10907#else
10908 fprintf (stream, _("\
b3b91714 10909 --divide ignored\n"));
4cc782b5 10910#endif
9103f4f4 10911 fprintf (stream, _("\
6305a203 10912 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10913 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10914 show_arch (stream, 0, 1);
8a2c8fef
L		 10915 fprintf (stream, _("\
10916 EXTENSION is combination of:\n"));
1ded5609 10917 show_arch (stream, 1, 0);
6305a203 10918 fprintf (stream, _("\
8a2c8fef 10919 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10920 show_arch (stream, 0, 0);
ba104c83 10921 fprintf (stream, _("\
c0f3af97
L		 10922 -msse2avx encode SSE instructions with VEX prefix\n"));
10923 fprintf (stream, _("\
daf50ae7
L		 10924 -msse-check=[none|error|warning]\n\
10925 check SSE instructions\n"));
10926 fprintf (stream, _("\
7bab8ab5
JB		 10927 -moperand-check=[none|error|warning]\n\
10928 check operand combinations for validity\n"));
10929 fprintf (stream, _("\
539f890d
L		 10930 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10931 length\n"));
10932 fprintf (stream, _("\
43234a1e
L		 10933 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10934 length\n"));
10935 fprintf (stream, _("\
10936 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10937 for EVEX.W bit ignored instructions\n"));
10938 fprintf (stream, _("\
d3d3c6db
IT		 10939 -mevexrcig=[rne|rd|ru|rz]\n\
10940 encode EVEX instructions with specific EVEX.RC value\n\
10941 for SAE-only ignored instructions\n"));
10942 fprintf (stream, _("\
ba104c83
L		 10943 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10944 fprintf (stream, _("\
10945 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10946 fprintf (stream, _("\
10947 -mindex-reg support pseudo index registers\n"));
10948 fprintf (stream, _("\
10949 -mnaked-reg don't require `%%' prefix for registers\n"));
10950 fprintf (stream, _("\
10951 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10952 fprintf (stream, _("\
10953 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10954 fprintf (stream, _("\
10955 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10956# if defined (TE_PE) || defined (TE_PEP)
10957 fprintf (stream, _("\
10958 -mbig-obj generate big object files\n"));
10959#endif
d022bddd
IT		 10960 fprintf (stream, _("\
10961 -momit-lock-prefix=[no|yes]\n\
10962 strip all lock prefixes\n"));
5db04b09 10963 fprintf (stream, _("\
e4e00185
AS		 10964 -mfence-as-lock-add=[no|yes]\n\
10965 encode lfence, mfence and sfence as\n\
10966 lock addl $0x0, (%%{re}sp)\n"));
10967 fprintf (stream, _("\
0cb4071e
L		 10968 -mrelax-relocations=[no|yes]\n\
10969 generate relax relocations\n"));
10970 fprintf (stream, _("\
5db04b09
L		 10971 -mamd64 accept only AMD64 ISA\n"));
10972 fprintf (stream, _("\
10973 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10974}
10975
3e73aa7c 10976#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10977 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10978 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10979
10980/* Pick the target format to use. */
10981
47926f60 10982const char *
e3bb37b5 10983i386_target_format (void)
252b5132 10984{
351f65ca
L		 10985 if (!strncmp (default_arch, "x86_64", 6))
10986 {
10987 update_code_flag (CODE_64BIT, 1);
10988 if (default_arch[6] == '\0')
7f56bc95 10989 x86_elf_abi = X86_64_ABI;
351f65ca 10990 else
7f56bc95 10991 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10992 }
3e73aa7c 10993 else if (!strcmp (default_arch, "i386"))
78f12dd3 10994 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10995 else if (!strcmp (default_arch, "iamcu"))
10996 {
10997 update_code_flag (CODE_32BIT, 1);
10998 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10999 {
11000 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11001 cpu_arch_name = "iamcu";
11002 cpu_sub_arch_name = NULL;
11003 cpu_arch_flags = iamcu_flags;
11004 cpu_arch_isa = PROCESSOR_IAMCU;
11005 cpu_arch_isa_flags = iamcu_flags;
11006 if (!cpu_arch_tune_set)
11007 {
11008 cpu_arch_tune = cpu_arch_isa;
11009 cpu_arch_tune_flags = cpu_arch_isa_flags;
11010 }
11011 }
8d471ec1 11012 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11013 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11014 cpu_arch_name);
11015 }
3e73aa7c 11016 else
2b5d6a91 11017 as_fatal (_("unknown architecture"));
89507696
JB		 11018
11019 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11020 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11021 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11022 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11023
252b5132
RH		 11024 switch (OUTPUT_FLAVOR)
11025 {
9384f2ff 11026#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11027 case bfd_target_aout_flavour:
47926f60 11028 return AOUT_TARGET_FORMAT;
4c63da97 11029#endif
9384f2ff
AM		 11030#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11031# if defined (TE_PE) || defined (TE_PEP)
11032 case bfd_target_coff_flavour:
167ad85b
TG		 11033 if (flag_code == CODE_64BIT)
11034 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11035 else
11036 return "pe-i386";
9384f2ff 11037# elif defined (TE_GO32)
0561d57c
JK		 11038 case bfd_target_coff_flavour:
11039 return "coff-go32";
9384f2ff 11040# else
252b5132
RH		 11041 case bfd_target_coff_flavour:
11042 return "coff-i386";
9384f2ff 11043# endif
4c63da97 11044#endif
3e73aa7c 11045#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11046 case bfd_target_elf_flavour:
3e73aa7c 11047 {
351f65ca
L		 11048 const char *format;
11049
11050 switch (x86_elf_abi)
4fa24527 11051 {
351f65ca
L		 11052 default:
11053 format = ELF_TARGET_FORMAT;
11054 break;
7f56bc95 11055 case X86_64_ABI:
351f65ca 11056 use_rela_relocations = 1;
4fa24527 11057 object_64bit = 1;
351f65ca
L		 11058 format = ELF_TARGET_FORMAT64;
11059 break;
7f56bc95 11060 case X86_64_X32_ABI:
4fa24527 11061 use_rela_relocations = 1;
351f65ca 11062 object_64bit = 1;
862be3fb 11063 disallow_64bit_reloc = 1;
351f65ca
L		 11064 format = ELF_TARGET_FORMAT32;
11065 break;
4fa24527 11066 }
3632d14b 11067 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11068 {
7f56bc95 11069 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11070 as_fatal (_("Intel L1OM is 64bit only"));
11071 return ELF_TARGET_L1OM_FORMAT;
11072 }
b49f93f6 11073 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11074 {
11075 if (x86_elf_abi != X86_64_ABI)
11076 as_fatal (_("Intel K1OM is 64bit only"));
11077 return ELF_TARGET_K1OM_FORMAT;
11078 }
81486035
L		 11079 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11080 {
11081 if (x86_elf_abi != I386_ABI)
11082 as_fatal (_("Intel MCU is 32bit only"));
11083 return ELF_TARGET_IAMCU_FORMAT;
11084 }
8a9036a4 11085 else
351f65ca 11086 return format;
3e73aa7c 11087 }
e57f8c65
TG		 11088#endif
11089#if defined (OBJ_MACH_O)
11090 case bfd_target_mach_o_flavour:
d382c579
TG		 11091 if (flag_code == CODE_64BIT)
11092 {
11093 use_rela_relocations = 1;
11094 object_64bit = 1;
11095 return "mach-o-x86-64";
11096 }
11097 else
11098 return "mach-o-i386";
4c63da97 11099#endif
252b5132
RH		 11100 default:
11101 abort ();
11102 return NULL;
11103 }
11104}
11105
47926f60 11106#endif /* OBJ_MAYBE_ more than one */
252b5132 11107\f
252b5132 11108symbolS *
7016a5d5 11109md_undefined_symbol (char *name)
252b5132 11110{
18dc2407
ILT		 11111 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11112 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11113 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11114 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11115 {
11116 if (!GOT_symbol)
11117 {
11118 if (symbol_find (name))
11119 as_bad (_("GOT already in symbol table"));
11120 GOT_symbol = symbol_new (name, undefined_section,
11121 (valueT) 0, &zero_address_frag);
11122 };
11123 return GOT_symbol;
11124 }
252b5132
RH		 11125 return 0;
11126}
11127
11128/* Round up a section size to the appropriate boundary. */
47926f60 11129
252b5132 11130valueT
7016a5d5 11131md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11132{
4c63da97
AM		 11133#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11134 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11135 {
11136 /* For a.out, force the section size to be aligned. If we don't do
11137 this, BFD will align it for us, but it will not write out the
11138 final bytes of the section. This may be a bug in BFD, but it is
11139 easier to fix it here since that is how the other a.out targets
11140 work. */
11141 int align;
11142
11143 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11144 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11145 }
252b5132
RH		 11146#endif
11147
11148 return size;
11149}
11150
11151/* On the i386, PC-relative offsets are relative to the start of the
11152 next instruction. That is, the address of the offset, plus its
11153 size, since the offset is always the last part of the insn. */
11154
11155long
e3bb37b5 11156md_pcrel_from (fixS *fixP)
252b5132
RH		 11157{
11158 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11159}
11160
11161#ifndef I386COFF
11162
11163static void
e3bb37b5 11164s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11165{
29b0f896 11166 int temp;
252b5132 11167
8a75718c
JB		 11168#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11169 if (IS_ELF)
11170 obj_elf_section_change_hook ();
11171#endif
252b5132
RH		 11172 temp = get_absolute_expression ();
11173 subseg_set (bss_section, (subsegT) temp);
11174 demand_empty_rest_of_line ();
11175}
11176
11177#endif
11178
252b5132 11179void
e3bb37b5 11180i386_validate_fix (fixS *fixp)
252b5132 11181{
02a86693 11182 if (fixp->fx_subsy)
252b5132 11183 {
02a86693 11184 if (fixp->fx_subsy == GOT_symbol)
23df1078 11185 {
02a86693
L		 11186 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11187 {
11188 if (!object_64bit)
11189 abort ();
11190#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11191 if (fixp->fx_tcbit2)
56ceb5b5
L		 11192 fixp->fx_r_type = (fixp->fx_tcbit
11193 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11194 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11195 else
11196#endif
11197 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11198 }
d6ab8113 11199 else
02a86693
L		 11200 {
11201 if (!object_64bit)
11202 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11203 else
11204 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11205 }
11206 fixp->fx_subsy = 0;
23df1078 11207 }
252b5132 11208 }
02a86693
L		 11209#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11210 else if (!object_64bit)
11211 {
11212 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11213 && fixp->fx_tcbit2)
11214 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11215 }
11216#endif
252b5132
RH		 11217}
11218
252b5132 11219arelent *
7016a5d5 11220tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11221{
11222 arelent *rel;
11223 bfd_reloc_code_real_type code;
11224
11225 switch (fixp->fx_r_type)
11226 {
8ce3d284 11227#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11228 case BFD_RELOC_SIZE32:
11229 case BFD_RELOC_SIZE64:
11230 if (S_IS_DEFINED (fixp->fx_addsy)
11231 && !S_IS_EXTERNAL (fixp->fx_addsy))
11232 {
11233 /* Resolve size relocation against local symbol to size of
11234 the symbol plus addend. */
11235 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11236 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11237 && !fits_in_unsigned_long (value))
11238 as_bad_where (fixp->fx_file, fixp->fx_line,
11239 _("symbol size computation overflow"));
11240 fixp->fx_addsy = NULL;
11241 fixp->fx_subsy = NULL;
11242 md_apply_fix (fixp, (valueT *) &value, NULL);
11243 return NULL;
11244 }
8ce3d284 11245#endif
1a0670f3 11246 /* Fall through. */
8fd4256d 11247
3e73aa7c
JH		 11248 case BFD_RELOC_X86_64_PLT32:
11249 case BFD_RELOC_X86_64_GOT32:
11250 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11251 case BFD_RELOC_X86_64_GOTPCRELX:
11252 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11253 case BFD_RELOC_386_PLT32:
11254 case BFD_RELOC_386_GOT32:
02a86693 11255 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11256 case BFD_RELOC_386_GOTOFF:
11257 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11258 case BFD_RELOC_386_TLS_GD:
11259 case BFD_RELOC_386_TLS_LDM:
11260 case BFD_RELOC_386_TLS_LDO_32:
11261 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11262 case BFD_RELOC_386_TLS_IE:
11263 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11264 case BFD_RELOC_386_TLS_LE_32:
11265 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11266 case BFD_RELOC_386_TLS_GOTDESC:
11267 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11268 case BFD_RELOC_X86_64_TLSGD:
11269 case BFD_RELOC_X86_64_TLSLD:
11270 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11271 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11272 case BFD_RELOC_X86_64_GOTTPOFF:
11273 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11274 case BFD_RELOC_X86_64_TPOFF64:
11275 case BFD_RELOC_X86_64_GOTOFF64:
11276 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11277 case BFD_RELOC_X86_64_GOT64:
11278 case BFD_RELOC_X86_64_GOTPCREL64:
11279 case BFD_RELOC_X86_64_GOTPC64:
11280 case BFD_RELOC_X86_64_GOTPLT64:
11281 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11282 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11283 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11284 case BFD_RELOC_RVA:
11285 case BFD_RELOC_VTABLE_ENTRY:
11286 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11287#ifdef TE_PE
11288 case BFD_RELOC_32_SECREL:
11289#endif
252b5132
RH		 11290 code = fixp->fx_r_type;
11291 break;
dbbaec26
L		 11292 case BFD_RELOC_X86_64_32S:
11293 if (!fixp->fx_pcrel)
11294 {
11295 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11296 code = fixp->fx_r_type;
11297 break;
11298 }
1a0670f3 11299 /* Fall through. */
252b5132 11300 default:
93382f6d 11301 if (fixp->fx_pcrel)
252b5132 11302 {
93382f6d
AM		 11303 switch (fixp->fx_size)
11304 {
11305 default:
b091f402
AM		 11306 as_bad_where (fixp->fx_file, fixp->fx_line,
11307 _("can not do %d byte pc-relative relocation"),
11308 fixp->fx_size);
93382f6d
AM		 11309 code = BFD_RELOC_32_PCREL;
11310 break;
11311 case 1: code = BFD_RELOC_8_PCREL; break;
11312 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11313 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11314#ifdef BFD64
11315 case 8: code = BFD_RELOC_64_PCREL; break;
11316#endif
93382f6d
AM		 11317 }
11318 }
11319 else
11320 {
11321 switch (fixp->fx_size)
11322 {
11323 default:
b091f402
AM		 11324 as_bad_where (fixp->fx_file, fixp->fx_line,
11325 _("can not do %d byte relocation"),
11326 fixp->fx_size);
93382f6d
AM		 11327 code = BFD_RELOC_32;
11328 break;
11329 case 1: code = BFD_RELOC_8; break;
11330 case 2: code = BFD_RELOC_16; break;
11331 case 4: code = BFD_RELOC_32; break;
937149dd 11332#ifdef BFD64
3e73aa7c 11333 case 8: code = BFD_RELOC_64; break;
937149dd 11334#endif
93382f6d 11335 }
252b5132
RH		 11336 }
11337 break;
11338 }
252b5132 11339
d182319b
JB		 11340 if ((code == BFD_RELOC_32
11341 || code == BFD_RELOC_32_PCREL
11342 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11343 && GOT_symbol
11344 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11345 {
4fa24527 11346 if (!object_64bit)
d6ab8113
JB		 11347 code = BFD_RELOC_386_GOTPC;
11348 else
11349 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11350 }
7b81dfbb
AJ		 11351 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11352 && GOT_symbol
11353 && fixp->fx_addsy == GOT_symbol)
11354 {
11355 code = BFD_RELOC_X86_64_GOTPC64;
11356 }
252b5132 11357
add39d23
TS		 11358 rel = XNEW (arelent);
11359 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11360 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11361
11362 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11363
3e73aa7c
JH		 11364 if (!use_rela_relocations)
11365 {
11366 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11367 vtable entry to be used in the relocation's section offset. */
11368 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11369 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11370#if defined (OBJ_COFF) && defined (TE_PE)
11371 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11372 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11373 else
11374#endif
c6682705 11375 rel->addend = 0;
3e73aa7c
JH		 11376 }
11377 /* Use the rela in 64bit mode. */
252b5132 11378 else
3e73aa7c 11379 {
862be3fb
L		 11380 if (disallow_64bit_reloc)
11381 switch (code)
11382 {
862be3fb
L		 11383 case BFD_RELOC_X86_64_DTPOFF64:
11384 case BFD_RELOC_X86_64_TPOFF64:
11385 case BFD_RELOC_64_PCREL:
11386 case BFD_RELOC_X86_64_GOTOFF64:
11387 case BFD_RELOC_X86_64_GOT64:
11388 case BFD_RELOC_X86_64_GOTPCREL64:
11389 case BFD_RELOC_X86_64_GOTPC64:
11390 case BFD_RELOC_X86_64_GOTPLT64:
11391 case BFD_RELOC_X86_64_PLTOFF64:
11392 as_bad_where (fixp->fx_file, fixp->fx_line,
11393 _("cannot represent relocation type %s in x32 mode"),
11394 bfd_get_reloc_code_name (code));
11395 break;
11396 default:
11397 break;
11398 }
11399
062cd5e7
AS		 11400 if (!fixp->fx_pcrel)
11401 rel->addend = fixp->fx_offset;
11402 else
11403 switch (code)
11404 {
11405 case BFD_RELOC_X86_64_PLT32:
11406 case BFD_RELOC_X86_64_GOT32:
11407 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11408 case BFD_RELOC_X86_64_GOTPCRELX:
11409 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11410 case BFD_RELOC_X86_64_TLSGD:
11411 case BFD_RELOC_X86_64_TLSLD:
11412 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11413 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11414 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11415 rel->addend = fixp->fx_offset - fixp->fx_size;
11416 break;
11417 default:
11418 rel->addend = (section->vma
11419 - fixp->fx_size
11420 + fixp->fx_addnumber
11421 + md_pcrel_from (fixp));
11422 break;
11423 }
3e73aa7c
JH		 11424 }
11425
252b5132
RH		 11426 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11427 if (rel->howto == NULL)
11428 {
11429 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11430 _("cannot represent relocation type %s"),
252b5132
RH		 11431 bfd_get_reloc_code_name (code));
11432 /* Set howto to a garbage value so that we can keep going. */
11433 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11434 gas_assert (rel->howto != NULL);
252b5132
RH		 11435 }
11436
11437 return rel;
11438}
11439
ee86248c 11440#include "tc-i386-intel.c"
54cfded0 11441
a60de03c
JB		 11442void
11443tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11444{
a60de03c
JB		 11445 int saved_naked_reg;
11446 char saved_register_dot;
54cfded0 11447
a60de03c
JB		 11448 saved_naked_reg = allow_naked_reg;
11449 allow_naked_reg = 1;
11450 saved_register_dot = register_chars['.'];
11451 register_chars['.'] = '.';
11452 allow_pseudo_reg = 1;
11453 expression_and_evaluate (exp);
11454 allow_pseudo_reg = 0;
11455 register_chars['.'] = saved_register_dot;
11456 allow_naked_reg = saved_naked_reg;
11457
e96d56a1 11458 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11459 {
a60de03c
JB		 11460 if ((addressT) exp->X_add_number < i386_regtab_size)
11461 {
11462 exp->X_op = O_constant;
11463 exp->X_add_number = i386_regtab[exp->X_add_number]
11464 .dw2_regnum[flag_code >> 1];
11465 }
11466 else
11467 exp->X_op = O_illegal;
54cfded0 11468 }
54cfded0
AM		 11469}
11470
11471void
11472tc_x86_frame_initial_instructions (void)
11473{
a60de03c
JB		 11474 static unsigned int sp_regno[2];
11475
11476 if (!sp_regno[flag_code >> 1])
11477 {
11478 char *saved_input = input_line_pointer;
11479 char sp[][4] = {"esp", "rsp"};
11480 expressionS exp;
a4447b93 11481
a60de03c
JB		 11482 input_line_pointer = sp[flag_code >> 1];
11483 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11484 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11485 sp_regno[flag_code >> 1] = exp.X_add_number;
11486 input_line_pointer = saved_input;
11487 }
a4447b93 11488
61ff971f
L		 11489 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11490 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11491}
d2b2c203 11492
d7921315
L		 11493int
11494x86_dwarf2_addr_size (void)
11495{
11496#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11497 if (x86_elf_abi == X86_64_X32_ABI)
11498 return 4;
11499#endif
11500 return bfd_arch_bits_per_address (stdoutput) / 8;
11501}
11502
d2b2c203
DJ		 11503int
11504i386_elf_section_type (const char *str, size_t len)
11505{
11506 if (flag_code == CODE_64BIT
11507 && len == sizeof ("unwind") - 1
11508 && strncmp (str, "unwind", 6) == 0)
11509 return SHT_X86_64_UNWIND;
11510
11511 return -1;
11512}
bb41ade5 11513
ad5fec3b
EB		 11514#ifdef TE_SOLARIS
11515void
11516i386_solaris_fix_up_eh_frame (segT sec)
11517{
11518 if (flag_code == CODE_64BIT)
11519 elf_section_type (sec) = SHT_X86_64_UNWIND;
11520}
11521#endif
11522
bb41ade5
AM		 11523#ifdef TE_PE
11524void
11525tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11526{
91d6fa6a 11527 expressionS exp;
bb41ade5 11528
91d6fa6a
NC		 11529 exp.X_op = O_secrel;
11530 exp.X_add_symbol = symbol;
11531 exp.X_add_number = 0;
11532 emit_expr (&exp, size);
bb41ade5
AM		 11533}
11534#endif
3b22753a
L		 11535
11536#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11537/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11538
01e1a5bc 11539bfd_vma
6d4af3c2 11540x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11541{
11542 if (flag_code == CODE_64BIT)
11543 {
11544 if (letter == 'l')
11545 return SHF_X86_64_LARGE;
11546
8f3bae45 11547 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11548 }
3b22753a 11549 else
8f3bae45 11550 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11551 return -1;
11552}
11553
01e1a5bc 11554bfd_vma
3b22753a
L		 11555x86_64_section_word (char *str, size_t len)
11556{
8620418b 11557 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11558 return SHF_X86_64_LARGE;
11559
11560 return -1;
11561}
11562
11563static void
11564handle_large_common (int small ATTRIBUTE_UNUSED)
11565{
11566 if (flag_code != CODE_64BIT)
11567 {
11568 s_comm_internal (0, elf_common_parse);
11569 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11570 }
11571 else
11572 {
11573 static segT lbss_section;
11574 asection *saved_com_section_ptr = elf_com_section_ptr;
11575 asection *saved_bss_section = bss_section;
11576
11577 if (lbss_section == NULL)
11578 {
11579 flagword applicable;
11580 segT seg = now_seg;
11581 subsegT subseg = now_subseg;
11582
11583 /* The .lbss section is for local .largecomm symbols. */
11584 lbss_section = subseg_new (".lbss", 0);
11585 applicable = bfd_applicable_section_flags (stdoutput);
11586 bfd_set_section_flags (stdoutput, lbss_section,
11587 applicable & SEC_ALLOC);
11588 seg_info (lbss_section)->bss = 1;
11589
11590 subseg_set (seg, subseg);
11591 }
11592
11593 elf_com_section_ptr = &_bfd_elf_large_com_section;
11594 bss_section = lbss_section;
11595
11596 s_comm_internal (0, elf_common_parse);
11597
11598 elf_com_section_ptr = saved_com_section_ptr;
11599 bss_section = saved_bss_section;
11600 }
11601}
11602#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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