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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
31b2323c
L		 275/* Per instruction expressionS buffers: max displacements & immediates. */
276static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
277static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 278
47926f60
KH		 279/* Current operand we are working on. */
280static int this_operand;
252b5132 281
3e73aa7c
JH		 282/* We support four different modes. FLAG_CODE variable is used to distinguish
283 these. */
284
285enum flag_code {
286 CODE_32BIT,
287 CODE_16BIT,
288 CODE_64BIT };
f3c180ae 289#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 290
291static enum flag_code flag_code;
4fa24527 292static unsigned int object_64bit;
3e73aa7c
JH		 293static int use_rela_relocations = 0;
294
295/* The names used to print error messages. */
b77a7acd 296static const char *flag_code_names[] =
3e73aa7c
JH		 297 {
298 "32",
299 "16",
300 "64"
301 };
252b5132 302
47926f60
KH		 303/* 1 for intel syntax,
304 0 if att syntax. */
305static int intel_syntax = 0;
252b5132 306
47926f60
KH		 307/* 1 if register prefix % not required. */
308static int allow_naked_reg = 0;
252b5132 309
47926f60
KH		 310/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
311 leave, push, and pop instructions so that gcc has the same stack
312 frame as in 32 bit mode. */
313static char stackop_size = '\0';
eecb386c 314
12b55ccc
L		 315/* Non-zero to optimize code alignment. */
316int optimize_align_code = 1;
317
47926f60
KH		 318/* Non-zero to quieten some warnings. */
319static int quiet_warnings = 0;
a38cf1db 320
47926f60
KH		 321/* CPU name. */
322static const char *cpu_arch_name = NULL;
5c6af06e 323static const char *cpu_sub_arch_name = NULL;
a38cf1db 324
47926f60 325/* CPU feature flags. */
29b0f896 326static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 327
ccc9c027
L		 328/* If we have selected a cpu we are generating instructions for. */
329static int cpu_arch_tune_set = 0;
330
9103f4f4
L		 331/* Cpu we are generating instructions for. */
332static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
333
334/* CPU feature flags of cpu we are generating instructions for. */
335static unsigned int cpu_arch_tune_flags = 0;
336
ccc9c027
L		 337/* CPU instruction set architecture used. */
338static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
339
9103f4f4
L		 340/* CPU feature flags of instruction set architecture used. */
341static unsigned int cpu_arch_isa_flags = 0;
342
fddf5b5b
AM		 343/* If set, conditional jumps are not automatically promoted to handle
344 larger than a byte offset. */
345static unsigned int no_cond_jump_promotion = 0;
346
29b0f896 347/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 348static symbolS *GOT_symbol;
29b0f896 349
a4447b93
RH		 350/* The dwarf2 return column, adjusted for 32 or 64 bit. */
351unsigned int x86_dwarf2_return_column;
352
353/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
354int x86_cie_data_alignment;
355
252b5132 356/* Interface to relax_segment.
fddf5b5b
AM		 357 There are 3 major relax states for 386 jump insns because the
358 different types of jumps add different sizes to frags when we're
359 figuring out what sort of jump to choose to reach a given label. */
252b5132 360
47926f60 361/* Types. */
93c2a809
AM		 362#define UNCOND_JUMP 0
363#define COND_JUMP 1
364#define COND_JUMP86 2
fddf5b5b 365
47926f60 366/* Sizes. */
252b5132
RH		 367#define CODE16 1
368#define SMALL 0
29b0f896 369#define SMALL16 (SMALL | CODE16)
252b5132 370#define BIG 2
29b0f896 371#define BIG16 (BIG | CODE16)
252b5132
RH		 372
373#ifndef INLINE
374#ifdef __GNUC__
375#define INLINE __inline__
376#else
377#define INLINE
378#endif
379#endif
380
fddf5b5b
AM		 381#define ENCODE_RELAX_STATE(type, size) \
382 ((relax_substateT) (((type) << 2) | (size)))
383#define TYPE_FROM_RELAX_STATE(s) \
384 ((s) >> 2)
385#define DISP_SIZE_FROM_RELAX_STATE(s) \
386 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 387
388/* This table is used by relax_frag to promote short jumps to long
389 ones where necessary. SMALL (short) jumps may be promoted to BIG
390 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
391 don't allow a short jump in a 32 bit code segment to be promoted to
392 a 16 bit offset jump because it's slower (requires data size
393 prefix), and doesn't work, unless the destination is in the bottom
394 64k of the code segment (The top 16 bits of eip are zeroed). */
395
396const relax_typeS md_relax_table[] =
397{
24eab124
AM		 398 /* The fields are:
399 1) most positive reach of this state,
400 2) most negative reach of this state,
93c2a809 401 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 402 4) which index into the table to try if we can't fit into this one. */
252b5132 403
fddf5b5b 404 /* UNCOND_JUMP states. */
93c2a809
AM		 405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
407 /* dword jmp adds 4 bytes to frag:
408 0 extra opcode bytes, 4 displacement bytes. */
252b5132 409 {0, 0, 4, 0},
93c2a809
AM		 410 /* word jmp adds 2 byte2 to frag:
411 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 412 {0, 0, 2, 0},
413
93c2a809
AM		 414 /* COND_JUMP states. */
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
416 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
417 /* dword conditionals adds 5 bytes to frag:
418 1 extra opcode byte, 4 displacement bytes. */
419 {0, 0, 5, 0},
fddf5b5b 420 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 421 1 extra opcode byte, 2 displacement bytes. */
422 {0, 0, 3, 0},
423
424 /* COND_JUMP86 states. */
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
426 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
427 /* dword conditionals adds 5 bytes to frag:
428 1 extra opcode byte, 4 displacement bytes. */
429 {0, 0, 5, 0},
430 /* word conditionals add 4 bytes to frag:
431 1 displacement byte and a 3 byte long branch insn. */
432 {0, 0, 4, 0}
252b5132
RH		 433};
434
9103f4f4
L		 435static const arch_entry cpu_arch[] =
436{
437 {"generic32", PROCESSOR_GENERIC32,
d32cad65 438 Cpu186|Cpu286|Cpu386},
9103f4f4 439 {"generic64", PROCESSOR_GENERIC64,
d32cad65 440 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 441 |CpuMMX2|CpuSSE|CpuSSE2},
442 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 443 0},
9103f4f4 444 {"i186", PROCESSOR_UNKNOWN,
d32cad65 445 Cpu186},
9103f4f4 446 {"i286", PROCESSOR_UNKNOWN,
d32cad65 447 Cpu186|Cpu286},
9103f4f4 448 {"i386", PROCESSOR_GENERIC32,
d32cad65 449 Cpu186|Cpu286|Cpu386},
9103f4f4 450 {"i486", PROCESSOR_I486,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 452 {"i586", PROCESSOR_PENTIUM,
d32cad65 453 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 454 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 455 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 456 {"pentium", PROCESSOR_PENTIUM,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 458 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 459 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 460 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 461 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 462 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 464 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 465 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 466 |CpuMMX2|CpuSSE|CpuSSE2},
467 {"prescott", PROCESSOR_NOCONA,
d32cad65 468 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 469 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
470 {"nocona", PROCESSOR_NOCONA,
d32cad65 471 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 472 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 473 {"yonah", PROCESSOR_CORE,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 475 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 476 {"core", PROCESSOR_CORE,
d32cad65 477 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 478 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
479 {"merom", PROCESSOR_CORE2,
480 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
481 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
482 {"core2", PROCESSOR_CORE2,
483 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
484 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 485 {"k6", PROCESSOR_K6,
d32cad65 486 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 487 {"k6_2", PROCESSOR_K6,
d32cad65 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 489 {"athlon", PROCESSOR_ATHLON,
d32cad65 490 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 491 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
492 {"sledgehammer", PROCESSOR_K8,
d32cad65 493 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 494 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
495 {"opteron", PROCESSOR_K8,
d32cad65 496 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 497 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
498 {"k8", PROCESSOR_K8,
d32cad65 499 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 500 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 501 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 502 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
503 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
504 |CpuABM},
9103f4f4
L		 505 {".mmx", PROCESSOR_UNKNOWN,
506 CpuMMX},
507 {".sse", PROCESSOR_UNKNOWN,
508 CpuMMX|CpuMMX2|CpuSSE},
509 {".sse2", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
511 {".sse3", PROCESSOR_UNKNOWN,
512 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 513 {".ssse3", PROCESSOR_UNKNOWN,
514 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 515 {".3dnow", PROCESSOR_UNKNOWN,
516 CpuMMX|Cpu3dnow},
517 {".3dnowa", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
519 {".padlock", PROCESSOR_UNKNOWN,
520 CpuPadLock},
521 {".pacifica", PROCESSOR_UNKNOWN,
522 CpuSVME},
523 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 524 CpuSVME},
525 {".sse4a", PROCESSOR_UNKNOWN,
526 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
527 {".abm", PROCESSOR_UNKNOWN,
528 CpuABM}
e413e4e9
AM		 529};
530
29b0f896
AM		 531const pseudo_typeS md_pseudo_table[] =
532{
533#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
534 {"align", s_align_bytes, 0},
535#else
536 {"align", s_align_ptwo, 0},
537#endif
538 {"arch", set_cpu_arch, 0},
539#ifndef I386COFF
540 {"bss", s_bss, 0},
541#endif
542 {"ffloat", float_cons, 'f'},
543 {"dfloat", float_cons, 'd'},
544 {"tfloat", float_cons, 'x'},
545 {"value", cons, 2},
d182319b 546 {"slong", signed_cons, 4},
29b0f896
AM		 547 {"noopt", s_ignore, 0},
548 {"optim", s_ignore, 0},
549 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
550 {"code16", set_code_flag, CODE_16BIT},
551 {"code32", set_code_flag, CODE_32BIT},
552 {"code64", set_code_flag, CODE_64BIT},
553 {"intel_syntax", set_intel_syntax, 1},
554 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
556 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 557#else
558 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
559 {"loc", dwarf2_directive_loc, 0},
560 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 561#endif
6482c264
NC		 562#ifdef TE_PE
563 {"secrel32", pe_directive_secrel, 0},
564#endif
29b0f896
AM		 565 {0, 0, 0}
566};
567
568/* For interface with expression (). */
569extern char *input_line_pointer;
570
571/* Hash table for instruction mnemonic lookup. */
572static struct hash_control *op_hash;
573
574/* Hash table for register lookup. */
575static struct hash_control *reg_hash;
576\f
252b5132
RH		 577void
578i386_align_code (fragP, count)
579 fragS *fragP;
580 int count;
581{
ce8a8b2f
AM		 582 /* Various efficient no-op patterns for aligning code labels.
583 Note: Don't try to assemble the instructions in the comments.
584 0L and 0w are not legal. */
252b5132
RH		 585 static const char f32_1[] =
586 {0x90}; /* nop */
587 static const char f32_2[] =
ccc9c027 588 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 589 static const char f32_3[] =
590 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
591 static const char f32_4[] =
592 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
593 static const char f32_5[] =
594 {0x90, /* nop */
595 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
596 static const char f32_6[] =
597 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
598 static const char f32_7[] =
599 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
600 static const char f32_8[] =
601 {0x90, /* nop */
602 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
603 static const char f32_9[] =
604 {0x89,0xf6, /* movl %esi,%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
606 static const char f32_10[] =
607 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_11[] =
610 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_12[] =
613 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
614 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
615 static const char f32_13[] =
616 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
617 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
618 static const char f32_14[] =
619 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
620 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
621 static const char f32_15[] =
622 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 624 static const char f16_3[] =
625 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 626 static const char f16_4[] =
627 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
628 static const char f16_5[] =
629 {0x90, /* nop */
630 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
631 static const char f16_6[] =
632 {0x89,0xf6, /* mov %si,%si */
633 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
634 static const char f16_7[] =
635 {0x8d,0x74,0x00, /* lea 0(%si),%si */
636 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
637 static const char f16_8[] =
638 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
639 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
640 static const char *const f32_patt[] = {
641 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
642 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
643 };
644 static const char *const f16_patt[] = {
c3332e24 645 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 646 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
647 };
ccc9c027
L		 648 /* nopl (%[re]ax) */
649 static const char alt_3[] =
650 {0x0f,0x1f,0x00};
651 /* nopl 0(%[re]ax) */
652 static const char alt_4[] =
653 {0x0f,0x1f,0x40,0x00};
654 /* nopl 0(%[re]ax,%[re]ax,1) */
655 static const char alt_5[] =
656 {0x0f,0x1f,0x44,0x00,0x00};
657 /* nopw 0(%[re]ax,%[re]ax,1) */
658 static const char alt_6[] =
659 {0x66,0x0f,0x1f,0x44,0x00,0x00};
660 /* nopl 0L(%[re]ax) */
661 static const char alt_7[] =
662 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
663 /* nopl 0L(%[re]ax,%[re]ax,1) */
664 static const char alt_8[] =
665 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
666 /* nopw 0L(%[re]ax,%[re]ax,1) */
667 static const char alt_9[] =
668 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
669 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_10[] =
671 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
672 /* data16
673 nopw %cs:0L(%[re]ax,%[re]ax,1) */
674 static const char alt_long_11[] =
675 {0x66,
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 /* data16
678 data16
679 nopw %cs:0L(%[re]ax,%[re]ax,1) */
680 static const char alt_long_12[] =
681 {0x66,
682 0x66,
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
684 /* data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_13[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
693 /* data16
694 data16
695 data16
696 data16
697 nopw %cs:0L(%[re]ax,%[re]ax,1) */
698 static const char alt_long_14[] =
699 {0x66,
700 0x66,
701 0x66,
702 0x66,
703 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
704 /* data16
705 data16
706 data16
707 data16
708 data16
709 nopw %cs:0L(%[re]ax,%[re]ax,1) */
710 static const char alt_long_15[] =
711 {0x66,
712 0x66,
713 0x66,
714 0x66,
715 0x66,
716 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
717 /* nopl 0(%[re]ax,%[re]ax,1)
718 nopw 0(%[re]ax,%[re]ax,1) */
719 static const char alt_short_11[] =
720 {0x0f,0x1f,0x44,0x00,0x00,
721 0x66,0x0f,0x1f,0x44,0x00,0x00};
722 /* nopw 0(%[re]ax,%[re]ax,1)
723 nopw 0(%[re]ax,%[re]ax,1) */
724 static const char alt_short_12[] =
725 {0x66,0x0f,0x1f,0x44,0x00,0x00,
726 0x66,0x0f,0x1f,0x44,0x00,0x00};
727 /* nopw 0(%[re]ax,%[re]ax,1)
728 nopl 0L(%[re]ax) */
729 static const char alt_short_13[] =
730 {0x66,0x0f,0x1f,0x44,0x00,0x00,
731 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
732 /* nopl 0L(%[re]ax)
733 nopl 0L(%[re]ax) */
734 static const char alt_short_14[] =
735 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
736 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
737 /* nopl 0L(%[re]ax)
738 nopl 0L(%[re]ax,%[re]ax,1) */
739 static const char alt_short_15[] =
740 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
741 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
742 static const char *const alt_short_patt[] = {
743 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
744 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
745 alt_short_14, alt_short_15
746 };
747 static const char *const alt_long_patt[] = {
748 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
749 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
750 alt_long_14, alt_long_15
751 };
252b5132 752
33fef721
JH		 753 if (count <= 0 || count > 15)
754 return;
3e73aa7c 755
ccc9c027
L		 756 /* We need to decide which NOP sequence to use for 32bit and
757 64bit. When -mtune= is used:
758
759 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
760 f32_patt will be used.
050dfa73 761 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ef05d495 762 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 763 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 764 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 765 and PROCESSOR_GENERIC64, alt_short_patt will be used.
766
767 When -mtune= isn't used, alt_short_patt will be used if
768 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
769
770 When -march= or .arch is used, we can't use anything beyond
771 cpu_arch_isa_flags. */
772
773 if (flag_code == CODE_16BIT)
774 {
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
777 if (count > 8)
778 /* Adjust jump offset. */
779 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
780 }
781 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 782 {
33fef721
JH		 783 int i;
784 int nnops = (count + 3) / 4;
785 int len = count / nnops;
786 int remains = count - nnops * len;
787 int pos = 0;
788
ccc9c027
L		 789 /* The recommended way to pad 64bit code is to use NOPs preceded
790 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 791 for (i = 0; i < remains; i++)
252b5132 792 {
33fef721
JH		 793 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
794 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
795 pos += len + 1;
796 }
797 for (; i < nnops; i++)
798 {
799 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
800 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
801 pos += len;
252b5132 802 }
252b5132 803 }
33fef721 804 else
ccc9c027
L		 805 {
806 const char *const *patt = NULL;
807
808 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
809 {
810 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
811 switch (cpu_arch_tune)
812 {
813 case PROCESSOR_UNKNOWN:
814 /* We use cpu_arch_isa_flags to check if we SHOULD
815 optimize for Cpu686. */
816 if ((cpu_arch_isa_flags & Cpu686) != 0)
817 patt = alt_short_patt;
818 else
819 patt = f32_patt;
820 break;
ef05d495 821 case PROCESSOR_CORE2:
ccc9c027
L		 822 patt = alt_long_patt;
823 break;
824 case PROCESSOR_PENTIUMPRO:
825 case PROCESSOR_PENTIUM4:
826 case PROCESSOR_NOCONA:
ef05d495 827 case PROCESSOR_CORE:
ccc9c027
L		 828 case PROCESSOR_K6:
829 case PROCESSOR_ATHLON:
830 case PROCESSOR_K8:
831 case PROCESSOR_GENERIC64:
050dfa73 832 case PROCESSOR_AMDFAM10:
ccc9c027
L		 833 patt = alt_short_patt;
834 break;
835 case PROCESSOR_I486:
836 case PROCESSOR_PENTIUM:
837 case PROCESSOR_GENERIC32:
838 patt = f32_patt;
839 break;
840 }
841 }
842 else
843 {
844 switch (cpu_arch_tune)
845 {
846 case PROCESSOR_UNKNOWN:
847 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
848 PROCESSOR_UNKNOWN. */
849 abort ();
850 break;
851
852 case PROCESSOR_I486:
853 case PROCESSOR_PENTIUM:
854 case PROCESSOR_PENTIUMPRO:
855 case PROCESSOR_PENTIUM4:
856 case PROCESSOR_NOCONA:
ef05d495 857 case PROCESSOR_CORE:
ccc9c027
L		 858 case PROCESSOR_K6:
859 case PROCESSOR_ATHLON:
860 case PROCESSOR_K8:
050dfa73 861 case PROCESSOR_AMDFAM10:
ccc9c027
L		 862 case PROCESSOR_GENERIC32:
863 /* We use cpu_arch_isa_flags to check if we CAN optimize
864 for Cpu686. */
865 if ((cpu_arch_isa_flags & Cpu686) != 0)
866 patt = alt_short_patt;
867 else
868 patt = f32_patt;
869 break;
ef05d495 870 case PROCESSOR_CORE2:
ccc9c027
L		 871 if ((cpu_arch_isa_flags & Cpu686) != 0)
872 patt = alt_long_patt;
873 else
874 patt = f32_patt;
875 break;
876 case PROCESSOR_GENERIC64:
877 patt = alt_short_patt;
878 break;
879 }
880 }
881
33fef721 882 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 883 patt[count - 1], count);
884 }
33fef721 885 fragP->fr_var = count;
252b5132
RH		 886}
887
252b5132
RH		 888static INLINE unsigned int
889mode_from_disp_size (t)
890 unsigned int t;
891{
3e73aa7c 892 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 893}
894
895static INLINE int
896fits_in_signed_byte (num)
847f7ad4 897 offsetT num;
252b5132
RH		 898{
899 return (num >= -128) && (num <= 127);
47926f60 900}
252b5132
RH		 901
902static INLINE int
903fits_in_unsigned_byte (num)
847f7ad4 904 offsetT num;
252b5132
RH		 905{
906 return (num & 0xff) == num;
47926f60 907}
252b5132
RH		 908
909static INLINE int
910fits_in_unsigned_word (num)
847f7ad4 911 offsetT num;
252b5132
RH		 912{
913 return (num & 0xffff) == num;
47926f60 914}
252b5132
RH		 915
916static INLINE int
917fits_in_signed_word (num)
847f7ad4 918 offsetT num;
252b5132
RH		 919{
920 return (-32768 <= num) && (num <= 32767);
47926f60 921}
2a962e6d 922
3e73aa7c
JH		 923static INLINE int
924fits_in_signed_long (num)
925 offsetT num ATTRIBUTE_UNUSED;
926{
927#ifndef BFD64
928 return 1;
929#else
930 return (!(((offsetT) -1 << 31) & num)
931 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
932#endif
933} /* fits_in_signed_long() */
2a962e6d 934
3e73aa7c
JH		 935static INLINE int
936fits_in_unsigned_long (num)
937 offsetT num ATTRIBUTE_UNUSED;
938{
939#ifndef BFD64
940 return 1;
941#else
942 return (num & (((offsetT) 2 << 31) - 1)) == num;
943#endif
944} /* fits_in_unsigned_long() */
252b5132
RH		 945
946static int
947smallest_imm_type (num)
847f7ad4 948 offsetT num;
252b5132 949{
d32cad65 950 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 951 {
952 /* This code is disabled on the 486 because all the Imm1 forms
953 in the opcode table are slower on the i486. They're the
954 versions with the implicitly specified single-position
955 displacement, which has another syntax if you really want to
956 use that form. */
957 if (num == 1)
3e73aa7c 958 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 959 }
252b5132 960 return (fits_in_signed_byte (num)
3e73aa7c 961 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 962 : fits_in_unsigned_byte (num)
3e73aa7c 963 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 964 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 965 ? (Imm16 | Imm32 | Imm32S | Imm64)
966 : fits_in_signed_long (num)
967 ? (Imm32 | Imm32S | Imm64)
968 : fits_in_unsigned_long (num)
969 ? (Imm32 | Imm64)
970 : Imm64);
47926f60 971}
252b5132 972
847f7ad4
AM		 973static offsetT
974offset_in_range (val, size)
975 offsetT val;
976 int size;
977{
508866be 978 addressT mask;
ba2adb93 979
847f7ad4
AM		 980 switch (size)
981 {
508866be
L		 982 case 1: mask = ((addressT) 1 << 8) - 1; break;
983 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 984 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 985#ifdef BFD64
986 case 8: mask = ((addressT) 2 << 63) - 1; break;
987#endif
47926f60 988 default: abort ();
847f7ad4
AM		 989 }
990
ba2adb93 991 /* If BFD64, sign extend val. */
3e73aa7c
JH		 992 if (!use_rela_relocations)
993 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
994 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 995
47926f60 996 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 997 {
998 char buf1[40], buf2[40];
999
1000 sprint_value (buf1, val);
1001 sprint_value (buf2, val & mask);
1002 as_warn (_("%s shortened to %s"), buf1, buf2);
1003 }
1004 return val & mask;
1005}
1006
252b5132
RH		 1007/* Returns 0 if attempting to add a prefix where one from the same
1008 class already exists, 1 if non rep/repne added, 2 if rep/repne
1009 added. */
1010static int
1011add_prefix (prefix)
1012 unsigned int prefix;
1013{
1014 int ret = 1;
b1905489 1015 unsigned int q;
252b5132 1016
29b0f896
AM		 1017 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1018 && flag_code == CODE_64BIT)
b1905489
JB		 1019 {
1020 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1021 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1022 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1023 ret = 0;
1024 q = REX_PREFIX;
1025 }
3e73aa7c 1026 else
b1905489
JB		 1027 {
1028 switch (prefix)
1029 {
1030 default:
1031 abort ();
1032
1033 case CS_PREFIX_OPCODE:
1034 case DS_PREFIX_OPCODE:
1035 case ES_PREFIX_OPCODE:
1036 case FS_PREFIX_OPCODE:
1037 case GS_PREFIX_OPCODE:
1038 case SS_PREFIX_OPCODE:
1039 q = SEG_PREFIX;
1040 break;
1041
1042 case REPNE_PREFIX_OPCODE:
1043 case REPE_PREFIX_OPCODE:
1044 ret = 2;
1045 /* fall thru */
1046 case LOCK_PREFIX_OPCODE:
1047 q = LOCKREP_PREFIX;
1048 break;
1049
1050 case FWAIT_OPCODE:
1051 q = WAIT_PREFIX;
1052 break;
1053
1054 case ADDR_PREFIX_OPCODE:
1055 q = ADDR_PREFIX;
1056 break;
1057
1058 case DATA_PREFIX_OPCODE:
1059 q = DATA_PREFIX;
1060 break;
1061 }
1062 if (i.prefix[q] != 0)
1063 ret = 0;
1064 }
252b5132 1065
b1905489 1066 if (ret)
252b5132 1067 {
b1905489
JB		 1068 if (!i.prefix[q])
1069 ++i.prefixes;
1070 i.prefix[q] |= prefix;
252b5132 1071 }
b1905489
JB		 1072 else
1073 as_bad (_("same type of prefix used twice"));
252b5132 1074
252b5132
RH		 1075 return ret;
1076}
1077
1078static void
3e73aa7c 1079set_code_flag (value)
e5cb08ac 1080 int value;
eecb386c 1081{
3e73aa7c
JH		 1082 flag_code = value;
1083 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1084 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1085 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1086 {
1087 as_bad (_("64bit mode not supported on this CPU."));
1088 }
1089 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1090 {
1091 as_bad (_("32bit mode not supported on this CPU."));
1092 }
eecb386c
AM		 1093 stackop_size = '\0';
1094}
1095
1096static void
3e73aa7c
JH		 1097set_16bit_gcc_code_flag (new_code_flag)
1098 int new_code_flag;
252b5132 1099{
3e73aa7c
JH		 1100 flag_code = new_code_flag;
1101 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1102 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1103 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1104}
1105
1106static void
1107set_intel_syntax (syntax_flag)
eecb386c 1108 int syntax_flag;
252b5132
RH		 1109{
1110 /* Find out if register prefixing is specified. */
1111 int ask_naked_reg = 0;
1112
1113 SKIP_WHITESPACE ();
29b0f896 1114 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1115 {
1116 char *string = input_line_pointer;
1117 int e = get_symbol_end ();
1118
47926f60 1119 if (strcmp (string, "prefix") == 0)
252b5132 1120 ask_naked_reg = 1;
47926f60 1121 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1122 ask_naked_reg = -1;
1123 else
d0b47220 1124 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1125 *input_line_pointer = e;
1126 }
1127 demand_empty_rest_of_line ();
c3332e24 1128
252b5132
RH		 1129 intel_syntax = syntax_flag;
1130
1131 if (ask_naked_reg == 0)
f86103b7
AM		 1132 allow_naked_reg = (intel_syntax
1133 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1134 else
1135 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1136
1137 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1138 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1139}
1140
e413e4e9
AM		 1141static void
1142set_cpu_arch (dummy)
47926f60 1143 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1144{
47926f60 1145 SKIP_WHITESPACE ();
e413e4e9 1146
29b0f896 1147 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1148 {
1149 char *string = input_line_pointer;
1150 int e = get_symbol_end ();
9103f4f4 1151 unsigned int i;
e413e4e9 1152
9103f4f4 1153 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1154 {
1155 if (strcmp (string, cpu_arch[i].name) == 0)
1156 {
5c6af06e
JB		 1157 if (*string != '.')
1158 {
1159 cpu_arch_name = cpu_arch[i].name;
1160 cpu_sub_arch_name = NULL;
1161 cpu_arch_flags = (cpu_arch[i].flags
1162 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1163 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1164 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1165 if (!cpu_arch_tune_set)
1166 {
1167 cpu_arch_tune = cpu_arch_isa;
1168 cpu_arch_tune_flags = cpu_arch_isa_flags;
1169 }
5c6af06e
JB		 1170 break;
1171 }
1172 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1173 {
1174 cpu_sub_arch_name = cpu_arch[i].name;
1175 cpu_arch_flags |= cpu_arch[i].flags;
1176 }
1177 *input_line_pointer = e;
1178 demand_empty_rest_of_line ();
1179 return;
e413e4e9
AM		 1180 }
1181 }
9103f4f4 1182 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1183 as_bad (_("no such architecture: `%s'"), string);
1184
1185 *input_line_pointer = e;
1186 }
1187 else
1188 as_bad (_("missing cpu architecture"));
1189
fddf5b5b
AM		 1190 no_cond_jump_promotion = 0;
1191 if (*input_line_pointer == ','
29b0f896 1192 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1193 {
1194 char *string = ++input_line_pointer;
1195 int e = get_symbol_end ();
1196
1197 if (strcmp (string, "nojumps") == 0)
1198 no_cond_jump_promotion = 1;
1199 else if (strcmp (string, "jumps") == 0)
1200 ;
1201 else
1202 as_bad (_("no such architecture modifier: `%s'"), string);
1203
1204 *input_line_pointer = e;
1205 }
1206
e413e4e9
AM		 1207 demand_empty_rest_of_line ();
1208}
1209
b9d79e03
JH		 1210unsigned long
1211i386_mach ()
1212{
1213 if (!strcmp (default_arch, "x86_64"))
1214 return bfd_mach_x86_64;
1215 else if (!strcmp (default_arch, "i386"))
1216 return bfd_mach_i386_i386;
1217 else
1218 as_fatal (_("Unknown architecture"));
1219}
b9d79e03 1220\f
252b5132
RH		 1221void
1222md_begin ()
1223{
1224 const char *hash_err;
1225
47926f60 1226 /* Initialize op_hash hash table. */
252b5132
RH		 1227 op_hash = hash_new ();
1228
1229 {
29b0f896
AM		 1230 const template *optab;
1231 templates *core_optab;
252b5132 1232
47926f60
KH		 1233 /* Setup for loop. */
1234 optab = i386_optab;
252b5132
RH		 1235 core_optab = (templates *) xmalloc (sizeof (templates));
1236 core_optab->start = optab;
1237
1238 while (1)
1239 {
1240 ++optab;
1241 if (optab->name == NULL
1242 || strcmp (optab->name, (optab - 1)->name) != 0)
1243 {
1244 /* different name --> ship out current template list;
47926f60 1245 add to hash table; & begin anew. */
252b5132
RH		 1246 core_optab->end = optab;
1247 hash_err = hash_insert (op_hash,
1248 (optab - 1)->name,
1249 (PTR) core_optab);
1250 if (hash_err)
1251 {
252b5132
RH		 1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 (optab - 1)->name,
1254 hash_err);
1255 }
1256 if (optab->name == NULL)
1257 break;
1258 core_optab = (templates *) xmalloc (sizeof (templates));
1259 core_optab->start = optab;
1260 }
1261 }
1262 }
1263
47926f60 1264 /* Initialize reg_hash hash table. */
252b5132
RH		 1265 reg_hash = hash_new ();
1266 {
29b0f896 1267 const reg_entry *regtab;
252b5132
RH		 1268
1269 for (regtab = i386_regtab;
1270 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1271 regtab++)
1272 {
1273 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1274 if (hash_err)
3e73aa7c
JH		 1275 as_fatal (_("Internal Error: Can't hash %s: %s"),
1276 regtab->reg_name,
1277 hash_err);
252b5132
RH		 1278 }
1279 }
1280
47926f60 1281 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1282 {
29b0f896
AM		 1283 int c;
1284 char *p;
252b5132
RH		 1285
1286 for (c = 0; c < 256; c++)
1287 {
3882b010 1288 if (ISDIGIT (c))
252b5132
RH		 1289 {
1290 digit_chars[c] = c;
1291 mnemonic_chars[c] = c;
1292 register_chars[c] = c;
1293 operand_chars[c] = c;
1294 }
3882b010 1295 else if (ISLOWER (c))
252b5132
RH		 1296 {
1297 mnemonic_chars[c] = c;
1298 register_chars[c] = c;
1299 operand_chars[c] = c;
1300 }
3882b010 1301 else if (ISUPPER (c))
252b5132 1302 {
3882b010 1303 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1304 register_chars[c] = mnemonic_chars[c];
1305 operand_chars[c] = c;
1306 }
1307
3882b010 1308 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1309 identifier_chars[c] = c;
1310 else if (c >= 128)
1311 {
1312 identifier_chars[c] = c;
1313 operand_chars[c] = c;
1314 }
1315 }
1316
1317#ifdef LEX_AT
1318 identifier_chars['@'] = '@';
32137342
NC		 1319#endif
1320#ifdef LEX_QM
1321 identifier_chars['?'] = '?';
1322 operand_chars['?'] = '?';
252b5132 1323#endif
252b5132 1324 digit_chars['-'] = '-';
791fe849 1325 mnemonic_chars['-'] = '-';
252b5132
RH		 1326 identifier_chars['_'] = '_';
1327 identifier_chars['.'] = '.';
1328
1329 for (p = operand_special_chars; *p != '\0'; p++)
1330 operand_chars[(unsigned char) *p] = *p;
1331 }
1332
1333#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1334 if (IS_ELF)
252b5132
RH		 1335 {
1336 record_alignment (text_section, 2);
1337 record_alignment (data_section, 2);
1338 record_alignment (bss_section, 2);
1339 }
1340#endif
a4447b93
RH		 1341
1342 if (flag_code == CODE_64BIT)
1343 {
1344 x86_dwarf2_return_column = 16;
1345 x86_cie_data_alignment = -8;
1346 }
1347 else
1348 {
1349 x86_dwarf2_return_column = 8;
1350 x86_cie_data_alignment = -4;
1351 }
252b5132
RH		 1352}
1353
1354void
1355i386_print_statistics (file)
1356 FILE *file;
1357{
1358 hash_print_statistics (file, "i386 opcode", op_hash);
1359 hash_print_statistics (file, "i386 register", reg_hash);
1360}
1361\f
252b5132
RH		 1362#ifdef DEBUG386
1363
ce8a8b2f 1364/* Debugging routines for md_assemble. */
252b5132
RH		 1365static void pi PARAMS ((char *, i386_insn *));
1366static void pte PARAMS ((template *));
1367static void pt PARAMS ((unsigned int));
1368static void pe PARAMS ((expressionS *));
1369static void ps PARAMS ((symbolS *));
1370
1371static void
1372pi (line, x)
1373 char *line;
1374 i386_insn *x;
1375{
09f131f2 1376 unsigned int i;
252b5132
RH		 1377
1378 fprintf (stdout, "%s: template ", line);
1379 pte (&x->tm);
09f131f2
JH		 1380 fprintf (stdout, " address: base %s index %s scale %x\n",
1381 x->base_reg ? x->base_reg->reg_name : "none",
1382 x->index_reg ? x->index_reg->reg_name : "none",
1383 x->log2_scale_factor);
1384 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1385 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1386 fprintf (stdout, " sib: base %x index %x scale %x\n",
1387 x->sib.base, x->sib.index, x->sib.scale);
1388 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1389 (x->rex & REX_MODE64) != 0,
1390 (x->rex & REX_EXTX) != 0,
1391 (x->rex & REX_EXTY) != 0,
1392 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1393 for (i = 0; i < x->operands; i++)
1394 {
1395 fprintf (stdout, " #%d: ", i + 1);
1396 pt (x->types[i]);
1397 fprintf (stdout, "\n");
1398 if (x->types[i]
3f4438ab 1399 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1400 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1401 if (x->types[i] & Imm)
520dc8e8 1402 pe (x->op[i].imms);
252b5132 1403 if (x->types[i] & Disp)
520dc8e8 1404 pe (x->op[i].disps);
252b5132
RH		 1405 }
1406}
1407
1408static void
1409pte (t)
1410 template *t;
1411{
09f131f2 1412 unsigned int i;
252b5132 1413 fprintf (stdout, " %d operands ", t->operands);
47926f60 1414 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1415 if (t->extension_opcode != None)
1416 fprintf (stdout, "ext %x ", t->extension_opcode);
1417 if (t->opcode_modifier & D)
1418 fprintf (stdout, "D");
1419 if (t->opcode_modifier & W)
1420 fprintf (stdout, "W");
1421 fprintf (stdout, "\n");
1422 for (i = 0; i < t->operands; i++)
1423 {
1424 fprintf (stdout, " #%d type ", i + 1);
1425 pt (t->operand_types[i]);
1426 fprintf (stdout, "\n");
1427 }
1428}
1429
1430static void
1431pe (e)
1432 expressionS *e;
1433{
24eab124 1434 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1435 fprintf (stdout, " add_number %ld (%lx)\n",
1436 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1437 if (e->X_add_symbol)
1438 {
1439 fprintf (stdout, " add_symbol ");
1440 ps (e->X_add_symbol);
1441 fprintf (stdout, "\n");
1442 }
1443 if (e->X_op_symbol)
1444 {
1445 fprintf (stdout, " op_symbol ");
1446 ps (e->X_op_symbol);
1447 fprintf (stdout, "\n");
1448 }
1449}
1450
1451static void
1452ps (s)
1453 symbolS *s;
1454{
1455 fprintf (stdout, "%s type %s%s",
1456 S_GET_NAME (s),
1457 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1458 segment_name (S_GET_SEGMENT (s)));
1459}
1460
7b81dfbb 1461static struct type_name
252b5132
RH		 1462 {
1463 unsigned int mask;
1464 char *tname;
1465 }
7b81dfbb 1466const type_names[] =
252b5132
RH		 1467{
1468 { Reg8, "r8" },
1469 { Reg16, "r16" },
1470 { Reg32, "r32" },
09f131f2 1471 { Reg64, "r64" },
252b5132
RH		 1472 { Imm8, "i8" },
1473 { Imm8S, "i8s" },
1474 { Imm16, "i16" },
1475 { Imm32, "i32" },
09f131f2
JH		 1476 { Imm32S, "i32s" },
1477 { Imm64, "i64" },
252b5132
RH		 1478 { Imm1, "i1" },
1479 { BaseIndex, "BaseIndex" },
1480 { Disp8, "d8" },
1481 { Disp16, "d16" },
1482 { Disp32, "d32" },
09f131f2
JH		 1483 { Disp32S, "d32s" },
1484 { Disp64, "d64" },
252b5132
RH		 1485 { InOutPortReg, "InOutPortReg" },
1486 { ShiftCount, "ShiftCount" },
1487 { Control, "control reg" },
1488 { Test, "test reg" },
1489 { Debug, "debug reg" },
1490 { FloatReg, "FReg" },
1491 { FloatAcc, "FAcc" },
1492 { SReg2, "SReg2" },
1493 { SReg3, "SReg3" },
1494 { Acc, "Acc" },
1495 { JumpAbsolute, "Jump Absolute" },
1496 { RegMMX, "rMMX" },
3f4438ab 1497 { RegXMM, "rXMM" },
252b5132
RH		 1498 { EsSeg, "es" },
1499 { 0, "" }
1500};
1501
1502static void
1503pt (t)
1504 unsigned int t;
1505{
29b0f896 1506 const struct type_name *ty;
252b5132 1507
09f131f2
JH		 1508 for (ty = type_names; ty->mask; ty++)
1509 if (t & ty->mask)
1510 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1511 fflush (stdout);
1512}
1513
1514#endif /* DEBUG386 */
1515\f
252b5132 1516static bfd_reloc_code_real_type
3956db08 1517reloc (unsigned int size,
64e74474
AM		 1518 int pcrel,
1519 int sign,
1520 bfd_reloc_code_real_type other)
252b5132 1521{
47926f60 1522 if (other != NO_RELOC)
3956db08
JB		 1523 {
1524 reloc_howto_type *reloc;
1525
1526 if (size == 8)
1527 switch (other)
1528 {
64e74474
AM		 1529 case BFD_RELOC_X86_64_GOT32:
1530 return BFD_RELOC_X86_64_GOT64;
1531 break;
1532 case BFD_RELOC_X86_64_PLTOFF64:
1533 return BFD_RELOC_X86_64_PLTOFF64;
1534 break;
1535 case BFD_RELOC_X86_64_GOTPC32:
1536 other = BFD_RELOC_X86_64_GOTPC64;
1537 break;
1538 case BFD_RELOC_X86_64_GOTPCREL:
1539 other = BFD_RELOC_X86_64_GOTPCREL64;
1540 break;
1541 case BFD_RELOC_X86_64_TPOFF32:
1542 other = BFD_RELOC_X86_64_TPOFF64;
1543 break;
1544 case BFD_RELOC_X86_64_DTPOFF32:
1545 other = BFD_RELOC_X86_64_DTPOFF64;
1546 break;
1547 default:
1548 break;
3956db08 1549 }
e05278af
JB		 1550
1551 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1552 if (size == 4 && flag_code != CODE_64BIT)
1553 sign = -1;
1554
3956db08
JB		 1555 reloc = bfd_reloc_type_lookup (stdoutput, other);
1556 if (!reloc)
1557 as_bad (_("unknown relocation (%u)"), other);
1558 else if (size != bfd_get_reloc_size (reloc))
1559 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1560 bfd_get_reloc_size (reloc),
1561 size);
1562 else if (pcrel && !reloc->pc_relative)
1563 as_bad (_("non-pc-relative relocation for pc-relative field"));
1564 else if ((reloc->complain_on_overflow == complain_overflow_signed
1565 && !sign)
1566 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1567 && sign > 0))
3956db08
JB		 1568 as_bad (_("relocated field and relocation type differ in signedness"));
1569 else
1570 return other;
1571 return NO_RELOC;
1572 }
252b5132
RH		 1573
1574 if (pcrel)
1575 {
3e73aa7c 1576 if (!sign)
3956db08 1577 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1578 switch (size)
1579 {
1580 case 1: return BFD_RELOC_8_PCREL;
1581 case 2: return BFD_RELOC_16_PCREL;
1582 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1583 case 8: return BFD_RELOC_64_PCREL;
252b5132 1584 }
3956db08 1585 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1586 }
1587 else
1588 {
3956db08 1589 if (sign > 0)
e5cb08ac 1590 switch (size)
3e73aa7c
JH		 1591 {
1592 case 4: return BFD_RELOC_X86_64_32S;
1593 }
1594 else
1595 switch (size)
1596 {
1597 case 1: return BFD_RELOC_8;
1598 case 2: return BFD_RELOC_16;
1599 case 4: return BFD_RELOC_32;
1600 case 8: return BFD_RELOC_64;
1601 }
3956db08
JB		 1602 as_bad (_("cannot do %s %u byte relocation"),
1603 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1604 }
1605
bfb32b52 1606 abort ();
252b5132
RH		 1607 return BFD_RELOC_NONE;
1608}
1609
47926f60
KH		 1610/* Here we decide which fixups can be adjusted to make them relative to
1611 the beginning of the section instead of the symbol. Basically we need
1612 to make sure that the dynamic relocations are done correctly, so in
1613 some cases we force the original symbol to be used. */
1614
252b5132 1615int
c0c949c7 1616tc_i386_fix_adjustable (fixP)
31312f95 1617 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1618{
6d249963 1619#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1620 if (!IS_ELF)
31312f95
AM		 1621 return 1;
1622
a161fe53
AM		 1623 /* Don't adjust pc-relative references to merge sections in 64-bit
1624 mode. */
1625 if (use_rela_relocations
1626 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1627 && fixP->fx_pcrel)
252b5132 1628 return 0;
31312f95 1629
8d01d9a9
AJ		 1630 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1631 and changed later by validate_fix. */
1632 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1633 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1634 return 0;
1635
ce8a8b2f 1636 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1637 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1638 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1639 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1640 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1641 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1642 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1643 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1644 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1645 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1646 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1647 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1648 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1649 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1650 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1652 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1653 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1654 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1655 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1656 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1657 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1658 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1659 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1660 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1661 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1662 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1663 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1664 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1665 return 0;
31312f95 1666#endif
252b5132
RH		 1667 return 1;
1668}
252b5132 1669
29b0f896 1670static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1671
1672static int
252b5132 1673intel_float_operand (mnemonic)
29b0f896 1674 const char *mnemonic;
252b5132 1675{
9306ca4a
JB		 1676 /* Note that the value returned is meaningful only for opcodes with (memory)
1677 operands, hence the code here is free to improperly handle opcodes that
1678 have no operands (for better performance and smaller code). */
1679
1680 if (mnemonic[0] != 'f')
1681 return 0; /* non-math */
1682
1683 switch (mnemonic[1])
1684 {
1685 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1686 the fs segment override prefix not currently handled because no
1687 call path can make opcodes without operands get here */
1688 case 'i':
1689 return 2 /* integer op */;
1690 case 'l':
1691 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1692 return 3; /* fldcw/fldenv */
1693 break;
1694 case 'n':
1695 if (mnemonic[2] != 'o' /* fnop */)
1696 return 3; /* non-waiting control op */
1697 break;
1698 case 'r':
1699 if (mnemonic[2] == 's')
1700 return 3; /* frstor/frstpm */
1701 break;
1702 case 's':
1703 if (mnemonic[2] == 'a')
1704 return 3; /* fsave */
1705 if (mnemonic[2] == 't')
1706 {
1707 switch (mnemonic[3])
1708 {
1709 case 'c': /* fstcw */
1710 case 'd': /* fstdw */
1711 case 'e': /* fstenv */
1712 case 's': /* fsts[gw] */
1713 return 3;
1714 }
1715 }
1716 break;
1717 case 'x':
1718 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1719 return 0; /* fxsave/fxrstor are not really math ops */
1720 break;
1721 }
252b5132 1722
9306ca4a 1723 return 1;
252b5132
RH		 1724}
1725
1726/* This is the guts of the machine-dependent assembler. LINE points to a
1727 machine dependent instruction. This function is supposed to emit
1728 the frags/bytes it assembles to. */
1729
1730void
1731md_assemble (line)
1732 char *line;
1733{
252b5132 1734 int j;
252b5132
RH		 1735 char mnemonic[MAX_MNEM_SIZE];
1736
47926f60 1737 /* Initialize globals. */
252b5132
RH		 1738 memset (&i, '\0', sizeof (i));
1739 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1740 i.reloc[j] = NO_RELOC;
252b5132
RH		 1741 memset (disp_expressions, '\0', sizeof (disp_expressions));
1742 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1743 save_stack_p = save_stack;
252b5132
RH		 1744
1745 /* First parse an instruction mnemonic & call i386_operand for the operands.
1746 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1747 start of a (possibly prefixed) mnemonic. */
252b5132 1748
29b0f896
AM		 1749 line = parse_insn (line, mnemonic);
1750 if (line == NULL)
1751 return;
252b5132 1752
29b0f896
AM		 1753 line = parse_operands (line, mnemonic);
1754 if (line == NULL)
1755 return;
252b5132 1756
050dfa73
MM		 1757 /* The order of the immediates should be reversed
1758 for 2 immediates extrq and insertq instructions */
1759 if ((i.imm_operands == 2) &&
1760 ((strcmp (mnemonic, "extrq") == 0)
1761 || (strcmp (mnemonic, "insertq") == 0)))
1762 {
1763 swap_imm_operands ();
1764 /* "extrq" and insertq" are the only two instructions whose operands
1765 have to be reversed even though they have two immediate operands.
1766 */
1767 if (intel_syntax)
1768 swap_operands ();
1769 }
1770
29b0f896
AM		 1771 /* Now we've parsed the mnemonic into a set of templates, and have the
1772 operands at hand. */
1773
1774 /* All intel opcodes have reversed operands except for "bound" and
1775 "enter". We also don't reverse intersegment "jmp" and "call"
1776 instructions with 2 immediate operands so that the immediate segment
050dfa73 1777 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1778 if (intel_syntax && i.operands > 1
1779 && (strcmp (mnemonic, "bound") != 0)
30123838 1780 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1781 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1782 swap_operands ();
1783
1784 if (i.imm_operands)
1785 optimize_imm ();
1786
b300c311
L		 1787 /* Don't optimize displacement for movabs since it only takes 64bit
1788 displacement. */
1789 if (i.disp_operands
1790 && (flag_code != CODE_64BIT
1791 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1792 optimize_disp ();
1793
1794 /* Next, we find a template that matches the given insn,
1795 making sure the overlap of the given operands types is consistent
1796 with the template operand types. */
252b5132 1797
29b0f896
AM		 1798 if (!match_template ())
1799 return;
252b5132 1800
cd61ebfe
AM		 1801 if (intel_syntax)
1802 {
1803 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1804 if (SYSV386_COMPAT
1805 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1806 i.tm.base_opcode ^= FloatR;
1807
1808 /* Zap movzx and movsx suffix. The suffix may have been set from
1809 "word ptr" or "byte ptr" on the source operand, but we'll use
1810 the suffix later to choose the destination register. */
1811 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1812 {
1813 if (i.reg_operands < 2
1814 && !i.suffix
1815 && (~i.tm.opcode_modifier
1816 & (No_bSuf
1817 | No_wSuf
1818 | No_lSuf
1819 | No_sSuf
1820 | No_xSuf
1821 | No_qSuf)))
1822 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1823
1824 i.suffix = 0;
1825 }
cd61ebfe 1826 }
24eab124 1827
29b0f896
AM		 1828 if (i.tm.opcode_modifier & FWait)
1829 if (!add_prefix (FWAIT_OPCODE))
1830 return;
252b5132 1831
29b0f896
AM		 1832 /* Check string instruction segment overrides. */
1833 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1834 {
1835 if (!check_string ())
5dd0794d 1836 return;
29b0f896 1837 }
5dd0794d 1838
29b0f896
AM		 1839 if (!process_suffix ())
1840 return;
e413e4e9 1841
29b0f896
AM		 1842 /* Make still unresolved immediate matches conform to size of immediate
1843 given in i.suffix. */
1844 if (!finalize_imm ())
1845 return;
252b5132 1846
29b0f896
AM		 1847 if (i.types[0] & Imm1)
1848 i.imm_operands = 0; /* kludge for shift insns. */
1849 if (i.types[0] & ImplicitRegister)
1850 i.reg_operands--;
1851 if (i.types[1] & ImplicitRegister)
1852 i.reg_operands--;
1853 if (i.types[2] & ImplicitRegister)
1854 i.reg_operands--;
252b5132 1855
29b0f896
AM		 1856 if (i.tm.opcode_modifier & ImmExt)
1857 {
02fc3089
L		 1858 expressionS *exp;
1859
b7d9ef37 1860 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1861 {
b7d9ef37 1862 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1863 operands with an opcode suffix which is coded in the same
1864 place as an 8-bit immediate field would be. Here we check
1865 those operands and remove them afterwards. */
1866 unsigned int x;
1867
a4622f40 1868 for (x = 0; x < i.operands; x++)
ca164297
L		 1869 if (i.op[x].regs->reg_num != x)
1870 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1871 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1872 i.operands = 0;
1873 }
1874
29b0f896
AM		 1875 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1876 opcode suffix which is coded in the same place as an 8-bit
1877 immediate field would be. Here we fake an 8-bit immediate
1878 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1879
29b0f896 1880 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1881
29b0f896
AM		 1882 exp = &im_expressions[i.imm_operands++];
1883 i.op[i.operands].imms = exp;
1884 i.types[i.operands++] = Imm8;
1885 exp->X_op = O_constant;
1886 exp->X_add_number = i.tm.extension_opcode;
1887 i.tm.extension_opcode = None;
1888 }
252b5132 1889
29b0f896
AM		 1890 /* For insns with operands there are more diddles to do to the opcode. */
1891 if (i.operands)
1892 {
1893 if (!process_operands ())
1894 return;
1895 }
1896 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1897 {
1898 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1899 as_warn (_("translating to `%sp'"), i.tm.name);
1900 }
252b5132 1901
29b0f896
AM		 1902 /* Handle conversion of 'int $3' --> special int3 insn. */
1903 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1904 {
1905 i.tm.base_opcode = INT3_OPCODE;
1906 i.imm_operands = 0;
1907 }
252b5132 1908
29b0f896
AM		 1909 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1910 && i.op[0].disps->X_op == O_constant)
1911 {
1912 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1913 the absolute address given by the constant. Since ix86 jumps and
1914 calls are pc relative, we need to generate a reloc. */
1915 i.op[0].disps->X_add_symbol = &abs_symbol;
1916 i.op[0].disps->X_op = O_symbol;
1917 }
252b5132 1918
29b0f896
AM		 1919 if ((i.tm.opcode_modifier & Rex64) != 0)
1920 i.rex |= REX_MODE64;
252b5132 1921
29b0f896
AM		 1922 /* For 8 bit registers we need an empty rex prefix. Also if the
1923 instruction already has a prefix, we need to convert old
1924 registers to new ones. */
773f551c 1925
29b0f896
AM		 1926 if (((i.types[0] & Reg8) != 0
1927 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1928 || ((i.types[1] & Reg8) != 0
1929 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1930 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1931 && i.rex != 0))
1932 {
1933 int x;
726c5dcd 1934
29b0f896
AM		 1935 i.rex |= REX_OPCODE;
1936 for (x = 0; x < 2; x++)
1937 {
1938 /* Look for 8 bit operand that uses old registers. */
1939 if ((i.types[x] & Reg8) != 0
1940 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1941 {
29b0f896
AM		 1942 /* In case it is "hi" register, give up. */
1943 if (i.op[x].regs->reg_num > 3)
0477af35 1944 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1945 i.op[x].regs->reg_name);
773f551c 1946
29b0f896
AM		 1947 /* Otherwise it is equivalent to the extended register.
1948 Since the encoding doesn't change this is merely
1949 cosmetic cleanup for debug output. */
1950
1951 i.op[x].regs = i.op[x].regs + 8;
773f551c 1952 }
29b0f896
AM		 1953 }
1954 }
773f551c 1955
29b0f896
AM		 1956 if (i.rex != 0)
1957 add_prefix (REX_OPCODE | i.rex);
1958
1959 /* We are ready to output the insn. */
1960 output_insn ();
1961}
1962
1963static char *
1964parse_insn (line, mnemonic)
1965 char *line;
1966 char *mnemonic;
1967{
1968 char *l = line;
1969 char *token_start = l;
1970 char *mnem_p;
5c6af06e
JB		 1971 int supported;
1972 const template *t;
29b0f896
AM		 1973
1974 /* Non-zero if we found a prefix only acceptable with string insns. */
1975 const char *expecting_string_instruction = NULL;
45288df1 1976
29b0f896
AM		 1977 while (1)
1978 {
1979 mnem_p = mnemonic;
1980 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1981 {
1982 mnem_p++;
1983 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1984 {
29b0f896
AM		 1985 as_bad (_("no such instruction: `%s'"), token_start);
1986 return NULL;
1987 }
1988 l++;
1989 }
1990 if (!is_space_char (*l)
1991 && *l != END_OF_INSN
e44823cf
JB		 1992 && (intel_syntax
1993 || (*l != PREFIX_SEPARATOR
1994 && *l != ',')))
29b0f896
AM		 1995 {
1996 as_bad (_("invalid character %s in mnemonic"),
1997 output_invalid (*l));
1998 return NULL;
1999 }
2000 if (token_start == l)
2001 {
e44823cf 2002 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2003 as_bad (_("expecting prefix; got nothing"));
2004 else
2005 as_bad (_("expecting mnemonic; got nothing"));
2006 return NULL;
2007 }
45288df1 2008
29b0f896
AM		 2009 /* Look up instruction (or prefix) via hash table. */
2010 current_templates = hash_find (op_hash, mnemonic);
47926f60 2011
29b0f896
AM		 2012 if (*l != END_OF_INSN
2013 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2014 && current_templates
2015 && (current_templates->start->opcode_modifier & IsPrefix))
2016 {
2dd88dca
JB		 2017 if (current_templates->start->cpu_flags
2018 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2019 {
2020 as_bad ((flag_code != CODE_64BIT
2021 ? _("`%s' is only supported in 64-bit mode")
2022 : _("`%s' is not supported in 64-bit mode")),
2023 current_templates->start->name);
2024 return NULL;
2025 }
29b0f896
AM		 2026 /* If we are in 16-bit mode, do not allow addr16 or data16.
2027 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2028 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2029 && flag_code != CODE_64BIT
2030 && (((current_templates->start->opcode_modifier & Size32) != 0)
2031 ^ (flag_code == CODE_16BIT)))
2032 {
2033 as_bad (_("redundant %s prefix"),
2034 current_templates->start->name);
2035 return NULL;
45288df1 2036 }
29b0f896
AM		 2037 /* Add prefix, checking for repeated prefixes. */
2038 switch (add_prefix (current_templates->start->base_opcode))
2039 {
2040 case 0:
2041 return NULL;
2042 case 2:
2043 expecting_string_instruction = current_templates->start->name;
2044 break;
2045 }
2046 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2047 token_start = ++l;
2048 }
2049 else
2050 break;
2051 }
45288df1 2052
29b0f896
AM		 2053 if (!current_templates)
2054 {
2055 /* See if we can get a match by trimming off a suffix. */
2056 switch (mnem_p[-1])
2057 {
2058 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2059 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2060 i.suffix = SHORT_MNEM_SUFFIX;
2061 else
29b0f896
AM		 2062 case BYTE_MNEM_SUFFIX:
2063 case QWORD_MNEM_SUFFIX:
2064 i.suffix = mnem_p[-1];
2065 mnem_p[-1] = '\0';
2066 current_templates = hash_find (op_hash, mnemonic);
2067 break;
2068 case SHORT_MNEM_SUFFIX:
2069 case LONG_MNEM_SUFFIX:
2070 if (!intel_syntax)
2071 {
2072 i.suffix = mnem_p[-1];
2073 mnem_p[-1] = '\0';
2074 current_templates = hash_find (op_hash, mnemonic);
2075 }
2076 break;
252b5132 2077
29b0f896
AM		 2078 /* Intel Syntax. */
2079 case 'd':
2080 if (intel_syntax)
2081 {
9306ca4a 2082 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2083 i.suffix = SHORT_MNEM_SUFFIX;
2084 else
2085 i.suffix = LONG_MNEM_SUFFIX;
2086 mnem_p[-1] = '\0';
2087 current_templates = hash_find (op_hash, mnemonic);
2088 }
2089 break;
2090 }
2091 if (!current_templates)
2092 {
2093 as_bad (_("no such instruction: `%s'"), token_start);
2094 return NULL;
2095 }
2096 }
252b5132 2097
29b0f896
AM		 2098 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2099 {
2100 /* Check for a branch hint. We allow ",pt" and ",pn" for
2101 predict taken and predict not taken respectively.
2102 I'm not sure that branch hints actually do anything on loop
2103 and jcxz insns (JumpByte) for current Pentium4 chips. They
2104 may work in the future and it doesn't hurt to accept them
2105 now. */
2106 if (l[0] == ',' && l[1] == 'p')
2107 {
2108 if (l[2] == 't')
2109 {
2110 if (!add_prefix (DS_PREFIX_OPCODE))
2111 return NULL;
2112 l += 3;
2113 }
2114 else if (l[2] == 'n')
2115 {
2116 if (!add_prefix (CS_PREFIX_OPCODE))
2117 return NULL;
2118 l += 3;
2119 }
2120 }
2121 }
2122 /* Any other comma loses. */
2123 if (*l == ',')
2124 {
2125 as_bad (_("invalid character %s in mnemonic"),
2126 output_invalid (*l));
2127 return NULL;
2128 }
252b5132 2129
29b0f896 2130 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2131 supported = 0;
2132 for (t = current_templates->start; t < current_templates->end; ++t)
2133 {
2134 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2135 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2136 supported |= 1;
5c6af06e 2137 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2138 supported |= 2;
5c6af06e
JB		 2139 }
2140 if (!(supported & 2))
2141 {
2142 as_bad (flag_code == CODE_64BIT
2143 ? _("`%s' is not supported in 64-bit mode")
2144 : _("`%s' is only supported in 64-bit mode"),
2145 current_templates->start->name);
2146 return NULL;
2147 }
2148 if (!(supported & 1))
29b0f896 2149 {
5c6af06e
JB		 2150 as_warn (_("`%s' is not supported on `%s%s'"),
2151 current_templates->start->name,
2152 cpu_arch_name,
2153 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2154 }
2155 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2156 {
2157 as_warn (_("use .code16 to ensure correct addressing mode"));
2158 }
252b5132 2159
29b0f896 2160 /* Check for rep/repne without a string instruction. */
f41bbced 2161 if (expecting_string_instruction)
29b0f896 2162 {
f41bbced
JB		 2163 static templates override;
2164
2165 for (t = current_templates->start; t < current_templates->end; ++t)
2166 if (t->opcode_modifier & IsString)
2167 break;
2168 if (t >= current_templates->end)
2169 {
2170 as_bad (_("expecting string instruction after `%s'"),
64e74474 2171 expecting_string_instruction);
f41bbced
JB		 2172 return NULL;
2173 }
2174 for (override.start = t; t < current_templates->end; ++t)
2175 if (!(t->opcode_modifier & IsString))
2176 break;
2177 override.end = t;
2178 current_templates = &override;
29b0f896 2179 }
252b5132 2180
29b0f896
AM		 2181 return l;
2182}
252b5132 2183
29b0f896
AM		 2184static char *
2185parse_operands (l, mnemonic)
2186 char *l;
2187 const char *mnemonic;
2188{
2189 char *token_start;
3138f287 2190
29b0f896
AM		 2191 /* 1 if operand is pending after ','. */
2192 unsigned int expecting_operand = 0;
252b5132 2193
29b0f896
AM		 2194 /* Non-zero if operand parens not balanced. */
2195 unsigned int paren_not_balanced;
2196
2197 while (*l != END_OF_INSN)
2198 {
2199 /* Skip optional white space before operand. */
2200 if (is_space_char (*l))
2201 ++l;
2202 if (!is_operand_char (*l) && *l != END_OF_INSN)
2203 {
2204 as_bad (_("invalid character %s before operand %d"),
2205 output_invalid (*l),
2206 i.operands + 1);
2207 return NULL;
2208 }
2209 token_start = l; /* after white space */
2210 paren_not_balanced = 0;
2211 while (paren_not_balanced || *l != ',')
2212 {
2213 if (*l == END_OF_INSN)
2214 {
2215 if (paren_not_balanced)
2216 {
2217 if (!intel_syntax)
2218 as_bad (_("unbalanced parenthesis in operand %d."),
2219 i.operands + 1);
2220 else
2221 as_bad (_("unbalanced brackets in operand %d."),
2222 i.operands + 1);
2223 return NULL;
2224 }
2225 else
2226 break; /* we are done */
2227 }
2228 else if (!is_operand_char (*l) && !is_space_char (*l))
2229 {
2230 as_bad (_("invalid character %s in operand %d"),
2231 output_invalid (*l),
2232 i.operands + 1);
2233 return NULL;
2234 }
2235 if (!intel_syntax)
2236 {
2237 if (*l == '(')
2238 ++paren_not_balanced;
2239 if (*l == ')')
2240 --paren_not_balanced;
2241 }
2242 else
2243 {
2244 if (*l == '[')
2245 ++paren_not_balanced;
2246 if (*l == ']')
2247 --paren_not_balanced;
2248 }
2249 l++;
2250 }
2251 if (l != token_start)
2252 { /* Yes, we've read in another operand. */
2253 unsigned int operand_ok;
2254 this_operand = i.operands++;
2255 if (i.operands > MAX_OPERANDS)
2256 {
2257 as_bad (_("spurious operands; (%d operands/instruction max)"),
2258 MAX_OPERANDS);
2259 return NULL;
2260 }
2261 /* Now parse operand adding info to 'i' as we go along. */
2262 END_STRING_AND_SAVE (l);
2263
2264 if (intel_syntax)
2265 operand_ok =
2266 i386_intel_operand (token_start,
2267 intel_float_operand (mnemonic));
2268 else
2269 operand_ok = i386_operand (token_start);
2270
2271 RESTORE_END_STRING (l);
2272 if (!operand_ok)
2273 return NULL;
2274 }
2275 else
2276 {
2277 if (expecting_operand)
2278 {
2279 expecting_operand_after_comma:
2280 as_bad (_("expecting operand after ','; got nothing"));
2281 return NULL;
2282 }
2283 if (*l == ',')
2284 {
2285 as_bad (_("expecting operand before ','; got nothing"));
2286 return NULL;
2287 }
2288 }
7f3f1ea2 2289
29b0f896
AM		 2290 /* Now *l must be either ',' or END_OF_INSN. */
2291 if (*l == ',')
2292 {
2293 if (*++l == END_OF_INSN)
2294 {
2295 /* Just skip it, if it's \n complain. */
2296 goto expecting_operand_after_comma;
2297 }
2298 expecting_operand = 1;
2299 }
2300 }
2301 return l;
2302}
7f3f1ea2 2303
050dfa73
MM		 2304static void
2305swap_imm_operands ()
2306{
2307 union i386_op temp_op;
2308 unsigned int temp_type;
2309 enum bfd_reloc_code_real temp_reloc;
2310 int xchg1 = 0;
2311 int xchg2 = 1;
2312
2313 temp_type = i.types[xchg2];
2314 i.types[xchg2] = i.types[xchg1];
2315 i.types[xchg1] = temp_type;
2316 temp_op = i.op[xchg2];
2317 i.op[xchg2] = i.op[xchg1];
2318 i.op[xchg1] = temp_op;
2319 temp_reloc = i.reloc[xchg2];
2320 i.reloc[xchg2] = i.reloc[xchg1];
2321 i.reloc[xchg1] = temp_reloc;
2322}
2323
2324
29b0f896
AM		 2325static void
2326swap_operands ()
2327{
2328 union i386_op temp_op;
2329 unsigned int temp_type;
f86103b7 2330 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2331 int xchg1 = 0;
2332 int xchg2 = 0;
252b5132 2333
050dfa73
MM		 2334 if (i.operands == 4)
2335 /* There will be two exchanges in a 4 operand instruction.
2336 First exchange is the done inside this block.(1st and 4rth operand)
2337 The next exchange is done outside this block.(2nd and 3rd operand) */
2338 {
2339 xchg1 = 0;
2340 xchg2 = 3;
2341 temp_type = i.types[xchg2];
2342 i.types[xchg2] = i.types[xchg1];
2343 i.types[xchg1] = temp_type;
2344 temp_op = i.op[xchg2];
2345 i.op[xchg2] = i.op[xchg1];
2346 i.op[xchg1] = temp_op;
2347 temp_reloc = i.reloc[xchg2];
2348 i.reloc[xchg2] = i.reloc[xchg1];
2349 i.reloc[xchg1] = temp_reloc;
2350 xchg1 = 1;
2351 xchg2 = 2;
2352 }
2353
29b0f896
AM		 2354 if (i.operands == 2)
2355 {
2356 xchg1 = 0;
2357 xchg2 = 1;
2358 }
2359 else if (i.operands == 3)
2360 {
2361 xchg1 = 0;
2362 xchg2 = 2;
2363 }
2364 temp_type = i.types[xchg2];
2365 i.types[xchg2] = i.types[xchg1];
2366 i.types[xchg1] = temp_type;
2367 temp_op = i.op[xchg2];
2368 i.op[xchg2] = i.op[xchg1];
2369 i.op[xchg1] = temp_op;
2370 temp_reloc = i.reloc[xchg2];
2371 i.reloc[xchg2] = i.reloc[xchg1];
2372 i.reloc[xchg1] = temp_reloc;
2373
2374 if (i.mem_operands == 2)
2375 {
2376 const seg_entry *temp_seg;
2377 temp_seg = i.seg[0];
2378 i.seg[0] = i.seg[1];
2379 i.seg[1] = temp_seg;
2380 }
2381}
252b5132 2382
29b0f896
AM		 2383/* Try to ensure constant immediates are represented in the smallest
2384 opcode possible. */
2385static void
2386optimize_imm ()
2387{
2388 char guess_suffix = 0;
2389 int op;
252b5132 2390
29b0f896
AM		 2391 if (i.suffix)
2392 guess_suffix = i.suffix;
2393 else if (i.reg_operands)
2394 {
2395 /* Figure out a suffix from the last register operand specified.
2396 We can't do this properly yet, ie. excluding InOutPortReg,
2397 but the following works for instructions with immediates.
2398 In any case, we can't set i.suffix yet. */
2399 for (op = i.operands; --op >= 0;)
2400 if (i.types[op] & Reg)
252b5132 2401 {
29b0f896
AM		 2402 if (i.types[op] & Reg8)
2403 guess_suffix = BYTE_MNEM_SUFFIX;
2404 else if (i.types[op] & Reg16)
2405 guess_suffix = WORD_MNEM_SUFFIX;
2406 else if (i.types[op] & Reg32)
2407 guess_suffix = LONG_MNEM_SUFFIX;
2408 else if (i.types[op] & Reg64)
2409 guess_suffix = QWORD_MNEM_SUFFIX;
2410 break;
252b5132 2411 }
29b0f896
AM		 2412 }
2413 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2414 guess_suffix = WORD_MNEM_SUFFIX;
2415
2416 for (op = i.operands; --op >= 0;)
2417 if (i.types[op] & Imm)
2418 {
2419 switch (i.op[op].imms->X_op)
252b5132 2420 {
29b0f896
AM		 2421 case O_constant:
2422 /* If a suffix is given, this operand may be shortened. */
2423 switch (guess_suffix)
252b5132 2424 {
29b0f896
AM		 2425 case LONG_MNEM_SUFFIX:
2426 i.types[op] |= Imm32 | Imm64;
2427 break;
2428 case WORD_MNEM_SUFFIX:
2429 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2430 break;
2431 case BYTE_MNEM_SUFFIX:
2432 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2433 break;
252b5132 2434 }
252b5132 2435
29b0f896
AM		 2436 /* If this operand is at most 16 bits, convert it
2437 to a signed 16 bit number before trying to see
2438 whether it will fit in an even smaller size.
2439 This allows a 16-bit operand such as $0xffe0 to
2440 be recognised as within Imm8S range. */
2441 if ((i.types[op] & Imm16)
2442 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2443 {
29b0f896
AM		 2444 i.op[op].imms->X_add_number =
2445 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2446 }
2447 if ((i.types[op] & Imm32)
2448 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2449 == 0))
2450 {
2451 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2452 ^ ((offsetT) 1 << 31))
2453 - ((offsetT) 1 << 31));
2454 }
2455 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2456
29b0f896
AM		 2457 /* We must avoid matching of Imm32 templates when 64bit
2458 only immediate is available. */
2459 if (guess_suffix == QWORD_MNEM_SUFFIX)
2460 i.types[op] &= ~Imm32;
2461 break;
252b5132 2462
29b0f896
AM		 2463 case O_absent:
2464 case O_register:
2465 abort ();
2466
2467 /* Symbols and expressions. */
2468 default:
9cd96992
JB		 2469 /* Convert symbolic operand to proper sizes for matching, but don't
2470 prevent matching a set of insns that only supports sizes other
2471 than those matching the insn suffix. */
2472 {
2473 unsigned int mask, allowed = 0;
2474 const template *t;
2475
2476 for (t = current_templates->start; t < current_templates->end; ++t)
2477 allowed |= t->operand_types[op];
2478 switch (guess_suffix)
2479 {
2480 case QWORD_MNEM_SUFFIX:
2481 mask = Imm64 | Imm32S;
2482 break;
2483 case LONG_MNEM_SUFFIX:
2484 mask = Imm32;
2485 break;
2486 case WORD_MNEM_SUFFIX:
2487 mask = Imm16;
2488 break;
2489 case BYTE_MNEM_SUFFIX:
2490 mask = Imm8;
2491 break;
2492 default:
2493 mask = 0;
2494 break;
2495 }
64e74474
AM		 2496 if (mask & allowed)
2497 i.types[op] &= mask;
9cd96992 2498 }
29b0f896 2499 break;
252b5132 2500 }
29b0f896
AM		 2501 }
2502}
47926f60 2503
29b0f896
AM		 2504/* Try to use the smallest displacement type too. */
2505static void
2506optimize_disp ()
2507{
2508 int op;
3e73aa7c 2509
29b0f896 2510 for (op = i.operands; --op >= 0;)
b300c311 2511 if (i.types[op] & Disp)
252b5132 2512 {
b300c311 2513 if (i.op[op].disps->X_op == O_constant)
252b5132 2514 {
b300c311 2515 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2516
b300c311
L		 2517 if ((i.types[op] & Disp16)
2518 && (disp & ~(offsetT) 0xffff) == 0)
2519 {
2520 /* If this operand is at most 16 bits, convert
2521 to a signed 16 bit number and don't use 64bit
2522 displacement. */
2523 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2524 i.types[op] &= ~Disp64;
2525 }
2526 if ((i.types[op] & Disp32)
2527 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2528 {
2529 /* If this operand is at most 32 bits, convert
2530 to a signed 32 bit number and don't use 64bit
2531 displacement. */
2532 disp &= (((offsetT) 2 << 31) - 1);
2533 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2534 i.types[op] &= ~Disp64;
2535 }
2536 if (!disp && (i.types[op] & BaseIndex))
2537 {
2538 i.types[op] &= ~Disp;
2539 i.op[op].disps = 0;
2540 i.disp_operands--;
2541 }
2542 else if (flag_code == CODE_64BIT)
2543 {
2544 if (fits_in_signed_long (disp))
28a9d8f5
L		 2545 {
2546 i.types[op] &= ~Disp64;
2547 i.types[op] |= Disp32S;
2548 }
b300c311
L		 2549 if (fits_in_unsigned_long (disp))
2550 i.types[op] |= Disp32;
2551 }
2552 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2553 && fits_in_signed_byte (disp))
2554 i.types[op] |= Disp8;
252b5132 2555 }
67a4f2b7
AO		 2556 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2557 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2558 {
2559 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2560 i.op[op].disps, 0, i.reloc[op]);
2561 i.types[op] &= ~Disp;
2562 }
2563 else
b300c311
L		 2564 /* We only support 64bit displacement on constants. */
2565 i.types[op] &= ~Disp64;
252b5132 2566 }
29b0f896
AM		 2567}
2568
2569static int
2570match_template ()
2571{
2572 /* Points to template once we've found it. */
2573 const template *t;
f48ff2ae 2574 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2575 unsigned int found_reverse_match;
2576 int suffix_check;
f48ff2ae 2577 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2578 int addr_prefix_disp;
a5c311ca 2579 unsigned int j;
29b0f896 2580
f48ff2ae
L		 2581#if MAX_OPERANDS != 4
2582# error "MAX_OPERANDS must be 4."
2583#endif
2584
29b0f896
AM		 2585#define MATCH(overlap, given, template) \
2586 ((overlap & ~JumpAbsolute) \
2587 && (((given) & (BaseIndex | JumpAbsolute)) \
2588 == ((overlap) & (BaseIndex | JumpAbsolute))))
2589
2590 /* If given types r0 and r1 are registers they must be of the same type
2591 unless the expected operand type register overlap is null.
2592 Note that Acc in a template matches every size of reg. */
2593#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2594 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2595 || ((g0) & Reg) == ((g1) & Reg) \
2596 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2597
2598 overlap0 = 0;
2599 overlap1 = 0;
2600 overlap2 = 0;
f48ff2ae 2601 overlap3 = 0;
29b0f896 2602 found_reverse_match = 0;
a5c311ca
L		 2603 for (j = 0; j < MAX_OPERANDS; j++)
2604 operand_types [j] = 0;
539e75ad 2605 addr_prefix_disp = -1;
29b0f896
AM		 2606 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2607 ? No_bSuf
2608 : (i.suffix == WORD_MNEM_SUFFIX
2609 ? No_wSuf
2610 : (i.suffix == SHORT_MNEM_SUFFIX
2611 ? No_sSuf
2612 : (i.suffix == LONG_MNEM_SUFFIX
2613 ? No_lSuf
2614 : (i.suffix == QWORD_MNEM_SUFFIX
2615 ? No_qSuf
2616 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2617 ? No_xSuf : 0))))));
2618
45aa61fe 2619 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2620 {
539e75ad
L		 2621 addr_prefix_disp = -1;
2622
29b0f896
AM		 2623 /* Must have right number of operands. */
2624 if (i.operands != t->operands)
2625 continue;
2626
2627 /* Check the suffix, except for some instructions in intel mode. */
2628 if ((t->opcode_modifier & suffix_check)
2629 && !(intel_syntax
9306ca4a 2630 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2631 continue;
2632
a5c311ca
L		 2633 for (j = 0; j < MAX_OPERANDS; j++)
2634 operand_types [j] = t->operand_types [j];
539e75ad 2635
45aa61fe
AM		 2636 /* In general, don't allow 64-bit operands in 32-bit mode. */
2637 if (i.suffix == QWORD_MNEM_SUFFIX
2638 && flag_code != CODE_64BIT
2639 && (intel_syntax
2640 ? (!(t->opcode_modifier & IgnoreSize)
2641 && !intel_float_operand (t->name))
2642 : intel_float_operand (t->name) != 2)
539e75ad
L		 2643 && (!(operand_types[0] & (RegMMX | RegXMM))
2644 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2645 && (t->base_opcode != 0x0fc7
2646 || t->extension_opcode != 1 /* cmpxchg8b */))
2647 continue;
2648
29b0f896
AM		 2649 /* Do not verify operands when there are none. */
2650 else if (!t->operands)
2651 {
2652 if (t->cpu_flags & ~cpu_arch_flags)
2653 continue;
2654 /* We've found a match; break out of loop. */
2655 break;
2656 }
252b5132 2657
539e75ad
L		 2658 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2659 into Disp32/Disp16/Disp32 operand. */
2660 if (i.prefix[ADDR_PREFIX] != 0)
2661 {
a5c311ca 2662 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2663
2664 switch (flag_code)
2665 {
2666 case CODE_16BIT:
2667 DispOn = Disp32;
2668 DispOff = Disp16;
2669 break;
2670 case CODE_32BIT:
2671 DispOn = Disp16;
2672 DispOff = Disp32;
2673 break;
2674 case CODE_64BIT:
2675 DispOn = Disp32;
2676 DispOff = Disp64;
2677 break;
2678 }
2679
f48ff2ae 2680 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2681 {
2682 /* There should be only one Disp operand. */
2683 if ((operand_types[j] & DispOff))
2684 {
2685 addr_prefix_disp = j;
2686 operand_types[j] |= DispOn;
2687 operand_types[j] &= ~DispOff;
2688 break;
2689 }
2690 }
2691 }
2692
2693 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2694 switch (t->operands)
2695 {
2696 case 1:
539e75ad 2697 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2698 continue;
2699 break;
2700 case 2:
2701 case 3:
f48ff2ae 2702 case 4:
539e75ad
L		 2703 overlap1 = i.types[1] & operand_types[1];
2704 if (!MATCH (overlap0, i.types[0], operand_types[0])
2705 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2706 /* monitor in SSE3 is a very special case. The first
708587a4 2707 register and the second register may have different
cb712a9e
L		 2708 sizes. */
2709 || !((t->base_opcode == 0x0f01
2710 && t->extension_opcode == 0xc8)
2711 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2712 operand_types[0],
cb712a9e 2713 overlap1, i.types[1],
539e75ad 2714 operand_types[1])))
29b0f896
AM		 2715 {
2716 /* Check if other direction is valid ... */
2717 if ((t->opcode_modifier & (D | FloatD)) == 0)
2718 continue;
2719
2720 /* Try reversing direction of operands. */
539e75ad
L		 2721 overlap0 = i.types[0] & operand_types[1];
2722 overlap1 = i.types[1] & operand_types[0];
2723 if (!MATCH (overlap0, i.types[0], operand_types[1])
2724 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2725 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2726 operand_types[1],
29b0f896 2727 overlap1, i.types[1],
539e75ad 2728 operand_types[0]))
29b0f896
AM		 2729 {
2730 /* Does not match either direction. */
2731 continue;
2732 }
2733 /* found_reverse_match holds which of D or FloatDR
2734 we've found. */
2735 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2736 }
f48ff2ae 2737 else
29b0f896 2738 {
f48ff2ae 2739 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2740 switch (t->operands)
2741 {
2742 case 4:
2743 overlap3 = i.types[3] & operand_types[3];
2744 case 3:
2745 overlap2 = i.types[2] & operand_types[2];
2746 break;
2747 }
29b0f896 2748
f48ff2ae
L		 2749 switch (t->operands)
2750 {
2751 case 4:
2752 if (!MATCH (overlap3, i.types[3], operand_types[3])
2753 || !CONSISTENT_REGISTER_MATCH (overlap2,
2754 i.types[2],
2755 operand_types[2],
2756 overlap3,
2757 i.types[3],
2758 operand_types[3]))
2759 continue;
2760 case 3:
2761 /* Here we make use of the fact that there are no
2762 reverse match 3 operand instructions, and all 3
2763 operand instructions only need to be checked for
2764 register consistency between operands 2 and 3. */
2765 if (!MATCH (overlap2, i.types[2], operand_types[2])
2766 || !CONSISTENT_REGISTER_MATCH (overlap1,
2767 i.types[1],
2768 operand_types[1],
2769 overlap2,
2770 i.types[2],
2771 operand_types[2]))
2772 continue;
2773 break;
2774 }
29b0f896 2775 }
f48ff2ae 2776 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2777 slip through to break. */
2778 }
2779 if (t->cpu_flags & ~cpu_arch_flags)
2780 {
2781 found_reverse_match = 0;
2782 continue;
2783 }
2784 /* We've found a match; break out of loop. */
2785 break;
2786 }
2787
2788 if (t == current_templates->end)
2789 {
2790 /* We found no match. */
2791 as_bad (_("suffix or operands invalid for `%s'"),
2792 current_templates->start->name);
2793 return 0;
2794 }
252b5132 2795
29b0f896
AM		 2796 if (!quiet_warnings)
2797 {
2798 if (!intel_syntax
2799 && ((i.types[0] & JumpAbsolute)
539e75ad 2800 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2801 {
2802 as_warn (_("indirect %s without `*'"), t->name);
2803 }
2804
2805 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2806 == (IsPrefix | IgnoreSize))
2807 {
2808 /* Warn them that a data or address size prefix doesn't
2809 affect assembly of the next line of code. */
2810 as_warn (_("stand-alone `%s' prefix"), t->name);
2811 }
2812 }
2813
2814 /* Copy the template we found. */
2815 i.tm = *t;
539e75ad
L		 2816
2817 if (addr_prefix_disp != -1)
2818 i.tm.operand_types[addr_prefix_disp]
2819 = operand_types[addr_prefix_disp];
2820
29b0f896
AM		 2821 if (found_reverse_match)
2822 {
2823 /* If we found a reverse match we must alter the opcode
2824 direction bit. found_reverse_match holds bits to change
2825 (different for int & float insns). */
2826
2827 i.tm.base_opcode ^= found_reverse_match;
2828
539e75ad
L		 2829 i.tm.operand_types[0] = operand_types[1];
2830 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2831 }
2832
2833 return 1;
2834}
2835
2836static int
2837check_string ()
2838{
2839 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2840 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2841 {
2842 if (i.seg[0] != NULL && i.seg[0] != &es)
2843 {
2844 as_bad (_("`%s' operand %d must use `%%es' segment"),
2845 i.tm.name,
2846 mem_op + 1);
2847 return 0;
2848 }
2849 /* There's only ever one segment override allowed per instruction.
2850 This instruction possibly has a legal segment override on the
2851 second operand, so copy the segment to where non-string
2852 instructions store it, allowing common code. */
2853 i.seg[0] = i.seg[1];
2854 }
2855 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2856 {
2857 if (i.seg[1] != NULL && i.seg[1] != &es)
2858 {
2859 as_bad (_("`%s' operand %d must use `%%es' segment"),
2860 i.tm.name,
2861 mem_op + 2);
2862 return 0;
2863 }
2864 }
2865 return 1;
2866}
2867
2868static int
543613e9 2869process_suffix (void)
29b0f896
AM		 2870{
2871 /* If matched instruction specifies an explicit instruction mnemonic
2872 suffix, use it. */
2873 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2874 {
2875 if (i.tm.opcode_modifier & Size16)
2876 i.suffix = WORD_MNEM_SUFFIX;
2877 else if (i.tm.opcode_modifier & Size64)
2878 i.suffix = QWORD_MNEM_SUFFIX;
2879 else
2880 i.suffix = LONG_MNEM_SUFFIX;
2881 }
2882 else if (i.reg_operands)
2883 {
2884 /* If there's no instruction mnemonic suffix we try to invent one
2885 based on register operands. */
2886 if (!i.suffix)
2887 {
2888 /* We take i.suffix from the last register operand specified,
2889 Destination register type is more significant than source
2890 register type. */
2891 int op;
543613e9 2892
29b0f896
AM		 2893 for (op = i.operands; --op >= 0;)
2894 if ((i.types[op] & Reg)
2895 && !(i.tm.operand_types[op] & InOutPortReg))
2896 {
2897 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2898 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2899 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2900 LONG_MNEM_SUFFIX);
2901 break;
2902 }
2903 }
2904 else if (i.suffix == BYTE_MNEM_SUFFIX)
2905 {
2906 if (!check_byte_reg ())
2907 return 0;
2908 }
2909 else if (i.suffix == LONG_MNEM_SUFFIX)
2910 {
2911 if (!check_long_reg ())
2912 return 0;
2913 }
2914 else if (i.suffix == QWORD_MNEM_SUFFIX)
2915 {
2916 if (!check_qword_reg ())
2917 return 0;
2918 }
2919 else if (i.suffix == WORD_MNEM_SUFFIX)
2920 {
2921 if (!check_word_reg ())
2922 return 0;
2923 }
2924 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2925 /* Do nothing if the instruction is going to ignore the prefix. */
2926 ;
2927 else
2928 abort ();
2929 }
9306ca4a
JB		 2930 else if ((i.tm.opcode_modifier & DefaultSize)
2931 && !i.suffix
2932 /* exclude fldenv/frstor/fsave/fstenv */
2933 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2934 {
2935 i.suffix = stackop_size;
2936 }
9306ca4a
JB		 2937 else if (intel_syntax
2938 && !i.suffix
2939 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2940 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2941 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2942 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2943 {
2944 switch (flag_code)
2945 {
2946 case CODE_64BIT:
2947 if (!(i.tm.opcode_modifier & No_qSuf))
2948 {
2949 i.suffix = QWORD_MNEM_SUFFIX;
2950 break;
2951 }
2952 case CODE_32BIT:
2953 if (!(i.tm.opcode_modifier & No_lSuf))
2954 i.suffix = LONG_MNEM_SUFFIX;
2955 break;
2956 case CODE_16BIT:
2957 if (!(i.tm.opcode_modifier & No_wSuf))
2958 i.suffix = WORD_MNEM_SUFFIX;
2959 break;
2960 }
2961 }
252b5132 2962
9306ca4a 2963 if (!i.suffix)
29b0f896 2964 {
9306ca4a
JB		 2965 if (!intel_syntax)
2966 {
2967 if (i.tm.opcode_modifier & W)
2968 {
2969 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2970 return 0;
2971 }
2972 }
2973 else
2974 {
64e74474
AM		 2975 unsigned int suffixes = (~i.tm.opcode_modifier
2976 & (No_bSuf
2977 | No_wSuf
2978 | No_lSuf
2979 | No_sSuf
2980 | No_xSuf
2981 | No_qSuf));
9306ca4a
JB		 2982
2983 if ((i.tm.opcode_modifier & W)
2984 || ((suffixes & (suffixes - 1))
2985 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2986 {
2987 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2988 return 0;
2989 }
2990 }
29b0f896 2991 }
252b5132 2992
9306ca4a
JB		 2993 /* Change the opcode based on the operand size given by i.suffix;
2994 We don't need to change things for byte insns. */
2995
29b0f896
AM		 2996 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2997 {
2998 /* It's not a byte, select word/dword operation. */
2999 if (i.tm.opcode_modifier & W)
3000 {
3001 if (i.tm.opcode_modifier & ShortForm)
3002 i.tm.base_opcode |= 8;
3003 else
3004 i.tm.base_opcode |= 1;
3005 }
0f3f3d8b 3006
29b0f896
AM		 3007 /* Now select between word & dword operations via the operand
3008 size prefix, except for instructions that will ignore this
3009 prefix anyway. */
cb712a9e
L		 3010 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
3011 {
3012 /* monitor in SSE3 is a very special case. The default size
3013 of AX is the size of mode. The address size override
3014 prefix will change the size of AX. */
3015 if (i.op->regs[0].reg_type &
3016 (flag_code == CODE_32BIT ? Reg16 : Reg32))
3017 if (!add_prefix (ADDR_PREFIX_OPCODE))
3018 return 0;
3019 }
3020 else if (i.suffix != QWORD_MNEM_SUFFIX
3021 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3022 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
3023 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3024 || (flag_code == CODE_64BIT
3025 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 3026 {
3027 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3028
29b0f896
AM		 3029 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
3030 prefix = ADDR_PREFIX_OPCODE;
252b5132 3031
29b0f896
AM		 3032 if (!add_prefix (prefix))
3033 return 0;
24eab124 3034 }
252b5132 3035
29b0f896
AM		 3036 /* Set mode64 for an operand. */
3037 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3038 && flag_code == CODE_64BIT
29b0f896 3039 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3040 {
3041 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3042 need rex64. */
3043 if (i.operands != 2
3044 || i.types [0] != (Acc | Reg64)
3045 || i.types [1] != (Acc | Reg64)
3046 || strcmp (i.tm.name, "xchg") != 0)
3047 i.rex |= REX_MODE64;
3048 }
3e73aa7c 3049
29b0f896
AM		 3050 /* Size floating point instruction. */
3051 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3052 if (i.tm.opcode_modifier & FloatMF)
3053 i.tm.base_opcode ^= 4;
29b0f896 3054 }
7ecd2f8b 3055
29b0f896
AM		 3056 return 1;
3057}
3e73aa7c 3058
29b0f896 3059static int
543613e9 3060check_byte_reg (void)
29b0f896
AM		 3061{
3062 int op;
543613e9 3063
29b0f896
AM		 3064 for (op = i.operands; --op >= 0;)
3065 {
3066 /* If this is an eight bit register, it's OK. If it's the 16 or
3067 32 bit version of an eight bit register, we will just use the
3068 low portion, and that's OK too. */
3069 if (i.types[op] & Reg8)
3070 continue;
3071
3072 /* movzx and movsx should not generate this warning. */
3073 if (intel_syntax
3074 && (i.tm.base_opcode == 0xfb7
3075 || i.tm.base_opcode == 0xfb6
3076 || i.tm.base_opcode == 0x63
3077 || i.tm.base_opcode == 0xfbe
3078 || i.tm.base_opcode == 0xfbf))
3079 continue;
3080
65ec77d2 3081 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3082 {
3083 /* Prohibit these changes in the 64bit mode, since the
3084 lowering is more complicated. */
3085 if (flag_code == CODE_64BIT
3086 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3087 {
0f3f3d8b 3088 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3089 i.op[op].regs->reg_name,
3090 i.suffix);
3091 return 0;
3092 }
3093#if REGISTER_WARNINGS
3094 if (!quiet_warnings
3095 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3096 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3097 (i.op[op].regs + (i.types[op] & Reg16
3098 ? REGNAM_AL - REGNAM_AX
3099 : REGNAM_AL - REGNAM_EAX))->reg_name,
3100 i.op[op].regs->reg_name,
3101 i.suffix);
3102#endif
3103 continue;
3104 }
3105 /* Any other register is bad. */
3106 if (i.types[op] & (Reg | RegMMX | RegXMM
3107 | SReg2 | SReg3
3108 | Control | Debug | Test
3109 | FloatReg | FloatAcc))
3110 {
3111 as_bad (_("`%%%s' not allowed with `%s%c'"),
3112 i.op[op].regs->reg_name,
3113 i.tm.name,
3114 i.suffix);
3115 return 0;
3116 }
3117 }
3118 return 1;
3119}
3120
3121static int
3122check_long_reg ()
3123{
3124 int op;
3125
3126 for (op = i.operands; --op >= 0;)
3127 /* Reject eight bit registers, except where the template requires
3128 them. (eg. movzb) */
3129 if ((i.types[op] & Reg8) != 0
3130 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3131 {
3132 as_bad (_("`%%%s' not allowed with `%s%c'"),
3133 i.op[op].regs->reg_name,
3134 i.tm.name,
3135 i.suffix);
3136 return 0;
3137 }
3138 /* Warn if the e prefix on a general reg is missing. */
3139 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3140 && (i.types[op] & Reg16) != 0
3141 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3142 {
3143 /* Prohibit these changes in the 64bit mode, since the
3144 lowering is more complicated. */
3145 if (flag_code == CODE_64BIT)
252b5132 3146 {
0f3f3d8b 3147 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3148 i.op[op].regs->reg_name,
3149 i.suffix);
3150 return 0;
252b5132 3151 }
29b0f896
AM		 3152#if REGISTER_WARNINGS
3153 else
3154 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3155 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3156 i.op[op].regs->reg_name,
3157 i.suffix);
3158#endif
252b5132 3159 }
29b0f896
AM		 3160 /* Warn if the r prefix on a general reg is missing. */
3161 else if ((i.types[op] & Reg64) != 0
3162 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3163 {
0f3f3d8b 3164 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3165 i.op[op].regs->reg_name,
3166 i.suffix);
3167 return 0;
3168 }
3169 return 1;
3170}
252b5132 3171
29b0f896
AM		 3172static int
3173check_qword_reg ()
3174{
3175 int op;
252b5132 3176
29b0f896
AM		 3177 for (op = i.operands; --op >= 0; )
3178 /* Reject eight bit registers, except where the template requires
3179 them. (eg. movzb) */
3180 if ((i.types[op] & Reg8) != 0
3181 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3182 {
3183 as_bad (_("`%%%s' not allowed with `%s%c'"),
3184 i.op[op].regs->reg_name,
3185 i.tm.name,
3186 i.suffix);
3187 return 0;
3188 }
3189 /* Warn if the e prefix on a general reg is missing. */
3190 else if (((i.types[op] & Reg16) != 0
3191 || (i.types[op] & Reg32) != 0)
3192 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3193 {
3194 /* Prohibit these changes in the 64bit mode, since the
3195 lowering is more complicated. */
0f3f3d8b 3196 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3197 i.op[op].regs->reg_name,
3198 i.suffix);
3199 return 0;
252b5132 3200 }
29b0f896
AM		 3201 return 1;
3202}
252b5132 3203
29b0f896
AM		 3204static int
3205check_word_reg ()
3206{
3207 int op;
3208 for (op = i.operands; --op >= 0;)
3209 /* Reject eight bit registers, except where the template requires
3210 them. (eg. movzb) */
3211 if ((i.types[op] & Reg8) != 0
3212 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3213 {
3214 as_bad (_("`%%%s' not allowed with `%s%c'"),
3215 i.op[op].regs->reg_name,
3216 i.tm.name,
3217 i.suffix);
3218 return 0;
3219 }
3220 /* Warn if the e prefix on a general reg is present. */
3221 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3222 && (i.types[op] & Reg32) != 0
3223 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3224 {
29b0f896
AM		 3225 /* Prohibit these changes in the 64bit mode, since the
3226 lowering is more complicated. */
3227 if (flag_code == CODE_64BIT)
252b5132 3228 {
0f3f3d8b 3229 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3230 i.op[op].regs->reg_name,
3231 i.suffix);
3232 return 0;
252b5132 3233 }
29b0f896
AM		 3234 else
3235#if REGISTER_WARNINGS
3236 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3237 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3238 i.op[op].regs->reg_name,
3239 i.suffix);
3240#endif
3241 }
3242 return 1;
3243}
252b5132 3244
29b0f896
AM		 3245static int
3246finalize_imm ()
3247{
3248 unsigned int overlap0, overlap1, overlap2;
3249
3250 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3251 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3252 && overlap0 != Imm8 && overlap0 != Imm8S
3253 && overlap0 != Imm16 && overlap0 != Imm32S
3254 && overlap0 != Imm32 && overlap0 != Imm64)
3255 {
3256 if (i.suffix)
3257 {
3258 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3259 ? Imm8 | Imm8S
3260 : (i.suffix == WORD_MNEM_SUFFIX
3261 ? Imm16
3262 : (i.suffix == QWORD_MNEM_SUFFIX
3263 ? Imm64 | Imm32S
3264 : Imm32)));
3265 }
3266 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3267 || overlap0 == (Imm16 | Imm32)
3268 || overlap0 == (Imm16 | Imm32S))
3269 {
3270 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3271 ? Imm16 : Imm32S);
3272 }
3273 if (overlap0 != Imm8 && overlap0 != Imm8S
3274 && overlap0 != Imm16 && overlap0 != Imm32S
3275 && overlap0 != Imm32 && overlap0 != Imm64)
3276 {
3277 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3278 return 0;
3279 }
3280 }
3281 i.types[0] = overlap0;
3282
3283 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3284 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3285 && overlap1 != Imm8 && overlap1 != Imm8S
3286 && overlap1 != Imm16 && overlap1 != Imm32S
3287 && overlap1 != Imm32 && overlap1 != Imm64)
3288 {
3289 if (i.suffix)
3290 {
3291 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3292 ? Imm8 | Imm8S
3293 : (i.suffix == WORD_MNEM_SUFFIX
3294 ? Imm16
3295 : (i.suffix == QWORD_MNEM_SUFFIX
3296 ? Imm64 | Imm32S
3297 : Imm32)));
3298 }
3299 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3300 || overlap1 == (Imm16 | Imm32)
3301 || overlap1 == (Imm16 | Imm32S))
3302 {
3303 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3304 ? Imm16 : Imm32S);
3305 }
3306 if (overlap1 != Imm8 && overlap1 != Imm8S
3307 && overlap1 != Imm16 && overlap1 != Imm32S
3308 && overlap1 != Imm32 && overlap1 != Imm64)
3309 {
3310 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3311 return 0;
3312 }
3313 }
3314 i.types[1] = overlap1;
3315
3316 overlap2 = i.types[2] & i.tm.operand_types[2];
3317 assert ((overlap2 & Imm) == 0);
3318 i.types[2] = overlap2;
3319
3320 return 1;
3321}
3322
3323static int
3324process_operands ()
3325{
3326 /* Default segment register this instruction will use for memory
3327 accesses. 0 means unknown. This is only for optimizing out
3328 unnecessary segment overrides. */
3329 const seg_entry *default_seg = 0;
3330
3331 /* The imul $imm, %reg instruction is converted into
3332 imul $imm, %reg, %reg, and the clr %reg instruction
3333 is converted into xor %reg, %reg. */
3334 if (i.tm.opcode_modifier & regKludge)
3335 {
3336 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3337 /* Pretend we saw the extra register operand. */
3338 assert (i.op[first_reg_op + 1].regs == 0);
3339 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3340 i.types[first_reg_op + 1] = i.types[first_reg_op];
3341 i.reg_operands = 2;
3342 }
3343
3344 if (i.tm.opcode_modifier & ShortForm)
3345 {
3346 /* The register or float register operand is in operand 0 or 1. */
3347 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3348 /* Register goes in low 3 bits of opcode. */
3349 i.tm.base_opcode |= i.op[op].regs->reg_num;
3350 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3351 i.rex |= REX_EXTZ;
3352 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3353 {
3354 /* Warn about some common errors, but press on regardless.
3355 The first case can be generated by gcc (<= 2.8.1). */
3356 if (i.operands == 2)
3357 {
3358 /* Reversed arguments on faddp, fsubp, etc. */
3359 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3360 i.op[1].regs->reg_name,
3361 i.op[0].regs->reg_name);
3362 }
3363 else
3364 {
3365 /* Extraneous `l' suffix on fp insn. */
3366 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3367 i.op[0].regs->reg_name);
3368 }
3369 }
3370 }
3371 else if (i.tm.opcode_modifier & Modrm)
3372 {
3373 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3374 must be put into the modrm byte). Now, we make the modrm and
3375 index base bytes based on all the info we've collected. */
29b0f896
AM		 3376
3377 default_seg = build_modrm_byte ();
3378 }
3379 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3380 {
3381 if (i.tm.base_opcode == POP_SEG_SHORT
3382 && i.op[0].regs->reg_num == 1)
3383 {
3384 as_bad (_("you can't `pop %%cs'"));
3385 return 0;
3386 }
3387 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3388 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3389 i.rex |= REX_EXTZ;
3390 }
3391 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3392 {
3393 default_seg = &ds;
3394 }
3395 else if ((i.tm.opcode_modifier & IsString) != 0)
3396 {
3397 /* For the string instructions that allow a segment override
3398 on one of their operands, the default segment is ds. */
3399 default_seg = &ds;
3400 }
3401
30123838
JB		 3402 if ((i.tm.base_opcode == 0x8d /* lea */
3403 || (i.tm.cpu_flags & CpuSVME))
3404 && i.seg[0] && !quiet_warnings)
3405 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3406
3407 /* If a segment was explicitly specified, and the specified segment
3408 is not the default, use an opcode prefix to select it. If we
3409 never figured out what the default segment is, then default_seg
3410 will be zero at this point, and the specified segment prefix will
3411 always be used. */
29b0f896
AM		 3412 if ((i.seg[0]) && (i.seg[0] != default_seg))
3413 {
3414 if (!add_prefix (i.seg[0]->seg_prefix))
3415 return 0;
3416 }
3417 return 1;
3418}
3419
3420static const seg_entry *
3421build_modrm_byte ()
3422{
3423 const seg_entry *default_seg = 0;
3424
3425 /* i.reg_operands MUST be the number of real register operands;
3426 implicit registers do not count. */
3427 if (i.reg_operands == 2)
3428 {
3429 unsigned int source, dest;
3430 source = ((i.types[0]
3431 & (Reg | RegMMX | RegXMM
3432 | SReg2 | SReg3
3433 | Control | Debug | Test))
3434 ? 0 : 1);
050dfa73 3435
fc225355
L		 3436 /* In 4 operands instructions with 2 immediate operands, the first
3437 two are immediate bytes and hence source operand will be in the
3438 next byte after the immediates */
050dfa73 3439 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
29b0f896
AM		 3440 dest = source + 1;
3441
3442 i.rm.mode = 3;
3443 /* One of the register operands will be encoded in the i.tm.reg
3444 field, the other in the combined i.tm.mode and i.tm.regmem
3445 fields. If no form of this instruction supports a memory
3446 destination operand, then we assume the source operand may
3447 sometimes be a memory operand and so we need to store the
3448 destination in the i.rm.reg field. */
3449 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3450 {
3451 i.rm.reg = i.op[dest].regs->reg_num;
3452 i.rm.regmem = i.op[source].regs->reg_num;
3453 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3454 i.rex |= REX_EXTX;
3455 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3456 i.rex |= REX_EXTZ;
3457 }
3458 else
3459 {
3460 i.rm.reg = i.op[source].regs->reg_num;
3461 i.rm.regmem = i.op[dest].regs->reg_num;
3462 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3463 i.rex |= REX_EXTZ;
3464 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3465 i.rex |= REX_EXTX;
3466 }
c4a530c5
JB		 3467 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3468 {
3469 if (!((i.types[0] | i.types[1]) & Control))
3470 abort ();
3471 i.rex &= ~(REX_EXTX | REX_EXTZ);
3472 add_prefix (LOCK_PREFIX_OPCODE);
3473 }
29b0f896
AM		 3474 }
3475 else
3476 { /* If it's not 2 reg operands... */
3477 if (i.mem_operands)
3478 {
3479 unsigned int fake_zero_displacement = 0;
3480 unsigned int op = ((i.types[0] & AnyMem)
3481 ? 0
3482 : (i.types[1] & AnyMem) ? 1 : 2);
3483
3484 default_seg = &ds;
3485
3486 if (i.base_reg == 0)
3487 {
3488 i.rm.mode = 0;
3489 if (!i.disp_operands)
3490 fake_zero_displacement = 1;
3491 if (i.index_reg == 0)
3492 {
3493 /* Operand is just <disp> */
20f0a1fc 3494 if (flag_code == CODE_64BIT)
29b0f896
AM		 3495 {
3496 /* 64bit mode overwrites the 32bit absolute
3497 addressing by RIP relative addressing and
3498 absolute addressing is encoded by one of the
3499 redundant SIB forms. */
3500 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3501 i.sib.base = NO_BASE_REGISTER;
3502 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3503 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3504 ? Disp32S : Disp32);
20f0a1fc 3505 }
fc225355
L		 3506 else if ((flag_code == CODE_16BIT)
3507 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3508 {
3509 i.rm.regmem = NO_BASE_REGISTER_16;
3510 i.types[op] = Disp16;
3511 }
3512 else
3513 {
3514 i.rm.regmem = NO_BASE_REGISTER;
3515 i.types[op] = Disp32;
29b0f896
AM		 3516 }
3517 }
3518 else /* !i.base_reg && i.index_reg */
3519 {
3520 i.sib.index = i.index_reg->reg_num;
3521 i.sib.base = NO_BASE_REGISTER;
3522 i.sib.scale = i.log2_scale_factor;
3523 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3524 i.types[op] &= ~Disp;
3525 if (flag_code != CODE_64BIT)
3526 i.types[op] |= Disp32; /* Must be 32 bit */
3527 else
3528 i.types[op] |= Disp32S;
3529 if ((i.index_reg->reg_flags & RegRex) != 0)
3530 i.rex |= REX_EXTY;
3531 }
3532 }
3533 /* RIP addressing for 64bit mode. */
3534 else if (i.base_reg->reg_type == BaseIndex)
3535 {
3536 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3537 i.types[op] &= ~ Disp;
29b0f896 3538 i.types[op] |= Disp32S;
71903a11 3539 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3540 if (! i.disp_operands)
3541 fake_zero_displacement = 1;
29b0f896
AM		 3542 }
3543 else if (i.base_reg->reg_type & Reg16)
3544 {
3545 switch (i.base_reg->reg_num)
3546 {
3547 case 3: /* (%bx) */
3548 if (i.index_reg == 0)
3549 i.rm.regmem = 7;
3550 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3551 i.rm.regmem = i.index_reg->reg_num - 6;
3552 break;
3553 case 5: /* (%bp) */
3554 default_seg = &ss;
3555 if (i.index_reg == 0)
3556 {
3557 i.rm.regmem = 6;
3558 if ((i.types[op] & Disp) == 0)
3559 {
3560 /* fake (%bp) into 0(%bp) */
3561 i.types[op] |= Disp8;
252b5132 3562 fake_zero_displacement = 1;
29b0f896
AM		 3563 }
3564 }
3565 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3566 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3567 break;
3568 default: /* (%si) -> 4 or (%di) -> 5 */
3569 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3570 }
3571 i.rm.mode = mode_from_disp_size (i.types[op]);
3572 }
3573 else /* i.base_reg and 32/64 bit mode */
3574 {
3575 if (flag_code == CODE_64BIT
3576 && (i.types[op] & Disp))
fc225355
L		 3577 i.types[op] = ((i.types[op] & Disp8)
3578 | (i.prefix[ADDR_PREFIX] == 0
3579 ? Disp32S : Disp32));
20f0a1fc 3580
29b0f896
AM		 3581 i.rm.regmem = i.base_reg->reg_num;
3582 if ((i.base_reg->reg_flags & RegRex) != 0)
3583 i.rex |= REX_EXTZ;
3584 i.sib.base = i.base_reg->reg_num;
3585 /* x86-64 ignores REX prefix bit here to avoid decoder
3586 complications. */
3587 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3588 {
3589 default_seg = &ss;
3590 if (i.disp_operands == 0)
3591 {
3592 fake_zero_displacement = 1;
3593 i.types[op] |= Disp8;
3594 }
3595 }
3596 else if (i.base_reg->reg_num == ESP_REG_NUM)
3597 {
3598 default_seg = &ss;
3599 }
3600 i.sib.scale = i.log2_scale_factor;
3601 if (i.index_reg == 0)
3602 {
3603 /* <disp>(%esp) becomes two byte modrm with no index
3604 register. We've already stored the code for esp
3605 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3606 Any base register besides %esp will not use the
3607 extra modrm byte. */
3608 i.sib.index = NO_INDEX_REGISTER;
3609#if !SCALE1_WHEN_NO_INDEX
3610 /* Another case where we force the second modrm byte. */
3611 if (i.log2_scale_factor)
3612 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3613#endif
29b0f896
AM		 3614 }
3615 else
3616 {
3617 i.sib.index = i.index_reg->reg_num;
3618 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3619 if ((i.index_reg->reg_flags & RegRex) != 0)
3620 i.rex |= REX_EXTY;
3621 }
67a4f2b7
AO		 3622
3623 if (i.disp_operands
3624 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3625 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3626 i.rm.mode = 0;
3627 else
3628 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3629 }
252b5132 3630
29b0f896
AM		 3631 if (fake_zero_displacement)
3632 {
3633 /* Fakes a zero displacement assuming that i.types[op]
3634 holds the correct displacement size. */
3635 expressionS *exp;
3636
3637 assert (i.op[op].disps == 0);
3638 exp = &disp_expressions[i.disp_operands++];
3639 i.op[op].disps = exp;
3640 exp->X_op = O_constant;
3641 exp->X_add_number = 0;
3642 exp->X_add_symbol = (symbolS *) 0;
3643 exp->X_op_symbol = (symbolS *) 0;
3644 }
3645 }
252b5132 3646
29b0f896
AM		 3647 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3648 (if any) based on i.tm.extension_opcode. Again, we must be
3649 careful to make sure that segment/control/debug/test/MMX
3650 registers are coded into the i.rm.reg field. */
3651 if (i.reg_operands)
3652 {
3653 unsigned int op =
3654 ((i.types[0]
3655 & (Reg | RegMMX | RegXMM
3656 | SReg2 | SReg3
3657 | Control | Debug | Test))
3658 ? 0
3659 : ((i.types[1]
3660 & (Reg | RegMMX | RegXMM
3661 | SReg2 | SReg3
3662 | Control | Debug | Test))
3663 ? 1
3664 : 2));
3665 /* If there is an extension opcode to put here, the register
3666 number must be put into the regmem field. */
3667 if (i.tm.extension_opcode != None)
3668 {
3669 i.rm.regmem = i.op[op].regs->reg_num;
3670 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3671 i.rex |= REX_EXTZ;
3672 }
3673 else
3674 {
3675 i.rm.reg = i.op[op].regs->reg_num;
3676 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3677 i.rex |= REX_EXTX;
3678 }
252b5132 3679
29b0f896
AM		 3680 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3681 must set it to 3 to indicate this is a register operand
3682 in the regmem field. */
3683 if (!i.mem_operands)
3684 i.rm.mode = 3;
3685 }
252b5132 3686
29b0f896
AM		 3687 /* Fill in i.rm.reg field with extension opcode (if any). */
3688 if (i.tm.extension_opcode != None)
3689 i.rm.reg = i.tm.extension_opcode;
3690 }
3691 return default_seg;
3692}
252b5132 3693
29b0f896
AM		 3694static void
3695output_branch ()
3696{
3697 char *p;
3698 int code16;
3699 int prefix;
3700 relax_substateT subtype;
3701 symbolS *sym;
3702 offsetT off;
3703
3704 code16 = 0;
3705 if (flag_code == CODE_16BIT)
3706 code16 = CODE16;
3707
3708 prefix = 0;
3709 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3710 {
29b0f896
AM		 3711 prefix = 1;
3712 i.prefixes -= 1;
3713 code16 ^= CODE16;
252b5132 3714 }
29b0f896
AM		 3715 /* Pentium4 branch hints. */
3716 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3717 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3718 {
29b0f896
AM		 3719 prefix++;
3720 i.prefixes--;
3721 }
3722 if (i.prefix[REX_PREFIX] != 0)
3723 {
3724 prefix++;
3725 i.prefixes--;
2f66722d
AM		 3726 }
3727
29b0f896
AM		 3728 if (i.prefixes != 0 && !intel_syntax)
3729 as_warn (_("skipping prefixes on this instruction"));
3730
3731 /* It's always a symbol; End frag & setup for relax.
3732 Make sure there is enough room in this frag for the largest
3733 instruction we may generate in md_convert_frag. This is 2
3734 bytes for the opcode and room for the prefix and largest
3735 displacement. */
3736 frag_grow (prefix + 2 + 4);
3737 /* Prefix and 1 opcode byte go in fr_fix. */
3738 p = frag_more (prefix + 1);
3739 if (i.prefix[DATA_PREFIX] != 0)
3740 *p++ = DATA_PREFIX_OPCODE;
3741 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3742 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3743 *p++ = i.prefix[SEG_PREFIX];
3744 if (i.prefix[REX_PREFIX] != 0)
3745 *p++ = i.prefix[REX_PREFIX];
3746 *p = i.tm.base_opcode;
3747
3748 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3749 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3750 else if ((cpu_arch_flags & Cpu386) != 0)
3751 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3752 else
3753 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3754 subtype |= code16;
3e73aa7c 3755
29b0f896
AM		 3756 sym = i.op[0].disps->X_add_symbol;
3757 off = i.op[0].disps->X_add_number;
3e73aa7c 3758
29b0f896
AM		 3759 if (i.op[0].disps->X_op != O_constant
3760 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3761 {
29b0f896
AM		 3762 /* Handle complex expressions. */
3763 sym = make_expr_symbol (i.op[0].disps);
3764 off = 0;
3765 }
3e73aa7c 3766
29b0f896
AM		 3767 /* 1 possible extra opcode + 4 byte displacement go in var part.
3768 Pass reloc in fr_var. */
3769 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3770}
3e73aa7c 3771
29b0f896
AM		 3772static void
3773output_jump ()
3774{
3775 char *p;
3776 int size;
3e02c1cc 3777 fixS *fixP;
29b0f896
AM		 3778
3779 if (i.tm.opcode_modifier & JumpByte)
3780 {
3781 /* This is a loop or jecxz type instruction. */
3782 size = 1;
3783 if (i.prefix[ADDR_PREFIX] != 0)
3784 {
3785 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3786 i.prefixes -= 1;
3787 }
3788 /* Pentium4 branch hints. */
3789 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3790 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3791 {
3792 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3793 i.prefixes--;
3e73aa7c
JH		 3794 }
3795 }
29b0f896
AM		 3796 else
3797 {
3798 int code16;
3e73aa7c 3799
29b0f896
AM		 3800 code16 = 0;
3801 if (flag_code == CODE_16BIT)
3802 code16 = CODE16;
3e73aa7c 3803
29b0f896
AM		 3804 if (i.prefix[DATA_PREFIX] != 0)
3805 {
3806 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3807 i.prefixes -= 1;
3808 code16 ^= CODE16;
3809 }
252b5132 3810
29b0f896
AM		 3811 size = 4;
3812 if (code16)
3813 size = 2;
3814 }
9fcc94b6 3815
29b0f896
AM		 3816 if (i.prefix[REX_PREFIX] != 0)
3817 {
3818 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3819 i.prefixes -= 1;
3820 }
252b5132 3821
29b0f896
AM		 3822 if (i.prefixes != 0 && !intel_syntax)
3823 as_warn (_("skipping prefixes on this instruction"));
e0890092 3824
29b0f896
AM		 3825 p = frag_more (1 + size);
3826 *p++ = i.tm.base_opcode;
e0890092 3827
3e02c1cc
AM		 3828 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3829 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3830
3831 /* All jumps handled here are signed, but don't use a signed limit
3832 check for 32 and 16 bit jumps as we want to allow wrap around at
3833 4G and 64k respectively. */
3834 if (size == 1)
3835 fixP->fx_signed = 1;
29b0f896 3836}
e0890092 3837
29b0f896
AM		 3838static void
3839output_interseg_jump ()
3840{
3841 char *p;
3842 int size;
3843 int prefix;
3844 int code16;
252b5132 3845
29b0f896
AM		 3846 code16 = 0;
3847 if (flag_code == CODE_16BIT)
3848 code16 = CODE16;
a217f122 3849
29b0f896
AM		 3850 prefix = 0;
3851 if (i.prefix[DATA_PREFIX] != 0)
3852 {
3853 prefix = 1;
3854 i.prefixes -= 1;
3855 code16 ^= CODE16;
3856 }
3857 if (i.prefix[REX_PREFIX] != 0)
3858 {
3859 prefix++;
3860 i.prefixes -= 1;
3861 }
252b5132 3862
29b0f896
AM		 3863 size = 4;
3864 if (code16)
3865 size = 2;
252b5132 3866
29b0f896
AM		 3867 if (i.prefixes != 0 && !intel_syntax)
3868 as_warn (_("skipping prefixes on this instruction"));
252b5132 3869
29b0f896
AM		 3870 /* 1 opcode; 2 segment; offset */
3871 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3872
29b0f896
AM		 3873 if (i.prefix[DATA_PREFIX] != 0)
3874 *p++ = DATA_PREFIX_OPCODE;
252b5132 3875
29b0f896
AM		 3876 if (i.prefix[REX_PREFIX] != 0)
3877 *p++ = i.prefix[REX_PREFIX];
252b5132 3878
29b0f896
AM		 3879 *p++ = i.tm.base_opcode;
3880 if (i.op[1].imms->X_op == O_constant)
3881 {
3882 offsetT n = i.op[1].imms->X_add_number;
252b5132 3883
29b0f896
AM		 3884 if (size == 2
3885 && !fits_in_unsigned_word (n)
3886 && !fits_in_signed_word (n))
3887 {
3888 as_bad (_("16-bit jump out of range"));
3889 return;
3890 }
3891 md_number_to_chars (p, n, size);
3892 }
3893 else
3894 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3895 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3896 if (i.op[0].imms->X_op != O_constant)
3897 as_bad (_("can't handle non absolute segment in `%s'"),
3898 i.tm.name);
3899 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3900}
a217f122 3901
29b0f896
AM		 3902static void
3903output_insn ()
3904{
2bbd9c25
JJ		 3905 fragS *insn_start_frag;
3906 offsetT insn_start_off;
3907
29b0f896
AM		 3908 /* Tie dwarf2 debug info to the address at the start of the insn.
3909 We can't do this after the insn has been output as the current
3910 frag may have been closed off. eg. by frag_var. */
3911 dwarf2_emit_insn (0);
3912
2bbd9c25
JJ		 3913 insn_start_frag = frag_now;
3914 insn_start_off = frag_now_fix ();
3915
29b0f896
AM		 3916 /* Output jumps. */
3917 if (i.tm.opcode_modifier & Jump)
3918 output_branch ();
3919 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3920 output_jump ();
3921 else if (i.tm.opcode_modifier & JumpInterSegment)
3922 output_interseg_jump ();
3923 else
3924 {
3925 /* Output normal instructions here. */
3926 char *p;
3927 unsigned char *q;
331d2d0d 3928 unsigned int prefix;
252b5132 3929
ef05d495
L		 3930 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3931 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3932 use one more higher byte to specify a prefix the instruction
3933 requires. */
3934 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3935 {
331d2d0d
L		 3936 if (i.tm.base_opcode & 0xff000000)
3937 {
3938 prefix = (i.tm.base_opcode >> 24) & 0xff;
3939 goto check_prefix;
3940 }
3941 }
3942 else if ((i.tm.base_opcode & 0xff0000) != 0)
3943 {
3944 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3945 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3946 {
64e74474 3947 check_prefix:
bc4bd9ab
MK		 3948 if (prefix != REPE_PREFIX_OPCODE
3949 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3950 add_prefix (prefix);
3951 }
3952 else
331d2d0d 3953 add_prefix (prefix);
0f10071e 3954 }
252b5132 3955
29b0f896
AM		 3956 /* The prefix bytes. */
3957 for (q = i.prefix;
3958 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3959 q++)
3960 {
3961 if (*q)
3962 {
3963 p = frag_more (1);
3964 md_number_to_chars (p, (valueT) *q, 1);
3965 }
3966 }
252b5132 3967
29b0f896
AM		 3968 /* Now the opcode; be careful about word order here! */
3969 if (fits_in_unsigned_byte (i.tm.base_opcode))
3970 {
3971 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3972 }
3973 else
3974 {
ef05d495 3975 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3976 {
3977 p = frag_more (3);
3978 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3979 }
3980 else
3981 p = frag_more (2);
0f10071e 3982
29b0f896
AM		 3983 /* Put out high byte first: can't use md_number_to_chars! */
3984 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3985 *p = i.tm.base_opcode & 0xff;
3986 }
3e73aa7c 3987
29b0f896
AM		 3988 /* Now the modrm byte and sib byte (if present). */
3989 if (i.tm.opcode_modifier & Modrm)
3990 {
3991 p = frag_more (1);
3992 md_number_to_chars (p,
3993 (valueT) (i.rm.regmem << 0
3994 | i.rm.reg << 3
3995 | i.rm.mode << 6),
3996 1);
3997 /* If i.rm.regmem == ESP (4)
3998 && i.rm.mode != (Register mode)
3999 && not 16 bit
4000 ==> need second modrm byte. */
4001 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4002 && i.rm.mode != 3
4003 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4004 {
4005 p = frag_more (1);
4006 md_number_to_chars (p,
4007 (valueT) (i.sib.base << 0
4008 | i.sib.index << 3
4009 | i.sib.scale << 6),
4010 1);
4011 }
4012 }
3e73aa7c 4013
29b0f896 4014 if (i.disp_operands)
2bbd9c25 4015 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4016
29b0f896 4017 if (i.imm_operands)
2bbd9c25 4018 output_imm (insn_start_frag, insn_start_off);
29b0f896 4019 }
252b5132 4020
29b0f896
AM		 4021#ifdef DEBUG386
4022 if (flag_debug)
4023 {
7b81dfbb 4024 pi ("" /*line*/, &i);
29b0f896
AM		 4025 }
4026#endif /* DEBUG386 */
4027}
252b5132 4028
29b0f896 4029static void
64e74474 4030output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4031{
4032 char *p;
4033 unsigned int n;
252b5132 4034
29b0f896
AM		 4035 for (n = 0; n < i.operands; n++)
4036 {
4037 if (i.types[n] & Disp)
4038 {
4039 if (i.op[n].disps->X_op == O_constant)
4040 {
4041 int size;
4042 offsetT val;
252b5132 4043
29b0f896
AM		 4044 size = 4;
4045 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4046 {
4047 size = 2;
4048 if (i.types[n] & Disp8)
4049 size = 1;
4050 if (i.types[n] & Disp64)
4051 size = 8;
4052 }
4053 val = offset_in_range (i.op[n].disps->X_add_number,
4054 size);
4055 p = frag_more (size);
4056 md_number_to_chars (p, val, size);
4057 }
4058 else
4059 {
f86103b7 4060 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4061 int size = 4;
4062 int sign = 0;
4063 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4064
4065 /* The PC relative address is computed relative
4066 to the instruction boundary, so in case immediate
4067 fields follows, we need to adjust the value. */
4068 if (pcrel && i.imm_operands)
4069 {
4070 int imm_size = 4;
4071 unsigned int n1;
252b5132 4072
29b0f896
AM		 4073 for (n1 = 0; n1 < i.operands; n1++)
4074 if (i.types[n1] & Imm)
252b5132 4075 {
29b0f896 4076 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4077 {
29b0f896
AM		 4078 imm_size = 2;
4079 if (i.types[n1] & (Imm8 | Imm8S))
4080 imm_size = 1;
4081 if (i.types[n1] & Imm64)
4082 imm_size = 8;
252b5132 4083 }
29b0f896 4084 break;
252b5132 4085 }
29b0f896
AM		 4086 /* We should find the immediate. */
4087 if (n1 == i.operands)
4088 abort ();
4089 i.op[n].disps->X_add_number -= imm_size;
4090 }
520dc8e8 4091
29b0f896
AM		 4092 if (i.types[n] & Disp32S)
4093 sign = 1;
3e73aa7c 4094
29b0f896
AM		 4095 if (i.types[n] & (Disp16 | Disp64))
4096 {
4097 size = 2;
4098 if (i.types[n] & Disp64)
4099 size = 8;
4100 }
520dc8e8 4101
29b0f896 4102 p = frag_more (size);
2bbd9c25 4103 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4104 if (GOT_symbol
2bbd9c25 4105 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4106 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4107 || reloc_type == BFD_RELOC_X86_64_32S
4108 || (reloc_type == BFD_RELOC_64
4109 && object_64bit))
d6ab8113
JB		 4110 && (i.op[n].disps->X_op == O_symbol
4111 || (i.op[n].disps->X_op == O_add
4112 && ((symbol_get_value_expression
4113 (i.op[n].disps->X_op_symbol)->X_op)
4114 == O_subtract))))
4115 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4116 {
4117 offsetT add;
4118
4119 if (insn_start_frag == frag_now)
4120 add = (p - frag_now->fr_literal) - insn_start_off;
4121 else
4122 {
4123 fragS *fr;
4124
4125 add = insn_start_frag->fr_fix - insn_start_off;
4126 for (fr = insn_start_frag->fr_next;
4127 fr && fr != frag_now; fr = fr->fr_next)
4128 add += fr->fr_fix;
4129 add += p - frag_now->fr_literal;
4130 }
4131
4fa24527 4132 if (!object_64bit)
7b81dfbb
AJ		 4133 {
4134 reloc_type = BFD_RELOC_386_GOTPC;
4135 i.op[n].imms->X_add_number += add;
4136 }
4137 else if (reloc_type == BFD_RELOC_64)
4138 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4139 else
7b81dfbb
AJ		 4140 /* Don't do the adjustment for x86-64, as there
4141 the pcrel addressing is relative to the _next_
4142 insn, and that is taken care of in other code. */
d6ab8113 4143 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4144 }
062cd5e7 4145 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4146 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4147 }
4148 }
4149 }
4150}
252b5132 4151
29b0f896 4152static void
64e74474 4153output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4154{
4155 char *p;
4156 unsigned int n;
252b5132 4157
29b0f896
AM		 4158 for (n = 0; n < i.operands; n++)
4159 {
4160 if (i.types[n] & Imm)
4161 {
4162 if (i.op[n].imms->X_op == O_constant)
4163 {
4164 int size;
4165 offsetT val;
b4cac588 4166
29b0f896
AM		 4167 size = 4;
4168 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4169 {
4170 size = 2;
4171 if (i.types[n] & (Imm8 | Imm8S))
4172 size = 1;
4173 else if (i.types[n] & Imm64)
4174 size = 8;
4175 }
4176 val = offset_in_range (i.op[n].imms->X_add_number,
4177 size);
4178 p = frag_more (size);
4179 md_number_to_chars (p, val, size);
4180 }
4181 else
4182 {
4183 /* Not absolute_section.
4184 Need a 32-bit fixup (don't support 8bit
4185 non-absolute imms). Try to support other
4186 sizes ... */
f86103b7 4187 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4188 int size = 4;
4189 int sign = 0;
4190
4191 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4192 && (i.suffix == QWORD_MNEM_SUFFIX
4193 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4194 sign = 1;
4195 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4196 {
4197 size = 2;
4198 if (i.types[n] & (Imm8 | Imm8S))
4199 size = 1;
4200 if (i.types[n] & Imm64)
4201 size = 8;
4202 }
520dc8e8 4203
29b0f896
AM		 4204 p = frag_more (size);
4205 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4206
2bbd9c25
JJ		 4207 /* This is tough to explain. We end up with this one if we
4208 * have operands that look like
4209 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4210 * obtain the absolute address of the GOT, and it is strongly
4211 * preferable from a performance point of view to avoid using
4212 * a runtime relocation for this. The actual sequence of
4213 * instructions often look something like:
4214 *
4215 * call .L66
4216 * .L66:
4217 * popl %ebx
4218 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4219 *
4220 * The call and pop essentially return the absolute address
4221 * of the label .L66 and store it in %ebx. The linker itself
4222 * will ultimately change the first operand of the addl so
4223 * that %ebx points to the GOT, but to keep things simple, the
4224 * .o file must have this operand set so that it generates not
4225 * the absolute address of .L66, but the absolute address of
4226 * itself. This allows the linker itself simply treat a GOTPC
4227 * relocation as asking for a pcrel offset to the GOT to be
4228 * added in, and the addend of the relocation is stored in the
4229 * operand field for the instruction itself.
4230 *
4231 * Our job here is to fix the operand so that it would add
4232 * the correct offset so that %ebx would point to itself. The
4233 * thing that is tricky is that .-.L66 will point to the
4234 * beginning of the instruction, so we need to further modify
4235 * the operand so that it will point to itself. There are
4236 * other cases where you have something like:
4237 *
4238 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4239 *
4240 * and here no correction would be required. Internally in
4241 * the assembler we treat operands of this form as not being
4242 * pcrel since the '.' is explicitly mentioned, and I wonder
4243 * whether it would simplify matters to do it this way. Who
4244 * knows. In earlier versions of the PIC patches, the
4245 * pcrel_adjust field was used to store the correction, but
4246 * since the expression is not pcrel, I felt it would be
4247 * confusing to do it this way. */
4248
d6ab8113 4249 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4250 || reloc_type == BFD_RELOC_X86_64_32S
4251 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4252 && GOT_symbol
4253 && GOT_symbol == i.op[n].imms->X_add_symbol
4254 && (i.op[n].imms->X_op == O_symbol
4255 || (i.op[n].imms->X_op == O_add
4256 && ((symbol_get_value_expression
4257 (i.op[n].imms->X_op_symbol)->X_op)
4258 == O_subtract))))
4259 {
2bbd9c25
JJ		 4260 offsetT add;
4261
4262 if (insn_start_frag == frag_now)
4263 add = (p - frag_now->fr_literal) - insn_start_off;
4264 else
4265 {
4266 fragS *fr;
4267
4268 add = insn_start_frag->fr_fix - insn_start_off;
4269 for (fr = insn_start_frag->fr_next;
4270 fr && fr != frag_now; fr = fr->fr_next)
4271 add += fr->fr_fix;
4272 add += p - frag_now->fr_literal;
4273 }
4274
4fa24527 4275 if (!object_64bit)
d6ab8113 4276 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4277 else if (size == 4)
d6ab8113 4278 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4279 else if (size == 8)
4280 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4281 i.op[n].imms->X_add_number += add;
29b0f896 4282 }
29b0f896
AM		 4283 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4284 i.op[n].imms, 0, reloc_type);
4285 }
4286 }
4287 }
252b5132
RH		 4288}
4289\f
d182319b
JB		 4290/* x86_cons_fix_new is called via the expression parsing code when a
4291 reloc is needed. We use this hook to get the correct .got reloc. */
4292static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4293static int cons_sign = -1;
4294
4295void
4296x86_cons_fix_new (fragS *frag,
64e74474
AM		 4297 unsigned int off,
4298 unsigned int len,
4299 expressionS *exp)
d182319b
JB		 4300{
4301 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4302
4303 got_reloc = NO_RELOC;
4304
4305#ifdef TE_PE
4306 if (exp->X_op == O_secrel)
4307 {
4308 exp->X_op = O_symbol;
4309 r = BFD_RELOC_32_SECREL;
4310 }
4311#endif
4312
4313 fix_new_exp (frag, off, len, exp, 0, r);
4314}
4315
718ddfc0
JB		 4316#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4317# define lex_got(reloc, adjust, types) NULL
4318#else
f3c180ae
AM		 4319/* Parse operands of the form
4320 <symbol>@GOTOFF+<nnn>
4321 and similar .plt or .got references.
4322
4323 If we find one, set up the correct relocation in RELOC and copy the
4324 input string, minus the `@GOTOFF' into a malloc'd buffer for
4325 parsing by the calling routine. Return this buffer, and if ADJUST
4326 is non-null set it to the length of the string we removed from the
4327 input line. Otherwise return NULL. */
4328static char *
3956db08 4329lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4330 int *adjust,
4331 unsigned int *types)
f3c180ae 4332{
7b81dfbb
AJ		 4333 /* Some of the relocations depend on the size of what field is to
4334 be relocated. But in our callers i386_immediate and i386_displacement
4335 we don't yet know the operand size (this will be set by insn
4336 matching). Hence we record the word32 relocation here,
4337 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4338 static const struct {
4339 const char *str;
4fa24527 4340 const enum bfd_reloc_code_real rel[2];
3956db08 4341 const unsigned int types64;
f3c180ae 4342 } gotrel[] = {
7b81dfbb 4343 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4344 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4345 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4346 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4347 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4348 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4349 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4350 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4351 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4352 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4353 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4354 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4355 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4356 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4357 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4358 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4359 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4360 };
4361 char *cp;
4362 unsigned int j;
4363
718ddfc0
JB		 4364 if (!IS_ELF)
4365 return NULL;
4366
f3c180ae
AM		 4367 for (cp = input_line_pointer; *cp != '@'; cp++)
4368 if (is_end_of_line[(unsigned char) *cp])
4369 return NULL;
4370
4371 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4372 {
4373 int len;
4374
4375 len = strlen (gotrel[j].str);
28f81592 4376 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4377 {
4fa24527 4378 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4379 {
28f81592
AM		 4380 int first, second;
4381 char *tmpbuf, *past_reloc;
f3c180ae 4382
4fa24527 4383 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4384 if (adjust)
4385 *adjust = len;
f3c180ae 4386
3956db08
JB		 4387 if (types)
4388 {
4389 if (flag_code != CODE_64BIT)
4390 *types = Imm32|Disp32;
4391 else
4392 *types = gotrel[j].types64;
4393 }
4394
f3c180ae
AM		 4395 if (GOT_symbol == NULL)
4396 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4397
4398 /* Replace the relocation token with ' ', so that
4399 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4400
4401 /* The length of the first part of our input line. */
f3c180ae 4402 first = cp - input_line_pointer;
28f81592
AM		 4403
4404 /* The second part goes from after the reloc token until
4405 (and including) an end_of_line char. Don't use strlen
4406 here as the end_of_line char may not be a NUL. */
4407 past_reloc = cp + 1 + len;
4408 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4409 ;
4410 second = cp - past_reloc;
4411
4412 /* Allocate and copy string. The trailing NUL shouldn't
4413 be necessary, but be safe. */
4414 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4415 memcpy (tmpbuf, input_line_pointer, first);
4416 tmpbuf[first] = ' ';
28f81592
AM		 4417 memcpy (tmpbuf + first + 1, past_reloc, second);
4418 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4419 return tmpbuf;
4420 }
4421
4fa24527
JB		 4422 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4423 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4424 return NULL;
4425 }
4426 }
4427
4428 /* Might be a symbol version string. Don't as_bad here. */
4429 return NULL;
4430}
4431
f3c180ae
AM		 4432void
4433x86_cons (exp, size)
4434 expressionS *exp;
4435 int size;
4436{
4fa24527 4437 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4438 {
4439 /* Handle @GOTOFF and the like in an expression. */
4440 char *save;
4441 char *gotfree_input_line;
4442 int adjust;
4443
4444 save = input_line_pointer;
3956db08 4445 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4446 if (gotfree_input_line)
4447 input_line_pointer = gotfree_input_line;
4448
4449 expression (exp);
4450
4451 if (gotfree_input_line)
4452 {
4453 /* expression () has merrily parsed up to the end of line,
4454 or a comma - in the wrong buffer. Transfer how far
4455 input_line_pointer has moved to the right buffer. */
4456 input_line_pointer = (save
4457 + (input_line_pointer - gotfree_input_line)
4458 + adjust);
4459 free (gotfree_input_line);
4460 }
4461 }
4462 else
4463 expression (exp);
4464}
4465#endif
4466
d182319b 4467static void signed_cons (int size)
6482c264 4468{
d182319b
JB		 4469 if (flag_code == CODE_64BIT)
4470 cons_sign = 1;
4471 cons (size);
4472 cons_sign = -1;
6482c264
NC		 4473}
4474
d182319b 4475#ifdef TE_PE
6482c264
NC		 4476static void
4477pe_directive_secrel (dummy)
4478 int dummy ATTRIBUTE_UNUSED;
4479{
4480 expressionS exp;
4481
4482 do
4483 {
4484 expression (&exp);
4485 if (exp.X_op == O_symbol)
4486 exp.X_op = O_secrel;
4487
4488 emit_expr (&exp, 4);
4489 }
4490 while (*input_line_pointer++ == ',');
4491
4492 input_line_pointer--;
4493 demand_empty_rest_of_line ();
4494}
6482c264
NC		 4495#endif
4496
252b5132 4497static int
70e41ade 4498i386_immediate (char *imm_start)
252b5132
RH		 4499{
4500 char *save_input_line_pointer;
f3c180ae 4501 char *gotfree_input_line;
252b5132 4502 segT exp_seg = 0;
47926f60 4503 expressionS *exp;
3956db08 4504 unsigned int types = ~0U;
252b5132
RH		 4505
4506 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4507 {
31b2323c
L		 4508 as_bad (_("at most %d immediate operands are allowed"),
4509 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4510 return 0;
4511 }
4512
4513 exp = &im_expressions[i.imm_operands++];
520dc8e8 4514 i.op[this_operand].imms = exp;
252b5132
RH		 4515
4516 if (is_space_char (*imm_start))
4517 ++imm_start;
4518
4519 save_input_line_pointer = input_line_pointer;
4520 input_line_pointer = imm_start;
4521
3956db08 4522 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4523 if (gotfree_input_line)
4524 input_line_pointer = gotfree_input_line;
252b5132
RH		 4525
4526 exp_seg = expression (exp);
4527
83183c0c 4528 SKIP_WHITESPACE ();
252b5132 4529 if (*input_line_pointer)
f3c180ae 4530 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4531
4532 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4533 if (gotfree_input_line)
4534 free (gotfree_input_line);
252b5132 4535
2daf4fd8 4536 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4537 {
47926f60 4538 /* Missing or bad expr becomes absolute 0. */
d0b47220 4539 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4540 imm_start);
252b5132
RH		 4541 exp->X_op = O_constant;
4542 exp->X_add_number = 0;
4543 exp->X_add_symbol = (symbolS *) 0;
4544 exp->X_op_symbol = (symbolS *) 0;
252b5132 4545 }
3e73aa7c 4546 else if (exp->X_op == O_constant)
252b5132 4547 {
47926f60 4548 /* Size it properly later. */
3e73aa7c
JH		 4549 i.types[this_operand] |= Imm64;
4550 /* If BFD64, sign extend val. */
4551 if (!use_rela_relocations)
4552 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4553 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4554 }
4c63da97 4555#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4556 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4557 && exp_seg != absolute_section
47926f60 4558 && exp_seg != text_section
24eab124
AM		 4559 && exp_seg != data_section
4560 && exp_seg != bss_section
4561 && exp_seg != undefined_section
f86103b7 4562 && !bfd_is_com_section (exp_seg))
252b5132 4563 {
d0b47220 4564 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4565 return 0;
4566 }
4567#endif
bb8f5920
L		 4568 else if (!intel_syntax && exp->X_op == O_register)
4569 {
4570 as_bad (_("illegal immediate register operand %s"), imm_start);
4571 return 0;
4572 }
252b5132
RH		 4573 else
4574 {
4575 /* This is an address. The size of the address will be
24eab124 4576 determined later, depending on destination register,
3e73aa7c
JH		 4577 suffix, or the default for the section. */
4578 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4579 i.types[this_operand] &= types;
252b5132
RH		 4580 }
4581
4582 return 1;
4583}
4584
551c1ca1 4585static char *i386_scale PARAMS ((char *));
252b5132 4586
551c1ca1 4587static char *
252b5132
RH		 4588i386_scale (scale)
4589 char *scale;
4590{
551c1ca1
AM		 4591 offsetT val;
4592 char *save = input_line_pointer;
252b5132 4593
551c1ca1
AM		 4594 input_line_pointer = scale;
4595 val = get_absolute_expression ();
4596
4597 switch (val)
252b5132 4598 {
551c1ca1 4599 case 1:
252b5132
RH		 4600 i.log2_scale_factor = 0;
4601 break;
551c1ca1 4602 case 2:
252b5132
RH		 4603 i.log2_scale_factor = 1;
4604 break;
551c1ca1 4605 case 4:
252b5132
RH		 4606 i.log2_scale_factor = 2;
4607 break;
551c1ca1 4608 case 8:
252b5132
RH		 4609 i.log2_scale_factor = 3;
4610 break;
4611 default:
a724f0f4
JB		 4612 {
4613 char sep = *input_line_pointer;
4614
4615 *input_line_pointer = '\0';
4616 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4617 scale);
4618 *input_line_pointer = sep;
4619 input_line_pointer = save;
4620 return NULL;
4621 }
252b5132 4622 }
29b0f896 4623 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4624 {
4625 as_warn (_("scale factor of %d without an index register"),
24eab124 4626 1 << i.log2_scale_factor);
252b5132
RH		 4627#if SCALE1_WHEN_NO_INDEX
4628 i.log2_scale_factor = 0;
4629#endif
4630 }
551c1ca1
AM		 4631 scale = input_line_pointer;
4632 input_line_pointer = save;
4633 return scale;
252b5132
RH		 4634}
4635
4636static int i386_displacement PARAMS ((char *, char *));
4637
4638static int
4639i386_displacement (disp_start, disp_end)
4640 char *disp_start;
4641 char *disp_end;
4642{
29b0f896 4643 expressionS *exp;
252b5132
RH		 4644 segT exp_seg = 0;
4645 char *save_input_line_pointer;
f3c180ae 4646 char *gotfree_input_line;
e05278af 4647 int bigdisp, override;
3956db08 4648 unsigned int types = Disp;
252b5132 4649
31b2323c
L		 4650 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4651 {
4652 as_bad (_("at most %d displacement operands are allowed"),
4653 MAX_MEMORY_OPERANDS);
4654 return 0;
4655 }
4656
e05278af
JB		 4657 if ((i.types[this_operand] & JumpAbsolute)
4658 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4659 {
4660 bigdisp = Disp32;
4661 override = (i.prefix[ADDR_PREFIX] != 0);
4662 }
4663 else
4664 {
4665 /* For PC-relative branches, the width of the displacement
4666 is dependent upon data size, not address size. */
4667 bigdisp = 0;
4668 override = (i.prefix[DATA_PREFIX] != 0);
4669 }
3e73aa7c 4670 if (flag_code == CODE_64BIT)
7ecd2f8b 4671 {
e05278af 4672 if (!bigdisp)
64e74474
AM		 4673 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4674 ? Disp16
4675 : Disp32S | Disp32);
e05278af 4676 else if (!override)
3956db08 4677 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4678 }
e05278af
JB		 4679 else
4680 {
4681 if (!bigdisp)
4682 {
4683 if (!override)
4684 override = (i.suffix == (flag_code != CODE_16BIT
4685 ? WORD_MNEM_SUFFIX
4686 : LONG_MNEM_SUFFIX));
4687 bigdisp = Disp32;
4688 }
4689 if ((flag_code == CODE_16BIT) ^ override)
4690 bigdisp = Disp16;
4691 }
252b5132
RH		 4692 i.types[this_operand] |= bigdisp;
4693
4694 exp = &disp_expressions[i.disp_operands];
520dc8e8 4695 i.op[this_operand].disps = exp;
252b5132
RH		 4696 i.disp_operands++;
4697 save_input_line_pointer = input_line_pointer;
4698 input_line_pointer = disp_start;
4699 END_STRING_AND_SAVE (disp_end);
4700
4701#ifndef GCC_ASM_O_HACK
4702#define GCC_ASM_O_HACK 0
4703#endif
4704#if GCC_ASM_O_HACK
4705 END_STRING_AND_SAVE (disp_end + 1);
4706 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4707 && displacement_string_end[-1] == '+')
252b5132
RH		 4708 {
4709 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4710 constraint within gcc asm statements.
4711 For instance:
4712
4713 #define _set_tssldt_desc(n,addr,limit,type) \
4714 __asm__ __volatile__ ( \
4715 "movw %w2,%0\n\t" \
4716 "movw %w1,2+%0\n\t" \
4717 "rorl $16,%1\n\t" \
4718 "movb %b1,4+%0\n\t" \
4719 "movb %4,5+%0\n\t" \
4720 "movb $0,6+%0\n\t" \
4721 "movb %h1,7+%0\n\t" \
4722 "rorl $16,%1" \
4723 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4724
4725 This works great except that the output assembler ends
4726 up looking a bit weird if it turns out that there is
4727 no offset. You end up producing code that looks like:
4728
4729 #APP
4730 movw $235,(%eax)
4731 movw %dx,2+(%eax)
4732 rorl $16,%edx
4733 movb %dl,4+(%eax)
4734 movb $137,5+(%eax)
4735 movb $0,6+(%eax)
4736 movb %dh,7+(%eax)
4737 rorl $16,%edx
4738 #NO_APP
4739
47926f60 4740 So here we provide the missing zero. */
24eab124
AM		 4741
4742 *displacement_string_end = '0';
252b5132
RH		 4743 }
4744#endif
3956db08 4745 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4746 if (gotfree_input_line)
4747 input_line_pointer = gotfree_input_line;
252b5132 4748
24eab124 4749 exp_seg = expression (exp);
252b5132 4750
636c26b0
AM		 4751 SKIP_WHITESPACE ();
4752 if (*input_line_pointer)
4753 as_bad (_("junk `%s' after expression"), input_line_pointer);
4754#if GCC_ASM_O_HACK
4755 RESTORE_END_STRING (disp_end + 1);
4756#endif
4757 RESTORE_END_STRING (disp_end);
4758 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4759 if (gotfree_input_line)
4760 free (gotfree_input_line);
636c26b0 4761
24eab124
AM		 4762 /* We do this to make sure that the section symbol is in
4763 the symbol table. We will ultimately change the relocation
47926f60 4764 to be relative to the beginning of the section. */
1ae12ab7 4765 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4766 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4767 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4768 {
636c26b0
AM		 4769 if (exp->X_op != O_symbol)
4770 {
4771 as_bad (_("bad expression used with @%s"),
4772 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4773 ? "GOTPCREL"
4774 : "GOTOFF"));
4775 return 0;
4776 }
4777
e5cb08ac 4778 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4779 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4780 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4781 exp->X_op = O_subtract;
4782 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4783 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4784 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4785 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4786 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4787 else
29b0f896 4788 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4789 }
252b5132 4790
2daf4fd8
AM		 4791 if (exp->X_op == O_absent || exp->X_op == O_big)
4792 {
47926f60 4793 /* Missing or bad expr becomes absolute 0. */
d0b47220 4794 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4795 disp_start);
4796 exp->X_op = O_constant;
4797 exp->X_add_number = 0;
4798 exp->X_add_symbol = (symbolS *) 0;
4799 exp->X_op_symbol = (symbolS *) 0;
4800 }
4801
4c63da97 4802#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4803 if (exp->X_op != O_constant
45288df1 4804 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4805 && exp_seg != absolute_section
45288df1
AM		 4806 && exp_seg != text_section
4807 && exp_seg != data_section
4808 && exp_seg != bss_section
31312f95 4809 && exp_seg != undefined_section
f86103b7 4810 && !bfd_is_com_section (exp_seg))
24eab124 4811 {
d0b47220 4812 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4813 return 0;
4814 }
252b5132 4815#endif
3956db08
JB		 4816
4817 if (!(i.types[this_operand] & ~Disp))
4818 i.types[this_operand] &= types;
4819
252b5132
RH		 4820 return 1;
4821}
4822
e5cb08ac 4823static int i386_index_check PARAMS ((const char *));
252b5132 4824
eecb386c 4825/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4826 Return 1 on success, 0 on a failure. */
4827
252b5132 4828static int
eecb386c
AM		 4829i386_index_check (operand_string)
4830 const char *operand_string;
252b5132 4831{
3e73aa7c 4832 int ok;
24eab124 4833#if INFER_ADDR_PREFIX
eecb386c
AM		 4834 int fudged = 0;
4835
24eab124
AM		 4836 tryprefix:
4837#endif
3e73aa7c 4838 ok = 1;
30123838
JB		 4839 if ((current_templates->start->cpu_flags & CpuSVME)
4840 && current_templates->end[-1].operand_types[0] == AnyMem)
4841 {
4842 /* Memory operands of SVME insns are special in that they only allow
4843 rAX as their memory address and ignore any segment override. */
4844 unsigned RegXX;
4845
4846 /* SKINIT is even more restrictive: it always requires EAX. */
4847 if (strcmp (current_templates->start->name, "skinit") == 0)
4848 RegXX = Reg32;
4849 else if (flag_code == CODE_64BIT)
4850 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4851 else
64e74474
AM		 4852 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4853 ? Reg16
4854 : Reg32);
30123838
JB		 4855 if (!i.base_reg
4856 || !(i.base_reg->reg_type & Acc)
4857 || !(i.base_reg->reg_type & RegXX)
4858 || i.index_reg
4859 || (i.types[0] & Disp))
4860 ok = 0;
4861 }
4862 else if (flag_code == CODE_64BIT)
64e74474
AM		 4863 {
4864 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4865
4866 if ((i.base_reg
4867 && ((i.base_reg->reg_type & RegXX) == 0)
4868 && (i.base_reg->reg_type != BaseIndex
4869 || i.index_reg))
4870 || (i.index_reg
4871 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4872 != (RegXX | BaseIndex))))
4873 ok = 0;
3e73aa7c
JH		 4874 }
4875 else
4876 {
4877 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4878 {
4879 /* 16bit checks. */
4880 if ((i.base_reg
29b0f896
AM		 4881 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4882 != (Reg16 | BaseIndex)))
3e73aa7c 4883 || (i.index_reg
29b0f896
AM		 4884 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4885 != (Reg16 | BaseIndex))
4886 || !(i.base_reg
4887 && i.base_reg->reg_num < 6
4888 && i.index_reg->reg_num >= 6
4889 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4890 ok = 0;
4891 }
4892 else
e5cb08ac 4893 {
3e73aa7c
JH		 4894 /* 32bit checks. */
4895 if ((i.base_reg
4896 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4897 || (i.index_reg
29b0f896
AM		 4898 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4899 != (Reg32 | BaseIndex))))
e5cb08ac 4900 ok = 0;
3e73aa7c
JH		 4901 }
4902 }
4903 if (!ok)
24eab124
AM		 4904 {
4905#if INFER_ADDR_PREFIX
20f0a1fc 4906 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4907 {
4908 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4909 i.prefixes += 1;
b23bac36
AM		 4910 /* Change the size of any displacement too. At most one of
4911 Disp16 or Disp32 is set.
4912 FIXME. There doesn't seem to be any real need for separate
4913 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4914 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4915 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4916 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4917 fudged = 1;
24eab124
AM		 4918 goto tryprefix;
4919 }
eecb386c
AM		 4920 if (fudged)
4921 as_bad (_("`%s' is not a valid base/index expression"),
4922 operand_string);
4923 else
c388dee8 4924#endif
eecb386c
AM		 4925 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4926 operand_string,
3e73aa7c 4927 flag_code_names[flag_code]);
24eab124 4928 }
20f0a1fc 4929 return ok;
24eab124 4930}
252b5132 4931
252b5132 4932/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4933 on error. */
252b5132 4934
252b5132
RH		 4935static int
4936i386_operand (operand_string)
4937 char *operand_string;
4938{
af6bdddf
AM		 4939 const reg_entry *r;
4940 char *end_op;
24eab124 4941 char *op_string = operand_string;
252b5132 4942
24eab124 4943 if (is_space_char (*op_string))
252b5132
RH		 4944 ++op_string;
4945
24eab124 4946 /* We check for an absolute prefix (differentiating,
47926f60 4947 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4948 if (*op_string == ABSOLUTE_PREFIX)
4949 {
4950 ++op_string;
4951 if (is_space_char (*op_string))
4952 ++op_string;
4953 i.types[this_operand] |= JumpAbsolute;
4954 }
252b5132 4955
47926f60 4956 /* Check if operand is a register. */
4d1bb795 4957 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4958 {
24eab124
AM		 4959 /* Check for a segment override by searching for ':' after a
4960 segment register. */
4961 op_string = end_op;
4962 if (is_space_char (*op_string))
4963 ++op_string;
4964 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4965 {
4966 switch (r->reg_num)
4967 {
4968 case 0:
4969 i.seg[i.mem_operands] = &es;
4970 break;
4971 case 1:
4972 i.seg[i.mem_operands] = &cs;
4973 break;
4974 case 2:
4975 i.seg[i.mem_operands] = &ss;
4976 break;
4977 case 3:
4978 i.seg[i.mem_operands] = &ds;
4979 break;
4980 case 4:
4981 i.seg[i.mem_operands] = &fs;
4982 break;
4983 case 5:
4984 i.seg[i.mem_operands] = &gs;
4985 break;
4986 }
252b5132 4987
24eab124 4988 /* Skip the ':' and whitespace. */
252b5132
RH		 4989 ++op_string;
4990 if (is_space_char (*op_string))
24eab124 4991 ++op_string;
252b5132 4992
24eab124
AM		 4993 if (!is_digit_char (*op_string)
4994 && !is_identifier_char (*op_string)
4995 && *op_string != '('
4996 && *op_string != ABSOLUTE_PREFIX)
4997 {
4998 as_bad (_("bad memory operand `%s'"), op_string);
4999 return 0;
5000 }
47926f60 5001 /* Handle case of %es:*foo. */
24eab124
AM		 5002 if (*op_string == ABSOLUTE_PREFIX)
5003 {
5004 ++op_string;
5005 if (is_space_char (*op_string))
5006 ++op_string;
5007 i.types[this_operand] |= JumpAbsolute;
5008 }
5009 goto do_memory_reference;
5010 }
5011 if (*op_string)
5012 {
d0b47220 5013 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5014 return 0;
5015 }
5016 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5017 i.op[this_operand].regs = r;
24eab124
AM		 5018 i.reg_operands++;
5019 }
af6bdddf
AM		 5020 else if (*op_string == REGISTER_PREFIX)
5021 {
5022 as_bad (_("bad register name `%s'"), op_string);
5023 return 0;
5024 }
24eab124 5025 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5026 {
24eab124
AM		 5027 ++op_string;
5028 if (i.types[this_operand] & JumpAbsolute)
5029 {
d0b47220 5030 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5031 return 0;
5032 }
5033 if (!i386_immediate (op_string))
5034 return 0;
5035 }
5036 else if (is_digit_char (*op_string)
5037 || is_identifier_char (*op_string)
e5cb08ac 5038 || *op_string == '(')
24eab124 5039 {
47926f60 5040 /* This is a memory reference of some sort. */
af6bdddf 5041 char *base_string;
252b5132 5042
47926f60 5043 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5044 char *displacement_string_start;
5045 char *displacement_string_end;
252b5132 5046
24eab124 5047 do_memory_reference:
24eab124
AM		 5048 if ((i.mem_operands == 1
5049 && (current_templates->start->opcode_modifier & IsString) == 0)
5050 || i.mem_operands == 2)
5051 {
5052 as_bad (_("too many memory references for `%s'"),
5053 current_templates->start->name);
5054 return 0;
5055 }
252b5132 5056
24eab124
AM		 5057 /* Check for base index form. We detect the base index form by
5058 looking for an ')' at the end of the operand, searching
5059 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5060 after the '('. */
af6bdddf 5061 base_string = op_string + strlen (op_string);
c3332e24 5062
af6bdddf
AM		 5063 --base_string;
5064 if (is_space_char (*base_string))
5065 --base_string;
252b5132 5066
47926f60 5067 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5068 displacement_string_start = op_string;
5069 displacement_string_end = base_string + 1;
252b5132 5070
24eab124
AM		 5071 if (*base_string == ')')
5072 {
af6bdddf 5073 char *temp_string;
24eab124
AM		 5074 unsigned int parens_balanced = 1;
5075 /* We've already checked that the number of left & right ()'s are
47926f60 5076 equal, so this loop will not be infinite. */
24eab124
AM		 5077 do
5078 {
5079 base_string--;
5080 if (*base_string == ')')
5081 parens_balanced++;
5082 if (*base_string == '(')
5083 parens_balanced--;
5084 }
5085 while (parens_balanced);
c3332e24 5086
af6bdddf 5087 temp_string = base_string;
c3332e24 5088
24eab124 5089 /* Skip past '(' and whitespace. */
252b5132
RH		 5090 ++base_string;
5091 if (is_space_char (*base_string))
24eab124 5092 ++base_string;
252b5132 5093
af6bdddf 5094 if (*base_string == ','
4d1bb795 5095 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 5096 {
af6bdddf 5097 displacement_string_end = temp_string;
252b5132 5098
af6bdddf 5099 i.types[this_operand] |= BaseIndex;
252b5132 5100
af6bdddf 5101 if (i.base_reg)
24eab124 5102 {
24eab124
AM		 5103 base_string = end_op;
5104 if (is_space_char (*base_string))
5105 ++base_string;
af6bdddf
AM		 5106 }
5107
5108 /* There may be an index reg or scale factor here. */
5109 if (*base_string == ',')
5110 {
5111 ++base_string;
5112 if (is_space_char (*base_string))
5113 ++base_string;
5114
4d1bb795 5115 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5116 {
af6bdddf 5117 base_string = end_op;
24eab124
AM		 5118 if (is_space_char (*base_string))
5119 ++base_string;
af6bdddf
AM		 5120 if (*base_string == ',')
5121 {
5122 ++base_string;
5123 if (is_space_char (*base_string))
5124 ++base_string;
5125 }
e5cb08ac 5126 else if (*base_string != ')')
af6bdddf
AM		 5127 {
5128 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5129 operand_string);
5130 return 0;
5131 }
24eab124 5132 }
af6bdddf 5133 else if (*base_string == REGISTER_PREFIX)
24eab124 5134 {
af6bdddf 5135 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5136 return 0;
5137 }
252b5132 5138
47926f60 5139 /* Check for scale factor. */
551c1ca1 5140 if (*base_string != ')')
af6bdddf 5141 {
551c1ca1
AM		 5142 char *end_scale = i386_scale (base_string);
5143
5144 if (!end_scale)
af6bdddf 5145 return 0;
24eab124 5146
551c1ca1 5147 base_string = end_scale;
af6bdddf
AM		 5148 if (is_space_char (*base_string))
5149 ++base_string;
5150 if (*base_string != ')')
5151 {
5152 as_bad (_("expecting `)' after scale factor in `%s'"),
5153 operand_string);
5154 return 0;
5155 }
5156 }
5157 else if (!i.index_reg)
24eab124 5158 {
af6bdddf
AM		 5159 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5160 *base_string);
24eab124
AM		 5161 return 0;
5162 }
5163 }
af6bdddf 5164 else if (*base_string != ')')
24eab124 5165 {
af6bdddf
AM		 5166 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5167 operand_string);
24eab124
AM		 5168 return 0;
5169 }
c3332e24 5170 }
af6bdddf 5171 else if (*base_string == REGISTER_PREFIX)
c3332e24 5172 {
af6bdddf 5173 as_bad (_("bad register name `%s'"), base_string);
24eab124 5174 return 0;
c3332e24 5175 }
24eab124
AM		 5176 }
5177
5178 /* If there's an expression beginning the operand, parse it,
5179 assuming displacement_string_start and
5180 displacement_string_end are meaningful. */
5181 if (displacement_string_start != displacement_string_end)
5182 {
5183 if (!i386_displacement (displacement_string_start,
5184 displacement_string_end))
5185 return 0;
5186 }
5187
5188 /* Special case for (%dx) while doing input/output op. */
5189 if (i.base_reg
5190 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5191 && i.index_reg == 0
5192 && i.log2_scale_factor == 0
5193 && i.seg[i.mem_operands] == 0
5194 && (i.types[this_operand] & Disp) == 0)
5195 {
5196 i.types[this_operand] = InOutPortReg;
5197 return 1;
5198 }
5199
eecb386c
AM		 5200 if (i386_index_check (operand_string) == 0)
5201 return 0;
24eab124
AM		 5202 i.mem_operands++;
5203 }
5204 else
ce8a8b2f
AM		 5205 {
5206 /* It's not a memory operand; argh! */
24eab124
AM		 5207 as_bad (_("invalid char %s beginning operand %d `%s'"),
5208 output_invalid (*op_string),
5209 this_operand + 1,
5210 op_string);
5211 return 0;
5212 }
47926f60 5213 return 1; /* Normal return. */
252b5132
RH		 5214}
5215\f
ee7fcc42
AM		 5216/* md_estimate_size_before_relax()
5217
5218 Called just before relax() for rs_machine_dependent frags. The x86
5219 assembler uses these frags to handle variable size jump
5220 instructions.
5221
5222 Any symbol that is now undefined will not become defined.
5223 Return the correct fr_subtype in the frag.
5224 Return the initial "guess for variable size of frag" to caller.
5225 The guess is actually the growth beyond the fixed part. Whatever
5226 we do to grow the fixed or variable part contributes to our
5227 returned value. */
5228
252b5132
RH		 5229int
5230md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5231 fragS *fragP;
5232 segT segment;
252b5132 5233{
252b5132 5234 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5235 check for un-relaxable symbols. On an ELF system, we can't relax
5236 an externally visible symbol, because it may be overridden by a
5237 shared library. */
5238 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5239#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5240 || (IS_ELF
31312f95
AM		 5241 && (S_IS_EXTERNAL (fragP->fr_symbol)
5242 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5243#endif
5244 )
252b5132 5245 {
b98ef147
AM		 5246 /* Symbol is undefined in this segment, or we need to keep a
5247 reloc so that weak symbols can be overridden. */
5248 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5249 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5250 unsigned char *opcode;
5251 int old_fr_fix;
f6af82bd 5252
ee7fcc42
AM		 5253 if (fragP->fr_var != NO_RELOC)
5254 reloc_type = fragP->fr_var;
b98ef147 5255 else if (size == 2)
f6af82bd
AM		 5256 reloc_type = BFD_RELOC_16_PCREL;
5257 else
5258 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5259
ee7fcc42
AM		 5260 old_fr_fix = fragP->fr_fix;
5261 opcode = (unsigned char *) fragP->fr_opcode;
5262
fddf5b5b 5263 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5264 {
fddf5b5b
AM		 5265 case UNCOND_JUMP:
5266 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5267 opcode[0] = 0xe9;
252b5132 5268 fragP->fr_fix += size;
062cd5e7
AS		 5269 fix_new (fragP, old_fr_fix, size,
5270 fragP->fr_symbol,
5271 fragP->fr_offset, 1,
5272 reloc_type);
252b5132
RH		 5273 break;
5274
fddf5b5b 5275 case COND_JUMP86:
412167cb
AM		 5276 if (size == 2
5277 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5278 {
5279 /* Negate the condition, and branch past an
5280 unconditional jump. */
5281 opcode[0] ^= 1;
5282 opcode[1] = 3;
5283 /* Insert an unconditional jump. */
5284 opcode[2] = 0xe9;
5285 /* We added two extra opcode bytes, and have a two byte
5286 offset. */
5287 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5288 fix_new (fragP, old_fr_fix + 2, 2,
5289 fragP->fr_symbol,
5290 fragP->fr_offset, 1,
5291 reloc_type);
fddf5b5b
AM		 5292 break;
5293 }
5294 /* Fall through. */
5295
5296 case COND_JUMP:
412167cb
AM		 5297 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5298 {
3e02c1cc
AM		 5299 fixS *fixP;
5300
412167cb 5301 fragP->fr_fix += 1;
3e02c1cc
AM		 5302 fixP = fix_new (fragP, old_fr_fix, 1,
5303 fragP->fr_symbol,
5304 fragP->fr_offset, 1,
5305 BFD_RELOC_8_PCREL);
5306 fixP->fx_signed = 1;
412167cb
AM		 5307 break;
5308 }
93c2a809 5309
24eab124 5310 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5311 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5312 opcode[1] = opcode[0] + 0x10;
f6af82bd 5313 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5314 /* We've added an opcode byte. */
5315 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5316 fix_new (fragP, old_fr_fix + 1, size,
5317 fragP->fr_symbol,
5318 fragP->fr_offset, 1,
5319 reloc_type);
252b5132 5320 break;
fddf5b5b
AM		 5321
5322 default:
5323 BAD_CASE (fragP->fr_subtype);
5324 break;
252b5132
RH		 5325 }
5326 frag_wane (fragP);
ee7fcc42 5327 return fragP->fr_fix - old_fr_fix;
252b5132 5328 }
93c2a809 5329
93c2a809
AM		 5330 /* Guess size depending on current relax state. Initially the relax
5331 state will correspond to a short jump and we return 1, because
5332 the variable part of the frag (the branch offset) is one byte
5333 long. However, we can relax a section more than once and in that
5334 case we must either set fr_subtype back to the unrelaxed state,
5335 or return the value for the appropriate branch. */
5336 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5337}
5338
47926f60
KH		 5339/* Called after relax() is finished.
5340
5341 In: Address of frag.
5342 fr_type == rs_machine_dependent.
5343 fr_subtype is what the address relaxed to.
5344
5345 Out: Any fixSs and constants are set up.
5346 Caller will turn frag into a ".space 0". */
5347
252b5132
RH		 5348void
5349md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5350 bfd *abfd ATTRIBUTE_UNUSED;
5351 segT sec ATTRIBUTE_UNUSED;
29b0f896 5352 fragS *fragP;
252b5132 5353{
29b0f896 5354 unsigned char *opcode;
252b5132 5355 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5356 offsetT target_address;
5357 offsetT opcode_address;
252b5132 5358 unsigned int extension = 0;
847f7ad4 5359 offsetT displacement_from_opcode_start;
252b5132
RH		 5360
5361 opcode = (unsigned char *) fragP->fr_opcode;
5362
47926f60 5363 /* Address we want to reach in file space. */
252b5132 5364 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5365
47926f60 5366 /* Address opcode resides at in file space. */
252b5132
RH		 5367 opcode_address = fragP->fr_address + fragP->fr_fix;
5368
47926f60 5369 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5370 displacement_from_opcode_start = target_address - opcode_address;
5371
fddf5b5b 5372 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5373 {
47926f60
KH		 5374 /* Don't have to change opcode. */
5375 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5376 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5377 }
5378 else
5379 {
5380 if (no_cond_jump_promotion
5381 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5382 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5383
fddf5b5b
AM		 5384 switch (fragP->fr_subtype)
5385 {
5386 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5387 extension = 4; /* 1 opcode + 4 displacement */
5388 opcode[0] = 0xe9;
5389 where_to_put_displacement = &opcode[1];
5390 break;
252b5132 5391
fddf5b5b
AM		 5392 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5393 extension = 2; /* 1 opcode + 2 displacement */
5394 opcode[0] = 0xe9;
5395 where_to_put_displacement = &opcode[1];
5396 break;
252b5132 5397
fddf5b5b
AM		 5398 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5399 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5400 extension = 5; /* 2 opcode + 4 displacement */
5401 opcode[1] = opcode[0] + 0x10;
5402 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5403 where_to_put_displacement = &opcode[2];
5404 break;
252b5132 5405
fddf5b5b
AM		 5406 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5407 extension = 3; /* 2 opcode + 2 displacement */
5408 opcode[1] = opcode[0] + 0x10;
5409 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5410 where_to_put_displacement = &opcode[2];
5411 break;
252b5132 5412
fddf5b5b
AM		 5413 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5414 extension = 4;
5415 opcode[0] ^= 1;
5416 opcode[1] = 3;
5417 opcode[2] = 0xe9;
5418 where_to_put_displacement = &opcode[3];
5419 break;
5420
5421 default:
5422 BAD_CASE (fragP->fr_subtype);
5423 break;
5424 }
252b5132 5425 }
fddf5b5b 5426
7b81dfbb
AJ		 5427 /* If size if less then four we are sure that the operand fits,
5428 but if it's 4, then it could be that the displacement is larger
5429 then -/+ 2GB. */
5430 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5431 && object_64bit
5432 && ((addressT) (displacement_from_opcode_start - extension
5433 + ((addressT) 1 << 31))
5434 > (((addressT) 2 << 31) - 1)))
5435 {
5436 as_bad_where (fragP->fr_file, fragP->fr_line,
5437 _("jump target out of range"));
5438 /* Make us emit 0. */
5439 displacement_from_opcode_start = extension;
5440 }
47926f60 5441 /* Now put displacement after opcode. */
252b5132
RH		 5442 md_number_to_chars ((char *) where_to_put_displacement,
5443 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5444 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5445 fragP->fr_fix += extension;
5446}
5447\f
47926f60
KH		 5448/* Size of byte displacement jmp. */
5449int md_short_jump_size = 2;
5450
5451/* Size of dword displacement jmp. */
5452int md_long_jump_size = 5;
252b5132 5453
252b5132
RH		 5454void
5455md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5456 char *ptr;
5457 addressT from_addr, to_addr;
ab9da554
ILT		 5458 fragS *frag ATTRIBUTE_UNUSED;
5459 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5460{
847f7ad4 5461 offsetT offset;
252b5132
RH		 5462
5463 offset = to_addr - (from_addr + 2);
47926f60
KH		 5464 /* Opcode for byte-disp jump. */
5465 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5466 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5467}
5468
5469void
5470md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5471 char *ptr;
5472 addressT from_addr, to_addr;
a38cf1db
AM		 5473 fragS *frag ATTRIBUTE_UNUSED;
5474 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5475{
847f7ad4 5476 offsetT offset;
252b5132 5477
a38cf1db
AM		 5478 offset = to_addr - (from_addr + 5);
5479 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5480 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5481}
5482\f
5483/* Apply a fixup (fixS) to segment data, once it has been determined
5484 by our caller that we have all the info we need to fix it up.
5485
5486 On the 386, immediates, displacements, and data pointers are all in
5487 the same (little-endian) format, so we don't need to care about which
5488 we are handling. */
5489
94f592af 5490void
55cf6793 5491md_apply_fix (fixP, valP, seg)
47926f60
KH		 5492 /* The fix we're to put in. */
5493 fixS *fixP;
47926f60 5494 /* Pointer to the value of the bits. */
c6682705 5495 valueT *valP;
47926f60
KH		 5496 /* Segment fix is from. */
5497 segT seg ATTRIBUTE_UNUSED;
252b5132 5498{
94f592af 5499 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5500 valueT value = *valP;
252b5132 5501
f86103b7 5502#if !defined (TE_Mach)
93382f6d
AM		 5503 if (fixP->fx_pcrel)
5504 {
5505 switch (fixP->fx_r_type)
5506 {
5865bb77
ILT		 5507 default:
5508 break;
5509
d6ab8113
JB		 5510 case BFD_RELOC_64:
5511 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5512 break;
93382f6d 5513 case BFD_RELOC_32:
ae8887b5 5514 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5515 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5516 break;
5517 case BFD_RELOC_16:
5518 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5519 break;
5520 case BFD_RELOC_8:
5521 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5522 break;
5523 }
5524 }
252b5132 5525
a161fe53 5526 if (fixP->fx_addsy != NULL
31312f95 5527 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5528 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5529 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5530 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5531 && !use_rela_relocations)
252b5132 5532 {
31312f95
AM		 5533 /* This is a hack. There should be a better way to handle this.
5534 This covers for the fact that bfd_install_relocation will
5535 subtract the current location (for partial_inplace, PC relative
5536 relocations); see more below. */
252b5132 5537#ifndef OBJ_AOUT
718ddfc0 5538 if (IS_ELF
252b5132
RH		 5539#ifdef TE_PE
5540 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5541#endif
5542 )
5543 value += fixP->fx_where + fixP->fx_frag->fr_address;
5544#endif
5545#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5546 if (IS_ELF)
252b5132 5547 {
6539b54b 5548 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5549
6539b54b 5550 if ((sym_seg == seg
2f66722d 5551 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5552 && sym_seg != absolute_section))
ae6063d4 5553 && !generic_force_reloc (fixP))
2f66722d
AM		 5554 {
5555 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5556 bfd_install_relocation subtracts them out again. I think
5557 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5558 it. FIXME. */
5559 value += fixP->fx_where + fixP->fx_frag->fr_address;
5560 }
252b5132
RH		 5561 }
5562#endif
5563#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5564 /* For some reason, the PE format does not store a
5565 section address offset for a PC relative symbol. */
5566 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5567 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5568 value += md_pcrel_from (fixP);
5569#endif
5570 }
5571
5572 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5573 and we must not disappoint it. */
252b5132 5574#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5575 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5576 switch (fixP->fx_r_type)
5577 {
5578 case BFD_RELOC_386_PLT32:
3e73aa7c 5579 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5580 /* Make the jump instruction point to the address of the operand. At
5581 runtime we merely add the offset to the actual PLT entry. */
5582 value = -4;
5583 break;
31312f95 5584
13ae64f3
JJ		 5585 case BFD_RELOC_386_TLS_GD:
5586 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5587 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5588 case BFD_RELOC_386_TLS_IE:
5589 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5590 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5591 case BFD_RELOC_X86_64_TLSGD:
5592 case BFD_RELOC_X86_64_TLSLD:
5593 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5594 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5595 value = 0; /* Fully resolved at runtime. No addend. */
5596 /* Fallthrough */
5597 case BFD_RELOC_386_TLS_LE:
5598 case BFD_RELOC_386_TLS_LDO_32:
5599 case BFD_RELOC_386_TLS_LE_32:
5600 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5601 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5602 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5603 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5604 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5605 break;
5606
67a4f2b7
AO		 5607 case BFD_RELOC_386_TLS_DESC_CALL:
5608 case BFD_RELOC_X86_64_TLSDESC_CALL:
5609 value = 0; /* Fully resolved at runtime. No addend. */
5610 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5611 fixP->fx_done = 0;
5612 return;
5613
00f7efb6
JJ		 5614 case BFD_RELOC_386_GOT32:
5615 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5616 value = 0; /* Fully resolved at runtime. No addend. */
5617 break;
47926f60
KH		 5618
5619 case BFD_RELOC_VTABLE_INHERIT:
5620 case BFD_RELOC_VTABLE_ENTRY:
5621 fixP->fx_done = 0;
94f592af 5622 return;
47926f60
KH		 5623
5624 default:
5625 break;
5626 }
5627#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5628 *valP = value;
f86103b7 5629#endif /* !defined (TE_Mach) */
3e73aa7c 5630
3e73aa7c 5631 /* Are we finished with this relocation now? */
c6682705 5632 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5633 fixP->fx_done = 1;
5634 else if (use_rela_relocations)
5635 {
5636 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5637 /* Remember value for tc_gen_reloc. */
5638 fixP->fx_addnumber = value;
3e73aa7c
JH		 5639 value = 0;
5640 }
f86103b7 5641
94f592af 5642 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5643}
252b5132 5644\f
252b5132
RH		 5645#define MAX_LITTLENUMS 6
5646
47926f60
KH		 5647/* Turn the string pointed to by litP into a floating point constant
5648 of type TYPE, and emit the appropriate bytes. The number of
5649 LITTLENUMS emitted is stored in *SIZEP. An error message is
5650 returned, or NULL on OK. */
5651
252b5132
RH		 5652char *
5653md_atof (type, litP, sizeP)
2ab9b79e 5654 int type;
252b5132
RH		 5655 char *litP;
5656 int *sizeP;
5657{
5658 int prec;
5659 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5660 LITTLENUM_TYPE *wordP;
5661 char *t;
5662
5663 switch (type)
5664 {
5665 case 'f':
5666 case 'F':
5667 prec = 2;
5668 break;
5669
5670 case 'd':
5671 case 'D':
5672 prec = 4;
5673 break;
5674
5675 case 'x':
5676 case 'X':
5677 prec = 5;
5678 break;
5679
5680 default:
5681 *sizeP = 0;
5682 return _("Bad call to md_atof ()");
5683 }
5684 t = atof_ieee (input_line_pointer, type, words);
5685 if (t)
5686 input_line_pointer = t;
5687
5688 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5689 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5690 the bigendian 386. */
5691 for (wordP = words + prec - 1; prec--;)
5692 {
5693 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5694 litP += sizeof (LITTLENUM_TYPE);
5695 }
5696 return 0;
5697}
5698\f
2d545b82 5699static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5700
252b5132
RH		 5701static char *
5702output_invalid (c)
5703 int c;
5704{
3882b010 5705 if (ISPRINT (c))
f9f21a03
L		 5706 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5707 "'%c'", c);
252b5132 5708 else
f9f21a03 5709 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5710 "(0x%x)", (unsigned char) c);
252b5132
RH		 5711 return output_invalid_buf;
5712}
5713
af6bdddf 5714/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5715
5716static const reg_entry *
4d1bb795 5717parse_real_register (char *reg_string, char **end_op)
252b5132 5718{
af6bdddf
AM		 5719 char *s = reg_string;
5720 char *p;
252b5132
RH		 5721 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5722 const reg_entry *r;
5723
5724 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5725 if (*s == REGISTER_PREFIX)
5726 ++s;
5727
5728 if (is_space_char (*s))
5729 ++s;
5730
5731 p = reg_name_given;
af6bdddf 5732 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5733 {
5734 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5735 return (const reg_entry *) NULL;
5736 s++;
252b5132
RH		 5737 }
5738
6588847e
DN		 5739 /* For naked regs, make sure that we are not dealing with an identifier.
5740 This prevents confusing an identifier like `eax_var' with register
5741 `eax'. */
5742 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5743 return (const reg_entry *) NULL;
5744
af6bdddf 5745 *end_op = s;
252b5132
RH		 5746
5747 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5748
5f47d35b 5749 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5750 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5751 {
5f47d35b
AM		 5752 if (is_space_char (*s))
5753 ++s;
5754 if (*s == '(')
5755 {
af6bdddf 5756 ++s;
5f47d35b
AM		 5757 if (is_space_char (*s))
5758 ++s;
5759 if (*s >= '0' && *s <= '7')
5760 {
5761 r = &i386_float_regtab[*s - '0'];
af6bdddf 5762 ++s;
5f47d35b
AM		 5763 if (is_space_char (*s))
5764 ++s;
5765 if (*s == ')')
5766 {
5767 *end_op = s + 1;
5768 return r;
5769 }
5f47d35b 5770 }
47926f60 5771 /* We have "%st(" then garbage. */
5f47d35b
AM		 5772 return (const reg_entry *) NULL;
5773 }
5774 }
5775
1ae00879 5776 if (r != NULL
20f0a1fc 5777 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5778 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5779 && flag_code != CODE_64BIT)
20f0a1fc 5780 return (const reg_entry *) NULL;
1ae00879 5781
252b5132
RH		 5782 return r;
5783}
4d1bb795
JB		 5784
5785/* REG_STRING starts *before* REGISTER_PREFIX. */
5786
5787static const reg_entry *
5788parse_register (char *reg_string, char **end_op)
5789{
5790 const reg_entry *r;
5791
5792 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5793 r = parse_real_register (reg_string, end_op);
5794 else
5795 r = NULL;
5796 if (!r)
5797 {
5798 char *save = input_line_pointer;
5799 char c;
5800 symbolS *symbolP;
5801
5802 input_line_pointer = reg_string;
5803 c = get_symbol_end ();
5804 symbolP = symbol_find (reg_string);
5805 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5806 {
5807 const expressionS *e = symbol_get_value_expression (symbolP);
5808
5809 know (e->X_op == O_register);
5810 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5811 r = i386_regtab + e->X_add_number;
5812 *end_op = input_line_pointer;
5813 }
5814 *input_line_pointer = c;
5815 input_line_pointer = save;
5816 }
5817 return r;
5818}
5819
5820int
5821i386_parse_name (char *name, expressionS *e, char *nextcharP)
5822{
5823 const reg_entry *r;
5824 char *end = input_line_pointer;
5825
5826 *end = *nextcharP;
5827 r = parse_register (name, &input_line_pointer);
5828 if (r && end <= input_line_pointer)
5829 {
5830 *nextcharP = *input_line_pointer;
5831 *input_line_pointer = 0;
5832 e->X_op = O_register;
5833 e->X_add_number = r - i386_regtab;
5834 return 1;
5835 }
5836 input_line_pointer = end;
5837 *end = 0;
5838 return 0;
5839}
5840
5841void
5842md_operand (expressionS *e)
5843{
5844 if (*input_line_pointer == REGISTER_PREFIX)
5845 {
5846 char *end;
5847 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5848
5849 if (r)
5850 {
5851 e->X_op = O_register;
5852 e->X_add_number = r - i386_regtab;
5853 input_line_pointer = end;
5854 }
5855 }
5856}
5857
252b5132 5858\f
4cc782b5 5859#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5860const char *md_shortopts = "kVQ:sqn";
252b5132 5861#else
12b55ccc 5862const char *md_shortopts = "qn";
252b5132 5863#endif
6e0b89ee 5864
3e73aa7c 5865#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5866#define OPTION_64 (OPTION_MD_BASE + 1)
5867#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5868#define OPTION_MARCH (OPTION_MD_BASE + 3)
5869#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5870
99ad8390
NC		 5871struct option md_longopts[] =
5872{
3e73aa7c 5873 {"32", no_argument, NULL, OPTION_32},
99ad8390 5874#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5875 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5876#endif
b3b91714 5877 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5878 {"march", required_argument, NULL, OPTION_MARCH},
5879 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5880 {NULL, no_argument, NULL, 0}
5881};
5882size_t md_longopts_size = sizeof (md_longopts);
5883
5884int
9103f4f4 5885md_parse_option (int c, char *arg)
252b5132 5886{
9103f4f4
L		 5887 unsigned int i;
5888
252b5132
RH		 5889 switch (c)
5890 {
12b55ccc
L		 5891 case 'n':
5892 optimize_align_code = 0;
5893 break;
5894
a38cf1db
AM		 5895 case 'q':
5896 quiet_warnings = 1;
252b5132
RH		 5897 break;
5898
5899#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5900 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5901 should be emitted or not. FIXME: Not implemented. */
5902 case 'Q':
252b5132
RH		 5903 break;
5904
5905 /* -V: SVR4 argument to print version ID. */
5906 case 'V':
5907 print_version_id ();
5908 break;
5909
a38cf1db
AM		 5910 /* -k: Ignore for FreeBSD compatibility. */
5911 case 'k':
252b5132 5912 break;
4cc782b5
ILT		 5913
5914 case 's':
5915 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5916 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5917 break;
99ad8390
NC		 5918#endif
5919#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5920 case OPTION_64:
5921 {
5922 const char **list, **l;
5923
3e73aa7c
JH		 5924 list = bfd_target_list ();
5925 for (l = list; *l != NULL; l++)
8620418b 5926 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5927 || strcmp (*l, "coff-x86-64") == 0
5928 || strcmp (*l, "pe-x86-64") == 0
5929 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5930 {
5931 default_arch = "x86_64";
5932 break;
5933 }
3e73aa7c 5934 if (*l == NULL)
6e0b89ee 5935 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5936 free (list);
5937 }
5938 break;
5939#endif
252b5132 5940
6e0b89ee
AM		 5941 case OPTION_32:
5942 default_arch = "i386";
5943 break;
5944
b3b91714
AM		 5945 case OPTION_DIVIDE:
5946#ifdef SVR4_COMMENT_CHARS
5947 {
5948 char *n, *t;
5949 const char *s;
5950
5951 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5952 t = n;
5953 for (s = i386_comment_chars; *s != '\0'; s++)
5954 if (*s != '/')
5955 *t++ = *s;
5956 *t = '\0';
5957 i386_comment_chars = n;
5958 }
5959#endif
5960 break;
5961
9103f4f4
L		 5962 case OPTION_MARCH:
5963 if (*arg == '.')
5964 as_fatal (_("Invalid -march= option: `%s'"), arg);
5965 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5966 {
5967 if (strcmp (arg, cpu_arch [i].name) == 0)
5968 {
ccc9c027 5969 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5970 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5971 if (!cpu_arch_tune_set)
5972 {
5973 cpu_arch_tune = cpu_arch_isa;
5974 cpu_arch_tune_flags = cpu_arch_isa_flags;
5975 }
9103f4f4
L		 5976 break;
5977 }
5978 }
5979 if (i >= ARRAY_SIZE (cpu_arch))
5980 as_fatal (_("Invalid -march= option: `%s'"), arg);
5981 break;
5982
5983 case OPTION_MTUNE:
5984 if (*arg == '.')
5985 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5986 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5987 {
5988 if (strcmp (arg, cpu_arch [i].name) == 0)
5989 {
ccc9c027 5990 cpu_arch_tune_set = 1;
9103f4f4
L		 5991 cpu_arch_tune = cpu_arch [i].type;
5992 cpu_arch_tune_flags = cpu_arch[i].flags;
5993 break;
5994 }
5995 }
5996 if (i >= ARRAY_SIZE (cpu_arch))
5997 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5998 break;
5999
252b5132
RH		 6000 default:
6001 return 0;
6002 }
6003 return 1;
6004}
6005
6006void
6007md_show_usage (stream)
6008 FILE *stream;
6009{
4cc782b5
ILT		 6010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6011 fprintf (stream, _("\
a38cf1db
AM		 6012 -Q ignored\n\
6013 -V print assembler version number\n\
b3b91714
AM		 6014 -k ignored\n"));
6015#endif
6016 fprintf (stream, _("\
12b55ccc 6017 -n Do not optimize code alignment\n\
b3b91714
AM		 6018 -q quieten some warnings\n"));
6019#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6020 fprintf (stream, _("\
a38cf1db 6021 -s ignored\n"));
b3b91714
AM		 6022#endif
6023#ifdef SVR4_COMMENT_CHARS
6024 fprintf (stream, _("\
6025 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6026#else
6027 fprintf (stream, _("\
b3b91714 6028 --divide ignored\n"));
4cc782b5 6029#endif
9103f4f4
L		 6030 fprintf (stream, _("\
6031 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6032 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
ef05d495 6033 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6034
252b5132
RH		 6035}
6036
99ad8390
NC		 6037#if defined(TE_PEP)
6038const char *
6039x86_64_target_format (void)
6040{
6041 if (strcmp (default_arch, "x86_64") == 0)
6042 {
6043 set_code_flag (CODE_64BIT);
6044 return COFF_TARGET_FORMAT;
6045 }
6046 else if (strcmp (default_arch, "i386") == 0)
6047 {
6048 set_code_flag (CODE_32BIT);
6049 return "coff-i386";
6050 }
6051
6052 as_fatal (_("Unknown architecture"));
6053 return NULL;
6054}
6055#endif
6056
3e73aa7c
JH		 6057#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6058 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6059
6060/* Pick the target format to use. */
6061
47926f60 6062const char *
252b5132
RH		 6063i386_target_format ()
6064{
3e73aa7c 6065 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6066 {
6067 set_code_flag (CODE_64BIT);
6068 if (cpu_arch_isa_flags == 0)
d32cad65 6069 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6070 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6071 |CpuSSE|CpuSSE2;
ccc9c027 6072 if (cpu_arch_tune_flags == 0)
d32cad65 6073 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6074 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6075 |CpuSSE|CpuSSE2;
9103f4f4 6076 }
3e73aa7c 6077 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6078 {
6079 set_code_flag (CODE_32BIT);
6080 if (cpu_arch_isa_flags == 0)
d32cad65 6081 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6082 if (cpu_arch_tune_flags == 0)
d32cad65 6083 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6084 }
3e73aa7c
JH		 6085 else
6086 as_fatal (_("Unknown architecture"));
252b5132
RH		 6087 switch (OUTPUT_FLAVOR)
6088 {
4c63da97
AM		 6089#ifdef OBJ_MAYBE_AOUT
6090 case bfd_target_aout_flavour:
47926f60 6091 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6092#endif
6093#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6094 case bfd_target_coff_flavour:
6095 return "coff-i386";
4c63da97 6096#endif
3e73aa7c 6097#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6098 case bfd_target_elf_flavour:
3e73aa7c 6099 {
e5cb08ac 6100 if (flag_code == CODE_64BIT)
4fa24527
JB		 6101 {
6102 object_64bit = 1;
6103 use_rela_relocations = 1;
6104 }
9d7cbccd 6105 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6106 }
4c63da97 6107#endif
252b5132
RH		 6108 default:
6109 abort ();
6110 return NULL;
6111 }
6112}
6113
47926f60 6114#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6115
6116#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6117void i386_elf_emit_arch_note ()
6118{
718ddfc0 6119 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6120 {
6121 char *p;
6122 asection *seg = now_seg;
6123 subsegT subseg = now_subseg;
6124 Elf_Internal_Note i_note;
6125 Elf_External_Note e_note;
6126 asection *note_secp;
6127 int len;
6128
6129 /* Create the .note section. */
6130 note_secp = subseg_new (".note", 0);
6131 bfd_set_section_flags (stdoutput,
6132 note_secp,
6133 SEC_HAS_CONTENTS | SEC_READONLY);
6134
6135 /* Process the arch string. */
6136 len = strlen (cpu_arch_name);
6137
6138 i_note.namesz = len + 1;
6139 i_note.descsz = 0;
6140 i_note.type = NT_ARCH;
6141 p = frag_more (sizeof (e_note.namesz));
6142 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6143 p = frag_more (sizeof (e_note.descsz));
6144 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6145 p = frag_more (sizeof (e_note.type));
6146 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6147 p = frag_more (len + 1);
6148 strcpy (p, cpu_arch_name);
6149
6150 frag_align (2, 0, 0);
6151
6152 subseg_set (seg, subseg);
6153 }
6154}
6155#endif
252b5132 6156\f
252b5132
RH		 6157symbolS *
6158md_undefined_symbol (name)
6159 char *name;
6160{
18dc2407
ILT		 6161 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6162 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6163 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6164 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6165 {
6166 if (!GOT_symbol)
6167 {
6168 if (symbol_find (name))
6169 as_bad (_("GOT already in symbol table"));
6170 GOT_symbol = symbol_new (name, undefined_section,
6171 (valueT) 0, &zero_address_frag);
6172 };
6173 return GOT_symbol;
6174 }
252b5132
RH		 6175 return 0;
6176}
6177
6178/* Round up a section size to the appropriate boundary. */
47926f60 6179
252b5132
RH		 6180valueT
6181md_section_align (segment, size)
ab9da554 6182 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6183 valueT size;
6184{
4c63da97
AM		 6185#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6186 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6187 {
6188 /* For a.out, force the section size to be aligned. If we don't do
6189 this, BFD will align it for us, but it will not write out the
6190 final bytes of the section. This may be a bug in BFD, but it is
6191 easier to fix it here since that is how the other a.out targets
6192 work. */
6193 int align;
6194
6195 align = bfd_get_section_alignment (stdoutput, segment);
6196 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6197 }
252b5132
RH		 6198#endif
6199
6200 return size;
6201}
6202
6203/* On the i386, PC-relative offsets are relative to the start of the
6204 next instruction. That is, the address of the offset, plus its
6205 size, since the offset is always the last part of the insn. */
6206
6207long
6208md_pcrel_from (fixP)
6209 fixS *fixP;
6210{
6211 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6212}
6213
6214#ifndef I386COFF
6215
6216static void
6217s_bss (ignore)
ab9da554 6218 int ignore ATTRIBUTE_UNUSED;
252b5132 6219{
29b0f896 6220 int temp;
252b5132 6221
8a75718c
JB		 6222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6223 if (IS_ELF)
6224 obj_elf_section_change_hook ();
6225#endif
252b5132
RH		 6226 temp = get_absolute_expression ();
6227 subseg_set (bss_section, (subsegT) temp);
6228 demand_empty_rest_of_line ();
6229}
6230
6231#endif
6232
252b5132
RH		 6233void
6234i386_validate_fix (fixp)
6235 fixS *fixp;
6236{
6237 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6238 {
23df1078
JH		 6239 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6240 {
4fa24527 6241 if (!object_64bit)
23df1078
JH		 6242 abort ();
6243 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6244 }
6245 else
6246 {
4fa24527 6247 if (!object_64bit)
d6ab8113
JB		 6248 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6249 else
6250 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6251 }
252b5132
RH		 6252 fixp->fx_subsy = 0;
6253 }
6254}
6255
252b5132
RH		 6256arelent *
6257tc_gen_reloc (section, fixp)
ab9da554 6258 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6259 fixS *fixp;
6260{
6261 arelent *rel;
6262 bfd_reloc_code_real_type code;
6263
6264 switch (fixp->fx_r_type)
6265 {
3e73aa7c
JH		 6266 case BFD_RELOC_X86_64_PLT32:
6267 case BFD_RELOC_X86_64_GOT32:
6268 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6269 case BFD_RELOC_386_PLT32:
6270 case BFD_RELOC_386_GOT32:
6271 case BFD_RELOC_386_GOTOFF:
6272 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6273 case BFD_RELOC_386_TLS_GD:
6274 case BFD_RELOC_386_TLS_LDM:
6275 case BFD_RELOC_386_TLS_LDO_32:
6276 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6277 case BFD_RELOC_386_TLS_IE:
6278 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6279 case BFD_RELOC_386_TLS_LE_32:
6280 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6281 case BFD_RELOC_386_TLS_GOTDESC:
6282 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6283 case BFD_RELOC_X86_64_TLSGD:
6284 case BFD_RELOC_X86_64_TLSLD:
6285 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6286 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6287 case BFD_RELOC_X86_64_GOTTPOFF:
6288 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6289 case BFD_RELOC_X86_64_TPOFF64:
6290 case BFD_RELOC_X86_64_GOTOFF64:
6291 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6292 case BFD_RELOC_X86_64_GOT64:
6293 case BFD_RELOC_X86_64_GOTPCREL64:
6294 case BFD_RELOC_X86_64_GOTPC64:
6295 case BFD_RELOC_X86_64_GOTPLT64:
6296 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6297 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6298 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6299 case BFD_RELOC_RVA:
6300 case BFD_RELOC_VTABLE_ENTRY:
6301 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6302#ifdef TE_PE
6303 case BFD_RELOC_32_SECREL:
6304#endif
252b5132
RH		 6305 code = fixp->fx_r_type;
6306 break;
dbbaec26
L		 6307 case BFD_RELOC_X86_64_32S:
6308 if (!fixp->fx_pcrel)
6309 {
6310 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6311 code = fixp->fx_r_type;
6312 break;
6313 }
252b5132 6314 default:
93382f6d 6315 if (fixp->fx_pcrel)
252b5132 6316 {
93382f6d
AM		 6317 switch (fixp->fx_size)
6318 {
6319 default:
b091f402
AM		 6320 as_bad_where (fixp->fx_file, fixp->fx_line,
6321 _("can not do %d byte pc-relative relocation"),
6322 fixp->fx_size);
93382f6d
AM		 6323 code = BFD_RELOC_32_PCREL;
6324 break;
6325 case 1: code = BFD_RELOC_8_PCREL; break;
6326 case 2: code = BFD_RELOC_16_PCREL; break;
6327 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6328#ifdef BFD64
6329 case 8: code = BFD_RELOC_64_PCREL; break;
6330#endif
93382f6d
AM		 6331 }
6332 }
6333 else
6334 {
6335 switch (fixp->fx_size)
6336 {
6337 default:
b091f402
AM		 6338 as_bad_where (fixp->fx_file, fixp->fx_line,
6339 _("can not do %d byte relocation"),
6340 fixp->fx_size);
93382f6d
AM		 6341 code = BFD_RELOC_32;
6342 break;
6343 case 1: code = BFD_RELOC_8; break;
6344 case 2: code = BFD_RELOC_16; break;
6345 case 4: code = BFD_RELOC_32; break;
937149dd 6346#ifdef BFD64
3e73aa7c 6347 case 8: code = BFD_RELOC_64; break;
937149dd 6348#endif
93382f6d 6349 }
252b5132
RH		 6350 }
6351 break;
6352 }
252b5132 6353
d182319b
JB		 6354 if ((code == BFD_RELOC_32
6355 || code == BFD_RELOC_32_PCREL
6356 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6357 && GOT_symbol
6358 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6359 {
4fa24527 6360 if (!object_64bit)
d6ab8113
JB		 6361 code = BFD_RELOC_386_GOTPC;
6362 else
6363 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6364 }
7b81dfbb
AJ		 6365 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6366 && GOT_symbol
6367 && fixp->fx_addsy == GOT_symbol)
6368 {
6369 code = BFD_RELOC_X86_64_GOTPC64;
6370 }
252b5132
RH		 6371
6372 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6373 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6374 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6375
6376 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6377
3e73aa7c
JH		 6378 if (!use_rela_relocations)
6379 {
6380 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6381 vtable entry to be used in the relocation's section offset. */
6382 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6383 rel->address = fixp->fx_offset;
252b5132 6384
c6682705 6385 rel->addend = 0;
3e73aa7c
JH		 6386 }
6387 /* Use the rela in 64bit mode. */
252b5132 6388 else
3e73aa7c 6389 {
062cd5e7
AS		 6390 if (!fixp->fx_pcrel)
6391 rel->addend = fixp->fx_offset;
6392 else
6393 switch (code)
6394 {
6395 case BFD_RELOC_X86_64_PLT32:
6396 case BFD_RELOC_X86_64_GOT32:
6397 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6398 case BFD_RELOC_X86_64_TLSGD:
6399 case BFD_RELOC_X86_64_TLSLD:
6400 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6401 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6402 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6403 rel->addend = fixp->fx_offset - fixp->fx_size;
6404 break;
6405 default:
6406 rel->addend = (section->vma
6407 - fixp->fx_size
6408 + fixp->fx_addnumber
6409 + md_pcrel_from (fixp));
6410 break;
6411 }
3e73aa7c
JH		 6412 }
6413
252b5132
RH		 6414 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6415 if (rel->howto == NULL)
6416 {
6417 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6418 _("cannot represent relocation type %s"),
252b5132
RH		 6419 bfd_get_reloc_code_name (code));
6420 /* Set howto to a garbage value so that we can keep going. */
6421 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6422 assert (rel->howto != NULL);
6423 }
6424
6425 return rel;
6426}
6427
64a0c779
DN		 6428\f
6429/* Parse operands using Intel syntax. This implements a recursive descent
6430 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6431 Programmer's Guide.
6432
6433 FIXME: We do not recognize the full operand grammar defined in the MASM
6434 documentation. In particular, all the structure/union and
6435 high-level macro operands are missing.
6436
6437 Uppercase words are terminals, lower case words are non-terminals.
6438 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6439 bars '|' denote choices. Most grammar productions are implemented in
6440 functions called 'intel_<production>'.
6441
6442 Initial production is 'expr'.
6443
9306ca4a 6444 addOp + | -
64a0c779
DN		 6445
6446 alpha [a-zA-Z]
6447
9306ca4a
JB		 6448 binOp & | AND | \| | OR | ^ | XOR
6449
64a0c779
DN		 6450 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6451
6452 constant digits [[ radixOverride ]]
6453
9306ca4a 6454 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6455
6456 digits decdigit
b77a7acd
AJ		 6457 | digits decdigit
6458 | digits hexdigit
64a0c779
DN		 6459
6460 decdigit [0-9]
6461
9306ca4a
JB		 6462 e04 e04 addOp e05
6463 | e05
6464
6465 e05 e05 binOp e06
b77a7acd 6466 | e06
64a0c779
DN		 6467
6468 e06 e06 mulOp e09
b77a7acd 6469 | e09
64a0c779
DN		 6470
6471 e09 OFFSET e10
a724f0f4
JB		 6472 | SHORT e10
6473 | + e10
6474 | - e10
9306ca4a
JB		 6475 | ~ e10
6476 | NOT e10
64a0c779
DN		 6477 | e09 PTR e10
6478 | e09 : e10
6479 | e10
6480
6481 e10 e10 [ expr ]
b77a7acd 6482 | e11
64a0c779
DN		 6483
6484 e11 ( expr )
b77a7acd 6485 | [ expr ]
64a0c779
DN		 6486 | constant
6487 | dataType
6488 | id
6489 | $
6490 | register
6491
a724f0f4 6492 => expr expr cmpOp e04
9306ca4a 6493 | e04
64a0c779
DN		 6494
6495 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6496 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6497
6498 hexdigit a | b | c | d | e | f
b77a7acd 6499 | A | B | C | D | E | F
64a0c779
DN		 6500
6501 id alpha
b77a7acd 6502 | id alpha
64a0c779
DN		 6503 | id decdigit
6504
9306ca4a 6505 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6506
6507 quote " | '
6508
6509 register specialRegister
b77a7acd 6510 | gpRegister
64a0c779
DN		 6511 | byteRegister
6512
6513 segmentRegister CS | DS | ES | FS | GS | SS
6514
9306ca4a 6515 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6516 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6517 | TR3 | TR4 | TR5 | TR6 | TR7
6518
64a0c779
DN		 6519 We simplify the grammar in obvious places (e.g., register parsing is
6520 done by calling parse_register) and eliminate immediate left recursion
6521 to implement a recursive-descent parser.
6522
a724f0f4
JB		 6523 expr e04 expr'
6524
6525 expr' cmpOp e04 expr'
6526 | Empty
9306ca4a
JB		 6527
6528 e04 e05 e04'
6529
6530 e04' addOp e05 e04'
6531 | Empty
64a0c779
DN		 6532
6533 e05 e06 e05'
6534
9306ca4a 6535 e05' binOp e06 e05'
b77a7acd 6536 | Empty
64a0c779
DN		 6537
6538 e06 e09 e06'
6539
6540 e06' mulOp e09 e06'
b77a7acd 6541 | Empty
64a0c779
DN		 6542
6543 e09 OFFSET e10 e09'
a724f0f4
JB		 6544 | SHORT e10'
6545 | + e10'
6546 | - e10'
6547 | ~ e10'
6548 | NOT e10'
b77a7acd 6549 | e10 e09'
64a0c779
DN		 6550
6551 e09' PTR e10 e09'
b77a7acd 6552 | : e10 e09'
64a0c779
DN		 6553 | Empty
6554
6555 e10 e11 e10'
6556
6557 e10' [ expr ] e10'
b77a7acd 6558 | Empty
64a0c779
DN		 6559
6560 e11 ( expr )
b77a7acd 6561 | [ expr ]
64a0c779
DN		 6562 | BYTE
6563 | WORD
6564 | DWORD
9306ca4a 6565 | FWORD
64a0c779 6566 | QWORD
9306ca4a
JB		 6567 | TBYTE
6568 | OWORD
6569 | XMMWORD
64a0c779
DN		 6570 | .
6571 | $
6572 | register
6573 | id
6574 | constant */
6575
6576/* Parsing structure for the intel syntax parser. Used to implement the
6577 semantic actions for the operand grammar. */
6578struct intel_parser_s
6579 {
6580 char *op_string; /* The string being parsed. */
6581 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6582 int op_modifier; /* Operand modifier. */
64a0c779 6583 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6584 int in_offset; /* >=1 if parsing operand of offset. */
6585 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6586 const reg_entry *reg; /* Last register reference found. */
6587 char *disp; /* Displacement string being built. */
a724f0f4 6588 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6589 };
6590
6591static struct intel_parser_s intel_parser;
6592
6593/* Token structure for parsing intel syntax. */
6594struct intel_token
6595 {
6596 int code; /* Token code. */
6597 const reg_entry *reg; /* Register entry for register tokens. */
6598 char *str; /* String representation. */
6599 };
6600
6601static struct intel_token cur_token, prev_token;
6602
50705ef4
AM		 6603/* Token codes for the intel parser. Since T_SHORT is already used
6604 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6605#define T_NIL -1
6606#define T_CONST 1
6607#define T_REG 2
6608#define T_BYTE 3
6609#define T_WORD 4
9306ca4a
JB		 6610#define T_DWORD 5
6611#define T_FWORD 6
6612#define T_QWORD 7
6613#define T_TBYTE 8
6614#define T_XMMWORD 9
50705ef4 6615#undef T_SHORT
9306ca4a
JB		 6616#define T_SHORT 10
6617#define T_OFFSET 11
6618#define T_PTR 12
6619#define T_ID 13
6620#define T_SHL 14
6621#define T_SHR 15
64a0c779
DN		 6622
6623/* Prototypes for intel parser functions. */
6624static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6625static void intel_get_token PARAMS ((void));
6626static void intel_putback_token PARAMS ((void));
6627static int intel_expr PARAMS ((void));
9306ca4a 6628static int intel_e04 PARAMS ((void));
cce0cbdc 6629static int intel_e05 PARAMS ((void));
cce0cbdc 6630static int intel_e06 PARAMS ((void));
cce0cbdc 6631static int intel_e09 PARAMS ((void));
a724f0f4 6632static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6633static int intel_e10 PARAMS ((void));
cce0cbdc 6634static int intel_e11 PARAMS ((void));
64a0c779 6635
64a0c779
DN		 6636static int
6637i386_intel_operand (operand_string, got_a_float)
6638 char *operand_string;
6639 int got_a_float;
6640{
6641 int ret;
6642 char *p;
6643
a724f0f4
JB		 6644 p = intel_parser.op_string = xstrdup (operand_string);
6645 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6646
6647 for (;;)
64a0c779 6648 {
a724f0f4
JB		 6649 /* Initialize token holders. */
6650 cur_token.code = prev_token.code = T_NIL;
6651 cur_token.reg = prev_token.reg = NULL;
6652 cur_token.str = prev_token.str = NULL;
6653
6654 /* Initialize parser structure. */
6655 intel_parser.got_a_float = got_a_float;
6656 intel_parser.op_modifier = 0;
6657 intel_parser.is_mem = 0;
6658 intel_parser.in_offset = 0;
6659 intel_parser.in_bracket = 0;
6660 intel_parser.reg = NULL;
6661 intel_parser.disp[0] = '\0';
6662 intel_parser.next_operand = NULL;
6663
6664 /* Read the first token and start the parser. */
6665 intel_get_token ();
6666 ret = intel_expr ();
6667
6668 if (!ret)
6669 break;
6670
9306ca4a
JB		 6671 if (cur_token.code != T_NIL)
6672 {
6673 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6674 current_templates->start->name, cur_token.str);
6675 ret = 0;
6676 }
64a0c779
DN		 6677 /* If we found a memory reference, hand it over to i386_displacement
6678 to fill in the rest of the operand fields. */
9306ca4a 6679 else if (intel_parser.is_mem)
64a0c779
DN		 6680 {
6681 if ((i.mem_operands == 1
6682 && (current_templates->start->opcode_modifier & IsString) == 0)
6683 || i.mem_operands == 2)
6684 {
6685 as_bad (_("too many memory references for '%s'"),
6686 current_templates->start->name);
6687 ret = 0;
6688 }
6689 else
6690 {
6691 char *s = intel_parser.disp;
6692 i.mem_operands++;
6693
a724f0f4
JB		 6694 if (!quiet_warnings && intel_parser.is_mem < 0)
6695 /* See the comments in intel_bracket_expr. */
6696 as_warn (_("Treating `%s' as memory reference"), operand_string);
6697
64a0c779
DN		 6698 /* Add the displacement expression. */
6699 if (*s != '\0')
a4622f40
AM		 6700 ret = i386_displacement (s, s + strlen (s));
6701 if (ret)
a724f0f4
JB		 6702 {
6703 /* Swap base and index in 16-bit memory operands like
6704 [si+bx]. Since i386_index_check is also used in AT&T
6705 mode we have to do that here. */
6706 if (i.base_reg
6707 && i.index_reg
6708 && (i.base_reg->reg_type & Reg16)
6709 && (i.index_reg->reg_type & Reg16)
6710 && i.base_reg->reg_num >= 6
6711 && i.index_reg->reg_num < 6)
6712 {
6713 const reg_entry *base = i.index_reg;
6714
6715 i.index_reg = i.base_reg;
6716 i.base_reg = base;
6717 }
6718 ret = i386_index_check (operand_string);
6719 }
64a0c779
DN		 6720 }
6721 }
6722
6723 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6724 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6725 || intel_parser.reg == NULL)
6726 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6727
6728 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6729 ret = 0;
6730 if (!ret || !intel_parser.next_operand)
6731 break;
6732 intel_parser.op_string = intel_parser.next_operand;
6733 this_operand = i.operands++;
64a0c779
DN		 6734 }
6735
6736 free (p);
6737 free (intel_parser.disp);
6738
6739 return ret;
6740}
6741
a724f0f4
JB		 6742#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6743
6744/* expr e04 expr'
6745
6746 expr' cmpOp e04 expr'
6747 | Empty */
64a0c779
DN		 6748static int
6749intel_expr ()
6750{
a724f0f4
JB		 6751 /* XXX Implement the comparison operators. */
6752 return intel_e04 ();
9306ca4a
JB		 6753}
6754
a724f0f4 6755/* e04 e05 e04'
9306ca4a 6756
a724f0f4 6757 e04' addOp e05 e04'
9306ca4a
JB		 6758 | Empty */
6759static int
6760intel_e04 ()
6761{
a724f0f4 6762 int nregs = -1;
9306ca4a 6763
a724f0f4 6764 for (;;)
9306ca4a 6765 {
a724f0f4
JB		 6766 if (!intel_e05())
6767 return 0;
9306ca4a 6768
a724f0f4
JB		 6769 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6770 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6771
a724f0f4
JB		 6772 if (cur_token.code == '+')
6773 nregs = -1;
6774 else if (cur_token.code == '-')
6775 nregs = NUM_ADDRESS_REGS;
6776 else
6777 return 1;
64a0c779 6778
a724f0f4
JB		 6779 strcat (intel_parser.disp, cur_token.str);
6780 intel_match_token (cur_token.code);
6781 }
64a0c779
DN		 6782}
6783
64a0c779
DN		 6784/* e05 e06 e05'
6785
9306ca4a 6786 e05' binOp e06 e05'
64a0c779
DN		 6787 | Empty */
6788static int
6789intel_e05 ()
6790{
a724f0f4 6791 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6792
a724f0f4 6793 for (;;)
64a0c779 6794 {
a724f0f4
JB		 6795 if (!intel_e06())
6796 return 0;
6797
6798 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6799 {
6800 char str[2];
6801
6802 str[0] = cur_token.code;
6803 str[1] = 0;
6804 strcat (intel_parser.disp, str);
6805 }
6806 else
6807 break;
9306ca4a 6808
64a0c779
DN		 6809 intel_match_token (cur_token.code);
6810
a724f0f4
JB		 6811 if (nregs < 0)
6812 nregs = ~nregs;
64a0c779 6813 }
a724f0f4
JB		 6814 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6815 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6816 return 1;
4a1805b1 6817}
64a0c779
DN		 6818
6819/* e06 e09 e06'
6820
6821 e06' mulOp e09 e06'
b77a7acd 6822 | Empty */
64a0c779
DN		 6823static int
6824intel_e06 ()
6825{
a724f0f4 6826 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6827
a724f0f4 6828 for (;;)
64a0c779 6829 {
a724f0f4
JB		 6830 if (!intel_e09())
6831 return 0;
9306ca4a 6832
a724f0f4
JB		 6833 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6834 {
6835 char str[2];
9306ca4a 6836
a724f0f4
JB		 6837 str[0] = cur_token.code;
6838 str[1] = 0;
6839 strcat (intel_parser.disp, str);
6840 }
6841 else if (cur_token.code == T_SHL)
6842 strcat (intel_parser.disp, "<<");
6843 else if (cur_token.code == T_SHR)
6844 strcat (intel_parser.disp, ">>");
6845 else
6846 break;
9306ca4a 6847
64e74474 6848 intel_match_token (cur_token.code);
64a0c779 6849
a724f0f4
JB		 6850 if (nregs < 0)
6851 nregs = ~nregs;
64a0c779 6852 }
a724f0f4
JB		 6853 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6854 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6855 return 1;
64a0c779
DN		 6856}
6857
a724f0f4
JB		 6858/* e09 OFFSET e09
6859 | SHORT e09
6860 | + e09
6861 | - e09
6862 | ~ e09
6863 | NOT e09
9306ca4a
JB		 6864 | e10 e09'
6865
64a0c779 6866 e09' PTR e10 e09'
b77a7acd 6867 | : e10 e09'
64a0c779
DN		 6868 | Empty */
6869static int
6870intel_e09 ()
6871{
a724f0f4
JB		 6872 int nregs = ~NUM_ADDRESS_REGS;
6873 int in_offset = 0;
6874
6875 for (;;)
64a0c779 6876 {
a724f0f4
JB		 6877 /* Don't consume constants here. */
6878 if (cur_token.code == '+' || cur_token.code == '-')
6879 {
6880 /* Need to look one token ahead - if the next token
6881 is a constant, the current token is its sign. */
6882 int next_code;
6883
6884 intel_match_token (cur_token.code);
6885 next_code = cur_token.code;
6886 intel_putback_token ();
6887 if (next_code == T_CONST)
6888 break;
6889 }
6890
6891 /* e09 OFFSET e09 */
6892 if (cur_token.code == T_OFFSET)
6893 {
6894 if (!in_offset++)
6895 ++intel_parser.in_offset;
6896 }
6897
6898 /* e09 SHORT e09 */
6899 else if (cur_token.code == T_SHORT)
6900 intel_parser.op_modifier |= 1 << T_SHORT;
6901
6902 /* e09 + e09 */
6903 else if (cur_token.code == '+')
6904 strcat (intel_parser.disp, "+");
6905
6906 /* e09 - e09
6907 | ~ e09
6908 | NOT e09 */
6909 else if (cur_token.code == '-' || cur_token.code == '~')
6910 {
6911 char str[2];
64a0c779 6912
a724f0f4
JB		 6913 if (nregs < 0)
6914 nregs = ~nregs;
6915 str[0] = cur_token.code;
6916 str[1] = 0;
6917 strcat (intel_parser.disp, str);
6918 }
6919
6920 /* e09 e10 e09' */
6921 else
6922 break;
6923
6924 intel_match_token (cur_token.code);
64a0c779
DN		 6925 }
6926
a724f0f4 6927 for (;;)
9306ca4a 6928 {
a724f0f4
JB		 6929 if (!intel_e10 ())
6930 return 0;
9306ca4a 6931
a724f0f4
JB		 6932 /* e09' PTR e10 e09' */
6933 if (cur_token.code == T_PTR)
6934 {
6935 char suffix;
9306ca4a 6936
a724f0f4
JB		 6937 if (prev_token.code == T_BYTE)
6938 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6939
a724f0f4
JB		 6940 else if (prev_token.code == T_WORD)
6941 {
6942 if (current_templates->start->name[0] == 'l'
6943 && current_templates->start->name[2] == 's'
6944 && current_templates->start->name[3] == 0)
6945 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6946 else if (intel_parser.got_a_float == 2) /* "fi..." */
6947 suffix = SHORT_MNEM_SUFFIX;
6948 else
6949 suffix = WORD_MNEM_SUFFIX;
6950 }
64a0c779 6951
a724f0f4
JB		 6952 else if (prev_token.code == T_DWORD)
6953 {
6954 if (current_templates->start->name[0] == 'l'
6955 && current_templates->start->name[2] == 's'
6956 && current_templates->start->name[3] == 0)
6957 suffix = WORD_MNEM_SUFFIX;
6958 else if (flag_code == CODE_16BIT
6959 && (current_templates->start->opcode_modifier
435acd52 6960 & (Jump | JumpDword)))
a724f0f4
JB		 6961 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6962 else if (intel_parser.got_a_float == 1) /* "f..." */
6963 suffix = SHORT_MNEM_SUFFIX;
6964 else
6965 suffix = LONG_MNEM_SUFFIX;
6966 }
9306ca4a 6967
a724f0f4
JB		 6968 else if (prev_token.code == T_FWORD)
6969 {
6970 if (current_templates->start->name[0] == 'l'
6971 && current_templates->start->name[2] == 's'
6972 && current_templates->start->name[3] == 0)
6973 suffix = LONG_MNEM_SUFFIX;
6974 else if (!intel_parser.got_a_float)
6975 {
6976 if (flag_code == CODE_16BIT)
6977 add_prefix (DATA_PREFIX_OPCODE);
6978 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6979 }
6980 else
6981 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6982 }
64a0c779 6983
a724f0f4
JB		 6984 else if (prev_token.code == T_QWORD)
6985 {
6986 if (intel_parser.got_a_float == 1) /* "f..." */
6987 suffix = LONG_MNEM_SUFFIX;
6988 else
6989 suffix = QWORD_MNEM_SUFFIX;
6990 }
64a0c779 6991
a724f0f4
JB		 6992 else if (prev_token.code == T_TBYTE)
6993 {
6994 if (intel_parser.got_a_float == 1)
6995 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6996 else
6997 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6998 }
9306ca4a 6999
a724f0f4 7000 else if (prev_token.code == T_XMMWORD)
9306ca4a 7001 {
a724f0f4
JB		 7002 /* XXX ignored for now, but accepted since gcc uses it */
7003 suffix = 0;
9306ca4a 7004 }
64a0c779 7005
f16b83df 7006 else
a724f0f4
JB		 7007 {
7008 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7009 return 0;
7010 }
7011
435acd52
JB		 7012 /* Operands for jump/call using 'ptr' notation denote absolute
7013 addresses. */
7014 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7015 i.types[this_operand] |= JumpAbsolute;
7016
a724f0f4
JB		 7017 if (current_templates->start->base_opcode == 0x8d /* lea */)
7018 ;
7019 else if (!i.suffix)
7020 i.suffix = suffix;
7021 else if (i.suffix != suffix)
7022 {
7023 as_bad (_("Conflicting operand modifiers"));
7024 return 0;
7025 }
64a0c779 7026
9306ca4a
JB		 7027 }
7028
a724f0f4
JB		 7029 /* e09' : e10 e09' */
7030 else if (cur_token.code == ':')
9306ca4a 7031 {
a724f0f4
JB		 7032 if (prev_token.code != T_REG)
7033 {
7034 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7035 segment/group identifier (which we don't have), using comma
7036 as the operand separator there is even less consistent, since
7037 there all branches only have a single operand. */
7038 if (this_operand != 0
7039 || intel_parser.in_offset
7040 || intel_parser.in_bracket
7041 || (!(current_templates->start->opcode_modifier
7042 & (Jump|JumpDword|JumpInterSegment))
7043 && !(current_templates->start->operand_types[0]
7044 & JumpAbsolute)))
7045 return intel_match_token (T_NIL);
7046 /* Remember the start of the 2nd operand and terminate 1st
7047 operand here.
7048 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7049 another expression), but it gets at least the simplest case
7050 (a plain number or symbol on the left side) right. */
7051 intel_parser.next_operand = intel_parser.op_string;
7052 *--intel_parser.op_string = '\0';
7053 return intel_match_token (':');
7054 }
9306ca4a 7055 }
64a0c779 7056
a724f0f4 7057 /* e09' Empty */
64a0c779 7058 else
a724f0f4 7059 break;
64a0c779 7060
a724f0f4
JB		 7061 intel_match_token (cur_token.code);
7062
7063 }
7064
7065 if (in_offset)
7066 {
7067 --intel_parser.in_offset;
7068 if (nregs < 0)
7069 nregs = ~nregs;
7070 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7071 {
a724f0f4 7072 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7073 return 0;
7074 }
a724f0f4
JB		 7075 intel_parser.op_modifier |= 1 << T_OFFSET;
7076 }
9306ca4a 7077
a724f0f4
JB		 7078 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7079 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7080 return 1;
7081}
64a0c779 7082
a724f0f4
JB		 7083static int
7084intel_bracket_expr ()
7085{
7086 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7087 const char *start = intel_parser.op_string;
7088 int len;
7089
7090 if (i.op[this_operand].regs)
7091 return intel_match_token (T_NIL);
7092
7093 intel_match_token ('[');
7094
7095 /* Mark as a memory operand only if it's not already known to be an
7096 offset expression. If it's an offset expression, we need to keep
7097 the brace in. */
7098 if (!intel_parser.in_offset)
7099 {
7100 ++intel_parser.in_bracket;
435acd52
JB		 7101
7102 /* Operands for jump/call inside brackets denote absolute addresses. */
7103 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7104 i.types[this_operand] |= JumpAbsolute;
7105
a724f0f4
JB		 7106 /* Unfortunately gas always diverged from MASM in a respect that can't
7107 be easily fixed without risking to break code sequences likely to be
7108 encountered (the testsuite even check for this): MASM doesn't consider
7109 an expression inside brackets unconditionally as a memory reference.
7110 When that is e.g. a constant, an offset expression, or the sum of the
7111 two, this is still taken as a constant load. gas, however, always
7112 treated these as memory references. As a compromise, we'll try to make
7113 offset expressions inside brackets work the MASM way (since that's
7114 less likely to be found in real world code), but make constants alone
7115 continue to work the traditional gas way. In either case, issue a
7116 warning. */
7117 intel_parser.op_modifier &= ~was_offset;
64a0c779 7118 }
a724f0f4 7119 else
64e74474 7120 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7121
7122 /* Add a '+' to the displacement string if necessary. */
7123 if (*intel_parser.disp != '\0'
7124 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7125 strcat (intel_parser.disp, "+");
64a0c779 7126
a724f0f4
JB		 7127 if (intel_expr ()
7128 && (len = intel_parser.op_string - start - 1,
7129 intel_match_token (']')))
64a0c779 7130 {
a724f0f4
JB		 7131 /* Preserve brackets when the operand is an offset expression. */
7132 if (intel_parser.in_offset)
7133 strcat (intel_parser.disp, "]");
7134 else
7135 {
7136 --intel_parser.in_bracket;
7137 if (i.base_reg || i.index_reg)
7138 intel_parser.is_mem = 1;
7139 if (!intel_parser.is_mem)
7140 {
7141 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7142 /* Defer the warning until all of the operand was parsed. */
7143 intel_parser.is_mem = -1;
7144 else if (!quiet_warnings)
7145 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7146 }
7147 }
7148 intel_parser.op_modifier |= was_offset;
64a0c779 7149
a724f0f4 7150 return 1;
64a0c779 7151 }
a724f0f4 7152 return 0;
64a0c779
DN		 7153}
7154
7155/* e10 e11 e10'
7156
7157 e10' [ expr ] e10'
b77a7acd 7158 | Empty */
64a0c779
DN		 7159static int
7160intel_e10 ()
7161{
a724f0f4
JB		 7162 if (!intel_e11 ())
7163 return 0;
64a0c779 7164
a724f0f4 7165 while (cur_token.code == '[')
64a0c779 7166 {
a724f0f4 7167 if (!intel_bracket_expr ())
21d6c4af 7168 return 0;
64a0c779
DN		 7169 }
7170
a724f0f4 7171 return 1;
64a0c779
DN		 7172}
7173
64a0c779 7174/* e11 ( expr )
b77a7acd 7175 | [ expr ]
64a0c779
DN		 7176 | BYTE
7177 | WORD
7178 | DWORD
9306ca4a 7179 | FWORD
64a0c779 7180 | QWORD
9306ca4a
JB		 7181 | TBYTE
7182 | OWORD
7183 | XMMWORD
4a1805b1 7184 | $
64a0c779
DN		 7185 | .
7186 | register
7187 | id
7188 | constant */
7189static int
7190intel_e11 ()
7191{
a724f0f4 7192 switch (cur_token.code)
64a0c779 7193 {
a724f0f4
JB		 7194 /* e11 ( expr ) */
7195 case '(':
64a0c779
DN		 7196 intel_match_token ('(');
7197 strcat (intel_parser.disp, "(");
7198
7199 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7200 {
7201 strcat (intel_parser.disp, ")");
7202 return 1;
7203 }
a724f0f4 7204 return 0;
4a1805b1 7205
a724f0f4
JB		 7206 /* e11 [ expr ] */
7207 case '[':
a724f0f4 7208 return intel_bracket_expr ();
64a0c779 7209
a724f0f4
JB		 7210 /* e11 $
7211 | . */
7212 case '.':
64a0c779
DN		 7213 strcat (intel_parser.disp, cur_token.str);
7214 intel_match_token (cur_token.code);
21d6c4af
DN		 7215
7216 /* Mark as a memory operand only if it's not already known to be an
7217 offset expression. */
a724f0f4 7218 if (!intel_parser.in_offset)
21d6c4af 7219 intel_parser.is_mem = 1;
64a0c779
DN		 7220
7221 return 1;
64a0c779 7222
a724f0f4
JB		 7223 /* e11 register */
7224 case T_REG:
7225 {
7226 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7227
a724f0f4 7228 intel_match_token (T_REG);
64a0c779 7229
a724f0f4
JB		 7230 /* Check for segment change. */
7231 if (cur_token.code == ':')
7232 {
7233 if (!(reg->reg_type & (SReg2 | SReg3)))
7234 {
7235 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7236 return 0;
7237 }
7238 else if (i.seg[i.mem_operands])
7239 as_warn (_("Extra segment override ignored"));
7240 else
7241 {
7242 if (!intel_parser.in_offset)
7243 intel_parser.is_mem = 1;
7244 switch (reg->reg_num)
7245 {
7246 case 0:
7247 i.seg[i.mem_operands] = &es;
7248 break;
7249 case 1:
7250 i.seg[i.mem_operands] = &cs;
7251 break;
7252 case 2:
7253 i.seg[i.mem_operands] = &ss;
7254 break;
7255 case 3:
7256 i.seg[i.mem_operands] = &ds;
7257 break;
7258 case 4:
7259 i.seg[i.mem_operands] = &fs;
7260 break;
7261 case 5:
7262 i.seg[i.mem_operands] = &gs;
7263 break;
7264 }
7265 }
7266 }
64a0c779 7267
a724f0f4
JB		 7268 /* Not a segment register. Check for register scaling. */
7269 else if (cur_token.code == '*')
7270 {
7271 if (!intel_parser.in_bracket)
7272 {
7273 as_bad (_("Register scaling only allowed in memory operands"));
7274 return 0;
7275 }
64a0c779 7276
a724f0f4
JB		 7277 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7278 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7279 else if (i.index_reg)
7280 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7281
a724f0f4
JB		 7282 /* What follows must be a valid scale. */
7283 intel_match_token ('*');
7284 i.index_reg = reg;
7285 i.types[this_operand] |= BaseIndex;
64a0c779 7286
a724f0f4
JB		 7287 /* Set the scale after setting the register (otherwise,
7288 i386_scale will complain) */
7289 if (cur_token.code == '+' || cur_token.code == '-')
7290 {
7291 char *str, sign = cur_token.code;
7292 intel_match_token (cur_token.code);
7293 if (cur_token.code != T_CONST)
7294 {
7295 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7296 cur_token.str);
7297 return 0;
7298 }
7299 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7300 strcpy (str + 1, cur_token.str);
7301 *str = sign;
7302 if (!i386_scale (str))
7303 return 0;
7304 free (str);
7305 }
7306 else if (!i386_scale (cur_token.str))
64a0c779 7307 return 0;
a724f0f4
JB		 7308 intel_match_token (cur_token.code);
7309 }
64a0c779 7310
a724f0f4
JB		 7311 /* No scaling. If this is a memory operand, the register is either a
7312 base register (first occurrence) or an index register (second
7313 occurrence). */
7b0441f6 7314 else if (intel_parser.in_bracket)
a724f0f4 7315 {
64a0c779 7316
a724f0f4
JB		 7317 if (!i.base_reg)
7318 i.base_reg = reg;
7319 else if (!i.index_reg)
7320 i.index_reg = reg;
7321 else
7322 {
7323 as_bad (_("Too many register references in memory operand"));
7324 return 0;
7325 }
64a0c779 7326
a724f0f4
JB		 7327 i.types[this_operand] |= BaseIndex;
7328 }
4a1805b1 7329
4d1bb795
JB		 7330 /* It's neither base nor index. */
7331 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7332 {
7333 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7334 i.op[this_operand].regs = reg;
7335 i.reg_operands++;
7336 }
7337 else
7338 {
7339 as_bad (_("Invalid use of register"));
7340 return 0;
7341 }
64a0c779 7342
a724f0f4
JB		 7343 /* Since registers are not part of the displacement string (except
7344 when we're parsing offset operands), we may need to remove any
7345 preceding '+' from the displacement string. */
7346 if (*intel_parser.disp != '\0'
7347 && !intel_parser.in_offset)
7348 {
7349 char *s = intel_parser.disp;
7350 s += strlen (s) - 1;
7351 if (*s == '+')
7352 *s = '\0';
7353 }
4a1805b1 7354
a724f0f4
JB		 7355 return 1;
7356 }
7357
7358 /* e11 BYTE
7359 | WORD
7360 | DWORD
7361 | FWORD
7362 | QWORD
7363 | TBYTE
7364 | OWORD
7365 | XMMWORD */
7366 case T_BYTE:
7367 case T_WORD:
7368 case T_DWORD:
7369 case T_FWORD:
7370 case T_QWORD:
7371 case T_TBYTE:
7372 case T_XMMWORD:
7373 intel_match_token (cur_token.code);
64a0c779 7374
a724f0f4
JB		 7375 if (cur_token.code == T_PTR)
7376 return 1;
7377
7378 /* It must have been an identifier. */
7379 intel_putback_token ();
7380 cur_token.code = T_ID;
7381 /* FALLTHRU */
7382
7383 /* e11 id
7384 | constant */
7385 case T_ID:
7386 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7387 {
7388 symbolS *symbolP;
7389
a724f0f4
JB		 7390 /* The identifier represents a memory reference only if it's not
7391 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7392 symbolP = symbol_find(cur_token.str);
7393 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7394 intel_parser.is_mem = 1;
7395 }
a724f0f4 7396 /* FALLTHRU */
64a0c779 7397
a724f0f4
JB		 7398 case T_CONST:
7399 case '-':
7400 case '+':
7401 {
7402 char *save_str, sign = 0;
64a0c779 7403
a724f0f4
JB		 7404 /* Allow constants that start with `+' or `-'. */
7405 if (cur_token.code == '-' || cur_token.code == '+')
7406 {
7407 sign = cur_token.code;
7408 intel_match_token (cur_token.code);
7409 if (cur_token.code != T_CONST)
7410 {
7411 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7412 cur_token.str);
7413 return 0;
7414 }
7415 }
64a0c779 7416
a724f0f4
JB		 7417 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7418 strcpy (save_str + !!sign, cur_token.str);
7419 if (sign)
7420 *save_str = sign;
64a0c779 7421
a724f0f4
JB		 7422 /* Get the next token to check for register scaling. */
7423 intel_match_token (cur_token.code);
64a0c779 7424
a724f0f4
JB		 7425 /* Check if this constant is a scaling factor for an index register. */
7426 if (cur_token.code == '*')
7427 {
7428 if (intel_match_token ('*') && cur_token.code == T_REG)
7429 {
7430 const reg_entry *reg = cur_token.reg;
7431
7432 if (!intel_parser.in_bracket)
7433 {
7434 as_bad (_("Register scaling only allowed in memory operands"));
7435 return 0;
7436 }
7437
7438 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7439 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7440 else if (i.index_reg)
7441 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7442
7443 /* The constant is followed by `* reg', so it must be
7444 a valid scale. */
7445 i.index_reg = reg;
7446 i.types[this_operand] |= BaseIndex;
7447
7448 /* Set the scale after setting the register (otherwise,
7449 i386_scale will complain) */
7450 if (!i386_scale (save_str))
64a0c779 7451 return 0;
a724f0f4
JB		 7452 intel_match_token (T_REG);
7453
7454 /* Since registers are not part of the displacement
7455 string, we may need to remove any preceding '+' from
7456 the displacement string. */
7457 if (*intel_parser.disp != '\0')
7458 {
7459 char *s = intel_parser.disp;
7460 s += strlen (s) - 1;
7461 if (*s == '+')
7462 *s = '\0';
7463 }
7464
7465 free (save_str);
7466
7467 return 1;
7468 }
64a0c779 7469
a724f0f4
JB		 7470 /* The constant was not used for register scaling. Since we have
7471 already consumed the token following `*' we now need to put it
7472 back in the stream. */
64a0c779 7473 intel_putback_token ();
a724f0f4 7474 }
64a0c779 7475
a724f0f4
JB		 7476 /* Add the constant to the displacement string. */
7477 strcat (intel_parser.disp, save_str);
7478 free (save_str);
64a0c779 7479
a724f0f4
JB		 7480 return 1;
7481 }
64a0c779
DN		 7482 }
7483
64a0c779
DN		 7484 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7485 return 0;
7486}
7487
64a0c779
DN		 7488/* Match the given token against cur_token. If they match, read the next
7489 token from the operand string. */
7490static int
7491intel_match_token (code)
e5cb08ac 7492 int code;
64a0c779
DN		 7493{
7494 if (cur_token.code == code)
7495 {
7496 intel_get_token ();
7497 return 1;
7498 }
7499 else
7500 {
0477af35 7501 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7502 return 0;
7503 }
7504}
7505
64a0c779
DN		 7506/* Read a new token from intel_parser.op_string and store it in cur_token. */
7507static void
7508intel_get_token ()
7509{
7510 char *end_op;
7511 const reg_entry *reg;
7512 struct intel_token new_token;
7513
7514 new_token.code = T_NIL;
7515 new_token.reg = NULL;
7516 new_token.str = NULL;
7517
4a1805b1 7518 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7519 cur_token to prev_token. */
7520 if (prev_token.str)
7521 free (prev_token.str);
7522
7523 prev_token = cur_token;
7524
7525 /* Skip whitespace. */
7526 while (is_space_char (*intel_parser.op_string))
7527 intel_parser.op_string++;
7528
7529 /* Return an empty token if we find nothing else on the line. */
7530 if (*intel_parser.op_string == '\0')
7531 {
7532 cur_token = new_token;
7533 return;
7534 }
7535
7536 /* The new token cannot be larger than the remainder of the operand
7537 string. */
a724f0f4 7538 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7539 new_token.str[0] = '\0';
7540
7541 if (strchr ("0123456789", *intel_parser.op_string))
7542 {
7543 char *p = new_token.str;
7544 char *q = intel_parser.op_string;
7545 new_token.code = T_CONST;
7546
7547 /* Allow any kind of identifier char to encompass floating point and
7548 hexadecimal numbers. */
7549 while (is_identifier_char (*q))
7550 *p++ = *q++;
7551 *p = '\0';
7552
7553 /* Recognize special symbol names [0-9][bf]. */
7554 if (strlen (intel_parser.op_string) == 2
4a1805b1 7555 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7556 || intel_parser.op_string[1] == 'f'))
7557 new_token.code = T_ID;
7558 }
7559
4d1bb795 7560 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7561 {
4d1bb795
JB		 7562 size_t len = end_op - intel_parser.op_string;
7563
64a0c779
DN		 7564 new_token.code = T_REG;
7565 new_token.reg = reg;
7566
4d1bb795
JB		 7567 memcpy (new_token.str, intel_parser.op_string, len);
7568 new_token.str[len] = '\0';
64a0c779
DN		 7569 }
7570
7571 else if (is_identifier_char (*intel_parser.op_string))
7572 {
7573 char *p = new_token.str;
7574 char *q = intel_parser.op_string;
7575
7576 /* A '.' or '$' followed by an identifier char is an identifier.
7577 Otherwise, it's operator '.' followed by an expression. */
7578 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7579 {
9306ca4a
JB		 7580 new_token.code = '.';
7581 new_token.str[0] = '.';
64a0c779
DN		 7582 new_token.str[1] = '\0';
7583 }
7584 else
7585 {
7586 while (is_identifier_char (*q) || *q == '@')
7587 *p++ = *q++;
7588 *p = '\0';
7589
9306ca4a
JB		 7590 if (strcasecmp (new_token.str, "NOT") == 0)
7591 new_token.code = '~';
7592
7593 else if (strcasecmp (new_token.str, "MOD") == 0)
7594 new_token.code = '%';
7595
7596 else if (strcasecmp (new_token.str, "AND") == 0)
7597 new_token.code = '&';
7598
7599 else if (strcasecmp (new_token.str, "OR") == 0)
7600 new_token.code = '|';
7601
7602 else if (strcasecmp (new_token.str, "XOR") == 0)
7603 new_token.code = '^';
7604
7605 else if (strcasecmp (new_token.str, "SHL") == 0)
7606 new_token.code = T_SHL;
7607
7608 else if (strcasecmp (new_token.str, "SHR") == 0)
7609 new_token.code = T_SHR;
7610
7611 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7612 new_token.code = T_BYTE;
7613
7614 else if (strcasecmp (new_token.str, "WORD") == 0)
7615 new_token.code = T_WORD;
7616
7617 else if (strcasecmp (new_token.str, "DWORD") == 0)
7618 new_token.code = T_DWORD;
7619
9306ca4a
JB		 7620 else if (strcasecmp (new_token.str, "FWORD") == 0)
7621 new_token.code = T_FWORD;
7622
64a0c779
DN		 7623 else if (strcasecmp (new_token.str, "QWORD") == 0)
7624 new_token.code = T_QWORD;
7625
9306ca4a
JB		 7626 else if (strcasecmp (new_token.str, "TBYTE") == 0
7627 /* XXX remove (gcc still uses it) */
7628 || strcasecmp (new_token.str, "XWORD") == 0)
7629 new_token.code = T_TBYTE;
7630
7631 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7632 || strcasecmp (new_token.str, "OWORD") == 0)
7633 new_token.code = T_XMMWORD;
64a0c779
DN		 7634
7635 else if (strcasecmp (new_token.str, "PTR") == 0)
7636 new_token.code = T_PTR;
7637
7638 else if (strcasecmp (new_token.str, "SHORT") == 0)
7639 new_token.code = T_SHORT;
7640
7641 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7642 {
7643 new_token.code = T_OFFSET;
7644
7645 /* ??? This is not mentioned in the MASM grammar but gcc
7646 makes use of it with -mintel-syntax. OFFSET may be
7647 followed by FLAT: */
7648 if (strncasecmp (q, " FLAT:", 6) == 0)
7649 strcat (new_token.str, " FLAT:");
7650 }
7651
7652 /* ??? This is not mentioned in the MASM grammar. */
7653 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7654 {
7655 new_token.code = T_OFFSET;
7656 if (*q == ':')
7657 strcat (new_token.str, ":");
7658 else
7659 as_bad (_("`:' expected"));
7660 }
64a0c779
DN		 7661
7662 else
7663 new_token.code = T_ID;
7664 }
7665 }
7666
9306ca4a
JB		 7667 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7668 {
7669 new_token.code = *intel_parser.op_string;
7670 new_token.str[0] = *intel_parser.op_string;
7671 new_token.str[1] = '\0';
7672 }
7673
7674 else if (strchr ("<>", *intel_parser.op_string)
7675 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7676 {
7677 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7678 new_token.str[0] = *intel_parser.op_string;
7679 new_token.str[1] = *intel_parser.op_string;
7680 new_token.str[2] = '\0';
7681 }
7682
64a0c779 7683 else
0477af35 7684 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7685
7686 intel_parser.op_string += strlen (new_token.str);
7687 cur_token = new_token;
7688}
7689
64a0c779
DN		 7690/* Put cur_token back into the token stream and make cur_token point to
7691 prev_token. */
7692static void
7693intel_putback_token ()
7694{
a724f0f4
JB		 7695 if (cur_token.code != T_NIL)
7696 {
7697 intel_parser.op_string -= strlen (cur_token.str);
7698 free (cur_token.str);
7699 }
64a0c779 7700 cur_token = prev_token;
4a1805b1 7701
64a0c779
DN		 7702 /* Forget prev_token. */
7703 prev_token.code = T_NIL;
7704 prev_token.reg = NULL;
7705 prev_token.str = NULL;
7706}
54cfded0 7707
a4447b93 7708int
1df69f4f 7709tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7710{
7711 unsigned int regnum;
7712 unsigned int regnames_count;
089dfecd 7713 static const char *const regnames_32[] =
54cfded0 7714 {
a4447b93
RH		 7715 "eax", "ecx", "edx", "ebx",
7716 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7717 "eip", "eflags", NULL,
7718 "st0", "st1", "st2", "st3",
7719 "st4", "st5", "st6", "st7",
7720 NULL, NULL,
7721 "xmm0", "xmm1", "xmm2", "xmm3",
7722 "xmm4", "xmm5", "xmm6", "xmm7",
7723 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7724 "mm4", "mm5", "mm6", "mm7",
7725 "fcw", "fsw", "mxcsr",
7726 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7727 "tr", "ldtr"
54cfded0 7728 };
089dfecd 7729 static const char *const regnames_64[] =
54cfded0 7730 {
089dfecd
JB		 7731 "rax", "rdx", "rcx", "rbx",
7732 "rsi", "rdi", "rbp", "rsp",
7733 "r8", "r9", "r10", "r11",
54cfded0 7734 "r12", "r13", "r14", "r15",
089dfecd
JB		 7735 "rip",
7736 "xmm0", "xmm1", "xmm2", "xmm3",
7737 "xmm4", "xmm5", "xmm6", "xmm7",
7738 "xmm8", "xmm9", "xmm10", "xmm11",
7739 "xmm12", "xmm13", "xmm14", "xmm15",
7740 "st0", "st1", "st2", "st3",
7741 "st4", "st5", "st6", "st7",
7742 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7743 "mm4", "mm5", "mm6", "mm7",
7744 "rflags",
7745 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7746 "fs.base", "gs.base", NULL, NULL,
7747 "tr", "ldtr",
7748 "mxcsr", "fcw", "fsw"
54cfded0 7749 };
089dfecd 7750 const char *const *regnames;
54cfded0
AM		 7751
7752 if (flag_code == CODE_64BIT)
7753 {
7754 regnames = regnames_64;
0cea6190 7755 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7756 }
7757 else
7758 {
7759 regnames = regnames_32;
0cea6190 7760 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7761 }
7762
7763 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7764 if (regnames[regnum] != NULL
7765 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7766 return regnum;
7767
54cfded0
AM		 7768 return -1;
7769}
7770
7771void
7772tc_x86_frame_initial_instructions (void)
7773{
a4447b93
RH		 7774 static unsigned int sp_regno;
7775
7776 if (!sp_regno)
7777 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7778 ? "rsp" : "esp");
7779
7780 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7781 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7782}
d2b2c203
DJ		 7783
7784int
7785i386_elf_section_type (const char *str, size_t len)
7786{
7787 if (flag_code == CODE_64BIT
7788 && len == sizeof ("unwind") - 1
7789 && strncmp (str, "unwind", 6) == 0)
7790 return SHT_X86_64_UNWIND;
7791
7792 return -1;
7793}
bb41ade5
AM		 7794
7795#ifdef TE_PE
7796void
7797tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7798{
7799 expressionS expr;
7800
7801 expr.X_op = O_secrel;
7802 expr.X_add_symbol = symbol;
7803 expr.X_add_number = 0;
7804 emit_expr (&expr, size);
7805}
7806#endif
3b22753a
L		 7807
7808#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7809/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7810
7811int
7812x86_64_section_letter (int letter, char **ptr_msg)
7813{
7814 if (flag_code == CODE_64BIT)
7815 {
7816 if (letter == 'l')
7817 return SHF_X86_64_LARGE;
7818
7819 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7820 }
3b22753a 7821 else
64e74474 7822 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7823 return -1;
7824}
7825
7826int
7827x86_64_section_word (char *str, size_t len)
7828{
8620418b 7829 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7830 return SHF_X86_64_LARGE;
7831
7832 return -1;
7833}
7834
7835static void
7836handle_large_common (int small ATTRIBUTE_UNUSED)
7837{
7838 if (flag_code != CODE_64BIT)
7839 {
7840 s_comm_internal (0, elf_common_parse);
7841 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7842 }
7843 else
7844 {
7845 static segT lbss_section;
7846 asection *saved_com_section_ptr = elf_com_section_ptr;
7847 asection *saved_bss_section = bss_section;
7848
7849 if (lbss_section == NULL)
7850 {
7851 flagword applicable;
7852 segT seg = now_seg;
7853 subsegT subseg = now_subseg;
7854
7855 /* The .lbss section is for local .largecomm symbols. */
7856 lbss_section = subseg_new (".lbss", 0);
7857 applicable = bfd_applicable_section_flags (stdoutput);
7858 bfd_set_section_flags (stdoutput, lbss_section,
7859 applicable & SEC_ALLOC);
7860 seg_info (lbss_section)->bss = 1;
7861
7862 subseg_set (seg, subseg);
7863 }
7864
7865 elf_com_section_ptr = &_bfd_elf_large_com_section;
7866 bss_section = lbss_section;
7867
7868 s_comm_internal (0, elf_common_parse);
7869
7870 elf_com_section_ptr = saved_com_section_ptr;
7871 bss_section = saved_bss_section;
7872 }
7873}
7874#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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