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Fix length arg in call to breakpoint_xfer_memory.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
143e9f4a 4 2012, 2013, 2014
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
7e8b059b 70#define BND_PREFIX REP_PREFIX
c32fa91d
L		 71#define LOCK_PREFIX 5
72#define REX_PREFIX 6 /* must come last. */
73#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 74
75/* we define the syntax here (modulo base,index,scale syntax) */
76#define REGISTER_PREFIX '%'
77#define IMMEDIATE_PREFIX '$'
78#define ABSOLUTE_PREFIX '*'
79
80/* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82#define WORD_MNEM_SUFFIX 'w'
83#define BYTE_MNEM_SUFFIX 'b'
84#define SHORT_MNEM_SUFFIX 's'
85#define LONG_MNEM_SUFFIX 'l'
86#define QWORD_MNEM_SUFFIX 'q'
87#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 88#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 89#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 90/* Intel Syntax. Use a non-ascii letter since since it never appears
91 in instructions. */
92#define LONG_DOUBLE_MNEM_SUFFIX '\1'
93
94#define END_OF_INSN '\0'
95
96/*
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
101 END.
102 */
103typedef struct
104{
d3ce72d0
NC		 105 const insn_template *start;
106 const insn_template *end;
6305a203
L		 107}
108templates;
109
110/* 386 operand encoding bytes: see 386 book for details of this. */
111typedef struct
112{
113 unsigned int regmem; /* codes register or memory operand */
114 unsigned int reg; /* codes register operand (or extended opcode) */
115 unsigned int mode; /* how to interpret regmem & reg */
116}
117modrm_byte;
118
119/* x86-64 extension prefix. */
120typedef int rex_byte;
121
6305a203
L		 122/* 386 opcode byte to code indirect addressing. */
123typedef struct
124{
125 unsigned base;
126 unsigned index;
127 unsigned scale;
128}
129sib_byte;
130
6305a203
L		 131/* x86 arch names, types and features */
132typedef struct
133{
134 const char *name; /* arch name */
8a2c8fef 135 unsigned int len; /* arch string length */
6305a203
L		 136 enum processor_type type; /* arch type */
137 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 138 unsigned int skip; /* show_arch should skip this. */
22109423 139 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 140}
141arch_entry;
142
78f12dd3 143static void update_code_flag (int, int);
e3bb37b5
L		 144static void set_code_flag (int);
145static void set_16bit_gcc_code_flag (int);
146static void set_intel_syntax (int);
1efbbeb4 147static void set_intel_mnemonic (int);
db51cc60 148static void set_allow_index_reg (int);
7bab8ab5 149static void set_check (int);
e3bb37b5 150static void set_cpu_arch (int);
6482c264 151#ifdef TE_PE
e3bb37b5 152static void pe_directive_secrel (int);
6482c264 153#endif
e3bb37b5
L		 154static void signed_cons (int);
155static char *output_invalid (int c);
ee86248c
JB		 156static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
157 const char *);
158static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
159 const char *);
a7619375 160static int i386_att_operand (char *);
e3bb37b5 161static int i386_intel_operand (char *, int);
ee86248c
JB		 162static int i386_intel_simplify (expressionS *);
163static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 164static const reg_entry *parse_register (char *, char **);
165static char *parse_insn (char *, char *);
166static char *parse_operands (char *, const char *);
167static void swap_operands (void);
4d456e3d 168static void swap_2_operands (int, int);
e3bb37b5
L		 169static void optimize_imm (void);
170static void optimize_disp (void);
d3ce72d0 171static const insn_template *match_template (void);
e3bb37b5
L		 172static int check_string (void);
173static int process_suffix (void);
174static int check_byte_reg (void);
175static int check_long_reg (void);
176static int check_qword_reg (void);
177static int check_word_reg (void);
178static int finalize_imm (void);
179static int process_operands (void);
180static const seg_entry *build_modrm_byte (void);
181static void output_insn (void);
182static void output_imm (fragS *, offsetT);
183static void output_disp (fragS *, offsetT);
29b0f896 184#ifndef I386COFF
e3bb37b5 185static void s_bss (int);
252b5132 186#endif
17d4e2a2
L		 187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188static void handle_large_common (int small ATTRIBUTE_UNUSED);
189#endif
252b5132 190
a847613f 191static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 192
43234a1e
L		 193/* This struct describes rounding control and SAE in the instruction. */
194struct RC_Operation
195{
196 enum rc_type
197 {
198 rne = 0,
199 rd,
200 ru,
201 rz,
202 saeonly
203 } type;
204 int operand;
205};
206
207static struct RC_Operation rc_op;
208
209/* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212struct Mask_Operation
213{
214 const reg_entry *mask;
215 unsigned int zeroing;
216 /* The operand where this operation is associated. */
217 int operand;
218};
219
220static struct Mask_Operation mask_op;
221
222/* The struct describes broadcasting, applied to OPERAND. FACTOR is
223 broadcast factor. */
224struct Broadcast_Operation
225{
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
227 int type;
228
229 /* Index of broadcasted operand. */
230 int operand;
231};
232
233static struct Broadcast_Operation broadcast_op;
234
c0f3af97
L		 235/* VEX prefix. */
236typedef struct
237{
43234a1e
L		 238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes[4];
c0f3af97
L		 240 unsigned int length;
241 /* Destination or source register specifier. */
242 const reg_entry *register_specifier;
243} vex_prefix;
244
252b5132 245/* 'md_assemble ()' gathers together information and puts it into a
47926f60 246 i386_insn. */
252b5132 247
520dc8e8
AM		 248union i386_op
249 {
250 expressionS *disps;
251 expressionS *imms;
252 const reg_entry *regs;
253 };
254
a65babc9
L		 255enum i386_error
256 {
86e026a4 257 operand_size_mismatch,
a65babc9
L		 258 operand_type_mismatch,
259 register_type_mismatch,
260 number_of_operands_mismatch,
261 invalid_instruction_suffix,
262 bad_imm4,
263 old_gcc_only,
264 unsupported_with_intel_mnemonic,
265 unsupported_syntax,
6c30d220
L		 266 unsupported,
267 invalid_vsib_address,
7bab8ab5 268 invalid_vector_register_set,
43234a1e
L		 269 unsupported_vector_index_register,
270 unsupported_broadcast,
271 broadcast_not_on_src_operand,
272 broadcast_needed,
273 unsupported_masking,
274 mask_not_on_destination,
275 no_default_mask,
276 unsupported_rc_sae,
277 rc_sae_operand_not_last_imm,
278 invalid_register_operand,
279 try_vector_disp8
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132
RH		 323
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes;
327 unsigned char prefix[MAX_PREFIXES];
328
329 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 330 addressing modes of this insn are encoded. */
252b5132 331 modrm_byte rm;
3e73aa7c 332 rex_byte rex;
43234a1e 333 rex_byte vrex;
252b5132 334 sib_byte sib;
c0f3af97 335 vex_prefix vex;
b6169b20 336
43234a1e
L		 337 /* Masking attributes. */
338 struct Mask_Operation *mask;
339
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation *rounding;
342
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation *broadcast;
345
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift;
348
b6169b20 349 /* Swap operand in encoding. */
4473e004 350 unsigned int swap_operand;
891edac4 351
a501d77e
L		 352 /* Prefer 8bit or 32bit displacement in encoding. */
353 enum
354 {
355 disp_encoding_default = 0,
356 disp_encoding_8bit,
357 disp_encoding_32bit
358 } disp_encoding;
f8a5c266 359
d5de92cf
L		 360 /* REP prefix. */
361 const char *rep_prefix;
362
165de32a
L		 363 /* HLE prefix. */
364 const char *hle_prefix;
42164a71 365
7e8b059b
L		 366 /* Have BND prefix. */
367 const char *bnd_prefix;
368
43234a1e
L		 369 /* Need VREX to support upper 16 registers. */
370 int need_vrex;
371
891edac4 372 /* Error message. */
a65babc9 373 enum i386_error error;
252b5132
RH		 374 };
375
376typedef struct _i386_insn i386_insn;
377
43234a1e
L		 378/* Link RC type with corresponding string, that'll be looked for in
379 asm. */
380struct RC_name
381{
382 enum rc_type type;
383 const char *name;
384 unsigned int len;
385};
386
387static const struct RC_name RC_NamesTable[] =
388{
389 { rne, STRING_COMMA_LEN ("rn-sae") },
390 { rd, STRING_COMMA_LEN ("rd-sae") },
391 { ru, STRING_COMMA_LEN ("ru-sae") },
392 { rz, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly, STRING_COMMA_LEN ("sae") },
394};
395
252b5132
RH		 396/* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 398const char extra_symbol_chars[] = "*%-([{"
252b5132 399#ifdef LEX_AT
32137342
NC		 400 "@"
401#endif
402#ifdef LEX_QM
403 "?"
252b5132 404#endif
32137342 405 ;
252b5132 406
29b0f896
AM		 407#if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 409 && !defined (TE_GNU) \
29b0f896 410 && !defined (TE_LINUX) \
8d63c93e
RM		 411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
29b0f896 413 && !defined (TE_FreeBSD) \
5b806d27 414 && !defined (TE_DragonFly) \
29b0f896 415 && !defined (TE_NetBSD)))
252b5132 416/* This array holds the chars that always start a comment. If the
b3b91714
AM		 417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419const char *i386_comment_chars = "#/";
420#define SVR4_COMMENT_CHARS 1
252b5132 421#define PREFIX_SEPARATOR '\\'
252b5132 422
b3b91714
AM		 423#else
424const char *i386_comment_chars = "#";
425#define PREFIX_SEPARATOR '/'
426#endif
427
252b5132
RH		 428/* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 432 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
252b5132 435 '/' isn't otherwise defined. */
b3b91714 436const char line_comment_chars[] = "#/";
252b5132 437
63a0b638 438const char line_separator_chars[] = ";";
252b5132 439
ce8a8b2f
AM		 440/* Chars that can be used to separate mant from exp in floating point
441 nums. */
252b5132
RH		 442const char EXP_CHARS[] = "eE";
443
ce8a8b2f
AM		 444/* Chars that mean this number is a floating point constant
445 As in 0f12.456
446 or 0d1.2345e12. */
252b5132
RH		 447const char FLT_CHARS[] = "fFdDxX";
448
ce8a8b2f 449/* Tables for lexical analysis. */
252b5132
RH		 450static char mnemonic_chars[256];
451static char register_chars[256];
452static char operand_chars[256];
453static char identifier_chars[256];
454static char digit_chars[256];
455
ce8a8b2f 456/* Lexical macros. */
252b5132
RH		 457#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458#define is_operand_char(x) (operand_chars[(unsigned char) x])
459#define is_register_char(x) (register_chars[(unsigned char) x])
460#define is_space_char(x) ((x) == ' ')
461#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462#define is_digit_char(x) (digit_chars[(unsigned char) x])
463
0234cb7c 464/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 465static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
466
467/* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
47926f60 470 assembler instruction). */
252b5132 471static char save_stack[32];
ce8a8b2f 472static char *save_stack_p;
252b5132
RH		 473#define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475#define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
477
47926f60 478/* The instruction we're assembling. */
252b5132
RH		 479static i386_insn i;
480
481/* Possible templates for current insn. */
482static const templates *current_templates;
483
31b2323c
L		 484/* Per instruction expressionS buffers: max displacements & immediates. */
485static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
486static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 487
47926f60 488/* Current operand we are working on. */
ee86248c 489static int this_operand = -1;
252b5132 490
3e73aa7c
JH		 491/* We support four different modes. FLAG_CODE variable is used to distinguish
492 these. */
493
494enum flag_code {
495 CODE_32BIT,
496 CODE_16BIT,
497 CODE_64BIT };
498
499static enum flag_code flag_code;
4fa24527 500static unsigned int object_64bit;
862be3fb 501static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 502static int use_rela_relocations = 0;
503
7af8ed2d
NC		 504#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
507
351f65ca
L		 508/* The ELF ABI to use. */
509enum x86_elf_abi
510{
511 I386_ABI,
7f56bc95
L		 512 X86_64_ABI,
513 X86_64_X32_ABI
351f65ca
L		 514};
515
516static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 517#endif
351f65ca 518
47926f60
KH		 519/* 1 for intel syntax,
520 0 if att syntax. */
521static int intel_syntax = 0;
252b5132 522
1efbbeb4
L		 523/* 1 for intel mnemonic,
524 0 if att mnemonic. */
525static int intel_mnemonic = !SYSV386_COMPAT;
526
5209009a 527/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 528static int old_gcc = OLDGCC_COMPAT;
529
a60de03c
JB		 530/* 1 if pseudo registers are permitted. */
531static int allow_pseudo_reg = 0;
532
47926f60
KH		 533/* 1 if register prefix % not required. */
534static int allow_naked_reg = 0;
252b5132 535
7e8b059b
L		 536/* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
538 explicitly. */
539static int add_bnd_prefix = 0;
540
ba104c83 541/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 542static int allow_index_reg = 0;
543
7bab8ab5 544static enum check_kind
daf50ae7 545 {
7bab8ab5
JB		 546 check_none = 0,
547 check_warning,
548 check_error
daf50ae7 549 }
7bab8ab5 550sse_check, operand_check = check_warning;
daf50ae7 551
2ca3ace5
L		 552/* Register prefix used for error message. */
553static const char *register_prefix = "%";
554
47926f60
KH		 555/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558static char stackop_size = '\0';
eecb386c 559
12b55ccc
L		 560/* Non-zero to optimize code alignment. */
561int optimize_align_code = 1;
562
47926f60
KH		 563/* Non-zero to quieten some warnings. */
564static int quiet_warnings = 0;
a38cf1db 565
47926f60
KH		 566/* CPU name. */
567static const char *cpu_arch_name = NULL;
6305a203 568static char *cpu_sub_arch_name = NULL;
a38cf1db 569
47926f60 570/* CPU feature flags. */
40fb9820
L		 571static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
572
ccc9c027
L		 573/* If we have selected a cpu we are generating instructions for. */
574static int cpu_arch_tune_set = 0;
575
9103f4f4 576/* Cpu we are generating instructions for. */
fbf3f584 577enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 578
579/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 580static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 581
ccc9c027 582/* CPU instruction set architecture used. */
fbf3f584 583enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 584
9103f4f4 585/* CPU feature flags of instruction set architecture used. */
fbf3f584 586i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 587
fddf5b5b
AM		 588/* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590static unsigned int no_cond_jump_promotion = 0;
591
c0f3af97
L		 592/* Encode SSE instructions with VEX prefix. */
593static unsigned int sse2avx;
594
539f890d
L		 595/* Encode scalar AVX instructions with specific vector length. */
596static enum
597 {
598 vex128 = 0,
599 vex256
600 } avxscalar;
601
43234a1e
L		 602/* Encode scalar EVEX LIG instructions with specific vector length. */
603static enum
604 {
605 evexl128 = 0,
606 evexl256,
607 evexl512
608 } evexlig;
609
610/* Encode EVEX WIG instructions with specific evex.w. */
611static enum
612 {
613 evexw0 = 0,
614 evexw1
615 } evexwig;
616
29b0f896 617/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 618static symbolS *GOT_symbol;
29b0f896 619
a4447b93
RH		 620/* The dwarf2 return column, adjusted for 32 or 64 bit. */
621unsigned int x86_dwarf2_return_column;
622
623/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624int x86_cie_data_alignment;
625
252b5132 626/* Interface to relax_segment.
fddf5b5b
AM		 627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
252b5132 630
47926f60 631/* Types. */
93c2a809
AM		 632#define UNCOND_JUMP 0
633#define COND_JUMP 1
634#define COND_JUMP86 2
fddf5b5b 635
47926f60 636/* Sizes. */
252b5132
RH		 637#define CODE16 1
638#define SMALL 0
29b0f896 639#define SMALL16 (SMALL | CODE16)
252b5132 640#define BIG 2
29b0f896 641#define BIG16 (BIG | CODE16)
252b5132
RH		 642
643#ifndef INLINE
644#ifdef __GNUC__
645#define INLINE __inline__
646#else
647#define INLINE
648#endif
649#endif
650
fddf5b5b
AM		 651#define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653#define TYPE_FROM_RELAX_STATE(s) \
654 ((s) >> 2)
655#define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 657
658/* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
665
666const relax_typeS md_relax_table[] =
667{
24eab124
AM		 668 /* The fields are:
669 1) most positive reach of this state,
670 2) most negative reach of this state,
93c2a809 671 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 672 4) which index into the table to try if we can't fit into this one. */
252b5132 673
fddf5b5b 674 /* UNCOND_JUMP states. */
93c2a809
AM		 675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
252b5132 679 {0, 0, 4, 0},
93c2a809
AM		 680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 682 {0, 0, 2, 0},
683
93c2a809
AM		 684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
689 {0, 0, 5, 0},
fddf5b5b 690 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 691 1 extra opcode byte, 2 displacement bytes. */
692 {0, 0, 3, 0},
693
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
699 {0, 0, 5, 0},
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
702 {0, 0, 4, 0}
252b5132
RH		 703};
704
9103f4f4
L		 705static const arch_entry cpu_arch[] =
706{
89507696
JB		 707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
8a2c8fef 709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 710 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 712 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 714 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 716 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 718 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 720 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 722 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 724 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 726 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 728 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 730 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 732 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 734 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 736 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 738 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 740 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 742 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 744 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 746 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 748 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 750 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 752 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
754 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 756 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 758 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 760 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 762 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 764 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 766 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 768 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 770 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 772 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
774 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 775 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
776 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 777 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
778 CPU_BTVER1_FLAGS, 0, 0 },
779 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
780 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 782 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 784 CPU_287_FLAGS, 0, 0 },
8a2c8fef 785 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 786 CPU_387_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 788 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 789 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 790 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 791 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 792 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 793 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 794 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 795 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 796 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 798 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 800 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 802 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 804 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 806 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 808 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 809 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 810 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 811 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
812 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 813 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
814 CPU_AVX512F_FLAGS, 0, 0 },
815 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
816 CPU_AVX512CD_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
818 CPU_AVX512ER_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
820 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 822 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 823 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 824 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 825 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
826 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 830 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 831 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 832 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 834 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 836 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 838 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 839 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 840 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 841 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 842 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 843 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 844 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 845 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
846 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 848 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 850 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 852 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 854 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 856 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 857 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
858 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 860 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 861 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
862 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 863 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
864 CPU_HLE_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
866 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 867 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
868 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 870 CPU_CLFLUSH_FLAGS, 0, 0 },
871 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
872 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 874 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 876 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 878 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 880 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 882 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 884 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 886 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 888 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 890 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 891 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
892 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 893 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
894 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 895 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
896 CPU_ADX_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
898 CPU_RDSEED_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
900 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 901 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
902 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 903 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
904 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 905 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
906 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 907 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
908 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
909 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
910 CPU_XSAVEC_FLAGS, 0, 0 },
911 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
912 CPU_XSAVES_FLAGS, 0, 0 },
e413e4e9
AM		 913};
914
704209c0 915#ifdef I386COFF
a6c24e68
NC		 916/* Like s_lcomm_internal in gas/read.c but the alignment string
917 is allowed to be optional. */
918
919static symbolS *
920pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
921{
922 addressT align = 0;
923
924 SKIP_WHITESPACE ();
925
7ab9ffdd 926 if (needs_align
a6c24e68
NC		 927 && *input_line_pointer == ',')
928 {
929 align = parse_align (needs_align - 1);
7ab9ffdd 930
a6c24e68
NC		 931 if (align == (addressT) -1)
932 return NULL;
933 }
934 else
935 {
936 if (size >= 8)
937 align = 3;
938 else if (size >= 4)
939 align = 2;
940 else if (size >= 2)
941 align = 1;
942 else
943 align = 0;
944 }
945
946 bss_alloc (symbolP, size, align);
947 return symbolP;
948}
949
704209c0 950static void
a6c24e68
NC		 951pe_lcomm (int needs_align)
952{
953 s_comm_internal (needs_align * 2, pe_lcomm_internal);
954}
704209c0 955#endif
a6c24e68 956
29b0f896
AM		 957const pseudo_typeS md_pseudo_table[] =
958{
959#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
960 {"align", s_align_bytes, 0},
961#else
962 {"align", s_align_ptwo, 0},
963#endif
964 {"arch", set_cpu_arch, 0},
965#ifndef I386COFF
966 {"bss", s_bss, 0},
a6c24e68
NC		 967#else
968 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 969#endif
970 {"ffloat", float_cons, 'f'},
971 {"dfloat", float_cons, 'd'},
972 {"tfloat", float_cons, 'x'},
973 {"value", cons, 2},
d182319b 974 {"slong", signed_cons, 4},
29b0f896
AM		 975 {"noopt", s_ignore, 0},
976 {"optim", s_ignore, 0},
977 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
978 {"code16", set_code_flag, CODE_16BIT},
979 {"code32", set_code_flag, CODE_32BIT},
980 {"code64", set_code_flag, CODE_64BIT},
981 {"intel_syntax", set_intel_syntax, 1},
982 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 983 {"intel_mnemonic", set_intel_mnemonic, 1},
984 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 985 {"allow_index_reg", set_allow_index_reg, 1},
986 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 987 {"sse_check", set_check, 0},
988 {"operand_check", set_check, 1},
3b22753a
L		 989#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
990 {"largecomm", handle_large_common, 0},
07a53e5c 991#else
e3bb37b5 992 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 993 {"loc", dwarf2_directive_loc, 0},
994 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 995#endif
6482c264
NC		 996#ifdef TE_PE
997 {"secrel32", pe_directive_secrel, 0},
998#endif
29b0f896
AM		 999 {0, 0, 0}
1000};
1001
1002/* For interface with expression (). */
1003extern char *input_line_pointer;
1004
1005/* Hash table for instruction mnemonic lookup. */
1006static struct hash_control *op_hash;
1007
1008/* Hash table for register lookup. */
1009static struct hash_control *reg_hash;
1010\f
252b5132 1011void
e3bb37b5 1012i386_align_code (fragS *fragP, int count)
252b5132 1013{
ce8a8b2f
AM		 1014 /* Various efficient no-op patterns for aligning code labels.
1015 Note: Don't try to assemble the instructions in the comments.
1016 0L and 0w are not legal. */
252b5132
RH		 1017 static const char f32_1[] =
1018 {0x90}; /* nop */
1019 static const char f32_2[] =
ccc9c027 1020 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1021 static const char f32_3[] =
1022 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1023 static const char f32_4[] =
1024 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1025 static const char f32_5[] =
1026 {0x90, /* nop */
1027 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1028 static const char f32_6[] =
1029 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1030 static const char f32_7[] =
1031 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1032 static const char f32_8[] =
1033 {0x90, /* nop */
1034 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1035 static const char f32_9[] =
1036 {0x89,0xf6, /* movl %esi,%esi */
1037 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1038 static const char f32_10[] =
1039 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1040 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1041 static const char f32_11[] =
1042 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_12[] =
1045 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1046 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1047 static const char f32_13[] =
1048 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1049 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1050 static const char f32_14[] =
1051 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1052 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1053 static const char f16_3[] =
1054 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1055 static const char f16_4[] =
1056 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1057 static const char f16_5[] =
1058 {0x90, /* nop */
1059 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1060 static const char f16_6[] =
1061 {0x89,0xf6, /* mov %si,%si */
1062 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1063 static const char f16_7[] =
1064 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1065 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1066 static const char f16_8[] =
1067 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1068 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1069 static const char jump_31[] =
1070 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1071 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1072 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1073 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1074 static const char *const f32_patt[] = {
1075 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1076 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1077 };
1078 static const char *const f16_patt[] = {
76bc74dc 1079 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1080 };
ccc9c027
L		 1081 /* nopl (%[re]ax) */
1082 static const char alt_3[] =
1083 {0x0f,0x1f,0x00};
1084 /* nopl 0(%[re]ax) */
1085 static const char alt_4[] =
1086 {0x0f,0x1f,0x40,0x00};
1087 /* nopl 0(%[re]ax,%[re]ax,1) */
1088 static const char alt_5[] =
1089 {0x0f,0x1f,0x44,0x00,0x00};
1090 /* nopw 0(%[re]ax,%[re]ax,1) */
1091 static const char alt_6[] =
1092 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1093 /* nopl 0L(%[re]ax) */
1094 static const char alt_7[] =
1095 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1096 /* nopl 0L(%[re]ax,%[re]ax,1) */
1097 static const char alt_8[] =
1098 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1099 /* nopw 0L(%[re]ax,%[re]ax,1) */
1100 static const char alt_9[] =
1101 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1102 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1103 static const char alt_10[] =
1104 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1105 /* data16
1106 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_long_11[] =
1108 {0x66,
1109 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1110 /* data16
1111 data16
1112 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_long_12[] =
1114 {0x66,
1115 0x66,
1116 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1117 /* data16
1118 data16
1119 data16
1120 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1121 static const char alt_long_13[] =
1122 {0x66,
1123 0x66,
1124 0x66,
1125 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 /* data16
1127 data16
1128 data16
1129 data16
1130 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1131 static const char alt_long_14[] =
1132 {0x66,
1133 0x66,
1134 0x66,
1135 0x66,
1136 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1137 /* data16
1138 data16
1139 data16
1140 data16
1141 data16
1142 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_long_15[] =
1144 {0x66,
1145 0x66,
1146 0x66,
1147 0x66,
1148 0x66,
1149 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1150 /* nopl 0(%[re]ax,%[re]ax,1)
1151 nopw 0(%[re]ax,%[re]ax,1) */
1152 static const char alt_short_11[] =
1153 {0x0f,0x1f,0x44,0x00,0x00,
1154 0x66,0x0f,0x1f,0x44,0x00,0x00};
1155 /* nopw 0(%[re]ax,%[re]ax,1)
1156 nopw 0(%[re]ax,%[re]ax,1) */
1157 static const char alt_short_12[] =
1158 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1159 0x66,0x0f,0x1f,0x44,0x00,0x00};
1160 /* nopw 0(%[re]ax,%[re]ax,1)
1161 nopl 0L(%[re]ax) */
1162 static const char alt_short_13[] =
1163 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1164 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1165 /* nopl 0L(%[re]ax)
1166 nopl 0L(%[re]ax) */
1167 static const char alt_short_14[] =
1168 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1169 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1170 /* nopl 0L(%[re]ax)
1171 nopl 0L(%[re]ax,%[re]ax,1) */
1172 static const char alt_short_15[] =
1173 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1174 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1175 static const char *const alt_short_patt[] = {
1176 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1177 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1178 alt_short_14, alt_short_15
1179 };
1180 static const char *const alt_long_patt[] = {
1181 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1182 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1183 alt_long_14, alt_long_15
1184 };
252b5132 1185
76bc74dc
L		 1186 /* Only align for at least a positive non-zero boundary. */
1187 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1188 return;
3e73aa7c 1189
ccc9c027
L		 1190 /* We need to decide which NOP sequence to use for 32bit and
1191 64bit. When -mtune= is used:
4eed87de 1192
76bc74dc
L		 1193 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1194 PROCESSOR_GENERIC32, f32_patt will be used.
1195 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1196 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1197 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1198 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1199 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1200 will be used.
ccc9c027 1201
76bc74dc 1202 When -mtune= isn't used, alt_long_patt will be used if
22109423 1203 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1204 be used.
ccc9c027
L		 1205
1206 When -march= or .arch is used, we can't use anything beyond
1207 cpu_arch_isa_flags. */
1208
1209 if (flag_code == CODE_16BIT)
1210 {
ccc9c027 1211 if (count > 8)
33fef721 1212 {
76bc74dc
L		 1213 memcpy (fragP->fr_literal + fragP->fr_fix,
1214 jump_31, count);
1215 /* Adjust jump offset. */
1216 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1217 }
76bc74dc
L		 1218 else
1219 memcpy (fragP->fr_literal + fragP->fr_fix,
1220 f16_patt[count - 1], count);
252b5132 1221 }
33fef721 1222 else
ccc9c027
L		 1223 {
1224 const char *const *patt = NULL;
1225
fbf3f584 1226 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1227 {
1228 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1229 switch (cpu_arch_tune)
1230 {
1231 case PROCESSOR_UNKNOWN:
1232 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1233 optimize with nops. */
1234 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1235 patt = alt_long_patt;
ccc9c027
L		 1236 else
1237 patt = f32_patt;
1238 break;
ccc9c027
L		 1239 case PROCESSOR_PENTIUM4:
1240 case PROCESSOR_NOCONA:
ef05d495 1241 case PROCESSOR_CORE:
76bc74dc 1242 case PROCESSOR_CORE2:
bd5295b2 1243 case PROCESSOR_COREI7:
3632d14b 1244 case PROCESSOR_L1OM:
7a9068fe 1245 case PROCESSOR_K1OM:
76bc74dc
L		 1246 case PROCESSOR_GENERIC64:
1247 patt = alt_long_patt;
1248 break;
ccc9c027
L		 1249 case PROCESSOR_K6:
1250 case PROCESSOR_ATHLON:
1251 case PROCESSOR_K8:
4eed87de 1252 case PROCESSOR_AMDFAM10:
8aedb9fe 1253 case PROCESSOR_BD:
7b458c12 1254 case PROCESSOR_BT:
ccc9c027
L		 1255 patt = alt_short_patt;
1256 break;
76bc74dc 1257 case PROCESSOR_I386:
ccc9c027
L		 1258 case PROCESSOR_I486:
1259 case PROCESSOR_PENTIUM:
2dde1948 1260 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1261 case PROCESSOR_GENERIC32:
1262 patt = f32_patt;
1263 break;
4eed87de 1264 }
ccc9c027
L		 1265 }
1266 else
1267 {
fbf3f584 1268 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1269 {
1270 case PROCESSOR_UNKNOWN:
e6a14101 1271 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1272 PROCESSOR_UNKNOWN. */
1273 abort ();
1274 break;
1275
76bc74dc 1276 case PROCESSOR_I386:
ccc9c027
L		 1277 case PROCESSOR_I486:
1278 case PROCESSOR_PENTIUM:
ccc9c027
L		 1279 case PROCESSOR_K6:
1280 case PROCESSOR_ATHLON:
1281 case PROCESSOR_K8:
4eed87de 1282 case PROCESSOR_AMDFAM10:
8aedb9fe 1283 case PROCESSOR_BD:
7b458c12 1284 case PROCESSOR_BT:
ccc9c027
L		 1285 case PROCESSOR_GENERIC32:
1286 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1287 with nops. */
1288 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1289 patt = alt_short_patt;
1290 else
1291 patt = f32_patt;
1292 break;
76bc74dc
L		 1293 case PROCESSOR_PENTIUMPRO:
1294 case PROCESSOR_PENTIUM4:
1295 case PROCESSOR_NOCONA:
1296 case PROCESSOR_CORE:
ef05d495 1297 case PROCESSOR_CORE2:
bd5295b2 1298 case PROCESSOR_COREI7:
3632d14b 1299 case PROCESSOR_L1OM:
7a9068fe 1300 case PROCESSOR_K1OM:
22109423 1301 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1302 patt = alt_long_patt;
1303 else
1304 patt = f32_patt;
1305 break;
1306 case PROCESSOR_GENERIC64:
76bc74dc 1307 patt = alt_long_patt;
ccc9c027 1308 break;
4eed87de 1309 }
ccc9c027
L		 1310 }
1311
76bc74dc
L		 1312 if (patt == f32_patt)
1313 {
1314 /* If the padding is less than 15 bytes, we use the normal
1315 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1316 its offset. */
1317 int limit;
76ba9986 1318
711eedef
L		 1319 /* For 64bit, the limit is 3 bytes. */
1320 if (flag_code == CODE_64BIT
1321 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1322 limit = 3;
1323 else
1324 limit = 15;
1325 if (count < limit)
76bc74dc
L		 1326 memcpy (fragP->fr_literal + fragP->fr_fix,
1327 patt[count - 1], count);
1328 else
1329 {
1330 memcpy (fragP->fr_literal + fragP->fr_fix,
1331 jump_31, count);
1332 /* Adjust jump offset. */
1333 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1334 }
1335 }
1336 else
1337 {
1338 /* Maximum length of an instruction is 15 byte. If the
1339 padding is greater than 15 bytes and we don't use jump,
1340 we have to break it into smaller pieces. */
1341 int padding = count;
1342 while (padding > 15)
1343 {
1344 padding -= 15;
1345 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1346 patt [14], 15);
1347 }
1348
1349 if (padding)
1350 memcpy (fragP->fr_literal + fragP->fr_fix,
1351 patt [padding - 1], padding);
1352 }
ccc9c027 1353 }
33fef721 1354 fragP->fr_var = count;
252b5132
RH		 1355}
1356
c6fb90c8 1357static INLINE int
0dfbf9d7 1358operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1359{
0dfbf9d7 1360 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1361 {
1362 case 3:
0dfbf9d7 1363 if (x->array[2])
c6fb90c8
L		 1364 return 0;
1365 case 2:
0dfbf9d7 1366 if (x->array[1])
c6fb90c8
L		 1367 return 0;
1368 case 1:
0dfbf9d7 1369 return !x->array[0];
c6fb90c8
L		 1370 default:
1371 abort ();
1372 }
40fb9820
L		 1373}
1374
c6fb90c8 1375static INLINE void
0dfbf9d7 1376operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1377{
0dfbf9d7 1378 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1379 {
1380 case 3:
0dfbf9d7 1381 x->array[2] = v;
c6fb90c8 1382 case 2:
0dfbf9d7 1383 x->array[1] = v;
c6fb90c8 1384 case 1:
0dfbf9d7 1385 x->array[0] = v;
c6fb90c8
L		 1386 break;
1387 default:
1388 abort ();
1389 }
1390}
40fb9820 1391
c6fb90c8 1392static INLINE int
0dfbf9d7
L		 1393operand_type_equal (const union i386_operand_type *x,
1394 const union i386_operand_type *y)
c6fb90c8 1395{
0dfbf9d7 1396 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1397 {
1398 case 3:
0dfbf9d7 1399 if (x->array[2] != y->array[2])
c6fb90c8
L		 1400 return 0;
1401 case 2:
0dfbf9d7 1402 if (x->array[1] != y->array[1])
c6fb90c8
L		 1403 return 0;
1404 case 1:
0dfbf9d7 1405 return x->array[0] == y->array[0];
c6fb90c8
L		 1406 break;
1407 default:
1408 abort ();
1409 }
1410}
40fb9820 1411
0dfbf9d7
L		 1412static INLINE int
1413cpu_flags_all_zero (const union i386_cpu_flags *x)
1414{
1415 switch (ARRAY_SIZE(x->array))
1416 {
1417 case 3:
1418 if (x->array[2])
1419 return 0;
1420 case 2:
1421 if (x->array[1])
1422 return 0;
1423 case 1:
1424 return !x->array[0];
1425 default:
1426 abort ();
1427 }
1428}
1429
1430static INLINE void
1431cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1432{
1433 switch (ARRAY_SIZE(x->array))
1434 {
1435 case 3:
1436 x->array[2] = v;
1437 case 2:
1438 x->array[1] = v;
1439 case 1:
1440 x->array[0] = v;
1441 break;
1442 default:
1443 abort ();
1444 }
1445}
1446
1447static INLINE int
1448cpu_flags_equal (const union i386_cpu_flags *x,
1449 const union i386_cpu_flags *y)
1450{
1451 switch (ARRAY_SIZE(x->array))
1452 {
1453 case 3:
1454 if (x->array[2] != y->array[2])
1455 return 0;
1456 case 2:
1457 if (x->array[1] != y->array[1])
1458 return 0;
1459 case 1:
1460 return x->array[0] == y->array[0];
1461 break;
1462 default:
1463 abort ();
1464 }
1465}
c6fb90c8
L		 1466
1467static INLINE int
1468cpu_flags_check_cpu64 (i386_cpu_flags f)
1469{
1470 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1471 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1472}
1473
c6fb90c8
L		 1474static INLINE i386_cpu_flags
1475cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1476{
c6fb90c8
L		 1477 switch (ARRAY_SIZE (x.array))
1478 {
1479 case 3:
1480 x.array [2] &= y.array [2];
1481 case 2:
1482 x.array [1] &= y.array [1];
1483 case 1:
1484 x.array [0] &= y.array [0];
1485 break;
1486 default:
1487 abort ();
1488 }
1489 return x;
1490}
40fb9820 1491
c6fb90c8
L		 1492static INLINE i386_cpu_flags
1493cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1494{
c6fb90c8 1495 switch (ARRAY_SIZE (x.array))
40fb9820 1496 {
c6fb90c8
L		 1497 case 3:
1498 x.array [2] |= y.array [2];
1499 case 2:
1500 x.array [1] |= y.array [1];
1501 case 1:
1502 x.array [0] |= y.array [0];
40fb9820
L		 1503 break;
1504 default:
1505 abort ();
1506 }
40fb9820
L		 1507 return x;
1508}
1509
309d3373
JB		 1510static INLINE i386_cpu_flags
1511cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1512{
1513 switch (ARRAY_SIZE (x.array))
1514 {
1515 case 3:
1516 x.array [2] &= ~y.array [2];
1517 case 2:
1518 x.array [1] &= ~y.array [1];
1519 case 1:
1520 x.array [0] &= ~y.array [0];
1521 break;
1522 default:
1523 abort ();
1524 }
1525 return x;
1526}
1527
c0f3af97
L		 1528#define CPU_FLAGS_ARCH_MATCH 0x1
1529#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1530#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1531#define CPU_FLAGS_PCLMUL_MATCH 0x8
1532#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1533
a5ff0eb2 1534#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1535 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1536 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1537#define CPU_FLAGS_PERFECT_MATCH \
1538 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1539
1540/* Return CPU flags match bits. */
3629bb00 1541
40fb9820 1542static int
d3ce72d0 1543cpu_flags_match (const insn_template *t)
40fb9820 1544{
c0f3af97
L		 1545 i386_cpu_flags x = t->cpu_flags;
1546 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1547
1548 x.bitfield.cpu64 = 0;
1549 x.bitfield.cpuno64 = 0;
1550
0dfbf9d7 1551 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1552 {
1553 /* This instruction is available on all archs. */
1554 match |= CPU_FLAGS_32BIT_MATCH;
1555 }
3629bb00
L		 1556 else
1557 {
c0f3af97 1558 /* This instruction is available only on some archs. */
3629bb00
L		 1559 i386_cpu_flags cpu = cpu_arch_flags;
1560
1561 cpu.bitfield.cpu64 = 0;
1562 cpu.bitfield.cpuno64 = 0;
1563 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1564 if (!cpu_flags_all_zero (&cpu))
1565 {
a5ff0eb2
L		 1566 if (x.bitfield.cpuavx)
1567 {
ce2f5b3c 1568 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1569 if (cpu.bitfield.cpuavx)
1570 {
1571 /* Check SSE2AVX. */
1572 if (!t->opcode_modifier.sse2avx|| sse2avx)
1573 {
1574 match |= (CPU_FLAGS_ARCH_MATCH
1575 | CPU_FLAGS_AVX_MATCH);
1576 /* Check AES. */
1577 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1578 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1579 /* Check PCLMUL. */
1580 if (!x.bitfield.cpupclmul
1581 || cpu.bitfield.cpupclmul)
1582 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1583 }
1584 }
1585 else
1586 match |= CPU_FLAGS_ARCH_MATCH;
1587 }
1588 else
c0f3af97
L		 1589 match |= CPU_FLAGS_32BIT_MATCH;
1590 }
3629bb00 1591 }
c0f3af97 1592 return match;
40fb9820
L		 1593}
1594
c6fb90c8
L		 1595static INLINE i386_operand_type
1596operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1597{
c6fb90c8
L		 1598 switch (ARRAY_SIZE (x.array))
1599 {
1600 case 3:
1601 x.array [2] &= y.array [2];
1602 case 2:
1603 x.array [1] &= y.array [1];
1604 case 1:
1605 x.array [0] &= y.array [0];
1606 break;
1607 default:
1608 abort ();
1609 }
1610 return x;
40fb9820
L		 1611}
1612
c6fb90c8
L		 1613static INLINE i386_operand_type
1614operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1615{
c6fb90c8 1616 switch (ARRAY_SIZE (x.array))
40fb9820 1617 {
c6fb90c8
L		 1618 case 3:
1619 x.array [2] |= y.array [2];
1620 case 2:
1621 x.array [1] |= y.array [1];
1622 case 1:
1623 x.array [0] |= y.array [0];
40fb9820
L		 1624 break;
1625 default:
1626 abort ();
1627 }
c6fb90c8
L		 1628 return x;
1629}
40fb9820 1630
c6fb90c8
L		 1631static INLINE i386_operand_type
1632operand_type_xor (i386_operand_type x, i386_operand_type y)
1633{
1634 switch (ARRAY_SIZE (x.array))
1635 {
1636 case 3:
1637 x.array [2] ^= y.array [2];
1638 case 2:
1639 x.array [1] ^= y.array [1];
1640 case 1:
1641 x.array [0] ^= y.array [0];
1642 break;
1643 default:
1644 abort ();
1645 }
40fb9820
L		 1646 return x;
1647}
1648
1649static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1650static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1651static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1652static const i386_operand_type inoutportreg
1653 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1654static const i386_operand_type reg16_inoutportreg
1655 = OPERAND_TYPE_REG16_INOUTPORTREG;
1656static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1657static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1658static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1659static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1660static const i386_operand_type anydisp
1661 = OPERAND_TYPE_ANYDISP;
40fb9820 1662static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1663static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1664static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1665static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1666static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1667static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1668static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1669static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1670static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1671static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1672static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1673static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1674static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1675static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1676
1677enum operand_type
1678{
1679 reg,
40fb9820
L		 1680 imm,
1681 disp,
1682 anymem
1683};
1684
c6fb90c8 1685static INLINE int
40fb9820
L		 1686operand_type_check (i386_operand_type t, enum operand_type c)
1687{
1688 switch (c)
1689 {
1690 case reg:
1691 return (t.bitfield.reg8
1692 || t.bitfield.reg16
1693 || t.bitfield.reg32
1694 || t.bitfield.reg64);
1695
40fb9820
L		 1696 case imm:
1697 return (t.bitfield.imm8
1698 || t.bitfield.imm8s
1699 || t.bitfield.imm16
1700 || t.bitfield.imm32
1701 || t.bitfield.imm32s
1702 || t.bitfield.imm64);
1703
1704 case disp:
1705 return (t.bitfield.disp8
1706 || t.bitfield.disp16
1707 || t.bitfield.disp32
1708 || t.bitfield.disp32s
1709 || t.bitfield.disp64);
1710
1711 case anymem:
1712 return (t.bitfield.disp8
1713 || t.bitfield.disp16
1714 || t.bitfield.disp32
1715 || t.bitfield.disp32s
1716 || t.bitfield.disp64
1717 || t.bitfield.baseindex);
1718
1719 default:
1720 abort ();
1721 }
2cfe26b6
AM		 1722
1723 return 0;
40fb9820
L		 1724}
1725
5c07affc
L		 1726/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1727 operand J for instruction template T. */
1728
1729static INLINE int
d3ce72d0 1730match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1731{
1732 return !((i.types[j].bitfield.byte
1733 && !t->operand_types[j].bitfield.byte)
1734 || (i.types[j].bitfield.word
1735 && !t->operand_types[j].bitfield.word)
1736 || (i.types[j].bitfield.dword
1737 && !t->operand_types[j].bitfield.dword)
1738 || (i.types[j].bitfield.qword
1739 && !t->operand_types[j].bitfield.qword));
1740}
1741
1742/* Return 1 if there is no conflict in any size on operand J for
1743 instruction template T. */
1744
1745static INLINE int
d3ce72d0 1746match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1747{
1748 return (match_reg_size (t, j)
1749 && !((i.types[j].bitfield.unspecified
1750 && !t->operand_types[j].bitfield.unspecified)
1751 || (i.types[j].bitfield.fword
1752 && !t->operand_types[j].bitfield.fword)
1753 || (i.types[j].bitfield.tbyte
1754 && !t->operand_types[j].bitfield.tbyte)
1755 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1756 && !t->operand_types[j].bitfield.xmmword)
1757 || (i.types[j].bitfield.ymmword
43234a1e
L		 1758 && !t->operand_types[j].bitfield.ymmword)
1759 || (i.types[j].bitfield.zmmword
1760 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1761}
1762
1763/* Return 1 if there is no size conflict on any operands for
1764 instruction template T. */
1765
1766static INLINE int
d3ce72d0 1767operand_size_match (const insn_template *t)
5c07affc
L		 1768{
1769 unsigned int j;
1770 int match = 1;
1771
1772 /* Don't check jump instructions. */
1773 if (t->opcode_modifier.jump
1774 || t->opcode_modifier.jumpbyte
1775 || t->opcode_modifier.jumpdword
1776 || t->opcode_modifier.jumpintersegment)
1777 return match;
1778
1779 /* Check memory and accumulator operand size. */
1780 for (j = 0; j < i.operands; j++)
1781 {
1782 if (t->operand_types[j].bitfield.anysize)
1783 continue;
1784
1785 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1786 {
1787 match = 0;
1788 break;
1789 }
1790
1791 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1792 {
1793 match = 0;
1794 break;
1795 }
1796 }
1797
891edac4 1798 if (match)
5c07affc 1799 return match;
891edac4
L		 1800 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1801 {
1802mismatch:
86e026a4 1803 i.error = operand_size_mismatch;
891edac4
L		 1804 return 0;
1805 }
5c07affc
L		 1806
1807 /* Check reverse. */
9c2799c2 1808 gas_assert (i.operands == 2);
5c07affc
L		 1809
1810 match = 1;
1811 for (j = 0; j < 2; j++)
1812 {
1813 if (t->operand_types[j].bitfield.acc
1814 && !match_reg_size (t, j ? 0 : 1))
891edac4 1815 goto mismatch;
5c07affc
L		 1816
1817 if (i.types[j].bitfield.mem
1818 && !match_mem_size (t, j ? 0 : 1))
891edac4 1819 goto mismatch;
5c07affc
L		 1820 }
1821
1822 return match;
1823}
1824
c6fb90c8 1825static INLINE int
40fb9820
L		 1826operand_type_match (i386_operand_type overlap,
1827 i386_operand_type given)
1828{
1829 i386_operand_type temp = overlap;
1830
1831 temp.bitfield.jumpabsolute = 0;
7d5e4556 1832 temp.bitfield.unspecified = 0;
5c07affc
L		 1833 temp.bitfield.byte = 0;
1834 temp.bitfield.word = 0;
1835 temp.bitfield.dword = 0;
1836 temp.bitfield.fword = 0;
1837 temp.bitfield.qword = 0;
1838 temp.bitfield.tbyte = 0;
1839 temp.bitfield.xmmword = 0;
c0f3af97 1840 temp.bitfield.ymmword = 0;
43234a1e 1841 temp.bitfield.zmmword = 0;
0dfbf9d7 1842 if (operand_type_all_zero (&temp))
891edac4 1843 goto mismatch;
40fb9820 1844
891edac4
L		 1845 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1846 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1847 return 1;
1848
1849mismatch:
a65babc9 1850 i.error = operand_type_mismatch;
891edac4 1851 return 0;
40fb9820
L		 1852}
1853
7d5e4556 1854/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1855 unless the expected operand type register overlap is null.
1856 Note that Acc in a template matches every size of reg. */
1857
c6fb90c8 1858static INLINE int
40fb9820
L		 1859operand_type_register_match (i386_operand_type m0,
1860 i386_operand_type g0,
1861 i386_operand_type t0,
1862 i386_operand_type m1,
1863 i386_operand_type g1,
1864 i386_operand_type t1)
1865{
1866 if (!operand_type_check (g0, reg))
1867 return 1;
1868
1869 if (!operand_type_check (g1, reg))
1870 return 1;
1871
1872 if (g0.bitfield.reg8 == g1.bitfield.reg8
1873 && g0.bitfield.reg16 == g1.bitfield.reg16
1874 && g0.bitfield.reg32 == g1.bitfield.reg32
1875 && g0.bitfield.reg64 == g1.bitfield.reg64)
1876 return 1;
1877
1878 if (m0.bitfield.acc)
1879 {
1880 t0.bitfield.reg8 = 1;
1881 t0.bitfield.reg16 = 1;
1882 t0.bitfield.reg32 = 1;
1883 t0.bitfield.reg64 = 1;
1884 }
1885
1886 if (m1.bitfield.acc)
1887 {
1888 t1.bitfield.reg8 = 1;
1889 t1.bitfield.reg16 = 1;
1890 t1.bitfield.reg32 = 1;
1891 t1.bitfield.reg64 = 1;
1892 }
1893
891edac4
L		 1894 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1895 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1896 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1897 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1898 return 1;
1899
a65babc9 1900 i.error = register_type_mismatch;
891edac4
L		 1901
1902 return 0;
40fb9820
L		 1903}
1904
4c692bc7
JB		 1905static INLINE unsigned int
1906register_number (const reg_entry *r)
1907{
1908 unsigned int nr = r->reg_num;
1909
1910 if (r->reg_flags & RegRex)
1911 nr += 8;
1912
1913 return nr;
1914}
1915
252b5132 1916static INLINE unsigned int
40fb9820 1917mode_from_disp_size (i386_operand_type t)
252b5132 1918{
43234a1e 1919 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1920 return 1;
1921 else if (t.bitfield.disp16
1922 || t.bitfield.disp32
1923 || t.bitfield.disp32s)
1924 return 2;
1925 else
1926 return 0;
252b5132
RH		 1927}
1928
1929static INLINE int
e3bb37b5 1930fits_in_signed_byte (offsetT num)
252b5132
RH		 1931{
1932 return (num >= -128) && (num <= 127);
47926f60 1933}
252b5132
RH		 1934
1935static INLINE int
e3bb37b5 1936fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1937{
1938 return (num & 0xff) == num;
47926f60 1939}
252b5132
RH		 1940
1941static INLINE int
e3bb37b5 1942fits_in_unsigned_word (offsetT num)
252b5132
RH		 1943{
1944 return (num & 0xffff) == num;
47926f60 1945}
252b5132
RH		 1946
1947static INLINE int
e3bb37b5 1948fits_in_signed_word (offsetT num)
252b5132
RH		 1949{
1950 return (-32768 <= num) && (num <= 32767);
47926f60 1951}
2a962e6d 1952
3e73aa7c 1953static INLINE int
e3bb37b5 1954fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1955{
1956#ifndef BFD64
1957 return 1;
1958#else
1959 return (!(((offsetT) -1 << 31) & num)
1960 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1961#endif
1962} /* fits_in_signed_long() */
2a962e6d 1963
3e73aa7c 1964static INLINE int
e3bb37b5 1965fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1966{
1967#ifndef BFD64
1968 return 1;
1969#else
1970 return (num & (((offsetT) 2 << 31) - 1)) == num;
1971#endif
1972} /* fits_in_unsigned_long() */
252b5132 1973
43234a1e
L		 1974static INLINE int
1975fits_in_vec_disp8 (offsetT num)
1976{
1977 int shift = i.memshift;
1978 unsigned int mask;
1979
1980 if (shift == -1)
1981 abort ();
1982
1983 mask = (1 << shift) - 1;
1984
1985 /* Return 0 if NUM isn't properly aligned. */
1986 if ((num & mask))
1987 return 0;
1988
1989 /* Check if NUM will fit in 8bit after shift. */
1990 return fits_in_signed_byte (num >> shift);
1991}
1992
a683cc34
SP		 1993static INLINE int
1994fits_in_imm4 (offsetT num)
1995{
1996 return (num & 0xf) == num;
1997}
1998
40fb9820 1999static i386_operand_type
e3bb37b5 2000smallest_imm_type (offsetT num)
252b5132 2001{
40fb9820 2002 i386_operand_type t;
7ab9ffdd 2003
0dfbf9d7 2004 operand_type_set (&t, 0);
40fb9820
L		 2005 t.bitfield.imm64 = 1;
2006
2007 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2008 {
2009 /* This code is disabled on the 486 because all the Imm1 forms
2010 in the opcode table are slower on the i486. They're the
2011 versions with the implicitly specified single-position
2012 displacement, which has another syntax if you really want to
2013 use that form. */
40fb9820
L		 2014 t.bitfield.imm1 = 1;
2015 t.bitfield.imm8 = 1;
2016 t.bitfield.imm8s = 1;
2017 t.bitfield.imm16 = 1;
2018 t.bitfield.imm32 = 1;
2019 t.bitfield.imm32s = 1;
2020 }
2021 else if (fits_in_signed_byte (num))
2022 {
2023 t.bitfield.imm8 = 1;
2024 t.bitfield.imm8s = 1;
2025 t.bitfield.imm16 = 1;
2026 t.bitfield.imm32 = 1;
2027 t.bitfield.imm32s = 1;
2028 }
2029 else if (fits_in_unsigned_byte (num))
2030 {
2031 t.bitfield.imm8 = 1;
2032 t.bitfield.imm16 = 1;
2033 t.bitfield.imm32 = 1;
2034 t.bitfield.imm32s = 1;
2035 }
2036 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2037 {
2038 t.bitfield.imm16 = 1;
2039 t.bitfield.imm32 = 1;
2040 t.bitfield.imm32s = 1;
2041 }
2042 else if (fits_in_signed_long (num))
2043 {
2044 t.bitfield.imm32 = 1;
2045 t.bitfield.imm32s = 1;
2046 }
2047 else if (fits_in_unsigned_long (num))
2048 t.bitfield.imm32 = 1;
2049
2050 return t;
47926f60 2051}
252b5132 2052
847f7ad4 2053static offsetT
e3bb37b5 2054offset_in_range (offsetT val, int size)
847f7ad4 2055{
508866be 2056 addressT mask;
ba2adb93 2057
847f7ad4
AM		 2058 switch (size)
2059 {
508866be
L		 2060 case 1: mask = ((addressT) 1 << 8) - 1; break;
2061 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2062 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2063#ifdef BFD64
2064 case 8: mask = ((addressT) 2 << 63) - 1; break;
2065#endif
47926f60 2066 default: abort ();
847f7ad4
AM		 2067 }
2068
9de868bf
L		 2069#ifdef BFD64
2070 /* If BFD64, sign extend val for 32bit address mode. */
2071 if (flag_code != CODE_64BIT
2072 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2073 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2074 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2075#endif
ba2adb93 2076
47926f60 2077 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2078 {
2079 char buf1[40], buf2[40];
2080
2081 sprint_value (buf1, val);
2082 sprint_value (buf2, val & mask);
2083 as_warn (_("%s shortened to %s"), buf1, buf2);
2084 }
2085 return val & mask;
2086}
2087
c32fa91d
L		 2088enum PREFIX_GROUP
2089{
2090 PREFIX_EXIST = 0,
2091 PREFIX_LOCK,
2092 PREFIX_REP,
2093 PREFIX_OTHER
2094};
2095
2096/* Returns
2097 a. PREFIX_EXIST if attempting to add a prefix where one from the
2098 same class already exists.
2099 b. PREFIX_LOCK if lock prefix is added.
2100 c. PREFIX_REP if rep/repne prefix is added.
2101 d. PREFIX_OTHER if other prefix is added.
2102 */
2103
2104static enum PREFIX_GROUP
e3bb37b5 2105add_prefix (unsigned int prefix)
252b5132 2106{
c32fa91d 2107 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2108 unsigned int q;
252b5132 2109
29b0f896
AM		 2110 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2111 && flag_code == CODE_64BIT)
b1905489 2112 {
161a04f6
L		 2113 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2114 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2115 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2116 ret = PREFIX_EXIST;
b1905489
JB		 2117 q = REX_PREFIX;
2118 }
3e73aa7c 2119 else
b1905489
JB		 2120 {
2121 switch (prefix)
2122 {
2123 default:
2124 abort ();
2125
2126 case CS_PREFIX_OPCODE:
2127 case DS_PREFIX_OPCODE:
2128 case ES_PREFIX_OPCODE:
2129 case FS_PREFIX_OPCODE:
2130 case GS_PREFIX_OPCODE:
2131 case SS_PREFIX_OPCODE:
2132 q = SEG_PREFIX;
2133 break;
2134
2135 case REPNE_PREFIX_OPCODE:
2136 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2137 q = REP_PREFIX;
2138 ret = PREFIX_REP;
2139 break;
2140
b1905489 2141 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2142 q = LOCK_PREFIX;
2143 ret = PREFIX_LOCK;
b1905489
JB		 2144 break;
2145
2146 case FWAIT_OPCODE:
2147 q = WAIT_PREFIX;
2148 break;
2149
2150 case ADDR_PREFIX_OPCODE:
2151 q = ADDR_PREFIX;
2152 break;
2153
2154 case DATA_PREFIX_OPCODE:
2155 q = DATA_PREFIX;
2156 break;
2157 }
2158 if (i.prefix[q] != 0)
c32fa91d 2159 ret = PREFIX_EXIST;
b1905489 2160 }
252b5132 2161
b1905489 2162 if (ret)
252b5132 2163 {
b1905489
JB		 2164 if (!i.prefix[q])
2165 ++i.prefixes;
2166 i.prefix[q] |= prefix;
252b5132 2167 }
b1905489
JB		 2168 else
2169 as_bad (_("same type of prefix used twice"));
252b5132 2170
252b5132
RH		 2171 return ret;
2172}
2173
2174static void
78f12dd3 2175update_code_flag (int value, int check)
eecb386c 2176{
78f12dd3
L		 2177 PRINTF_LIKE ((*as_error));
2178
1e9cc1c2 2179 flag_code = (enum flag_code) value;
40fb9820
L		 2180 if (flag_code == CODE_64BIT)
2181 {
2182 cpu_arch_flags.bitfield.cpu64 = 1;
2183 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2184 }
2185 else
2186 {
2187 cpu_arch_flags.bitfield.cpu64 = 0;
2188 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2189 }
2190 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2191 {
78f12dd3
L		 2192 if (check)
2193 as_error = as_fatal;
2194 else
2195 as_error = as_bad;
2196 (*as_error) (_("64bit mode not supported on `%s'."),
2197 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2198 }
40fb9820 2199 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2200 {
78f12dd3
L		 2201 if (check)
2202 as_error = as_fatal;
2203 else
2204 as_error = as_bad;
2205 (*as_error) (_("32bit mode not supported on `%s'."),
2206 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2207 }
eecb386c
AM		 2208 stackop_size = '\0';
2209}
2210
78f12dd3
L		 2211static void
2212set_code_flag (int value)
2213{
2214 update_code_flag (value, 0);
2215}
2216
eecb386c 2217static void
e3bb37b5 2218set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2219{
1e9cc1c2 2220 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2221 if (flag_code != CODE_16BIT)
2222 abort ();
2223 cpu_arch_flags.bitfield.cpu64 = 0;
2224 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2225 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2226}
2227
2228static void
e3bb37b5 2229set_intel_syntax (int syntax_flag)
252b5132
RH		 2230{
2231 /* Find out if register prefixing is specified. */
2232 int ask_naked_reg = 0;
2233
2234 SKIP_WHITESPACE ();
29b0f896 2235 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2236 {
2237 char *string = input_line_pointer;
2238 int e = get_symbol_end ();
2239
47926f60 2240 if (strcmp (string, "prefix") == 0)
252b5132 2241 ask_naked_reg = 1;
47926f60 2242 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2243 ask_naked_reg = -1;
2244 else
d0b47220 2245 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2246 *input_line_pointer = e;
2247 }
2248 demand_empty_rest_of_line ();
c3332e24 2249
252b5132
RH		 2250 intel_syntax = syntax_flag;
2251
2252 if (ask_naked_reg == 0)
f86103b7
AM		 2253 allow_naked_reg = (intel_syntax
2254 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2255 else
2256 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2257
ee86248c 2258 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2259
e4a3b5a4 2260 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2261 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2262 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2263}
2264
1efbbeb4
L		 2265static void
2266set_intel_mnemonic (int mnemonic_flag)
2267{
e1d4d893 2268 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2269}
2270
db51cc60
L		 2271static void
2272set_allow_index_reg (int flag)
2273{
2274 allow_index_reg = flag;
2275}
2276
cb19c032 2277static void
7bab8ab5 2278set_check (int what)
cb19c032 2279{
7bab8ab5
JB		 2280 enum check_kind *kind;
2281 const char *str;
2282
2283 if (what)
2284 {
2285 kind = &operand_check;
2286 str = "operand";
2287 }
2288 else
2289 {
2290 kind = &sse_check;
2291 str = "sse";
2292 }
2293
cb19c032
L		 2294 SKIP_WHITESPACE ();
2295
2296 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2297 {
2298 char *string = input_line_pointer;
2299 int e = get_symbol_end ();
2300
2301 if (strcmp (string, "none") == 0)
7bab8ab5 2302 *kind = check_none;
cb19c032 2303 else if (strcmp (string, "warning") == 0)
7bab8ab5 2304 *kind = check_warning;
cb19c032 2305 else if (strcmp (string, "error") == 0)
7bab8ab5 2306 *kind = check_error;
cb19c032 2307 else
7bab8ab5 2308 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2309 *input_line_pointer = e;
2310 }
2311 else
7bab8ab5 2312 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2313
2314 demand_empty_rest_of_line ();
2315}
2316
8a9036a4
L		 2317static void
2318check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2319 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2320{
2321#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2322 static const char *arch;
2323
2324 /* Intel LIOM is only supported on ELF. */
2325 if (!IS_ELF)
2326 return;
2327
2328 if (!arch)
2329 {
2330 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2331 use default_arch. */
2332 arch = cpu_arch_name;
2333 if (!arch)
2334 arch = default_arch;
2335 }
2336
3632d14b 2337 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2338 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2339 || new_flag.bitfield.cpul1om)
8a9036a4 2340 return;
76ba9986 2341
7a9068fe
L		 2342 /* If we are targeting Intel K1OM, we must enable it. */
2343 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2344 || new_flag.bitfield.cpuk1om)
2345 return;
2346
8a9036a4
L		 2347 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2348#endif
2349}
2350
e413e4e9 2351static void
e3bb37b5 2352set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2353{
47926f60 2354 SKIP_WHITESPACE ();
e413e4e9 2355
29b0f896 2356 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2357 {
2358 char *string = input_line_pointer;
2359 int e = get_symbol_end ();
91d6fa6a 2360 unsigned int j;
40fb9820 2361 i386_cpu_flags flags;
e413e4e9 2362
91d6fa6a 2363 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2364 {
91d6fa6a 2365 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2366 {
91d6fa6a 2367 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2368
5c6af06e
JB		 2369 if (*string != '.')
2370 {
91d6fa6a 2371 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2372 cpu_sub_arch_name = NULL;
91d6fa6a 2373 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2374 if (flag_code == CODE_64BIT)
2375 {
2376 cpu_arch_flags.bitfield.cpu64 = 1;
2377 cpu_arch_flags.bitfield.cpuno64 = 0;
2378 }
2379 else
2380 {
2381 cpu_arch_flags.bitfield.cpu64 = 0;
2382 cpu_arch_flags.bitfield.cpuno64 = 1;
2383 }
91d6fa6a
NC		 2384 cpu_arch_isa = cpu_arch[j].type;
2385 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2386 if (!cpu_arch_tune_set)
2387 {
2388 cpu_arch_tune = cpu_arch_isa;
2389 cpu_arch_tune_flags = cpu_arch_isa_flags;
2390 }
5c6af06e
JB		 2391 break;
2392 }
40fb9820 2393
22109423 2394 if (!cpu_arch[j].negated)
309d3373 2395 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2396 cpu_arch[j].flags);
309d3373
JB		 2397 else
2398 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2399 cpu_arch[j].flags);
0dfbf9d7 2400 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2401 {
6305a203
L		 2402 if (cpu_sub_arch_name)
2403 {
2404 char *name = cpu_sub_arch_name;
2405 cpu_sub_arch_name = concat (name,
91d6fa6a 2406 cpu_arch[j].name,
1bf57e9f 2407 (const char *) NULL);
6305a203
L		 2408 free (name);
2409 }
2410 else
91d6fa6a 2411 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2412 cpu_arch_flags = flags;
a586129e 2413 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2414 }
2415 *input_line_pointer = e;
2416 demand_empty_rest_of_line ();
2417 return;
e413e4e9
AM		 2418 }
2419 }
91d6fa6a 2420 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2421 as_bad (_("no such architecture: `%s'"), string);
2422
2423 *input_line_pointer = e;
2424 }
2425 else
2426 as_bad (_("missing cpu architecture"));
2427
fddf5b5b
AM		 2428 no_cond_jump_promotion = 0;
2429 if (*input_line_pointer == ','
29b0f896 2430 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2431 {
2432 char *string = ++input_line_pointer;
2433 int e = get_symbol_end ();
2434
2435 if (strcmp (string, "nojumps") == 0)
2436 no_cond_jump_promotion = 1;
2437 else if (strcmp (string, "jumps") == 0)
2438 ;
2439 else
2440 as_bad (_("no such architecture modifier: `%s'"), string);
2441
2442 *input_line_pointer = e;
2443 }
2444
e413e4e9
AM		 2445 demand_empty_rest_of_line ();
2446}
2447
8a9036a4
L		 2448enum bfd_architecture
2449i386_arch (void)
2450{
3632d14b 2451 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2452 {
2453 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2454 || flag_code != CODE_64BIT)
2455 as_fatal (_("Intel L1OM is 64bit ELF only"));
2456 return bfd_arch_l1om;
2457 }
7a9068fe
L		 2458 else if (cpu_arch_isa == PROCESSOR_K1OM)
2459 {
2460 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2461 || flag_code != CODE_64BIT)
2462 as_fatal (_("Intel K1OM is 64bit ELF only"));
2463 return bfd_arch_k1om;
2464 }
8a9036a4
L		 2465 else
2466 return bfd_arch_i386;
2467}
2468
b9d79e03 2469unsigned long
7016a5d5 2470i386_mach (void)
b9d79e03 2471{
351f65ca 2472 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2473 {
3632d14b 2474 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2475 {
351f65ca
L		 2476 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2477 || default_arch[6] != '\0')
8a9036a4
L		 2478 as_fatal (_("Intel L1OM is 64bit ELF only"));
2479 return bfd_mach_l1om;
2480 }
7a9068fe
L		 2481 else if (cpu_arch_isa == PROCESSOR_K1OM)
2482 {
2483 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2484 || default_arch[6] != '\0')
2485 as_fatal (_("Intel K1OM is 64bit ELF only"));
2486 return bfd_mach_k1om;
2487 }
351f65ca 2488 else if (default_arch[6] == '\0')
8a9036a4 2489 return bfd_mach_x86_64;
351f65ca
L		 2490 else
2491 return bfd_mach_x64_32;
8a9036a4 2492 }
b9d79e03
JH		 2493 else if (!strcmp (default_arch, "i386"))
2494 return bfd_mach_i386_i386;
2495 else
2b5d6a91 2496 as_fatal (_("unknown architecture"));
b9d79e03 2497}
b9d79e03 2498\f
252b5132 2499void
7016a5d5 2500md_begin (void)
252b5132
RH		 2501{
2502 const char *hash_err;
2503
47926f60 2504 /* Initialize op_hash hash table. */
252b5132
RH		 2505 op_hash = hash_new ();
2506
2507 {
d3ce72d0 2508 const insn_template *optab;
29b0f896 2509 templates *core_optab;
252b5132 2510
47926f60
KH		 2511 /* Setup for loop. */
2512 optab = i386_optab;
252b5132
RH		 2513 core_optab = (templates *) xmalloc (sizeof (templates));
2514 core_optab->start = optab;
2515
2516 while (1)
2517 {
2518 ++optab;
2519 if (optab->name == NULL
2520 || strcmp (optab->name, (optab - 1)->name) != 0)
2521 {
2522 /* different name --> ship out current template list;
47926f60 2523 add to hash table; & begin anew. */
252b5132
RH		 2524 core_optab->end = optab;
2525 hash_err = hash_insert (op_hash,
2526 (optab - 1)->name,
5a49b8ac 2527 (void *) core_optab);
252b5132
RH		 2528 if (hash_err)
2529 {
b37df7c4 2530 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2531 (optab - 1)->name,
2532 hash_err);
2533 }
2534 if (optab->name == NULL)
2535 break;
2536 core_optab = (templates *) xmalloc (sizeof (templates));
2537 core_optab->start = optab;
2538 }
2539 }
2540 }
2541
47926f60 2542 /* Initialize reg_hash hash table. */
252b5132
RH		 2543 reg_hash = hash_new ();
2544 {
29b0f896 2545 const reg_entry *regtab;
c3fe08fa 2546 unsigned int regtab_size = i386_regtab_size;
252b5132 2547
c3fe08fa 2548 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2549 {
5a49b8ac 2550 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2551 if (hash_err)
b37df7c4 2552 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2553 regtab->reg_name,
2554 hash_err);
252b5132
RH		 2555 }
2556 }
2557
47926f60 2558 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2559 {
29b0f896
AM		 2560 int c;
2561 char *p;
252b5132
RH		 2562
2563 for (c = 0; c < 256; c++)
2564 {
3882b010 2565 if (ISDIGIT (c))
252b5132
RH		 2566 {
2567 digit_chars[c] = c;
2568 mnemonic_chars[c] = c;
2569 register_chars[c] = c;
2570 operand_chars[c] = c;
2571 }
3882b010 2572 else if (ISLOWER (c))
252b5132
RH		 2573 {
2574 mnemonic_chars[c] = c;
2575 register_chars[c] = c;
2576 operand_chars[c] = c;
2577 }
3882b010 2578 else if (ISUPPER (c))
252b5132 2579 {
3882b010 2580 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2581 register_chars[c] = mnemonic_chars[c];
2582 operand_chars[c] = c;
2583 }
43234a1e
L		 2584 else if (c == '{' || c == '}')
2585 operand_chars[c] = c;
252b5132 2586
3882b010 2587 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2588 identifier_chars[c] = c;
2589 else if (c >= 128)
2590 {
2591 identifier_chars[c] = c;
2592 operand_chars[c] = c;
2593 }
2594 }
2595
2596#ifdef LEX_AT
2597 identifier_chars['@'] = '@';
32137342
NC		 2598#endif
2599#ifdef LEX_QM
2600 identifier_chars['?'] = '?';
2601 operand_chars['?'] = '?';
252b5132 2602#endif
252b5132 2603 digit_chars['-'] = '-';
c0f3af97 2604 mnemonic_chars['_'] = '_';
791fe849 2605 mnemonic_chars['-'] = '-';
0003779b 2606 mnemonic_chars['.'] = '.';
252b5132
RH		 2607 identifier_chars['_'] = '_';
2608 identifier_chars['.'] = '.';
2609
2610 for (p = operand_special_chars; *p != '\0'; p++)
2611 operand_chars[(unsigned char) *p] = *p;
2612 }
2613
a4447b93
RH		 2614 if (flag_code == CODE_64BIT)
2615 {
ca19b261
KT		 2616#if defined (OBJ_COFF) && defined (TE_PE)
2617 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2618 ? 32 : 16);
2619#else
a4447b93 2620 x86_dwarf2_return_column = 16;
ca19b261 2621#endif
61ff971f 2622 x86_cie_data_alignment = -8;
a4447b93
RH		 2623 }
2624 else
2625 {
2626 x86_dwarf2_return_column = 8;
2627 x86_cie_data_alignment = -4;
2628 }
252b5132
RH		 2629}
2630
2631void
e3bb37b5 2632i386_print_statistics (FILE *file)
252b5132
RH		 2633{
2634 hash_print_statistics (file, "i386 opcode", op_hash);
2635 hash_print_statistics (file, "i386 register", reg_hash);
2636}
2637\f
252b5132
RH		 2638#ifdef DEBUG386
2639
ce8a8b2f 2640/* Debugging routines for md_assemble. */
d3ce72d0 2641static void pte (insn_template *);
40fb9820 2642static void pt (i386_operand_type);
e3bb37b5
L		 2643static void pe (expressionS *);
2644static void ps (symbolS *);
252b5132
RH		 2645
2646static void
e3bb37b5 2647pi (char *line, i386_insn *x)
252b5132 2648{
09137c09 2649 unsigned int j;
252b5132
RH		 2650
2651 fprintf (stdout, "%s: template ", line);
2652 pte (&x->tm);
09f131f2
JH		 2653 fprintf (stdout, " address: base %s index %s scale %x\n",
2654 x->base_reg ? x->base_reg->reg_name : "none",
2655 x->index_reg ? x->index_reg->reg_name : "none",
2656 x->log2_scale_factor);
2657 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2658 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2659 fprintf (stdout, " sib: base %x index %x scale %x\n",
2660 x->sib.base, x->sib.index, x->sib.scale);
2661 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2662 (x->rex & REX_W) != 0,
2663 (x->rex & REX_R) != 0,
2664 (x->rex & REX_X) != 0,
2665 (x->rex & REX_B) != 0);
09137c09 2666 for (j = 0; j < x->operands; j++)
252b5132 2667 {
09137c09
SP		 2668 fprintf (stdout, " #%d: ", j + 1);
2669 pt (x->types[j]);
252b5132 2670 fprintf (stdout, "\n");
09137c09
SP		 2671 if (x->types[j].bitfield.reg8
2672 || x->types[j].bitfield.reg16
2673 || x->types[j].bitfield.reg32
2674 || x->types[j].bitfield.reg64
2675 || x->types[j].bitfield.regmmx
2676 || x->types[j].bitfield.regxmm
2677 || x->types[j].bitfield.regymm
43234a1e 2678 || x->types[j].bitfield.regzmm
09137c09
SP		 2679 || x->types[j].bitfield.sreg2
2680 || x->types[j].bitfield.sreg3
2681 || x->types[j].bitfield.control
2682 || x->types[j].bitfield.debug
2683 || x->types[j].bitfield.test)
2684 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2685 if (operand_type_check (x->types[j], imm))
2686 pe (x->op[j].imms);
2687 if (operand_type_check (x->types[j], disp))
2688 pe (x->op[j].disps);
252b5132
RH		 2689 }
2690}
2691
2692static void
d3ce72d0 2693pte (insn_template *t)
252b5132 2694{
09137c09 2695 unsigned int j;
252b5132 2696 fprintf (stdout, " %d operands ", t->operands);
47926f60 2697 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2698 if (t->extension_opcode != None)
2699 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2700 if (t->opcode_modifier.d)
252b5132 2701 fprintf (stdout, "D");
40fb9820 2702 if (t->opcode_modifier.w)
252b5132
RH		 2703 fprintf (stdout, "W");
2704 fprintf (stdout, "\n");
09137c09 2705 for (j = 0; j < t->operands; j++)
252b5132 2706 {
09137c09
SP		 2707 fprintf (stdout, " #%d type ", j + 1);
2708 pt (t->operand_types[j]);
252b5132
RH		 2709 fprintf (stdout, "\n");
2710 }
2711}
2712
2713static void
e3bb37b5 2714pe (expressionS *e)
252b5132 2715{
24eab124 2716 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2717 fprintf (stdout, " add_number %ld (%lx)\n",
2718 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2719 if (e->X_add_symbol)
2720 {
2721 fprintf (stdout, " add_symbol ");
2722 ps (e->X_add_symbol);
2723 fprintf (stdout, "\n");
2724 }
2725 if (e->X_op_symbol)
2726 {
2727 fprintf (stdout, " op_symbol ");
2728 ps (e->X_op_symbol);
2729 fprintf (stdout, "\n");
2730 }
2731}
2732
2733static void
e3bb37b5 2734ps (symbolS *s)
252b5132
RH		 2735{
2736 fprintf (stdout, "%s type %s%s",
2737 S_GET_NAME (s),
2738 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2739 segment_name (S_GET_SEGMENT (s)));
2740}
2741
7b81dfbb 2742static struct type_name
252b5132 2743 {
40fb9820
L		 2744 i386_operand_type mask;
2745 const char *name;
252b5132 2746 }
7b81dfbb 2747const type_names[] =
252b5132 2748{
40fb9820
L		 2749 { OPERAND_TYPE_REG8, "r8" },
2750 { OPERAND_TYPE_REG16, "r16" },
2751 { OPERAND_TYPE_REG32, "r32" },
2752 { OPERAND_TYPE_REG64, "r64" },
2753 { OPERAND_TYPE_IMM8, "i8" },
2754 { OPERAND_TYPE_IMM8, "i8s" },
2755 { OPERAND_TYPE_IMM16, "i16" },
2756 { OPERAND_TYPE_IMM32, "i32" },
2757 { OPERAND_TYPE_IMM32S, "i32s" },
2758 { OPERAND_TYPE_IMM64, "i64" },
2759 { OPERAND_TYPE_IMM1, "i1" },
2760 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2761 { OPERAND_TYPE_DISP8, "d8" },
2762 { OPERAND_TYPE_DISP16, "d16" },
2763 { OPERAND_TYPE_DISP32, "d32" },
2764 { OPERAND_TYPE_DISP32S, "d32s" },
2765 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2766 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2767 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2768 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2769 { OPERAND_TYPE_CONTROL, "control reg" },
2770 { OPERAND_TYPE_TEST, "test reg" },
2771 { OPERAND_TYPE_DEBUG, "debug reg" },
2772 { OPERAND_TYPE_FLOATREG, "FReg" },
2773 { OPERAND_TYPE_FLOATACC, "FAcc" },
2774 { OPERAND_TYPE_SREG2, "SReg2" },
2775 { OPERAND_TYPE_SREG3, "SReg3" },
2776 { OPERAND_TYPE_ACC, "Acc" },
2777 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2778 { OPERAND_TYPE_REGMMX, "rMMX" },
2779 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2780 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2781 { OPERAND_TYPE_REGZMM, "rZMM" },
2782 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2783 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2784};
2785
2786static void
40fb9820 2787pt (i386_operand_type t)
252b5132 2788{
40fb9820 2789 unsigned int j;
c6fb90c8 2790 i386_operand_type a;
252b5132 2791
40fb9820 2792 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2793 {
2794 a = operand_type_and (t, type_names[j].mask);
0349dc08 2795 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2796 fprintf (stdout, "%s, ", type_names[j].name);
2797 }
252b5132
RH		 2798 fflush (stdout);
2799}
2800
2801#endif /* DEBUG386 */
2802\f
252b5132 2803static bfd_reloc_code_real_type
3956db08 2804reloc (unsigned int size,
64e74474
AM		 2805 int pcrel,
2806 int sign,
c3320543 2807 int bnd_prefix,
64e74474 2808 bfd_reloc_code_real_type other)
252b5132 2809{
47926f60 2810 if (other != NO_RELOC)
3956db08 2811 {
91d6fa6a 2812 reloc_howto_type *rel;
3956db08
JB		 2813
2814 if (size == 8)
2815 switch (other)
2816 {
64e74474
AM		 2817 case BFD_RELOC_X86_64_GOT32:
2818 return BFD_RELOC_X86_64_GOT64;
2819 break;
2820 case BFD_RELOC_X86_64_PLTOFF64:
2821 return BFD_RELOC_X86_64_PLTOFF64;
2822 break;
2823 case BFD_RELOC_X86_64_GOTPC32:
2824 other = BFD_RELOC_X86_64_GOTPC64;
2825 break;
2826 case BFD_RELOC_X86_64_GOTPCREL:
2827 other = BFD_RELOC_X86_64_GOTPCREL64;
2828 break;
2829 case BFD_RELOC_X86_64_TPOFF32:
2830 other = BFD_RELOC_X86_64_TPOFF64;
2831 break;
2832 case BFD_RELOC_X86_64_DTPOFF32:
2833 other = BFD_RELOC_X86_64_DTPOFF64;
2834 break;
2835 default:
2836 break;
3956db08 2837 }
e05278af 2838
8ce3d284 2839#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2840 if (other == BFD_RELOC_SIZE32)
2841 {
2842 if (size == 8)
2843 return BFD_RELOC_SIZE64;
2844 if (pcrel)
2845 as_bad (_("there are no pc-relative size relocations"));
2846 }
8ce3d284 2847#endif
8fd4256d 2848
e05278af 2849 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2850 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2851 sign = -1;
2852
91d6fa6a
NC		 2853 rel = bfd_reloc_type_lookup (stdoutput, other);
2854 if (!rel)
3956db08 2855 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2856 else if (size != bfd_get_reloc_size (rel))
3956db08 2857 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2858 bfd_get_reloc_size (rel),
3956db08 2859 size);
91d6fa6a 2860 else if (pcrel && !rel->pc_relative)
3956db08 2861 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2862 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2863 && !sign)
91d6fa6a 2864 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2865 && sign > 0))
3956db08
JB		 2866 as_bad (_("relocated field and relocation type differ in signedness"));
2867 else
2868 return other;
2869 return NO_RELOC;
2870 }
252b5132
RH		 2871
2872 if (pcrel)
2873 {
3e73aa7c 2874 if (!sign)
3956db08 2875 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2876 switch (size)
2877 {
2878 case 1: return BFD_RELOC_8_PCREL;
2879 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2880 case 4: return (bnd_prefix && object_64bit
2881 ? BFD_RELOC_X86_64_PC32_BND
2882 : BFD_RELOC_32_PCREL);
d6ab8113 2883 case 8: return BFD_RELOC_64_PCREL;
252b5132 2884 }
3956db08 2885 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2886 }
2887 else
2888 {
3956db08 2889 if (sign > 0)
e5cb08ac 2890 switch (size)
3e73aa7c
JH		 2891 {
2892 case 4: return BFD_RELOC_X86_64_32S;
2893 }
2894 else
2895 switch (size)
2896 {
2897 case 1: return BFD_RELOC_8;
2898 case 2: return BFD_RELOC_16;
2899 case 4: return BFD_RELOC_32;
2900 case 8: return BFD_RELOC_64;
2901 }
3956db08
JB		 2902 as_bad (_("cannot do %s %u byte relocation"),
2903 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2904 }
2905
0cc9e1d3 2906 return NO_RELOC;
252b5132
RH		 2907}
2908
47926f60
KH		 2909/* Here we decide which fixups can be adjusted to make them relative to
2910 the beginning of the section instead of the symbol. Basically we need
2911 to make sure that the dynamic relocations are done correctly, so in
2912 some cases we force the original symbol to be used. */
2913
252b5132 2914int
e3bb37b5 2915tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2916{
6d249963 2917#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2918 if (!IS_ELF)
31312f95
AM		 2919 return 1;
2920
a161fe53
AM		 2921 /* Don't adjust pc-relative references to merge sections in 64-bit
2922 mode. */
2923 if (use_rela_relocations
2924 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2925 && fixP->fx_pcrel)
252b5132 2926 return 0;
31312f95 2927
8d01d9a9
AJ		 2928 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2929 and changed later by validate_fix. */
2930 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2931 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2932 return 0;
2933
8fd4256d
L		 2934 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2935 for size relocations. */
2936 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2937 || fixP->fx_r_type == BFD_RELOC_SIZE64
2938 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2939 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2940 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2944 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2945 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2946 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2947 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2948 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2949 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2950 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2951 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2954 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2955 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2956 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2957 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2958 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2959 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2960 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2961 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2962 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2963 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2964 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2965 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2966 return 0;
31312f95 2967#endif
252b5132
RH		 2968 return 1;
2969}
252b5132 2970
b4cac588 2971static int
e3bb37b5 2972intel_float_operand (const char *mnemonic)
252b5132 2973{
9306ca4a
JB		 2974 /* Note that the value returned is meaningful only for opcodes with (memory)
2975 operands, hence the code here is free to improperly handle opcodes that
2976 have no operands (for better performance and smaller code). */
2977
2978 if (mnemonic[0] != 'f')
2979 return 0; /* non-math */
2980
2981 switch (mnemonic[1])
2982 {
2983 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2984 the fs segment override prefix not currently handled because no
2985 call path can make opcodes without operands get here */
2986 case 'i':
2987 return 2 /* integer op */;
2988 case 'l':
2989 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2990 return 3; /* fldcw/fldenv */
2991 break;
2992 case 'n':
2993 if (mnemonic[2] != 'o' /* fnop */)
2994 return 3; /* non-waiting control op */
2995 break;
2996 case 'r':
2997 if (mnemonic[2] == 's')
2998 return 3; /* frstor/frstpm */
2999 break;
3000 case 's':
3001 if (mnemonic[2] == 'a')
3002 return 3; /* fsave */
3003 if (mnemonic[2] == 't')
3004 {
3005 switch (mnemonic[3])
3006 {
3007 case 'c': /* fstcw */
3008 case 'd': /* fstdw */
3009 case 'e': /* fstenv */
3010 case 's': /* fsts[gw] */
3011 return 3;
3012 }
3013 }
3014 break;
3015 case 'x':
3016 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3017 return 0; /* fxsave/fxrstor are not really math ops */
3018 break;
3019 }
252b5132 3020
9306ca4a 3021 return 1;
252b5132
RH		 3022}
3023
c0f3af97
L		 3024/* Build the VEX prefix. */
3025
3026static void
d3ce72d0 3027build_vex_prefix (const insn_template *t)
c0f3af97
L		 3028{
3029 unsigned int register_specifier;
3030 unsigned int implied_prefix;
3031 unsigned int vector_length;
3032
3033 /* Check register specifier. */
3034 if (i.vex.register_specifier)
43234a1e
L		 3035 {
3036 register_specifier =
3037 ~register_number (i.vex.register_specifier) & 0xf;
3038 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3039 }
c0f3af97
L		 3040 else
3041 register_specifier = 0xf;
3042
fa99fab2
L		 3043 /* Use 2-byte VEX prefix by swappping destination and source
3044 operand. */
3045 if (!i.swap_operand
3046 && i.operands == i.reg_operands
7f399153 3047 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3048 && i.tm.opcode_modifier.s
3049 && i.rex == REX_B)
3050 {
3051 unsigned int xchg = i.operands - 1;
3052 union i386_op temp_op;
3053 i386_operand_type temp_type;
3054
3055 temp_type = i.types[xchg];
3056 i.types[xchg] = i.types[0];
3057 i.types[0] = temp_type;
3058 temp_op = i.op[xchg];
3059 i.op[xchg] = i.op[0];
3060 i.op[0] = temp_op;
3061
9c2799c2 3062 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3063
3064 i.rex = REX_R;
3065 xchg = i.rm.regmem;
3066 i.rm.regmem = i.rm.reg;
3067 i.rm.reg = xchg;
3068
3069 /* Use the next insn. */
3070 i.tm = t[1];
3071 }
3072
539f890d
L		 3073 if (i.tm.opcode_modifier.vex == VEXScalar)
3074 vector_length = avxscalar;
3075 else
3076 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3077
3078 switch ((i.tm.base_opcode >> 8) & 0xff)
3079 {
3080 case 0:
3081 implied_prefix = 0;
3082 break;
3083 case DATA_PREFIX_OPCODE:
3084 implied_prefix = 1;
3085 break;
3086 case REPE_PREFIX_OPCODE:
3087 implied_prefix = 2;
3088 break;
3089 case REPNE_PREFIX_OPCODE:
3090 implied_prefix = 3;
3091 break;
3092 default:
3093 abort ();
3094 }
3095
3096 /* Use 2-byte VEX prefix if possible. */
7f399153 3097 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3098 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3099 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3100 {
3101 /* 2-byte VEX prefix. */
3102 unsigned int r;
3103
3104 i.vex.length = 2;
3105 i.vex.bytes[0] = 0xc5;
3106
3107 /* Check the REX.R bit. */
3108 r = (i.rex & REX_R) ? 0 : 1;
3109 i.vex.bytes[1] = (r << 7
3110 | register_specifier << 3
3111 | vector_length << 2
3112 | implied_prefix);
3113 }
3114 else
3115 {
3116 /* 3-byte VEX prefix. */
3117 unsigned int m, w;
3118
f88c9eb0 3119 i.vex.length = 3;
f88c9eb0 3120
7f399153 3121 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3122 {
7f399153
L		 3123 case VEX0F:
3124 m = 0x1;
80de6e00 3125 i.vex.bytes[0] = 0xc4;
7f399153
L		 3126 break;
3127 case VEX0F38:
3128 m = 0x2;
80de6e00 3129 i.vex.bytes[0] = 0xc4;
7f399153
L		 3130 break;
3131 case VEX0F3A:
3132 m = 0x3;
80de6e00 3133 i.vex.bytes[0] = 0xc4;
7f399153
L		 3134 break;
3135 case XOP08:
5dd85c99
SP		 3136 m = 0x8;
3137 i.vex.bytes[0] = 0x8f;
7f399153
L		 3138 break;
3139 case XOP09:
f88c9eb0
SP		 3140 m = 0x9;
3141 i.vex.bytes[0] = 0x8f;
7f399153
L		 3142 break;
3143 case XOP0A:
f88c9eb0
SP		 3144 m = 0xa;
3145 i.vex.bytes[0] = 0x8f;
7f399153
L		 3146 break;
3147 default:
3148 abort ();
f88c9eb0 3149 }
c0f3af97 3150
c0f3af97
L		 3151 /* The high 3 bits of the second VEX byte are 1's compliment
3152 of RXB bits from REX. */
3153 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3154
3155 /* Check the REX.W bit. */
3156 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3157 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3158 {
3159 if (w)
3160 abort ();
3161
1ef99a7b 3162 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3163 w = 1;
3164 }
3165
3166 i.vex.bytes[2] = (w << 7
3167 | register_specifier << 3
3168 | vector_length << 2
3169 | implied_prefix);
3170 }
3171}
3172
43234a1e
L		 3173/* Build the EVEX prefix. */
3174
3175static void
3176build_evex_prefix (void)
3177{
3178 unsigned int register_specifier;
3179 unsigned int implied_prefix;
3180 unsigned int m, w;
3181 rex_byte vrex_used = 0;
3182
3183 /* Check register specifier. */
3184 if (i.vex.register_specifier)
3185 {
3186 gas_assert ((i.vrex & REX_X) == 0);
3187
3188 register_specifier = i.vex.register_specifier->reg_num;
3189 if ((i.vex.register_specifier->reg_flags & RegRex))
3190 register_specifier += 8;
3191 /* The upper 16 registers are encoded in the fourth byte of the
3192 EVEX prefix. */
3193 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3194 i.vex.bytes[3] = 0x8;
3195 register_specifier = ~register_specifier & 0xf;
3196 }
3197 else
3198 {
3199 register_specifier = 0xf;
3200
3201 /* Encode upper 16 vector index register in the fourth byte of
3202 the EVEX prefix. */
3203 if (!(i.vrex & REX_X))
3204 i.vex.bytes[3] = 0x8;
3205 else
3206 vrex_used |= REX_X;
3207 }
3208
3209 switch ((i.tm.base_opcode >> 8) & 0xff)
3210 {
3211 case 0:
3212 implied_prefix = 0;
3213 break;
3214 case DATA_PREFIX_OPCODE:
3215 implied_prefix = 1;
3216 break;
3217 case REPE_PREFIX_OPCODE:
3218 implied_prefix = 2;
3219 break;
3220 case REPNE_PREFIX_OPCODE:
3221 implied_prefix = 3;
3222 break;
3223 default:
3224 abort ();
3225 }
3226
3227 /* 4 byte EVEX prefix. */
3228 i.vex.length = 4;
3229 i.vex.bytes[0] = 0x62;
3230
3231 /* mmmm bits. */
3232 switch (i.tm.opcode_modifier.vexopcode)
3233 {
3234 case VEX0F:
3235 m = 1;
3236 break;
3237 case VEX0F38:
3238 m = 2;
3239 break;
3240 case VEX0F3A:
3241 m = 3;
3242 break;
3243 default:
3244 abort ();
3245 break;
3246 }
3247
3248 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3249 bits from REX. */
3250 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3251
3252 /* The fifth bit of the second EVEX byte is 1's compliment of the
3253 REX_R bit in VREX. */
3254 if (!(i.vrex & REX_R))
3255 i.vex.bytes[1] |= 0x10;
3256 else
3257 vrex_used |= REX_R;
3258
3259 if ((i.reg_operands + i.imm_operands) == i.operands)
3260 {
3261 /* When all operands are registers, the REX_X bit in REX is not
3262 used. We reuse it to encode the upper 16 registers, which is
3263 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3264 as 1's compliment. */
3265 if ((i.vrex & REX_B))
3266 {
3267 vrex_used |= REX_B;
3268 i.vex.bytes[1] &= ~0x40;
3269 }
3270 }
3271
3272 /* EVEX instructions shouldn't need the REX prefix. */
3273 i.vrex &= ~vrex_used;
3274 gas_assert (i.vrex == 0);
3275
3276 /* Check the REX.W bit. */
3277 w = (i.rex & REX_W) ? 1 : 0;
3278 if (i.tm.opcode_modifier.vexw)
3279 {
3280 if (i.tm.opcode_modifier.vexw == VEXW1)
3281 w = 1;
3282 }
3283 /* If w is not set it means we are dealing with WIG instruction. */
3284 else if (!w)
3285 {
3286 if (evexwig == evexw1)
3287 w = 1;
3288 }
3289
3290 /* Encode the U bit. */
3291 implied_prefix |= 0x4;
3292
3293 /* The third byte of the EVEX prefix. */
3294 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3295
3296 /* The fourth byte of the EVEX prefix. */
3297 /* The zeroing-masking bit. */
3298 if (i.mask && i.mask->zeroing)
3299 i.vex.bytes[3] |= 0x80;
3300
3301 /* Don't always set the broadcast bit if there is no RC. */
3302 if (!i.rounding)
3303 {
3304 /* Encode the vector length. */
3305 unsigned int vec_length;
3306
3307 switch (i.tm.opcode_modifier.evex)
3308 {
3309 case EVEXLIG: /* LL' is ignored */
3310 vec_length = evexlig << 5;
3311 break;
3312 case EVEX128:
3313 vec_length = 0 << 5;
3314 break;
3315 case EVEX256:
3316 vec_length = 1 << 5;
3317 break;
3318 case EVEX512:
3319 vec_length = 2 << 5;
3320 break;
3321 default:
3322 abort ();
3323 break;
3324 }
3325 i.vex.bytes[3] |= vec_length;
3326 /* Encode the broadcast bit. */
3327 if (i.broadcast)
3328 i.vex.bytes[3] |= 0x10;
3329 }
3330 else
3331 {
3332 if (i.rounding->type != saeonly)
3333 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3334 else
3335 i.vex.bytes[3] |= 0x10;
3336 }
3337
3338 if (i.mask && i.mask->mask)
3339 i.vex.bytes[3] |= i.mask->mask->reg_num;
3340}
3341
65da13b5
L		 3342static void
3343process_immext (void)
3344{
3345 expressionS *exp;
3346
4c692bc7
JB		 3347 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3348 && i.operands > 0)
65da13b5 3349 {
4c692bc7
JB		 3350 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3351 with an opcode suffix which is coded in the same place as an
3352 8-bit immediate field would be.
3353 Here we check those operands and remove them afterwards. */
65da13b5
L		 3354 unsigned int x;
3355
3356 for (x = 0; x < i.operands; x++)
4c692bc7 3357 if (register_number (i.op[x].regs) != x)
65da13b5 3358 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3359 register_prefix, i.op[x].regs->reg_name, x + 1,
3360 i.tm.name);
3361
3362 i.operands = 0;
65da13b5
L		 3363 }
3364
c0f3af97 3365 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3366 which is coded in the same place as an 8-bit immediate field
3367 would be. Here we fake an 8-bit immediate operand from the
3368 opcode suffix stored in tm.extension_opcode.
3369
c1e679ec 3370 AVX instructions also use this encoding, for some of
c0f3af97 3371 3 argument instructions. */
65da13b5 3372
43234a1e 3373 gas_assert (i.imm_operands <= 1
7ab9ffdd 3374 && (i.operands <= 2
43234a1e
L		 3375 || ((i.tm.opcode_modifier.vex
3376 || i.tm.opcode_modifier.evex)
7ab9ffdd 3377 && i.operands <= 4)));
65da13b5
L		 3378
3379 exp = &im_expressions[i.imm_operands++];
3380 i.op[i.operands].imms = exp;
3381 i.types[i.operands] = imm8;
3382 i.operands++;
3383 exp->X_op = O_constant;
3384 exp->X_add_number = i.tm.extension_opcode;
3385 i.tm.extension_opcode = None;
3386}
3387
42164a71
L		 3388
3389static int
3390check_hle (void)
3391{
3392 switch (i.tm.opcode_modifier.hleprefixok)
3393 {
3394 default:
3395 abort ();
82c2def5 3396 case HLEPrefixNone:
165de32a
L		 3397 as_bad (_("invalid instruction `%s' after `%s'"),
3398 i.tm.name, i.hle_prefix);
42164a71 3399 return 0;
82c2def5 3400 case HLEPrefixLock:
42164a71
L		 3401 if (i.prefix[LOCK_PREFIX])
3402 return 1;
165de32a 3403 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3404 return 0;
82c2def5 3405 case HLEPrefixAny:
42164a71 3406 return 1;
82c2def5 3407 case HLEPrefixRelease:
42164a71
L		 3408 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3409 {
3410 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3411 i.tm.name);
3412 return 0;
3413 }
3414 if (i.mem_operands == 0
3415 || !operand_type_check (i.types[i.operands - 1], anymem))
3416 {
3417 as_bad (_("memory destination needed for instruction `%s'"
3418 " after `xrelease'"), i.tm.name);
3419 return 0;
3420 }
3421 return 1;
3422 }
3423}
3424
252b5132
RH		 3425/* This is the guts of the machine-dependent assembler. LINE points to a
3426 machine dependent instruction. This function is supposed to emit
3427 the frags/bytes it assembles to. */
3428
3429void
65da13b5 3430md_assemble (char *line)
252b5132 3431{
40fb9820 3432 unsigned int j;
252b5132 3433 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3434 const insn_template *t;
252b5132 3435
47926f60 3436 /* Initialize globals. */
252b5132
RH		 3437 memset (&i, '\0', sizeof (i));
3438 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3439 i.reloc[j] = NO_RELOC;
252b5132
RH		 3440 memset (disp_expressions, '\0', sizeof (disp_expressions));
3441 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3442 save_stack_p = save_stack;
252b5132
RH		 3443
3444 /* First parse an instruction mnemonic & call i386_operand for the operands.
3445 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3446 start of a (possibly prefixed) mnemonic. */
252b5132 3447
29b0f896
AM		 3448 line = parse_insn (line, mnemonic);
3449 if (line == NULL)
3450 return;
252b5132 3451
29b0f896 3452 line = parse_operands (line, mnemonic);
ee86248c 3453 this_operand = -1;
29b0f896
AM		 3454 if (line == NULL)
3455 return;
252b5132 3456
29b0f896
AM		 3457 /* Now we've parsed the mnemonic into a set of templates, and have the
3458 operands at hand. */
3459
3460 /* All intel opcodes have reversed operands except for "bound" and
3461 "enter". We also don't reverse intersegment "jmp" and "call"
3462 instructions with 2 immediate operands so that the immediate segment
050dfa73 3463 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3464 if (intel_syntax
3465 && i.operands > 1
29b0f896 3466 && (strcmp (mnemonic, "bound") != 0)
30123838 3467 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3468 && !(operand_type_check (i.types[0], imm)
3469 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3470 swap_operands ();
3471
ec56d5c0
JB		 3472 /* The order of the immediates should be reversed
3473 for 2 immediates extrq and insertq instructions */
3474 if (i.imm_operands == 2
3475 && (strcmp (mnemonic, "extrq") == 0
3476 || strcmp (mnemonic, "insertq") == 0))
3477 swap_2_operands (0, 1);
3478
29b0f896
AM		 3479 if (i.imm_operands)
3480 optimize_imm ();
3481
b300c311
L		 3482 /* Don't optimize displacement for movabs since it only takes 64bit
3483 displacement. */
3484 if (i.disp_operands
a501d77e 3485 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3486 && (flag_code != CODE_64BIT
3487 || strcmp (mnemonic, "movabs") != 0))
3488 optimize_disp ();
29b0f896
AM		 3489
3490 /* Next, we find a template that matches the given insn,
3491 making sure the overlap of the given operands types is consistent
3492 with the template operand types. */
252b5132 3493
fa99fab2 3494 if (!(t = match_template ()))
29b0f896 3495 return;
252b5132 3496
7bab8ab5 3497 if (sse_check != check_none
81f8a913 3498 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3499 && (i.tm.cpu_flags.bitfield.cpusse
3500 || i.tm.cpu_flags.bitfield.cpusse2
3501 || i.tm.cpu_flags.bitfield.cpusse3
3502 || i.tm.cpu_flags.bitfield.cpussse3
3503 || i.tm.cpu_flags.bitfield.cpusse4_1
3504 || i.tm.cpu_flags.bitfield.cpusse4_2))
3505 {
7bab8ab5 3506 (sse_check == check_warning
daf50ae7
L		 3507 ? as_warn
3508 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3509 }
3510
321fd21e
L		 3511 /* Zap movzx and movsx suffix. The suffix has been set from
3512 "word ptr" or "byte ptr" on the source operand in Intel syntax
3513 or extracted from mnemonic in AT&T syntax. But we'll use
3514 the destination register to choose the suffix for encoding. */
3515 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3516 {
321fd21e
L		 3517 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3518 there is no suffix, the default will be byte extension. */
3519 if (i.reg_operands != 2
3520 && !i.suffix
7ab9ffdd 3521 && intel_syntax)
321fd21e
L		 3522 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3523
3524 i.suffix = 0;
cd61ebfe 3525 }
24eab124 3526
40fb9820 3527 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3528 if (!add_prefix (FWAIT_OPCODE))
3529 return;
252b5132 3530
d5de92cf
L		 3531 /* Check if REP prefix is OK. */
3532 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3533 {
3534 as_bad (_("invalid instruction `%s' after `%s'"),
3535 i.tm.name, i.rep_prefix);
3536 return;
3537 }
3538
c1ba0266
L		 3539 /* Check for lock without a lockable instruction. Destination operand
3540 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3541 if (i.prefix[LOCK_PREFIX]
3542 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3543 || i.mem_operands == 0
3544 || (i.tm.base_opcode != 0x86
3545 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3546 {
3547 as_bad (_("expecting lockable instruction after `lock'"));
3548 return;
3549 }
3550
42164a71 3551 /* Check if HLE prefix is OK. */
165de32a 3552 if (i.hle_prefix && !check_hle ())
42164a71
L		 3553 return;
3554
7e8b059b
L		 3555 /* Check BND prefix. */
3556 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3557 as_bad (_("expecting valid branch instruction after `bnd'"));
3558
3559 if (i.tm.cpu_flags.bitfield.cpumpx
3560 && flag_code == CODE_64BIT
3561 && i.prefix[ADDR_PREFIX])
3562 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3563
3564 /* Insert BND prefix. */
3565 if (add_bnd_prefix
3566 && i.tm.opcode_modifier.bndprefixok
3567 && !i.prefix[BND_PREFIX])
3568 add_prefix (BND_PREFIX_OPCODE);
3569
29b0f896 3570 /* Check string instruction segment overrides. */
40fb9820 3571 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3572 {
3573 if (!check_string ())
5dd0794d 3574 return;
fc0763e6 3575 i.disp_operands = 0;
29b0f896 3576 }
5dd0794d 3577
29b0f896
AM		 3578 if (!process_suffix ())
3579 return;
e413e4e9 3580
bc0844ae
L		 3581 /* Update operand types. */
3582 for (j = 0; j < i.operands; j++)
3583 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3584
29b0f896
AM		 3585 /* Make still unresolved immediate matches conform to size of immediate
3586 given in i.suffix. */
3587 if (!finalize_imm ())
3588 return;
252b5132 3589
40fb9820 3590 if (i.types[0].bitfield.imm1)
29b0f896 3591 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3592
9afe6eb8
L		 3593 /* We only need to check those implicit registers for instructions
3594 with 3 operands or less. */
3595 if (i.operands <= 3)
3596 for (j = 0; j < i.operands; j++)
3597 if (i.types[j].bitfield.inoutportreg
3598 || i.types[j].bitfield.shiftcount
3599 || i.types[j].bitfield.acc
3600 || i.types[j].bitfield.floatacc)
3601 i.reg_operands--;
40fb9820 3602
c0f3af97
L		 3603 /* ImmExt should be processed after SSE2AVX. */
3604 if (!i.tm.opcode_modifier.sse2avx
3605 && i.tm.opcode_modifier.immext)
65da13b5 3606 process_immext ();
252b5132 3607
29b0f896
AM		 3608 /* For insns with operands there are more diddles to do to the opcode. */
3609 if (i.operands)
3610 {
3611 if (!process_operands ())
3612 return;
3613 }
40fb9820 3614 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3615 {
3616 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3617 as_warn (_("translating to `%sp'"), i.tm.name);
3618 }
252b5132 3619
c0f3af97 3620 if (i.tm.opcode_modifier.vex)
fa99fab2 3621 build_vex_prefix (t);
c0f3af97 3622
43234a1e
L		 3623 if (i.tm.opcode_modifier.evex)
3624 build_evex_prefix ();
3625
5dd85c99
SP		 3626 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3627 instructions may define INT_OPCODE as well, so avoid this corner
3628 case for those instructions that use MODRM. */
3629 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3630 && !i.tm.opcode_modifier.modrm
3631 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3632 {
3633 i.tm.base_opcode = INT3_OPCODE;
3634 i.imm_operands = 0;
3635 }
252b5132 3636
40fb9820
L		 3637 if ((i.tm.opcode_modifier.jump
3638 || i.tm.opcode_modifier.jumpbyte
3639 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3640 && i.op[0].disps->X_op == O_constant)
3641 {
3642 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3643 the absolute address given by the constant. Since ix86 jumps and
3644 calls are pc relative, we need to generate a reloc. */
3645 i.op[0].disps->X_add_symbol = &abs_symbol;
3646 i.op[0].disps->X_op = O_symbol;
3647 }
252b5132 3648
40fb9820 3649 if (i.tm.opcode_modifier.rex64)
161a04f6 3650 i.rex |= REX_W;
252b5132 3651
29b0f896
AM		 3652 /* For 8 bit registers we need an empty rex prefix. Also if the
3653 instruction already has a prefix, we need to convert old
3654 registers to new ones. */
773f551c 3655
40fb9820 3656 if ((i.types[0].bitfield.reg8
29b0f896 3657 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3658 || (i.types[1].bitfield.reg8
29b0f896 3659 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3660 || ((i.types[0].bitfield.reg8
3661 || i.types[1].bitfield.reg8)
29b0f896
AM		 3662 && i.rex != 0))
3663 {
3664 int x;
726c5dcd 3665
29b0f896
AM		 3666 i.rex |= REX_OPCODE;
3667 for (x = 0; x < 2; x++)
3668 {
3669 /* Look for 8 bit operand that uses old registers. */
40fb9820 3670 if (i.types[x].bitfield.reg8
29b0f896 3671 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3672 {
29b0f896
AM		 3673 /* In case it is "hi" register, give up. */
3674 if (i.op[x].regs->reg_num > 3)
a540244d 3675 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3676 "instruction requiring REX prefix."),
a540244d 3677 register_prefix, i.op[x].regs->reg_name);
773f551c 3678
29b0f896
AM		 3679 /* Otherwise it is equivalent to the extended register.
3680 Since the encoding doesn't change this is merely
3681 cosmetic cleanup for debug output. */
3682
3683 i.op[x].regs = i.op[x].regs + 8;
773f551c 3684 }
29b0f896
AM		 3685 }
3686 }
773f551c 3687
7ab9ffdd 3688 if (i.rex != 0)
29b0f896
AM		 3689 add_prefix (REX_OPCODE | i.rex);
3690
3691 /* We are ready to output the insn. */
3692 output_insn ();
3693}
3694
3695static char *
e3bb37b5 3696parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3697{
3698 char *l = line;
3699 char *token_start = l;
3700 char *mnem_p;
5c6af06e 3701 int supported;
d3ce72d0 3702 const insn_template *t;
b6169b20 3703 char *dot_p = NULL;
29b0f896 3704
29b0f896
AM		 3705 while (1)
3706 {
3707 mnem_p = mnemonic;
3708 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3709 {
b6169b20
L		 3710 if (*mnem_p == '.')
3711 dot_p = mnem_p;
29b0f896
AM		 3712 mnem_p++;
3713 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3714 {
29b0f896
AM		 3715 as_bad (_("no such instruction: `%s'"), token_start);
3716 return NULL;
3717 }
3718 l++;
3719 }
3720 if (!is_space_char (*l)
3721 && *l != END_OF_INSN
e44823cf
JB		 3722 && (intel_syntax
3723 || (*l != PREFIX_SEPARATOR
3724 && *l != ',')))
29b0f896
AM		 3725 {
3726 as_bad (_("invalid character %s in mnemonic"),
3727 output_invalid (*l));
3728 return NULL;
3729 }
3730 if (token_start == l)
3731 {
e44823cf 3732 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3733 as_bad (_("expecting prefix; got nothing"));
3734 else
3735 as_bad (_("expecting mnemonic; got nothing"));
3736 return NULL;
3737 }
45288df1 3738
29b0f896 3739 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3740 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3741
29b0f896
AM		 3742 if (*l != END_OF_INSN
3743 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3744 && current_templates
40fb9820 3745 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3746 {
c6fb90c8 3747 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3748 {
3749 as_bad ((flag_code != CODE_64BIT
3750 ? _("`%s' is only supported in 64-bit mode")
3751 : _("`%s' is not supported in 64-bit mode")),
3752 current_templates->start->name);
3753 return NULL;
3754 }
29b0f896
AM		 3755 /* If we are in 16-bit mode, do not allow addr16 or data16.
3756 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3757 if ((current_templates->start->opcode_modifier.size16
3758 || current_templates->start->opcode_modifier.size32)
29b0f896 3759 && flag_code != CODE_64BIT
40fb9820 3760 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3761 ^ (flag_code == CODE_16BIT)))
3762 {
3763 as_bad (_("redundant %s prefix"),
3764 current_templates->start->name);
3765 return NULL;
45288df1 3766 }
29b0f896
AM		 3767 /* Add prefix, checking for repeated prefixes. */
3768 switch (add_prefix (current_templates->start->base_opcode))
3769 {
c32fa91d 3770 case PREFIX_EXIST:
29b0f896 3771 return NULL;
c32fa91d 3772 case PREFIX_REP:
42164a71 3773 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3774 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3775 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3776 i.bnd_prefix = current_templates->start->name;
42164a71 3777 else
d5de92cf 3778 i.rep_prefix = current_templates->start->name;
29b0f896 3779 break;
c32fa91d
L		 3780 default:
3781 break;
29b0f896
AM		 3782 }
3783 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3784 token_start = ++l;
3785 }
3786 else
3787 break;
3788 }
45288df1 3789
30a55f88 3790 if (!current_templates)
b6169b20 3791 {
f8a5c266
L		 3792 /* Check if we should swap operand or force 32bit displacement in
3793 encoding. */
30a55f88
L		 3794 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3795 i.swap_operand = 1;
8d63c93e 3796 else if (mnem_p - 3 == dot_p
a501d77e
L		 3797 && dot_p[1] == 'd'
3798 && dot_p[2] == '8')
3799 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3800 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3801 && dot_p[1] == 'd'
3802 && dot_p[2] == '3'
3803 && dot_p[3] == '2')
a501d77e 3804 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3805 else
3806 goto check_suffix;
3807 mnem_p = dot_p;
3808 *dot_p = '\0';
d3ce72d0 3809 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3810 }
3811
29b0f896
AM		 3812 if (!current_templates)
3813 {
b6169b20 3814check_suffix:
29b0f896
AM		 3815 /* See if we can get a match by trimming off a suffix. */
3816 switch (mnem_p[-1])
3817 {
3818 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3819 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3820 i.suffix = SHORT_MNEM_SUFFIX;
3821 else
29b0f896
AM		 3822 case BYTE_MNEM_SUFFIX:
3823 case QWORD_MNEM_SUFFIX:
3824 i.suffix = mnem_p[-1];
3825 mnem_p[-1] = '\0';
d3ce72d0
NC		 3826 current_templates = (const templates *) hash_find (op_hash,
3827 mnemonic);
29b0f896
AM		 3828 break;
3829 case SHORT_MNEM_SUFFIX:
3830 case LONG_MNEM_SUFFIX:
3831 if (!intel_syntax)
3832 {
3833 i.suffix = mnem_p[-1];
3834 mnem_p[-1] = '\0';
d3ce72d0
NC		 3835 current_templates = (const templates *) hash_find (op_hash,
3836 mnemonic);
29b0f896
AM		 3837 }
3838 break;
252b5132 3839
29b0f896
AM		 3840 /* Intel Syntax. */
3841 case 'd':
3842 if (intel_syntax)
3843 {
9306ca4a 3844 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3845 i.suffix = SHORT_MNEM_SUFFIX;
3846 else
3847 i.suffix = LONG_MNEM_SUFFIX;
3848 mnem_p[-1] = '\0';
d3ce72d0
NC		 3849 current_templates = (const templates *) hash_find (op_hash,
3850 mnemonic);
29b0f896
AM		 3851 }
3852 break;
3853 }
3854 if (!current_templates)
3855 {
3856 as_bad (_("no such instruction: `%s'"), token_start);
3857 return NULL;
3858 }
3859 }
252b5132 3860
40fb9820
L		 3861 if (current_templates->start->opcode_modifier.jump
3862 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3863 {
3864 /* Check for a branch hint. We allow ",pt" and ",pn" for
3865 predict taken and predict not taken respectively.
3866 I'm not sure that branch hints actually do anything on loop
3867 and jcxz insns (JumpByte) for current Pentium4 chips. They
3868 may work in the future and it doesn't hurt to accept them
3869 now. */
3870 if (l[0] == ',' && l[1] == 'p')
3871 {
3872 if (l[2] == 't')
3873 {
3874 if (!add_prefix (DS_PREFIX_OPCODE))
3875 return NULL;
3876 l += 3;
3877 }
3878 else if (l[2] == 'n')
3879 {
3880 if (!add_prefix (CS_PREFIX_OPCODE))
3881 return NULL;
3882 l += 3;
3883 }
3884 }
3885 }
3886 /* Any other comma loses. */
3887 if (*l == ',')
3888 {
3889 as_bad (_("invalid character %s in mnemonic"),
3890 output_invalid (*l));
3891 return NULL;
3892 }
252b5132 3893
29b0f896 3894 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3895 supported = 0;
3896 for (t = current_templates->start; t < current_templates->end; ++t)
3897 {
c0f3af97
L		 3898 supported |= cpu_flags_match (t);
3899 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3900 goto skip;
5c6af06e 3901 }
3629bb00 3902
c0f3af97 3903 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3904 {
3905 as_bad (flag_code == CODE_64BIT
3906 ? _("`%s' is not supported in 64-bit mode")
3907 : _("`%s' is only supported in 64-bit mode"),
3908 current_templates->start->name);
3909 return NULL;
3910 }
c0f3af97 3911 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3912 {
3629bb00 3913 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3914 current_templates->start->name,
41aacd83 3915 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3916 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3917 return NULL;
29b0f896 3918 }
3629bb00
L		 3919
3920skip:
3921 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3922 && (flag_code != CODE_16BIT))
29b0f896
AM		 3923 {
3924 as_warn (_("use .code16 to ensure correct addressing mode"));
3925 }
252b5132 3926
29b0f896
AM		 3927 return l;
3928}
252b5132 3929
29b0f896 3930static char *
e3bb37b5 3931parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3932{
3933 char *token_start;
3138f287 3934
29b0f896
AM		 3935 /* 1 if operand is pending after ','. */
3936 unsigned int expecting_operand = 0;
252b5132 3937
29b0f896
AM		 3938 /* Non-zero if operand parens not balanced. */
3939 unsigned int paren_not_balanced;
3940
3941 while (*l != END_OF_INSN)
3942 {
3943 /* Skip optional white space before operand. */
3944 if (is_space_char (*l))
3945 ++l;
3946 if (!is_operand_char (*l) && *l != END_OF_INSN)
3947 {
3948 as_bad (_("invalid character %s before operand %d"),
3949 output_invalid (*l),
3950 i.operands + 1);
3951 return NULL;
3952 }
3953 token_start = l; /* after white space */
3954 paren_not_balanced = 0;
3955 while (paren_not_balanced || *l != ',')
3956 {
3957 if (*l == END_OF_INSN)
3958 {
3959 if (paren_not_balanced)
3960 {
3961 if (!intel_syntax)
3962 as_bad (_("unbalanced parenthesis in operand %d."),
3963 i.operands + 1);
3964 else
3965 as_bad (_("unbalanced brackets in operand %d."),
3966 i.operands + 1);
3967 return NULL;
3968 }
3969 else
3970 break; /* we are done */
3971 }
3972 else if (!is_operand_char (*l) && !is_space_char (*l))
3973 {
3974 as_bad (_("invalid character %s in operand %d"),
3975 output_invalid (*l),
3976 i.operands + 1);
3977 return NULL;
3978 }
3979 if (!intel_syntax)
3980 {
3981 if (*l == '(')
3982 ++paren_not_balanced;
3983 if (*l == ')')
3984 --paren_not_balanced;
3985 }
3986 else
3987 {
3988 if (*l == '[')
3989 ++paren_not_balanced;
3990 if (*l == ']')
3991 --paren_not_balanced;
3992 }
3993 l++;
3994 }
3995 if (l != token_start)
3996 { /* Yes, we've read in another operand. */
3997 unsigned int operand_ok;
3998 this_operand = i.operands++;
7d5e4556 3999 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4000 if (i.operands > MAX_OPERANDS)
4001 {
4002 as_bad (_("spurious operands; (%d operands/instruction max)"),
4003 MAX_OPERANDS);
4004 return NULL;
4005 }
4006 /* Now parse operand adding info to 'i' as we go along. */
4007 END_STRING_AND_SAVE (l);
4008
4009 if (intel_syntax)
4010 operand_ok =
4011 i386_intel_operand (token_start,
4012 intel_float_operand (mnemonic));
4013 else
a7619375 4014 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4015
4016 RESTORE_END_STRING (l);
4017 if (!operand_ok)
4018 return NULL;
4019 }
4020 else
4021 {
4022 if (expecting_operand)
4023 {
4024 expecting_operand_after_comma:
4025 as_bad (_("expecting operand after ','; got nothing"));
4026 return NULL;
4027 }
4028 if (*l == ',')
4029 {
4030 as_bad (_("expecting operand before ','; got nothing"));
4031 return NULL;
4032 }
4033 }
7f3f1ea2 4034
29b0f896
AM		 4035 /* Now *l must be either ',' or END_OF_INSN. */
4036 if (*l == ',')
4037 {
4038 if (*++l == END_OF_INSN)
4039 {
4040 /* Just skip it, if it's \n complain. */
4041 goto expecting_operand_after_comma;
4042 }
4043 expecting_operand = 1;
4044 }
4045 }
4046 return l;
4047}
7f3f1ea2 4048
050dfa73 4049static void
4d456e3d 4050swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4051{
4052 union i386_op temp_op;
40fb9820 4053 i386_operand_type temp_type;
050dfa73 4054 enum bfd_reloc_code_real temp_reloc;
4eed87de 4055
050dfa73
MM		 4056 temp_type = i.types[xchg2];
4057 i.types[xchg2] = i.types[xchg1];
4058 i.types[xchg1] = temp_type;
4059 temp_op = i.op[xchg2];
4060 i.op[xchg2] = i.op[xchg1];
4061 i.op[xchg1] = temp_op;
4062 temp_reloc = i.reloc[xchg2];
4063 i.reloc[xchg2] = i.reloc[xchg1];
4064 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4065
4066 if (i.mask)
4067 {
4068 if (i.mask->operand == xchg1)
4069 i.mask->operand = xchg2;
4070 else if (i.mask->operand == xchg2)
4071 i.mask->operand = xchg1;
4072 }
4073 if (i.broadcast)
4074 {
4075 if (i.broadcast->operand == xchg1)
4076 i.broadcast->operand = xchg2;
4077 else if (i.broadcast->operand == xchg2)
4078 i.broadcast->operand = xchg1;
4079 }
4080 if (i.rounding)
4081 {
4082 if (i.rounding->operand == xchg1)
4083 i.rounding->operand = xchg2;
4084 else if (i.rounding->operand == xchg2)
4085 i.rounding->operand = xchg1;
4086 }
050dfa73
MM		 4087}
4088
29b0f896 4089static void
e3bb37b5 4090swap_operands (void)
29b0f896 4091{
b7c61d9a 4092 switch (i.operands)
050dfa73 4093 {
c0f3af97 4094 case 5:
b7c61d9a 4095 case 4:
4d456e3d 4096 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4097 case 3:
4098 case 2:
4d456e3d 4099 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4100 break;
4101 default:
4102 abort ();
29b0f896 4103 }
29b0f896
AM		 4104
4105 if (i.mem_operands == 2)
4106 {
4107 const seg_entry *temp_seg;
4108 temp_seg = i.seg[0];
4109 i.seg[0] = i.seg[1];
4110 i.seg[1] = temp_seg;
4111 }
4112}
252b5132 4113
29b0f896
AM		 4114/* Try to ensure constant immediates are represented in the smallest
4115 opcode possible. */
4116static void
e3bb37b5 4117optimize_imm (void)
29b0f896
AM		 4118{
4119 char guess_suffix = 0;
4120 int op;
252b5132 4121
29b0f896
AM		 4122 if (i.suffix)
4123 guess_suffix = i.suffix;
4124 else if (i.reg_operands)
4125 {
4126 /* Figure out a suffix from the last register operand specified.
4127 We can't do this properly yet, ie. excluding InOutPortReg,
4128 but the following works for instructions with immediates.
4129 In any case, we can't set i.suffix yet. */
4130 for (op = i.operands; --op >= 0;)
40fb9820 4131 if (i.types[op].bitfield.reg8)
7ab9ffdd 4132 {
40fb9820
L		 4133 guess_suffix = BYTE_MNEM_SUFFIX;
4134 break;
4135 }
4136 else if (i.types[op].bitfield.reg16)
252b5132 4137 {
40fb9820
L		 4138 guess_suffix = WORD_MNEM_SUFFIX;
4139 break;
4140 }
4141 else if (i.types[op].bitfield.reg32)
4142 {
4143 guess_suffix = LONG_MNEM_SUFFIX;
4144 break;
4145 }
4146 else if (i.types[op].bitfield.reg64)
4147 {
4148 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4149 break;
252b5132 4150 }
29b0f896
AM		 4151 }
4152 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4153 guess_suffix = WORD_MNEM_SUFFIX;
4154
4155 for (op = i.operands; --op >= 0;)
40fb9820 4156 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4157 {
4158 switch (i.op[op].imms->X_op)
252b5132 4159 {
29b0f896
AM		 4160 case O_constant:
4161 /* If a suffix is given, this operand may be shortened. */
4162 switch (guess_suffix)
252b5132 4163 {
29b0f896 4164 case LONG_MNEM_SUFFIX:
40fb9820
L		 4165 i.types[op].bitfield.imm32 = 1;
4166 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4167 break;
4168 case WORD_MNEM_SUFFIX:
40fb9820
L		 4169 i.types[op].bitfield.imm16 = 1;
4170 i.types[op].bitfield.imm32 = 1;
4171 i.types[op].bitfield.imm32s = 1;
4172 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4173 break;
4174 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4175 i.types[op].bitfield.imm8 = 1;
4176 i.types[op].bitfield.imm8s = 1;
4177 i.types[op].bitfield.imm16 = 1;
4178 i.types[op].bitfield.imm32 = 1;
4179 i.types[op].bitfield.imm32s = 1;
4180 i.types[op].bitfield.imm64 = 1;
29b0f896 4181 break;
252b5132 4182 }
252b5132 4183
29b0f896
AM		 4184 /* If this operand is at most 16 bits, convert it
4185 to a signed 16 bit number before trying to see
4186 whether it will fit in an even smaller size.
4187 This allows a 16-bit operand such as $0xffe0 to
4188 be recognised as within Imm8S range. */
40fb9820 4189 if ((i.types[op].bitfield.imm16)
29b0f896 4190 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4191 {
29b0f896
AM		 4192 i.op[op].imms->X_add_number =
4193 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4194 }
40fb9820 4195 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4196 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4197 == 0))
4198 {
4199 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4200 ^ ((offsetT) 1 << 31))
4201 - ((offsetT) 1 << 31));
4202 }
40fb9820 4203 i.types[op]
c6fb90c8
L		 4204 = operand_type_or (i.types[op],
4205 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4206
29b0f896
AM		 4207 /* We must avoid matching of Imm32 templates when 64bit
4208 only immediate is available. */
4209 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4210 i.types[op].bitfield.imm32 = 0;
29b0f896 4211 break;
252b5132 4212
29b0f896
AM		 4213 case O_absent:
4214 case O_register:
4215 abort ();
4216
4217 /* Symbols and expressions. */
4218 default:
9cd96992
JB		 4219 /* Convert symbolic operand to proper sizes for matching, but don't
4220 prevent matching a set of insns that only supports sizes other
4221 than those matching the insn suffix. */
4222 {
40fb9820 4223 i386_operand_type mask, allowed;
d3ce72d0 4224 const insn_template *t;
9cd96992 4225
0dfbf9d7
L		 4226 operand_type_set (&mask, 0);
4227 operand_type_set (&allowed, 0);
40fb9820 4228
4eed87de
AM		 4229 for (t = current_templates->start;
4230 t < current_templates->end;
4231 ++t)
c6fb90c8
L		 4232 allowed = operand_type_or (allowed,
4233 t->operand_types[op]);
9cd96992
JB		 4234 switch (guess_suffix)
4235 {
4236 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4237 mask.bitfield.imm64 = 1;
4238 mask.bitfield.imm32s = 1;
9cd96992
JB		 4239 break;
4240 case LONG_MNEM_SUFFIX:
40fb9820 4241 mask.bitfield.imm32 = 1;
9cd96992
JB		 4242 break;
4243 case WORD_MNEM_SUFFIX:
40fb9820 4244 mask.bitfield.imm16 = 1;
9cd96992
JB		 4245 break;
4246 case BYTE_MNEM_SUFFIX:
40fb9820 4247 mask.bitfield.imm8 = 1;
9cd96992
JB		 4248 break;
4249 default:
9cd96992
JB		 4250 break;
4251 }
c6fb90c8 4252 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4253 if (!operand_type_all_zero (&allowed))
c6fb90c8 4254 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4255 }
29b0f896 4256 break;
252b5132 4257 }
29b0f896
AM		 4258 }
4259}
47926f60 4260
29b0f896
AM		 4261/* Try to use the smallest displacement type too. */
4262static void
e3bb37b5 4263optimize_disp (void)
29b0f896
AM		 4264{
4265 int op;
3e73aa7c 4266
29b0f896 4267 for (op = i.operands; --op >= 0;)
40fb9820 4268 if (operand_type_check (i.types[op], disp))
252b5132 4269 {
b300c311 4270 if (i.op[op].disps->X_op == O_constant)
252b5132 4271 {
91d6fa6a 4272 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4273
40fb9820 4274 if (i.types[op].bitfield.disp16
91d6fa6a 4275 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4276 {
4277 /* If this operand is at most 16 bits, convert
4278 to a signed 16 bit number and don't use 64bit
4279 displacement. */
91d6fa6a 4280 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4281 i.types[op].bitfield.disp64 = 0;
b300c311 4282 }
40fb9820 4283 if (i.types[op].bitfield.disp32
91d6fa6a 4284 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4285 {
4286 /* If this operand is at most 32 bits, convert
4287 to a signed 32 bit number and don't use 64bit
4288 displacement. */
91d6fa6a
NC		 4289 op_disp &= (((offsetT) 2 << 31) - 1);
4290 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4291 i.types[op].bitfield.disp64 = 0;
b300c311 4292 }
91d6fa6a 4293 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4294 {
40fb9820
L		 4295 i.types[op].bitfield.disp8 = 0;
4296 i.types[op].bitfield.disp16 = 0;
4297 i.types[op].bitfield.disp32 = 0;
4298 i.types[op].bitfield.disp32s = 0;
4299 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4300 i.op[op].disps = 0;
4301 i.disp_operands--;
4302 }
4303 else if (flag_code == CODE_64BIT)
4304 {
91d6fa6a 4305 if (fits_in_signed_long (op_disp))
28a9d8f5 4306 {
40fb9820
L		 4307 i.types[op].bitfield.disp64 = 0;
4308 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4309 }
0e1147d9 4310 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4311 && fits_in_unsigned_long (op_disp))
40fb9820 4312 i.types[op].bitfield.disp32 = 1;
b300c311 4313 }
40fb9820
L		 4314 if ((i.types[op].bitfield.disp32
4315 || i.types[op].bitfield.disp32s
4316 || i.types[op].bitfield.disp16)
91d6fa6a 4317 && fits_in_signed_byte (op_disp))
40fb9820 4318 i.types[op].bitfield.disp8 = 1;
252b5132 4319 }
67a4f2b7
AO		 4320 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4321 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4322 {
4323 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4324 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4325 i.types[op].bitfield.disp8 = 0;
4326 i.types[op].bitfield.disp16 = 0;
4327 i.types[op].bitfield.disp32 = 0;
4328 i.types[op].bitfield.disp32s = 0;
4329 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4330 }
4331 else
b300c311 4332 /* We only support 64bit displacement on constants. */
40fb9820 4333 i.types[op].bitfield.disp64 = 0;
252b5132 4334 }
29b0f896
AM		 4335}
4336
6c30d220
L		 4337/* Check if operands are valid for the instruction. */
4338
4339static int
4340check_VecOperands (const insn_template *t)
4341{
43234a1e
L		 4342 unsigned int op;
4343
6c30d220
L		 4344 /* Without VSIB byte, we can't have a vector register for index. */
4345 if (!t->opcode_modifier.vecsib
4346 && i.index_reg
4347 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4348 || i.index_reg->reg_type.bitfield.regymm
4349 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4350 {
4351 i.error = unsupported_vector_index_register;
4352 return 1;
4353 }
4354
ad8ecc81
MZ		 4355 /* Check if default mask is allowed. */
4356 if (t->opcode_modifier.nodefmask
4357 && (!i.mask || i.mask->mask->reg_num == 0))
4358 {
4359 i.error = no_default_mask;
4360 return 1;
4361 }
4362
7bab8ab5
JB		 4363 /* For VSIB byte, we need a vector register for index, and all vector
4364 registers must be distinct. */
4365 if (t->opcode_modifier.vecsib)
4366 {
4367 if (!i.index_reg
6c30d220
L		 4368 || !((t->opcode_modifier.vecsib == VecSIB128
4369 && i.index_reg->reg_type.bitfield.regxmm)
4370 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4371 && i.index_reg->reg_type.bitfield.regymm)
4372 || (t->opcode_modifier.vecsib == VecSIB512
4373 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4374 {
4375 i.error = invalid_vsib_address;
4376 return 1;
4377 }
4378
43234a1e
L		 4379 gas_assert (i.reg_operands == 2 || i.mask);
4380 if (i.reg_operands == 2 && !i.mask)
4381 {
4382 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4383 || i.types[0].bitfield.regymm);
43234a1e 4384 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4385 || i.types[2].bitfield.regymm);
43234a1e
L		 4386 if (operand_check == check_none)
4387 return 0;
4388 if (register_number (i.op[0].regs)
4389 != register_number (i.index_reg)
4390 && register_number (i.op[2].regs)
4391 != register_number (i.index_reg)
4392 && register_number (i.op[0].regs)
4393 != register_number (i.op[2].regs))
4394 return 0;
4395 if (operand_check == check_error)
4396 {
4397 i.error = invalid_vector_register_set;
4398 return 1;
4399 }
4400 as_warn (_("mask, index, and destination registers should be distinct"));
4401 }
8444f82a
MZ		 4402 else if (i.reg_operands == 1 && i.mask)
4403 {
4404 if ((i.types[1].bitfield.regymm
4405 || i.types[1].bitfield.regzmm)
4406 && (register_number (i.op[1].regs)
4407 == register_number (i.index_reg)))
4408 {
4409 if (operand_check == check_error)
4410 {
4411 i.error = invalid_vector_register_set;
4412 return 1;
4413 }
4414 if (operand_check != check_none)
4415 as_warn (_("index and destination registers should be distinct"));
4416 }
4417 }
43234a1e 4418 }
7bab8ab5 4419
43234a1e
L		 4420 /* Check if broadcast is supported by the instruction and is applied
4421 to the memory operand. */
4422 if (i.broadcast)
4423 {
4424 int broadcasted_opnd_size;
4425
4426 /* Check if specified broadcast is supported in this instruction,
4427 and it's applied to memory operand of DWORD or QWORD type,
4428 depending on VecESize. */
4429 if (i.broadcast->type != t->opcode_modifier.broadcast
4430 || !i.types[i.broadcast->operand].bitfield.mem
4431 || (t->opcode_modifier.vecesize == 0
4432 && !i.types[i.broadcast->operand].bitfield.dword
4433 && !i.types[i.broadcast->operand].bitfield.unspecified)
4434 || (t->opcode_modifier.vecesize == 1
4435 && !i.types[i.broadcast->operand].bitfield.qword
4436 && !i.types[i.broadcast->operand].bitfield.unspecified))
4437 goto bad_broadcast;
4438
4439 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4440 if (i.broadcast->type == BROADCAST_1TO16)
4441 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4442 else if (i.broadcast->type == BROADCAST_1TO8)
4443 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4444 else
4445 goto bad_broadcast;
4446
4447 if ((broadcasted_opnd_size == 256
4448 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4449 || (broadcasted_opnd_size == 512
4450 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4451 {
4452 bad_broadcast:
4453 i.error = unsupported_broadcast;
4454 return 1;
4455 }
4456 }
4457 /* If broadcast is supported in this instruction, we need to check if
4458 operand of one-element size isn't specified without broadcast. */
4459 else if (t->opcode_modifier.broadcast && i.mem_operands)
4460 {
4461 /* Find memory operand. */
4462 for (op = 0; op < i.operands; op++)
4463 if (operand_type_check (i.types[op], anymem))
4464 break;
4465 gas_assert (op < i.operands);
4466 /* Check size of the memory operand. */
4467 if ((t->opcode_modifier.vecesize == 0
4468 && i.types[op].bitfield.dword)
4469 || (t->opcode_modifier.vecesize == 1
4470 && i.types[op].bitfield.qword))
4471 {
4472 i.error = broadcast_needed;
4473 return 1;
4474 }
4475 }
4476
4477 /* Check if requested masking is supported. */
4478 if (i.mask
4479 && (!t->opcode_modifier.masking
4480 || (i.mask->zeroing
4481 && t->opcode_modifier.masking == MERGING_MASKING)))
4482 {
4483 i.error = unsupported_masking;
4484 return 1;
4485 }
4486
4487 /* Check if masking is applied to dest operand. */
4488 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4489 {
4490 i.error = mask_not_on_destination;
4491 return 1;
4492 }
4493
43234a1e
L		 4494 /* Check RC/SAE. */
4495 if (i.rounding)
4496 {
4497 if ((i.rounding->type != saeonly
4498 && !t->opcode_modifier.staticrounding)
4499 || (i.rounding->type == saeonly
4500 && (t->opcode_modifier.staticrounding
4501 || !t->opcode_modifier.sae)))
4502 {
4503 i.error = unsupported_rc_sae;
4504 return 1;
4505 }
4506 /* If the instruction has several immediate operands and one of
4507 them is rounding, the rounding operand should be the last
4508 immediate operand. */
4509 if (i.imm_operands > 1
4510 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4511 {
43234a1e 4512 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4513 return 1;
4514 }
6c30d220
L		 4515 }
4516
43234a1e
L		 4517 /* Check vector Disp8 operand. */
4518 if (t->opcode_modifier.disp8memshift)
4519 {
4520 if (i.broadcast)
4521 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4522 else
4523 i.memshift = t->opcode_modifier.disp8memshift;
4524
4525 for (op = 0; op < i.operands; op++)
4526 if (operand_type_check (i.types[op], disp)
4527 && i.op[op].disps->X_op == O_constant)
4528 {
4529 offsetT value = i.op[op].disps->X_add_number;
4530 int vec_disp8_ok = fits_in_vec_disp8 (value);
4531 if (t->operand_types [op].bitfield.vec_disp8)
4532 {
4533 if (vec_disp8_ok)
4534 i.types[op].bitfield.vec_disp8 = 1;
4535 else
4536 {
4537 /* Vector insn can only have Vec_Disp8/Disp32 in
4538 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4539 mode. */
4540 i.types[op].bitfield.disp8 = 0;
4541 if (flag_code != CODE_16BIT)
4542 i.types[op].bitfield.disp16 = 0;
4543 }
4544 }
4545 else if (flag_code != CODE_16BIT)
4546 {
4547 /* One form of this instruction supports vector Disp8.
4548 Try vector Disp8 if we need to use Disp32. */
4549 if (vec_disp8_ok && !fits_in_signed_byte (value))
4550 {
4551 i.error = try_vector_disp8;
4552 return 1;
4553 }
4554 }
4555 }
4556 }
4557 else
4558 i.memshift = -1;
4559
6c30d220
L		 4560 return 0;
4561}
4562
43f3e2ee 4563/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4564 operand types. */
4565
4566static int
4567VEX_check_operands (const insn_template *t)
4568{
43234a1e
L		 4569 /* VREX is only valid with EVEX prefix. */
4570 if (i.need_vrex && !t->opcode_modifier.evex)
4571 {
4572 i.error = invalid_register_operand;
4573 return 1;
4574 }
4575
a683cc34
SP		 4576 if (!t->opcode_modifier.vex)
4577 return 0;
4578
4579 /* Only check VEX_Imm4, which must be the first operand. */
4580 if (t->operand_types[0].bitfield.vec_imm4)
4581 {
4582 if (i.op[0].imms->X_op != O_constant
4583 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4584 {
a65babc9 4585 i.error = bad_imm4;
891edac4
L		 4586 return 1;
4587 }
a683cc34
SP		 4588
4589 /* Turn off Imm8 so that update_imm won't complain. */
4590 i.types[0] = vec_imm4;
4591 }
4592
4593 return 0;
4594}
4595
d3ce72d0 4596static const insn_template *
e3bb37b5 4597match_template (void)
29b0f896
AM		 4598{
4599 /* Points to template once we've found it. */
d3ce72d0 4600 const insn_template *t;
40fb9820 4601 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4602 i386_operand_type overlap4;
29b0f896 4603 unsigned int found_reverse_match;
40fb9820
L		 4604 i386_opcode_modifier suffix_check;
4605 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4606 int addr_prefix_disp;
a5c311ca 4607 unsigned int j;
3629bb00 4608 unsigned int found_cpu_match;
45664ddb 4609 unsigned int check_register;
5614d22c 4610 enum i386_error specific_error = 0;
29b0f896 4611
c0f3af97
L		 4612#if MAX_OPERANDS != 5
4613# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4614#endif
4615
29b0f896 4616 found_reverse_match = 0;
539e75ad 4617 addr_prefix_disp = -1;
40fb9820
L		 4618
4619 memset (&suffix_check, 0, sizeof (suffix_check));
4620 if (i.suffix == BYTE_MNEM_SUFFIX)
4621 suffix_check.no_bsuf = 1;
4622 else if (i.suffix == WORD_MNEM_SUFFIX)
4623 suffix_check.no_wsuf = 1;
4624 else if (i.suffix == SHORT_MNEM_SUFFIX)
4625 suffix_check.no_ssuf = 1;
4626 else if (i.suffix == LONG_MNEM_SUFFIX)
4627 suffix_check.no_lsuf = 1;
4628 else if (i.suffix == QWORD_MNEM_SUFFIX)
4629 suffix_check.no_qsuf = 1;
4630 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4631 suffix_check.no_ldsuf = 1;
29b0f896 4632
01559ecc
L		 4633 /* Must have right number of operands. */
4634 i.error = number_of_operands_mismatch;
4635
45aa61fe 4636 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4637 {
539e75ad
L		 4638 addr_prefix_disp = -1;
4639
29b0f896
AM		 4640 if (i.operands != t->operands)
4641 continue;
4642
50aecf8c 4643 /* Check processor support. */
a65babc9 4644 i.error = unsupported;
c0f3af97
L		 4645 found_cpu_match = (cpu_flags_match (t)
4646 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4647 if (!found_cpu_match)
4648 continue;
4649
e1d4d893 4650 /* Check old gcc support. */
a65babc9 4651 i.error = old_gcc_only;
e1d4d893
L		 4652 if (!old_gcc && t->opcode_modifier.oldgcc)
4653 continue;
4654
4655 /* Check AT&T mnemonic. */
a65babc9 4656 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4657 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4658 continue;
4659
891edac4 4660 /* Check AT&T/Intel syntax. */
a65babc9 4661 i.error = unsupported_syntax;
5c07affc
L		 4662 if ((intel_syntax && t->opcode_modifier.attsyntax)
4663 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4664 continue;
4665
20592a94 4666 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4667 i.error = invalid_instruction_suffix;
567e4e96
L		 4668 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4669 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4670 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4671 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4672 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4673 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4674 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4675 continue;
4676
5c07affc 4677 if (!operand_size_match (t))
7d5e4556 4678 continue;
539e75ad 4679
5c07affc
L		 4680 for (j = 0; j < MAX_OPERANDS; j++)
4681 operand_types[j] = t->operand_types[j];
4682
45aa61fe
AM		 4683 /* In general, don't allow 64-bit operands in 32-bit mode. */
4684 if (i.suffix == QWORD_MNEM_SUFFIX
4685 && flag_code != CODE_64BIT
4686 && (intel_syntax
40fb9820 4687 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4688 && !intel_float_operand (t->name))
4689 : intel_float_operand (t->name) != 2)
40fb9820 4690 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4691 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4692 && !operand_types[0].bitfield.regymm
4693 && !operand_types[0].bitfield.regzmm)
40fb9820 4694 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97 4695 && !!operand_types[t->operands > 1].bitfield.regxmm
43234a1e
L		 4696 && !!operand_types[t->operands > 1].bitfield.regymm
4697 && !!operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4698 && (t->base_opcode != 0x0fc7
4699 || t->extension_opcode != 1 /* cmpxchg8b */))
4700 continue;
4701
192dc9c6
JB		 4702 /* In general, don't allow 32-bit operands on pre-386. */
4703 else if (i.suffix == LONG_MNEM_SUFFIX
4704 && !cpu_arch_flags.bitfield.cpui386
4705 && (intel_syntax
4706 ? (!t->opcode_modifier.ignoresize
4707 && !intel_float_operand (t->name))
4708 : intel_float_operand (t->name) != 2)
4709 && ((!operand_types[0].bitfield.regmmx
4710 && !operand_types[0].bitfield.regxmm)
4711 || (!operand_types[t->operands > 1].bitfield.regmmx
4712 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4713 continue;
4714
29b0f896 4715 /* Do not verify operands when there are none. */
50aecf8c 4716 else
29b0f896 4717 {
c6fb90c8 4718 if (!t->operands)
2dbab7d5
L		 4719 /* We've found a match; break out of loop. */
4720 break;
29b0f896 4721 }
252b5132 4722
539e75ad
L		 4723 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4724 into Disp32/Disp16/Disp32 operand. */
4725 if (i.prefix[ADDR_PREFIX] != 0)
4726 {
40fb9820 4727 /* There should be only one Disp operand. */
539e75ad
L		 4728 switch (flag_code)
4729 {
4730 case CODE_16BIT:
40fb9820
L		 4731 for (j = 0; j < MAX_OPERANDS; j++)
4732 {
4733 if (operand_types[j].bitfield.disp16)
4734 {
4735 addr_prefix_disp = j;
4736 operand_types[j].bitfield.disp32 = 1;
4737 operand_types[j].bitfield.disp16 = 0;
4738 break;
4739 }
4740 }
539e75ad
L		 4741 break;
4742 case CODE_32BIT:
40fb9820
L		 4743 for (j = 0; j < MAX_OPERANDS; j++)
4744 {
4745 if (operand_types[j].bitfield.disp32)
4746 {
4747 addr_prefix_disp = j;
4748 operand_types[j].bitfield.disp32 = 0;
4749 operand_types[j].bitfield.disp16 = 1;
4750 break;
4751 }
4752 }
539e75ad
L		 4753 break;
4754 case CODE_64BIT:
40fb9820
L		 4755 for (j = 0; j < MAX_OPERANDS; j++)
4756 {
4757 if (operand_types[j].bitfield.disp64)
4758 {
4759 addr_prefix_disp = j;
4760 operand_types[j].bitfield.disp64 = 0;
4761 operand_types[j].bitfield.disp32 = 1;
4762 break;
4763 }
4764 }
539e75ad
L		 4765 break;
4766 }
539e75ad
L		 4767 }
4768
56ffb741
L		 4769 /* We check register size if needed. */
4770 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4771 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4772 switch (t->operands)
4773 {
4774 case 1:
40fb9820 4775 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4776 continue;
4777 break;
4778 case 2:
8b38ad71
L		 4779 /* xchg %eax, %eax is a special case. It is an aliase for nop
4780 only in 32bit mode and we can use opcode 0x90. In 64bit
4781 mode, we can't use 0x90 for xchg %eax, %eax since it should
4782 zero-extend %eax to %rax. */
4783 if (flag_code == CODE_64BIT
4784 && t->base_opcode == 0x90
0dfbf9d7
L		 4785 && operand_type_equal (&i.types [0], &acc32)
4786 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4787 continue;
b6169b20
L		 4788 if (i.swap_operand)
4789 {
4790 /* If we swap operand in encoding, we either match
4791 the next one or reverse direction of operands. */
4792 if (t->opcode_modifier.s)
4793 continue;
4794 else if (t->opcode_modifier.d)
4795 goto check_reverse;
4796 }
4797
29b0f896 4798 case 3:
fa99fab2
L		 4799 /* If we swap operand in encoding, we match the next one. */
4800 if (i.swap_operand && t->opcode_modifier.s)
4801 continue;
f48ff2ae 4802 case 4:
c0f3af97 4803 case 5:
c6fb90c8 4804 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4805 if (!operand_type_match (overlap0, i.types[0])
4806 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4807 || (check_register
4808 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4809 operand_types[0],
4810 overlap1, i.types[1],
4811 operand_types[1])))
29b0f896
AM		 4812 {
4813 /* Check if other direction is valid ... */
40fb9820 4814 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4815 continue;
4816
b6169b20 4817check_reverse:
29b0f896 4818 /* Try reversing direction of operands. */
c6fb90c8
L		 4819 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4820 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4821 if (!operand_type_match (overlap0, i.types[0])
4822 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4823 || (check_register
4824 && !operand_type_register_match (overlap0,
4825 i.types[0],
4826 operand_types[1],
4827 overlap1,
4828 i.types[1],
4829 operand_types[0])))
29b0f896
AM		 4830 {
4831 /* Does not match either direction. */
4832 continue;
4833 }
4834 /* found_reverse_match holds which of D or FloatDR
4835 we've found. */
40fb9820 4836 if (t->opcode_modifier.d)
8a2ed489 4837 found_reverse_match = Opcode_D;
40fb9820 4838 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4839 found_reverse_match = Opcode_FloatD;
4840 else
4841 found_reverse_match = 0;
40fb9820 4842 if (t->opcode_modifier.floatr)
8a2ed489 4843 found_reverse_match |= Opcode_FloatR;
29b0f896 4844 }
f48ff2ae 4845 else
29b0f896 4846 {
f48ff2ae 4847 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4848 switch (t->operands)
4849 {
c0f3af97
L		 4850 case 5:
4851 overlap4 = operand_type_and (i.types[4],
4852 operand_types[4]);
d1cbb4db 4853 case 4:
c6fb90c8
L		 4854 overlap3 = operand_type_and (i.types[3],
4855 operand_types[3]);
d1cbb4db 4856 case 3:
c6fb90c8
L		 4857 overlap2 = operand_type_and (i.types[2],
4858 operand_types[2]);
d1cbb4db
L		 4859 break;
4860 }
29b0f896 4861
f48ff2ae
L		 4862 switch (t->operands)
4863 {
c0f3af97
L		 4864 case 5:
4865 if (!operand_type_match (overlap4, i.types[4])
4866 || !operand_type_register_match (overlap3,
4867 i.types[3],
4868 operand_types[3],
4869 overlap4,
4870 i.types[4],
4871 operand_types[4]))
4872 continue;
f48ff2ae 4873 case 4:
40fb9820 4874 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4875 || (check_register
4876 && !operand_type_register_match (overlap2,
4877 i.types[2],
4878 operand_types[2],
4879 overlap3,
4880 i.types[3],
4881 operand_types[3])))
f48ff2ae
L		 4882 continue;
4883 case 3:
4884 /* Here we make use of the fact that there are no
4885 reverse match 3 operand instructions, and all 3
4886 operand instructions only need to be checked for
4887 register consistency between operands 2 and 3. */
40fb9820 4888 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4889 || (check_register
4890 && !operand_type_register_match (overlap1,
4891 i.types[1],
4892 operand_types[1],
4893 overlap2,
4894 i.types[2],
4895 operand_types[2])))
f48ff2ae
L		 4896 continue;
4897 break;
4898 }
29b0f896 4899 }
f48ff2ae 4900 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4901 slip through to break. */
4902 }
3629bb00 4903 if (!found_cpu_match)
29b0f896
AM		 4904 {
4905 found_reverse_match = 0;
4906 continue;
4907 }
c0f3af97 4908
5614d22c
JB		 4909 /* Check if vector and VEX operands are valid. */
4910 if (check_VecOperands (t) || VEX_check_operands (t))
4911 {
4912 specific_error = i.error;
4913 continue;
4914 }
a683cc34 4915
29b0f896
AM		 4916 /* We've found a match; break out of loop. */
4917 break;
4918 }
4919
4920 if (t == current_templates->end)
4921 {
4922 /* We found no match. */
a65babc9 4923 const char *err_msg;
5614d22c 4924 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4925 {
4926 default:
4927 abort ();
86e026a4 4928 case operand_size_mismatch:
a65babc9
L		 4929 err_msg = _("operand size mismatch");
4930 break;
4931 case operand_type_mismatch:
4932 err_msg = _("operand type mismatch");
4933 break;
4934 case register_type_mismatch:
4935 err_msg = _("register type mismatch");
4936 break;
4937 case number_of_operands_mismatch:
4938 err_msg = _("number of operands mismatch");
4939 break;
4940 case invalid_instruction_suffix:
4941 err_msg = _("invalid instruction suffix");
4942 break;
4943 case bad_imm4:
4a2608e3 4944 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4945 break;
4946 case old_gcc_only:
4947 err_msg = _("only supported with old gcc");
4948 break;
4949 case unsupported_with_intel_mnemonic:
4950 err_msg = _("unsupported with Intel mnemonic");
4951 break;
4952 case unsupported_syntax:
4953 err_msg = _("unsupported syntax");
4954 break;
4955 case unsupported:
35262a23 4956 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4957 current_templates->start->name);
4958 return NULL;
6c30d220
L		 4959 case invalid_vsib_address:
4960 err_msg = _("invalid VSIB address");
4961 break;
7bab8ab5
JB		 4962 case invalid_vector_register_set:
4963 err_msg = _("mask, index, and destination registers must be distinct");
4964 break;
6c30d220
L		 4965 case unsupported_vector_index_register:
4966 err_msg = _("unsupported vector index register");
4967 break;
43234a1e
L		 4968 case unsupported_broadcast:
4969 err_msg = _("unsupported broadcast");
4970 break;
4971 case broadcast_not_on_src_operand:
4972 err_msg = _("broadcast not on source memory operand");
4973 break;
4974 case broadcast_needed:
4975 err_msg = _("broadcast is needed for operand of such type");
4976 break;
4977 case unsupported_masking:
4978 err_msg = _("unsupported masking");
4979 break;
4980 case mask_not_on_destination:
4981 err_msg = _("mask not on destination operand");
4982 break;
4983 case no_default_mask:
4984 err_msg = _("default mask isn't allowed");
4985 break;
4986 case unsupported_rc_sae:
4987 err_msg = _("unsupported static rounding/sae");
4988 break;
4989 case rc_sae_operand_not_last_imm:
4990 if (intel_syntax)
4991 err_msg = _("RC/SAE operand must precede immediate operands");
4992 else
4993 err_msg = _("RC/SAE operand must follow immediate operands");
4994 break;
4995 case invalid_register_operand:
4996 err_msg = _("invalid register operand");
4997 break;
a65babc9
L		 4998 }
4999 as_bad (_("%s for `%s'"), err_msg,
891edac4 5000 current_templates->start->name);
fa99fab2 5001 return NULL;
29b0f896 5002 }
252b5132 5003
29b0f896
AM		 5004 if (!quiet_warnings)
5005 {
5006 if (!intel_syntax
40fb9820
L		 5007 && (i.types[0].bitfield.jumpabsolute
5008 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5009 {
5010 as_warn (_("indirect %s without `*'"), t->name);
5011 }
5012
40fb9820
L		 5013 if (t->opcode_modifier.isprefix
5014 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5015 {
5016 /* Warn them that a data or address size prefix doesn't
5017 affect assembly of the next line of code. */
5018 as_warn (_("stand-alone `%s' prefix"), t->name);
5019 }
5020 }
5021
5022 /* Copy the template we found. */
5023 i.tm = *t;
539e75ad
L		 5024
5025 if (addr_prefix_disp != -1)
5026 i.tm.operand_types[addr_prefix_disp]
5027 = operand_types[addr_prefix_disp];
5028
29b0f896
AM		 5029 if (found_reverse_match)
5030 {
5031 /* If we found a reverse match we must alter the opcode
5032 direction bit. found_reverse_match holds bits to change
5033 (different for int & float insns). */
5034
5035 i.tm.base_opcode ^= found_reverse_match;
5036
539e75ad
L		 5037 i.tm.operand_types[0] = operand_types[1];
5038 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5039 }
5040
fa99fab2 5041 return t;
29b0f896
AM		 5042}
5043
5044static int
e3bb37b5 5045check_string (void)
29b0f896 5046{
40fb9820
L		 5047 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5048 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5049 {
5050 if (i.seg[0] != NULL && i.seg[0] != &es)
5051 {
a87af027 5052 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5053 i.tm.name,
a87af027
JB		 5054 mem_op + 1,
5055 register_prefix);
29b0f896
AM		 5056 return 0;
5057 }
5058 /* There's only ever one segment override allowed per instruction.
5059 This instruction possibly has a legal segment override on the
5060 second operand, so copy the segment to where non-string
5061 instructions store it, allowing common code. */
5062 i.seg[0] = i.seg[1];
5063 }
40fb9820 5064 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5065 {
5066 if (i.seg[1] != NULL && i.seg[1] != &es)
5067 {
a87af027 5068 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5069 i.tm.name,
a87af027
JB		 5070 mem_op + 2,
5071 register_prefix);
29b0f896
AM		 5072 return 0;
5073 }
5074 }
5075 return 1;
5076}
5077
5078static int
543613e9 5079process_suffix (void)
29b0f896
AM		 5080{
5081 /* If matched instruction specifies an explicit instruction mnemonic
5082 suffix, use it. */
40fb9820
L		 5083 if (i.tm.opcode_modifier.size16)
5084 i.suffix = WORD_MNEM_SUFFIX;
5085 else if (i.tm.opcode_modifier.size32)
5086 i.suffix = LONG_MNEM_SUFFIX;
5087 else if (i.tm.opcode_modifier.size64)
5088 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5089 else if (i.reg_operands)
5090 {
5091 /* If there's no instruction mnemonic suffix we try to invent one
5092 based on register operands. */
5093 if (!i.suffix)
5094 {
5095 /* We take i.suffix from the last register operand specified,
5096 Destination register type is more significant than source
381d071f
L		 5097 register type. crc32 in SSE4.2 prefers source register
5098 type. */
5099 if (i.tm.base_opcode == 0xf20f38f1)
5100 {
40fb9820
L		 5101 if (i.types[0].bitfield.reg16)
5102 i.suffix = WORD_MNEM_SUFFIX;
5103 else if (i.types[0].bitfield.reg32)
5104 i.suffix = LONG_MNEM_SUFFIX;
5105 else if (i.types[0].bitfield.reg64)
5106 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5107 }
9344ff29 5108 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5109 {
40fb9820 5110 if (i.types[0].bitfield.reg8)
20592a94
L		 5111 i.suffix = BYTE_MNEM_SUFFIX;
5112 }
381d071f
L		 5113
5114 if (!i.suffix)
5115 {
5116 int op;
5117
20592a94
L		 5118 if (i.tm.base_opcode == 0xf20f38f1
5119 || i.tm.base_opcode == 0xf20f38f0)
5120 {
5121 /* We have to know the operand size for crc32. */
5122 as_bad (_("ambiguous memory operand size for `%s`"),
5123 i.tm.name);
5124 return 0;
5125 }
5126
381d071f 5127 for (op = i.operands; --op >= 0;)
40fb9820 5128 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5129 {
40fb9820
L		 5130 if (i.types[op].bitfield.reg8)
5131 {
5132 i.suffix = BYTE_MNEM_SUFFIX;
5133 break;
5134 }
5135 else if (i.types[op].bitfield.reg16)
5136 {
5137 i.suffix = WORD_MNEM_SUFFIX;
5138 break;
5139 }
5140 else if (i.types[op].bitfield.reg32)
5141 {
5142 i.suffix = LONG_MNEM_SUFFIX;
5143 break;
5144 }
5145 else if (i.types[op].bitfield.reg64)
5146 {
5147 i.suffix = QWORD_MNEM_SUFFIX;
5148 break;
5149 }
381d071f
L		 5150 }
5151 }
29b0f896
AM		 5152 }
5153 else if (i.suffix == BYTE_MNEM_SUFFIX)
5154 {
2eb952a4
L		 5155 if (intel_syntax
5156 && i.tm.opcode_modifier.ignoresize
5157 && i.tm.opcode_modifier.no_bsuf)
5158 i.suffix = 0;
5159 else if (!check_byte_reg ())
29b0f896
AM		 5160 return 0;
5161 }
5162 else if (i.suffix == LONG_MNEM_SUFFIX)
5163 {
2eb952a4
L		 5164 if (intel_syntax
5165 && i.tm.opcode_modifier.ignoresize
5166 && i.tm.opcode_modifier.no_lsuf)
5167 i.suffix = 0;
5168 else if (!check_long_reg ())
29b0f896
AM		 5169 return 0;
5170 }
5171 else if (i.suffix == QWORD_MNEM_SUFFIX)
5172 {
955e1e6a
L		 5173 if (intel_syntax
5174 && i.tm.opcode_modifier.ignoresize
5175 && i.tm.opcode_modifier.no_qsuf)
5176 i.suffix = 0;
5177 else if (!check_qword_reg ())
29b0f896
AM		 5178 return 0;
5179 }
5180 else if (i.suffix == WORD_MNEM_SUFFIX)
5181 {
2eb952a4
L		 5182 if (intel_syntax
5183 && i.tm.opcode_modifier.ignoresize
5184 && i.tm.opcode_modifier.no_wsuf)
5185 i.suffix = 0;
5186 else if (!check_word_reg ())
29b0f896
AM		 5187 return 0;
5188 }
c0f3af97 5189 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5190 || i.suffix == YMMWORD_MNEM_SUFFIX
5191 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5192 {
43234a1e 5193 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5194 should check if it is a valid suffix. */
5195 }
40fb9820 5196 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5197 /* Do nothing if the instruction is going to ignore the prefix. */
5198 ;
5199 else
5200 abort ();
5201 }
40fb9820 5202 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5203 && !i.suffix
5204 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5205 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5206 {
5207 i.suffix = stackop_size;
5208 }
9306ca4a
JB		 5209 else if (intel_syntax
5210 && !i.suffix
40fb9820
L		 5211 && (i.tm.operand_types[0].bitfield.jumpabsolute
5212 || i.tm.opcode_modifier.jumpbyte
5213 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5214 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5215 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5216 {
5217 switch (flag_code)
5218 {
5219 case CODE_64BIT:
40fb9820 5220 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5221 {
5222 i.suffix = QWORD_MNEM_SUFFIX;
5223 break;
5224 }
5225 case CODE_32BIT:
40fb9820 5226 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5227 i.suffix = LONG_MNEM_SUFFIX;
5228 break;
5229 case CODE_16BIT:
40fb9820 5230 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5231 i.suffix = WORD_MNEM_SUFFIX;
5232 break;
5233 }
5234 }
252b5132 5235
9306ca4a 5236 if (!i.suffix)
29b0f896 5237 {
9306ca4a
JB		 5238 if (!intel_syntax)
5239 {
40fb9820 5240 if (i.tm.opcode_modifier.w)
9306ca4a 5241 {
4eed87de
AM		 5242 as_bad (_("no instruction mnemonic suffix given and "
5243 "no register operands; can't size instruction"));
9306ca4a
JB		 5244 return 0;
5245 }
5246 }
5247 else
5248 {
40fb9820 5249 unsigned int suffixes;
7ab9ffdd 5250
40fb9820
L		 5251 suffixes = !i.tm.opcode_modifier.no_bsuf;
5252 if (!i.tm.opcode_modifier.no_wsuf)
5253 suffixes |= 1 << 1;
5254 if (!i.tm.opcode_modifier.no_lsuf)
5255 suffixes |= 1 << 2;
fc4adea1 5256 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5257 suffixes |= 1 << 3;
5258 if (!i.tm.opcode_modifier.no_ssuf)
5259 suffixes |= 1 << 4;
5260 if (!i.tm.opcode_modifier.no_qsuf)
5261 suffixes |= 1 << 5;
5262
5263 /* There are more than suffix matches. */
5264 if (i.tm.opcode_modifier.w
9306ca4a 5265 || ((suffixes & (suffixes - 1))
40fb9820
L		 5266 && !i.tm.opcode_modifier.defaultsize
5267 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5268 {
5269 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5270 return 0;
5271 }
5272 }
29b0f896 5273 }
252b5132 5274
9306ca4a
JB		 5275 /* Change the opcode based on the operand size given by i.suffix;
5276 We don't need to change things for byte insns. */
5277
582d5edd
L		 5278 if (i.suffix
5279 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5280 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5281 && i.suffix != YMMWORD_MNEM_SUFFIX
5282 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5283 {
5284 /* It's not a byte, select word/dword operation. */
40fb9820 5285 if (i.tm.opcode_modifier.w)
29b0f896 5286 {
40fb9820 5287 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5288 i.tm.base_opcode |= 8;
5289 else
5290 i.tm.base_opcode |= 1;
5291 }
0f3f3d8b 5292
29b0f896
AM		 5293 /* Now select between word & dword operations via the operand
5294 size prefix, except for instructions that will ignore this
5295 prefix anyway. */
ca61edf2 5296 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5297 {
ca61edf2
L		 5298 /* The address size override prefix changes the size of the
5299 first operand. */
40fb9820
L		 5300 if ((flag_code == CODE_32BIT
5301 && i.op->regs[0].reg_type.bitfield.reg16)
5302 || (flag_code != CODE_32BIT
5303 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5304 if (!add_prefix (ADDR_PREFIX_OPCODE))
5305 return 0;
5306 }
5307 else if (i.suffix != QWORD_MNEM_SUFFIX
5308 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5309 && !i.tm.opcode_modifier.ignoresize
5310 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5311 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5312 || (flag_code == CODE_64BIT
40fb9820 5313 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5314 {
5315 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5316
40fb9820 5317 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5318 prefix = ADDR_PREFIX_OPCODE;
252b5132 5319
29b0f896
AM		 5320 if (!add_prefix (prefix))
5321 return 0;
24eab124 5322 }
252b5132 5323
29b0f896
AM		 5324 /* Set mode64 for an operand. */
5325 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5326 && flag_code == CODE_64BIT
40fb9820 5327 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5328 {
5329 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5330 need rex64. cmpxchg8b is also a special case. */
5331 if (! (i.operands == 2
5332 && i.tm.base_opcode == 0x90
5333 && i.tm.extension_opcode == None
0dfbf9d7
L		 5334 && operand_type_equal (&i.types [0], &acc64)
5335 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5336 && ! (i.operands == 1
5337 && i.tm.base_opcode == 0xfc7
5338 && i.tm.extension_opcode == 1
40fb9820
L		 5339 && !operand_type_check (i.types [0], reg)
5340 && operand_type_check (i.types [0], anymem)))
f6bee062 5341 i.rex |= REX_W;
46e883c5 5342 }
3e73aa7c 5343
29b0f896
AM		 5344 /* Size floating point instruction. */
5345 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5346 if (i.tm.opcode_modifier.floatmf)
543613e9 5347 i.tm.base_opcode ^= 4;
29b0f896 5348 }
7ecd2f8b 5349
29b0f896
AM		 5350 return 1;
5351}
3e73aa7c 5352
29b0f896 5353static int
543613e9 5354check_byte_reg (void)
29b0f896
AM		 5355{
5356 int op;
543613e9 5357
29b0f896
AM		 5358 for (op = i.operands; --op >= 0;)
5359 {
5360 /* If this is an eight bit register, it's OK. If it's the 16 or
5361 32 bit version of an eight bit register, we will just use the
5362 low portion, and that's OK too. */
40fb9820 5363 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5364 continue;
5365
5a819eb9
JB		 5366 /* I/O port address operands are OK too. */
5367 if (i.tm.operand_types[op].bitfield.inoutportreg)
5368 continue;
5369
9344ff29
L		 5370 /* crc32 doesn't generate this warning. */
5371 if (i.tm.base_opcode == 0xf20f38f0)
5372 continue;
5373
40fb9820
L		 5374 if ((i.types[op].bitfield.reg16
5375 || i.types[op].bitfield.reg32
5376 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5377 && i.op[op].regs->reg_num < 4
5378 /* Prohibit these changes in 64bit mode, since the lowering
5379 would be more complicated. */
5380 && flag_code != CODE_64BIT)
29b0f896 5381 {
29b0f896 5382#if REGISTER_WARNINGS
5a819eb9 5383 if (!quiet_warnings)
a540244d
L		 5384 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5385 register_prefix,
40fb9820 5386 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5387 ? REGNAM_AL - REGNAM_AX
5388 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5389 register_prefix,
29b0f896
AM		 5390 i.op[op].regs->reg_name,
5391 i.suffix);
5392#endif
5393 continue;
5394 }
5395 /* Any other register is bad. */
40fb9820
L		 5396 if (i.types[op].bitfield.reg16
5397 || i.types[op].bitfield.reg32
5398 || i.types[op].bitfield.reg64
5399 || i.types[op].bitfield.regmmx
5400 || i.types[op].bitfield.regxmm
c0f3af97 5401 || i.types[op].bitfield.regymm
43234a1e 5402 || i.types[op].bitfield.regzmm
40fb9820
L		 5403 || i.types[op].bitfield.sreg2
5404 || i.types[op].bitfield.sreg3
5405 || i.types[op].bitfield.control
5406 || i.types[op].bitfield.debug
5407 || i.types[op].bitfield.test
5408 || i.types[op].bitfield.floatreg
5409 || i.types[op].bitfield.floatacc)
29b0f896 5410 {
a540244d
L		 5411 as_bad (_("`%s%s' not allowed with `%s%c'"),
5412 register_prefix,
29b0f896
AM		 5413 i.op[op].regs->reg_name,
5414 i.tm.name,
5415 i.suffix);
5416 return 0;
5417 }
5418 }
5419 return 1;
5420}
5421
5422static int
e3bb37b5 5423check_long_reg (void)
29b0f896
AM		 5424{
5425 int op;
5426
5427 for (op = i.operands; --op >= 0;)
5428 /* Reject eight bit registers, except where the template requires
5429 them. (eg. movzb) */
40fb9820
L		 5430 if (i.types[op].bitfield.reg8
5431 && (i.tm.operand_types[op].bitfield.reg16
5432 || i.tm.operand_types[op].bitfield.reg32
5433 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5434 {
a540244d
L		 5435 as_bad (_("`%s%s' not allowed with `%s%c'"),
5436 register_prefix,
29b0f896
AM		 5437 i.op[op].regs->reg_name,
5438 i.tm.name,
5439 i.suffix);
5440 return 0;
5441 }
e4630f71 5442 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5443 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5444 && i.types[op].bitfield.reg16
5445 && (i.tm.operand_types[op].bitfield.reg32
5446 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5447 {
5448 /* Prohibit these changes in the 64bit mode, since the
5449 lowering is more complicated. */
5450 if (flag_code == CODE_64BIT)
252b5132 5451 {
2b5d6a91 5452 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5453 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5454 i.suffix);
5455 return 0;
252b5132 5456 }
29b0f896 5457#if REGISTER_WARNINGS
cecf1424
JB		 5458 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5459 register_prefix,
5460 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5461 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5462#endif
252b5132 5463 }
e4630f71 5464 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5465 else if (i.types[op].bitfield.reg64
5466 && (i.tm.operand_types[op].bitfield.reg32
5467 || i.tm.operand_types[op].bitfield.acc))
252b5132 5468 {
34828aad 5469 if (intel_syntax
ca61edf2 5470 && i.tm.opcode_modifier.toqword
40fb9820 5471 && !i.types[0].bitfield.regxmm)
34828aad 5472 {
ca61edf2 5473 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5474 i.suffix = QWORD_MNEM_SUFFIX;
5475 }
5476 else
5477 {
2b5d6a91 5478 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5479 register_prefix, i.op[op].regs->reg_name,
5480 i.suffix);
5481 return 0;
5482 }
29b0f896
AM		 5483 }
5484 return 1;
5485}
252b5132 5486
29b0f896 5487static int
e3bb37b5 5488check_qword_reg (void)
29b0f896
AM		 5489{
5490 int op;
252b5132 5491
29b0f896
AM		 5492 for (op = i.operands; --op >= 0; )
5493 /* Reject eight bit registers, except where the template requires
5494 them. (eg. movzb) */
40fb9820
L		 5495 if (i.types[op].bitfield.reg8
5496 && (i.tm.operand_types[op].bitfield.reg16
5497 || i.tm.operand_types[op].bitfield.reg32
5498 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5499 {
a540244d
L		 5500 as_bad (_("`%s%s' not allowed with `%s%c'"),
5501 register_prefix,
29b0f896
AM		 5502 i.op[op].regs->reg_name,
5503 i.tm.name,
5504 i.suffix);
5505 return 0;
5506 }
e4630f71 5507 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5508 else if ((i.types[op].bitfield.reg16
5509 || i.types[op].bitfield.reg32)
5510 && (i.tm.operand_types[op].bitfield.reg32
5511 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5512 {
5513 /* Prohibit these changes in the 64bit mode, since the
5514 lowering is more complicated. */
34828aad 5515 if (intel_syntax
ca61edf2 5516 && i.tm.opcode_modifier.todword
40fb9820 5517 && !i.types[0].bitfield.regxmm)
34828aad 5518 {
ca61edf2 5519 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5520 i.suffix = LONG_MNEM_SUFFIX;
5521 }
5522 else
5523 {
2b5d6a91 5524 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5525 register_prefix, i.op[op].regs->reg_name,
5526 i.suffix);
5527 return 0;
5528 }
252b5132 5529 }
29b0f896
AM		 5530 return 1;
5531}
252b5132 5532
29b0f896 5533static int
e3bb37b5 5534check_word_reg (void)
29b0f896
AM		 5535{
5536 int op;
5537 for (op = i.operands; --op >= 0;)
5538 /* Reject eight bit registers, except where the template requires
5539 them. (eg. movzb) */
40fb9820
L		 5540 if (i.types[op].bitfield.reg8
5541 && (i.tm.operand_types[op].bitfield.reg16
5542 || i.tm.operand_types[op].bitfield.reg32
5543 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5544 {
a540244d
L		 5545 as_bad (_("`%s%s' not allowed with `%s%c'"),
5546 register_prefix,
29b0f896
AM		 5547 i.op[op].regs->reg_name,
5548 i.tm.name,
5549 i.suffix);
5550 return 0;
5551 }
e4630f71 5552 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5553 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5554 && (i.types[op].bitfield.reg32
5555 || i.types[op].bitfield.reg64)
40fb9820
L		 5556 && (i.tm.operand_types[op].bitfield.reg16
5557 || i.tm.operand_types[op].bitfield.acc))
252b5132 5558 {
29b0f896
AM		 5559 /* Prohibit these changes in the 64bit mode, since the
5560 lowering is more complicated. */
5561 if (flag_code == CODE_64BIT)
252b5132 5562 {
2b5d6a91 5563 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5564 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5565 i.suffix);
5566 return 0;
252b5132 5567 }
29b0f896 5568#if REGISTER_WARNINGS
cecf1424
JB		 5569 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5570 register_prefix,
5571 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5572 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5573#endif
5574 }
5575 return 1;
5576}
252b5132 5577
29b0f896 5578static int
40fb9820 5579update_imm (unsigned int j)
29b0f896 5580{
bc0844ae 5581 i386_operand_type overlap = i.types[j];
40fb9820
L		 5582 if ((overlap.bitfield.imm8
5583 || overlap.bitfield.imm8s
5584 || overlap.bitfield.imm16
5585 || overlap.bitfield.imm32
5586 || overlap.bitfield.imm32s
5587 || overlap.bitfield.imm64)
0dfbf9d7
L		 5588 && !operand_type_equal (&overlap, &imm8)
5589 && !operand_type_equal (&overlap, &imm8s)
5590 && !operand_type_equal (&overlap, &imm16)
5591 && !operand_type_equal (&overlap, &imm32)
5592 && !operand_type_equal (&overlap, &imm32s)
5593 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5594 {
5595 if (i.suffix)
5596 {
40fb9820
L		 5597 i386_operand_type temp;
5598
0dfbf9d7 5599 operand_type_set (&temp, 0);
7ab9ffdd 5600 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5601 {
5602 temp.bitfield.imm8 = overlap.bitfield.imm8;
5603 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5604 }
5605 else if (i.suffix == WORD_MNEM_SUFFIX)
5606 temp.bitfield.imm16 = overlap.bitfield.imm16;
5607 else if (i.suffix == QWORD_MNEM_SUFFIX)
5608 {
5609 temp.bitfield.imm64 = overlap.bitfield.imm64;
5610 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5611 }
5612 else
5613 temp.bitfield.imm32 = overlap.bitfield.imm32;
5614 overlap = temp;
29b0f896 5615 }
0dfbf9d7
L		 5616 else if (operand_type_equal (&overlap, &imm16_32_32s)
5617 || operand_type_equal (&overlap, &imm16_32)
5618 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5619 {
40fb9820 5620 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5621 overlap = imm16;
40fb9820 5622 else
65da13b5 5623 overlap = imm32s;
29b0f896 5624 }
0dfbf9d7
L		 5625 if (!operand_type_equal (&overlap, &imm8)
5626 && !operand_type_equal (&overlap, &imm8s)
5627 && !operand_type_equal (&overlap, &imm16)
5628 && !operand_type_equal (&overlap, &imm32)
5629 && !operand_type_equal (&overlap, &imm32s)
5630 && !operand_type_equal (&overlap, &imm64))
29b0f896 5631 {
4eed87de
AM		 5632 as_bad (_("no instruction mnemonic suffix given; "
5633 "can't determine immediate size"));
29b0f896
AM		 5634 return 0;
5635 }
5636 }
40fb9820 5637 i.types[j] = overlap;
29b0f896 5638
40fb9820
L		 5639 return 1;
5640}
5641
5642static int
5643finalize_imm (void)
5644{
bc0844ae 5645 unsigned int j, n;
29b0f896 5646
bc0844ae
L		 5647 /* Update the first 2 immediate operands. */
5648 n = i.operands > 2 ? 2 : i.operands;
5649 if (n)
5650 {
5651 for (j = 0; j < n; j++)
5652 if (update_imm (j) == 0)
5653 return 0;
40fb9820 5654
bc0844ae
L		 5655 /* The 3rd operand can't be immediate operand. */
5656 gas_assert (operand_type_check (i.types[2], imm) == 0);
5657 }
29b0f896
AM		 5658
5659 return 1;
5660}
5661
c0f3af97
L		 5662static int
5663bad_implicit_operand (int xmm)
5664{
91d6fa6a
NC		 5665 const char *ireg = xmm ? "xmm0" : "ymm0";
5666
c0f3af97
L		 5667 if (intel_syntax)
5668 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5669 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5670 else
5671 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5672 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5673 return 0;
5674}
5675
29b0f896 5676static int
e3bb37b5 5677process_operands (void)
29b0f896
AM		 5678{
5679 /* Default segment register this instruction will use for memory
5680 accesses. 0 means unknown. This is only for optimizing out
5681 unnecessary segment overrides. */
5682 const seg_entry *default_seg = 0;
5683
2426c15f 5684 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5685 {
91d6fa6a
NC		 5686 unsigned int dupl = i.operands;
5687 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5688 unsigned int j;
5689
c0f3af97 5690 /* The destination must be an xmm register. */
9c2799c2 5691 gas_assert (i.reg_operands
91d6fa6a 5692 && MAX_OPERANDS > dupl
7ab9ffdd 5693 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5694
5695 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5696 {
c0f3af97 5697 /* The first operand is implicit and must be xmm0. */
9c2799c2 5698 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5699 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5700 return bad_implicit_operand (1);
5701
8cd7925b 5702 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5703 {
5704 /* Keep xmm0 for instructions with VEX prefix and 3
5705 sources. */
5706 goto duplicate;
5707 }
e2ec9d29 5708 else
c0f3af97
L		 5709 {
5710 /* We remove the first xmm0 and keep the number of
5711 operands unchanged, which in fact duplicates the
5712 destination. */
5713 for (j = 1; j < i.operands; j++)
5714 {
5715 i.op[j - 1] = i.op[j];
5716 i.types[j - 1] = i.types[j];
5717 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5718 }
5719 }
5720 }
5721 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5722 {
91d6fa6a 5723 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5724 && (i.tm.opcode_modifier.vexsources
5725 == VEX3SOURCES));
c0f3af97
L		 5726
5727 /* Add the implicit xmm0 for instructions with VEX prefix
5728 and 3 sources. */
5729 for (j = i.operands; j > 0; j--)
5730 {
5731 i.op[j] = i.op[j - 1];
5732 i.types[j] = i.types[j - 1];
5733 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5734 }
5735 i.op[0].regs
5736 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5737 i.types[0] = regxmm;
c0f3af97
L		 5738 i.tm.operand_types[0] = regxmm;
5739
5740 i.operands += 2;
5741 i.reg_operands += 2;
5742 i.tm.operands += 2;
5743
91d6fa6a 5744 dupl++;
c0f3af97 5745 dest++;
91d6fa6a
NC		 5746 i.op[dupl] = i.op[dest];
5747 i.types[dupl] = i.types[dest];
5748 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5749 }
c0f3af97
L		 5750 else
5751 {
5752duplicate:
5753 i.operands++;
5754 i.reg_operands++;
5755 i.tm.operands++;
5756
91d6fa6a
NC		 5757 i.op[dupl] = i.op[dest];
5758 i.types[dupl] = i.types[dest];
5759 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5760 }
5761
5762 if (i.tm.opcode_modifier.immext)
5763 process_immext ();
5764 }
5765 else if (i.tm.opcode_modifier.firstxmm0)
5766 {
5767 unsigned int j;
5768
43234a1e 5769 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5770 gas_assert (i.reg_operands
7ab9ffdd 5771 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5772 || operand_type_equal (&i.types[0], &regymm)
5773 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5774 if (register_number (i.op[0].regs) != 0)
c0f3af97 5775 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5776
5777 for (j = 1; j < i.operands; j++)
5778 {
5779 i.op[j - 1] = i.op[j];
5780 i.types[j - 1] = i.types[j];
5781
5782 /* We need to adjust fields in i.tm since they are used by
5783 build_modrm_byte. */
5784 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5785 }
5786
e2ec9d29
L		 5787 i.operands--;
5788 i.reg_operands--;
e2ec9d29
L		 5789 i.tm.operands--;
5790 }
5791 else if (i.tm.opcode_modifier.regkludge)
5792 {
5793 /* The imul $imm, %reg instruction is converted into
5794 imul $imm, %reg, %reg, and the clr %reg instruction
5795 is converted into xor %reg, %reg. */
5796
5797 unsigned int first_reg_op;
5798
5799 if (operand_type_check (i.types[0], reg))
5800 first_reg_op = 0;
5801 else
5802 first_reg_op = 1;
5803 /* Pretend we saw the extra register operand. */
9c2799c2 5804 gas_assert (i.reg_operands == 1
7ab9ffdd 5805 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5806 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5807 i.types[first_reg_op + 1] = i.types[first_reg_op];
5808 i.operands++;
5809 i.reg_operands++;
29b0f896
AM		 5810 }
5811
40fb9820 5812 if (i.tm.opcode_modifier.shortform)
29b0f896 5813 {
40fb9820
L		 5814 if (i.types[0].bitfield.sreg2
5815 || i.types[0].bitfield.sreg3)
29b0f896 5816 {
4eed87de
AM		 5817 if (i.tm.base_opcode == POP_SEG_SHORT
5818 && i.op[0].regs->reg_num == 1)
29b0f896 5819 {
a87af027 5820 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5821 return 0;
29b0f896 5822 }
4eed87de
AM		 5823 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5824 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5825 i.rex |= REX_B;
4eed87de
AM		 5826 }
5827 else
5828 {
7ab9ffdd 5829 /* The register or float register operand is in operand
85f10a01 5830 0 or 1. */
40fb9820 5831 unsigned int op;
7ab9ffdd
L		 5832
5833 if (i.types[0].bitfield.floatreg
5834 || operand_type_check (i.types[0], reg))
5835 op = 0;
5836 else
5837 op = 1;
4eed87de
AM		 5838 /* Register goes in low 3 bits of opcode. */
5839 i.tm.base_opcode |= i.op[op].regs->reg_num;
5840 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5841 i.rex |= REX_B;
40fb9820 5842 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5843 {
4eed87de
AM		 5844 /* Warn about some common errors, but press on regardless.
5845 The first case can be generated by gcc (<= 2.8.1). */
5846 if (i.operands == 2)
5847 {
5848 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5849 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5850 register_prefix, i.op[!intel_syntax].regs->reg_name,
5851 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5852 }
5853 else
5854 {
5855 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5856 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5857 register_prefix, i.op[0].regs->reg_name);
4eed87de 5858 }
29b0f896
AM		 5859 }
5860 }
5861 }
40fb9820 5862 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5863 {
5864 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5865 must be put into the modrm byte). Now, we make the modrm and
5866 index base bytes based on all the info we've collected. */
29b0f896
AM		 5867
5868 default_seg = build_modrm_byte ();
5869 }
8a2ed489 5870 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5871 {
5872 default_seg = &ds;
5873 }
40fb9820 5874 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5875 {
5876 /* For the string instructions that allow a segment override
5877 on one of their operands, the default segment is ds. */
5878 default_seg = &ds;
5879 }
5880
75178d9d
L		 5881 if (i.tm.base_opcode == 0x8d /* lea */
5882 && i.seg[0]
5883 && !quiet_warnings)
30123838 5884 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5885
5886 /* If a segment was explicitly specified, and the specified segment
5887 is not the default, use an opcode prefix to select it. If we
5888 never figured out what the default segment is, then default_seg
5889 will be zero at this point, and the specified segment prefix will
5890 always be used. */
29b0f896
AM		 5891 if ((i.seg[0]) && (i.seg[0] != default_seg))
5892 {
5893 if (!add_prefix (i.seg[0]->seg_prefix))
5894 return 0;
5895 }
5896 return 1;
5897}
5898
5899static const seg_entry *
e3bb37b5 5900build_modrm_byte (void)
29b0f896
AM		 5901{
5902 const seg_entry *default_seg = 0;
c0f3af97 5903 unsigned int source, dest;
8cd7925b 5904 int vex_3_sources;
c0f3af97
L		 5905
5906 /* The first operand of instructions with VEX prefix and 3 sources
5907 must be VEX_Imm4. */
8cd7925b 5908 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5909 if (vex_3_sources)
5910 {
91d6fa6a 5911 unsigned int nds, reg_slot;
4c2c6516 5912 expressionS *exp;
c0f3af97 5913
922d8de8 5914 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5915 && i.tm.opcode_modifier.immext)
5916 {
5917 dest = i.operands - 2;
5918 gas_assert (dest == 3);
5919 }
922d8de8 5920 else
a683cc34 5921 dest = i.operands - 1;
c0f3af97 5922 nds = dest - 1;
922d8de8 5923
a683cc34
SP		 5924 /* There are 2 kinds of instructions:
5925 1. 5 operands: 4 register operands or 3 register operands
5926 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5927 VexW0 or VexW1. The destination must be either XMM, YMM or
5928 ZMM register.
a683cc34
SP		 5929 2. 4 operands: 4 register operands or 3 register operands
5930 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5931 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5932 || (i.reg_operands == 3 && i.mem_operands == 1))
5933 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5934 && (i.tm.opcode_modifier.veximmext
5935 || (i.imm_operands == 1
5936 && i.types[0].bitfield.vec_imm4
5937 && (i.tm.opcode_modifier.vexw == VEXW0
5938 || i.tm.opcode_modifier.vexw == VEXW1)
5939 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5940 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5941 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5942
5943 if (i.imm_operands == 0)
5944 {
5945 /* When there is no immediate operand, generate an 8bit
5946 immediate operand to encode the first operand. */
5947 exp = &im_expressions[i.imm_operands++];
5948 i.op[i.operands].imms = exp;
5949 i.types[i.operands] = imm8;
5950 i.operands++;
5951 /* If VexW1 is set, the first operand is the source and
5952 the second operand is encoded in the immediate operand. */
5953 if (i.tm.opcode_modifier.vexw == VEXW1)
5954 {
5955 source = 0;
5956 reg_slot = 1;
5957 }
5958 else
5959 {
5960 source = 1;
5961 reg_slot = 0;
5962 }
5963
5964 /* FMA swaps REG and NDS. */
5965 if (i.tm.cpu_flags.bitfield.cpufma)
5966 {
5967 unsigned int tmp;
5968 tmp = reg_slot;
5969 reg_slot = nds;
5970 nds = tmp;
5971 }
5972
24981e7b
L		 5973 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5974 &regxmm)
a683cc34 5975 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5976 &regymm)
5977 || operand_type_equal (&i.tm.operand_types[reg_slot],
5978 &regzmm));
a683cc34 5979 exp->X_op = O_constant;
4c692bc7 5980 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5981 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5982 }
922d8de8 5983 else
a683cc34
SP		 5984 {
5985 unsigned int imm_slot;
5986
5987 if (i.tm.opcode_modifier.vexw == VEXW0)
5988 {
5989 /* If VexW0 is set, the third operand is the source and
5990 the second operand is encoded in the immediate
5991 operand. */
5992 source = 2;
5993 reg_slot = 1;
5994 }
5995 else
5996 {
5997 /* VexW1 is set, the second operand is the source and
5998 the third operand is encoded in the immediate
5999 operand. */
6000 source = 1;
6001 reg_slot = 2;
6002 }
6003
6004 if (i.tm.opcode_modifier.immext)
6005 {
6006 /* When ImmExt is set, the immdiate byte is the last
6007 operand. */
6008 imm_slot = i.operands - 1;
6009 source--;
6010 reg_slot--;
6011 }
6012 else
6013 {
6014 imm_slot = 0;
6015
6016 /* Turn on Imm8 so that output_imm will generate it. */
6017 i.types[imm_slot].bitfield.imm8 = 1;
6018 }
6019
24981e7b
L		 6020 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6021 &regxmm)
6022 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6023 &regymm)
6024 || operand_type_equal (&i.tm.operand_types[reg_slot],
6025 &regzmm));
a683cc34 6026 i.op[imm_slot].imms->X_add_number
4c692bc7 6027 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6028 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6029 }
6030
6031 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6032 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6033 &regymm)
6034 || operand_type_equal (&i.tm.operand_types[nds],
6035 &regzmm));
dae39acc 6036 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6037 }
6038 else
6039 source = dest = 0;
29b0f896
AM		 6040
6041 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6042 implicit registers do not count. If there are 3 register
6043 operands, it must be a instruction with VexNDS. For a
6044 instruction with VexNDD, the destination register is encoded
6045 in VEX prefix. If there are 4 register operands, it must be
6046 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6047 if (i.mem_operands == 0
6048 && ((i.reg_operands == 2
2426c15f 6049 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6050 || (i.reg_operands == 3
2426c15f 6051 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6052 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6053 {
cab737b9
L		 6054 switch (i.operands)
6055 {
6056 case 2:
6057 source = 0;
6058 break;
6059 case 3:
c81128dc
L		 6060 /* When there are 3 operands, one of them may be immediate,
6061 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6062 the first operand must be shift count register (cl) or it
6063 is an instruction with VexNDS. */
9c2799c2 6064 gas_assert (i.imm_operands == 1
7ab9ffdd 6065 || (i.imm_operands == 0
2426c15f 6066 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6067 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6068 if (operand_type_check (i.types[0], imm)
6069 || i.types[0].bitfield.shiftcount)
6070 source = 1;
6071 else
6072 source = 0;
cab737b9
L		 6073 break;
6074 case 4:
368d64cc
L		 6075 /* When there are 4 operands, the first two must be 8bit
6076 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6077 one.
6078
6079 For instructions with VexNDS, if the first operand
6080 an imm8, the source operand is the 2nd one. If the last
6081 operand is imm8, the source operand is the first one. */
9c2799c2 6082 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6083 && i.types[0].bitfield.imm8
6084 && i.types[1].bitfield.imm8)
2426c15f 6085 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6086 && i.imm_operands == 1
6087 && (i.types[0].bitfield.imm8
43234a1e
L		 6088 || i.types[i.operands - 1].bitfield.imm8
6089 || i.rounding)));
9f2670f2
L		 6090 if (i.imm_operands == 2)
6091 source = 2;
6092 else
c0f3af97
L		 6093 {
6094 if (i.types[0].bitfield.imm8)
6095 source = 1;
6096 else
6097 source = 0;
6098 }
c0f3af97
L		 6099 break;
6100 case 5:
43234a1e
L		 6101 if (i.tm.opcode_modifier.evex)
6102 {
6103 /* For EVEX instructions, when there are 5 operands, the
6104 first one must be immediate operand. If the second one
6105 is immediate operand, the source operand is the 3th
6106 one. If the last one is immediate operand, the source
6107 operand is the 2nd one. */
6108 gas_assert (i.imm_operands == 2
6109 && i.tm.opcode_modifier.sae
6110 && operand_type_check (i.types[0], imm));
6111 if (operand_type_check (i.types[1], imm))
6112 source = 2;
6113 else if (operand_type_check (i.types[4], imm))
6114 source = 1;
6115 else
6116 abort ();
6117 }
cab737b9
L		 6118 break;
6119 default:
6120 abort ();
6121 }
6122
c0f3af97
L		 6123 if (!vex_3_sources)
6124 {
6125 dest = source + 1;
6126
43234a1e
L		 6127 /* RC/SAE operand could be between DEST and SRC. That happens
6128 when one operand is GPR and the other one is XMM/YMM/ZMM
6129 register. */
6130 if (i.rounding && i.rounding->operand == (int) dest)
6131 dest++;
6132
2426c15f 6133 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6134 {
43234a1e
L		 6135 /* For instructions with VexNDS, the register-only source
6136 operand must be 32/64bit integer, XMM, YMM or ZMM
6137 register. It is encoded in VEX prefix. We need to
6138 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6139
6140 i386_operand_type op;
6141 unsigned int vvvv;
6142
6143 /* Check register-only source operand when two source
6144 operands are swapped. */
6145 if (!i.tm.operand_types[source].bitfield.baseindex
6146 && i.tm.operand_types[dest].bitfield.baseindex)
6147 {
6148 vvvv = source;
6149 source = dest;
6150 }
6151 else
6152 vvvv = dest;
6153
6154 op = i.tm.operand_types[vvvv];
fa99fab2 6155 op.bitfield.regmem = 0;
c0f3af97 6156 if ((dest + 1) >= i.operands
f12dc422
L		 6157 || (op.bitfield.reg32 != 1
6158 && !op.bitfield.reg64 != 1
6159 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6160 && !operand_type_equal (&op, &regymm)
6161 && !operand_type_equal (&op, &regzmm)
6162 && !operand_type_equal (&op, &regmask)))
c0f3af97 6163 abort ();
f12dc422 6164 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6165 dest++;
6166 }
6167 }
29b0f896
AM		 6168
6169 i.rm.mode = 3;
6170 /* One of the register operands will be encoded in the i.tm.reg
6171 field, the other in the combined i.tm.mode and i.tm.regmem
6172 fields. If no form of this instruction supports a memory
6173 destination operand, then we assume the source operand may
6174 sometimes be a memory operand and so we need to store the
6175 destination in the i.rm.reg field. */
40fb9820
L		 6176 if (!i.tm.operand_types[dest].bitfield.regmem
6177 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6178 {
6179 i.rm.reg = i.op[dest].regs->reg_num;
6180 i.rm.regmem = i.op[source].regs->reg_num;
6181 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6182 i.rex |= REX_R;
43234a1e
L		 6183 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6184 i.vrex |= REX_R;
29b0f896 6185 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6186 i.rex |= REX_B;
43234a1e
L		 6187 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6188 i.vrex |= REX_B;
29b0f896
AM		 6189 }
6190 else
6191 {
6192 i.rm.reg = i.op[source].regs->reg_num;
6193 i.rm.regmem = i.op[dest].regs->reg_num;
6194 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6195 i.rex |= REX_B;
43234a1e
L		 6196 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6197 i.vrex |= REX_B;
29b0f896 6198 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6199 i.rex |= REX_R;
43234a1e
L		 6200 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6201 i.vrex |= REX_R;
29b0f896 6202 }
161a04f6 6203 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6204 {
40fb9820
L		 6205 if (!i.types[0].bitfield.control
6206 && !i.types[1].bitfield.control)
c4a530c5 6207 abort ();
161a04f6 6208 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6209 add_prefix (LOCK_PREFIX_OPCODE);
6210 }
29b0f896
AM		 6211 }
6212 else
6213 { /* If it's not 2 reg operands... */
c0f3af97
L		 6214 unsigned int mem;
6215
29b0f896
AM		 6216 if (i.mem_operands)
6217 {
6218 unsigned int fake_zero_displacement = 0;
99018f42 6219 unsigned int op;
4eed87de 6220
7ab9ffdd
L		 6221 for (op = 0; op < i.operands; op++)
6222 if (operand_type_check (i.types[op], anymem))
6223 break;
7ab9ffdd 6224 gas_assert (op < i.operands);
29b0f896 6225
6c30d220
L		 6226 if (i.tm.opcode_modifier.vecsib)
6227 {
6228 if (i.index_reg->reg_num == RegEiz
6229 || i.index_reg->reg_num == RegRiz)
6230 abort ();
6231
6232 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6233 if (!i.base_reg)
6234 {
6235 i.sib.base = NO_BASE_REGISTER;
6236 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6237 /* No Vec_Disp8 if there is no base. */
6238 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6239 i.types[op].bitfield.disp8 = 0;
6240 i.types[op].bitfield.disp16 = 0;
6241 i.types[op].bitfield.disp64 = 0;
6242 if (flag_code != CODE_64BIT)
6243 {
6244 /* Must be 32 bit */
6245 i.types[op].bitfield.disp32 = 1;
6246 i.types[op].bitfield.disp32s = 0;
6247 }
6248 else
6249 {
6250 i.types[op].bitfield.disp32 = 0;
6251 i.types[op].bitfield.disp32s = 1;
6252 }
6253 }
6254 i.sib.index = i.index_reg->reg_num;
6255 if ((i.index_reg->reg_flags & RegRex) != 0)
6256 i.rex |= REX_X;
43234a1e
L		 6257 if ((i.index_reg->reg_flags & RegVRex) != 0)
6258 i.vrex |= REX_X;
6c30d220
L		 6259 }
6260
29b0f896
AM		 6261 default_seg = &ds;
6262
6263 if (i.base_reg == 0)
6264 {
6265 i.rm.mode = 0;
6266 if (!i.disp_operands)
6c30d220
L		 6267 {
6268 fake_zero_displacement = 1;
6269 /* Instructions with VSIB byte need 32bit displacement
6270 if there is no base register. */
6271 if (i.tm.opcode_modifier.vecsib)
6272 i.types[op].bitfield.disp32 = 1;
6273 }
29b0f896
AM		 6274 if (i.index_reg == 0)
6275 {
6c30d220 6276 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6277 /* Operand is just <disp> */
20f0a1fc 6278 if (flag_code == CODE_64BIT)
29b0f896
AM		 6279 {
6280 /* 64bit mode overwrites the 32bit absolute
6281 addressing by RIP relative addressing and
6282 absolute addressing is encoded by one of the
6283 redundant SIB forms. */
6284 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6285 i.sib.base = NO_BASE_REGISTER;
6286 i.sib.index = NO_INDEX_REGISTER;
fc225355 6287 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6288 ? disp32s : disp32);
20f0a1fc 6289 }
fc225355
L		 6290 else if ((flag_code == CODE_16BIT)
6291 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6292 {
6293 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6294 i.types[op] = disp16;
20f0a1fc
NC		 6295 }
6296 else
6297 {
6298 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6299 i.types[op] = disp32;
29b0f896
AM		 6300 }
6301 }
6c30d220 6302 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6303 {
6c30d220 6304 /* !i.base_reg && i.index_reg */
db51cc60
L		 6305 if (i.index_reg->reg_num == RegEiz
6306 || i.index_reg->reg_num == RegRiz)
6307 i.sib.index = NO_INDEX_REGISTER;
6308 else
6309 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6310 i.sib.base = NO_BASE_REGISTER;
6311 i.sib.scale = i.log2_scale_factor;
6312 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6313 /* No Vec_Disp8 if there is no base. */
6314 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6315 i.types[op].bitfield.disp8 = 0;
6316 i.types[op].bitfield.disp16 = 0;
6317 i.types[op].bitfield.disp64 = 0;
29b0f896 6318 if (flag_code != CODE_64BIT)
40fb9820
L		 6319 {
6320 /* Must be 32 bit */
6321 i.types[op].bitfield.disp32 = 1;
6322 i.types[op].bitfield.disp32s = 0;
6323 }
29b0f896 6324 else
40fb9820
L		 6325 {
6326 i.types[op].bitfield.disp32 = 0;
6327 i.types[op].bitfield.disp32s = 1;
6328 }
29b0f896 6329 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6330 i.rex |= REX_X;
29b0f896
AM		 6331 }
6332 }
6333 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6334 else if (i.base_reg->reg_num == RegRip ||
6335 i.base_reg->reg_num == RegEip)
29b0f896 6336 {
6c30d220 6337 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6338 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6339 i.types[op].bitfield.disp8 = 0;
6340 i.types[op].bitfield.disp16 = 0;
6341 i.types[op].bitfield.disp32 = 0;
6342 i.types[op].bitfield.disp32s = 1;
6343 i.types[op].bitfield.disp64 = 0;
43234a1e 6344 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6345 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6346 if (! i.disp_operands)
6347 fake_zero_displacement = 1;
29b0f896 6348 }
40fb9820 6349 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6350 {
6c30d220 6351 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6352 switch (i.base_reg->reg_num)
6353 {
6354 case 3: /* (%bx) */
6355 if (i.index_reg == 0)
6356 i.rm.regmem = 7;
6357 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6358 i.rm.regmem = i.index_reg->reg_num - 6;
6359 break;
6360 case 5: /* (%bp) */
6361 default_seg = &ss;
6362 if (i.index_reg == 0)
6363 {
6364 i.rm.regmem = 6;
40fb9820 6365 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6366 {
6367 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6368 if (i.tm.operand_types[op].bitfield.vec_disp8)
6369 i.types[op].bitfield.vec_disp8 = 1;
6370 else
6371 i.types[op].bitfield.disp8 = 1;
252b5132 6372 fake_zero_displacement = 1;
29b0f896
AM		 6373 }
6374 }
6375 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6376 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6377 break;
6378 default: /* (%si) -> 4 or (%di) -> 5 */
6379 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6380 }
6381 i.rm.mode = mode_from_disp_size (i.types[op]);
6382 }
6383 else /* i.base_reg and 32/64 bit mode */
6384 {
6385 if (flag_code == CODE_64BIT
40fb9820
L		 6386 && operand_type_check (i.types[op], disp))
6387 {
6388 i386_operand_type temp;
0dfbf9d7 6389 operand_type_set (&temp, 0);
40fb9820 6390 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6391 temp.bitfield.vec_disp8
6392 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6393 i.types[op] = temp;
6394 if (i.prefix[ADDR_PREFIX] == 0)
6395 i.types[op].bitfield.disp32s = 1;
6396 else
6397 i.types[op].bitfield.disp32 = 1;
6398 }
20f0a1fc 6399
6c30d220
L		 6400 if (!i.tm.opcode_modifier.vecsib)
6401 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6402 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6403 i.rex |= REX_B;
29b0f896
AM		 6404 i.sib.base = i.base_reg->reg_num;
6405 /* x86-64 ignores REX prefix bit here to avoid decoder
6406 complications. */
848930b2
JB		 6407 if (!(i.base_reg->reg_flags & RegRex)
6408 && (i.base_reg->reg_num == EBP_REG_NUM
6409 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6410 default_seg = &ss;
848930b2 6411 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6412 {
848930b2 6413 fake_zero_displacement = 1;
43234a1e
L		 6414 if (i.tm.operand_types [op].bitfield.vec_disp8)
6415 i.types[op].bitfield.vec_disp8 = 1;
6416 else
6417 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6418 }
6419 i.sib.scale = i.log2_scale_factor;
6420 if (i.index_reg == 0)
6421 {
6c30d220 6422 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6423 /* <disp>(%esp) becomes two byte modrm with no index
6424 register. We've already stored the code for esp
6425 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6426 Any base register besides %esp will not use the
6427 extra modrm byte. */
6428 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6429 }
6c30d220 6430 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6431 {
db51cc60
L		 6432 if (i.index_reg->reg_num == RegEiz
6433 || i.index_reg->reg_num == RegRiz)
6434 i.sib.index = NO_INDEX_REGISTER;
6435 else
6436 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6437 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6438 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6439 i.rex |= REX_X;
29b0f896 6440 }
67a4f2b7
AO		 6441
6442 if (i.disp_operands
6443 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6444 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6445 i.rm.mode = 0;
6446 else
a501d77e
L		 6447 {
6448 if (!fake_zero_displacement
6449 && !i.disp_operands
6450 && i.disp_encoding)
6451 {
6452 fake_zero_displacement = 1;
6453 if (i.disp_encoding == disp_encoding_8bit)
6454 i.types[op].bitfield.disp8 = 1;
6455 else
6456 i.types[op].bitfield.disp32 = 1;
6457 }
6458 i.rm.mode = mode_from_disp_size (i.types[op]);
6459 }
29b0f896 6460 }
252b5132 6461
29b0f896
AM		 6462 if (fake_zero_displacement)
6463 {
6464 /* Fakes a zero displacement assuming that i.types[op]
6465 holds the correct displacement size. */
6466 expressionS *exp;
6467
9c2799c2 6468 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6469 exp = &disp_expressions[i.disp_operands++];
6470 i.op[op].disps = exp;
6471 exp->X_op = O_constant;
6472 exp->X_add_number = 0;
6473 exp->X_add_symbol = (symbolS *) 0;
6474 exp->X_op_symbol = (symbolS *) 0;
6475 }
c0f3af97
L		 6476
6477 mem = op;
29b0f896 6478 }
c0f3af97
L		 6479 else
6480 mem = ~0;
252b5132 6481
8c43a48b 6482 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6483 {
6484 if (operand_type_check (i.types[0], imm))
6485 i.vex.register_specifier = NULL;
6486 else
6487 {
6488 /* VEX.vvvv encodes one of the sources when the first
6489 operand is not an immediate. */
1ef99a7b 6490 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6491 i.vex.register_specifier = i.op[0].regs;
6492 else
6493 i.vex.register_specifier = i.op[1].regs;
6494 }
6495
6496 /* Destination is a XMM register encoded in the ModRM.reg
6497 and VEX.R bit. */
6498 i.rm.reg = i.op[2].regs->reg_num;
6499 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6500 i.rex |= REX_R;
6501
6502 /* ModRM.rm and VEX.B encodes the other source. */
6503 if (!i.mem_operands)
6504 {
6505 i.rm.mode = 3;
6506
1ef99a7b 6507 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6508 i.rm.regmem = i.op[1].regs->reg_num;
6509 else
6510 i.rm.regmem = i.op[0].regs->reg_num;
6511
6512 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6513 i.rex |= REX_B;
6514 }
6515 }
2426c15f 6516 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6517 {
6518 i.vex.register_specifier = i.op[2].regs;
6519 if (!i.mem_operands)
6520 {
6521 i.rm.mode = 3;
6522 i.rm.regmem = i.op[1].regs->reg_num;
6523 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6524 i.rex |= REX_B;
6525 }
6526 }
29b0f896
AM		 6527 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6528 (if any) based on i.tm.extension_opcode. Again, we must be
6529 careful to make sure that segment/control/debug/test/MMX
6530 registers are coded into the i.rm.reg field. */
f88c9eb0 6531 else if (i.reg_operands)
29b0f896 6532 {
99018f42 6533 unsigned int op;
7ab9ffdd
L		 6534 unsigned int vex_reg = ~0;
6535
6536 for (op = 0; op < i.operands; op++)
6537 if (i.types[op].bitfield.reg8
6538 || i.types[op].bitfield.reg16
6539 || i.types[op].bitfield.reg32
6540 || i.types[op].bitfield.reg64
6541 || i.types[op].bitfield.regmmx
6542 || i.types[op].bitfield.regxmm
6543 || i.types[op].bitfield.regymm
7e8b059b 6544 || i.types[op].bitfield.regbnd
43234a1e
L		 6545 || i.types[op].bitfield.regzmm
6546 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6547 || i.types[op].bitfield.sreg2
6548 || i.types[op].bitfield.sreg3
6549 || i.types[op].bitfield.control
6550 || i.types[op].bitfield.debug
6551 || i.types[op].bitfield.test)
6552 break;
c0209578 6553
7ab9ffdd
L		 6554 if (vex_3_sources)
6555 op = dest;
2426c15f 6556 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6557 {
6558 /* For instructions with VexNDS, the register-only
6559 source operand is encoded in VEX prefix. */
6560 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6561
7ab9ffdd 6562 if (op > mem)
c0f3af97 6563 {
7ab9ffdd
L		 6564 vex_reg = op++;
6565 gas_assert (op < i.operands);
c0f3af97
L		 6566 }
6567 else
c0f3af97 6568 {
f12dc422
L		 6569 /* Check register-only source operand when two source
6570 operands are swapped. */
6571 if (!i.tm.operand_types[op].bitfield.baseindex
6572 && i.tm.operand_types[op + 1].bitfield.baseindex)
6573 {
6574 vex_reg = op;
6575 op += 2;
6576 gas_assert (mem == (vex_reg + 1)
6577 && op < i.operands);
6578 }
6579 else
6580 {
6581 vex_reg = op + 1;
6582 gas_assert (vex_reg < i.operands);
6583 }
c0f3af97 6584 }
7ab9ffdd 6585 }
2426c15f 6586 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6587 {
f12dc422 6588 /* For instructions with VexNDD, the register destination
7ab9ffdd 6589 is encoded in VEX prefix. */
f12dc422
L		 6590 if (i.mem_operands == 0)
6591 {
6592 /* There is no memory operand. */
6593 gas_assert ((op + 2) == i.operands);
6594 vex_reg = op + 1;
6595 }
6596 else
8d63c93e 6597 {
f12dc422
L		 6598 /* There are only 2 operands. */
6599 gas_assert (op < 2 && i.operands == 2);
6600 vex_reg = 1;
6601 }
7ab9ffdd
L		 6602 }
6603 else
6604 gas_assert (op < i.operands);
99018f42 6605
7ab9ffdd
L		 6606 if (vex_reg != (unsigned int) ~0)
6607 {
f12dc422 6608 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6609
f12dc422
L		 6610 if (type->bitfield.reg32 != 1
6611 && type->bitfield.reg64 != 1
6612 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6613 && !operand_type_equal (type, &regymm)
6614 && !operand_type_equal (type, &regzmm)
6615 && !operand_type_equal (type, &regmask))
7ab9ffdd 6616 abort ();
f88c9eb0 6617
7ab9ffdd
L		 6618 i.vex.register_specifier = i.op[vex_reg].regs;
6619 }
6620
1b9f0c97
L		 6621 /* Don't set OP operand twice. */
6622 if (vex_reg != op)
7ab9ffdd 6623 {
1b9f0c97
L		 6624 /* If there is an extension opcode to put here, the
6625 register number must be put into the regmem field. */
6626 if (i.tm.extension_opcode != None)
6627 {
6628 i.rm.regmem = i.op[op].regs->reg_num;
6629 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6630 i.rex |= REX_B;
43234a1e
L		 6631 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6632 i.vrex |= REX_B;
1b9f0c97
L		 6633 }
6634 else
6635 {
6636 i.rm.reg = i.op[op].regs->reg_num;
6637 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6638 i.rex |= REX_R;
43234a1e
L		 6639 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6640 i.vrex |= REX_R;
1b9f0c97 6641 }
7ab9ffdd 6642 }
252b5132 6643
29b0f896
AM		 6644 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6645 must set it to 3 to indicate this is a register operand
6646 in the regmem field. */
6647 if (!i.mem_operands)
6648 i.rm.mode = 3;
6649 }
252b5132 6650
29b0f896 6651 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6652 if (i.tm.extension_opcode != None)
29b0f896
AM		 6653 i.rm.reg = i.tm.extension_opcode;
6654 }
6655 return default_seg;
6656}
252b5132 6657
29b0f896 6658static void
e3bb37b5 6659output_branch (void)
29b0f896
AM		 6660{
6661 char *p;
f8a5c266 6662 int size;
29b0f896
AM		 6663 int code16;
6664 int prefix;
6665 relax_substateT subtype;
6666 symbolS *sym;
6667 offsetT off;
6668
f8a5c266 6669 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6670 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6671
6672 prefix = 0;
6673 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6674 {
29b0f896
AM		 6675 prefix = 1;
6676 i.prefixes -= 1;
6677 code16 ^= CODE16;
252b5132 6678 }
29b0f896
AM		 6679 /* Pentium4 branch hints. */
6680 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6681 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6682 {
29b0f896
AM		 6683 prefix++;
6684 i.prefixes--;
6685 }
6686 if (i.prefix[REX_PREFIX] != 0)
6687 {
6688 prefix++;
6689 i.prefixes--;
2f66722d
AM		 6690 }
6691
7e8b059b
L		 6692 /* BND prefixed jump. */
6693 if (i.prefix[BND_PREFIX] != 0)
6694 {
6695 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6696 i.prefixes -= 1;
6697 }
6698
29b0f896
AM		 6699 if (i.prefixes != 0 && !intel_syntax)
6700 as_warn (_("skipping prefixes on this instruction"));
6701
6702 /* It's always a symbol; End frag & setup for relax.
6703 Make sure there is enough room in this frag for the largest
6704 instruction we may generate in md_convert_frag. This is 2
6705 bytes for the opcode and room for the prefix and largest
6706 displacement. */
6707 frag_grow (prefix + 2 + 4);
6708 /* Prefix and 1 opcode byte go in fr_fix. */
6709 p = frag_more (prefix + 1);
6710 if (i.prefix[DATA_PREFIX] != 0)
6711 *p++ = DATA_PREFIX_OPCODE;
6712 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6713 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6714 *p++ = i.prefix[SEG_PREFIX];
6715 if (i.prefix[REX_PREFIX] != 0)
6716 *p++ = i.prefix[REX_PREFIX];
6717 *p = i.tm.base_opcode;
6718
6719 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6720 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6721 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6722 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6723 else
f8a5c266 6724 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6725 subtype |= code16;
3e73aa7c 6726
29b0f896
AM		 6727 sym = i.op[0].disps->X_add_symbol;
6728 off = i.op[0].disps->X_add_number;
3e73aa7c 6729
29b0f896
AM		 6730 if (i.op[0].disps->X_op != O_constant
6731 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6732 {
29b0f896
AM		 6733 /* Handle complex expressions. */
6734 sym = make_expr_symbol (i.op[0].disps);
6735 off = 0;
6736 }
3e73aa7c 6737
29b0f896
AM		 6738 /* 1 possible extra opcode + 4 byte displacement go in var part.
6739 Pass reloc in fr_var. */
c3320543
L		 6740 frag_var (rs_machine_dependent, 5,
6741 ((!object_64bit
6742 || i.reloc[0] != NO_RELOC
6743 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6744 ? i.reloc[0]
6745 : BFD_RELOC_X86_64_PC32_BND),
6746 subtype, sym, off, p);
29b0f896 6747}
3e73aa7c 6748
29b0f896 6749static void
e3bb37b5 6750output_jump (void)
29b0f896
AM		 6751{
6752 char *p;
6753 int size;
3e02c1cc 6754 fixS *fixP;
29b0f896 6755
40fb9820 6756 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6757 {
6758 /* This is a loop or jecxz type instruction. */
6759 size = 1;
6760 if (i.prefix[ADDR_PREFIX] != 0)
6761 {
6762 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6763 i.prefixes -= 1;
6764 }
6765 /* Pentium4 branch hints. */
6766 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6767 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6768 {
6769 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6770 i.prefixes--;
3e73aa7c
JH		 6771 }
6772 }
29b0f896
AM		 6773 else
6774 {
6775 int code16;
3e73aa7c 6776
29b0f896
AM		 6777 code16 = 0;
6778 if (flag_code == CODE_16BIT)
6779 code16 = CODE16;
3e73aa7c 6780
29b0f896
AM		 6781 if (i.prefix[DATA_PREFIX] != 0)
6782 {
6783 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6784 i.prefixes -= 1;
6785 code16 ^= CODE16;
6786 }
252b5132 6787
29b0f896
AM		 6788 size = 4;
6789 if (code16)
6790 size = 2;
6791 }
9fcc94b6 6792
29b0f896
AM		 6793 if (i.prefix[REX_PREFIX] != 0)
6794 {
6795 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6796 i.prefixes -= 1;
6797 }
252b5132 6798
7e8b059b
L		 6799 /* BND prefixed jump. */
6800 if (i.prefix[BND_PREFIX] != 0)
6801 {
6802 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6803 i.prefixes -= 1;
6804 }
6805
29b0f896
AM		 6806 if (i.prefixes != 0 && !intel_syntax)
6807 as_warn (_("skipping prefixes on this instruction"));
e0890092 6808
42164a71
L		 6809 p = frag_more (i.tm.opcode_length + size);
6810 switch (i.tm.opcode_length)
6811 {
6812 case 2:
6813 *p++ = i.tm.base_opcode >> 8;
6814 case 1:
6815 *p++ = i.tm.base_opcode;
6816 break;
6817 default:
6818 abort ();
6819 }
e0890092 6820
3e02c1cc 6821 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6822 i.op[0].disps, 1, reloc (size, 1, 1,
6823 (i.bnd_prefix != NULL
6824 || add_bnd_prefix),
6825 i.reloc[0]));
3e02c1cc
AM		 6826
6827 /* All jumps handled here are signed, but don't use a signed limit
6828 check for 32 and 16 bit jumps as we want to allow wrap around at
6829 4G and 64k respectively. */
6830 if (size == 1)
6831 fixP->fx_signed = 1;
29b0f896 6832}
e0890092 6833
29b0f896 6834static void
e3bb37b5 6835output_interseg_jump (void)
29b0f896
AM		 6836{
6837 char *p;
6838 int size;
6839 int prefix;
6840 int code16;
252b5132 6841
29b0f896
AM		 6842 code16 = 0;
6843 if (flag_code == CODE_16BIT)
6844 code16 = CODE16;
a217f122 6845
29b0f896
AM		 6846 prefix = 0;
6847 if (i.prefix[DATA_PREFIX] != 0)
6848 {
6849 prefix = 1;
6850 i.prefixes -= 1;
6851 code16 ^= CODE16;
6852 }
6853 if (i.prefix[REX_PREFIX] != 0)
6854 {
6855 prefix++;
6856 i.prefixes -= 1;
6857 }
252b5132 6858
29b0f896
AM		 6859 size = 4;
6860 if (code16)
6861 size = 2;
252b5132 6862
29b0f896
AM		 6863 if (i.prefixes != 0 && !intel_syntax)
6864 as_warn (_("skipping prefixes on this instruction"));
252b5132 6865
29b0f896
AM		 6866 /* 1 opcode; 2 segment; offset */
6867 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6868
29b0f896
AM		 6869 if (i.prefix[DATA_PREFIX] != 0)
6870 *p++ = DATA_PREFIX_OPCODE;
252b5132 6871
29b0f896
AM		 6872 if (i.prefix[REX_PREFIX] != 0)
6873 *p++ = i.prefix[REX_PREFIX];
252b5132 6874
29b0f896
AM		 6875 *p++ = i.tm.base_opcode;
6876 if (i.op[1].imms->X_op == O_constant)
6877 {
6878 offsetT n = i.op[1].imms->X_add_number;
252b5132 6879
29b0f896
AM		 6880 if (size == 2
6881 && !fits_in_unsigned_word (n)
6882 && !fits_in_signed_word (n))
6883 {
6884 as_bad (_("16-bit jump out of range"));
6885 return;
6886 }
6887 md_number_to_chars (p, n, size);
6888 }
6889 else
6890 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6891 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6892 if (i.op[0].imms->X_op != O_constant)
6893 as_bad (_("can't handle non absolute segment in `%s'"),
6894 i.tm.name);
6895 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6896}
a217f122 6897
29b0f896 6898static void
e3bb37b5 6899output_insn (void)
29b0f896 6900{
2bbd9c25
JJ		 6901 fragS *insn_start_frag;
6902 offsetT insn_start_off;
6903
29b0f896
AM		 6904 /* Tie dwarf2 debug info to the address at the start of the insn.
6905 We can't do this after the insn has been output as the current
6906 frag may have been closed off. eg. by frag_var. */
6907 dwarf2_emit_insn (0);
6908
2bbd9c25
JJ		 6909 insn_start_frag = frag_now;
6910 insn_start_off = frag_now_fix ();
6911
29b0f896 6912 /* Output jumps. */
40fb9820 6913 if (i.tm.opcode_modifier.jump)
29b0f896 6914 output_branch ();
40fb9820
L		 6915 else if (i.tm.opcode_modifier.jumpbyte
6916 || i.tm.opcode_modifier.jumpdword)
29b0f896 6917 output_jump ();
40fb9820 6918 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6919 output_interseg_jump ();
6920 else
6921 {
6922 /* Output normal instructions here. */
6923 char *p;
6924 unsigned char *q;
47465058 6925 unsigned int j;
331d2d0d 6926 unsigned int prefix;
4dffcebc 6927
43234a1e
L		 6928 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6929 don't need the explicit prefix. */
6930 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6931 {
c0f3af97 6932 switch (i.tm.opcode_length)
bc4bd9ab 6933 {
c0f3af97
L		 6934 case 3:
6935 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6936 {
c0f3af97
L		 6937 prefix = (i.tm.base_opcode >> 24) & 0xff;
6938 goto check_prefix;
6939 }
6940 break;
6941 case 2:
6942 if ((i.tm.base_opcode & 0xff0000) != 0)
6943 {
6944 prefix = (i.tm.base_opcode >> 16) & 0xff;
6945 if (i.tm.cpu_flags.bitfield.cpupadlock)
6946 {
4dffcebc 6947check_prefix:
c0f3af97 6948 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6949 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6950 != REPE_PREFIX_OPCODE))
6951 add_prefix (prefix);
6952 }
6953 else
4dffcebc
L		 6954 add_prefix (prefix);
6955 }
c0f3af97
L		 6956 break;
6957 case 1:
6958 break;
6959 default:
6960 abort ();
bc4bd9ab 6961 }
c0f3af97
L		 6962
6963 /* The prefix bytes. */
6964 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6965 if (*q)
6966 FRAG_APPEND_1_CHAR (*q);
0f10071e 6967 }
ae5c1c7b 6968 else
c0f3af97
L		 6969 {
6970 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6971 if (*q)
6972 switch (j)
6973 {
6974 case REX_PREFIX:
6975 /* REX byte is encoded in VEX prefix. */
6976 break;
6977 case SEG_PREFIX:
6978 case ADDR_PREFIX:
6979 FRAG_APPEND_1_CHAR (*q);
6980 break;
6981 default:
6982 /* There should be no other prefixes for instructions
6983 with VEX prefix. */
6984 abort ();
6985 }
6986
43234a1e
L		 6987 /* For EVEX instructions i.vrex should become 0 after
6988 build_evex_prefix. For VEX instructions upper 16 registers
6989 aren't available, so VREX should be 0. */
6990 if (i.vrex)
6991 abort ();
c0f3af97
L		 6992 /* Now the VEX prefix. */
6993 p = frag_more (i.vex.length);
6994 for (j = 0; j < i.vex.length; j++)
6995 p[j] = i.vex.bytes[j];
6996 }
252b5132 6997
29b0f896 6998 /* Now the opcode; be careful about word order here! */
4dffcebc 6999 if (i.tm.opcode_length == 1)
29b0f896
AM		 7000 {
7001 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7002 }
7003 else
7004 {
4dffcebc 7005 switch (i.tm.opcode_length)
331d2d0d 7006 {
43234a1e
L		 7007 case 4:
7008 p = frag_more (4);
7009 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7010 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7011 break;
4dffcebc 7012 case 3:
331d2d0d
L		 7013 p = frag_more (3);
7014 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7015 break;
7016 case 2:
7017 p = frag_more (2);
7018 break;
7019 default:
7020 abort ();
7021 break;
331d2d0d 7022 }
0f10071e 7023
29b0f896
AM		 7024 /* Put out high byte first: can't use md_number_to_chars! */
7025 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7026 *p = i.tm.base_opcode & 0xff;
7027 }
3e73aa7c 7028
29b0f896 7029 /* Now the modrm byte and sib byte (if present). */
40fb9820 7030 if (i.tm.opcode_modifier.modrm)
29b0f896 7031 {
4a3523fa
L		 7032 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7033 | i.rm.reg << 3
7034 | i.rm.mode << 6));
29b0f896
AM		 7035 /* If i.rm.regmem == ESP (4)
7036 && i.rm.mode != (Register mode)
7037 && not 16 bit
7038 ==> need second modrm byte. */
7039 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7040 && i.rm.mode != 3
40fb9820 7041 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7042 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7043 | i.sib.index << 3
7044 | i.sib.scale << 6));
29b0f896 7045 }
3e73aa7c 7046
29b0f896 7047 if (i.disp_operands)
2bbd9c25 7048 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7049
29b0f896 7050 if (i.imm_operands)
2bbd9c25 7051 output_imm (insn_start_frag, insn_start_off);
29b0f896 7052 }
252b5132 7053
29b0f896
AM		 7054#ifdef DEBUG386
7055 if (flag_debug)
7056 {
7b81dfbb 7057 pi ("" /*line*/, &i);
29b0f896
AM		 7058 }
7059#endif /* DEBUG386 */
7060}
252b5132 7061
e205caa7
L		 7062/* Return the size of the displacement operand N. */
7063
7064static int
7065disp_size (unsigned int n)
7066{
7067 int size = 4;
43234a1e
L		 7068
7069 /* Vec_Disp8 has to be 8bit. */
7070 if (i.types[n].bitfield.vec_disp8)
7071 size = 1;
7072 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7073 size = 8;
7074 else if (i.types[n].bitfield.disp8)
7075 size = 1;
7076 else if (i.types[n].bitfield.disp16)
7077 size = 2;
e205caa7
L		 7078 return size;
7079}
7080
7081/* Return the size of the immediate operand N. */
7082
7083static int
7084imm_size (unsigned int n)
7085{
7086 int size = 4;
40fb9820
L		 7087 if (i.types[n].bitfield.imm64)
7088 size = 8;
7089 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7090 size = 1;
7091 else if (i.types[n].bitfield.imm16)
7092 size = 2;
e205caa7
L		 7093 return size;
7094}
7095
29b0f896 7096static void
64e74474 7097output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7098{
7099 char *p;
7100 unsigned int n;
252b5132 7101
29b0f896
AM		 7102 for (n = 0; n < i.operands; n++)
7103 {
43234a1e
L		 7104 if (i.types[n].bitfield.vec_disp8
7105 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7106 {
7107 if (i.op[n].disps->X_op == O_constant)
7108 {
e205caa7 7109 int size = disp_size (n);
43234a1e 7110 offsetT val = i.op[n].disps->X_add_number;
252b5132 7111
43234a1e
L		 7112 if (i.types[n].bitfield.vec_disp8)
7113 val >>= i.memshift;
7114 val = offset_in_range (val, size);
29b0f896
AM		 7115 p = frag_more (size);
7116 md_number_to_chars (p, val, size);
7117 }
7118 else
7119 {
f86103b7 7120 enum bfd_reloc_code_real reloc_type;
e205caa7 7121 int size = disp_size (n);
40fb9820 7122 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7123 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7124
e205caa7 7125 /* We can't have 8 bit displacement here. */
9c2799c2 7126 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7127
29b0f896
AM		 7128 /* The PC relative address is computed relative
7129 to the instruction boundary, so in case immediate
7130 fields follows, we need to adjust the value. */
7131 if (pcrel && i.imm_operands)
7132 {
29b0f896 7133 unsigned int n1;
e205caa7 7134 int sz = 0;
252b5132 7135
29b0f896 7136 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7137 if (operand_type_check (i.types[n1], imm))
252b5132 7138 {
e205caa7
L		 7139 /* Only one immediate is allowed for PC
7140 relative address. */
9c2799c2 7141 gas_assert (sz == 0);
e205caa7
L		 7142 sz = imm_size (n1);
7143 i.op[n].disps->X_add_number -= sz;
252b5132 7144 }
29b0f896 7145 /* We should find the immediate. */
9c2799c2 7146 gas_assert (sz != 0);
29b0f896 7147 }
520dc8e8 7148
29b0f896 7149 p = frag_more (size);
c3320543
L		 7150 reloc_type = reloc (size, pcrel, sign,
7151 (i.bnd_prefix != NULL
7152 || add_bnd_prefix),
7153 i.reloc[n]);
d6ab8113 7154 if (GOT_symbol
2bbd9c25 7155 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7156 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7157 || reloc_type == BFD_RELOC_X86_64_32S
7158 || (reloc_type == BFD_RELOC_64
7159 && object_64bit))
d6ab8113
JB		 7160 && (i.op[n].disps->X_op == O_symbol
7161 || (i.op[n].disps->X_op == O_add
7162 && ((symbol_get_value_expression
7163 (i.op[n].disps->X_op_symbol)->X_op)
7164 == O_subtract))))
7165 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7166 {
7167 offsetT add;
7168
7169 if (insn_start_frag == frag_now)
7170 add = (p - frag_now->fr_literal) - insn_start_off;
7171 else
7172 {
7173 fragS *fr;
7174
7175 add = insn_start_frag->fr_fix - insn_start_off;
7176 for (fr = insn_start_frag->fr_next;
7177 fr && fr != frag_now; fr = fr->fr_next)
7178 add += fr->fr_fix;
7179 add += p - frag_now->fr_literal;
7180 }
7181
4fa24527 7182 if (!object_64bit)
7b81dfbb
AJ		 7183 {
7184 reloc_type = BFD_RELOC_386_GOTPC;
7185 i.op[n].imms->X_add_number += add;
7186 }
7187 else if (reloc_type == BFD_RELOC_64)
7188 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7189 else
7b81dfbb
AJ		 7190 /* Don't do the adjustment for x86-64, as there
7191 the pcrel addressing is relative to the _next_
7192 insn, and that is taken care of in other code. */
d6ab8113 7193 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7194 }
062cd5e7 7195 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7196 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7197 }
7198 }
7199 }
7200}
252b5132 7201
29b0f896 7202static void
64e74474 7203output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7204{
7205 char *p;
7206 unsigned int n;
252b5132 7207
29b0f896
AM		 7208 for (n = 0; n < i.operands; n++)
7209 {
43234a1e
L		 7210 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7211 if (i.rounding && (int) n == i.rounding->operand)
7212 continue;
7213
40fb9820 7214 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7215 {
7216 if (i.op[n].imms->X_op == O_constant)
7217 {
e205caa7 7218 int size = imm_size (n);
29b0f896 7219 offsetT val;
b4cac588 7220
29b0f896
AM		 7221 val = offset_in_range (i.op[n].imms->X_add_number,
7222 size);
7223 p = frag_more (size);
7224 md_number_to_chars (p, val, size);
7225 }
7226 else
7227 {
7228 /* Not absolute_section.
7229 Need a 32-bit fixup (don't support 8bit
7230 non-absolute imms). Try to support other
7231 sizes ... */
f86103b7 7232 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7233 int size = imm_size (n);
7234 int sign;
29b0f896 7235
40fb9820 7236 if (i.types[n].bitfield.imm32s
a7d61044 7237 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7238 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7239 sign = 1;
e205caa7
L		 7240 else
7241 sign = 0;
520dc8e8 7242
29b0f896 7243 p = frag_more (size);
c3320543 7244 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7245
2bbd9c25
JJ		 7246 /* This is tough to explain. We end up with this one if we
7247 * have operands that look like
7248 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7249 * obtain the absolute address of the GOT, and it is strongly
7250 * preferable from a performance point of view to avoid using
7251 * a runtime relocation for this. The actual sequence of
7252 * instructions often look something like:
7253 *
7254 * call .L66
7255 * .L66:
7256 * popl %ebx
7257 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7258 *
7259 * The call and pop essentially return the absolute address
7260 * of the label .L66 and store it in %ebx. The linker itself
7261 * will ultimately change the first operand of the addl so
7262 * that %ebx points to the GOT, but to keep things simple, the
7263 * .o file must have this operand set so that it generates not
7264 * the absolute address of .L66, but the absolute address of
7265 * itself. This allows the linker itself simply treat a GOTPC
7266 * relocation as asking for a pcrel offset to the GOT to be
7267 * added in, and the addend of the relocation is stored in the
7268 * operand field for the instruction itself.
7269 *
7270 * Our job here is to fix the operand so that it would add
7271 * the correct offset so that %ebx would point to itself. The
7272 * thing that is tricky is that .-.L66 will point to the
7273 * beginning of the instruction, so we need to further modify
7274 * the operand so that it will point to itself. There are
7275 * other cases where you have something like:
7276 *
7277 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7278 *
7279 * and here no correction would be required. Internally in
7280 * the assembler we treat operands of this form as not being
7281 * pcrel since the '.' is explicitly mentioned, and I wonder
7282 * whether it would simplify matters to do it this way. Who
7283 * knows. In earlier versions of the PIC patches, the
7284 * pcrel_adjust field was used to store the correction, but
7285 * since the expression is not pcrel, I felt it would be
7286 * confusing to do it this way. */
7287
d6ab8113 7288 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7289 || reloc_type == BFD_RELOC_X86_64_32S
7290 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7291 && GOT_symbol
7292 && GOT_symbol == i.op[n].imms->X_add_symbol
7293 && (i.op[n].imms->X_op == O_symbol
7294 || (i.op[n].imms->X_op == O_add
7295 && ((symbol_get_value_expression
7296 (i.op[n].imms->X_op_symbol)->X_op)
7297 == O_subtract))))
7298 {
2bbd9c25
JJ		 7299 offsetT add;
7300
7301 if (insn_start_frag == frag_now)
7302 add = (p - frag_now->fr_literal) - insn_start_off;
7303 else
7304 {
7305 fragS *fr;
7306
7307 add = insn_start_frag->fr_fix - insn_start_off;
7308 for (fr = insn_start_frag->fr_next;
7309 fr && fr != frag_now; fr = fr->fr_next)
7310 add += fr->fr_fix;
7311 add += p - frag_now->fr_literal;
7312 }
7313
4fa24527 7314 if (!object_64bit)
d6ab8113 7315 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7316 else if (size == 4)
d6ab8113 7317 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7318 else if (size == 8)
7319 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7320 i.op[n].imms->X_add_number += add;
29b0f896 7321 }
29b0f896
AM		 7322 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7323 i.op[n].imms, 0, reloc_type);
7324 }
7325 }
7326 }
252b5132
RH		 7327}
7328\f
d182319b
JB		 7329/* x86_cons_fix_new is called via the expression parsing code when a
7330 reloc is needed. We use this hook to get the correct .got reloc. */
7331static enum bfd_reloc_code_real got_reloc = NO_RELOC;
7332static int cons_sign = -1;
7333
7334void
e3bb37b5 7335x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 7336 expressionS *exp)
d182319b 7337{
c3320543 7338 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, 0, got_reloc);
d182319b
JB		 7339
7340 got_reloc = NO_RELOC;
7341
7342#ifdef TE_PE
7343 if (exp->X_op == O_secrel)
7344 {
7345 exp->X_op = O_symbol;
7346 r = BFD_RELOC_32_SECREL;
7347 }
7348#endif
7349
7350 fix_new_exp (frag, off, len, exp, 0, r);
7351}
7352
357d1bd8
L		 7353/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7354 purpose of the `.dc.a' internal pseudo-op. */
7355
7356int
7357x86_address_bytes (void)
7358{
7359 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7360 return 4;
7361 return stdoutput->arch_info->bits_per_address / 8;
7362}
7363
d382c579
TG		 7364#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7365 || defined (LEX_AT)
c06ec724 7366# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7367#else
f3c180ae
AM		 7368/* Parse operands of the form
7369 <symbol>@GOTOFF+<nnn>
7370 and similar .plt or .got references.
7371
7372 If we find one, set up the correct relocation in RELOC and copy the
7373 input string, minus the `@GOTOFF' into a malloc'd buffer for
7374 parsing by the calling routine. Return this buffer, and if ADJUST
7375 is non-null set it to the length of the string we removed from the
7376 input line. Otherwise return NULL. */
7377static char *
91d6fa6a 7378lex_got (enum bfd_reloc_code_real *rel,
64e74474 7379 int *adjust,
c3320543
L		 7380 i386_operand_type *types,
7381 int bnd_prefix)
f3c180ae 7382{
7b81dfbb
AJ		 7383 /* Some of the relocations depend on the size of what field is to
7384 be relocated. But in our callers i386_immediate and i386_displacement
7385 we don't yet know the operand size (this will be set by insn
7386 matching). Hence we record the word32 relocation here,
7387 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7388 static const struct {
7389 const char *str;
cff8d58a 7390 int len;
4fa24527 7391 const enum bfd_reloc_code_real rel[2];
40fb9820 7392 const i386_operand_type types64;
f3c180ae 7393 } gotrel[] = {
8ce3d284 7394#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7395 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7396 BFD_RELOC_SIZE32 },
7397 OPERAND_TYPE_IMM32_64 },
8ce3d284 7398#endif
cff8d58a
L		 7399 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7400 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7401 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7402 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7403 BFD_RELOC_X86_64_PLT32 },
40fb9820 7404 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7405 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7406 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7407 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7408 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7409 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7410 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7411 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7412 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7413 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7414 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7415 BFD_RELOC_X86_64_TLSGD },
40fb9820 7416 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7417 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7418 _dummy_first_bfd_reloc_code_real },
40fb9820 7419 OPERAND_TYPE_NONE },
cff8d58a
L		 7420 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7421 BFD_RELOC_X86_64_TLSLD },
40fb9820 7422 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7423 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7424 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7425 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7426 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7427 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7428 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7429 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7430 _dummy_first_bfd_reloc_code_real },
40fb9820 7431 OPERAND_TYPE_NONE },
cff8d58a
L		 7432 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7433 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7434 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7435 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7436 _dummy_first_bfd_reloc_code_real },
40fb9820 7437 OPERAND_TYPE_NONE },
cff8d58a
L		 7438 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7439 _dummy_first_bfd_reloc_code_real },
40fb9820 7440 OPERAND_TYPE_NONE },
cff8d58a
L		 7441 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7442 BFD_RELOC_X86_64_GOT32 },
40fb9820 7443 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7444 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7445 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7446 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7447 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7448 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7449 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7450 };
7451 char *cp;
7452 unsigned int j;
7453
d382c579 7454#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7455 if (!IS_ELF)
7456 return NULL;
d382c579 7457#endif
718ddfc0 7458
f3c180ae 7459 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7460 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7461 return NULL;
7462
47465058 7463 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7464 {
cff8d58a 7465 int len = gotrel[j].len;
28f81592 7466 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7467 {
4fa24527 7468 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7469 {
28f81592
AM		 7470 int first, second;
7471 char *tmpbuf, *past_reloc;
f3c180ae 7472
91d6fa6a 7473 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7474
3956db08
JB		 7475 if (types)
7476 {
7477 if (flag_code != CODE_64BIT)
40fb9820
L		 7478 {
7479 types->bitfield.imm32 = 1;
7480 types->bitfield.disp32 = 1;
7481 }
3956db08
JB		 7482 else
7483 *types = gotrel[j].types64;
7484 }
7485
8fd4256d 7486 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7487 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7488
28f81592 7489 /* The length of the first part of our input line. */
f3c180ae 7490 first = cp - input_line_pointer;
28f81592
AM		 7491
7492 /* The second part goes from after the reloc token until
67c11a9b 7493 (and including) an end_of_line char or comma. */
28f81592 7494 past_reloc = cp + 1 + len;
67c11a9b
AM		 7495 cp = past_reloc;
7496 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7497 ++cp;
7498 second = cp + 1 - past_reloc;
28f81592
AM		 7499
7500 /* Allocate and copy string. The trailing NUL shouldn't
7501 be necessary, but be safe. */
1e9cc1c2 7502 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7503 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7504 if (second != 0 && *past_reloc != ' ')
7505 /* Replace the relocation token with ' ', so that
7506 errors like foo@GOTOFF1 will be detected. */
7507 tmpbuf[first++] = ' ';
af89796a
L		 7508 else
7509 /* Increment length by 1 if the relocation token is
7510 removed. */
7511 len++;
7512 if (adjust)
7513 *adjust = len;
0787a12d
AM		 7514 memcpy (tmpbuf + first, past_reloc, second);
7515 tmpbuf[first + second] = '\0';
c3320543
L		 7516 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7517 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7518 return tmpbuf;
7519 }
7520
4fa24527
JB		 7521 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7522 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7523 return NULL;
7524 }
7525 }
7526
7527 /* Might be a symbol version string. Don't as_bad here. */
7528 return NULL;
7529}
4e4f7c87 7530#endif
f3c180ae 7531
a988325c
NC		 7532#ifdef TE_PE
7533#ifdef lex_got
7534#undef lex_got
7535#endif
7536/* Parse operands of the form
7537 <symbol>@SECREL32+<nnn>
7538
7539 If we find one, set up the correct relocation in RELOC and copy the
7540 input string, minus the `@SECREL32' into a malloc'd buffer for
7541 parsing by the calling routine. Return this buffer, and if ADJUST
7542 is non-null set it to the length of the string we removed from the
34bca508
L		 7543 input line. Otherwise return NULL.
7544
a988325c
NC		 7545 This function is copied from the ELF version above adjusted for PE targets. */
7546
7547static char *
7548lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7549 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7550 i386_operand_type *types,
7551 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7552{
7553 static const struct
7554 {
7555 const char *str;
7556 int len;
7557 const enum bfd_reloc_code_real rel[2];
7558 const i386_operand_type types64;
7559 }
7560 gotrel[] =
7561 {
7562 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7563 BFD_RELOC_32_SECREL },
7564 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7565 };
7566
7567 char *cp;
7568 unsigned j;
7569
7570 for (cp = input_line_pointer; *cp != '@'; cp++)
7571 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7572 return NULL;
7573
7574 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7575 {
7576 int len = gotrel[j].len;
7577
7578 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7579 {
7580 if (gotrel[j].rel[object_64bit] != 0)
7581 {
7582 int first, second;
7583 char *tmpbuf, *past_reloc;
7584
7585 *rel = gotrel[j].rel[object_64bit];
7586 if (adjust)
7587 *adjust = len;
7588
7589 if (types)
7590 {
7591 if (flag_code != CODE_64BIT)
7592 {
7593 types->bitfield.imm32 = 1;
7594 types->bitfield.disp32 = 1;
7595 }
7596 else
7597 *types = gotrel[j].types64;
7598 }
7599
7600 /* The length of the first part of our input line. */
7601 first = cp - input_line_pointer;
7602
7603 /* The second part goes from after the reloc token until
7604 (and including) an end_of_line char or comma. */
7605 past_reloc = cp + 1 + len;
7606 cp = past_reloc;
7607 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7608 ++cp;
7609 second = cp + 1 - past_reloc;
7610
7611 /* Allocate and copy string. The trailing NUL shouldn't
7612 be necessary, but be safe. */
7613 tmpbuf = (char *) xmalloc (first + second + 2);
7614 memcpy (tmpbuf, input_line_pointer, first);
7615 if (second != 0 && *past_reloc != ' ')
7616 /* Replace the relocation token with ' ', so that
7617 errors like foo@SECLREL321 will be detected. */
7618 tmpbuf[first++] = ' ';
7619 memcpy (tmpbuf + first, past_reloc, second);
7620 tmpbuf[first + second] = '\0';
7621 return tmpbuf;
7622 }
7623
7624 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7625 gotrel[j].str, 1 << (5 + object_64bit));
7626 return NULL;
7627 }
7628 }
7629
7630 /* Might be a symbol version string. Don't as_bad here. */
7631 return NULL;
7632}
7633
7634#endif /* TE_PE */
7635
f3c180ae 7636void
e3bb37b5 7637x86_cons (expressionS *exp, int size)
f3c180ae 7638{
ee86248c
JB		 7639 intel_syntax = -intel_syntax;
7640
3c7b9c2c 7641 exp->X_md = 0;
4fa24527 7642 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7643 {
7644 /* Handle @GOTOFF and the like in an expression. */
7645 char *save;
7646 char *gotfree_input_line;
4a57f2cf 7647 int adjust = 0;
f3c180ae
AM		 7648
7649 save = input_line_pointer;
c3320543 7650 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7651 if (gotfree_input_line)
7652 input_line_pointer = gotfree_input_line;
7653
7654 expression (exp);
7655
7656 if (gotfree_input_line)
7657 {
7658 /* expression () has merrily parsed up to the end of line,
7659 or a comma - in the wrong buffer. Transfer how far
7660 input_line_pointer has moved to the right buffer. */
7661 input_line_pointer = (save
7662 + (input_line_pointer - gotfree_input_line)
7663 + adjust);
7664 free (gotfree_input_line);
3992d3b7
AM		 7665 if (exp->X_op == O_constant
7666 || exp->X_op == O_absent
7667 || exp->X_op == O_illegal
0398aac5 7668 || exp->X_op == O_register
3992d3b7
AM		 7669 || exp->X_op == O_big)
7670 {
7671 char c = *input_line_pointer;
7672 *input_line_pointer = 0;
7673 as_bad (_("missing or invalid expression `%s'"), save);
7674 *input_line_pointer = c;
7675 }
f3c180ae
AM		 7676 }
7677 }
7678 else
7679 expression (exp);
ee86248c
JB		 7680
7681 intel_syntax = -intel_syntax;
7682
7683 if (intel_syntax)
7684 i386_intel_simplify (exp);
f3c180ae 7685}
f3c180ae 7686
9f32dd5b
L		 7687static void
7688signed_cons (int size)
6482c264 7689{
d182319b
JB		 7690 if (flag_code == CODE_64BIT)
7691 cons_sign = 1;
7692 cons (size);
7693 cons_sign = -1;
6482c264
NC		 7694}
7695
d182319b 7696#ifdef TE_PE
6482c264 7697static void
7016a5d5 7698pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7699{
7700 expressionS exp;
7701
7702 do
7703 {
7704 expression (&exp);
7705 if (exp.X_op == O_symbol)
7706 exp.X_op = O_secrel;
7707
7708 emit_expr (&exp, 4);
7709 }
7710 while (*input_line_pointer++ == ',');
7711
7712 input_line_pointer--;
7713 demand_empty_rest_of_line ();
7714}
6482c264
NC		 7715#endif
7716
43234a1e
L		 7717/* Handle Vector operations. */
7718
7719static char *
7720check_VecOperations (char *op_string, char *op_end)
7721{
7722 const reg_entry *mask;
7723 const char *saved;
7724 char *end_op;
7725
7726 while (*op_string
7727 && (op_end == NULL || op_string < op_end))
7728 {
7729 saved = op_string;
7730 if (*op_string == '{')
7731 {
7732 op_string++;
7733
7734 /* Check broadcasts. */
7735 if (strncmp (op_string, "1to", 3) == 0)
7736 {
7737 int bcst_type;
7738
7739 if (i.broadcast)
7740 goto duplicated_vec_op;
7741
7742 op_string += 3;
7743 if (*op_string == '8')
7744 bcst_type = BROADCAST_1TO8;
7745 else if (*op_string == '1'
7746 && *(op_string+1) == '6')
7747 {
7748 bcst_type = BROADCAST_1TO16;
7749 op_string++;
7750 }
7751 else
7752 {
7753 as_bad (_("Unsupported broadcast: `%s'"), saved);
7754 return NULL;
7755 }
7756 op_string++;
7757
7758 broadcast_op.type = bcst_type;
7759 broadcast_op.operand = this_operand;
7760 i.broadcast = &broadcast_op;
7761 }
7762 /* Check masking operation. */
7763 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7764 {
7765 /* k0 can't be used for write mask. */
7766 if (mask->reg_num == 0)
7767 {
7768 as_bad (_("`%s' can't be used for write mask"),
7769 op_string);
7770 return NULL;
7771 }
7772
7773 if (!i.mask)
7774 {
7775 mask_op.mask = mask;
7776 mask_op.zeroing = 0;
7777 mask_op.operand = this_operand;
7778 i.mask = &mask_op;
7779 }
7780 else
7781 {
7782 if (i.mask->mask)
7783 goto duplicated_vec_op;
7784
7785 i.mask->mask = mask;
7786
7787 /* Only "{z}" is allowed here. No need to check
7788 zeroing mask explicitly. */
7789 if (i.mask->operand != this_operand)
7790 {
7791 as_bad (_("invalid write mask `%s'"), saved);
7792 return NULL;
7793 }
7794 }
7795
7796 op_string = end_op;
7797 }
7798 /* Check zeroing-flag for masking operation. */
7799 else if (*op_string == 'z')
7800 {
7801 if (!i.mask)
7802 {
7803 mask_op.mask = NULL;
7804 mask_op.zeroing = 1;
7805 mask_op.operand = this_operand;
7806 i.mask = &mask_op;
7807 }
7808 else
7809 {
7810 if (i.mask->zeroing)
7811 {
7812 duplicated_vec_op:
7813 as_bad (_("duplicated `%s'"), saved);
7814 return NULL;
7815 }
7816
7817 i.mask->zeroing = 1;
7818
7819 /* Only "{%k}" is allowed here. No need to check mask
7820 register explicitly. */
7821 if (i.mask->operand != this_operand)
7822 {
7823 as_bad (_("invalid zeroing-masking `%s'"),
7824 saved);
7825 return NULL;
7826 }
7827 }
7828
7829 op_string++;
7830 }
7831 else
7832 goto unknown_vec_op;
7833
7834 if (*op_string != '}')
7835 {
7836 as_bad (_("missing `}' in `%s'"), saved);
7837 return NULL;
7838 }
7839 op_string++;
7840 continue;
7841 }
7842 unknown_vec_op:
7843 /* We don't know this one. */
7844 as_bad (_("unknown vector operation: `%s'"), saved);
7845 return NULL;
7846 }
7847
7848 return op_string;
7849}
7850
252b5132 7851static int
70e41ade 7852i386_immediate (char *imm_start)
252b5132
RH		 7853{
7854 char *save_input_line_pointer;
f3c180ae 7855 char *gotfree_input_line;
252b5132 7856 segT exp_seg = 0;
47926f60 7857 expressionS *exp;
40fb9820
L		 7858 i386_operand_type types;
7859
0dfbf9d7 7860 operand_type_set (&types, ~0);
252b5132
RH		 7861
7862 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7863 {
31b2323c
L		 7864 as_bad (_("at most %d immediate operands are allowed"),
7865 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7866 return 0;
7867 }
7868
7869 exp = &im_expressions[i.imm_operands++];
520dc8e8 7870 i.op[this_operand].imms = exp;
252b5132
RH		 7871
7872 if (is_space_char (*imm_start))
7873 ++imm_start;
7874
7875 save_input_line_pointer = input_line_pointer;
7876 input_line_pointer = imm_start;
7877
c3320543
L		 7878 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7879 (i.bnd_prefix != NULL
7880 || add_bnd_prefix));
f3c180ae
AM		 7881 if (gotfree_input_line)
7882 input_line_pointer = gotfree_input_line;
252b5132
RH		 7883
7884 exp_seg = expression (exp);
7885
83183c0c 7886 SKIP_WHITESPACE ();
43234a1e
L		 7887
7888 /* Handle vector operations. */
7889 if (*input_line_pointer == '{')
7890 {
7891 input_line_pointer = check_VecOperations (input_line_pointer,
7892 NULL);
7893 if (input_line_pointer == NULL)
7894 return 0;
7895 }
7896
252b5132 7897 if (*input_line_pointer)
f3c180ae 7898 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7899
7900 input_line_pointer = save_input_line_pointer;
f3c180ae 7901 if (gotfree_input_line)
ee86248c
JB		 7902 {
7903 free (gotfree_input_line);
7904
7905 if (exp->X_op == O_constant || exp->X_op == O_register)
7906 exp->X_op = O_illegal;
7907 }
7908
7909 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7910}
252b5132 7911
ee86248c
JB		 7912static int
7913i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7914 i386_operand_type types, const char *imm_start)
7915{
7916 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7917 {
313c53d1
L		 7918 if (imm_start)
7919 as_bad (_("missing or invalid immediate expression `%s'"),
7920 imm_start);
3992d3b7 7921 return 0;
252b5132 7922 }
3e73aa7c 7923 else if (exp->X_op == O_constant)
252b5132 7924 {
47926f60 7925 /* Size it properly later. */
40fb9820 7926 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7927 /* If not 64bit, sign extend val. */
7928 if (flag_code != CODE_64BIT
4eed87de
AM		 7929 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7930 exp->X_add_number
7931 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7932 }
4c63da97 7933#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7934 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7935 && exp_seg != absolute_section
47926f60 7936 && exp_seg != text_section
24eab124
AM		 7937 && exp_seg != data_section
7938 && exp_seg != bss_section
7939 && exp_seg != undefined_section
f86103b7 7940 && !bfd_is_com_section (exp_seg))
252b5132 7941 {
d0b47220 7942 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7943 return 0;
7944 }
7945#endif
bb8f5920
L		 7946 else if (!intel_syntax && exp->X_op == O_register)
7947 {
313c53d1
L		 7948 if (imm_start)
7949 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7950 return 0;
7951 }
252b5132
RH		 7952 else
7953 {
7954 /* This is an address. The size of the address will be
24eab124 7955 determined later, depending on destination register,
3e73aa7c 7956 suffix, or the default for the section. */
40fb9820
L		 7957 i.types[this_operand].bitfield.imm8 = 1;
7958 i.types[this_operand].bitfield.imm16 = 1;
7959 i.types[this_operand].bitfield.imm32 = 1;
7960 i.types[this_operand].bitfield.imm32s = 1;
7961 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7962 i.types[this_operand] = operand_type_and (i.types[this_operand],
7963 types);
252b5132
RH		 7964 }
7965
7966 return 1;
7967}
7968
551c1ca1 7969static char *
e3bb37b5 7970i386_scale (char *scale)
252b5132 7971{
551c1ca1
AM		 7972 offsetT val;
7973 char *save = input_line_pointer;
252b5132 7974
551c1ca1
AM		 7975 input_line_pointer = scale;
7976 val = get_absolute_expression ();
7977
7978 switch (val)
252b5132 7979 {
551c1ca1 7980 case 1:
252b5132
RH		 7981 i.log2_scale_factor = 0;
7982 break;
551c1ca1 7983 case 2:
252b5132
RH		 7984 i.log2_scale_factor = 1;
7985 break;
551c1ca1 7986 case 4:
252b5132
RH		 7987 i.log2_scale_factor = 2;
7988 break;
551c1ca1 7989 case 8:
252b5132
RH		 7990 i.log2_scale_factor = 3;
7991 break;
7992 default:
a724f0f4
JB		 7993 {
7994 char sep = *input_line_pointer;
7995
7996 *input_line_pointer = '\0';
7997 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7998 scale);
7999 *input_line_pointer = sep;
8000 input_line_pointer = save;
8001 return NULL;
8002 }
252b5132 8003 }
29b0f896 8004 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8005 {
8006 as_warn (_("scale factor of %d without an index register"),
24eab124 8007 1 << i.log2_scale_factor);
252b5132 8008 i.log2_scale_factor = 0;
252b5132 8009 }
551c1ca1
AM		 8010 scale = input_line_pointer;
8011 input_line_pointer = save;
8012 return scale;
252b5132
RH		 8013}
8014
252b5132 8015static int
e3bb37b5 8016i386_displacement (char *disp_start, char *disp_end)
252b5132 8017{
29b0f896 8018 expressionS *exp;
252b5132
RH		 8019 segT exp_seg = 0;
8020 char *save_input_line_pointer;
f3c180ae 8021 char *gotfree_input_line;
40fb9820
L		 8022 int override;
8023 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8024 int ret;
252b5132 8025
31b2323c
L		 8026 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8027 {
8028 as_bad (_("at most %d displacement operands are allowed"),
8029 MAX_MEMORY_OPERANDS);
8030 return 0;
8031 }
8032
0dfbf9d7 8033 operand_type_set (&bigdisp, 0);
40fb9820
L		 8034 if ((i.types[this_operand].bitfield.jumpabsolute)
8035 || (!current_templates->start->opcode_modifier.jump
8036 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8037 {
40fb9820 8038 bigdisp.bitfield.disp32 = 1;
e05278af 8039 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8040 if (flag_code == CODE_64BIT)
8041 {
8042 if (!override)
8043 {
8044 bigdisp.bitfield.disp32s = 1;
8045 bigdisp.bitfield.disp64 = 1;
8046 }
8047 }
8048 else if ((flag_code == CODE_16BIT) ^ override)
8049 {
8050 bigdisp.bitfield.disp32 = 0;
8051 bigdisp.bitfield.disp16 = 1;
8052 }
e05278af
JB		 8053 }
8054 else
8055 {
8056 /* For PC-relative branches, the width of the displacement
8057 is dependent upon data size, not address size. */
e05278af 8058 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8059 if (flag_code == CODE_64BIT)
8060 {
8061 if (override || i.suffix == WORD_MNEM_SUFFIX)
8062 bigdisp.bitfield.disp16 = 1;
8063 else
8064 {
8065 bigdisp.bitfield.disp32 = 1;
8066 bigdisp.bitfield.disp32s = 1;
8067 }
8068 }
8069 else
e05278af
JB		 8070 {
8071 if (!override)
8072 override = (i.suffix == (flag_code != CODE_16BIT
8073 ? WORD_MNEM_SUFFIX
8074 : LONG_MNEM_SUFFIX));
40fb9820
L		 8075 bigdisp.bitfield.disp32 = 1;
8076 if ((flag_code == CODE_16BIT) ^ override)
8077 {
8078 bigdisp.bitfield.disp32 = 0;
8079 bigdisp.bitfield.disp16 = 1;
8080 }
e05278af 8081 }
e05278af 8082 }
c6fb90c8
L		 8083 i.types[this_operand] = operand_type_or (i.types[this_operand],
8084 bigdisp);
252b5132
RH		 8085
8086 exp = &disp_expressions[i.disp_operands];
520dc8e8 8087 i.op[this_operand].disps = exp;
252b5132
RH		 8088 i.disp_operands++;
8089 save_input_line_pointer = input_line_pointer;
8090 input_line_pointer = disp_start;
8091 END_STRING_AND_SAVE (disp_end);
8092
8093#ifndef GCC_ASM_O_HACK
8094#define GCC_ASM_O_HACK 0
8095#endif
8096#if GCC_ASM_O_HACK
8097 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8098 if (i.types[this_operand].bitfield.baseIndex
24eab124 8099 && displacement_string_end[-1] == '+')
252b5132
RH		 8100 {
8101 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8102 constraint within gcc asm statements.
8103 For instance:
8104
8105 #define _set_tssldt_desc(n,addr,limit,type) \
8106 __asm__ __volatile__ ( \
8107 "movw %w2,%0\n\t" \
8108 "movw %w1,2+%0\n\t" \
8109 "rorl $16,%1\n\t" \
8110 "movb %b1,4+%0\n\t" \
8111 "movb %4,5+%0\n\t" \
8112 "movb $0,6+%0\n\t" \
8113 "movb %h1,7+%0\n\t" \
8114 "rorl $16,%1" \
8115 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8116
8117 This works great except that the output assembler ends
8118 up looking a bit weird if it turns out that there is
8119 no offset. You end up producing code that looks like:
8120
8121 #APP
8122 movw $235,(%eax)
8123 movw %dx,2+(%eax)
8124 rorl $16,%edx
8125 movb %dl,4+(%eax)
8126 movb $137,5+(%eax)
8127 movb $0,6+(%eax)
8128 movb %dh,7+(%eax)
8129 rorl $16,%edx
8130 #NO_APP
8131
47926f60 8132 So here we provide the missing zero. */
24eab124
AM		 8133
8134 *displacement_string_end = '0';
252b5132
RH		 8135 }
8136#endif
c3320543
L		 8137 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8138 (i.bnd_prefix != NULL
8139 || add_bnd_prefix));
f3c180ae
AM		 8140 if (gotfree_input_line)
8141 input_line_pointer = gotfree_input_line;
252b5132 8142
24eab124 8143 exp_seg = expression (exp);
252b5132 8144
636c26b0
AM		 8145 SKIP_WHITESPACE ();
8146 if (*input_line_pointer)
8147 as_bad (_("junk `%s' after expression"), input_line_pointer);
8148#if GCC_ASM_O_HACK
8149 RESTORE_END_STRING (disp_end + 1);
8150#endif
636c26b0 8151 input_line_pointer = save_input_line_pointer;
636c26b0 8152 if (gotfree_input_line)
ee86248c
JB		 8153 {
8154 free (gotfree_input_line);
8155
8156 if (exp->X_op == O_constant || exp->X_op == O_register)
8157 exp->X_op = O_illegal;
8158 }
8159
8160 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8161
8162 RESTORE_END_STRING (disp_end);
8163
8164 return ret;
8165}
8166
8167static int
8168i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8169 i386_operand_type types, const char *disp_start)
8170{
8171 i386_operand_type bigdisp;
8172 int ret = 1;
636c26b0 8173
24eab124
AM		 8174 /* We do this to make sure that the section symbol is in
8175 the symbol table. We will ultimately change the relocation
47926f60 8176 to be relative to the beginning of the section. */
1ae12ab7 8177 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8178 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8179 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8180 {
636c26b0 8181 if (exp->X_op != O_symbol)
3992d3b7 8182 goto inv_disp;
636c26b0 8183
e5cb08ac 8184 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8185 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8186 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8187 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8188 exp->X_op = O_subtract;
8189 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8190 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8191 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8192 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8193 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8194 else
29b0f896 8195 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8196 }
252b5132 8197
3992d3b7
AM		 8198 else if (exp->X_op == O_absent
8199 || exp->X_op == O_illegal
ee86248c 8200 || exp->X_op == O_big)
2daf4fd8 8201 {
3992d3b7
AM		 8202 inv_disp:
8203 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8204 disp_start);
3992d3b7 8205 ret = 0;
2daf4fd8
AM		 8206 }
8207
0e1147d9
L		 8208 else if (flag_code == CODE_64BIT
8209 && !i.prefix[ADDR_PREFIX]
8210 && exp->X_op == O_constant)
8211 {
8212 /* Since displacement is signed extended to 64bit, don't allow
8213 disp32 and turn off disp32s if they are out of range. */
8214 i.types[this_operand].bitfield.disp32 = 0;
8215 if (!fits_in_signed_long (exp->X_add_number))
8216 {
8217 i.types[this_operand].bitfield.disp32s = 0;
8218 if (i.types[this_operand].bitfield.baseindex)
8219 {
8220 as_bad (_("0x%lx out range of signed 32bit displacement"),
8221 (long) exp->X_add_number);
8222 ret = 0;
8223 }
8224 }
8225 }
8226
4c63da97 8227#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8228 else if (exp->X_op != O_constant
8229 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8230 && exp_seg != absolute_section
8231 && exp_seg != text_section
8232 && exp_seg != data_section
8233 && exp_seg != bss_section
8234 && exp_seg != undefined_section
8235 && !bfd_is_com_section (exp_seg))
24eab124 8236 {
d0b47220 8237 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8238 ret = 0;
24eab124 8239 }
252b5132 8240#endif
3956db08 8241
40fb9820
L		 8242 /* Check if this is a displacement only operand. */
8243 bigdisp = i.types[this_operand];
8244 bigdisp.bitfield.disp8 = 0;
8245 bigdisp.bitfield.disp16 = 0;
8246 bigdisp.bitfield.disp32 = 0;
8247 bigdisp.bitfield.disp32s = 0;
8248 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8249 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8250 i.types[this_operand] = operand_type_and (i.types[this_operand],
8251 types);
3956db08 8252
3992d3b7 8253 return ret;
252b5132
RH		 8254}
8255
eecb386c 8256/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8257 Return 1 on success, 0 on a failure. */
8258
252b5132 8259static int
e3bb37b5 8260i386_index_check (const char *operand_string)
252b5132 8261{
fc0763e6 8262 const char *kind = "base/index";
be05d201
L		 8263 enum flag_code addr_mode;
8264
8265 if (i.prefix[ADDR_PREFIX])
8266 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8267 else
8268 {
8269 addr_mode = flag_code;
8270
24eab124 8271#if INFER_ADDR_PREFIX
be05d201
L		 8272 if (i.mem_operands == 0)
8273 {
8274 /* Infer address prefix from the first memory operand. */
8275 const reg_entry *addr_reg = i.base_reg;
8276
8277 if (addr_reg == NULL)
8278 addr_reg = i.index_reg;
eecb386c 8279
be05d201
L		 8280 if (addr_reg)
8281 {
8282 if (addr_reg->reg_num == RegEip
8283 || addr_reg->reg_num == RegEiz
8284 || addr_reg->reg_type.bitfield.reg32)
8285 addr_mode = CODE_32BIT;
8286 else if (flag_code != CODE_64BIT
8287 && addr_reg->reg_type.bitfield.reg16)
8288 addr_mode = CODE_16BIT;
8289
8290 if (addr_mode != flag_code)
8291 {
8292 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8293 i.prefixes += 1;
8294 /* Change the size of any displacement too. At most one
8295 of Disp16 or Disp32 is set.
8296 FIXME. There doesn't seem to be any real need for
8297 separate Disp16 and Disp32 flags. The same goes for
8298 Imm16 and Imm32. Removing them would probably clean
8299 up the code quite a lot. */
8300 if (flag_code != CODE_64BIT
8301 && (i.types[this_operand].bitfield.disp16
8302 || i.types[this_operand].bitfield.disp32))
8303 i.types[this_operand]
8304 = operand_type_xor (i.types[this_operand], disp16_32);
8305 }
8306 }
8307 }
24eab124 8308#endif
be05d201
L		 8309 }
8310
fc0763e6
JB		 8311 if (current_templates->start->opcode_modifier.isstring
8312 && !current_templates->start->opcode_modifier.immext
8313 && (current_templates->end[-1].opcode_modifier.isstring
8314 || i.mem_operands))
8315 {
8316 /* Memory operands of string insns are special in that they only allow
8317 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8318 const reg_entry *expected_reg;
8319 static const char *di_si[][2] =
8320 {
8321 { "esi", "edi" },
8322 { "si", "di" },
8323 { "rsi", "rdi" }
8324 };
8325 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8326
8327 kind = "string address";
8328
8329 if (current_templates->start->opcode_modifier.w)
8330 {
8331 i386_operand_type type = current_templates->end[-1].operand_types[0];
8332
8333 if (!type.bitfield.baseindex
8334 || ((!i.mem_operands != !intel_syntax)
8335 && current_templates->end[-1].operand_types[1]
8336 .bitfield.baseindex))
8337 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8338 expected_reg = hash_find (reg_hash,
8339 di_si[addr_mode][type.bitfield.esseg]);
8340
fc0763e6
JB		 8341 }
8342 else
be05d201 8343 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8344
be05d201
L		 8345 if (i.base_reg != expected_reg
8346 || i.index_reg
fc0763e6 8347 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8348 {
be05d201
L		 8349 /* The second memory operand must have the same size as
8350 the first one. */
8351 if (i.mem_operands
8352 && i.base_reg
8353 && !((addr_mode == CODE_64BIT
8354 && i.base_reg->reg_type.bitfield.reg64)
8355 || (addr_mode == CODE_32BIT
8356 ? i.base_reg->reg_type.bitfield.reg32
8357 : i.base_reg->reg_type.bitfield.reg16)))
8358 goto bad_address;
8359
fc0763e6
JB		 8360 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8361 operand_string,
8362 intel_syntax ? '[' : '(',
8363 register_prefix,
be05d201 8364 expected_reg->reg_name,
fc0763e6 8365 intel_syntax ? ']' : ')');
be05d201 8366 return 1;
fc0763e6 8367 }
be05d201
L		 8368 else
8369 return 1;
8370
8371bad_address:
8372 as_bad (_("`%s' is not a valid %s expression"),
8373 operand_string, kind);
8374 return 0;
3e73aa7c
JH		 8375 }
8376 else
8377 {
be05d201
L		 8378 if (addr_mode != CODE_16BIT)
8379 {
8380 /* 32-bit/64-bit checks. */
8381 if ((i.base_reg
8382 && (addr_mode == CODE_64BIT
8383 ? !i.base_reg->reg_type.bitfield.reg64
8384 : !i.base_reg->reg_type.bitfield.reg32)
8385 && (i.index_reg
8386 || (i.base_reg->reg_num
8387 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8388 || (i.index_reg
8389 && !i.index_reg->reg_type.bitfield.regxmm
8390 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8391 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8392 && ((addr_mode == CODE_64BIT
8393 ? !(i.index_reg->reg_type.bitfield.reg64
8394 || i.index_reg->reg_num == RegRiz)
8395 : !(i.index_reg->reg_type.bitfield.reg32
8396 || i.index_reg->reg_num == RegEiz))
8397 || !i.index_reg->reg_type.bitfield.baseindex)))
8398 goto bad_address;
8399 }
8400 else
3e73aa7c 8401 {
be05d201 8402 /* 16-bit checks. */
3e73aa7c 8403 if ((i.base_reg
40fb9820
L		 8404 && (!i.base_reg->reg_type.bitfield.reg16
8405 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8406 || (i.index_reg
40fb9820
L		 8407 && (!i.index_reg->reg_type.bitfield.reg16
8408 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8409 || !(i.base_reg
8410 && i.base_reg->reg_num < 6
8411 && i.index_reg->reg_num >= 6
8412 && i.log2_scale_factor == 0))))
be05d201 8413 goto bad_address;
3e73aa7c
JH		 8414 }
8415 }
be05d201 8416 return 1;
24eab124 8417}
252b5132 8418
43234a1e
L		 8419/* Handle vector immediates. */
8420
8421static int
8422RC_SAE_immediate (const char *imm_start)
8423{
8424 unsigned int match_found, j;
8425 const char *pstr = imm_start;
8426 expressionS *exp;
8427
8428 if (*pstr != '{')
8429 return 0;
8430
8431 pstr++;
8432 match_found = 0;
8433 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8434 {
8435 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8436 {
8437 if (!i.rounding)
8438 {
8439 rc_op.type = RC_NamesTable[j].type;
8440 rc_op.operand = this_operand;
8441 i.rounding = &rc_op;
8442 }
8443 else
8444 {
8445 as_bad (_("duplicated `%s'"), imm_start);
8446 return 0;
8447 }
8448 pstr += RC_NamesTable[j].len;
8449 match_found = 1;
8450 break;
8451 }
8452 }
8453 if (!match_found)
8454 return 0;
8455
8456 if (*pstr++ != '}')
8457 {
8458 as_bad (_("Missing '}': '%s'"), imm_start);
8459 return 0;
8460 }
8461 /* RC/SAE immediate string should contain nothing more. */;
8462 if (*pstr != 0)
8463 {
8464 as_bad (_("Junk after '}': '%s'"), imm_start);
8465 return 0;
8466 }
8467
8468 exp = &im_expressions[i.imm_operands++];
8469 i.op[this_operand].imms = exp;
8470
8471 exp->X_op = O_constant;
8472 exp->X_add_number = 0;
8473 exp->X_add_symbol = (symbolS *) 0;
8474 exp->X_op_symbol = (symbolS *) 0;
8475
8476 i.types[this_operand].bitfield.imm8 = 1;
8477 return 1;
8478}
8479
fc0763e6 8480/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8481 on error. */
252b5132 8482
252b5132 8483static int
a7619375 8484i386_att_operand (char *operand_string)
252b5132 8485{
af6bdddf
AM		 8486 const reg_entry *r;
8487 char *end_op;
24eab124 8488 char *op_string = operand_string;
252b5132 8489
24eab124 8490 if (is_space_char (*op_string))
252b5132
RH		 8491 ++op_string;
8492
24eab124 8493 /* We check for an absolute prefix (differentiating,
47926f60 8494 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8495 if (*op_string == ABSOLUTE_PREFIX)
8496 {
8497 ++op_string;
8498 if (is_space_char (*op_string))
8499 ++op_string;
40fb9820 8500 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8501 }
252b5132 8502
47926f60 8503 /* Check if operand is a register. */
4d1bb795 8504 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8505 {
40fb9820
L		 8506 i386_operand_type temp;
8507
24eab124
AM		 8508 /* Check for a segment override by searching for ':' after a
8509 segment register. */
8510 op_string = end_op;
8511 if (is_space_char (*op_string))
8512 ++op_string;
40fb9820
L		 8513 if (*op_string == ':'
8514 && (r->reg_type.bitfield.sreg2
8515 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8516 {
8517 switch (r->reg_num)
8518 {
8519 case 0:
8520 i.seg[i.mem_operands] = &es;
8521 break;
8522 case 1:
8523 i.seg[i.mem_operands] = &cs;
8524 break;
8525 case 2:
8526 i.seg[i.mem_operands] = &ss;
8527 break;
8528 case 3:
8529 i.seg[i.mem_operands] = &ds;
8530 break;
8531 case 4:
8532 i.seg[i.mem_operands] = &fs;
8533 break;
8534 case 5:
8535 i.seg[i.mem_operands] = &gs;
8536 break;
8537 }
252b5132 8538
24eab124 8539 /* Skip the ':' and whitespace. */
252b5132
RH		 8540 ++op_string;
8541 if (is_space_char (*op_string))
24eab124 8542 ++op_string;
252b5132 8543
24eab124
AM		 8544 if (!is_digit_char (*op_string)
8545 && !is_identifier_char (*op_string)
8546 && *op_string != '('
8547 && *op_string != ABSOLUTE_PREFIX)
8548 {
8549 as_bad (_("bad memory operand `%s'"), op_string);
8550 return 0;
8551 }
47926f60 8552 /* Handle case of %es:*foo. */
24eab124
AM		 8553 if (*op_string == ABSOLUTE_PREFIX)
8554 {
8555 ++op_string;
8556 if (is_space_char (*op_string))
8557 ++op_string;
40fb9820 8558 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8559 }
8560 goto do_memory_reference;
8561 }
43234a1e
L		 8562
8563 /* Handle vector operations. */
8564 if (*op_string == '{')
8565 {
8566 op_string = check_VecOperations (op_string, NULL);
8567 if (op_string == NULL)
8568 return 0;
8569 }
8570
24eab124
AM		 8571 if (*op_string)
8572 {
d0b47220 8573 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8574 return 0;
8575 }
40fb9820
L		 8576 temp = r->reg_type;
8577 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8578 i.types[this_operand] = operand_type_or (i.types[this_operand],
8579 temp);
7d5e4556 8580 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8581 i.op[this_operand].regs = r;
24eab124
AM		 8582 i.reg_operands++;
8583 }
af6bdddf
AM		 8584 else if (*op_string == REGISTER_PREFIX)
8585 {
8586 as_bad (_("bad register name `%s'"), op_string);
8587 return 0;
8588 }
24eab124 8589 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8590 {
24eab124 8591 ++op_string;
40fb9820 8592 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8593 {
d0b47220 8594 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8595 return 0;
8596 }
8597 if (!i386_immediate (op_string))
8598 return 0;
8599 }
43234a1e
L		 8600 else if (RC_SAE_immediate (operand_string))
8601 {
8602 /* If it is a RC or SAE immediate, do nothing. */
8603 ;
8604 }
24eab124
AM		 8605 else if (is_digit_char (*op_string)
8606 || is_identifier_char (*op_string)
e5cb08ac 8607 || *op_string == '(')
24eab124 8608 {
47926f60 8609 /* This is a memory reference of some sort. */
af6bdddf 8610 char *base_string;
252b5132 8611
47926f60 8612 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8613 char *displacement_string_start;
8614 char *displacement_string_end;
43234a1e 8615 char *vop_start;
252b5132 8616
24eab124 8617 do_memory_reference:
24eab124 8618 if ((i.mem_operands == 1
40fb9820 8619 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8620 || i.mem_operands == 2)
8621 {
8622 as_bad (_("too many memory references for `%s'"),
8623 current_templates->start->name);
8624 return 0;
8625 }
252b5132 8626
24eab124
AM		 8627 /* Check for base index form. We detect the base index form by
8628 looking for an ')' at the end of the operand, searching
8629 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8630 after the '('. */
af6bdddf 8631 base_string = op_string + strlen (op_string);
c3332e24 8632
43234a1e
L		 8633 /* Handle vector operations. */
8634 vop_start = strchr (op_string, '{');
8635 if (vop_start && vop_start < base_string)
8636 {
8637 if (check_VecOperations (vop_start, base_string) == NULL)
8638 return 0;
8639 base_string = vop_start;
8640 }
8641
af6bdddf
AM		 8642 --base_string;
8643 if (is_space_char (*base_string))
8644 --base_string;
252b5132 8645
47926f60 8646 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8647 displacement_string_start = op_string;
8648 displacement_string_end = base_string + 1;
252b5132 8649
24eab124
AM		 8650 if (*base_string == ')')
8651 {
af6bdddf 8652 char *temp_string;
24eab124
AM		 8653 unsigned int parens_balanced = 1;
8654 /* We've already checked that the number of left & right ()'s are
47926f60 8655 equal, so this loop will not be infinite. */
24eab124
AM		 8656 do
8657 {
8658 base_string--;
8659 if (*base_string == ')')
8660 parens_balanced++;
8661 if (*base_string == '(')
8662 parens_balanced--;
8663 }
8664 while (parens_balanced);
c3332e24 8665
af6bdddf 8666 temp_string = base_string;
c3332e24 8667
24eab124 8668 /* Skip past '(' and whitespace. */
252b5132
RH		 8669 ++base_string;
8670 if (is_space_char (*base_string))
24eab124 8671 ++base_string;
252b5132 8672
af6bdddf 8673 if (*base_string == ','
4eed87de
AM		 8674 || ((i.base_reg = parse_register (base_string, &end_op))
8675 != NULL))
252b5132 8676 {
af6bdddf 8677 displacement_string_end = temp_string;
252b5132 8678
40fb9820 8679 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8680
af6bdddf 8681 if (i.base_reg)
24eab124 8682 {
24eab124
AM		 8683 base_string = end_op;
8684 if (is_space_char (*base_string))
8685 ++base_string;
af6bdddf
AM		 8686 }
8687
8688 /* There may be an index reg or scale factor here. */
8689 if (*base_string == ',')
8690 {
8691 ++base_string;
8692 if (is_space_char (*base_string))
8693 ++base_string;
8694
4eed87de
AM		 8695 if ((i.index_reg = parse_register (base_string, &end_op))
8696 != NULL)
24eab124 8697 {
af6bdddf 8698 base_string = end_op;
24eab124
AM		 8699 if (is_space_char (*base_string))
8700 ++base_string;
af6bdddf
AM		 8701 if (*base_string == ',')
8702 {
8703 ++base_string;
8704 if (is_space_char (*base_string))
8705 ++base_string;
8706 }
e5cb08ac 8707 else if (*base_string != ')')
af6bdddf 8708 {
4eed87de
AM		 8709 as_bad (_("expecting `,' or `)' "
8710 "after index register in `%s'"),
af6bdddf
AM		 8711 operand_string);
8712 return 0;
8713 }
24eab124 8714 }
af6bdddf 8715 else if (*base_string == REGISTER_PREFIX)
24eab124 8716 {
f76bf5e0
L		 8717 end_op = strchr (base_string, ',');
8718 if (end_op)
8719 *end_op = '\0';
af6bdddf 8720 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8721 return 0;
8722 }
252b5132 8723
47926f60 8724 /* Check for scale factor. */
551c1ca1 8725 if (*base_string != ')')
af6bdddf 8726 {
551c1ca1
AM		 8727 char *end_scale = i386_scale (base_string);
8728
8729 if (!end_scale)
af6bdddf 8730 return 0;
24eab124 8731
551c1ca1 8732 base_string = end_scale;
af6bdddf
AM		 8733 if (is_space_char (*base_string))
8734 ++base_string;
8735 if (*base_string != ')')
8736 {
4eed87de
AM		 8737 as_bad (_("expecting `)' "
8738 "after scale factor in `%s'"),
af6bdddf
AM		 8739 operand_string);
8740 return 0;
8741 }
8742 }
8743 else if (!i.index_reg)
24eab124 8744 {
4eed87de
AM		 8745 as_bad (_("expecting index register or scale factor "
8746 "after `,'; got '%c'"),
af6bdddf 8747 *base_string);
24eab124
AM		 8748 return 0;
8749 }
8750 }
af6bdddf 8751 else if (*base_string != ')')
24eab124 8752 {
4eed87de
AM		 8753 as_bad (_("expecting `,' or `)' "
8754 "after base register in `%s'"),
af6bdddf 8755 operand_string);
24eab124
AM		 8756 return 0;
8757 }
c3332e24 8758 }
af6bdddf 8759 else if (*base_string == REGISTER_PREFIX)
c3332e24 8760 {
f76bf5e0
L		 8761 end_op = strchr (base_string, ',');
8762 if (end_op)
8763 *end_op = '\0';
af6bdddf 8764 as_bad (_("bad register name `%s'"), base_string);
24eab124 8765 return 0;
c3332e24 8766 }
24eab124
AM		 8767 }
8768
8769 /* If there's an expression beginning the operand, parse it,
8770 assuming displacement_string_start and
8771 displacement_string_end are meaningful. */
8772 if (displacement_string_start != displacement_string_end)
8773 {
8774 if (!i386_displacement (displacement_string_start,
8775 displacement_string_end))
8776 return 0;
8777 }
8778
8779 /* Special case for (%dx) while doing input/output op. */
8780 if (i.base_reg
0dfbf9d7
L		 8781 && operand_type_equal (&i.base_reg->reg_type,
8782 &reg16_inoutportreg)
24eab124
AM		 8783 && i.index_reg == 0
8784 && i.log2_scale_factor == 0
8785 && i.seg[i.mem_operands] == 0
40fb9820 8786 && !operand_type_check (i.types[this_operand], disp))
24eab124 8787 {
65da13b5 8788 i.types[this_operand] = inoutportreg;
24eab124
AM		 8789 return 1;
8790 }
8791
eecb386c
AM		 8792 if (i386_index_check (operand_string) == 0)
8793 return 0;
5c07affc 8794 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8795 i.mem_operands++;
8796 }
8797 else
ce8a8b2f
AM		 8798 {
8799 /* It's not a memory operand; argh! */
24eab124
AM		 8800 as_bad (_("invalid char %s beginning operand %d `%s'"),
8801 output_invalid (*op_string),
8802 this_operand + 1,
8803 op_string);
8804 return 0;
8805 }
47926f60 8806 return 1; /* Normal return. */
252b5132
RH		 8807}
8808\f
fa94de6b
RM		 8809/* Calculate the maximum variable size (i.e., excluding fr_fix)
8810 that an rs_machine_dependent frag may reach. */
8811
8812unsigned int
8813i386_frag_max_var (fragS *frag)
8814{
8815 /* The only relaxable frags are for jumps.
8816 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8817 gas_assert (frag->fr_type == rs_machine_dependent);
8818 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8819}
8820
ee7fcc42
AM		 8821/* md_estimate_size_before_relax()
8822
8823 Called just before relax() for rs_machine_dependent frags. The x86
8824 assembler uses these frags to handle variable size jump
8825 instructions.
8826
8827 Any symbol that is now undefined will not become defined.
8828 Return the correct fr_subtype in the frag.
8829 Return the initial "guess for variable size of frag" to caller.
8830 The guess is actually the growth beyond the fixed part. Whatever
8831 we do to grow the fixed or variable part contributes to our
8832 returned value. */
8833
252b5132 8834int
7016a5d5 8835md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8836{
252b5132 8837 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8838 check for un-relaxable symbols. On an ELF system, we can't relax
8839 an externally visible symbol, because it may be overridden by a
8840 shared library. */
8841 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8842#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8843 || (IS_ELF
31312f95 8844 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8845 || S_IS_WEAK (fragP->fr_symbol)
8846 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8847 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8848#endif
8849#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8850 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8851 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8852#endif
8853 )
252b5132 8854 {
b98ef147
AM		 8855 /* Symbol is undefined in this segment, or we need to keep a
8856 reloc so that weak symbols can be overridden. */
8857 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8858 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8859 unsigned char *opcode;
8860 int old_fr_fix;
f6af82bd 8861
ee7fcc42 8862 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8863 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8864 else if (size == 2)
f6af82bd
AM		 8865 reloc_type = BFD_RELOC_16_PCREL;
8866 else
8867 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8868
ee7fcc42
AM		 8869 old_fr_fix = fragP->fr_fix;
8870 opcode = (unsigned char *) fragP->fr_opcode;
8871
fddf5b5b 8872 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8873 {
fddf5b5b
AM		 8874 case UNCOND_JUMP:
8875 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8876 opcode[0] = 0xe9;
252b5132 8877 fragP->fr_fix += size;
062cd5e7
AS		 8878 fix_new (fragP, old_fr_fix, size,
8879 fragP->fr_symbol,
8880 fragP->fr_offset, 1,
8881 reloc_type);
252b5132
RH		 8882 break;
8883
fddf5b5b 8884 case COND_JUMP86:
412167cb
AM		 8885 if (size == 2
8886 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8887 {
8888 /* Negate the condition, and branch past an
8889 unconditional jump. */
8890 opcode[0] ^= 1;
8891 opcode[1] = 3;
8892 /* Insert an unconditional jump. */
8893 opcode[2] = 0xe9;
8894 /* We added two extra opcode bytes, and have a two byte
8895 offset. */
8896 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8897 fix_new (fragP, old_fr_fix + 2, 2,
8898 fragP->fr_symbol,
8899 fragP->fr_offset, 1,
8900 reloc_type);
fddf5b5b
AM		 8901 break;
8902 }
8903 /* Fall through. */
8904
8905 case COND_JUMP:
412167cb
AM		 8906 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8907 {
3e02c1cc
AM		 8908 fixS *fixP;
8909
412167cb 8910 fragP->fr_fix += 1;
3e02c1cc
AM		 8911 fixP = fix_new (fragP, old_fr_fix, 1,
8912 fragP->fr_symbol,
8913 fragP->fr_offset, 1,
8914 BFD_RELOC_8_PCREL);
8915 fixP->fx_signed = 1;
412167cb
AM		 8916 break;
8917 }
93c2a809 8918
24eab124 8919 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8920 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8921 opcode[1] = opcode[0] + 0x10;
f6af82bd 8922 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8923 /* We've added an opcode byte. */
8924 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8925 fix_new (fragP, old_fr_fix + 1, size,
8926 fragP->fr_symbol,
8927 fragP->fr_offset, 1,
8928 reloc_type);
252b5132 8929 break;
fddf5b5b
AM		 8930
8931 default:
8932 BAD_CASE (fragP->fr_subtype);
8933 break;
252b5132
RH		 8934 }
8935 frag_wane (fragP);
ee7fcc42 8936 return fragP->fr_fix - old_fr_fix;
252b5132 8937 }
93c2a809 8938
93c2a809
AM		 8939 /* Guess size depending on current relax state. Initially the relax
8940 state will correspond to a short jump and we return 1, because
8941 the variable part of the frag (the branch offset) is one byte
8942 long. However, we can relax a section more than once and in that
8943 case we must either set fr_subtype back to the unrelaxed state,
8944 or return the value for the appropriate branch. */
8945 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8946}
8947
47926f60
KH		 8948/* Called after relax() is finished.
8949
8950 In: Address of frag.
8951 fr_type == rs_machine_dependent.
8952 fr_subtype is what the address relaxed to.
8953
8954 Out: Any fixSs and constants are set up.
8955 Caller will turn frag into a ".space 0". */
8956
252b5132 8957void
7016a5d5
TG		 8958md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8959 fragS *fragP)
252b5132 8960{
29b0f896 8961 unsigned char *opcode;
252b5132 8962 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8963 offsetT target_address;
8964 offsetT opcode_address;
252b5132 8965 unsigned int extension = 0;
847f7ad4 8966 offsetT displacement_from_opcode_start;
252b5132
RH		 8967
8968 opcode = (unsigned char *) fragP->fr_opcode;
8969
47926f60 8970 /* Address we want to reach in file space. */
252b5132 8971 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8972
47926f60 8973 /* Address opcode resides at in file space. */
252b5132
RH		 8974 opcode_address = fragP->fr_address + fragP->fr_fix;
8975
47926f60 8976 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8977 displacement_from_opcode_start = target_address - opcode_address;
8978
fddf5b5b 8979 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8980 {
47926f60
KH		 8981 /* Don't have to change opcode. */
8982 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8983 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8984 }
8985 else
8986 {
8987 if (no_cond_jump_promotion
8988 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8989 as_warn_where (fragP->fr_file, fragP->fr_line,
8990 _("long jump required"));
252b5132 8991
fddf5b5b
AM		 8992 switch (fragP->fr_subtype)
8993 {
8994 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8995 extension = 4; /* 1 opcode + 4 displacement */
8996 opcode[0] = 0xe9;
8997 where_to_put_displacement = &opcode[1];
8998 break;
252b5132 8999
fddf5b5b
AM		 9000 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9001 extension = 2; /* 1 opcode + 2 displacement */
9002 opcode[0] = 0xe9;
9003 where_to_put_displacement = &opcode[1];
9004 break;
252b5132 9005
fddf5b5b
AM		 9006 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9007 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9008 extension = 5; /* 2 opcode + 4 displacement */
9009 opcode[1] = opcode[0] + 0x10;
9010 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9011 where_to_put_displacement = &opcode[2];
9012 break;
252b5132 9013
fddf5b5b
AM		 9014 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9015 extension = 3; /* 2 opcode + 2 displacement */
9016 opcode[1] = opcode[0] + 0x10;
9017 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9018 where_to_put_displacement = &opcode[2];
9019 break;
252b5132 9020
fddf5b5b
AM		 9021 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9022 extension = 4;
9023 opcode[0] ^= 1;
9024 opcode[1] = 3;
9025 opcode[2] = 0xe9;
9026 where_to_put_displacement = &opcode[3];
9027 break;
9028
9029 default:
9030 BAD_CASE (fragP->fr_subtype);
9031 break;
9032 }
252b5132 9033 }
fddf5b5b 9034
7b81dfbb
AJ		 9035 /* If size if less then four we are sure that the operand fits,
9036 but if it's 4, then it could be that the displacement is larger
9037 then -/+ 2GB. */
9038 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9039 && object_64bit
9040 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9041 + ((addressT) 1 << 31))
9042 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9043 {
9044 as_bad_where (fragP->fr_file, fragP->fr_line,
9045 _("jump target out of range"));
9046 /* Make us emit 0. */
9047 displacement_from_opcode_start = extension;
9048 }
47926f60 9049 /* Now put displacement after opcode. */
252b5132
RH		 9050 md_number_to_chars ((char *) where_to_put_displacement,
9051 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9052 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9053 fragP->fr_fix += extension;
9054}
9055\f
7016a5d5 9056/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9057 by our caller that we have all the info we need to fix it up.
9058
7016a5d5
TG		 9059 Parameter valP is the pointer to the value of the bits.
9060
252b5132
RH		 9061 On the 386, immediates, displacements, and data pointers are all in
9062 the same (little-endian) format, so we don't need to care about which
9063 we are handling. */
9064
94f592af 9065void
7016a5d5 9066md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9067{
94f592af 9068 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9069 valueT value = *valP;
252b5132 9070
f86103b7 9071#if !defined (TE_Mach)
93382f6d
AM		 9072 if (fixP->fx_pcrel)
9073 {
9074 switch (fixP->fx_r_type)
9075 {
5865bb77
ILT		 9076 default:
9077 break;
9078
d6ab8113
JB		 9079 case BFD_RELOC_64:
9080 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9081 break;
93382f6d 9082 case BFD_RELOC_32:
ae8887b5 9083 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9084 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9085 break;
9086 case BFD_RELOC_16:
9087 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9088 break;
9089 case BFD_RELOC_8:
9090 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9091 break;
9092 }
9093 }
252b5132 9094
a161fe53 9095 if (fixP->fx_addsy != NULL
31312f95 9096 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9097 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9098 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9099 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9100 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9101 && !use_rela_relocations)
252b5132 9102 {
31312f95
AM		 9103 /* This is a hack. There should be a better way to handle this.
9104 This covers for the fact that bfd_install_relocation will
9105 subtract the current location (for partial_inplace, PC relative
9106 relocations); see more below. */
252b5132 9107#ifndef OBJ_AOUT
718ddfc0 9108 if (IS_ELF
252b5132
RH		 9109#ifdef TE_PE
9110 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9111#endif
9112 )
9113 value += fixP->fx_where + fixP->fx_frag->fr_address;
9114#endif
9115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9116 if (IS_ELF)
252b5132 9117 {
6539b54b 9118 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9119
6539b54b 9120 if ((sym_seg == seg
2f66722d 9121 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9122 && sym_seg != absolute_section))
af65af87 9123 && !generic_force_reloc (fixP))
2f66722d
AM		 9124 {
9125 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9126 bfd_install_relocation subtracts them out again. I think
9127 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9128 it. FIXME. */
9129 value += fixP->fx_where + fixP->fx_frag->fr_address;
9130 }
252b5132
RH		 9131 }
9132#endif
9133#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9134 /* For some reason, the PE format does not store a
9135 section address offset for a PC relative symbol. */
9136 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9137 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9138 value += md_pcrel_from (fixP);
9139#endif
9140 }
fbeb56a4
DK		 9141#if defined (OBJ_COFF) && defined (TE_PE)
9142 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9143 {
9144 value -= S_GET_VALUE (fixP->fx_addsy);
9145 }
9146#endif
252b5132
RH		 9147
9148 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9149 and we must not disappoint it. */
252b5132 9150#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9151 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9152 switch (fixP->fx_r_type)
9153 {
9154 case BFD_RELOC_386_PLT32:
3e73aa7c 9155 case BFD_RELOC_X86_64_PLT32:
c3320543 9156 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9157 /* Make the jump instruction point to the address of the operand. At
9158 runtime we merely add the offset to the actual PLT entry. */
9159 value = -4;
9160 break;
31312f95 9161
13ae64f3
JJ		 9162 case BFD_RELOC_386_TLS_GD:
9163 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9164 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9165 case BFD_RELOC_386_TLS_IE:
9166 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9167 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9168 case BFD_RELOC_X86_64_TLSGD:
9169 case BFD_RELOC_X86_64_TLSLD:
9170 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9171 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9172 value = 0; /* Fully resolved at runtime. No addend. */
9173 /* Fallthrough */
9174 case BFD_RELOC_386_TLS_LE:
9175 case BFD_RELOC_386_TLS_LDO_32:
9176 case BFD_RELOC_386_TLS_LE_32:
9177 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9178 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9179 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9180 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9181 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9182 break;
9183
67a4f2b7
AO		 9184 case BFD_RELOC_386_TLS_DESC_CALL:
9185 case BFD_RELOC_X86_64_TLSDESC_CALL:
9186 value = 0; /* Fully resolved at runtime. No addend. */
9187 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9188 fixP->fx_done = 0;
9189 return;
9190
00f7efb6
JJ		 9191 case BFD_RELOC_386_GOT32:
9192 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9193 value = 0; /* Fully resolved at runtime. No addend. */
9194 break;
47926f60
KH		 9195
9196 case BFD_RELOC_VTABLE_INHERIT:
9197 case BFD_RELOC_VTABLE_ENTRY:
9198 fixP->fx_done = 0;
94f592af 9199 return;
47926f60
KH		 9200
9201 default:
9202 break;
9203 }
9204#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9205 *valP = value;
f86103b7 9206#endif /* !defined (TE_Mach) */
3e73aa7c 9207
3e73aa7c 9208 /* Are we finished with this relocation now? */
c6682705 9209 if (fixP->fx_addsy == NULL)
3e73aa7c 9210 fixP->fx_done = 1;
fbeb56a4
DK		 9211#if defined (OBJ_COFF) && defined (TE_PE)
9212 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9213 {
9214 fixP->fx_done = 0;
9215 /* Remember value for tc_gen_reloc. */
9216 fixP->fx_addnumber = value;
9217 /* Clear out the frag for now. */
9218 value = 0;
9219 }
9220#endif
3e73aa7c
JH		 9221 else if (use_rela_relocations)
9222 {
9223 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9224 /* Remember value for tc_gen_reloc. */
9225 fixP->fx_addnumber = value;
3e73aa7c
JH		 9226 value = 0;
9227 }
f86103b7 9228
94f592af 9229 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9230}
252b5132 9231\f
252b5132 9232char *
499ac353 9233md_atof (int type, char *litP, int *sizeP)
252b5132 9234{
499ac353
NC		 9235 /* This outputs the LITTLENUMs in REVERSE order;
9236 in accord with the bigendian 386. */
9237 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9238}
9239\f
2d545b82 9240static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9241
252b5132 9242static char *
e3bb37b5 9243output_invalid (int c)
252b5132 9244{
3882b010 9245 if (ISPRINT (c))
f9f21a03
L		 9246 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9247 "'%c'", c);
252b5132 9248 else
f9f21a03 9249 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9250 "(0x%x)", (unsigned char) c);
252b5132
RH		 9251 return output_invalid_buf;
9252}
9253
af6bdddf 9254/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9255
9256static const reg_entry *
4d1bb795 9257parse_real_register (char *reg_string, char **end_op)
252b5132 9258{
af6bdddf
AM		 9259 char *s = reg_string;
9260 char *p;
252b5132
RH		 9261 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9262 const reg_entry *r;
9263
9264 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9265 if (*s == REGISTER_PREFIX)
9266 ++s;
9267
9268 if (is_space_char (*s))
9269 ++s;
9270
9271 p = reg_name_given;
af6bdddf 9272 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9273 {
9274 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9275 return (const reg_entry *) NULL;
9276 s++;
252b5132
RH		 9277 }
9278
6588847e
DN		 9279 /* For naked regs, make sure that we are not dealing with an identifier.
9280 This prevents confusing an identifier like `eax_var' with register
9281 `eax'. */
9282 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9283 return (const reg_entry *) NULL;
9284
af6bdddf 9285 *end_op = s;
252b5132
RH		 9286
9287 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9288
5f47d35b 9289 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9290 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9291 {
5f47d35b
AM		 9292 if (is_space_char (*s))
9293 ++s;
9294 if (*s == '(')
9295 {
af6bdddf 9296 ++s;
5f47d35b
AM		 9297 if (is_space_char (*s))
9298 ++s;
9299 if (*s >= '0' && *s <= '7')
9300 {
db557034 9301 int fpr = *s - '0';
af6bdddf 9302 ++s;
5f47d35b
AM		 9303 if (is_space_char (*s))
9304 ++s;
9305 if (*s == ')')
9306 {
9307 *end_op = s + 1;
1e9cc1c2 9308 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9309 know (r);
9310 return r + fpr;
5f47d35b 9311 }
5f47d35b 9312 }
47926f60 9313 /* We have "%st(" then garbage. */
5f47d35b
AM		 9314 return (const reg_entry *) NULL;
9315 }
9316 }
9317
a60de03c
JB		 9318 if (r == NULL || allow_pseudo_reg)
9319 return r;
9320
0dfbf9d7 9321 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9322 return (const reg_entry *) NULL;
9323
192dc9c6
JB		 9324 if ((r->reg_type.bitfield.reg32
9325 || r->reg_type.bitfield.sreg3
9326 || r->reg_type.bitfield.control
9327 || r->reg_type.bitfield.debug
9328 || r->reg_type.bitfield.test)
9329 && !cpu_arch_flags.bitfield.cpui386)
9330 return (const reg_entry *) NULL;
9331
309d3373
JB		 9332 if (r->reg_type.bitfield.floatreg
9333 && !cpu_arch_flags.bitfield.cpu8087
9334 && !cpu_arch_flags.bitfield.cpu287
9335 && !cpu_arch_flags.bitfield.cpu387)
9336 return (const reg_entry *) NULL;
9337
192dc9c6
JB		 9338 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9339 return (const reg_entry *) NULL;
9340
9341 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9342 return (const reg_entry *) NULL;
9343
40f12533
L		 9344 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9345 return (const reg_entry *) NULL;
9346
43234a1e
L		 9347 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9348 && !cpu_arch_flags.bitfield.cpuavx512f)
9349 return (const reg_entry *) NULL;
9350
db51cc60 9351 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9352 if (!allow_index_reg
db51cc60
L		 9353 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9354 return (const reg_entry *) NULL;
9355
43234a1e
L		 9356 /* Upper 16 vector register is only available with VREX in 64bit
9357 mode. */
9358 if ((r->reg_flags & RegVRex))
9359 {
9360 if (!cpu_arch_flags.bitfield.cpuvrex
9361 || flag_code != CODE_64BIT)
9362 return (const reg_entry *) NULL;
9363
9364 i.need_vrex = 1;
9365 }
9366
a60de03c
JB		 9367 if (((r->reg_flags & (RegRex64 | RegRex))
9368 || r->reg_type.bitfield.reg64)
40fb9820 9369 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9370 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9371 && flag_code != CODE_64BIT)
20f0a1fc 9372 return (const reg_entry *) NULL;
1ae00879 9373
b7240065
JB		 9374 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9375 return (const reg_entry *) NULL;
9376
252b5132
RH		 9377 return r;
9378}
4d1bb795
JB		 9379
9380/* REG_STRING starts *before* REGISTER_PREFIX. */
9381
9382static const reg_entry *
9383parse_register (char *reg_string, char **end_op)
9384{
9385 const reg_entry *r;
9386
9387 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9388 r = parse_real_register (reg_string, end_op);
9389 else
9390 r = NULL;
9391 if (!r)
9392 {
9393 char *save = input_line_pointer;
9394 char c;
9395 symbolS *symbolP;
9396
9397 input_line_pointer = reg_string;
9398 c = get_symbol_end ();
9399 symbolP = symbol_find (reg_string);
9400 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9401 {
9402 const expressionS *e = symbol_get_value_expression (symbolP);
9403
0398aac5 9404 know (e->X_op == O_register);
4eed87de 9405 know (e->X_add_number >= 0
c3fe08fa 9406 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 9407 r = i386_regtab + e->X_add_number;
9408 *end_op = input_line_pointer;
9409 }
9410 *input_line_pointer = c;
9411 input_line_pointer = save;
9412 }
9413 return r;
9414}
9415
9416int
9417i386_parse_name (char *name, expressionS *e, char *nextcharP)
9418{
9419 const reg_entry *r;
9420 char *end = input_line_pointer;
9421
9422 *end = *nextcharP;
9423 r = parse_register (name, &input_line_pointer);
9424 if (r && end <= input_line_pointer)
9425 {
9426 *nextcharP = *input_line_pointer;
9427 *input_line_pointer = 0;
9428 e->X_op = O_register;
9429 e->X_add_number = r - i386_regtab;
9430 return 1;
9431 }
9432 input_line_pointer = end;
9433 *end = 0;
ee86248c 9434 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9435}
9436
9437void
9438md_operand (expressionS *e)
9439{
ee86248c
JB		 9440 char *end;
9441 const reg_entry *r;
4d1bb795 9442
ee86248c
JB		 9443 switch (*input_line_pointer)
9444 {
9445 case REGISTER_PREFIX:
9446 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9447 if (r)
9448 {
9449 e->X_op = O_register;
9450 e->X_add_number = r - i386_regtab;
9451 input_line_pointer = end;
9452 }
ee86248c
JB		 9453 break;
9454
9455 case '[':
9c2799c2 9456 gas_assert (intel_syntax);
ee86248c
JB		 9457 end = input_line_pointer++;
9458 expression (e);
9459 if (*input_line_pointer == ']')
9460 {
9461 ++input_line_pointer;
9462 e->X_op_symbol = make_expr_symbol (e);
9463 e->X_add_symbol = NULL;
9464 e->X_add_number = 0;
9465 e->X_op = O_index;
9466 }
9467 else
9468 {
9469 e->X_op = O_absent;
9470 input_line_pointer = end;
9471 }
9472 break;
4d1bb795
JB		 9473 }
9474}
9475
252b5132 9476\f
4cc782b5 9477#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9478const char *md_shortopts = "kVQ:sqn";
252b5132 9479#else
12b55ccc 9480const char *md_shortopts = "qn";
252b5132 9481#endif
6e0b89ee 9482
3e73aa7c 9483#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9484#define OPTION_64 (OPTION_MD_BASE + 1)
9485#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9486#define OPTION_MARCH (OPTION_MD_BASE + 3)
9487#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9488#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9489#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9490#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9491#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9492#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9493#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9494#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9495#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9496#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9497#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9498#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9499#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9500#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
b3b91714 9501
99ad8390
NC		 9502struct option md_longopts[] =
9503{
3e73aa7c 9504 {"32", no_argument, NULL, OPTION_32},
321098a5 9505#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9507 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9508#endif
9509#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9510 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9511#endif
b3b91714 9512 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9513 {"march", required_argument, NULL, OPTION_MARCH},
9514 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9515 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9516 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9517 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9518 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9519 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9520 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9521 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9522 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9523 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9524 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9525 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9526 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
252b5132
RH		 9527 {NULL, no_argument, NULL, 0}
9528};
9529size_t md_longopts_size = sizeof (md_longopts);
9530
9531int
9103f4f4 9532md_parse_option (int c, char *arg)
252b5132 9533{
91d6fa6a 9534 unsigned int j;
6305a203 9535 char *arch, *next;
9103f4f4 9536
252b5132
RH		 9537 switch (c)
9538 {
12b55ccc
L		 9539 case 'n':
9540 optimize_align_code = 0;
9541 break;
9542
a38cf1db
AM		 9543 case 'q':
9544 quiet_warnings = 1;
252b5132
RH		 9545 break;
9546
9547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9548 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9549 should be emitted or not. FIXME: Not implemented. */
9550 case 'Q':
252b5132
RH		 9551 break;
9552
9553 /* -V: SVR4 argument to print version ID. */
9554 case 'V':
9555 print_version_id ();
9556 break;
9557
a38cf1db
AM		 9558 /* -k: Ignore for FreeBSD compatibility. */
9559 case 'k':
252b5132 9560 break;
4cc782b5
ILT		 9561
9562 case 's':
9563 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9564 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9565 break;
99ad8390 9566#endif
321098a5 9567#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9568 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9569 case OPTION_64:
9570 {
9571 const char **list, **l;
9572
3e73aa7c
JH		 9573 list = bfd_target_list ();
9574 for (l = list; *l != NULL; l++)
8620418b 9575 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9576 || strcmp (*l, "coff-x86-64") == 0
9577 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9578 || strcmp (*l, "pei-x86-64") == 0
9579 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9580 {
9581 default_arch = "x86_64";
9582 break;
9583 }
3e73aa7c 9584 if (*l == NULL)
2b5d6a91 9585 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9586 free (list);
9587 }
9588 break;
9589#endif
252b5132 9590
351f65ca 9591#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9592 case OPTION_X32:
351f65ca
L		 9593 if (IS_ELF)
9594 {
9595 const char **list, **l;
9596
9597 list = bfd_target_list ();
9598 for (l = list; *l != NULL; l++)
9599 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9600 {
9601 default_arch = "x86_64:32";
9602 break;
9603 }
9604 if (*l == NULL)
2b5d6a91 9605 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9606 free (list);
9607 }
9608 else
9609 as_fatal (_("32bit x86_64 is only supported for ELF"));
9610 break;
9611#endif
9612
6e0b89ee
AM		 9613 case OPTION_32:
9614 default_arch = "i386";
9615 break;
9616
b3b91714
AM		 9617 case OPTION_DIVIDE:
9618#ifdef SVR4_COMMENT_CHARS
9619 {
9620 char *n, *t;
9621 const char *s;
9622
9623 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9624 t = n;
9625 for (s = i386_comment_chars; *s != '\0'; s++)
9626 if (*s != '/')
9627 *t++ = *s;
9628 *t = '\0';
9629 i386_comment_chars = n;
9630 }
9631#endif
9632 break;
9633
9103f4f4 9634 case OPTION_MARCH:
6305a203
L		 9635 arch = xstrdup (arg);
9636 do
9103f4f4 9637 {
6305a203 9638 if (*arch == '.')
2b5d6a91 9639 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9640 next = strchr (arch, '+');
9641 if (next)
9642 *next++ = '\0';
91d6fa6a 9643 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9644 {
91d6fa6a 9645 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9646 {
6305a203 9647 /* Processor. */
1ded5609
JB		 9648 if (! cpu_arch[j].flags.bitfield.cpui386)
9649 continue;
9650
91d6fa6a 9651 cpu_arch_name = cpu_arch[j].name;
6305a203 9652 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9653 cpu_arch_flags = cpu_arch[j].flags;
9654 cpu_arch_isa = cpu_arch[j].type;
9655 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9656 if (!cpu_arch_tune_set)
9657 {
9658 cpu_arch_tune = cpu_arch_isa;
9659 cpu_arch_tune_flags = cpu_arch_isa_flags;
9660 }
9661 break;
9662 }
91d6fa6a
NC		 9663 else if (*cpu_arch [j].name == '.'
9664 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9665 {
9666 /* ISA entension. */
9667 i386_cpu_flags flags;
309d3373 9668
49021df2 9669 if (!cpu_arch[j].negated)
309d3373 9670 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9671 cpu_arch[j].flags);
309d3373
JB		 9672 else
9673 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9674 cpu_arch[j].flags);
0dfbf9d7 9675 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9676 {
9677 if (cpu_sub_arch_name)
9678 {
9679 char *name = cpu_sub_arch_name;
9680 cpu_sub_arch_name = concat (name,
91d6fa6a 9681 cpu_arch[j].name,
1bf57e9f 9682 (const char *) NULL);
6305a203
L		 9683 free (name);
9684 }
9685 else
91d6fa6a 9686 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9687 cpu_arch_flags = flags;
a586129e 9688 cpu_arch_isa_flags = flags;
6305a203
L		 9689 }
9690 break;
ccc9c027 9691 }
9103f4f4 9692 }
6305a203 9693
91d6fa6a 9694 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9695 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9696
9697 arch = next;
9103f4f4 9698 }
6305a203 9699 while (next != NULL );
9103f4f4
L		 9700 break;
9701
9702 case OPTION_MTUNE:
9703 if (*arg == '.')
2b5d6a91 9704 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9705 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9706 {
91d6fa6a 9707 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9708 {
ccc9c027 9709 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9710 cpu_arch_tune = cpu_arch [j].type;
9711 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9712 break;
9713 }
9714 }
91d6fa6a 9715 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9716 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9717 break;
9718
1efbbeb4
L		 9719 case OPTION_MMNEMONIC:
9720 if (strcasecmp (arg, "att") == 0)
9721 intel_mnemonic = 0;
9722 else if (strcasecmp (arg, "intel") == 0)
9723 intel_mnemonic = 1;
9724 else
2b5d6a91 9725 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9726 break;
9727
9728 case OPTION_MSYNTAX:
9729 if (strcasecmp (arg, "att") == 0)
9730 intel_syntax = 0;
9731 else if (strcasecmp (arg, "intel") == 0)
9732 intel_syntax = 1;
9733 else
2b5d6a91 9734 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9735 break;
9736
9737 case OPTION_MINDEX_REG:
9738 allow_index_reg = 1;
9739 break;
9740
9741 case OPTION_MNAKED_REG:
9742 allow_naked_reg = 1;
9743 break;
9744
9745 case OPTION_MOLD_GCC:
9746 old_gcc = 1;
1efbbeb4
L		 9747 break;
9748
c0f3af97
L		 9749 case OPTION_MSSE2AVX:
9750 sse2avx = 1;
9751 break;
9752
daf50ae7
L		 9753 case OPTION_MSSE_CHECK:
9754 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9755 sse_check = check_error;
daf50ae7 9756 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9757 sse_check = check_warning;
daf50ae7 9758 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9759 sse_check = check_none;
daf50ae7 9760 else
2b5d6a91 9761 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9762 break;
9763
7bab8ab5
JB		 9764 case OPTION_MOPERAND_CHECK:
9765 if (strcasecmp (arg, "error") == 0)
9766 operand_check = check_error;
9767 else if (strcasecmp (arg, "warning") == 0)
9768 operand_check = check_warning;
9769 else if (strcasecmp (arg, "none") == 0)
9770 operand_check = check_none;
9771 else
9772 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9773 break;
9774
539f890d
L		 9775 case OPTION_MAVXSCALAR:
9776 if (strcasecmp (arg, "128") == 0)
9777 avxscalar = vex128;
9778 else if (strcasecmp (arg, "256") == 0)
9779 avxscalar = vex256;
9780 else
2b5d6a91 9781 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9782 break;
9783
7e8b059b
L		 9784 case OPTION_MADD_BND_PREFIX:
9785 add_bnd_prefix = 1;
9786 break;
9787
43234a1e
L		 9788 case OPTION_MEVEXLIG:
9789 if (strcmp (arg, "128") == 0)
9790 evexlig = evexl128;
9791 else if (strcmp (arg, "256") == 0)
9792 evexlig = evexl256;
9793 else if (strcmp (arg, "512") == 0)
9794 evexlig = evexl512;
9795 else
9796 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9797 break;
9798
9799 case OPTION_MEVEXWIG:
9800 if (strcmp (arg, "0") == 0)
9801 evexwig = evexw0;
9802 else if (strcmp (arg, "1") == 0)
9803 evexwig = evexw1;
9804 else
9805 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9806 break;
9807
252b5132
RH		 9808 default:
9809 return 0;
9810 }
9811 return 1;
9812}
9813
8a2c8fef
L		 9814#define MESSAGE_TEMPLATE \
9815" "
9816
9817static void
1ded5609 9818show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9819{
9820 static char message[] = MESSAGE_TEMPLATE;
9821 char *start = message + 27;
9822 char *p;
9823 int size = sizeof (MESSAGE_TEMPLATE);
9824 int left;
9825 const char *name;
9826 int len;
9827 unsigned int j;
9828
9829 p = start;
9830 left = size - (start - message);
9831 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9832 {
9833 /* Should it be skipped? */
9834 if (cpu_arch [j].skip)
9835 continue;
9836
9837 name = cpu_arch [j].name;
9838 len = cpu_arch [j].len;
9839 if (*name == '.')
9840 {
9841 /* It is an extension. Skip if we aren't asked to show it. */
9842 if (ext)
9843 {
9844 name++;
9845 len--;
9846 }
9847 else
9848 continue;
9849 }
9850 else if (ext)
9851 {
9852 /* It is an processor. Skip if we show only extension. */
9853 continue;
9854 }
1ded5609
JB		 9855 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9856 {
9857 /* It is an impossible processor - skip. */
9858 continue;
9859 }
8a2c8fef
L		 9860
9861 /* Reserve 2 spaces for ", " or ",\0" */
9862 left -= len + 2;
9863
9864 /* Check if there is any room. */
9865 if (left >= 0)
9866 {
9867 if (p != start)
9868 {
9869 *p++ = ',';
9870 *p++ = ' ';
9871 }
9872 p = mempcpy (p, name, len);
9873 }
9874 else
9875 {
9876 /* Output the current message now and start a new one. */
9877 *p++ = ',';
9878 *p = '\0';
9879 fprintf (stream, "%s\n", message);
9880 p = start;
9881 left = size - (start - message) - len - 2;
8d63c93e 9882
8a2c8fef
L		 9883 gas_assert (left >= 0);
9884
9885 p = mempcpy (p, name, len);
9886 }
9887 }
9888
9889 *p = '\0';
9890 fprintf (stream, "%s\n", message);
9891}
9892
252b5132 9893void
8a2c8fef 9894md_show_usage (FILE *stream)
252b5132 9895{
4cc782b5
ILT		 9896#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9897 fprintf (stream, _("\
a38cf1db
AM		 9898 -Q ignored\n\
9899 -V print assembler version number\n\
b3b91714
AM		 9900 -k ignored\n"));
9901#endif
9902 fprintf (stream, _("\
12b55ccc 9903 -n Do not optimize code alignment\n\
b3b91714
AM		 9904 -q quieten some warnings\n"));
9905#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9906 fprintf (stream, _("\
a38cf1db 9907 -s ignored\n"));
b3b91714 9908#endif
321098a5
L		 9909#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9910 || defined (TE_PE) || defined (TE_PEP))
751d281c 9911 fprintf (stream, _("\
570561f7 9912 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9913#endif
b3b91714
AM		 9914#ifdef SVR4_COMMENT_CHARS
9915 fprintf (stream, _("\
9916 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9917#else
9918 fprintf (stream, _("\
b3b91714 9919 --divide ignored\n"));
4cc782b5 9920#endif
9103f4f4 9921 fprintf (stream, _("\
6305a203 9922 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9923 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9924 show_arch (stream, 0, 1);
8a2c8fef
L		 9925 fprintf (stream, _("\
9926 EXTENSION is combination of:\n"));
1ded5609 9927 show_arch (stream, 1, 0);
6305a203 9928 fprintf (stream, _("\
8a2c8fef 9929 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9930 show_arch (stream, 0, 0);
ba104c83 9931 fprintf (stream, _("\
c0f3af97
L		 9932 -msse2avx encode SSE instructions with VEX prefix\n"));
9933 fprintf (stream, _("\
daf50ae7
L		 9934 -msse-check=[none|error|warning]\n\
9935 check SSE instructions\n"));
9936 fprintf (stream, _("\
7bab8ab5
JB		 9937 -moperand-check=[none|error|warning]\n\
9938 check operand combinations for validity\n"));
9939 fprintf (stream, _("\
539f890d
L		 9940 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9941 length\n"));
9942 fprintf (stream, _("\
43234a1e
L		 9943 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9944 length\n"));
9945 fprintf (stream, _("\
9946 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9947 for EVEX.W bit ignored instructions\n"));
9948 fprintf (stream, _("\
ba104c83
L		 9949 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9950 fprintf (stream, _("\
9951 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9952 fprintf (stream, _("\
9953 -mindex-reg support pseudo index registers\n"));
9954 fprintf (stream, _("\
9955 -mnaked-reg don't require `%%' prefix for registers\n"));
9956 fprintf (stream, _("\
9957 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9958 fprintf (stream, _("\
9959 -madd-bnd-prefix add BND prefix for all valid branches\n"));
252b5132
RH		 9960}
9961
3e73aa7c 9962#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9963 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9964 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9965
9966/* Pick the target format to use. */
9967
47926f60 9968const char *
e3bb37b5 9969i386_target_format (void)
252b5132 9970{
351f65ca
L		 9971 if (!strncmp (default_arch, "x86_64", 6))
9972 {
9973 update_code_flag (CODE_64BIT, 1);
9974 if (default_arch[6] == '\0')
7f56bc95 9975 x86_elf_abi = X86_64_ABI;
351f65ca 9976 else
7f56bc95 9977 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9978 }
3e73aa7c 9979 else if (!strcmp (default_arch, "i386"))
78f12dd3 9980 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9981 else
2b5d6a91 9982 as_fatal (_("unknown architecture"));
89507696
JB		 9983
9984 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9985 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9986 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9987 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9988
252b5132
RH		 9989 switch (OUTPUT_FLAVOR)
9990 {
9384f2ff 9991#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 9992 case bfd_target_aout_flavour:
47926f60 9993 return AOUT_TARGET_FORMAT;
4c63da97 9994#endif
9384f2ff
AM		 9995#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9996# if defined (TE_PE) || defined (TE_PEP)
9997 case bfd_target_coff_flavour:
9998 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9999# elif defined (TE_GO32)
0561d57c
JK		 10000 case bfd_target_coff_flavour:
10001 return "coff-go32";
9384f2ff 10002# else
252b5132
RH		 10003 case bfd_target_coff_flavour:
10004 return "coff-i386";
9384f2ff 10005# endif
4c63da97 10006#endif
3e73aa7c 10007#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10008 case bfd_target_elf_flavour:
3e73aa7c 10009 {
351f65ca
L		 10010 const char *format;
10011
10012 switch (x86_elf_abi)
4fa24527 10013 {
351f65ca
L		 10014 default:
10015 format = ELF_TARGET_FORMAT;
10016 break;
7f56bc95 10017 case X86_64_ABI:
351f65ca 10018 use_rela_relocations = 1;
4fa24527 10019 object_64bit = 1;
351f65ca
L		 10020 format = ELF_TARGET_FORMAT64;
10021 break;
7f56bc95 10022 case X86_64_X32_ABI:
4fa24527 10023 use_rela_relocations = 1;
351f65ca 10024 object_64bit = 1;
862be3fb 10025 disallow_64bit_reloc = 1;
351f65ca
L		 10026 format = ELF_TARGET_FORMAT32;
10027 break;
4fa24527 10028 }
3632d14b 10029 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10030 {
7f56bc95 10031 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10032 as_fatal (_("Intel L1OM is 64bit only"));
10033 return ELF_TARGET_L1OM_FORMAT;
10034 }
7a9068fe
L		 10035 if (cpu_arch_isa == PROCESSOR_K1OM)
10036 {
10037 if (x86_elf_abi != X86_64_ABI)
10038 as_fatal (_("Intel K1OM is 64bit only"));
10039 return ELF_TARGET_K1OM_FORMAT;
10040 }
8a9036a4 10041 else
351f65ca 10042 return format;
3e73aa7c 10043 }
e57f8c65
TG		 10044#endif
10045#if defined (OBJ_MACH_O)
10046 case bfd_target_mach_o_flavour:
d382c579
TG		 10047 if (flag_code == CODE_64BIT)
10048 {
10049 use_rela_relocations = 1;
10050 object_64bit = 1;
10051 return "mach-o-x86-64";
10052 }
10053 else
10054 return "mach-o-i386";
4c63da97 10055#endif
252b5132
RH		 10056 default:
10057 abort ();
10058 return NULL;
10059 }
10060}
10061
47926f60 10062#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10063
10064#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10065void
10066i386_elf_emit_arch_note (void)
a847613f 10067{
718ddfc0 10068 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10069 {
10070 char *p;
10071 asection *seg = now_seg;
10072 subsegT subseg = now_subseg;
10073 Elf_Internal_Note i_note;
10074 Elf_External_Note e_note;
10075 asection *note_secp;
10076 int len;
10077
10078 /* Create the .note section. */
10079 note_secp = subseg_new (".note", 0);
10080 bfd_set_section_flags (stdoutput,
10081 note_secp,
10082 SEC_HAS_CONTENTS | SEC_READONLY);
10083
10084 /* Process the arch string. */
10085 len = strlen (cpu_arch_name);
10086
10087 i_note.namesz = len + 1;
10088 i_note.descsz = 0;
10089 i_note.type = NT_ARCH;
10090 p = frag_more (sizeof (e_note.namesz));
10091 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10092 p = frag_more (sizeof (e_note.descsz));
10093 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10094 p = frag_more (sizeof (e_note.type));
10095 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10096 p = frag_more (len + 1);
10097 strcpy (p, cpu_arch_name);
10098
10099 frag_align (2, 0, 0);
10100
10101 subseg_set (seg, subseg);
10102 }
10103}
10104#endif
252b5132 10105\f
252b5132 10106symbolS *
7016a5d5 10107md_undefined_symbol (char *name)
252b5132 10108{
18dc2407
ILT		 10109 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10110 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10111 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10112 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10113 {
10114 if (!GOT_symbol)
10115 {
10116 if (symbol_find (name))
10117 as_bad (_("GOT already in symbol table"));
10118 GOT_symbol = symbol_new (name, undefined_section,
10119 (valueT) 0, &zero_address_frag);
10120 };
10121 return GOT_symbol;
10122 }
252b5132
RH		 10123 return 0;
10124}
10125
10126/* Round up a section size to the appropriate boundary. */
47926f60 10127
252b5132 10128valueT
7016a5d5 10129md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10130{
4c63da97
AM		 10131#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10132 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10133 {
10134 /* For a.out, force the section size to be aligned. If we don't do
10135 this, BFD will align it for us, but it will not write out the
10136 final bytes of the section. This may be a bug in BFD, but it is
10137 easier to fix it here since that is how the other a.out targets
10138 work. */
10139 int align;
10140
10141 align = bfd_get_section_alignment (stdoutput, segment);
10142 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10143 }
252b5132
RH		 10144#endif
10145
10146 return size;
10147}
10148
10149/* On the i386, PC-relative offsets are relative to the start of the
10150 next instruction. That is, the address of the offset, plus its
10151 size, since the offset is always the last part of the insn. */
10152
10153long
e3bb37b5 10154md_pcrel_from (fixS *fixP)
252b5132
RH		 10155{
10156 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10157}
10158
10159#ifndef I386COFF
10160
10161static void
e3bb37b5 10162s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10163{
29b0f896 10164 int temp;
252b5132 10165
8a75718c
JB		 10166#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10167 if (IS_ELF)
10168 obj_elf_section_change_hook ();
10169#endif
252b5132
RH		 10170 temp = get_absolute_expression ();
10171 subseg_set (bss_section, (subsegT) temp);
10172 demand_empty_rest_of_line ();
10173}
10174
10175#endif
10176
252b5132 10177void
e3bb37b5 10178i386_validate_fix (fixS *fixp)
252b5132
RH		 10179{
10180 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10181 {
23df1078
JH		 10182 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10183 {
4fa24527 10184 if (!object_64bit)
23df1078
JH		 10185 abort ();
10186 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10187 }
10188 else
10189 {
4fa24527 10190 if (!object_64bit)
d6ab8113
JB		 10191 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10192 else
10193 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10194 }
252b5132
RH		 10195 fixp->fx_subsy = 0;
10196 }
10197}
10198
252b5132 10199arelent *
7016a5d5 10200tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10201{
10202 arelent *rel;
10203 bfd_reloc_code_real_type code;
10204
10205 switch (fixp->fx_r_type)
10206 {
8ce3d284 10207#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10208 case BFD_RELOC_SIZE32:
10209 case BFD_RELOC_SIZE64:
10210 if (S_IS_DEFINED (fixp->fx_addsy)
10211 && !S_IS_EXTERNAL (fixp->fx_addsy))
10212 {
10213 /* Resolve size relocation against local symbol to size of
10214 the symbol plus addend. */
10215 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10216 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10217 && !fits_in_unsigned_long (value))
10218 as_bad_where (fixp->fx_file, fixp->fx_line,
10219 _("symbol size computation overflow"));
10220 fixp->fx_addsy = NULL;
10221 fixp->fx_subsy = NULL;
10222 md_apply_fix (fixp, (valueT *) &value, NULL);
10223 return NULL;
10224 }
8ce3d284 10225#endif
8fd4256d 10226
3e73aa7c 10227 case BFD_RELOC_X86_64_PLT32:
c3320543 10228 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10229 case BFD_RELOC_X86_64_GOT32:
10230 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10231 case BFD_RELOC_386_PLT32:
10232 case BFD_RELOC_386_GOT32:
10233 case BFD_RELOC_386_GOTOFF:
10234 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10235 case BFD_RELOC_386_TLS_GD:
10236 case BFD_RELOC_386_TLS_LDM:
10237 case BFD_RELOC_386_TLS_LDO_32:
10238 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10239 case BFD_RELOC_386_TLS_IE:
10240 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10241 case BFD_RELOC_386_TLS_LE_32:
10242 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10243 case BFD_RELOC_386_TLS_GOTDESC:
10244 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10245 case BFD_RELOC_X86_64_TLSGD:
10246 case BFD_RELOC_X86_64_TLSLD:
10247 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10248 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10249 case BFD_RELOC_X86_64_GOTTPOFF:
10250 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10251 case BFD_RELOC_X86_64_TPOFF64:
10252 case BFD_RELOC_X86_64_GOTOFF64:
10253 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10254 case BFD_RELOC_X86_64_GOT64:
10255 case BFD_RELOC_X86_64_GOTPCREL64:
10256 case BFD_RELOC_X86_64_GOTPC64:
10257 case BFD_RELOC_X86_64_GOTPLT64:
10258 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10259 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10260 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10261 case BFD_RELOC_RVA:
10262 case BFD_RELOC_VTABLE_ENTRY:
10263 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10264#ifdef TE_PE
10265 case BFD_RELOC_32_SECREL:
10266#endif
252b5132
RH		 10267 code = fixp->fx_r_type;
10268 break;
dbbaec26
L		 10269 case BFD_RELOC_X86_64_32S:
10270 if (!fixp->fx_pcrel)
10271 {
10272 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10273 code = fixp->fx_r_type;
10274 break;
10275 }
252b5132 10276 default:
93382f6d 10277 if (fixp->fx_pcrel)
252b5132 10278 {
93382f6d
AM		 10279 switch (fixp->fx_size)
10280 {
10281 default:
b091f402
AM		 10282 as_bad_where (fixp->fx_file, fixp->fx_line,
10283 _("can not do %d byte pc-relative relocation"),
10284 fixp->fx_size);
93382f6d
AM		 10285 code = BFD_RELOC_32_PCREL;
10286 break;
10287 case 1: code = BFD_RELOC_8_PCREL; break;
10288 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10289 case 4:
10290 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10291 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10292 break;
d6ab8113
JB		 10293#ifdef BFD64
10294 case 8: code = BFD_RELOC_64_PCREL; break;
10295#endif
93382f6d
AM		 10296 }
10297 }
10298 else
10299 {
10300 switch (fixp->fx_size)
10301 {
10302 default:
b091f402
AM		 10303 as_bad_where (fixp->fx_file, fixp->fx_line,
10304 _("can not do %d byte relocation"),
10305 fixp->fx_size);
93382f6d
AM		 10306 code = BFD_RELOC_32;
10307 break;
10308 case 1: code = BFD_RELOC_8; break;
10309 case 2: code = BFD_RELOC_16; break;
10310 case 4: code = BFD_RELOC_32; break;
937149dd 10311#ifdef BFD64
3e73aa7c 10312 case 8: code = BFD_RELOC_64; break;
937149dd 10313#endif
93382f6d 10314 }
252b5132
RH		 10315 }
10316 break;
10317 }
252b5132 10318
d182319b
JB		 10319 if ((code == BFD_RELOC_32
10320 || code == BFD_RELOC_32_PCREL
10321 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10322 && GOT_symbol
10323 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10324 {
4fa24527 10325 if (!object_64bit)
d6ab8113
JB		 10326 code = BFD_RELOC_386_GOTPC;
10327 else
10328 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10329 }
7b81dfbb
AJ		 10330 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10331 && GOT_symbol
10332 && fixp->fx_addsy == GOT_symbol)
10333 {
10334 code = BFD_RELOC_X86_64_GOTPC64;
10335 }
252b5132
RH		 10336
10337 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10338 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10339 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10340
10341 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10342
3e73aa7c
JH		 10343 if (!use_rela_relocations)
10344 {
10345 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10346 vtable entry to be used in the relocation's section offset. */
10347 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10348 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10349#if defined (OBJ_COFF) && defined (TE_PE)
10350 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10351 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10352 else
10353#endif
c6682705 10354 rel->addend = 0;
3e73aa7c
JH		 10355 }
10356 /* Use the rela in 64bit mode. */
252b5132 10357 else
3e73aa7c 10358 {
862be3fb
L		 10359 if (disallow_64bit_reloc)
10360 switch (code)
10361 {
862be3fb
L		 10362 case BFD_RELOC_X86_64_DTPOFF64:
10363 case BFD_RELOC_X86_64_TPOFF64:
10364 case BFD_RELOC_64_PCREL:
10365 case BFD_RELOC_X86_64_GOTOFF64:
10366 case BFD_RELOC_X86_64_GOT64:
10367 case BFD_RELOC_X86_64_GOTPCREL64:
10368 case BFD_RELOC_X86_64_GOTPC64:
10369 case BFD_RELOC_X86_64_GOTPLT64:
10370 case BFD_RELOC_X86_64_PLTOFF64:
10371 as_bad_where (fixp->fx_file, fixp->fx_line,
10372 _("cannot represent relocation type %s in x32 mode"),
10373 bfd_get_reloc_code_name (code));
10374 break;
10375 default:
10376 break;
10377 }
10378
062cd5e7
AS		 10379 if (!fixp->fx_pcrel)
10380 rel->addend = fixp->fx_offset;
10381 else
10382 switch (code)
10383 {
10384 case BFD_RELOC_X86_64_PLT32:
c3320543 10385 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10386 case BFD_RELOC_X86_64_GOT32:
10387 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10388 case BFD_RELOC_X86_64_TLSGD:
10389 case BFD_RELOC_X86_64_TLSLD:
10390 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10391 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10392 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10393 rel->addend = fixp->fx_offset - fixp->fx_size;
10394 break;
10395 default:
10396 rel->addend = (section->vma
10397 - fixp->fx_size
10398 + fixp->fx_addnumber
10399 + md_pcrel_from (fixp));
10400 break;
10401 }
3e73aa7c
JH		 10402 }
10403
252b5132
RH		 10404 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10405 if (rel->howto == NULL)
10406 {
10407 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10408 _("cannot represent relocation type %s"),
252b5132
RH		 10409 bfd_get_reloc_code_name (code));
10410 /* Set howto to a garbage value so that we can keep going. */
10411 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10412 gas_assert (rel->howto != NULL);
252b5132
RH		 10413 }
10414
10415 return rel;
10416}
10417
ee86248c 10418#include "tc-i386-intel.c"
54cfded0 10419
a60de03c
JB		 10420void
10421tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10422{
a60de03c
JB		 10423 int saved_naked_reg;
10424 char saved_register_dot;
54cfded0 10425
a60de03c
JB		 10426 saved_naked_reg = allow_naked_reg;
10427 allow_naked_reg = 1;
10428 saved_register_dot = register_chars['.'];
10429 register_chars['.'] = '.';
10430 allow_pseudo_reg = 1;
10431 expression_and_evaluate (exp);
10432 allow_pseudo_reg = 0;
10433 register_chars['.'] = saved_register_dot;
10434 allow_naked_reg = saved_naked_reg;
10435
e96d56a1 10436 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10437 {
a60de03c
JB		 10438 if ((addressT) exp->X_add_number < i386_regtab_size)
10439 {
10440 exp->X_op = O_constant;
10441 exp->X_add_number = i386_regtab[exp->X_add_number]
10442 .dw2_regnum[flag_code >> 1];
10443 }
10444 else
10445 exp->X_op = O_illegal;
54cfded0 10446 }
54cfded0
AM		 10447}
10448
10449void
10450tc_x86_frame_initial_instructions (void)
10451{
a60de03c
JB		 10452 static unsigned int sp_regno[2];
10453
10454 if (!sp_regno[flag_code >> 1])
10455 {
10456 char *saved_input = input_line_pointer;
10457 char sp[][4] = {"esp", "rsp"};
10458 expressionS exp;
a4447b93 10459
a60de03c
JB		 10460 input_line_pointer = sp[flag_code >> 1];
10461 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10462 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10463 sp_regno[flag_code >> 1] = exp.X_add_number;
10464 input_line_pointer = saved_input;
10465 }
a4447b93 10466
61ff971f
L		 10467 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10468 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10469}
d2b2c203 10470
d7921315
L		 10471int
10472x86_dwarf2_addr_size (void)
10473{
10474#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10475 if (x86_elf_abi == X86_64_X32_ABI)
10476 return 4;
10477#endif
10478 return bfd_arch_bits_per_address (stdoutput) / 8;
10479}
10480
d2b2c203
DJ		 10481int
10482i386_elf_section_type (const char *str, size_t len)
10483{
10484 if (flag_code == CODE_64BIT
10485 && len == sizeof ("unwind") - 1
10486 && strncmp (str, "unwind", 6) == 0)
10487 return SHT_X86_64_UNWIND;
10488
10489 return -1;
10490}
bb41ade5 10491
ad5fec3b
EB		 10492#ifdef TE_SOLARIS
10493void
10494i386_solaris_fix_up_eh_frame (segT sec)
10495{
10496 if (flag_code == CODE_64BIT)
10497 elf_section_type (sec) = SHT_X86_64_UNWIND;
10498}
10499#endif
10500
bb41ade5
AM		 10501#ifdef TE_PE
10502void
10503tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10504{
91d6fa6a 10505 expressionS exp;
bb41ade5 10506
91d6fa6a
NC		 10507 exp.X_op = O_secrel;
10508 exp.X_add_symbol = symbol;
10509 exp.X_add_number = 0;
10510 emit_expr (&exp, size);
bb41ade5
AM		 10511}
10512#endif
3b22753a
L		 10513
10514#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10515/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10516
01e1a5bc 10517bfd_vma
3b22753a
L		 10518x86_64_section_letter (int letter, char **ptr_msg)
10519{
10520 if (flag_code == CODE_64BIT)
10521 {
10522 if (letter == 'l')
10523 return SHF_X86_64_LARGE;
10524
8f3bae45 10525 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10526 }
3b22753a 10527 else
8f3bae45 10528 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10529 return -1;
10530}
10531
01e1a5bc 10532bfd_vma
3b22753a
L		 10533x86_64_section_word (char *str, size_t len)
10534{
8620418b 10535 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10536 return SHF_X86_64_LARGE;
10537
10538 return -1;
10539}
10540
10541static void
10542handle_large_common (int small ATTRIBUTE_UNUSED)
10543{
10544 if (flag_code != CODE_64BIT)
10545 {
10546 s_comm_internal (0, elf_common_parse);
10547 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10548 }
10549 else
10550 {
10551 static segT lbss_section;
10552 asection *saved_com_section_ptr = elf_com_section_ptr;
10553 asection *saved_bss_section = bss_section;
10554
10555 if (lbss_section == NULL)
10556 {
10557 flagword applicable;
10558 segT seg = now_seg;
10559 subsegT subseg = now_subseg;
10560
10561 /* The .lbss section is for local .largecomm symbols. */
10562 lbss_section = subseg_new (".lbss", 0);
10563 applicable = bfd_applicable_section_flags (stdoutput);
10564 bfd_set_section_flags (stdoutput, lbss_section,
10565 applicable & SEC_ALLOC);
10566 seg_info (lbss_section)->bss = 1;
10567
10568 subseg_set (seg, subseg);
10569 }
10570
10571 elf_com_section_ptr = &_bfd_elf_large_com_section;
10572 bss_section = lbss_section;
10573
10574 s_comm_internal (0, elf_common_parse);
10575
10576 elf_com_section_ptr = saved_com_section_ptr;
10577 bss_section = saved_bss_section;
10578 }
10579}
10580#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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