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* dwarf2read.c (dwarf2_add_field): Correctly scale all byte
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
db51cc60 61static void set_allow_index_reg (int);
e3bb37b5 62static void set_cpu_arch (int);
6482c264 63#ifdef TE_PE
e3bb37b5 64static void pe_directive_secrel (int);
6482c264 65#endif
e3bb37b5
L		 66static void signed_cons (int);
67static char *output_invalid (int c);
68static int i386_operand (char *);
69static int i386_intel_operand (char *, int);
70static const reg_entry *parse_register (char *, char **);
71static char *parse_insn (char *, char *);
72static char *parse_operands (char *, const char *);
73static void swap_operands (void);
4d456e3d 74static void swap_2_operands (int, int);
e3bb37b5
L		 75static void optimize_imm (void);
76static void optimize_disp (void);
77static int match_template (void);
78static int check_string (void);
79static int process_suffix (void);
80static int check_byte_reg (void);
81static int check_long_reg (void);
82static int check_qword_reg (void);
83static int check_word_reg (void);
84static int finalize_imm (void);
85f10a01 85static void process_drex (void);
e3bb37b5
L		 86static int process_operands (void);
87static const seg_entry *build_modrm_byte (void);
88static void output_insn (void);
89static void output_imm (fragS *, offsetT);
90static void output_disp (fragS *, offsetT);
29b0f896 91#ifndef I386COFF
e3bb37b5 92static void s_bss (int);
252b5132 93#endif
17d4e2a2
L		 94#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
95static void handle_large_common (int small ATTRIBUTE_UNUSED);
96#endif
252b5132 97
a847613f 98static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 99
252b5132 100/* 'md_assemble ()' gathers together information and puts it into a
47926f60 101 i386_insn. */
252b5132 102
520dc8e8
AM		 103union i386_op
104 {
105 expressionS *disps;
106 expressionS *imms;
107 const reg_entry *regs;
108 };
109
252b5132
RH		 110struct _i386_insn
111 {
47926f60 112 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 113 template tm;
114
115 /* SUFFIX holds the instruction mnemonic suffix if given.
116 (e.g. 'l' for 'movl') */
117 char suffix;
118
47926f60 119 /* OPERANDS gives the number of given operands. */
252b5132
RH		 120 unsigned int operands;
121
122 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
123 of given register, displacement, memory operands and immediate
47926f60 124 operands. */
252b5132
RH		 125 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
126
127 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 128 use OP[i] for the corresponding operand. */
40fb9820 129 i386_operand_type types[MAX_OPERANDS];
252b5132 130
520dc8e8
AM		 131 /* Displacement expression, immediate expression, or register for each
132 operand. */
133 union i386_op op[MAX_OPERANDS];
252b5132 134
3e73aa7c
JH		 135 /* Flags for operands. */
136 unsigned int flags[MAX_OPERANDS];
137#define Operand_PCrel 1
138
252b5132 139 /* Relocation type for operand */
f86103b7 140 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 141
252b5132
RH		 142 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
143 the base index byte below. */
144 const reg_entry *base_reg;
145 const reg_entry *index_reg;
146 unsigned int log2_scale_factor;
147
148 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 149 explicit segment overrides are given. */
ce8a8b2f 150 const seg_entry *seg[2];
252b5132
RH		 151
152 /* PREFIX holds all the given prefix opcodes (usually null).
153 PREFIXES is the number of prefix opcodes. */
154 unsigned int prefixes;
155 unsigned char prefix[MAX_PREFIXES];
156
157 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 158 addressing modes of this insn are encoded. DREX is the byte
159 added by the SSE5 instructions. */
252b5132
RH		 160
161 modrm_byte rm;
3e73aa7c 162 rex_byte rex;
252b5132 163 sib_byte sib;
85f10a01 164 drex_byte drex;
252b5132
RH		 165 };
166
167typedef struct _i386_insn i386_insn;
168
169/* List of chars besides those in app.c:symbol_chars that can start an
170 operand. Used to prevent the scrubber eating vital white-space. */
32137342 171const char extra_symbol_chars[] = "*%-(["
252b5132 172#ifdef LEX_AT
32137342
NC		 173 "@"
174#endif
175#ifdef LEX_QM
176 "?"
252b5132 177#endif
32137342 178 ;
252b5132 179
29b0f896
AM		 180#if (defined (TE_I386AIX) \
181 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 182 && !defined (TE_GNU) \
29b0f896 183 && !defined (TE_LINUX) \
32137342 184 && !defined (TE_NETWARE) \
29b0f896
AM		 185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
252b5132 187/* This array holds the chars that always start a comment. If the
b3b91714
AM		 188 pre-processor is disabled, these aren't very useful. The option
189 --divide will remove '/' from this list. */
190const char *i386_comment_chars = "#/";
191#define SVR4_COMMENT_CHARS 1
252b5132 192#define PREFIX_SEPARATOR '\\'
252b5132 193
b3b91714
AM		 194#else
195const char *i386_comment_chars = "#";
196#define PREFIX_SEPARATOR '/'
197#endif
198
252b5132
RH		 199/* This array holds the chars that only start a comment at the beginning of
200 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 201 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 203 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 204 #NO_APP at the beginning of its output.
205 Also note that comments started like this one will always work if
252b5132 206 '/' isn't otherwise defined. */
b3b91714 207const char line_comment_chars[] = "#/";
252b5132 208
63a0b638 209const char line_separator_chars[] = ";";
252b5132 210
ce8a8b2f
AM		 211/* Chars that can be used to separate mant from exp in floating point
212 nums. */
252b5132
RH		 213const char EXP_CHARS[] = "eE";
214
ce8a8b2f
AM		 215/* Chars that mean this number is a floating point constant
216 As in 0f12.456
217 or 0d1.2345e12. */
252b5132
RH		 218const char FLT_CHARS[] = "fFdDxX";
219
ce8a8b2f 220/* Tables for lexical analysis. */
252b5132
RH		 221static char mnemonic_chars[256];
222static char register_chars[256];
223static char operand_chars[256];
224static char identifier_chars[256];
225static char digit_chars[256];
226
ce8a8b2f 227/* Lexical macros. */
252b5132
RH		 228#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
229#define is_operand_char(x) (operand_chars[(unsigned char) x])
230#define is_register_char(x) (register_chars[(unsigned char) x])
231#define is_space_char(x) ((x) == ' ')
232#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
233#define is_digit_char(x) (digit_chars[(unsigned char) x])
234
0234cb7c 235/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 236static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
237
238/* md_assemble() always leaves the strings it's passed unaltered. To
239 effect this we maintain a stack of saved characters that we've smashed
240 with '\0's (indicating end of strings for various sub-fields of the
47926f60 241 assembler instruction). */
252b5132 242static char save_stack[32];
ce8a8b2f 243static char *save_stack_p;
252b5132
RH		 244#define END_STRING_AND_SAVE(s) \
245 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
246#define RESTORE_END_STRING(s) \
247 do { *(s) = *--save_stack_p; } while (0)
248
47926f60 249/* The instruction we're assembling. */
252b5132
RH		 250static i386_insn i;
251
252/* Possible templates for current insn. */
253static const templates *current_templates;
254
31b2323c
L		 255/* Per instruction expressionS buffers: max displacements & immediates. */
256static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
257static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 258
47926f60
KH		 259/* Current operand we are working on. */
260static int this_operand;
252b5132 261
3e73aa7c
JH		 262/* We support four different modes. FLAG_CODE variable is used to distinguish
263 these. */
264
265enum flag_code {
266 CODE_32BIT,
267 CODE_16BIT,
268 CODE_64BIT };
269
270static enum flag_code flag_code;
4fa24527 271static unsigned int object_64bit;
3e73aa7c
JH		 272static int use_rela_relocations = 0;
273
274/* The names used to print error messages. */
b77a7acd 275static const char *flag_code_names[] =
3e73aa7c
JH		 276 {
277 "32",
278 "16",
279 "64"
280 };
252b5132 281
47926f60
KH		 282/* 1 for intel syntax,
283 0 if att syntax. */
284static int intel_syntax = 0;
252b5132 285
47926f60
KH		 286/* 1 if register prefix % not required. */
287static int allow_naked_reg = 0;
252b5132 288
db51cc60
L		 289/* 1 if fake index register, eiz/riz, is allowed . */
290static int allow_index_reg = 0;
291
2ca3ace5
L		 292/* Register prefix used for error message. */
293static const char *register_prefix = "%";
294
47926f60
KH		 295/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
296 leave, push, and pop instructions so that gcc has the same stack
297 frame as in 32 bit mode. */
298static char stackop_size = '\0';
eecb386c 299
12b55ccc
L		 300/* Non-zero to optimize code alignment. */
301int optimize_align_code = 1;
302
47926f60
KH		 303/* Non-zero to quieten some warnings. */
304static int quiet_warnings = 0;
a38cf1db 305
47926f60
KH		 306/* CPU name. */
307static const char *cpu_arch_name = NULL;
5c6af06e 308static const char *cpu_sub_arch_name = NULL;
a38cf1db 309
47926f60 310/* CPU feature flags. */
40fb9820
L		 311static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
312
313/* Bitwise NOT of cpu_arch_flags. */
314static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 315
ccc9c027
L		 316/* If we have selected a cpu we are generating instructions for. */
317static int cpu_arch_tune_set = 0;
318
9103f4f4
L		 319/* Cpu we are generating instructions for. */
320static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
321
322/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 323static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 324
ccc9c027
L		 325/* CPU instruction set architecture used. */
326static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
327
9103f4f4 328/* CPU feature flags of instruction set architecture used. */
40fb9820 329static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 330
fddf5b5b
AM		 331/* If set, conditional jumps are not automatically promoted to handle
332 larger than a byte offset. */
333static unsigned int no_cond_jump_promotion = 0;
334
29b0f896 335/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 336static symbolS *GOT_symbol;
29b0f896 337
a4447b93
RH		 338/* The dwarf2 return column, adjusted for 32 or 64 bit. */
339unsigned int x86_dwarf2_return_column;
340
341/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
342int x86_cie_data_alignment;
343
252b5132 344/* Interface to relax_segment.
fddf5b5b
AM		 345 There are 3 major relax states for 386 jump insns because the
346 different types of jumps add different sizes to frags when we're
347 figuring out what sort of jump to choose to reach a given label. */
252b5132 348
47926f60 349/* Types. */
93c2a809
AM		 350#define UNCOND_JUMP 0
351#define COND_JUMP 1
352#define COND_JUMP86 2
fddf5b5b 353
47926f60 354/* Sizes. */
252b5132
RH		 355#define CODE16 1
356#define SMALL 0
29b0f896 357#define SMALL16 (SMALL | CODE16)
252b5132 358#define BIG 2
29b0f896 359#define BIG16 (BIG | CODE16)
252b5132
RH		 360
361#ifndef INLINE
362#ifdef __GNUC__
363#define INLINE __inline__
364#else
365#define INLINE
366#endif
367#endif
368
fddf5b5b
AM		 369#define ENCODE_RELAX_STATE(type, size) \
370 ((relax_substateT) (((type) << 2) | (size)))
371#define TYPE_FROM_RELAX_STATE(s) \
372 ((s) >> 2)
373#define DISP_SIZE_FROM_RELAX_STATE(s) \
374 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 375
376/* This table is used by relax_frag to promote short jumps to long
377 ones where necessary. SMALL (short) jumps may be promoted to BIG
378 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
379 don't allow a short jump in a 32 bit code segment to be promoted to
380 a 16 bit offset jump because it's slower (requires data size
381 prefix), and doesn't work, unless the destination is in the bottom
382 64k of the code segment (The top 16 bits of eip are zeroed). */
383
384const relax_typeS md_relax_table[] =
385{
24eab124
AM		 386 /* The fields are:
387 1) most positive reach of this state,
388 2) most negative reach of this state,
93c2a809 389 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 390 4) which index into the table to try if we can't fit into this one. */
252b5132 391
fddf5b5b 392 /* UNCOND_JUMP states. */
93c2a809
AM		 393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
395 /* dword jmp adds 4 bytes to frag:
396 0 extra opcode bytes, 4 displacement bytes. */
252b5132 397 {0, 0, 4, 0},
93c2a809
AM		 398 /* word jmp adds 2 byte2 to frag:
399 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 400 {0, 0, 2, 0},
401
93c2a809
AM		 402 /* COND_JUMP states. */
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
405 /* dword conditionals adds 5 bytes to frag:
406 1 extra opcode byte, 4 displacement bytes. */
407 {0, 0, 5, 0},
fddf5b5b 408 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 409 1 extra opcode byte, 2 displacement bytes. */
410 {0, 0, 3, 0},
411
412 /* COND_JUMP86 states. */
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
415 /* dword conditionals adds 5 bytes to frag:
416 1 extra opcode byte, 4 displacement bytes. */
417 {0, 0, 5, 0},
418 /* word conditionals add 4 bytes to frag:
419 1 displacement byte and a 3 byte long branch insn. */
420 {0, 0, 4, 0}
252b5132
RH		 421};
422
9103f4f4
L		 423static const arch_entry cpu_arch[] =
424{
425 {"generic32", PROCESSOR_GENERIC32,
40fb9820 426 CPU_GENERIC32_FLAGS },
9103f4f4 427 {"generic64", PROCESSOR_GENERIC64,
40fb9820 428 CPU_GENERIC64_FLAGS },
9103f4f4 429 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 430 CPU_NONE_FLAGS },
9103f4f4 431 {"i186", PROCESSOR_UNKNOWN,
40fb9820 432 CPU_I186_FLAGS },
9103f4f4 433 {"i286", PROCESSOR_UNKNOWN,
40fb9820 434 CPU_I286_FLAGS },
76bc74dc 435 {"i386", PROCESSOR_I386,
40fb9820 436 CPU_I386_FLAGS },
9103f4f4 437 {"i486", PROCESSOR_I486,
40fb9820 438 CPU_I486_FLAGS },
9103f4f4 439 {"i586", PROCESSOR_PENTIUM,
40fb9820 440 CPU_I586_FLAGS },
9103f4f4 441 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 442 CPU_I686_FLAGS },
9103f4f4 443 {"pentium", PROCESSOR_PENTIUM,
40fb9820 444 CPU_I586_FLAGS },
9103f4f4 445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 446 CPU_I686_FLAGS },
9103f4f4 447 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 448 CPU_P2_FLAGS },
9103f4f4 449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 450 CPU_P3_FLAGS },
9103f4f4 451 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 452 CPU_P4_FLAGS },
9103f4f4 453 {"prescott", PROCESSOR_NOCONA,
40fb9820 454 CPU_CORE_FLAGS },
9103f4f4 455 {"nocona", PROCESSOR_NOCONA,
40fb9820 456 CPU_NOCONA_FLAGS },
ef05d495 457 {"yonah", PROCESSOR_CORE,
40fb9820 458 CPU_CORE_FLAGS },
ef05d495 459 {"core", PROCESSOR_CORE,
40fb9820 460 CPU_CORE_FLAGS },
ef05d495 461 {"merom", PROCESSOR_CORE2,
40fb9820 462 CPU_CORE2_FLAGS },
ef05d495 463 {"core2", PROCESSOR_CORE2,
40fb9820 464 CPU_CORE2_FLAGS },
9103f4f4 465 {"k6", PROCESSOR_K6,
40fb9820 466 CPU_K6_FLAGS },
9103f4f4 467 {"k6_2", PROCESSOR_K6,
40fb9820 468 CPU_K6_2_FLAGS },
9103f4f4 469 {"athlon", PROCESSOR_ATHLON,
40fb9820 470 CPU_ATHLON_FLAGS },
9103f4f4 471 {"sledgehammer", PROCESSOR_K8,
40fb9820 472 CPU_K8_FLAGS },
9103f4f4 473 {"opteron", PROCESSOR_K8,
40fb9820 474 CPU_K8_FLAGS },
9103f4f4 475 {"k8", PROCESSOR_K8,
40fb9820 476 CPU_K8_FLAGS },
050dfa73 477 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 478 CPU_AMDFAM10_FLAGS },
9103f4f4 479 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 480 CPU_MMX_FLAGS },
9103f4f4 481 {".sse", PROCESSOR_UNKNOWN,
40fb9820 482 CPU_SSE_FLAGS },
9103f4f4 483 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 484 CPU_SSE2_FLAGS },
9103f4f4 485 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 486 CPU_SSE3_FLAGS },
ef05d495 487 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 488 CPU_SSSE3_FLAGS },
42903f7f 489 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 490 CPU_SSE4_1_FLAGS },
381d071f 491 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 492 CPU_SSE4_2_FLAGS },
381d071f 493 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 494 CPU_SSE4_2_FLAGS },
9103f4f4 495 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 496 CPU_3DNOW_FLAGS },
9103f4f4 497 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 498 CPU_3DNOWA_FLAGS },
9103f4f4 499 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 500 CPU_PADLOCK_FLAGS },
9103f4f4 501 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 502 CPU_SVME_FLAGS },
9103f4f4 503 {".svme", PROCESSOR_UNKNOWN,
40fb9820 504 CPU_SVME_FLAGS },
050dfa73 505 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 506 CPU_SSE4A_FLAGS },
050dfa73 507 {".abm", PROCESSOR_UNKNOWN,
40fb9820 508 CPU_ABM_FLAGS },
85f10a01
MM		 509 {".sse5", PROCESSOR_UNKNOWN,
510 CPU_SSE5_FLAGS },
e413e4e9
AM		 511};
512
29b0f896
AM		 513const pseudo_typeS md_pseudo_table[] =
514{
515#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes, 0},
517#else
518 {"align", s_align_ptwo, 0},
519#endif
520 {"arch", set_cpu_arch, 0},
521#ifndef I386COFF
522 {"bss", s_bss, 0},
523#endif
524 {"ffloat", float_cons, 'f'},
525 {"dfloat", float_cons, 'd'},
526 {"tfloat", float_cons, 'x'},
527 {"value", cons, 2},
d182319b 528 {"slong", signed_cons, 4},
29b0f896
AM		 529 {"noopt", s_ignore, 0},
530 {"optim", s_ignore, 0},
531 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
532 {"code16", set_code_flag, CODE_16BIT},
533 {"code32", set_code_flag, CODE_32BIT},
534 {"code64", set_code_flag, CODE_64BIT},
535 {"intel_syntax", set_intel_syntax, 1},
536 {"att_syntax", set_intel_syntax, 0},
db51cc60
L		 537 {"allow_index_reg", set_allow_index_reg, 1},
538 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 539#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
540 {"largecomm", handle_large_common, 0},
07a53e5c 541#else
e3bb37b5 542 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 543 {"loc", dwarf2_directive_loc, 0},
544 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 545#endif
6482c264
NC		 546#ifdef TE_PE
547 {"secrel32", pe_directive_secrel, 0},
548#endif
29b0f896
AM		 549 {0, 0, 0}
550};
551
552/* For interface with expression (). */
553extern char *input_line_pointer;
554
555/* Hash table for instruction mnemonic lookup. */
556static struct hash_control *op_hash;
557
558/* Hash table for register lookup. */
559static struct hash_control *reg_hash;
560\f
252b5132 561void
e3bb37b5 562i386_align_code (fragS *fragP, int count)
252b5132 563{
ce8a8b2f
AM		 564 /* Various efficient no-op patterns for aligning code labels.
565 Note: Don't try to assemble the instructions in the comments.
566 0L and 0w are not legal. */
252b5132
RH		 567 static const char f32_1[] =
568 {0x90}; /* nop */
569 static const char f32_2[] =
ccc9c027 570 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 571 static const char f32_3[] =
572 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
573 static const char f32_4[] =
574 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
575 static const char f32_5[] =
576 {0x90, /* nop */
577 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_6[] =
579 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
580 static const char f32_7[] =
581 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
582 static const char f32_8[] =
583 {0x90, /* nop */
584 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_9[] =
586 {0x89,0xf6, /* movl %esi,%esi */
587 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
588 static const char f32_10[] =
589 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_11[] =
592 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_12[] =
595 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
596 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
597 static const char f32_13[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_14[] =
601 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 603 static const char f16_3[] =
604 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 605 static const char f16_4[] =
606 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
607 static const char f16_5[] =
608 {0x90, /* nop */
609 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_6[] =
611 {0x89,0xf6, /* mov %si,%si */
612 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
613 static const char f16_7[] =
614 {0x8d,0x74,0x00, /* lea 0(%si),%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_8[] =
617 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 619 static const char jump_31[] =
620 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 624 static const char *const f32_patt[] = {
625 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 626 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 627 };
628 static const char *const f16_patt[] = {
76bc74dc 629 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 630 };
ccc9c027
L		 631 /* nopl (%[re]ax) */
632 static const char alt_3[] =
633 {0x0f,0x1f,0x00};
634 /* nopl 0(%[re]ax) */
635 static const char alt_4[] =
636 {0x0f,0x1f,0x40,0x00};
637 /* nopl 0(%[re]ax,%[re]ax,1) */
638 static const char alt_5[] =
639 {0x0f,0x1f,0x44,0x00,0x00};
640 /* nopw 0(%[re]ax,%[re]ax,1) */
641 static const char alt_6[] =
642 {0x66,0x0f,0x1f,0x44,0x00,0x00};
643 /* nopl 0L(%[re]ax) */
644 static const char alt_7[] =
645 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
646 /* nopl 0L(%[re]ax,%[re]ax,1) */
647 static const char alt_8[] =
648 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
649 /* nopw 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_9[] =
651 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
653 static const char alt_10[] =
654 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 /* data16
656 nopw %cs:0L(%[re]ax,%[re]ax,1) */
657 static const char alt_long_11[] =
658 {0x66,
659 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* data16
661 data16
662 nopw %cs:0L(%[re]ax,%[re]ax,1) */
663 static const char alt_long_12[] =
664 {0x66,
665 0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_13[] =
672 {0x66,
673 0x66,
674 0x66,
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
676 /* data16
677 data16
678 data16
679 data16
680 nopw %cs:0L(%[re]ax,%[re]ax,1) */
681 static const char alt_long_14[] =
682 {0x66,
683 0x66,
684 0x66,
685 0x66,
686 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 /* data16
688 data16
689 data16
690 data16
691 data16
692 nopw %cs:0L(%[re]ax,%[re]ax,1) */
693 static const char alt_long_15[] =
694 {0x66,
695 0x66,
696 0x66,
697 0x66,
698 0x66,
699 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 /* nopl 0(%[re]ax,%[re]ax,1)
701 nopw 0(%[re]ax,%[re]ax,1) */
702 static const char alt_short_11[] =
703 {0x0f,0x1f,0x44,0x00,0x00,
704 0x66,0x0f,0x1f,0x44,0x00,0x00};
705 /* nopw 0(%[re]ax,%[re]ax,1)
706 nopw 0(%[re]ax,%[re]ax,1) */
707 static const char alt_short_12[] =
708 {0x66,0x0f,0x1f,0x44,0x00,0x00,
709 0x66,0x0f,0x1f,0x44,0x00,0x00};
710 /* nopw 0(%[re]ax,%[re]ax,1)
711 nopl 0L(%[re]ax) */
712 static const char alt_short_13[] =
713 {0x66,0x0f,0x1f,0x44,0x00,0x00,
714 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
715 /* nopl 0L(%[re]ax)
716 nopl 0L(%[re]ax) */
717 static const char alt_short_14[] =
718 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
719 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
720 /* nopl 0L(%[re]ax)
721 nopl 0L(%[re]ax,%[re]ax,1) */
722 static const char alt_short_15[] =
723 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
724 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
725 static const char *const alt_short_patt[] = {
726 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
727 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
728 alt_short_14, alt_short_15
729 };
730 static const char *const alt_long_patt[] = {
731 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
732 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
733 alt_long_14, alt_long_15
734 };
252b5132 735
76bc74dc
L		 736 /* Only align for at least a positive non-zero boundary. */
737 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 738 return;
3e73aa7c 739
ccc9c027
L		 740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
4eed87de 742
76bc74dc
L		 743 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
744 PROCESSOR_GENERIC32, f32_patt will be used.
745 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
746 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
747 alt_long_patt will be used.
748 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
749 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 750
76bc74dc
L		 751 When -mtune= isn't used, alt_long_patt will be used if
752 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
753 be used.
ccc9c027
L		 754
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
757
758 if (flag_code == CODE_16BIT)
759 {
ccc9c027 760 if (count > 8)
33fef721 761 {
76bc74dc
L		 762 memcpy (fragP->fr_literal + fragP->fr_fix,
763 jump_31, count);
764 /* Adjust jump offset. */
765 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 766 }
76bc74dc
L		 767 else
768 memcpy (fragP->fr_literal + fragP->fr_fix,
769 f16_patt[count - 1], count);
252b5132 770 }
33fef721 771 else
ccc9c027
L		 772 {
773 const char *const *patt = NULL;
774
775 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
776 {
777 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
778 switch (cpu_arch_tune)
779 {
780 case PROCESSOR_UNKNOWN:
781 /* We use cpu_arch_isa_flags to check if we SHOULD
782 optimize for Cpu686. */
40fb9820 783 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 784 patt = alt_long_patt;
ccc9c027
L		 785 else
786 patt = f32_patt;
787 break;
ccc9c027
L		 788 case PROCESSOR_PENTIUMPRO:
789 case PROCESSOR_PENTIUM4:
790 case PROCESSOR_NOCONA:
ef05d495 791 case PROCESSOR_CORE:
76bc74dc
L		 792 case PROCESSOR_CORE2:
793 case PROCESSOR_GENERIC64:
794 patt = alt_long_patt;
795 break;
ccc9c027
L		 796 case PROCESSOR_K6:
797 case PROCESSOR_ATHLON:
798 case PROCESSOR_K8:
4eed87de 799 case PROCESSOR_AMDFAM10:
ccc9c027
L		 800 patt = alt_short_patt;
801 break;
76bc74dc 802 case PROCESSOR_I386:
ccc9c027
L		 803 case PROCESSOR_I486:
804 case PROCESSOR_PENTIUM:
805 case PROCESSOR_GENERIC32:
806 patt = f32_patt;
807 break;
4eed87de 808 }
ccc9c027
L		 809 }
810 else
811 {
812 switch (cpu_arch_tune)
813 {
814 case PROCESSOR_UNKNOWN:
815 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
816 PROCESSOR_UNKNOWN. */
817 abort ();
818 break;
819
76bc74dc 820 case PROCESSOR_I386:
ccc9c027
L		 821 case PROCESSOR_I486:
822 case PROCESSOR_PENTIUM:
ccc9c027
L		 823 case PROCESSOR_K6:
824 case PROCESSOR_ATHLON:
825 case PROCESSOR_K8:
4eed87de 826 case PROCESSOR_AMDFAM10:
ccc9c027
L		 827 case PROCESSOR_GENERIC32:
828 /* We use cpu_arch_isa_flags to check if we CAN optimize
829 for Cpu686. */
40fb9820 830 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 831 patt = alt_short_patt;
832 else
833 patt = f32_patt;
834 break;
76bc74dc
L		 835 case PROCESSOR_PENTIUMPRO:
836 case PROCESSOR_PENTIUM4:
837 case PROCESSOR_NOCONA:
838 case PROCESSOR_CORE:
ef05d495 839 case PROCESSOR_CORE2:
40fb9820 840 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 841 patt = alt_long_patt;
842 else
843 patt = f32_patt;
844 break;
845 case PROCESSOR_GENERIC64:
76bc74dc 846 patt = alt_long_patt;
ccc9c027 847 break;
4eed87de 848 }
ccc9c027
L		 849 }
850
76bc74dc
L		 851 if (patt == f32_patt)
852 {
853 /* If the padding is less than 15 bytes, we use the normal
854 ones. Otherwise, we use a jump instruction and adjust
855 its offset. */
856 if (count < 15)
857 memcpy (fragP->fr_literal + fragP->fr_fix,
858 patt[count - 1], count);
859 else
860 {
861 memcpy (fragP->fr_literal + fragP->fr_fix,
862 jump_31, count);
863 /* Adjust jump offset. */
864 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
865 }
866 }
867 else
868 {
869 /* Maximum length of an instruction is 15 byte. If the
870 padding is greater than 15 bytes and we don't use jump,
871 we have to break it into smaller pieces. */
872 int padding = count;
873 while (padding > 15)
874 {
875 padding -= 15;
876 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
877 patt [14], 15);
878 }
879
880 if (padding)
881 memcpy (fragP->fr_literal + fragP->fr_fix,
882 patt [padding - 1], padding);
883 }
ccc9c027 884 }
33fef721 885 fragP->fr_var = count;
252b5132
RH		 886}
887
c6fb90c8
L		 888static INLINE int
889uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 890{
c6fb90c8
L		 891 switch (size)
892 {
893 case 3:
894 if (x[2])
895 return 0;
896 case 2:
897 if (x[1])
898 return 0;
899 case 1:
900 return !x[0];
901 default:
902 abort ();
903 }
40fb9820
L		 904}
905
c6fb90c8
L		 906static INLINE void
907uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 908{
c6fb90c8
L		 909 switch (size)
910 {
911 case 3:
912 x[2] = v;
913 case 2:
914 x[1] = v;
915 case 1:
916 x[0] = v;
917 break;
918 default:
919 abort ();
920 }
921}
40fb9820 922
c6fb90c8
L		 923static INLINE int
924uints_equal (const unsigned int *x, const unsigned int *y,
925 unsigned int size)
926{
927 switch (size)
928 {
929 case 3:
930 if (x[2] != y [2])
931 return 0;
932 case 2:
933 if (x[1] != y [1])
934 return 0;
935 case 1:
936 return x[0] == y [0];
937 break;
938 default:
939 abort ();
940 }
941}
40fb9820 942
c6fb90c8
L		 943#define UINTS_ALL_ZERO(x) \
944 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
945#define UINTS_SET(x, v) \
946 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
947#define UINTS_CLEAR(x) \
948 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
949#define UINTS_EQUAL(x, y) \
950 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
951
952static INLINE int
953cpu_flags_check_cpu64 (i386_cpu_flags f)
954{
955 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
956 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 957}
958
c6fb90c8 959static INLINE i386_cpu_flags
40fb9820
L		 960cpu_flags_not (i386_cpu_flags x)
961{
c6fb90c8
L		 962 switch (ARRAY_SIZE (x.array))
963 {
964 case 3:
965 x.array [2] = ~x.array [2];
966 case 2:
967 x.array [1] = ~x.array [1];
968 case 1:
969 x.array [0] = ~x.array [0];
970 break;
971 default:
972 abort ();
973 }
40fb9820
L		 974
975#ifdef CpuUnused
976 x.bitfield.unused = 0;
977#endif
978
979 return x;
980}
981
c6fb90c8
L		 982static INLINE i386_cpu_flags
983cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 984{
c6fb90c8
L		 985 switch (ARRAY_SIZE (x.array))
986 {
987 case 3:
988 x.array [2] &= y.array [2];
989 case 2:
990 x.array [1] &= y.array [1];
991 case 1:
992 x.array [0] &= y.array [0];
993 break;
994 default:
995 abort ();
996 }
997 return x;
998}
40fb9820 999
c6fb90c8
L		 1000static INLINE i386_cpu_flags
1001cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1002{
c6fb90c8 1003 switch (ARRAY_SIZE (x.array))
40fb9820 1004 {
c6fb90c8
L		 1005 case 3:
1006 x.array [2] |= y.array [2];
1007 case 2:
1008 x.array [1] |= y.array [1];
1009 case 1:
1010 x.array [0] |= y.array [0];
40fb9820
L		 1011 break;
1012 default:
1013 abort ();
1014 }
40fb9820
L		 1015 return x;
1016}
1017
1018static int
1019cpu_flags_match (i386_cpu_flags x)
1020{
1021 i386_cpu_flags not = cpu_arch_flags_not;
1022
1023 not.bitfield.cpu64 = 1;
1024 not.bitfield.cpuno64 = 1;
1025
1026 x.bitfield.cpu64 = 0;
1027 x.bitfield.cpuno64 = 0;
1028
c6fb90c8
L		 1029 not = cpu_flags_and (x, not);
1030 return UINTS_ALL_ZERO (not);
40fb9820
L		 1031}
1032
c6fb90c8
L		 1033static INLINE i386_operand_type
1034operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1035{
c6fb90c8
L		 1036 switch (ARRAY_SIZE (x.array))
1037 {
1038 case 3:
1039 x.array [2] &= y.array [2];
1040 case 2:
1041 x.array [1] &= y.array [1];
1042 case 1:
1043 x.array [0] &= y.array [0];
1044 break;
1045 default:
1046 abort ();
1047 }
1048 return x;
40fb9820
L		 1049}
1050
c6fb90c8
L		 1051static INLINE i386_operand_type
1052operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1053{
c6fb90c8 1054 switch (ARRAY_SIZE (x.array))
40fb9820 1055 {
c6fb90c8
L		 1056 case 3:
1057 x.array [2] |= y.array [2];
1058 case 2:
1059 x.array [1] |= y.array [1];
1060 case 1:
1061 x.array [0] |= y.array [0];
40fb9820
L		 1062 break;
1063 default:
1064 abort ();
1065 }
c6fb90c8
L		 1066 return x;
1067}
40fb9820 1068
c6fb90c8
L		 1069static INLINE i386_operand_type
1070operand_type_xor (i386_operand_type x, i386_operand_type y)
1071{
1072 switch (ARRAY_SIZE (x.array))
1073 {
1074 case 3:
1075 x.array [2] ^= y.array [2];
1076 case 2:
1077 x.array [1] ^= y.array [1];
1078 case 1:
1079 x.array [0] ^= y.array [0];
1080 break;
1081 default:
1082 abort ();
1083 }
40fb9820
L		 1084 return x;
1085}
1086
1087static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1088static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1089static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1090static const i386_operand_type reg16_inoutportreg
1091 = OPERAND_TYPE_REG16_INOUTPORTREG;
1092static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1093static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1094static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1095static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1096static const i386_operand_type anydisp
1097 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1098static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1099static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1100static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1101static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1102static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1103static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1104static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1105static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1106static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1107static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1108
1109enum operand_type
1110{
1111 reg,
40fb9820
L		 1112 imm,
1113 disp,
1114 anymem
1115};
1116
c6fb90c8 1117static INLINE int
40fb9820
L		 1118operand_type_check (i386_operand_type t, enum operand_type c)
1119{
1120 switch (c)
1121 {
1122 case reg:
1123 return (t.bitfield.reg8
1124 || t.bitfield.reg16
1125 || t.bitfield.reg32
1126 || t.bitfield.reg64);
1127
40fb9820
L		 1128 case imm:
1129 return (t.bitfield.imm8
1130 || t.bitfield.imm8s
1131 || t.bitfield.imm16
1132 || t.bitfield.imm32
1133 || t.bitfield.imm32s
1134 || t.bitfield.imm64);
1135
1136 case disp:
1137 return (t.bitfield.disp8
1138 || t.bitfield.disp16
1139 || t.bitfield.disp32
1140 || t.bitfield.disp32s
1141 || t.bitfield.disp64);
1142
1143 case anymem:
1144 return (t.bitfield.disp8
1145 || t.bitfield.disp16
1146 || t.bitfield.disp32
1147 || t.bitfield.disp32s
1148 || t.bitfield.disp64
1149 || t.bitfield.baseindex);
1150
1151 default:
1152 abort ();
1153 }
1154}
1155
c6fb90c8 1156static INLINE int
40fb9820
L		 1157operand_type_match (i386_operand_type overlap,
1158 i386_operand_type given)
1159{
1160 i386_operand_type temp = overlap;
1161
1162 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1163 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1164 return 0;
1165
1166 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1167 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1168}
1169
1170/* If given types r0 and r1 are registers they must be of the same type
1171 unless the expected operand type register overlap is null.
1172 Note that Acc in a template matches every size of reg. */
1173
c6fb90c8 1174static INLINE int
40fb9820
L		 1175operand_type_register_match (i386_operand_type m0,
1176 i386_operand_type g0,
1177 i386_operand_type t0,
1178 i386_operand_type m1,
1179 i386_operand_type g1,
1180 i386_operand_type t1)
1181{
1182 if (!operand_type_check (g0, reg))
1183 return 1;
1184
1185 if (!operand_type_check (g1, reg))
1186 return 1;
1187
1188 if (g0.bitfield.reg8 == g1.bitfield.reg8
1189 && g0.bitfield.reg16 == g1.bitfield.reg16
1190 && g0.bitfield.reg32 == g1.bitfield.reg32
1191 && g0.bitfield.reg64 == g1.bitfield.reg64)
1192 return 1;
1193
1194 if (m0.bitfield.acc)
1195 {
1196 t0.bitfield.reg8 = 1;
1197 t0.bitfield.reg16 = 1;
1198 t0.bitfield.reg32 = 1;
1199 t0.bitfield.reg64 = 1;
1200 }
1201
1202 if (m1.bitfield.acc)
1203 {
1204 t1.bitfield.reg8 = 1;
1205 t1.bitfield.reg16 = 1;
1206 t1.bitfield.reg32 = 1;
1207 t1.bitfield.reg64 = 1;
1208 }
1209
1210 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1211 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1212 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1213 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1214}
1215
252b5132 1216static INLINE unsigned int
40fb9820 1217mode_from_disp_size (i386_operand_type t)
252b5132 1218{
40fb9820
L		 1219 if (t.bitfield.disp8)
1220 return 1;
1221 else if (t.bitfield.disp16
1222 || t.bitfield.disp32
1223 || t.bitfield.disp32s)
1224 return 2;
1225 else
1226 return 0;
252b5132
RH		 1227}
1228
1229static INLINE int
e3bb37b5 1230fits_in_signed_byte (offsetT num)
252b5132
RH		 1231{
1232 return (num >= -128) && (num <= 127);
47926f60 1233}
252b5132
RH		 1234
1235static INLINE int
e3bb37b5 1236fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1237{
1238 return (num & 0xff) == num;
47926f60 1239}
252b5132
RH		 1240
1241static INLINE int
e3bb37b5 1242fits_in_unsigned_word (offsetT num)
252b5132
RH		 1243{
1244 return (num & 0xffff) == num;
47926f60 1245}
252b5132
RH		 1246
1247static INLINE int
e3bb37b5 1248fits_in_signed_word (offsetT num)
252b5132
RH		 1249{
1250 return (-32768 <= num) && (num <= 32767);
47926f60 1251}
2a962e6d 1252
3e73aa7c 1253static INLINE int
e3bb37b5 1254fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1255{
1256#ifndef BFD64
1257 return 1;
1258#else
1259 return (!(((offsetT) -1 << 31) & num)
1260 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1261#endif
1262} /* fits_in_signed_long() */
2a962e6d 1263
3e73aa7c 1264static INLINE int
e3bb37b5 1265fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1266{
1267#ifndef BFD64
1268 return 1;
1269#else
1270 return (num & (((offsetT) 2 << 31) - 1)) == num;
1271#endif
1272} /* fits_in_unsigned_long() */
252b5132 1273
40fb9820 1274static i386_operand_type
e3bb37b5 1275smallest_imm_type (offsetT num)
252b5132 1276{
40fb9820
L		 1277 i386_operand_type t;
1278
c6fb90c8 1279 UINTS_CLEAR (t);
40fb9820
L		 1280 t.bitfield.imm64 = 1;
1281
1282 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1283 {
1284 /* This code is disabled on the 486 because all the Imm1 forms
1285 in the opcode table are slower on the i486. They're the
1286 versions with the implicitly specified single-position
1287 displacement, which has another syntax if you really want to
1288 use that form. */
40fb9820
L		 1289 t.bitfield.imm1 = 1;
1290 t.bitfield.imm8 = 1;
1291 t.bitfield.imm8s = 1;
1292 t.bitfield.imm16 = 1;
1293 t.bitfield.imm32 = 1;
1294 t.bitfield.imm32s = 1;
1295 }
1296 else if (fits_in_signed_byte (num))
1297 {
1298 t.bitfield.imm8 = 1;
1299 t.bitfield.imm8s = 1;
1300 t.bitfield.imm16 = 1;
1301 t.bitfield.imm32 = 1;
1302 t.bitfield.imm32s = 1;
1303 }
1304 else if (fits_in_unsigned_byte (num))
1305 {
1306 t.bitfield.imm8 = 1;
1307 t.bitfield.imm16 = 1;
1308 t.bitfield.imm32 = 1;
1309 t.bitfield.imm32s = 1;
1310 }
1311 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1312 {
1313 t.bitfield.imm16 = 1;
1314 t.bitfield.imm32 = 1;
1315 t.bitfield.imm32s = 1;
1316 }
1317 else if (fits_in_signed_long (num))
1318 {
1319 t.bitfield.imm32 = 1;
1320 t.bitfield.imm32s = 1;
1321 }
1322 else if (fits_in_unsigned_long (num))
1323 t.bitfield.imm32 = 1;
1324
1325 return t;
47926f60 1326}
252b5132 1327
847f7ad4 1328static offsetT
e3bb37b5 1329offset_in_range (offsetT val, int size)
847f7ad4 1330{
508866be 1331 addressT mask;
ba2adb93 1332
847f7ad4
AM		 1333 switch (size)
1334 {
508866be
L		 1335 case 1: mask = ((addressT) 1 << 8) - 1; break;
1336 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1337 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1338#ifdef BFD64
1339 case 8: mask = ((addressT) 2 << 63) - 1; break;
1340#endif
47926f60 1341 default: abort ();
847f7ad4
AM		 1342 }
1343
ba2adb93 1344 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1345 if (!use_rela_relocations)
1346 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1347 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1348
47926f60 1349 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1350 {
1351 char buf1[40], buf2[40];
1352
1353 sprint_value (buf1, val);
1354 sprint_value (buf2, val & mask);
1355 as_warn (_("%s shortened to %s"), buf1, buf2);
1356 }
1357 return val & mask;
1358}
1359
252b5132
RH		 1360/* Returns 0 if attempting to add a prefix where one from the same
1361 class already exists, 1 if non rep/repne added, 2 if rep/repne
1362 added. */
1363static int
e3bb37b5 1364add_prefix (unsigned int prefix)
252b5132
RH		 1365{
1366 int ret = 1;
b1905489 1367 unsigned int q;
252b5132 1368
29b0f896
AM		 1369 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1370 && flag_code == CODE_64BIT)
b1905489 1371 {
161a04f6
L		 1372 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1373 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1374 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1375 ret = 0;
1376 q = REX_PREFIX;
1377 }
3e73aa7c 1378 else
b1905489
JB		 1379 {
1380 switch (prefix)
1381 {
1382 default:
1383 abort ();
1384
1385 case CS_PREFIX_OPCODE:
1386 case DS_PREFIX_OPCODE:
1387 case ES_PREFIX_OPCODE:
1388 case FS_PREFIX_OPCODE:
1389 case GS_PREFIX_OPCODE:
1390 case SS_PREFIX_OPCODE:
1391 q = SEG_PREFIX;
1392 break;
1393
1394 case REPNE_PREFIX_OPCODE:
1395 case REPE_PREFIX_OPCODE:
1396 ret = 2;
1397 /* fall thru */
1398 case LOCK_PREFIX_OPCODE:
1399 q = LOCKREP_PREFIX;
1400 break;
1401
1402 case FWAIT_OPCODE:
1403 q = WAIT_PREFIX;
1404 break;
1405
1406 case ADDR_PREFIX_OPCODE:
1407 q = ADDR_PREFIX;
1408 break;
1409
1410 case DATA_PREFIX_OPCODE:
1411 q = DATA_PREFIX;
1412 break;
1413 }
1414 if (i.prefix[q] != 0)
1415 ret = 0;
1416 }
252b5132 1417
b1905489 1418 if (ret)
252b5132 1419 {
b1905489
JB		 1420 if (!i.prefix[q])
1421 ++i.prefixes;
1422 i.prefix[q] |= prefix;
252b5132 1423 }
b1905489
JB		 1424 else
1425 as_bad (_("same type of prefix used twice"));
252b5132 1426
252b5132
RH		 1427 return ret;
1428}
1429
1430static void
e3bb37b5 1431set_code_flag (int value)
eecb386c 1432{
3e73aa7c 1433 flag_code = value;
40fb9820
L		 1434 if (flag_code == CODE_64BIT)
1435 {
1436 cpu_arch_flags.bitfield.cpu64 = 1;
1437 cpu_arch_flags.bitfield.cpuno64 = 0;
1438 cpu_arch_flags_not.bitfield.cpu64 = 0;
1439 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1440 }
1441 else
1442 {
1443 cpu_arch_flags.bitfield.cpu64 = 0;
1444 cpu_arch_flags.bitfield.cpuno64 = 1;
1445 cpu_arch_flags_not.bitfield.cpu64 = 1;
1446 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1447 }
1448 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1449 {
1450 as_bad (_("64bit mode not supported on this CPU."));
1451 }
40fb9820 1452 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1453 {
1454 as_bad (_("32bit mode not supported on this CPU."));
1455 }
eecb386c
AM		 1456 stackop_size = '\0';
1457}
1458
1459static void
e3bb37b5 1460set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1461{
3e73aa7c 1462 flag_code = new_code_flag;
40fb9820
L		 1463 if (flag_code != CODE_16BIT)
1464 abort ();
1465 cpu_arch_flags.bitfield.cpu64 = 0;
1466 cpu_arch_flags.bitfield.cpuno64 = 1;
1467 cpu_arch_flags_not.bitfield.cpu64 = 1;
1468 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1469 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1470}
1471
1472static void
e3bb37b5 1473set_intel_syntax (int syntax_flag)
252b5132
RH		 1474{
1475 /* Find out if register prefixing is specified. */
1476 int ask_naked_reg = 0;
1477
1478 SKIP_WHITESPACE ();
29b0f896 1479 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1480 {
1481 char *string = input_line_pointer;
1482 int e = get_symbol_end ();
1483
47926f60 1484 if (strcmp (string, "prefix") == 0)
252b5132 1485 ask_naked_reg = 1;
47926f60 1486 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1487 ask_naked_reg = -1;
1488 else
d0b47220 1489 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1490 *input_line_pointer = e;
1491 }
1492 demand_empty_rest_of_line ();
c3332e24 1493
252b5132
RH		 1494 intel_syntax = syntax_flag;
1495
1496 if (ask_naked_reg == 0)
f86103b7
AM		 1497 allow_naked_reg = (intel_syntax
1498 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1499 else
1500 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1501
e4a3b5a4 1502 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1503 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1504 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1505}
1506
db51cc60
L		 1507static void
1508set_allow_index_reg (int flag)
1509{
1510 allow_index_reg = flag;
1511}
1512
e413e4e9 1513static void
e3bb37b5 1514set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1515{
47926f60 1516 SKIP_WHITESPACE ();
e413e4e9 1517
29b0f896 1518 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1519 {
1520 char *string = input_line_pointer;
1521 int e = get_symbol_end ();
9103f4f4 1522 unsigned int i;
40fb9820 1523 i386_cpu_flags flags;
e413e4e9 1524
9103f4f4 1525 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1526 {
1527 if (strcmp (string, cpu_arch[i].name) == 0)
1528 {
5c6af06e
JB		 1529 if (*string != '.')
1530 {
1531 cpu_arch_name = cpu_arch[i].name;
1532 cpu_sub_arch_name = NULL;
40fb9820
L		 1533 cpu_arch_flags = cpu_arch[i].flags;
1534 if (flag_code == CODE_64BIT)
1535 {
1536 cpu_arch_flags.bitfield.cpu64 = 1;
1537 cpu_arch_flags.bitfield.cpuno64 = 0;
1538 }
1539 else
1540 {
1541 cpu_arch_flags.bitfield.cpu64 = 0;
1542 cpu_arch_flags.bitfield.cpuno64 = 1;
1543 }
1544 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1545 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1546 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1547 if (!cpu_arch_tune_set)
1548 {
1549 cpu_arch_tune = cpu_arch_isa;
1550 cpu_arch_tune_flags = cpu_arch_isa_flags;
1551 }
5c6af06e
JB		 1552 break;
1553 }
40fb9820 1554
c6fb90c8
L		 1555 flags = cpu_flags_or (cpu_arch_flags,
1556 cpu_arch[i].flags);
1557 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1558 {
1559 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1560 cpu_arch_flags = flags;
1561 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1562 }
1563 *input_line_pointer = e;
1564 demand_empty_rest_of_line ();
1565 return;
e413e4e9
AM		 1566 }
1567 }
9103f4f4 1568 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1569 as_bad (_("no such architecture: `%s'"), string);
1570
1571 *input_line_pointer = e;
1572 }
1573 else
1574 as_bad (_("missing cpu architecture"));
1575
fddf5b5b
AM		 1576 no_cond_jump_promotion = 0;
1577 if (*input_line_pointer == ','
29b0f896 1578 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1579 {
1580 char *string = ++input_line_pointer;
1581 int e = get_symbol_end ();
1582
1583 if (strcmp (string, "nojumps") == 0)
1584 no_cond_jump_promotion = 1;
1585 else if (strcmp (string, "jumps") == 0)
1586 ;
1587 else
1588 as_bad (_("no such architecture modifier: `%s'"), string);
1589
1590 *input_line_pointer = e;
1591 }
1592
e413e4e9
AM		 1593 demand_empty_rest_of_line ();
1594}
1595
b9d79e03
JH		 1596unsigned long
1597i386_mach ()
1598{
1599 if (!strcmp (default_arch, "x86_64"))
1600 return bfd_mach_x86_64;
1601 else if (!strcmp (default_arch, "i386"))
1602 return bfd_mach_i386_i386;
1603 else
1604 as_fatal (_("Unknown architecture"));
1605}
b9d79e03 1606\f
252b5132
RH		 1607void
1608md_begin ()
1609{
1610 const char *hash_err;
1611
40fb9820
L		 1612 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1613
47926f60 1614 /* Initialize op_hash hash table. */
252b5132
RH		 1615 op_hash = hash_new ();
1616
1617 {
29b0f896
AM		 1618 const template *optab;
1619 templates *core_optab;
252b5132 1620
47926f60
KH		 1621 /* Setup for loop. */
1622 optab = i386_optab;
252b5132
RH		 1623 core_optab = (templates *) xmalloc (sizeof (templates));
1624 core_optab->start = optab;
1625
1626 while (1)
1627 {
1628 ++optab;
1629 if (optab->name == NULL
1630 || strcmp (optab->name, (optab - 1)->name) != 0)
1631 {
1632 /* different name --> ship out current template list;
47926f60 1633 add to hash table; & begin anew. */
252b5132
RH		 1634 core_optab->end = optab;
1635 hash_err = hash_insert (op_hash,
1636 (optab - 1)->name,
1637 (PTR) core_optab);
1638 if (hash_err)
1639 {
252b5132
RH		 1640 as_fatal (_("Internal Error: Can't hash %s: %s"),
1641 (optab - 1)->name,
1642 hash_err);
1643 }
1644 if (optab->name == NULL)
1645 break;
1646 core_optab = (templates *) xmalloc (sizeof (templates));
1647 core_optab->start = optab;
1648 }
1649 }
1650 }
1651
47926f60 1652 /* Initialize reg_hash hash table. */
252b5132
RH		 1653 reg_hash = hash_new ();
1654 {
29b0f896 1655 const reg_entry *regtab;
c3fe08fa 1656 unsigned int regtab_size = i386_regtab_size;
252b5132 1657
c3fe08fa 1658 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1659 {
1660 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1661 if (hash_err)
3e73aa7c
JH		 1662 as_fatal (_("Internal Error: Can't hash %s: %s"),
1663 regtab->reg_name,
1664 hash_err);
252b5132
RH		 1665 }
1666 }
1667
47926f60 1668 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1669 {
29b0f896
AM		 1670 int c;
1671 char *p;
252b5132
RH		 1672
1673 for (c = 0; c < 256; c++)
1674 {
3882b010 1675 if (ISDIGIT (c))
252b5132
RH		 1676 {
1677 digit_chars[c] = c;
1678 mnemonic_chars[c] = c;
1679 register_chars[c] = c;
1680 operand_chars[c] = c;
1681 }
3882b010 1682 else if (ISLOWER (c))
252b5132
RH		 1683 {
1684 mnemonic_chars[c] = c;
1685 register_chars[c] = c;
1686 operand_chars[c] = c;
1687 }
3882b010 1688 else if (ISUPPER (c))
252b5132 1689 {
3882b010 1690 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1691 register_chars[c] = mnemonic_chars[c];
1692 operand_chars[c] = c;
1693 }
1694
3882b010 1695 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1696 identifier_chars[c] = c;
1697 else if (c >= 128)
1698 {
1699 identifier_chars[c] = c;
1700 operand_chars[c] = c;
1701 }
1702 }
1703
1704#ifdef LEX_AT
1705 identifier_chars['@'] = '@';
32137342
NC		 1706#endif
1707#ifdef LEX_QM
1708 identifier_chars['?'] = '?';
1709 operand_chars['?'] = '?';
252b5132 1710#endif
252b5132 1711 digit_chars['-'] = '-';
791fe849 1712 mnemonic_chars['-'] = '-';
0003779b 1713 mnemonic_chars['.'] = '.';
252b5132
RH		 1714 identifier_chars['_'] = '_';
1715 identifier_chars['.'] = '.';
1716
1717 for (p = operand_special_chars; *p != '\0'; p++)
1718 operand_chars[(unsigned char) *p] = *p;
1719 }
1720
1721#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1722 if (IS_ELF)
252b5132
RH		 1723 {
1724 record_alignment (text_section, 2);
1725 record_alignment (data_section, 2);
1726 record_alignment (bss_section, 2);
1727 }
1728#endif
a4447b93
RH		 1729
1730 if (flag_code == CODE_64BIT)
1731 {
1732 x86_dwarf2_return_column = 16;
1733 x86_cie_data_alignment = -8;
1734 }
1735 else
1736 {
1737 x86_dwarf2_return_column = 8;
1738 x86_cie_data_alignment = -4;
1739 }
252b5132
RH		 1740}
1741
1742void
e3bb37b5 1743i386_print_statistics (FILE *file)
252b5132
RH		 1744{
1745 hash_print_statistics (file, "i386 opcode", op_hash);
1746 hash_print_statistics (file, "i386 register", reg_hash);
1747}
1748\f
252b5132
RH		 1749#ifdef DEBUG386
1750
ce8a8b2f 1751/* Debugging routines for md_assemble. */
e3bb37b5 1752static void pte (template *);
40fb9820 1753static void pt (i386_operand_type);
e3bb37b5
L		 1754static void pe (expressionS *);
1755static void ps (symbolS *);
252b5132
RH		 1756
1757static void
e3bb37b5 1758pi (char *line, i386_insn *x)
252b5132 1759{
09f131f2 1760 unsigned int i;
252b5132
RH		 1761
1762 fprintf (stdout, "%s: template ", line);
1763 pte (&x->tm);
09f131f2
JH		 1764 fprintf (stdout, " address: base %s index %s scale %x\n",
1765 x->base_reg ? x->base_reg->reg_name : "none",
1766 x->index_reg ? x->index_reg->reg_name : "none",
1767 x->log2_scale_factor);
1768 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1769 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1770 fprintf (stdout, " sib: base %x index %x scale %x\n",
1771 x->sib.base, x->sib.index, x->sib.scale);
1772 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1773 (x->rex & REX_W) != 0,
1774 (x->rex & REX_R) != 0,
1775 (x->rex & REX_X) != 0,
1776 (x->rex & REX_B) != 0);
85f10a01
MM		 1777 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1778 x->drex.reg, x->drex.rex);
252b5132
RH		 1779 for (i = 0; i < x->operands; i++)
1780 {
1781 fprintf (stdout, " #%d: ", i + 1);
1782 pt (x->types[i]);
1783 fprintf (stdout, "\n");
40fb9820
L		 1784 if (x->types[i].bitfield.reg8
1785 || x->types[i].bitfield.reg16
1786 || x->types[i].bitfield.reg32
1787 || x->types[i].bitfield.reg64
1788 || x->types[i].bitfield.regmmx
1789 || x->types[i].bitfield.regxmm
1790 || x->types[i].bitfield.sreg2
1791 || x->types[i].bitfield.sreg3
1792 || x->types[i].bitfield.control
1793 || x->types[i].bitfield.debug
1794 || x->types[i].bitfield.test)
520dc8e8 1795 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1796 if (operand_type_check (x->types[i], imm))
520dc8e8 1797 pe (x->op[i].imms);
40fb9820 1798 if (operand_type_check (x->types[i], disp))
520dc8e8 1799 pe (x->op[i].disps);
252b5132
RH		 1800 }
1801}
1802
1803static void
e3bb37b5 1804pte (template *t)
252b5132 1805{
09f131f2 1806 unsigned int i;
252b5132 1807 fprintf (stdout, " %d operands ", t->operands);
47926f60 1808 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1809 if (t->extension_opcode != None)
1810 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1811 if (t->opcode_modifier.d)
252b5132 1812 fprintf (stdout, "D");
40fb9820 1813 if (t->opcode_modifier.w)
252b5132
RH		 1814 fprintf (stdout, "W");
1815 fprintf (stdout, "\n");
1816 for (i = 0; i < t->operands; i++)
1817 {
1818 fprintf (stdout, " #%d type ", i + 1);
1819 pt (t->operand_types[i]);
1820 fprintf (stdout, "\n");
1821 }
1822}
1823
1824static void
e3bb37b5 1825pe (expressionS *e)
252b5132 1826{
24eab124 1827 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1828 fprintf (stdout, " add_number %ld (%lx)\n",
1829 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1830 if (e->X_add_symbol)
1831 {
1832 fprintf (stdout, " add_symbol ");
1833 ps (e->X_add_symbol);
1834 fprintf (stdout, "\n");
1835 }
1836 if (e->X_op_symbol)
1837 {
1838 fprintf (stdout, " op_symbol ");
1839 ps (e->X_op_symbol);
1840 fprintf (stdout, "\n");
1841 }
1842}
1843
1844static void
e3bb37b5 1845ps (symbolS *s)
252b5132
RH		 1846{
1847 fprintf (stdout, "%s type %s%s",
1848 S_GET_NAME (s),
1849 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1850 segment_name (S_GET_SEGMENT (s)));
1851}
1852
7b81dfbb 1853static struct type_name
252b5132 1854 {
40fb9820
L		 1855 i386_operand_type mask;
1856 const char *name;
252b5132 1857 }
7b81dfbb 1858const type_names[] =
252b5132 1859{
40fb9820
L		 1860 { OPERAND_TYPE_REG8, "r8" },
1861 { OPERAND_TYPE_REG16, "r16" },
1862 { OPERAND_TYPE_REG32, "r32" },
1863 { OPERAND_TYPE_REG64, "r64" },
1864 { OPERAND_TYPE_IMM8, "i8" },
1865 { OPERAND_TYPE_IMM8, "i8s" },
1866 { OPERAND_TYPE_IMM16, "i16" },
1867 { OPERAND_TYPE_IMM32, "i32" },
1868 { OPERAND_TYPE_IMM32S, "i32s" },
1869 { OPERAND_TYPE_IMM64, "i64" },
1870 { OPERAND_TYPE_IMM1, "i1" },
1871 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1872 { OPERAND_TYPE_DISP8, "d8" },
1873 { OPERAND_TYPE_DISP16, "d16" },
1874 { OPERAND_TYPE_DISP32, "d32" },
1875 { OPERAND_TYPE_DISP32S, "d32s" },
1876 { OPERAND_TYPE_DISP64, "d64" },
1877 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1878 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1879 { OPERAND_TYPE_CONTROL, "control reg" },
1880 { OPERAND_TYPE_TEST, "test reg" },
1881 { OPERAND_TYPE_DEBUG, "debug reg" },
1882 { OPERAND_TYPE_FLOATREG, "FReg" },
1883 { OPERAND_TYPE_FLOATACC, "FAcc" },
1884 { OPERAND_TYPE_SREG2, "SReg2" },
1885 { OPERAND_TYPE_SREG3, "SReg3" },
1886 { OPERAND_TYPE_ACC, "Acc" },
1887 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1888 { OPERAND_TYPE_REGMMX, "rMMX" },
1889 { OPERAND_TYPE_REGXMM, "rXMM" },
1890 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1891};
1892
1893static void
40fb9820 1894pt (i386_operand_type t)
252b5132 1895{
40fb9820 1896 unsigned int j;
c6fb90c8 1897 i386_operand_type a;
252b5132 1898
40fb9820 1899 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1900 {
1901 a = operand_type_and (t, type_names[j].mask);
1902 if (!UINTS_ALL_ZERO (a))
1903 fprintf (stdout, "%s, ", type_names[j].name);
1904 }
252b5132
RH		 1905 fflush (stdout);
1906}
1907
1908#endif /* DEBUG386 */
1909\f
252b5132 1910static bfd_reloc_code_real_type
3956db08 1911reloc (unsigned int size,
64e74474
AM		 1912 int pcrel,
1913 int sign,
1914 bfd_reloc_code_real_type other)
252b5132 1915{
47926f60 1916 if (other != NO_RELOC)
3956db08
JB		 1917 {
1918 reloc_howto_type *reloc;
1919
1920 if (size == 8)
1921 switch (other)
1922 {
64e74474
AM		 1923 case BFD_RELOC_X86_64_GOT32:
1924 return BFD_RELOC_X86_64_GOT64;
1925 break;
1926 case BFD_RELOC_X86_64_PLTOFF64:
1927 return BFD_RELOC_X86_64_PLTOFF64;
1928 break;
1929 case BFD_RELOC_X86_64_GOTPC32:
1930 other = BFD_RELOC_X86_64_GOTPC64;
1931 break;
1932 case BFD_RELOC_X86_64_GOTPCREL:
1933 other = BFD_RELOC_X86_64_GOTPCREL64;
1934 break;
1935 case BFD_RELOC_X86_64_TPOFF32:
1936 other = BFD_RELOC_X86_64_TPOFF64;
1937 break;
1938 case BFD_RELOC_X86_64_DTPOFF32:
1939 other = BFD_RELOC_X86_64_DTPOFF64;
1940 break;
1941 default:
1942 break;
3956db08 1943 }
e05278af
JB		 1944
1945 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1946 if (size == 4 && flag_code != CODE_64BIT)
1947 sign = -1;
1948
3956db08
JB		 1949 reloc = bfd_reloc_type_lookup (stdoutput, other);
1950 if (!reloc)
1951 as_bad (_("unknown relocation (%u)"), other);
1952 else if (size != bfd_get_reloc_size (reloc))
1953 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1954 bfd_get_reloc_size (reloc),
1955 size);
1956 else if (pcrel && !reloc->pc_relative)
1957 as_bad (_("non-pc-relative relocation for pc-relative field"));
1958 else if ((reloc->complain_on_overflow == complain_overflow_signed
1959 && !sign)
1960 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1961 && sign > 0))
3956db08
JB		 1962 as_bad (_("relocated field and relocation type differ in signedness"));
1963 else
1964 return other;
1965 return NO_RELOC;
1966 }
252b5132
RH		 1967
1968 if (pcrel)
1969 {
3e73aa7c 1970 if (!sign)
3956db08 1971 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1972 switch (size)
1973 {
1974 case 1: return BFD_RELOC_8_PCREL;
1975 case 2: return BFD_RELOC_16_PCREL;
1976 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1977 case 8: return BFD_RELOC_64_PCREL;
252b5132 1978 }
3956db08 1979 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1980 }
1981 else
1982 {
3956db08 1983 if (sign > 0)
e5cb08ac 1984 switch (size)
3e73aa7c
JH		 1985 {
1986 case 4: return BFD_RELOC_X86_64_32S;
1987 }
1988 else
1989 switch (size)
1990 {
1991 case 1: return BFD_RELOC_8;
1992 case 2: return BFD_RELOC_16;
1993 case 4: return BFD_RELOC_32;
1994 case 8: return BFD_RELOC_64;
1995 }
3956db08
JB		 1996 as_bad (_("cannot do %s %u byte relocation"),
1997 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1998 }
1999
bfb32b52 2000 abort ();
252b5132
RH		 2001 return BFD_RELOC_NONE;
2002}
2003
47926f60
KH		 2004/* Here we decide which fixups can be adjusted to make them relative to
2005 the beginning of the section instead of the symbol. Basically we need
2006 to make sure that the dynamic relocations are done correctly, so in
2007 some cases we force the original symbol to be used. */
2008
252b5132 2009int
e3bb37b5 2010tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2011{
6d249963 2012#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2013 if (!IS_ELF)
31312f95
AM		 2014 return 1;
2015
a161fe53
AM		 2016 /* Don't adjust pc-relative references to merge sections in 64-bit
2017 mode. */
2018 if (use_rela_relocations
2019 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2020 && fixP->fx_pcrel)
252b5132 2021 return 0;
31312f95 2022
8d01d9a9
AJ		 2023 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2024 and changed later by validate_fix. */
2025 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2026 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2027 return 0;
2028
ce8a8b2f 2029 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2030 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2031 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2032 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2040 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2041 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2042 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2043 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2046 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2047 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2049 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2050 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2051 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2052 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2053 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2054 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2055 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2056 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2057 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2058 return 0;
31312f95 2059#endif
252b5132
RH		 2060 return 1;
2061}
252b5132 2062
b4cac588 2063static int
e3bb37b5 2064intel_float_operand (const char *mnemonic)
252b5132 2065{
9306ca4a
JB		 2066 /* Note that the value returned is meaningful only for opcodes with (memory)
2067 operands, hence the code here is free to improperly handle opcodes that
2068 have no operands (for better performance and smaller code). */
2069
2070 if (mnemonic[0] != 'f')
2071 return 0; /* non-math */
2072
2073 switch (mnemonic[1])
2074 {
2075 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2076 the fs segment override prefix not currently handled because no
2077 call path can make opcodes without operands get here */
2078 case 'i':
2079 return 2 /* integer op */;
2080 case 'l':
2081 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2082 return 3; /* fldcw/fldenv */
2083 break;
2084 case 'n':
2085 if (mnemonic[2] != 'o' /* fnop */)
2086 return 3; /* non-waiting control op */
2087 break;
2088 case 'r':
2089 if (mnemonic[2] == 's')
2090 return 3; /* frstor/frstpm */
2091 break;
2092 case 's':
2093 if (mnemonic[2] == 'a')
2094 return 3; /* fsave */
2095 if (mnemonic[2] == 't')
2096 {
2097 switch (mnemonic[3])
2098 {
2099 case 'c': /* fstcw */
2100 case 'd': /* fstdw */
2101 case 'e': /* fstenv */
2102 case 's': /* fsts[gw] */
2103 return 3;
2104 }
2105 }
2106 break;
2107 case 'x':
2108 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2109 return 0; /* fxsave/fxrstor are not really math ops */
2110 break;
2111 }
252b5132 2112
9306ca4a 2113 return 1;
252b5132
RH		 2114}
2115
2116/* This is the guts of the machine-dependent assembler. LINE points to a
2117 machine dependent instruction. This function is supposed to emit
2118 the frags/bytes it assembles to. */
2119
2120void
2121md_assemble (line)
2122 char *line;
2123{
40fb9820 2124 unsigned int j;
252b5132
RH		 2125 char mnemonic[MAX_MNEM_SIZE];
2126
47926f60 2127 /* Initialize globals. */
252b5132
RH		 2128 memset (&i, '\0', sizeof (i));
2129 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2130 i.reloc[j] = NO_RELOC;
252b5132
RH		 2131 memset (disp_expressions, '\0', sizeof (disp_expressions));
2132 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2133 save_stack_p = save_stack;
252b5132
RH		 2134
2135 /* First parse an instruction mnemonic & call i386_operand for the operands.
2136 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2137 start of a (possibly prefixed) mnemonic. */
252b5132 2138
29b0f896
AM		 2139 line = parse_insn (line, mnemonic);
2140 if (line == NULL)
2141 return;
252b5132 2142
29b0f896
AM		 2143 line = parse_operands (line, mnemonic);
2144 if (line == NULL)
2145 return;
252b5132 2146
29b0f896
AM		 2147 /* Now we've parsed the mnemonic into a set of templates, and have the
2148 operands at hand. */
2149
2150 /* All intel opcodes have reversed operands except for "bound" and
2151 "enter". We also don't reverse intersegment "jmp" and "call"
2152 instructions with 2 immediate operands so that the immediate segment
050dfa73 2153 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2154 if (intel_syntax
2155 && i.operands > 1
29b0f896 2156 && (strcmp (mnemonic, "bound") != 0)
30123838 2157 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2158 && !(operand_type_check (i.types[0], imm)
2159 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2160 swap_operands ();
2161
ec56d5c0
JB		 2162 /* The order of the immediates should be reversed
2163 for 2 immediates extrq and insertq instructions */
2164 if (i.imm_operands == 2
2165 && (strcmp (mnemonic, "extrq") == 0
2166 || strcmp (mnemonic, "insertq") == 0))
2167 swap_2_operands (0, 1);
2168
29b0f896
AM		 2169 if (i.imm_operands)
2170 optimize_imm ();
2171
b300c311
L		 2172 /* Don't optimize displacement for movabs since it only takes 64bit
2173 displacement. */
2174 if (i.disp_operands
2175 && (flag_code != CODE_64BIT
2176 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2177 optimize_disp ();
2178
2179 /* Next, we find a template that matches the given insn,
2180 making sure the overlap of the given operands types is consistent
2181 with the template operand types. */
252b5132 2182
29b0f896
AM		 2183 if (!match_template ())
2184 return;
252b5132 2185
cd61ebfe
AM		 2186 if (intel_syntax)
2187 {
2188 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2189 if (SYSV386_COMPAT
2190 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2191 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2192
2193 /* Zap movzx and movsx suffix. The suffix may have been set from
2194 "word ptr" or "byte ptr" on the source operand, but we'll use
2195 the suffix later to choose the destination register. */
2196 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2197 {
2198 if (i.reg_operands < 2
2199 && !i.suffix
40fb9820
L		 2200 && (!i.tm.opcode_modifier.no_bsuf
2201 || !i.tm.opcode_modifier.no_wsuf
2202 || !i.tm.opcode_modifier.no_lsuf
2203 || !i.tm.opcode_modifier.no_ssuf
7ce189b3 2204 || !i.tm.opcode_modifier.no_ldsuf
40fb9820 2205 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2206 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2207
2208 i.suffix = 0;
2209 }
cd61ebfe 2210 }
24eab124 2211
40fb9820 2212 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2213 if (!add_prefix (FWAIT_OPCODE))
2214 return;
252b5132 2215
29b0f896 2216 /* Check string instruction segment overrides. */
40fb9820 2217 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2218 {
2219 if (!check_string ())
5dd0794d 2220 return;
29b0f896 2221 }
5dd0794d 2222
29b0f896
AM		 2223 if (!process_suffix ())
2224 return;
e413e4e9 2225
29b0f896
AM		 2226 /* Make still unresolved immediate matches conform to size of immediate
2227 given in i.suffix. */
2228 if (!finalize_imm ())
2229 return;
252b5132 2230
40fb9820 2231 if (i.types[0].bitfield.imm1)
29b0f896 2232 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2233
40fb9820 2234 for (j = 0; j < 3; j++)
c6fb90c8
L		 2235 if (i.types[j].bitfield.inoutportreg
2236 || i.types[j].bitfield.shiftcount
2237 || i.types[j].bitfield.acc
2238 || i.types[j].bitfield.floatacc)
40fb9820
L		 2239 i.reg_operands--;
2240
2241 if (i.tm.opcode_modifier.immext)
29b0f896 2242 {
02fc3089
L		 2243 expressionS *exp;
2244
40fb9820 2245 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2246 {
b7d9ef37 2247 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2248 operands with an opcode suffix which is coded in the same
2249 place as an 8-bit immediate field would be. Here we check
2250 those operands and remove them afterwards. */
2251 unsigned int x;
2252
a4622f40 2253 for (x = 0; x < i.operands; x++)
ca164297 2254 if (i.op[x].regs->reg_num != x)
a540244d
L		 2255 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2256 register_prefix,
2257 i.op[x].regs->reg_name,
2258 x + 1,
2259 i.tm.name);
ca164297
L		 2260 i.operands = 0;
2261 }
2262
29b0f896
AM		 2263 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2264 opcode suffix which is coded in the same place as an 8-bit
2265 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2266 operand from the opcode suffix stored in tm.extension_opcode.
2267 SSE5 also uses this encoding, for some of its 3 argument
2268 instructions. */
252b5132 2269
85f10a01
MM		 2270 assert (i.imm_operands == 0
2271 && (i.operands <= 2
2272 || (i.tm.cpu_flags.bitfield.cpusse5
2273 && i.operands <= 3)));
252b5132 2274
29b0f896
AM		 2275 exp = &im_expressions[i.imm_operands++];
2276 i.op[i.operands].imms = exp;
c6fb90c8 2277 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2278 i.types[i.operands].bitfield.imm8 = 1;
2279 i.operands++;
29b0f896
AM		 2280 exp->X_op = O_constant;
2281 exp->X_add_number = i.tm.extension_opcode;
2282 i.tm.extension_opcode = None;
2283 }
252b5132 2284
29b0f896
AM		 2285 /* For insns with operands there are more diddles to do to the opcode. */
2286 if (i.operands)
2287 {
2288 if (!process_operands ())
2289 return;
2290 }
40fb9820 2291 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2292 {
2293 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2294 as_warn (_("translating to `%sp'"), i.tm.name);
2295 }
252b5132 2296
29b0f896
AM		 2297 /* Handle conversion of 'int $3' --> special int3 insn. */
2298 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2299 {
2300 i.tm.base_opcode = INT3_OPCODE;
2301 i.imm_operands = 0;
2302 }
252b5132 2303
40fb9820
L		 2304 if ((i.tm.opcode_modifier.jump
2305 || i.tm.opcode_modifier.jumpbyte
2306 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2307 && i.op[0].disps->X_op == O_constant)
2308 {
2309 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2310 the absolute address given by the constant. Since ix86 jumps and
2311 calls are pc relative, we need to generate a reloc. */
2312 i.op[0].disps->X_add_symbol = &abs_symbol;
2313 i.op[0].disps->X_op = O_symbol;
2314 }
252b5132 2315
40fb9820 2316 if (i.tm.opcode_modifier.rex64)
161a04f6 2317 i.rex |= REX_W;
252b5132 2318
29b0f896
AM		 2319 /* For 8 bit registers we need an empty rex prefix. Also if the
2320 instruction already has a prefix, we need to convert old
2321 registers to new ones. */
773f551c 2322
40fb9820 2323 if ((i.types[0].bitfield.reg8
29b0f896 2324 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2325 || (i.types[1].bitfield.reg8
29b0f896 2326 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2327 || ((i.types[0].bitfield.reg8
2328 || i.types[1].bitfield.reg8)
29b0f896
AM		 2329 && i.rex != 0))
2330 {
2331 int x;
726c5dcd 2332
29b0f896
AM		 2333 i.rex |= REX_OPCODE;
2334 for (x = 0; x < 2; x++)
2335 {
2336 /* Look for 8 bit operand that uses old registers. */
40fb9820 2337 if (i.types[x].bitfield.reg8
29b0f896 2338 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2339 {
29b0f896
AM		 2340 /* In case it is "hi" register, give up. */
2341 if (i.op[x].regs->reg_num > 3)
a540244d 2342 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2343 "instruction requiring REX prefix."),
a540244d 2344 register_prefix, i.op[x].regs->reg_name);
773f551c 2345
29b0f896
AM		 2346 /* Otherwise it is equivalent to the extended register.
2347 Since the encoding doesn't change this is merely
2348 cosmetic cleanup for debug output. */
2349
2350 i.op[x].regs = i.op[x].regs + 8;
773f551c 2351 }
29b0f896
AM		 2352 }
2353 }
773f551c 2354
85f10a01
MM		 2355 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2356 REX prefix. */
2357 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2358 {
2359 i.drex.rex = i.rex;
2360 i.rex = 0;
2361 }
2362 else if (i.rex != 0)
29b0f896
AM		 2363 add_prefix (REX_OPCODE | i.rex);
2364
2365 /* We are ready to output the insn. */
2366 output_insn ();
2367}
2368
2369static char *
e3bb37b5 2370parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2371{
2372 char *l = line;
2373 char *token_start = l;
2374 char *mnem_p;
5c6af06e
JB		 2375 int supported;
2376 const template *t;
29b0f896
AM		 2377
2378 /* Non-zero if we found a prefix only acceptable with string insns. */
2379 const char *expecting_string_instruction = NULL;
45288df1 2380
29b0f896
AM		 2381 while (1)
2382 {
2383 mnem_p = mnemonic;
2384 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2385 {
2386 mnem_p++;
2387 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2388 {
29b0f896
AM		 2389 as_bad (_("no such instruction: `%s'"), token_start);
2390 return NULL;
2391 }
2392 l++;
2393 }
2394 if (!is_space_char (*l)
2395 && *l != END_OF_INSN
e44823cf
JB		 2396 && (intel_syntax
2397 || (*l != PREFIX_SEPARATOR
2398 && *l != ',')))
29b0f896
AM		 2399 {
2400 as_bad (_("invalid character %s in mnemonic"),
2401 output_invalid (*l));
2402 return NULL;
2403 }
2404 if (token_start == l)
2405 {
e44823cf 2406 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2407 as_bad (_("expecting prefix; got nothing"));
2408 else
2409 as_bad (_("expecting mnemonic; got nothing"));
2410 return NULL;
2411 }
45288df1 2412
29b0f896
AM		 2413 /* Look up instruction (or prefix) via hash table. */
2414 current_templates = hash_find (op_hash, mnemonic);
47926f60 2415
29b0f896
AM		 2416 if (*l != END_OF_INSN
2417 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2418 && current_templates
40fb9820 2419 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2420 {
c6fb90c8 2421 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2422 {
2423 as_bad ((flag_code != CODE_64BIT
2424 ? _("`%s' is only supported in 64-bit mode")
2425 : _("`%s' is not supported in 64-bit mode")),
2426 current_templates->start->name);
2427 return NULL;
2428 }
29b0f896
AM		 2429 /* If we are in 16-bit mode, do not allow addr16 or data16.
2430 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2431 if ((current_templates->start->opcode_modifier.size16
2432 || current_templates->start->opcode_modifier.size32)
29b0f896 2433 && flag_code != CODE_64BIT
40fb9820 2434 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2435 ^ (flag_code == CODE_16BIT)))
2436 {
2437 as_bad (_("redundant %s prefix"),
2438 current_templates->start->name);
2439 return NULL;
45288df1 2440 }
29b0f896
AM		 2441 /* Add prefix, checking for repeated prefixes. */
2442 switch (add_prefix (current_templates->start->base_opcode))
2443 {
2444 case 0:
2445 return NULL;
2446 case 2:
2447 expecting_string_instruction = current_templates->start->name;
2448 break;
2449 }
2450 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2451 token_start = ++l;
2452 }
2453 else
2454 break;
2455 }
45288df1 2456
29b0f896
AM		 2457 if (!current_templates)
2458 {
2459 /* See if we can get a match by trimming off a suffix. */
2460 switch (mnem_p[-1])
2461 {
2462 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2463 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2464 i.suffix = SHORT_MNEM_SUFFIX;
2465 else
29b0f896
AM		 2466 case BYTE_MNEM_SUFFIX:
2467 case QWORD_MNEM_SUFFIX:
2468 i.suffix = mnem_p[-1];
2469 mnem_p[-1] = '\0';
2470 current_templates = hash_find (op_hash, mnemonic);
2471 break;
2472 case SHORT_MNEM_SUFFIX:
2473 case LONG_MNEM_SUFFIX:
2474 if (!intel_syntax)
2475 {
2476 i.suffix = mnem_p[-1];
2477 mnem_p[-1] = '\0';
2478 current_templates = hash_find (op_hash, mnemonic);
2479 }
2480 break;
252b5132 2481
29b0f896
AM		 2482 /* Intel Syntax. */
2483 case 'd':
2484 if (intel_syntax)
2485 {
9306ca4a 2486 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2487 i.suffix = SHORT_MNEM_SUFFIX;
2488 else
2489 i.suffix = LONG_MNEM_SUFFIX;
2490 mnem_p[-1] = '\0';
2491 current_templates = hash_find (op_hash, mnemonic);
2492 }
2493 break;
2494 }
2495 if (!current_templates)
2496 {
2497 as_bad (_("no such instruction: `%s'"), token_start);
2498 return NULL;
2499 }
2500 }
252b5132 2501
40fb9820
L		 2502 if (current_templates->start->opcode_modifier.jump
2503 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2504 {
2505 /* Check for a branch hint. We allow ",pt" and ",pn" for
2506 predict taken and predict not taken respectively.
2507 I'm not sure that branch hints actually do anything on loop
2508 and jcxz insns (JumpByte) for current Pentium4 chips. They
2509 may work in the future and it doesn't hurt to accept them
2510 now. */
2511 if (l[0] == ',' && l[1] == 'p')
2512 {
2513 if (l[2] == 't')
2514 {
2515 if (!add_prefix (DS_PREFIX_OPCODE))
2516 return NULL;
2517 l += 3;
2518 }
2519 else if (l[2] == 'n')
2520 {
2521 if (!add_prefix (CS_PREFIX_OPCODE))
2522 return NULL;
2523 l += 3;
2524 }
2525 }
2526 }
2527 /* Any other comma loses. */
2528 if (*l == ',')
2529 {
2530 as_bad (_("invalid character %s in mnemonic"),
2531 output_invalid (*l));
2532 return NULL;
2533 }
252b5132 2534
29b0f896 2535 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2536 supported = 0;
2537 for (t = current_templates->start; t < current_templates->end; ++t)
2538 {
40fb9820 2539 if (cpu_flags_match (t->cpu_flags))
64e74474 2540 supported |= 1;
c6fb90c8 2541 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2542 supported |= 2;
5c6af06e
JB		 2543 }
2544 if (!(supported & 2))
2545 {
2546 as_bad (flag_code == CODE_64BIT
2547 ? _("`%s' is not supported in 64-bit mode")
2548 : _("`%s' is only supported in 64-bit mode"),
2549 current_templates->start->name);
2550 return NULL;
2551 }
2552 if (!(supported & 1))
29b0f896 2553 {
5c6af06e
JB		 2554 as_warn (_("`%s' is not supported on `%s%s'"),
2555 current_templates->start->name,
2556 cpu_arch_name,
2557 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2558 }
40fb9820
L		 2559 else if (!cpu_arch_flags.bitfield.cpui386
2560 && (flag_code != CODE_16BIT))
29b0f896
AM		 2561 {
2562 as_warn (_("use .code16 to ensure correct addressing mode"));
2563 }
252b5132 2564
29b0f896 2565 /* Check for rep/repne without a string instruction. */
f41bbced 2566 if (expecting_string_instruction)
29b0f896 2567 {
f41bbced
JB		 2568 static templates override;
2569
2570 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2571 if (t->opcode_modifier.isstring)
f41bbced
JB		 2572 break;
2573 if (t >= current_templates->end)
2574 {
2575 as_bad (_("expecting string instruction after `%s'"),
64e74474 2576 expecting_string_instruction);
f41bbced
JB		 2577 return NULL;
2578 }
2579 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2580 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2581 break;
2582 override.end = t;
2583 current_templates = &override;
29b0f896 2584 }
252b5132 2585
29b0f896
AM		 2586 return l;
2587}
252b5132 2588
29b0f896 2589static char *
e3bb37b5 2590parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2591{
2592 char *token_start;
3138f287 2593
29b0f896
AM		 2594 /* 1 if operand is pending after ','. */
2595 unsigned int expecting_operand = 0;
252b5132 2596
29b0f896
AM		 2597 /* Non-zero if operand parens not balanced. */
2598 unsigned int paren_not_balanced;
2599
2600 while (*l != END_OF_INSN)
2601 {
2602 /* Skip optional white space before operand. */
2603 if (is_space_char (*l))
2604 ++l;
2605 if (!is_operand_char (*l) && *l != END_OF_INSN)
2606 {
2607 as_bad (_("invalid character %s before operand %d"),
2608 output_invalid (*l),
2609 i.operands + 1);
2610 return NULL;
2611 }
2612 token_start = l; /* after white space */
2613 paren_not_balanced = 0;
2614 while (paren_not_balanced || *l != ',')
2615 {
2616 if (*l == END_OF_INSN)
2617 {
2618 if (paren_not_balanced)
2619 {
2620 if (!intel_syntax)
2621 as_bad (_("unbalanced parenthesis in operand %d."),
2622 i.operands + 1);
2623 else
2624 as_bad (_("unbalanced brackets in operand %d."),
2625 i.operands + 1);
2626 return NULL;
2627 }
2628 else
2629 break; /* we are done */
2630 }
2631 else if (!is_operand_char (*l) && !is_space_char (*l))
2632 {
2633 as_bad (_("invalid character %s in operand %d"),
2634 output_invalid (*l),
2635 i.operands + 1);
2636 return NULL;
2637 }
2638 if (!intel_syntax)
2639 {
2640 if (*l == '(')
2641 ++paren_not_balanced;
2642 if (*l == ')')
2643 --paren_not_balanced;
2644 }
2645 else
2646 {
2647 if (*l == '[')
2648 ++paren_not_balanced;
2649 if (*l == ']')
2650 --paren_not_balanced;
2651 }
2652 l++;
2653 }
2654 if (l != token_start)
2655 { /* Yes, we've read in another operand. */
2656 unsigned int operand_ok;
2657 this_operand = i.operands++;
2658 if (i.operands > MAX_OPERANDS)
2659 {
2660 as_bad (_("spurious operands; (%d operands/instruction max)"),
2661 MAX_OPERANDS);
2662 return NULL;
2663 }
2664 /* Now parse operand adding info to 'i' as we go along. */
2665 END_STRING_AND_SAVE (l);
2666
2667 if (intel_syntax)
2668 operand_ok =
2669 i386_intel_operand (token_start,
2670 intel_float_operand (mnemonic));
2671 else
2672 operand_ok = i386_operand (token_start);
2673
2674 RESTORE_END_STRING (l);
2675 if (!operand_ok)
2676 return NULL;
2677 }
2678 else
2679 {
2680 if (expecting_operand)
2681 {
2682 expecting_operand_after_comma:
2683 as_bad (_("expecting operand after ','; got nothing"));
2684 return NULL;
2685 }
2686 if (*l == ',')
2687 {
2688 as_bad (_("expecting operand before ','; got nothing"));
2689 return NULL;
2690 }
2691 }
7f3f1ea2 2692
29b0f896
AM		 2693 /* Now *l must be either ',' or END_OF_INSN. */
2694 if (*l == ',')
2695 {
2696 if (*++l == END_OF_INSN)
2697 {
2698 /* Just skip it, if it's \n complain. */
2699 goto expecting_operand_after_comma;
2700 }
2701 expecting_operand = 1;
2702 }
2703 }
2704 return l;
2705}
7f3f1ea2 2706
050dfa73 2707static void
4d456e3d 2708swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2709{
2710 union i386_op temp_op;
40fb9820 2711 i386_operand_type temp_type;
050dfa73 2712 enum bfd_reloc_code_real temp_reloc;
4eed87de 2713
050dfa73
MM		 2714 temp_type = i.types[xchg2];
2715 i.types[xchg2] = i.types[xchg1];
2716 i.types[xchg1] = temp_type;
2717 temp_op = i.op[xchg2];
2718 i.op[xchg2] = i.op[xchg1];
2719 i.op[xchg1] = temp_op;
2720 temp_reloc = i.reloc[xchg2];
2721 i.reloc[xchg2] = i.reloc[xchg1];
2722 i.reloc[xchg1] = temp_reloc;
2723}
2724
29b0f896 2725static void
e3bb37b5 2726swap_operands (void)
29b0f896 2727{
b7c61d9a 2728 switch (i.operands)
050dfa73 2729 {
b7c61d9a 2730 case 4:
4d456e3d 2731 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2732 case 3:
2733 case 2:
4d456e3d 2734 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2735 break;
2736 default:
2737 abort ();
29b0f896 2738 }
29b0f896
AM		 2739
2740 if (i.mem_operands == 2)
2741 {
2742 const seg_entry *temp_seg;
2743 temp_seg = i.seg[0];
2744 i.seg[0] = i.seg[1];
2745 i.seg[1] = temp_seg;
2746 }
2747}
252b5132 2748
29b0f896
AM		 2749/* Try to ensure constant immediates are represented in the smallest
2750 opcode possible. */
2751static void
e3bb37b5 2752optimize_imm (void)
29b0f896
AM		 2753{
2754 char guess_suffix = 0;
2755 int op;
252b5132 2756
29b0f896
AM		 2757 if (i.suffix)
2758 guess_suffix = i.suffix;
2759 else if (i.reg_operands)
2760 {
2761 /* Figure out a suffix from the last register operand specified.
2762 We can't do this properly yet, ie. excluding InOutPortReg,
2763 but the following works for instructions with immediates.
2764 In any case, we can't set i.suffix yet. */
2765 for (op = i.operands; --op >= 0;)
40fb9820
L		 2766 if (i.types[op].bitfield.reg8)
2767 {
2768 guess_suffix = BYTE_MNEM_SUFFIX;
2769 break;
2770 }
2771 else if (i.types[op].bitfield.reg16)
252b5132 2772 {
40fb9820
L		 2773 guess_suffix = WORD_MNEM_SUFFIX;
2774 break;
2775 }
2776 else if (i.types[op].bitfield.reg32)
2777 {
2778 guess_suffix = LONG_MNEM_SUFFIX;
2779 break;
2780 }
2781 else if (i.types[op].bitfield.reg64)
2782 {
2783 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2784 break;
252b5132 2785 }
29b0f896
AM		 2786 }
2787 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2788 guess_suffix = WORD_MNEM_SUFFIX;
2789
2790 for (op = i.operands; --op >= 0;)
40fb9820 2791 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2792 {
2793 switch (i.op[op].imms->X_op)
252b5132 2794 {
29b0f896
AM		 2795 case O_constant:
2796 /* If a suffix is given, this operand may be shortened. */
2797 switch (guess_suffix)
252b5132 2798 {
29b0f896 2799 case LONG_MNEM_SUFFIX:
40fb9820
L		 2800 i.types[op].bitfield.imm32 = 1;
2801 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2802 break;
2803 case WORD_MNEM_SUFFIX:
40fb9820
L		 2804 i.types[op].bitfield.imm16 = 1;
2805 i.types[op].bitfield.imm32 = 1;
2806 i.types[op].bitfield.imm32s = 1;
2807 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2808 break;
2809 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2810 i.types[op].bitfield.imm8 = 1;
2811 i.types[op].bitfield.imm8s = 1;
2812 i.types[op].bitfield.imm16 = 1;
2813 i.types[op].bitfield.imm32 = 1;
2814 i.types[op].bitfield.imm32s = 1;
2815 i.types[op].bitfield.imm64 = 1;
29b0f896 2816 break;
252b5132 2817 }
252b5132 2818
29b0f896
AM		 2819 /* If this operand is at most 16 bits, convert it
2820 to a signed 16 bit number before trying to see
2821 whether it will fit in an even smaller size.
2822 This allows a 16-bit operand such as $0xffe0 to
2823 be recognised as within Imm8S range. */
40fb9820 2824 if ((i.types[op].bitfield.imm16)
29b0f896 2825 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2826 {
29b0f896
AM		 2827 i.op[op].imms->X_add_number =
2828 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2829 }
40fb9820 2830 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2831 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2832 == 0))
2833 {
2834 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2835 ^ ((offsetT) 1 << 31))
2836 - ((offsetT) 1 << 31));
2837 }
40fb9820 2838 i.types[op]
c6fb90c8
L		 2839 = operand_type_or (i.types[op],
2840 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2841
29b0f896
AM		 2842 /* We must avoid matching of Imm32 templates when 64bit
2843 only immediate is available. */
2844 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2845 i.types[op].bitfield.imm32 = 0;
29b0f896 2846 break;
252b5132 2847
29b0f896
AM		 2848 case O_absent:
2849 case O_register:
2850 abort ();
2851
2852 /* Symbols and expressions. */
2853 default:
9cd96992
JB		 2854 /* Convert symbolic operand to proper sizes for matching, but don't
2855 prevent matching a set of insns that only supports sizes other
2856 than those matching the insn suffix. */
2857 {
40fb9820 2858 i386_operand_type mask, allowed;
9cd96992
JB		 2859 const template *t;
2860
c6fb90c8
L		 2861 UINTS_CLEAR (mask);
2862 UINTS_CLEAR (allowed);
40fb9820 2863
4eed87de
AM		 2864 for (t = current_templates->start;
2865 t < current_templates->end;
2866 ++t)
c6fb90c8
L		 2867 allowed = operand_type_or (allowed,
2868 t->operand_types[op]);
9cd96992
JB		 2869 switch (guess_suffix)
2870 {
2871 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2872 mask.bitfield.imm64 = 1;
2873 mask.bitfield.imm32s = 1;
9cd96992
JB		 2874 break;
2875 case LONG_MNEM_SUFFIX:
40fb9820 2876 mask.bitfield.imm32 = 1;
9cd96992
JB		 2877 break;
2878 case WORD_MNEM_SUFFIX:
40fb9820 2879 mask.bitfield.imm16 = 1;
9cd96992
JB		 2880 break;
2881 case BYTE_MNEM_SUFFIX:
40fb9820 2882 mask.bitfield.imm8 = 1;
9cd96992
JB		 2883 break;
2884 default:
9cd96992
JB		 2885 break;
2886 }
c6fb90c8
L		 2887 allowed = operand_type_and (mask, allowed);
2888 if (!UINTS_ALL_ZERO (allowed))
2889 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2890 }
29b0f896 2891 break;
252b5132 2892 }
29b0f896
AM		 2893 }
2894}
47926f60 2895
29b0f896
AM		 2896/* Try to use the smallest displacement type too. */
2897static void
e3bb37b5 2898optimize_disp (void)
29b0f896
AM		 2899{
2900 int op;
3e73aa7c 2901
29b0f896 2902 for (op = i.operands; --op >= 0;)
40fb9820 2903 if (operand_type_check (i.types[op], disp))
252b5132 2904 {
b300c311 2905 if (i.op[op].disps->X_op == O_constant)
252b5132 2906 {
b300c311 2907 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2908
40fb9820 2909 if (i.types[op].bitfield.disp16
b300c311
L		 2910 && (disp & ~(offsetT) 0xffff) == 0)
2911 {
2912 /* If this operand is at most 16 bits, convert
2913 to a signed 16 bit number and don't use 64bit
2914 displacement. */
2915 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2916 i.types[op].bitfield.disp64 = 0;
b300c311 2917 }
40fb9820 2918 if (i.types[op].bitfield.disp32
b300c311
L		 2919 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2920 {
2921 /* If this operand is at most 32 bits, convert
2922 to a signed 32 bit number and don't use 64bit
2923 displacement. */
2924 disp &= (((offsetT) 2 << 31) - 1);
2925 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2926 i.types[op].bitfield.disp64 = 0;
b300c311 2927 }
40fb9820 2928 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2929 {
40fb9820
L		 2930 i.types[op].bitfield.disp8 = 0;
2931 i.types[op].bitfield.disp16 = 0;
2932 i.types[op].bitfield.disp32 = 0;
2933 i.types[op].bitfield.disp32s = 0;
2934 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2935 i.op[op].disps = 0;
2936 i.disp_operands--;
2937 }
2938 else if (flag_code == CODE_64BIT)
2939 {
2940 if (fits_in_signed_long (disp))
28a9d8f5 2941 {
40fb9820
L		 2942 i.types[op].bitfield.disp64 = 0;
2943 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2944 }
b300c311 2945 if (fits_in_unsigned_long (disp))
40fb9820 2946 i.types[op].bitfield.disp32 = 1;
b300c311 2947 }
40fb9820
L		 2948 if ((i.types[op].bitfield.disp32
2949 || i.types[op].bitfield.disp32s
2950 || i.types[op].bitfield.disp16)
b300c311 2951 && fits_in_signed_byte (disp))
40fb9820 2952 i.types[op].bitfield.disp8 = 1;
252b5132 2953 }
67a4f2b7
AO		 2954 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2955 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2956 {
2957 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2958 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2959 i.types[op].bitfield.disp8 = 0;
2960 i.types[op].bitfield.disp16 = 0;
2961 i.types[op].bitfield.disp32 = 0;
2962 i.types[op].bitfield.disp32s = 0;
2963 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2964 }
2965 else
b300c311 2966 /* We only support 64bit displacement on constants. */
40fb9820 2967 i.types[op].bitfield.disp64 = 0;
252b5132 2968 }
29b0f896
AM		 2969}
2970
2971static int
e3bb37b5 2972match_template (void)
29b0f896
AM		 2973{
2974 /* Points to template once we've found it. */
2975 const template *t;
40fb9820 2976 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2977 unsigned int found_reverse_match;
40fb9820
L		 2978 i386_opcode_modifier suffix_check;
2979 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2980 int addr_prefix_disp;
a5c311ca 2981 unsigned int j;
c6fb90c8 2982 i386_cpu_flags overlap;
29b0f896 2983
f48ff2ae
L		 2984#if MAX_OPERANDS != 4
2985# error "MAX_OPERANDS must be 4."
2986#endif
2987
29b0f896 2988 found_reverse_match = 0;
539e75ad 2989 addr_prefix_disp = -1;
40fb9820
L		 2990
2991 memset (&suffix_check, 0, sizeof (suffix_check));
2992 if (i.suffix == BYTE_MNEM_SUFFIX)
2993 suffix_check.no_bsuf = 1;
2994 else if (i.suffix == WORD_MNEM_SUFFIX)
2995 suffix_check.no_wsuf = 1;
2996 else if (i.suffix == SHORT_MNEM_SUFFIX)
2997 suffix_check.no_ssuf = 1;
2998 else if (i.suffix == LONG_MNEM_SUFFIX)
2999 suffix_check.no_lsuf = 1;
3000 else if (i.suffix == QWORD_MNEM_SUFFIX)
3001 suffix_check.no_qsuf = 1;
3002 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3003 suffix_check.no_ldsuf = 1;
29b0f896 3004
45aa61fe 3005 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3006 {
539e75ad
L		 3007 addr_prefix_disp = -1;
3008
29b0f896
AM		 3009 /* Must have right number of operands. */
3010 if (i.operands != t->operands)
3011 continue;
3012
20592a94 3013 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3014 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3015 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3016 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3017 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3018 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3019 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3020 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3021 continue;
3022
a5c311ca
L		 3023 for (j = 0; j < MAX_OPERANDS; j++)
3024 operand_types [j] = t->operand_types [j];
539e75ad 3025
45aa61fe
AM		 3026 /* In general, don't allow 64-bit operands in 32-bit mode. */
3027 if (i.suffix == QWORD_MNEM_SUFFIX
3028 && flag_code != CODE_64BIT
3029 && (intel_syntax
40fb9820 3030 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3031 && !intel_float_operand (t->name))
3032 : intel_float_operand (t->name) != 2)
40fb9820
L		 3033 && ((!operand_types[0].bitfield.regmmx
3034 && !operand_types[0].bitfield.regxmm)
3035 || (!operand_types[t->operands > 1].bitfield.regmmx
3036 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3037 && (t->base_opcode != 0x0fc7
3038 || t->extension_opcode != 1 /* cmpxchg8b */))
3039 continue;
3040
29b0f896 3041 /* Do not verify operands when there are none. */
c6fb90c8 3042 else
29b0f896 3043 {
c6fb90c8
L		 3044 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3045 if (!t->operands)
3046 {
3047 if (!UINTS_ALL_ZERO (overlap))
3048 continue;
3049 /* We've found a match; break out of loop. */
3050 break;
3051 }
29b0f896 3052 }
252b5132 3053
539e75ad
L		 3054 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3055 into Disp32/Disp16/Disp32 operand. */
3056 if (i.prefix[ADDR_PREFIX] != 0)
3057 {
40fb9820 3058 /* There should be only one Disp operand. */
539e75ad
L		 3059 switch (flag_code)
3060 {
3061 case CODE_16BIT:
40fb9820
L		 3062 for (j = 0; j < MAX_OPERANDS; j++)
3063 {
3064 if (operand_types[j].bitfield.disp16)
3065 {
3066 addr_prefix_disp = j;
3067 operand_types[j].bitfield.disp32 = 1;
3068 operand_types[j].bitfield.disp16 = 0;
3069 break;
3070 }
3071 }
539e75ad
L		 3072 break;
3073 case CODE_32BIT:
40fb9820
L		 3074 for (j = 0; j < MAX_OPERANDS; j++)
3075 {
3076 if (operand_types[j].bitfield.disp32)
3077 {
3078 addr_prefix_disp = j;
3079 operand_types[j].bitfield.disp32 = 0;
3080 operand_types[j].bitfield.disp16 = 1;
3081 break;
3082 }
3083 }
539e75ad
L		 3084 break;
3085 case CODE_64BIT:
40fb9820
L		 3086 for (j = 0; j < MAX_OPERANDS; j++)
3087 {
3088 if (operand_types[j].bitfield.disp64)
3089 {
3090 addr_prefix_disp = j;
3091 operand_types[j].bitfield.disp64 = 0;
3092 operand_types[j].bitfield.disp32 = 1;
3093 break;
3094 }
3095 }
539e75ad
L		 3096 break;
3097 }
539e75ad
L		 3098 }
3099
c6fb90c8 3100 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3101 switch (t->operands)
3102 {
3103 case 1:
40fb9820 3104 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3105 continue;
3106 break;
3107 case 2:
8b38ad71
L		 3108 /* xchg %eax, %eax is a special case. It is an aliase for nop
3109 only in 32bit mode and we can use opcode 0x90. In 64bit
3110 mode, we can't use 0x90 for xchg %eax, %eax since it should
3111 zero-extend %eax to %rax. */
3112 if (flag_code == CODE_64BIT
3113 && t->base_opcode == 0x90
c6fb90c8
L		 3114 && UINTS_EQUAL (i.types [0], acc32)
3115 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3116 continue;
29b0f896 3117 case 3:
f48ff2ae 3118 case 4:
c6fb90c8 3119 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3120 if (!operand_type_match (overlap0, i.types[0])
3121 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3122 /* monitor in SSE3 is a very special case. The first
708587a4 3123 register and the second register may have different
26186d74
L		 3124 sizes. The same applies to crc32 in SSE4.2. It is
3125 also true for invlpga, vmload, vmrun and vmsave in
3126 SVME. */
cb712a9e 3127 || !((t->base_opcode == 0x0f01
26186d74
L		 3128 && (t->extension_opcode == 0xc8
3129 || t->extension_opcode == 0xd8
3130 || t->extension_opcode == 0xda
3131 || t->extension_opcode == 0xdb
3132 || t->extension_opcode == 0xdf))
381d071f 3133 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3134 || operand_type_register_match (overlap0, i.types[0],
3135 operand_types[0],
3136 overlap1, i.types[1],
3137 operand_types[1])))
29b0f896
AM		 3138 {
3139 /* Check if other direction is valid ... */
40fb9820 3140 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3141 continue;
3142
3143 /* Try reversing direction of operands. */
c6fb90c8
L		 3144 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3145 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3146 if (!operand_type_match (overlap0, i.types[0])
3147 || !operand_type_match (overlap1, i.types[1])
3148 || !operand_type_register_match (overlap0, i.types[0],
3149 operand_types[1],
3150 overlap1, i.types[1],
3151 operand_types[0]))
29b0f896
AM		 3152 {
3153 /* Does not match either direction. */
3154 continue;
3155 }
3156 /* found_reverse_match holds which of D or FloatDR
3157 we've found. */
40fb9820 3158 if (t->opcode_modifier.d)
8a2ed489 3159 found_reverse_match = Opcode_D;
40fb9820 3160 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3161 found_reverse_match = Opcode_FloatD;
3162 else
3163 found_reverse_match = 0;
40fb9820 3164 if (t->opcode_modifier.floatr)
8a2ed489 3165 found_reverse_match |= Opcode_FloatR;
29b0f896 3166 }
f48ff2ae 3167 else
29b0f896 3168 {
f48ff2ae 3169 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3170 switch (t->operands)
3171 {
3172 case 4:
c6fb90c8
L		 3173 overlap3 = operand_type_and (i.types[3],
3174 operand_types[3]);
d1cbb4db 3175 case 3:
c6fb90c8
L		 3176 overlap2 = operand_type_and (i.types[2],
3177 operand_types[2]);
d1cbb4db
L		 3178 break;
3179 }
29b0f896 3180
f48ff2ae
L		 3181 switch (t->operands)
3182 {
3183 case 4:
40fb9820
L		 3184 if (!operand_type_match (overlap3, i.types[3])
3185 || !operand_type_register_match (overlap2,
3186 i.types[2],
3187 operand_types[2],
3188 overlap3,
3189 i.types[3],
3190 operand_types[3]))
f48ff2ae
L		 3191 continue;
3192 case 3:
3193 /* Here we make use of the fact that there are no
3194 reverse match 3 operand instructions, and all 3
3195 operand instructions only need to be checked for
3196 register consistency between operands 2 and 3. */
40fb9820
L		 3197 if (!operand_type_match (overlap2, i.types[2])
3198 || !operand_type_register_match (overlap1,
3199 i.types[1],
3200 operand_types[1],
3201 overlap2,
3202 i.types[2],
3203 operand_types[2]))
f48ff2ae
L		 3204 continue;
3205 break;
3206 }
29b0f896 3207 }
f48ff2ae 3208 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3209 slip through to break. */
3210 }
c6fb90c8 3211 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3212 {
3213 found_reverse_match = 0;
3214 continue;
3215 }
3216 /* We've found a match; break out of loop. */
3217 break;
3218 }
3219
3220 if (t == current_templates->end)
3221 {
3222 /* We found no match. */
3223 as_bad (_("suffix or operands invalid for `%s'"),
3224 current_templates->start->name);
3225 return 0;
3226 }
252b5132 3227
29b0f896
AM		 3228 if (!quiet_warnings)
3229 {
3230 if (!intel_syntax
40fb9820
L		 3231 && (i.types[0].bitfield.jumpabsolute
3232 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3233 {
3234 as_warn (_("indirect %s without `*'"), t->name);
3235 }
3236
40fb9820
L		 3237 if (t->opcode_modifier.isprefix
3238 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3239 {
3240 /* Warn them that a data or address size prefix doesn't
3241 affect assembly of the next line of code. */
3242 as_warn (_("stand-alone `%s' prefix"), t->name);
3243 }
3244 }
3245
3246 /* Copy the template we found. */
3247 i.tm = *t;
539e75ad
L		 3248
3249 if (addr_prefix_disp != -1)
3250 i.tm.operand_types[addr_prefix_disp]
3251 = operand_types[addr_prefix_disp];
3252
29b0f896
AM		 3253 if (found_reverse_match)
3254 {
3255 /* If we found a reverse match we must alter the opcode
3256 direction bit. found_reverse_match holds bits to change
3257 (different for int & float insns). */
3258
3259 i.tm.base_opcode ^= found_reverse_match;
3260
539e75ad
L		 3261 i.tm.operand_types[0] = operand_types[1];
3262 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3263 }
3264
3265 return 1;
3266}
3267
3268static int
e3bb37b5 3269check_string (void)
29b0f896 3270{
40fb9820
L		 3271 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3272 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3273 {
3274 if (i.seg[0] != NULL && i.seg[0] != &es)
3275 {
3276 as_bad (_("`%s' operand %d must use `%%es' segment"),
3277 i.tm.name,
3278 mem_op + 1);
3279 return 0;
3280 }
3281 /* There's only ever one segment override allowed per instruction.
3282 This instruction possibly has a legal segment override on the
3283 second operand, so copy the segment to where non-string
3284 instructions store it, allowing common code. */
3285 i.seg[0] = i.seg[1];
3286 }
40fb9820 3287 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3288 {
3289 if (i.seg[1] != NULL && i.seg[1] != &es)
3290 {
3291 as_bad (_("`%s' operand %d must use `%%es' segment"),
3292 i.tm.name,
3293 mem_op + 2);
3294 return 0;
3295 }
3296 }
3297 return 1;
3298}
3299
3300static int
543613e9 3301process_suffix (void)
29b0f896
AM		 3302{
3303 /* If matched instruction specifies an explicit instruction mnemonic
3304 suffix, use it. */
40fb9820
L		 3305 if (i.tm.opcode_modifier.size16)
3306 i.suffix = WORD_MNEM_SUFFIX;
3307 else if (i.tm.opcode_modifier.size32)
3308 i.suffix = LONG_MNEM_SUFFIX;
3309 else if (i.tm.opcode_modifier.size64)
3310 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3311 else if (i.reg_operands)
3312 {
3313 /* If there's no instruction mnemonic suffix we try to invent one
3314 based on register operands. */
3315 if (!i.suffix)
3316 {
3317 /* We take i.suffix from the last register operand specified,
3318 Destination register type is more significant than source
381d071f
L		 3319 register type. crc32 in SSE4.2 prefers source register
3320 type. */
3321 if (i.tm.base_opcode == 0xf20f38f1)
3322 {
40fb9820
L		 3323 if (i.types[0].bitfield.reg16)
3324 i.suffix = WORD_MNEM_SUFFIX;
3325 else if (i.types[0].bitfield.reg32)
3326 i.suffix = LONG_MNEM_SUFFIX;
3327 else if (i.types[0].bitfield.reg64)
3328 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3329 }
9344ff29 3330 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3331 {
40fb9820 3332 if (i.types[0].bitfield.reg8)
20592a94
L		 3333 i.suffix = BYTE_MNEM_SUFFIX;
3334 }
381d071f
L		 3335
3336 if (!i.suffix)
3337 {
3338 int op;
3339
20592a94
L		 3340 if (i.tm.base_opcode == 0xf20f38f1
3341 || i.tm.base_opcode == 0xf20f38f0)
3342 {
3343 /* We have to know the operand size for crc32. */
3344 as_bad (_("ambiguous memory operand size for `%s`"),
3345 i.tm.name);
3346 return 0;
3347 }
3348
381d071f 3349 for (op = i.operands; --op >= 0;)
40fb9820 3350 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3351 {
40fb9820
L		 3352 if (i.types[op].bitfield.reg8)
3353 {
3354 i.suffix = BYTE_MNEM_SUFFIX;
3355 break;
3356 }
3357 else if (i.types[op].bitfield.reg16)
3358 {
3359 i.suffix = WORD_MNEM_SUFFIX;
3360 break;
3361 }
3362 else if (i.types[op].bitfield.reg32)
3363 {
3364 i.suffix = LONG_MNEM_SUFFIX;
3365 break;
3366 }
3367 else if (i.types[op].bitfield.reg64)
3368 {
3369 i.suffix = QWORD_MNEM_SUFFIX;
3370 break;
3371 }
381d071f
L		 3372 }
3373 }
29b0f896
AM		 3374 }
3375 else if (i.suffix == BYTE_MNEM_SUFFIX)
3376 {
3377 if (!check_byte_reg ())
3378 return 0;
3379 }
3380 else if (i.suffix == LONG_MNEM_SUFFIX)
3381 {
3382 if (!check_long_reg ())
3383 return 0;
3384 }
3385 else if (i.suffix == QWORD_MNEM_SUFFIX)
3386 {
955e1e6a
L		 3387 if (intel_syntax
3388 && i.tm.opcode_modifier.ignoresize
3389 && i.tm.opcode_modifier.no_qsuf)
3390 i.suffix = 0;
3391 else if (!check_qword_reg ())
29b0f896
AM		 3392 return 0;
3393 }
3394 else if (i.suffix == WORD_MNEM_SUFFIX)
3395 {
3396 if (!check_word_reg ())
3397 return 0;
3398 }
40fb9820 3399 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3400 /* Do nothing if the instruction is going to ignore the prefix. */
3401 ;
3402 else
3403 abort ();
3404 }
40fb9820 3405 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3406 && !i.suffix
3407 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3408 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3409 {
3410 i.suffix = stackop_size;
3411 }
9306ca4a
JB		 3412 else if (intel_syntax
3413 && !i.suffix
40fb9820
L		 3414 && (i.tm.operand_types[0].bitfield.jumpabsolute
3415 || i.tm.opcode_modifier.jumpbyte
3416 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3417 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3418 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3419 {
3420 switch (flag_code)
3421 {
3422 case CODE_64BIT:
40fb9820 3423 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3424 {
3425 i.suffix = QWORD_MNEM_SUFFIX;
3426 break;
3427 }
3428 case CODE_32BIT:
40fb9820 3429 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3430 i.suffix = LONG_MNEM_SUFFIX;
3431 break;
3432 case CODE_16BIT:
40fb9820 3433 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3434 i.suffix = WORD_MNEM_SUFFIX;
3435 break;
3436 }
3437 }
252b5132 3438
9306ca4a 3439 if (!i.suffix)
29b0f896 3440 {
9306ca4a
JB		 3441 if (!intel_syntax)
3442 {
40fb9820 3443 if (i.tm.opcode_modifier.w)
9306ca4a 3444 {
4eed87de
AM		 3445 as_bad (_("no instruction mnemonic suffix given and "
3446 "no register operands; can't size instruction"));
9306ca4a
JB		 3447 return 0;
3448 }
3449 }
3450 else
3451 {
40fb9820
L		 3452 unsigned int suffixes;
3453
3454 suffixes = !i.tm.opcode_modifier.no_bsuf;
3455 if (!i.tm.opcode_modifier.no_wsuf)
3456 suffixes |= 1 << 1;
3457 if (!i.tm.opcode_modifier.no_lsuf)
3458 suffixes |= 1 << 2;
3459 if (!i.tm.opcode_modifier.no_lsuf)
3460 suffixes |= 1 << 3;
3461 if (!i.tm.opcode_modifier.no_ssuf)
3462 suffixes |= 1 << 4;
3463 if (!i.tm.opcode_modifier.no_qsuf)
3464 suffixes |= 1 << 5;
3465
3466 /* There are more than suffix matches. */
3467 if (i.tm.opcode_modifier.w
9306ca4a 3468 || ((suffixes & (suffixes - 1))
40fb9820
L		 3469 && !i.tm.opcode_modifier.defaultsize
3470 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3471 {
3472 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3473 return 0;
3474 }
3475 }
29b0f896 3476 }
252b5132 3477
9306ca4a
JB		 3478 /* Change the opcode based on the operand size given by i.suffix;
3479 We don't need to change things for byte insns. */
3480
29b0f896
AM		 3481 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3482 {
3483 /* It's not a byte, select word/dword operation. */
40fb9820 3484 if (i.tm.opcode_modifier.w)
29b0f896 3485 {
40fb9820 3486 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3487 i.tm.base_opcode |= 8;
3488 else
3489 i.tm.base_opcode |= 1;
3490 }
0f3f3d8b 3491
29b0f896
AM		 3492 /* Now select between word & dword operations via the operand
3493 size prefix, except for instructions that will ignore this
3494 prefix anyway. */
ca61edf2 3495 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3496 {
ca61edf2
L		 3497 /* The address size override prefix changes the size of the
3498 first operand. */
40fb9820
L		 3499 if ((flag_code == CODE_32BIT
3500 && i.op->regs[0].reg_type.bitfield.reg16)
3501 || (flag_code != CODE_32BIT
3502 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3503 if (!add_prefix (ADDR_PREFIX_OPCODE))
3504 return 0;
3505 }
3506 else if (i.suffix != QWORD_MNEM_SUFFIX
3507 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3508 && !i.tm.opcode_modifier.ignoresize
3509 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3510 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3511 || (flag_code == CODE_64BIT
40fb9820 3512 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3513 {
3514 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3515
40fb9820 3516 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3517 prefix = ADDR_PREFIX_OPCODE;
252b5132 3518
29b0f896
AM		 3519 if (!add_prefix (prefix))
3520 return 0;
24eab124 3521 }
252b5132 3522
29b0f896
AM		 3523 /* Set mode64 for an operand. */
3524 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3525 && flag_code == CODE_64BIT
40fb9820 3526 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3527 {
3528 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3529 need rex64. cmpxchg8b is also a special case. */
3530 if (! (i.operands == 2
3531 && i.tm.base_opcode == 0x90
3532 && i.tm.extension_opcode == None
c6fb90c8
L		 3533 && UINTS_EQUAL (i.types [0], acc64)
3534 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3535 && ! (i.operands == 1
3536 && i.tm.base_opcode == 0xfc7
3537 && i.tm.extension_opcode == 1
40fb9820
L		 3538 && !operand_type_check (i.types [0], reg)
3539 && operand_type_check (i.types [0], anymem)))
f6bee062 3540 i.rex |= REX_W;
46e883c5 3541 }
3e73aa7c 3542
29b0f896
AM		 3543 /* Size floating point instruction. */
3544 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3545 if (i.tm.opcode_modifier.floatmf)
543613e9 3546 i.tm.base_opcode ^= 4;
29b0f896 3547 }
7ecd2f8b 3548
29b0f896
AM		 3549 return 1;
3550}
3e73aa7c 3551
29b0f896 3552static int
543613e9 3553check_byte_reg (void)
29b0f896
AM		 3554{
3555 int op;
543613e9 3556
29b0f896
AM		 3557 for (op = i.operands; --op >= 0;)
3558 {
3559 /* If this is an eight bit register, it's OK. If it's the 16 or
3560 32 bit version of an eight bit register, we will just use the
3561 low portion, and that's OK too. */
40fb9820 3562 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3563 continue;
3564
ca61edf2
L		 3565 /* Don't generate this warning if not needed. */
3566 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3567 continue;
3568
9344ff29
L		 3569 /* crc32 doesn't generate this warning. */
3570 if (i.tm.base_opcode == 0xf20f38f0)
3571 continue;
3572
40fb9820
L		 3573 if ((i.types[op].bitfield.reg16
3574 || i.types[op].bitfield.reg32
3575 || i.types[op].bitfield.reg64)
3576 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3577 {
3578 /* Prohibit these changes in the 64bit mode, since the
3579 lowering is more complicated. */
3580 if (flag_code == CODE_64BIT
40fb9820 3581 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3582 {
2ca3ace5
L		 3583 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3584 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3585 i.suffix);
3586 return 0;
3587 }
3588#if REGISTER_WARNINGS
3589 if (!quiet_warnings
40fb9820 3590 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3591 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3592 register_prefix,
40fb9820 3593 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3594 ? REGNAM_AL - REGNAM_AX
3595 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3596 register_prefix,
29b0f896
AM		 3597 i.op[op].regs->reg_name,
3598 i.suffix);
3599#endif
3600 continue;
3601 }
3602 /* Any other register is bad. */
40fb9820
L		 3603 if (i.types[op].bitfield.reg16
3604 || i.types[op].bitfield.reg32
3605 || i.types[op].bitfield.reg64
3606 || i.types[op].bitfield.regmmx
3607 || i.types[op].bitfield.regxmm
3608 || i.types[op].bitfield.sreg2
3609 || i.types[op].bitfield.sreg3
3610 || i.types[op].bitfield.control
3611 || i.types[op].bitfield.debug
3612 || i.types[op].bitfield.test
3613 || i.types[op].bitfield.floatreg
3614 || i.types[op].bitfield.floatacc)
29b0f896 3615 {
a540244d
L		 3616 as_bad (_("`%s%s' not allowed with `%s%c'"),
3617 register_prefix,
29b0f896
AM		 3618 i.op[op].regs->reg_name,
3619 i.tm.name,
3620 i.suffix);
3621 return 0;
3622 }
3623 }
3624 return 1;
3625}
3626
3627static int
e3bb37b5 3628check_long_reg (void)
29b0f896
AM		 3629{
3630 int op;
3631
3632 for (op = i.operands; --op >= 0;)
3633 /* Reject eight bit registers, except where the template requires
3634 them. (eg. movzb) */
40fb9820
L		 3635 if (i.types[op].bitfield.reg8
3636 && (i.tm.operand_types[op].bitfield.reg16
3637 || i.tm.operand_types[op].bitfield.reg32
3638 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3639 {
a540244d
L		 3640 as_bad (_("`%s%s' not allowed with `%s%c'"),
3641 register_prefix,
29b0f896
AM		 3642 i.op[op].regs->reg_name,
3643 i.tm.name,
3644 i.suffix);
3645 return 0;
3646 }
3647 /* Warn if the e prefix on a general reg is missing. */
3648 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3649 && i.types[op].bitfield.reg16
3650 && (i.tm.operand_types[op].bitfield.reg32
3651 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3652 {
3653 /* Prohibit these changes in the 64bit mode, since the
3654 lowering is more complicated. */
3655 if (flag_code == CODE_64BIT)
252b5132 3656 {
2ca3ace5
L		 3657 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3658 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3659 i.suffix);
3660 return 0;
252b5132 3661 }
29b0f896
AM		 3662#if REGISTER_WARNINGS
3663 else
a540244d
L		 3664 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3665 register_prefix,
29b0f896 3666 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3667 register_prefix,
29b0f896
AM		 3668 i.op[op].regs->reg_name,
3669 i.suffix);
3670#endif
252b5132 3671 }
29b0f896 3672 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3673 else if (i.types[op].bitfield.reg64
3674 && (i.tm.operand_types[op].bitfield.reg32
3675 || i.tm.operand_types[op].bitfield.acc))
252b5132 3676 {
34828aad 3677 if (intel_syntax
ca61edf2 3678 && i.tm.opcode_modifier.toqword
40fb9820 3679 && !i.types[0].bitfield.regxmm)
34828aad 3680 {
ca61edf2 3681 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3682 i.suffix = QWORD_MNEM_SUFFIX;
3683 }
3684 else
3685 {
3686 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3687 register_prefix, i.op[op].regs->reg_name,
3688 i.suffix);
3689 return 0;
3690 }
29b0f896
AM		 3691 }
3692 return 1;
3693}
252b5132 3694
29b0f896 3695static int
e3bb37b5 3696check_qword_reg (void)
29b0f896
AM		 3697{
3698 int op;
252b5132 3699
29b0f896
AM		 3700 for (op = i.operands; --op >= 0; )
3701 /* Reject eight bit registers, except where the template requires
3702 them. (eg. movzb) */
40fb9820
L		 3703 if (i.types[op].bitfield.reg8
3704 && (i.tm.operand_types[op].bitfield.reg16
3705 || i.tm.operand_types[op].bitfield.reg32
3706 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3707 {
a540244d
L		 3708 as_bad (_("`%s%s' not allowed with `%s%c'"),
3709 register_prefix,
29b0f896
AM		 3710 i.op[op].regs->reg_name,
3711 i.tm.name,
3712 i.suffix);
3713 return 0;
3714 }
3715 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3716 else if ((i.types[op].bitfield.reg16
3717 || i.types[op].bitfield.reg32)
3718 && (i.tm.operand_types[op].bitfield.reg32
3719 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3720 {
3721 /* Prohibit these changes in the 64bit mode, since the
3722 lowering is more complicated. */
34828aad 3723 if (intel_syntax
ca61edf2 3724 && i.tm.opcode_modifier.todword
40fb9820 3725 && !i.types[0].bitfield.regxmm)
34828aad 3726 {
ca61edf2 3727 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 3728 i.suffix = LONG_MNEM_SUFFIX;
3729 }
3730 else
3731 {
3732 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3733 register_prefix, i.op[op].regs->reg_name,
3734 i.suffix);
3735 return 0;
3736 }
252b5132 3737 }
29b0f896
AM		 3738 return 1;
3739}
252b5132 3740
29b0f896 3741static int
e3bb37b5 3742check_word_reg (void)
29b0f896
AM		 3743{
3744 int op;
3745 for (op = i.operands; --op >= 0;)
3746 /* Reject eight bit registers, except where the template requires
3747 them. (eg. movzb) */
40fb9820
L		 3748 if (i.types[op].bitfield.reg8
3749 && (i.tm.operand_types[op].bitfield.reg16
3750 || i.tm.operand_types[op].bitfield.reg32
3751 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3752 {
a540244d
L		 3753 as_bad (_("`%s%s' not allowed with `%s%c'"),
3754 register_prefix,
29b0f896
AM		 3755 i.op[op].regs->reg_name,
3756 i.tm.name,
3757 i.suffix);
3758 return 0;
3759 }
3760 /* Warn if the e prefix on a general reg is present. */
3761 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3762 && i.types[op].bitfield.reg32
3763 && (i.tm.operand_types[op].bitfield.reg16
3764 || i.tm.operand_types[op].bitfield.acc))
252b5132 3765 {
29b0f896
AM		 3766 /* Prohibit these changes in the 64bit mode, since the
3767 lowering is more complicated. */
3768 if (flag_code == CODE_64BIT)
252b5132 3769 {
2ca3ace5
L		 3770 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3771 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3772 i.suffix);
3773 return 0;
252b5132 3774 }
29b0f896
AM		 3775 else
3776#if REGISTER_WARNINGS
a540244d
L		 3777 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3778 register_prefix,
29b0f896 3779 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3780 register_prefix,
29b0f896
AM		 3781 i.op[op].regs->reg_name,
3782 i.suffix);
3783#endif
3784 }
3785 return 1;
3786}
252b5132 3787
29b0f896 3788static int
40fb9820 3789update_imm (unsigned int j)
29b0f896 3790{
40fb9820
L		 3791 i386_operand_type overlap;
3792
c6fb90c8 3793 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3794 if ((overlap.bitfield.imm8
3795 || overlap.bitfield.imm8s
3796 || overlap.bitfield.imm16
3797 || overlap.bitfield.imm32
3798 || overlap.bitfield.imm32s
3799 || overlap.bitfield.imm64)
c6fb90c8
L		 3800 && !UINTS_EQUAL (overlap, imm8)
3801 && !UINTS_EQUAL (overlap, imm8s)
3802 && !UINTS_EQUAL (overlap, imm16)
3803 && !UINTS_EQUAL (overlap, imm32)
3804 && !UINTS_EQUAL (overlap, imm32s)
3805 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3806 {
3807 if (i.suffix)
3808 {
40fb9820
L		 3809 i386_operand_type temp;
3810
c6fb90c8 3811 UINTS_CLEAR (temp);
40fb9820
L		 3812 if (i.suffix == BYTE_MNEM_SUFFIX)
3813 {
3814 temp.bitfield.imm8 = overlap.bitfield.imm8;
3815 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3816 }
3817 else if (i.suffix == WORD_MNEM_SUFFIX)
3818 temp.bitfield.imm16 = overlap.bitfield.imm16;
3819 else if (i.suffix == QWORD_MNEM_SUFFIX)
3820 {
3821 temp.bitfield.imm64 = overlap.bitfield.imm64;
3822 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3823 }
3824 else
3825 temp.bitfield.imm32 = overlap.bitfield.imm32;
3826 overlap = temp;
29b0f896 3827 }
c6fb90c8
L		 3828 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3829 || UINTS_EQUAL (overlap, imm16_32)
3830 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3831 {
c6fb90c8 3832 UINTS_CLEAR (overlap);
40fb9820
L		 3833 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3834 overlap.bitfield.imm16 = 1;
3835 else
3836 overlap.bitfield.imm32s = 1;
29b0f896 3837 }
c6fb90c8
L		 3838 if (!UINTS_EQUAL (overlap, imm8)
3839 && !UINTS_EQUAL (overlap, imm8s)
3840 && !UINTS_EQUAL (overlap, imm16)
3841 && !UINTS_EQUAL (overlap, imm32)
3842 && !UINTS_EQUAL (overlap, imm32s)
3843 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3844 {
4eed87de
AM		 3845 as_bad (_("no instruction mnemonic suffix given; "
3846 "can't determine immediate size"));
29b0f896
AM		 3847 return 0;
3848 }
3849 }
40fb9820 3850 i.types[j] = overlap;
29b0f896 3851
40fb9820
L		 3852 return 1;
3853}
3854
3855static int
3856finalize_imm (void)
3857{
3858 unsigned int j;
29b0f896 3859
40fb9820
L		 3860 for (j = 0; j < 2; j++)
3861 if (update_imm (j) == 0)
3862 return 0;
3863
c6fb90c8 3864 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3865 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3866
3867 return 1;
3868}
3869
85f10a01
MM		 3870static void
3871process_drex (void)
3872{
3873 i.drex.modrm_reg = None;
3874 i.drex.modrm_regmem = None;
3875
3876 /* SSE5 4 operand instructions must have the destination the same as
3877 one of the inputs. Figure out the destination register and cache
3878 it away in the drex field, and remember which fields to use for
3879 the modrm byte. */
3880 if (i.tm.opcode_modifier.drex
3881 && i.tm.opcode_modifier.drexv
3882 && i.operands == 4)
3883 {
3884 i.tm.extension_opcode = None;
3885
3886 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3887 if (i.types[0].bitfield.regxmm != 0
3888 && i.types[1].bitfield.regxmm != 0
3889 && i.types[2].bitfield.regxmm != 0
3890 && i.types[3].bitfield.regxmm != 0
3891 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3892 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3893 {
3894 /* Clear the arguments that are stored in drex. */
3895 UINTS_CLEAR (i.types[0]);
3896 UINTS_CLEAR (i.types[3]);
3897 i.reg_operands -= 2;
3898
3899 /* There are two different ways to encode a 4 operand
3900 instruction with all registers that uses OC1 set to
3901 0 or 1. Favor setting OC1 to 0 since this mimics the
3902 actions of other SSE5 assemblers. Use modrm encoding 2
3903 for register/register. Include the high order bit that
3904 is normally stored in the REX byte in the register
3905 field. */
3906 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3907 i.drex.modrm_reg = 2;
3908 i.drex.modrm_regmem = 1;
3909 i.drex.reg = (i.op[3].regs->reg_num
3910 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3911 }
3912
3913 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3914 else if (i.types[0].bitfield.regxmm != 0
3915 && i.types[1].bitfield.regxmm != 0
3916 && (i.types[2].bitfield.regxmm
3917 || operand_type_check (i.types[2], anymem))
3918 && i.types[3].bitfield.regxmm != 0
3919 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3920 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3921 {
3922 /* clear the arguments that are stored in drex */
3923 UINTS_CLEAR (i.types[0]);
3924 UINTS_CLEAR (i.types[3]);
3925 i.reg_operands -= 2;
3926
3927 /* Specify the modrm encoding for memory addressing. Include
3928 the high order bit that is normally stored in the REX byte
3929 in the register field. */
3930 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3931 i.drex.modrm_reg = 1;
3932 i.drex.modrm_regmem = 2;
3933 i.drex.reg = (i.op[3].regs->reg_num
3934 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3935 }
3936
3937 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3938 else if (i.types[0].bitfield.regxmm != 0
3939 && operand_type_check (i.types[1], anymem) != 0
3940 && i.types[2].bitfield.regxmm != 0
3941 && i.types[3].bitfield.regxmm != 0
3942 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3943 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3944 {
3945 /* Clear the arguments that are stored in drex. */
3946 UINTS_CLEAR (i.types[0]);
3947 UINTS_CLEAR (i.types[3]);
3948 i.reg_operands -= 2;
3949
3950 /* Specify the modrm encoding for memory addressing. Include
3951 the high order bit that is normally stored in the REX byte
3952 in the register field. */
3953 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3954 i.drex.modrm_reg = 2;
3955 i.drex.modrm_regmem = 1;
3956 i.drex.reg = (i.op[3].regs->reg_num
3957 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3958 }
3959
3960 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3961 else if (i.types[0].bitfield.regxmm != 0
3962 && i.types[1].bitfield.regxmm != 0
3963 && i.types[2].bitfield.regxmm != 0
3964 && i.types[3].bitfield.regxmm != 0
3965 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3966 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3967 {
3968 /* clear the arguments that are stored in drex */
3969 UINTS_CLEAR (i.types[2]);
3970 UINTS_CLEAR (i.types[3]);
3971 i.reg_operands -= 2;
3972
3973 /* There are two different ways to encode a 4 operand
3974 instruction with all registers that uses OC1 set to
3975 0 or 1. Favor setting OC1 to 0 since this mimics the
3976 actions of other SSE5 assemblers. Use modrm encoding
3977 2 for register/register. Include the high order bit that
3978 is normally stored in the REX byte in the register
3979 field. */
3980 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3981 i.drex.modrm_reg = 1;
3982 i.drex.modrm_regmem = 0;
3983
3984 /* Remember the register, including the upper bits */
3985 i.drex.reg = (i.op[3].regs->reg_num
3986 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3987 }
3988
3989 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
3990 else if (i.types[0].bitfield.regxmm != 0
3991 && (i.types[1].bitfield.regxmm
3992 || operand_type_check (i.types[1], anymem))
3993 && i.types[2].bitfield.regxmm != 0
3994 && i.types[3].bitfield.regxmm != 0
3995 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3996 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3997 {
3998 /* Clear the arguments that are stored in drex. */
3999 UINTS_CLEAR (i.types[2]);
4000 UINTS_CLEAR (i.types[3]);
4001 i.reg_operands -= 2;
4002
4003 /* Specify the modrm encoding and remember the register
4004 including the bits normally stored in the REX byte. */
4005 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4006 i.drex.modrm_reg = 0;
4007 i.drex.modrm_regmem = 1;
4008 i.drex.reg = (i.op[3].regs->reg_num
4009 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4010 }
4011
4012 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4013 else if (operand_type_check (i.types[0], anymem) != 0
4014 && i.types[1].bitfield.regxmm != 0
4015 && i.types[2].bitfield.regxmm != 0
4016 && i.types[3].bitfield.regxmm != 0
4017 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4018 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4019 {
4020 /* clear the arguments that are stored in drex */
4021 UINTS_CLEAR (i.types[2]);
4022 UINTS_CLEAR (i.types[3]);
4023 i.reg_operands -= 2;
4024
4025 /* Specify the modrm encoding and remember the register
4026 including the bits normally stored in the REX byte. */
4027 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4028 i.drex.modrm_reg = 1;
4029 i.drex.modrm_regmem = 0;
4030 i.drex.reg = (i.op[3].regs->reg_num
4031 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4032 }
4033
4034 else
4035 as_bad (_("Incorrect operands for the '%s' instruction"),
4036 i.tm.name);
4037 }
4038
4039 /* SSE5 instructions with the DREX byte where the only memory operand
4040 is in the 2nd argument, and the first and last xmm register must
4041 match, and is encoded in the DREX byte. */
4042 else if (i.tm.opcode_modifier.drex
4043 && !i.tm.opcode_modifier.drexv
4044 && i.operands == 4)
4045 {
4046 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4047 if (i.types[0].bitfield.regxmm != 0
4048 && (i.types[1].bitfield.regxmm
4049 || operand_type_check(i.types[1], anymem))
4050 && i.types[2].bitfield.regxmm != 0
4051 && i.types[3].bitfield.regxmm != 0
4052 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4053 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4054 {
4055 /* clear the arguments that are stored in drex */
4056 UINTS_CLEAR (i.types[0]);
4057 UINTS_CLEAR (i.types[3]);
4058 i.reg_operands -= 2;
4059
4060 /* Specify the modrm encoding and remember the register
4061 including the high bit normally stored in the REX
4062 byte. */
4063 i.drex.modrm_reg = 2;
4064 i.drex.modrm_regmem = 1;
4065 i.drex.reg = (i.op[3].regs->reg_num
4066 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4067 }
4068
4069 else
4070 as_bad (_("Incorrect operands for the '%s' instruction"),
4071 i.tm.name);
4072 }
4073
4074 /* SSE5 3 operand instructions that the result is a register, being
4075 either operand can be a memory operand, using OC0 to note which
4076 one is the memory. */
4077 else if (i.tm.opcode_modifier.drex
4078 && i.tm.opcode_modifier.drexv
4079 && i.operands == 3)
4080 {
4081 i.tm.extension_opcode = None;
4082
4083 /* Case 1: 3 operand insn, src1 = register. */
4084 if (i.types[0].bitfield.regxmm != 0
4085 && i.types[1].bitfield.regxmm != 0
4086 && i.types[2].bitfield.regxmm != 0)
4087 {
4088 /* Clear the arguments that are stored in drex. */
4089 UINTS_CLEAR (i.types[2]);
4090 i.reg_operands--;
4091
4092 /* Specify the modrm encoding and remember the register
4093 including the high bit normally stored in the REX byte. */
4094 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4095 i.drex.modrm_reg = 1;
4096 i.drex.modrm_regmem = 0;
4097 i.drex.reg = (i.op[2].regs->reg_num
4098 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4099 }
4100
4101 /* Case 2: 3 operand insn, src1 = memory. */
4102 else if (operand_type_check (i.types[0], anymem) != 0
4103 && i.types[1].bitfield.regxmm != 0
4104 && i.types[2].bitfield.regxmm != 0)
4105 {
4106 /* Clear the arguments that are stored in drex. */
4107 UINTS_CLEAR (i.types[2]);
4108 i.reg_operands--;
4109
4110 /* Specify the modrm encoding and remember the register
4111 including the high bit normally stored in the REX
4112 byte. */
4113 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4114 i.drex.modrm_reg = 1;
4115 i.drex.modrm_regmem = 0;
4116 i.drex.reg = (i.op[2].regs->reg_num
4117 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4118 }
4119
4120 /* Case 3: 3 operand insn, src2 = memory. */
4121 else if (i.types[0].bitfield.regxmm != 0
4122 && operand_type_check (i.types[1], anymem) != 0
4123 && i.types[2].bitfield.regxmm != 0)
4124 {
4125 /* Clear the arguments that are stored in drex. */
4126 UINTS_CLEAR (i.types[2]);
4127 i.reg_operands--;
4128
4129 /* Specify the modrm encoding and remember the register
4130 including the high bit normally stored in the REX byte. */
4131 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4132 i.drex.modrm_reg = 0;
4133 i.drex.modrm_regmem = 1;
4134 i.drex.reg = (i.op[2].regs->reg_num
4135 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4136 }
4137
4138 else
4139 as_bad (_("Incorrect operands for the '%s' instruction"),
4140 i.tm.name);
4141 }
4142
4143 /* SSE5 4 operand instructions that are the comparison instructions
4144 where the first operand is the immediate value of the comparison
4145 to be done. */
4146 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4147 {
4148 /* Case 1: 4 operand insn, src1 = reg/memory. */
4149 if (operand_type_check (i.types[0], imm) != 0
4150 && (i.types[1].bitfield.regxmm
4151 || operand_type_check (i.types[1], anymem))
4152 && i.types[2].bitfield.regxmm != 0
4153 && i.types[3].bitfield.regxmm != 0)
4154 {
4155 /* clear the arguments that are stored in drex */
4156 UINTS_CLEAR (i.types[3]);
4157 i.reg_operands--;
4158
4159 /* Specify the modrm encoding and remember the register
4160 including the high bit normally stored in the REX byte. */
4161 i.drex.modrm_reg = 2;
4162 i.drex.modrm_regmem = 1;
4163 i.drex.reg = (i.op[3].regs->reg_num
4164 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4165 }
4166
4167 /* Case 2: 3 operand insn with ImmExt that places the
4168 opcode_extension as an immediate argument. This is used for
4169 all of the varients of comparison that supplies the appropriate
4170 value as part of the instruction. */
4171 else if ((i.types[0].bitfield.regxmm
4172 || operand_type_check (i.types[0], anymem))
4173 && i.types[1].bitfield.regxmm != 0
4174 && i.types[2].bitfield.regxmm != 0
4175 && operand_type_check (i.types[3], imm) != 0)
4176 {
4177 /* clear the arguments that are stored in drex */
4178 UINTS_CLEAR (i.types[2]);
4179 i.reg_operands--;
4180
4181 /* Specify the modrm encoding and remember the register
4182 including the high bit normally stored in the REX byte. */
4183 i.drex.modrm_reg = 1;
4184 i.drex.modrm_regmem = 0;
4185 i.drex.reg = (i.op[2].regs->reg_num
4186 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4187 }
4188
4189 else
4190 as_bad (_("Incorrect operands for the '%s' instruction"),
4191 i.tm.name);
4192 }
4193
4194 else if (i.tm.opcode_modifier.drex
4195 || i.tm.opcode_modifier.drexv
4196 || i.tm.opcode_modifier.drexc)
4197 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4198}
4199
29b0f896 4200static int
e3bb37b5 4201process_operands (void)
29b0f896
AM		 4202{
4203 /* Default segment register this instruction will use for memory
4204 accesses. 0 means unknown. This is only for optimizing out
4205 unnecessary segment overrides. */
4206 const seg_entry *default_seg = 0;
4207
85f10a01
MM		 4208 /* Handle all of the DREX munging that SSE5 needs. */
4209 if (i.tm.opcode_modifier.drex
4210 || i.tm.opcode_modifier.drexv
4211 || i.tm.opcode_modifier.drexc)
4212 process_drex ();
4213
e2ec9d29 4214 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4215 {
9fcfb3d7
L		 4216 unsigned int j;
4217
e2ec9d29
L		 4218 /* The first operand is implicit and must be xmm0. */
4219 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4220 if (i.op[0].regs->reg_num != 0)
4221 {
4222 if (intel_syntax)
4223 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4224 i.tm.name, register_prefix);
4225 else
4226 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4227 i.tm.name, register_prefix);
4228 return 0;
4229 }
9fcfb3d7
L		 4230
4231 for (j = 1; j < i.operands; j++)
4232 {
4233 i.op[j - 1] = i.op[j];
4234 i.types[j - 1] = i.types[j];
4235
4236 /* We need to adjust fields in i.tm since they are used by
4237 build_modrm_byte. */
4238 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4239 }
4240
e2ec9d29
L		 4241 i.operands--;
4242 i.reg_operands--;
e2ec9d29
L		 4243 i.tm.operands--;
4244 }
4245 else if (i.tm.opcode_modifier.regkludge)
4246 {
4247 /* The imul $imm, %reg instruction is converted into
4248 imul $imm, %reg, %reg, and the clr %reg instruction
4249 is converted into xor %reg, %reg. */
4250
4251 unsigned int first_reg_op;
4252
4253 if (operand_type_check (i.types[0], reg))
4254 first_reg_op = 0;
4255 else
4256 first_reg_op = 1;
4257 /* Pretend we saw the extra register operand. */
4258 assert (i.reg_operands == 1
4259 && i.op[first_reg_op + 1].regs == 0);
4260 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4261 i.types[first_reg_op + 1] = i.types[first_reg_op];
4262 i.operands++;
4263 i.reg_operands++;
29b0f896
AM		 4264 }
4265
40fb9820 4266 if (i.tm.opcode_modifier.shortform)
29b0f896 4267 {
40fb9820
L		 4268 if (i.types[0].bitfield.sreg2
4269 || i.types[0].bitfield.sreg3)
29b0f896 4270 {
4eed87de
AM		 4271 if (i.tm.base_opcode == POP_SEG_SHORT
4272 && i.op[0].regs->reg_num == 1)
29b0f896 4273 {
4eed87de
AM		 4274 as_bad (_("you can't `pop %%cs'"));
4275 return 0;
29b0f896 4276 }
4eed87de
AM		 4277 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4278 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4279 i.rex |= REX_B;
4eed87de
AM		 4280 }
4281 else
4282 {
85f10a01
MM		 4283 /* The register or float register operand is in operand
4284 0 or 1. */
40fb9820
L		 4285 unsigned int op;
4286
4287 if (i.types[0].bitfield.floatreg
4288 || operand_type_check (i.types[0], reg))
4289 op = 0;
4290 else
4291 op = 1;
4eed87de
AM		 4292 /* Register goes in low 3 bits of opcode. */
4293 i.tm.base_opcode |= i.op[op].regs->reg_num;
4294 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4295 i.rex |= REX_B;
40fb9820 4296 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4297 {
4eed87de
AM		 4298 /* Warn about some common errors, but press on regardless.
4299 The first case can be generated by gcc (<= 2.8.1). */
4300 if (i.operands == 2)
4301 {
4302 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4303 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4304 register_prefix, i.op[1].regs->reg_name,
4305 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4306 }
4307 else
4308 {
4309 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4310 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4311 register_prefix, i.op[0].regs->reg_name);
4eed87de 4312 }
29b0f896
AM		 4313 }
4314 }
4315 }
40fb9820 4316 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4317 {
4318 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4319 must be put into the modrm byte). Now, we make the modrm and
4320 index base bytes based on all the info we've collected. */
29b0f896
AM		 4321
4322 default_seg = build_modrm_byte ();
4323 }
8a2ed489 4324 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4325 {
4326 default_seg = &ds;
4327 }
40fb9820 4328 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4329 {
4330 /* For the string instructions that allow a segment override
4331 on one of their operands, the default segment is ds. */
4332 default_seg = &ds;
4333 }
4334
75178d9d
L		 4335 if (i.tm.base_opcode == 0x8d /* lea */
4336 && i.seg[0]
4337 && !quiet_warnings)
30123838 4338 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4339
4340 /* If a segment was explicitly specified, and the specified segment
4341 is not the default, use an opcode prefix to select it. If we
4342 never figured out what the default segment is, then default_seg
4343 will be zero at this point, and the specified segment prefix will
4344 always be used. */
29b0f896
AM		 4345 if ((i.seg[0]) && (i.seg[0] != default_seg))
4346 {
4347 if (!add_prefix (i.seg[0]->seg_prefix))
4348 return 0;
4349 }
4350 return 1;
4351}
4352
4353static const seg_entry *
e3bb37b5 4354build_modrm_byte (void)
29b0f896
AM		 4355{
4356 const seg_entry *default_seg = 0;
4357
85f10a01
MM		 4358 /* SSE5 4 operand instructions are encoded in such a way that one of
4359 the inputs must match the destination register. Process_drex hides
4360 the 3rd argument in the drex field, so that by the time we get
4361 here, it looks to GAS as if this is a 2 operand instruction. */
4362 if ((i.tm.opcode_modifier.drex
4363 || i.tm.opcode_modifier.drexv
b5016f89 4364 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4365 && i.reg_operands == 2)
4366 {
4367 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4368 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4369
4370 i.rm.reg = reg->reg_num;
4371 i.rm.regmem = regmem->reg_num;
4372 i.rm.mode = 3;
4373 if ((reg->reg_flags & RegRex) != 0)
4374 i.rex |= REX_R;
4375 if ((regmem->reg_flags & RegRex) != 0)
4376 i.rex |= REX_B;
4377 }
4378
29b0f896
AM		 4379 /* i.reg_operands MUST be the number of real register operands;
4380 implicit registers do not count. */
85f10a01 4381 else if (i.reg_operands == 2)
29b0f896
AM		 4382 {
4383 unsigned int source, dest;
cab737b9
L		 4384
4385 switch (i.operands)
4386 {
4387 case 2:
4388 source = 0;
4389 break;
4390 case 3:
c81128dc
L		 4391 /* When there are 3 operands, one of them may be immediate,
4392 which may be the first or the last operand. Otherwise,
4393 the first operand must be shift count register (cl). */
4394 assert (i.imm_operands == 1
4395 || (i.imm_operands == 0
40fb9820
L		 4396 && i.types[0].bitfield.shiftcount));
4397 if (operand_type_check (i.types[0], imm)
4398 || i.types[0].bitfield.shiftcount)
4399 source = 1;
4400 else
4401 source = 0;
cab737b9
L		 4402 break;
4403 case 4:
368d64cc
L		 4404 /* When there are 4 operands, the first two must be 8bit
4405 immediate operands. The source operand will be the 3rd
4406 one. */
cab737b9 4407 assert (i.imm_operands == 2
368d64cc
L		 4408 && i.types[0].bitfield.imm8
4409 && i.types[1].bitfield.imm8);
cab737b9
L		 4410 source = 2;
4411 break;
4412 default:
4413 abort ();
4414 }
4415
29b0f896
AM		 4416 dest = source + 1;
4417
4418 i.rm.mode = 3;
4419 /* One of the register operands will be encoded in the i.tm.reg
4420 field, the other in the combined i.tm.mode and i.tm.regmem
4421 fields. If no form of this instruction supports a memory
4422 destination operand, then we assume the source operand may
4423 sometimes be a memory operand and so we need to store the
4424 destination in the i.rm.reg field. */
40fb9820
L		 4425 if (!i.tm.operand_types[dest].bitfield.regmem
4426 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4427 {
4428 i.rm.reg = i.op[dest].regs->reg_num;
4429 i.rm.regmem = i.op[source].regs->reg_num;
4430 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4431 i.rex |= REX_R;
29b0f896 4432 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4433 i.rex |= REX_B;
29b0f896
AM		 4434 }
4435 else
4436 {
4437 i.rm.reg = i.op[source].regs->reg_num;
4438 i.rm.regmem = i.op[dest].regs->reg_num;
4439 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4440 i.rex |= REX_B;
29b0f896 4441 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4442 i.rex |= REX_R;
29b0f896 4443 }
161a04f6 4444 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4445 {
40fb9820
L		 4446 if (!i.types[0].bitfield.control
4447 && !i.types[1].bitfield.control)
c4a530c5 4448 abort ();
161a04f6 4449 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4450 add_prefix (LOCK_PREFIX_OPCODE);
4451 }
29b0f896
AM		 4452 }
4453 else
4454 { /* If it's not 2 reg operands... */
4455 if (i.mem_operands)
4456 {
4457 unsigned int fake_zero_displacement = 0;
99018f42 4458 unsigned int op;
4eed87de 4459
85f10a01
MM		 4460 /* This has been precalculated for SSE5 instructions
4461 that have a DREX field earlier in process_drex. */
b5016f89
L		 4462 if (i.tm.opcode_modifier.drex
4463 || i.tm.opcode_modifier.drexv
4464 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4465 op = i.drex.modrm_regmem;
4466 else
4467 {
c0209578
L		 4468 for (op = 0; op < i.operands; op++)
4469 if (operand_type_check (i.types[op], anymem))
4470 break;
4471 assert (op < i.operands);
85f10a01 4472 }
29b0f896
AM		 4473
4474 default_seg = &ds;
4475
4476 if (i.base_reg == 0)
4477 {
4478 i.rm.mode = 0;
4479 if (!i.disp_operands)
4480 fake_zero_displacement = 1;
4481 if (i.index_reg == 0)
4482 {
4483 /* Operand is just <disp> */
20f0a1fc 4484 if (flag_code == CODE_64BIT)
29b0f896
AM		 4485 {
4486 /* 64bit mode overwrites the 32bit absolute
4487 addressing by RIP relative addressing and
4488 absolute addressing is encoded by one of the
4489 redundant SIB forms. */
4490 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4491 i.sib.base = NO_BASE_REGISTER;
4492 i.sib.index = NO_INDEX_REGISTER;
fc225355 4493 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4494 ? disp32s : disp32);
20f0a1fc 4495 }
fc225355
L		 4496 else if ((flag_code == CODE_16BIT)
4497 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4498 {
4499 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4500 i.types[op] = disp16;
20f0a1fc
NC		 4501 }
4502 else
4503 {
4504 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4505 i.types[op] = disp32;
29b0f896
AM		 4506 }
4507 }
4508 else /* !i.base_reg && i.index_reg */
4509 {
db51cc60
L		 4510 if (i.index_reg->reg_num == RegEiz
4511 || i.index_reg->reg_num == RegRiz)
4512 i.sib.index = NO_INDEX_REGISTER;
4513 else
4514 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4515 i.sib.base = NO_BASE_REGISTER;
4516 i.sib.scale = i.log2_scale_factor;
4517 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4518 i.types[op].bitfield.disp8 = 0;
4519 i.types[op].bitfield.disp16 = 0;
4520 i.types[op].bitfield.disp64 = 0;
29b0f896 4521 if (flag_code != CODE_64BIT)
40fb9820
L		 4522 {
4523 /* Must be 32 bit */
4524 i.types[op].bitfield.disp32 = 1;
4525 i.types[op].bitfield.disp32s = 0;
4526 }
29b0f896 4527 else
40fb9820
L		 4528 {
4529 i.types[op].bitfield.disp32 = 0;
4530 i.types[op].bitfield.disp32s = 1;
4531 }
29b0f896 4532 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4533 i.rex |= REX_X;
29b0f896
AM		 4534 }
4535 }
4536 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4537 else if (i.base_reg->reg_num == RegRip ||
4538 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4539 {
4540 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4541 i.types[op].bitfield.disp8 = 0;
4542 i.types[op].bitfield.disp16 = 0;
4543 i.types[op].bitfield.disp32 = 0;
4544 i.types[op].bitfield.disp32s = 1;
4545 i.types[op].bitfield.disp64 = 0;
71903a11 4546 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4547 if (! i.disp_operands)
4548 fake_zero_displacement = 1;
29b0f896 4549 }
40fb9820 4550 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4551 {
4552 switch (i.base_reg->reg_num)
4553 {
4554 case 3: /* (%bx) */
4555 if (i.index_reg == 0)
4556 i.rm.regmem = 7;
4557 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4558 i.rm.regmem = i.index_reg->reg_num - 6;
4559 break;
4560 case 5: /* (%bp) */
4561 default_seg = &ss;
4562 if (i.index_reg == 0)
4563 {
4564 i.rm.regmem = 6;
40fb9820 4565 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4566 {
4567 /* fake (%bp) into 0(%bp) */
40fb9820 4568 i.types[op].bitfield.disp8 = 1;
252b5132 4569 fake_zero_displacement = 1;
29b0f896
AM		 4570 }
4571 }
4572 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4573 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4574 break;
4575 default: /* (%si) -> 4 or (%di) -> 5 */
4576 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4577 }
4578 i.rm.mode = mode_from_disp_size (i.types[op]);
4579 }
4580 else /* i.base_reg and 32/64 bit mode */
4581 {
4582 if (flag_code == CODE_64BIT
40fb9820
L		 4583 && operand_type_check (i.types[op], disp))
4584 {
4585 i386_operand_type temp;
c6fb90c8 4586 UINTS_CLEAR (temp);
40fb9820
L		 4587 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4588 i.types[op] = temp;
4589 if (i.prefix[ADDR_PREFIX] == 0)
4590 i.types[op].bitfield.disp32s = 1;
4591 else
4592 i.types[op].bitfield.disp32 = 1;
4593 }
20f0a1fc 4594
29b0f896
AM		 4595 i.rm.regmem = i.base_reg->reg_num;
4596 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4597 i.rex |= REX_B;
29b0f896
AM		 4598 i.sib.base = i.base_reg->reg_num;
4599 /* x86-64 ignores REX prefix bit here to avoid decoder
4600 complications. */
4601 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4602 {
4603 default_seg = &ss;
4604 if (i.disp_operands == 0)
4605 {
4606 fake_zero_displacement = 1;
40fb9820 4607 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4608 }
4609 }
4610 else if (i.base_reg->reg_num == ESP_REG_NUM)
4611 {
4612 default_seg = &ss;
4613 }
4614 i.sib.scale = i.log2_scale_factor;
4615 if (i.index_reg == 0)
4616 {
4617 /* <disp>(%esp) becomes two byte modrm with no index
4618 register. We've already stored the code for esp
4619 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4620 Any base register besides %esp will not use the
4621 extra modrm byte. */
4622 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4623 }
4624 else
4625 {
db51cc60
L		 4626 if (i.index_reg->reg_num == RegEiz
4627 || i.index_reg->reg_num == RegRiz)
4628 i.sib.index = NO_INDEX_REGISTER;
4629 else
4630 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4631 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4632 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4633 i.rex |= REX_X;
29b0f896 4634 }
67a4f2b7
AO		 4635
4636 if (i.disp_operands
4637 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4638 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4639 i.rm.mode = 0;
4640 else
4641 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4642 }
252b5132 4643
29b0f896
AM		 4644 if (fake_zero_displacement)
4645 {
4646 /* Fakes a zero displacement assuming that i.types[op]
4647 holds the correct displacement size. */
4648 expressionS *exp;
4649
4650 assert (i.op[op].disps == 0);
4651 exp = &disp_expressions[i.disp_operands++];
4652 i.op[op].disps = exp;
4653 exp->X_op = O_constant;
4654 exp->X_add_number = 0;
4655 exp->X_add_symbol = (symbolS *) 0;
4656 exp->X_op_symbol = (symbolS *) 0;
4657 }
4658 }
252b5132 4659
29b0f896
AM		 4660 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4661 (if any) based on i.tm.extension_opcode. Again, we must be
4662 careful to make sure that segment/control/debug/test/MMX
4663 registers are coded into the i.rm.reg field. */
4664 if (i.reg_operands)
4665 {
99018f42
L		 4666 unsigned int op;
4667
85f10a01
MM		 4668 /* This has been precalculated for SSE5 instructions
4669 that have a DREX field earlier in process_drex. */
b5016f89
L		 4670 if (i.tm.opcode_modifier.drex
4671 || i.tm.opcode_modifier.drexv
4672 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4673 {
4674 op = i.drex.modrm_reg;
4675 i.rm.reg = i.op[op].regs->reg_num;
4676 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4677 i.rex |= REX_R;
4678 }
4679 else
4680 {
c0209578
L		 4681 for (op = 0; op < i.operands; op++)
4682 if (i.types[op].bitfield.reg8
4683 || i.types[op].bitfield.reg16
4684 || i.types[op].bitfield.reg32
4685 || i.types[op].bitfield.reg64
4686 || i.types[op].bitfield.regmmx
4687 || i.types[op].bitfield.regxmm
4688 || i.types[op].bitfield.sreg2
4689 || i.types[op].bitfield.sreg3
4690 || i.types[op].bitfield.control
4691 || i.types[op].bitfield.debug
4692 || i.types[op].bitfield.test)
4693 break;
4694
4695 assert (op < i.operands);
99018f42 4696
85f10a01
MM		 4697 /* If there is an extension opcode to put here, the
4698 register number must be put into the regmem field. */
c0209578
L		 4699 if (i.tm.extension_opcode != None)
4700 {
4701 i.rm.regmem = i.op[op].regs->reg_num;
4702 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4703 i.rex |= REX_B;
4704 }
4705 else
4706 {
4707 i.rm.reg = i.op[op].regs->reg_num;
4708 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4709 i.rex |= REX_R;
4710 }
85f10a01 4711 }
252b5132 4712
29b0f896
AM		 4713 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4714 must set it to 3 to indicate this is a register operand
4715 in the regmem field. */
4716 if (!i.mem_operands)
4717 i.rm.mode = 3;
4718 }
252b5132 4719
29b0f896 4720 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4721 if (i.tm.extension_opcode != None
4722 && !(i.tm.opcode_modifier.drex
4723 || i.tm.opcode_modifier.drexv
4724 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4725 i.rm.reg = i.tm.extension_opcode;
4726 }
4727 return default_seg;
4728}
252b5132 4729
29b0f896 4730static void
e3bb37b5 4731output_branch (void)
29b0f896
AM		 4732{
4733 char *p;
4734 int code16;
4735 int prefix;
4736 relax_substateT subtype;
4737 symbolS *sym;
4738 offsetT off;
4739
4740 code16 = 0;
4741 if (flag_code == CODE_16BIT)
4742 code16 = CODE16;
4743
4744 prefix = 0;
4745 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4746 {
29b0f896
AM		 4747 prefix = 1;
4748 i.prefixes -= 1;
4749 code16 ^= CODE16;
252b5132 4750 }
29b0f896
AM		 4751 /* Pentium4 branch hints. */
4752 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4753 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4754 {
29b0f896
AM		 4755 prefix++;
4756 i.prefixes--;
4757 }
4758 if (i.prefix[REX_PREFIX] != 0)
4759 {
4760 prefix++;
4761 i.prefixes--;
2f66722d
AM		 4762 }
4763
29b0f896
AM		 4764 if (i.prefixes != 0 && !intel_syntax)
4765 as_warn (_("skipping prefixes on this instruction"));
4766
4767 /* It's always a symbol; End frag & setup for relax.
4768 Make sure there is enough room in this frag for the largest
4769 instruction we may generate in md_convert_frag. This is 2
4770 bytes for the opcode and room for the prefix and largest
4771 displacement. */
4772 frag_grow (prefix + 2 + 4);
4773 /* Prefix and 1 opcode byte go in fr_fix. */
4774 p = frag_more (prefix + 1);
4775 if (i.prefix[DATA_PREFIX] != 0)
4776 *p++ = DATA_PREFIX_OPCODE;
4777 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4778 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4779 *p++ = i.prefix[SEG_PREFIX];
4780 if (i.prefix[REX_PREFIX] != 0)
4781 *p++ = i.prefix[REX_PREFIX];
4782 *p = i.tm.base_opcode;
4783
4784 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4785 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4786 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4787 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4788 else
4789 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4790 subtype |= code16;
3e73aa7c 4791
29b0f896
AM		 4792 sym = i.op[0].disps->X_add_symbol;
4793 off = i.op[0].disps->X_add_number;
3e73aa7c 4794
29b0f896
AM		 4795 if (i.op[0].disps->X_op != O_constant
4796 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4797 {
29b0f896
AM		 4798 /* Handle complex expressions. */
4799 sym = make_expr_symbol (i.op[0].disps);
4800 off = 0;
4801 }
3e73aa7c 4802
29b0f896
AM		 4803 /* 1 possible extra opcode + 4 byte displacement go in var part.
4804 Pass reloc in fr_var. */
4805 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4806}
3e73aa7c 4807
29b0f896 4808static void
e3bb37b5 4809output_jump (void)
29b0f896
AM		 4810{
4811 char *p;
4812 int size;
3e02c1cc 4813 fixS *fixP;
29b0f896 4814
40fb9820 4815 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4816 {
4817 /* This is a loop or jecxz type instruction. */
4818 size = 1;
4819 if (i.prefix[ADDR_PREFIX] != 0)
4820 {
4821 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4822 i.prefixes -= 1;
4823 }
4824 /* Pentium4 branch hints. */
4825 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4826 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4827 {
4828 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4829 i.prefixes--;
3e73aa7c
JH		 4830 }
4831 }
29b0f896
AM		 4832 else
4833 {
4834 int code16;
3e73aa7c 4835
29b0f896
AM		 4836 code16 = 0;
4837 if (flag_code == CODE_16BIT)
4838 code16 = CODE16;
3e73aa7c 4839
29b0f896
AM		 4840 if (i.prefix[DATA_PREFIX] != 0)
4841 {
4842 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4843 i.prefixes -= 1;
4844 code16 ^= CODE16;
4845 }
252b5132 4846
29b0f896
AM		 4847 size = 4;
4848 if (code16)
4849 size = 2;
4850 }
9fcc94b6 4851
29b0f896
AM		 4852 if (i.prefix[REX_PREFIX] != 0)
4853 {
4854 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4855 i.prefixes -= 1;
4856 }
252b5132 4857
29b0f896
AM		 4858 if (i.prefixes != 0 && !intel_syntax)
4859 as_warn (_("skipping prefixes on this instruction"));
e0890092 4860
29b0f896
AM		 4861 p = frag_more (1 + size);
4862 *p++ = i.tm.base_opcode;
e0890092 4863
3e02c1cc
AM		 4864 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4865 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4866
4867 /* All jumps handled here are signed, but don't use a signed limit
4868 check for 32 and 16 bit jumps as we want to allow wrap around at
4869 4G and 64k respectively. */
4870 if (size == 1)
4871 fixP->fx_signed = 1;
29b0f896 4872}
e0890092 4873
29b0f896 4874static void
e3bb37b5 4875output_interseg_jump (void)
29b0f896
AM		 4876{
4877 char *p;
4878 int size;
4879 int prefix;
4880 int code16;
252b5132 4881
29b0f896
AM		 4882 code16 = 0;
4883 if (flag_code == CODE_16BIT)
4884 code16 = CODE16;
a217f122 4885
29b0f896
AM		 4886 prefix = 0;
4887 if (i.prefix[DATA_PREFIX] != 0)
4888 {
4889 prefix = 1;
4890 i.prefixes -= 1;
4891 code16 ^= CODE16;
4892 }
4893 if (i.prefix[REX_PREFIX] != 0)
4894 {
4895 prefix++;
4896 i.prefixes -= 1;
4897 }
252b5132 4898
29b0f896
AM		 4899 size = 4;
4900 if (code16)
4901 size = 2;
252b5132 4902
29b0f896
AM		 4903 if (i.prefixes != 0 && !intel_syntax)
4904 as_warn (_("skipping prefixes on this instruction"));
252b5132 4905
29b0f896
AM		 4906 /* 1 opcode; 2 segment; offset */
4907 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4908
29b0f896
AM		 4909 if (i.prefix[DATA_PREFIX] != 0)
4910 *p++ = DATA_PREFIX_OPCODE;
252b5132 4911
29b0f896
AM		 4912 if (i.prefix[REX_PREFIX] != 0)
4913 *p++ = i.prefix[REX_PREFIX];
252b5132 4914
29b0f896
AM		 4915 *p++ = i.tm.base_opcode;
4916 if (i.op[1].imms->X_op == O_constant)
4917 {
4918 offsetT n = i.op[1].imms->X_add_number;
252b5132 4919
29b0f896
AM		 4920 if (size == 2
4921 && !fits_in_unsigned_word (n)
4922 && !fits_in_signed_word (n))
4923 {
4924 as_bad (_("16-bit jump out of range"));
4925 return;
4926 }
4927 md_number_to_chars (p, n, size);
4928 }
4929 else
4930 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4931 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4932 if (i.op[0].imms->X_op != O_constant)
4933 as_bad (_("can't handle non absolute segment in `%s'"),
4934 i.tm.name);
4935 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4936}
a217f122 4937
29b0f896 4938static void
e3bb37b5 4939output_insn (void)
29b0f896 4940{
2bbd9c25
JJ		 4941 fragS *insn_start_frag;
4942 offsetT insn_start_off;
4943
29b0f896
AM		 4944 /* Tie dwarf2 debug info to the address at the start of the insn.
4945 We can't do this after the insn has been output as the current
4946 frag may have been closed off. eg. by frag_var. */
4947 dwarf2_emit_insn (0);
4948
2bbd9c25
JJ		 4949 insn_start_frag = frag_now;
4950 insn_start_off = frag_now_fix ();
4951
29b0f896 4952 /* Output jumps. */
40fb9820 4953 if (i.tm.opcode_modifier.jump)
29b0f896 4954 output_branch ();
40fb9820
L		 4955 else if (i.tm.opcode_modifier.jumpbyte
4956 || i.tm.opcode_modifier.jumpdword)
29b0f896 4957 output_jump ();
40fb9820 4958 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4959 output_interseg_jump ();
4960 else
4961 {
4962 /* Output normal instructions here. */
4963 char *p;
4964 unsigned char *q;
331d2d0d 4965 unsigned int prefix;
4dffcebc
L		 4966
4967 switch (i.tm.opcode_length)
bc4bd9ab 4968 {
4dffcebc 4969 case 3:
331d2d0d
L		 4970 if (i.tm.base_opcode & 0xff000000)
4971 {
4972 prefix = (i.tm.base_opcode >> 24) & 0xff;
4973 goto check_prefix;
4974 }
4dffcebc
L		 4975 break;
4976 case 2:
4977 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 4978 {
4dffcebc
L		 4979 prefix = (i.tm.base_opcode >> 16) & 0xff;
4980 if (i.tm.cpu_flags.bitfield.cpupadlock)
4981 {
4982check_prefix:
4983 if (prefix != REPE_PREFIX_OPCODE
4984 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
4985 add_prefix (prefix);
4986 }
4987 else
bc4bd9ab
MK		 4988 add_prefix (prefix);
4989 }
4dffcebc
L		 4990 break;
4991 case 1:
4992 break;
4993 default:
4994 abort ();
0f10071e 4995 }
252b5132 4996
29b0f896
AM		 4997 /* The prefix bytes. */
4998 for (q = i.prefix;
4999 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5000 q++)
5001 {
5002 if (*q)
5003 {
5004 p = frag_more (1);
5005 md_number_to_chars (p, (valueT) *q, 1);
5006 }
5007 }
252b5132 5008
29b0f896 5009 /* Now the opcode; be careful about word order here! */
4dffcebc 5010 if (i.tm.opcode_length == 1)
29b0f896
AM		 5011 {
5012 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5013 }
5014 else
5015 {
4dffcebc 5016 switch (i.tm.opcode_length)
331d2d0d 5017 {
4dffcebc 5018 case 3:
331d2d0d
L		 5019 p = frag_more (3);
5020 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5021 break;
5022 case 2:
5023 p = frag_more (2);
5024 break;
5025 default:
5026 abort ();
5027 break;
331d2d0d 5028 }
0f10071e 5029
29b0f896
AM		 5030 /* Put out high byte first: can't use md_number_to_chars! */
5031 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5032 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5033
5034 /* On SSE5, encode the OC1 bit in the DREX field if this
5035 encoding has multiple formats. */
5036 if (i.tm.opcode_modifier.drex
5037 && i.tm.opcode_modifier.drexv
5038 && DREX_OC1 (i.tm.extension_opcode))
5039 *p |= DREX_OC1_MASK;
29b0f896 5040 }
3e73aa7c 5041
29b0f896 5042 /* Now the modrm byte and sib byte (if present). */
40fb9820 5043 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5044 {
5045 p = frag_more (1);
5046 md_number_to_chars (p,
5047 (valueT) (i.rm.regmem << 0
5048 | i.rm.reg << 3
5049 | i.rm.mode << 6),
5050 1);
5051 /* If i.rm.regmem == ESP (4)
5052 && i.rm.mode != (Register mode)
5053 && not 16 bit
5054 ==> need second modrm byte. */
5055 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5056 && i.rm.mode != 3
40fb9820 5057 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 5058 {
5059 p = frag_more (1);
5060 md_number_to_chars (p,
5061 (valueT) (i.sib.base << 0
5062 | i.sib.index << 3
5063 | i.sib.scale << 6),
5064 1);
5065 }
5066 }
3e73aa7c 5067
85f10a01
MM		 5068 /* Write the DREX byte if needed. */
5069 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5070 {
5071 p = frag_more (1);
5072 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5073
5074 /* Encode the OC0 bit if this encoding has multiple
5075 formats. */
5076 if ((i.tm.opcode_modifier.drex
5077 || i.tm.opcode_modifier.drexv)
5078 && DREX_OC0 (i.tm.extension_opcode))
5079 *p |= DREX_OC0_MASK;
5080 }
5081
29b0f896 5082 if (i.disp_operands)
2bbd9c25 5083 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5084
29b0f896 5085 if (i.imm_operands)
2bbd9c25 5086 output_imm (insn_start_frag, insn_start_off);
29b0f896 5087 }
252b5132 5088
29b0f896
AM		 5089#ifdef DEBUG386
5090 if (flag_debug)
5091 {
7b81dfbb 5092 pi ("" /*line*/, &i);
29b0f896
AM		 5093 }
5094#endif /* DEBUG386 */
5095}
252b5132 5096
e205caa7
L		 5097/* Return the size of the displacement operand N. */
5098
5099static int
5100disp_size (unsigned int n)
5101{
5102 int size = 4;
40fb9820
L		 5103 if (i.types[n].bitfield.disp64)
5104 size = 8;
5105 else if (i.types[n].bitfield.disp8)
5106 size = 1;
5107 else if (i.types[n].bitfield.disp16)
5108 size = 2;
e205caa7
L		 5109 return size;
5110}
5111
5112/* Return the size of the immediate operand N. */
5113
5114static int
5115imm_size (unsigned int n)
5116{
5117 int size = 4;
40fb9820
L		 5118 if (i.types[n].bitfield.imm64)
5119 size = 8;
5120 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5121 size = 1;
5122 else if (i.types[n].bitfield.imm16)
5123 size = 2;
e205caa7
L		 5124 return size;
5125}
5126
29b0f896 5127static void
64e74474 5128output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5129{
5130 char *p;
5131 unsigned int n;
252b5132 5132
29b0f896
AM		 5133 for (n = 0; n < i.operands; n++)
5134 {
40fb9820 5135 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5136 {
5137 if (i.op[n].disps->X_op == O_constant)
5138 {
e205caa7 5139 int size = disp_size (n);
29b0f896 5140 offsetT val;
252b5132 5141
29b0f896
AM		 5142 val = offset_in_range (i.op[n].disps->X_add_number,
5143 size);
5144 p = frag_more (size);
5145 md_number_to_chars (p, val, size);
5146 }
5147 else
5148 {
f86103b7 5149 enum bfd_reloc_code_real reloc_type;
e205caa7 5150 int size = disp_size (n);
40fb9820 5151 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5152 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5153
e205caa7 5154 /* We can't have 8 bit displacement here. */
40fb9820 5155 assert (!i.types[n].bitfield.disp8);
e205caa7 5156
29b0f896
AM		 5157 /* The PC relative address is computed relative
5158 to the instruction boundary, so in case immediate
5159 fields follows, we need to adjust the value. */
5160 if (pcrel && i.imm_operands)
5161 {
29b0f896 5162 unsigned int n1;
e205caa7 5163 int sz = 0;
252b5132 5164
29b0f896 5165 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5166 if (operand_type_check (i.types[n1], imm))
252b5132 5167 {
e205caa7
L		 5168 /* Only one immediate is allowed for PC
5169 relative address. */
5170 assert (sz == 0);
5171 sz = imm_size (n1);
5172 i.op[n].disps->X_add_number -= sz;
252b5132 5173 }
29b0f896 5174 /* We should find the immediate. */
e205caa7 5175 assert (sz != 0);
29b0f896 5176 }
520dc8e8 5177
29b0f896 5178 p = frag_more (size);
2bbd9c25 5179 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5180 if (GOT_symbol
2bbd9c25 5181 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5182 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5183 || reloc_type == BFD_RELOC_X86_64_32S
5184 || (reloc_type == BFD_RELOC_64
5185 && object_64bit))
d6ab8113
JB		 5186 && (i.op[n].disps->X_op == O_symbol
5187 || (i.op[n].disps->X_op == O_add
5188 && ((symbol_get_value_expression
5189 (i.op[n].disps->X_op_symbol)->X_op)
5190 == O_subtract))))
5191 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5192 {
5193 offsetT add;
5194
5195 if (insn_start_frag == frag_now)
5196 add = (p - frag_now->fr_literal) - insn_start_off;
5197 else
5198 {
5199 fragS *fr;
5200
5201 add = insn_start_frag->fr_fix - insn_start_off;
5202 for (fr = insn_start_frag->fr_next;
5203 fr && fr != frag_now; fr = fr->fr_next)
5204 add += fr->fr_fix;
5205 add += p - frag_now->fr_literal;
5206 }
5207
4fa24527 5208 if (!object_64bit)
7b81dfbb
AJ		 5209 {
5210 reloc_type = BFD_RELOC_386_GOTPC;
5211 i.op[n].imms->X_add_number += add;
5212 }
5213 else if (reloc_type == BFD_RELOC_64)
5214 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5215 else
7b81dfbb
AJ		 5216 /* Don't do the adjustment for x86-64, as there
5217 the pcrel addressing is relative to the _next_
5218 insn, and that is taken care of in other code. */
d6ab8113 5219 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5220 }
062cd5e7 5221 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5222 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5223 }
5224 }
5225 }
5226}
252b5132 5227
29b0f896 5228static void
64e74474 5229output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5230{
5231 char *p;
5232 unsigned int n;
252b5132 5233
29b0f896
AM		 5234 for (n = 0; n < i.operands; n++)
5235 {
40fb9820 5236 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5237 {
5238 if (i.op[n].imms->X_op == O_constant)
5239 {
e205caa7 5240 int size = imm_size (n);
29b0f896 5241 offsetT val;
b4cac588 5242
29b0f896
AM		 5243 val = offset_in_range (i.op[n].imms->X_add_number,
5244 size);
5245 p = frag_more (size);
5246 md_number_to_chars (p, val, size);
5247 }
5248 else
5249 {
5250 /* Not absolute_section.
5251 Need a 32-bit fixup (don't support 8bit
5252 non-absolute imms). Try to support other
5253 sizes ... */
f86103b7 5254 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5255 int size = imm_size (n);
5256 int sign;
29b0f896 5257
40fb9820 5258 if (i.types[n].bitfield.imm32s
a7d61044 5259 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5260 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5261 sign = 1;
e205caa7
L		 5262 else
5263 sign = 0;
520dc8e8 5264
29b0f896
AM		 5265 p = frag_more (size);
5266 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5267
2bbd9c25
JJ		 5268 /* This is tough to explain. We end up with this one if we
5269 * have operands that look like
5270 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5271 * obtain the absolute address of the GOT, and it is strongly
5272 * preferable from a performance point of view to avoid using
5273 * a runtime relocation for this. The actual sequence of
5274 * instructions often look something like:
5275 *
5276 * call .L66
5277 * .L66:
5278 * popl %ebx
5279 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5280 *
5281 * The call and pop essentially return the absolute address
5282 * of the label .L66 and store it in %ebx. The linker itself
5283 * will ultimately change the first operand of the addl so
5284 * that %ebx points to the GOT, but to keep things simple, the
5285 * .o file must have this operand set so that it generates not
5286 * the absolute address of .L66, but the absolute address of
5287 * itself. This allows the linker itself simply treat a GOTPC
5288 * relocation as asking for a pcrel offset to the GOT to be
5289 * added in, and the addend of the relocation is stored in the
5290 * operand field for the instruction itself.
5291 *
5292 * Our job here is to fix the operand so that it would add
5293 * the correct offset so that %ebx would point to itself. The
5294 * thing that is tricky is that .-.L66 will point to the
5295 * beginning of the instruction, so we need to further modify
5296 * the operand so that it will point to itself. There are
5297 * other cases where you have something like:
5298 *
5299 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5300 *
5301 * and here no correction would be required. Internally in
5302 * the assembler we treat operands of this form as not being
5303 * pcrel since the '.' is explicitly mentioned, and I wonder
5304 * whether it would simplify matters to do it this way. Who
5305 * knows. In earlier versions of the PIC patches, the
5306 * pcrel_adjust field was used to store the correction, but
5307 * since the expression is not pcrel, I felt it would be
5308 * confusing to do it this way. */
5309
d6ab8113 5310 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5311 || reloc_type == BFD_RELOC_X86_64_32S
5312 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5313 && GOT_symbol
5314 && GOT_symbol == i.op[n].imms->X_add_symbol
5315 && (i.op[n].imms->X_op == O_symbol
5316 || (i.op[n].imms->X_op == O_add
5317 && ((symbol_get_value_expression
5318 (i.op[n].imms->X_op_symbol)->X_op)
5319 == O_subtract))))
5320 {
2bbd9c25
JJ		 5321 offsetT add;
5322
5323 if (insn_start_frag == frag_now)
5324 add = (p - frag_now->fr_literal) - insn_start_off;
5325 else
5326 {
5327 fragS *fr;
5328
5329 add = insn_start_frag->fr_fix - insn_start_off;
5330 for (fr = insn_start_frag->fr_next;
5331 fr && fr != frag_now; fr = fr->fr_next)
5332 add += fr->fr_fix;
5333 add += p - frag_now->fr_literal;
5334 }
5335
4fa24527 5336 if (!object_64bit)
d6ab8113 5337 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5338 else if (size == 4)
d6ab8113 5339 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5340 else if (size == 8)
5341 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5342 i.op[n].imms->X_add_number += add;
29b0f896 5343 }
29b0f896
AM		 5344 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5345 i.op[n].imms, 0, reloc_type);
5346 }
5347 }
5348 }
252b5132
RH		 5349}
5350\f
d182319b
JB		 5351/* x86_cons_fix_new is called via the expression parsing code when a
5352 reloc is needed. We use this hook to get the correct .got reloc. */
5353static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5354static int cons_sign = -1;
5355
5356void
e3bb37b5 5357x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5358 expressionS *exp)
d182319b
JB		 5359{
5360 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5361
5362 got_reloc = NO_RELOC;
5363
5364#ifdef TE_PE
5365 if (exp->X_op == O_secrel)
5366 {
5367 exp->X_op = O_symbol;
5368 r = BFD_RELOC_32_SECREL;
5369 }
5370#endif
5371
5372 fix_new_exp (frag, off, len, exp, 0, r);
5373}
5374
718ddfc0
JB		 5375#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5376# define lex_got(reloc, adjust, types) NULL
5377#else
f3c180ae
AM		 5378/* Parse operands of the form
5379 <symbol>@GOTOFF+<nnn>
5380 and similar .plt or .got references.
5381
5382 If we find one, set up the correct relocation in RELOC and copy the
5383 input string, minus the `@GOTOFF' into a malloc'd buffer for
5384 parsing by the calling routine. Return this buffer, and if ADJUST
5385 is non-null set it to the length of the string we removed from the
5386 input line. Otherwise return NULL. */
5387static char *
3956db08 5388lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5389 int *adjust,
40fb9820 5390 i386_operand_type *types)
f3c180ae 5391{
7b81dfbb
AJ		 5392 /* Some of the relocations depend on the size of what field is to
5393 be relocated. But in our callers i386_immediate and i386_displacement
5394 we don't yet know the operand size (this will be set by insn
5395 matching). Hence we record the word32 relocation here,
5396 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5397 static const struct {
5398 const char *str;
4fa24527 5399 const enum bfd_reloc_code_real rel[2];
40fb9820 5400 const i386_operand_type types64;
f3c180ae 5401 } gotrel[] = {
4eed87de
AM		 5402 { "PLTOFF", { 0,
5403 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5404 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5405 { "PLT", { BFD_RELOC_386_PLT32,
5406 BFD_RELOC_X86_64_PLT32 },
40fb9820 5407 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5408 { "GOTPLT", { 0,
5409 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5410 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5411 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5412 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5413 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5414 { "GOTPCREL", { 0,
5415 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5416 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5417 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5418 BFD_RELOC_X86_64_TLSGD },
40fb9820 5419 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5420 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5421 0 },
40fb9820 5422 OPERAND_TYPE_NONE },
4eed87de
AM		 5423 { "TLSLD", { 0,
5424 BFD_RELOC_X86_64_TLSLD },
40fb9820 5425 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5426 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5427 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5428 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5429 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5430 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5431 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5432 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5433 0 },
40fb9820 5434 OPERAND_TYPE_NONE },
4eed87de
AM		 5435 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5436 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5437
5438 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5439 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5440 0 },
40fb9820 5441 OPERAND_TYPE_NONE },
4eed87de
AM		 5442 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5443 0 },
40fb9820 5444 OPERAND_TYPE_NONE },
4eed87de
AM		 5445 { "GOT", { BFD_RELOC_386_GOT32,
5446 BFD_RELOC_X86_64_GOT32 },
40fb9820 5447 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5448 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5449 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5450 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5451 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5452 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5453 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5454 };
5455 char *cp;
5456 unsigned int j;
5457
718ddfc0
JB		 5458 if (!IS_ELF)
5459 return NULL;
5460
f3c180ae 5461 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5462 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5463 return NULL;
5464
5465 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5466 {
5467 int len;
5468
5469 len = strlen (gotrel[j].str);
28f81592 5470 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5471 {
4fa24527 5472 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5473 {
28f81592
AM		 5474 int first, second;
5475 char *tmpbuf, *past_reloc;
f3c180ae 5476
4fa24527 5477 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5478 if (adjust)
5479 *adjust = len;
f3c180ae 5480
3956db08
JB		 5481 if (types)
5482 {
5483 if (flag_code != CODE_64BIT)
40fb9820
L		 5484 {
5485 types->bitfield.imm32 = 1;
5486 types->bitfield.disp32 = 1;
5487 }
3956db08
JB		 5488 else
5489 *types = gotrel[j].types64;
5490 }
5491
f3c180ae
AM		 5492 if (GOT_symbol == NULL)
5493 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5494
28f81592 5495 /* The length of the first part of our input line. */
f3c180ae 5496 first = cp - input_line_pointer;
28f81592
AM		 5497
5498 /* The second part goes from after the reloc token until
67c11a9b 5499 (and including) an end_of_line char or comma. */
28f81592 5500 past_reloc = cp + 1 + len;
67c11a9b
AM		 5501 cp = past_reloc;
5502 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5503 ++cp;
5504 second = cp + 1 - past_reloc;
28f81592
AM		 5505
5506 /* Allocate and copy string. The trailing NUL shouldn't
5507 be necessary, but be safe. */
5508 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5509 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5510 if (second != 0 && *past_reloc != ' ')
5511 /* Replace the relocation token with ' ', so that
5512 errors like foo@GOTOFF1 will be detected. */
5513 tmpbuf[first++] = ' ';
5514 memcpy (tmpbuf + first, past_reloc, second);
5515 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5516 return tmpbuf;
5517 }
5518
4fa24527
JB		 5519 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5520 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5521 return NULL;
5522 }
5523 }
5524
5525 /* Might be a symbol version string. Don't as_bad here. */
5526 return NULL;
5527}
5528
f3c180ae 5529void
e3bb37b5 5530x86_cons (expressionS *exp, int size)
f3c180ae 5531{
4fa24527 5532 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5533 {
5534 /* Handle @GOTOFF and the like in an expression. */
5535 char *save;
5536 char *gotfree_input_line;
5537 int adjust;
5538
5539 save = input_line_pointer;
3956db08 5540 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5541 if (gotfree_input_line)
5542 input_line_pointer = gotfree_input_line;
5543
5544 expression (exp);
5545
5546 if (gotfree_input_line)
5547 {
5548 /* expression () has merrily parsed up to the end of line,
5549 or a comma - in the wrong buffer. Transfer how far
5550 input_line_pointer has moved to the right buffer. */
5551 input_line_pointer = (save
5552 + (input_line_pointer - gotfree_input_line)
5553 + adjust);
5554 free (gotfree_input_line);
3992d3b7
AM		 5555 if (exp->X_op == O_constant
5556 || exp->X_op == O_absent
5557 || exp->X_op == O_illegal
5558 || exp->X_op == O_register
5559 || exp->X_op == O_big)
5560 {
5561 char c = *input_line_pointer;
5562 *input_line_pointer = 0;
5563 as_bad (_("missing or invalid expression `%s'"), save);
5564 *input_line_pointer = c;
5565 }
f3c180ae
AM		 5566 }
5567 }
5568 else
5569 expression (exp);
5570}
5571#endif
5572
d182319b 5573static void signed_cons (int size)
6482c264 5574{
d182319b
JB		 5575 if (flag_code == CODE_64BIT)
5576 cons_sign = 1;
5577 cons (size);
5578 cons_sign = -1;
6482c264
NC		 5579}
5580
d182319b 5581#ifdef TE_PE
6482c264
NC		 5582static void
5583pe_directive_secrel (dummy)
5584 int dummy ATTRIBUTE_UNUSED;
5585{
5586 expressionS exp;
5587
5588 do
5589 {
5590 expression (&exp);
5591 if (exp.X_op == O_symbol)
5592 exp.X_op = O_secrel;
5593
5594 emit_expr (&exp, 4);
5595 }
5596 while (*input_line_pointer++ == ',');
5597
5598 input_line_pointer--;
5599 demand_empty_rest_of_line ();
5600}
6482c264
NC		 5601#endif
5602
252b5132 5603static int
70e41ade 5604i386_immediate (char *imm_start)
252b5132
RH		 5605{
5606 char *save_input_line_pointer;
f3c180ae 5607 char *gotfree_input_line;
252b5132 5608 segT exp_seg = 0;
47926f60 5609 expressionS *exp;
40fb9820
L		 5610 i386_operand_type types;
5611
c6fb90c8 5612 UINTS_SET (types, ~0);
252b5132
RH		 5613
5614 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5615 {
31b2323c
L		 5616 as_bad (_("at most %d immediate operands are allowed"),
5617 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5618 return 0;
5619 }
5620
5621 exp = &im_expressions[i.imm_operands++];
520dc8e8 5622 i.op[this_operand].imms = exp;
252b5132
RH		 5623
5624 if (is_space_char (*imm_start))
5625 ++imm_start;
5626
5627 save_input_line_pointer = input_line_pointer;
5628 input_line_pointer = imm_start;
5629
3956db08 5630 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5631 if (gotfree_input_line)
5632 input_line_pointer = gotfree_input_line;
252b5132
RH		 5633
5634 exp_seg = expression (exp);
5635
83183c0c 5636 SKIP_WHITESPACE ();
252b5132 5637 if (*input_line_pointer)
f3c180ae 5638 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5639
5640 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5641 if (gotfree_input_line)
5642 free (gotfree_input_line);
252b5132 5643
3992d3b7
AM		 5644 if (exp->X_op == O_absent
5645 || exp->X_op == O_illegal
5646 || exp->X_op == O_big
5647 || (gotfree_input_line
5648 && (exp->X_op == O_constant
5649 || exp->X_op == O_register)))
252b5132 5650 {
3992d3b7 5651 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5652 imm_start);
3992d3b7 5653 return 0;
252b5132 5654 }
3e73aa7c 5655 else if (exp->X_op == O_constant)
252b5132 5656 {
47926f60 5657 /* Size it properly later. */
40fb9820 5658 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5659 /* If BFD64, sign extend val. */
4eed87de
AM		 5660 if (!use_rela_relocations
5661 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5662 exp->X_add_number
5663 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5664 }
4c63da97 5665#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5666 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5667 && exp_seg != absolute_section
47926f60 5668 && exp_seg != text_section
24eab124
AM		 5669 && exp_seg != data_section
5670 && exp_seg != bss_section
5671 && exp_seg != undefined_section
f86103b7 5672 && !bfd_is_com_section (exp_seg))
252b5132 5673 {
d0b47220 5674 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5675 return 0;
5676 }
5677#endif
bb8f5920
L		 5678 else if (!intel_syntax && exp->X_op == O_register)
5679 {
5680 as_bad (_("illegal immediate register operand %s"), imm_start);
5681 return 0;
5682 }
252b5132
RH		 5683 else
5684 {
5685 /* This is an address. The size of the address will be
24eab124 5686 determined later, depending on destination register,
3e73aa7c 5687 suffix, or the default for the section. */
40fb9820
L		 5688 i.types[this_operand].bitfield.imm8 = 1;
5689 i.types[this_operand].bitfield.imm16 = 1;
5690 i.types[this_operand].bitfield.imm32 = 1;
5691 i.types[this_operand].bitfield.imm32s = 1;
5692 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5693 i.types[this_operand] = operand_type_and (i.types[this_operand],
5694 types);
252b5132
RH		 5695 }
5696
5697 return 1;
5698}
5699
551c1ca1 5700static char *
e3bb37b5 5701i386_scale (char *scale)
252b5132 5702{
551c1ca1
AM		 5703 offsetT val;
5704 char *save = input_line_pointer;
252b5132 5705
551c1ca1
AM		 5706 input_line_pointer = scale;
5707 val = get_absolute_expression ();
5708
5709 switch (val)
252b5132 5710 {
551c1ca1 5711 case 1:
252b5132
RH		 5712 i.log2_scale_factor = 0;
5713 break;
551c1ca1 5714 case 2:
252b5132
RH		 5715 i.log2_scale_factor = 1;
5716 break;
551c1ca1 5717 case 4:
252b5132
RH		 5718 i.log2_scale_factor = 2;
5719 break;
551c1ca1 5720 case 8:
252b5132
RH		 5721 i.log2_scale_factor = 3;
5722 break;
5723 default:
a724f0f4
JB		 5724 {
5725 char sep = *input_line_pointer;
5726
5727 *input_line_pointer = '\0';
5728 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5729 scale);
5730 *input_line_pointer = sep;
5731 input_line_pointer = save;
5732 return NULL;
5733 }
252b5132 5734 }
29b0f896 5735 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5736 {
5737 as_warn (_("scale factor of %d without an index register"),
24eab124 5738 1 << i.log2_scale_factor);
252b5132 5739 i.log2_scale_factor = 0;
252b5132 5740 }
551c1ca1
AM		 5741 scale = input_line_pointer;
5742 input_line_pointer = save;
5743 return scale;
252b5132
RH		 5744}
5745
252b5132 5746static int
e3bb37b5 5747i386_displacement (char *disp_start, char *disp_end)
252b5132 5748{
29b0f896 5749 expressionS *exp;
252b5132
RH		 5750 segT exp_seg = 0;
5751 char *save_input_line_pointer;
f3c180ae 5752 char *gotfree_input_line;
40fb9820
L		 5753 int override;
5754 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5755 int ret;
252b5132 5756
31b2323c
L		 5757 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5758 {
5759 as_bad (_("at most %d displacement operands are allowed"),
5760 MAX_MEMORY_OPERANDS);
5761 return 0;
5762 }
5763
c6fb90c8 5764 UINTS_CLEAR (bigdisp);
40fb9820
L		 5765 if ((i.types[this_operand].bitfield.jumpabsolute)
5766 || (!current_templates->start->opcode_modifier.jump
5767 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5768 {
40fb9820 5769 bigdisp.bitfield.disp32 = 1;
e05278af 5770 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5771 if (flag_code == CODE_64BIT)
5772 {
5773 if (!override)
5774 {
5775 bigdisp.bitfield.disp32s = 1;
5776 bigdisp.bitfield.disp64 = 1;
5777 }
5778 }
5779 else if ((flag_code == CODE_16BIT) ^ override)
5780 {
5781 bigdisp.bitfield.disp32 = 0;
5782 bigdisp.bitfield.disp16 = 1;
5783 }
e05278af
JB		 5784 }
5785 else
5786 {
5787 /* For PC-relative branches, the width of the displacement
5788 is dependent upon data size, not address size. */
e05278af 5789 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5790 if (flag_code == CODE_64BIT)
5791 {
5792 if (override || i.suffix == WORD_MNEM_SUFFIX)
5793 bigdisp.bitfield.disp16 = 1;
5794 else
5795 {
5796 bigdisp.bitfield.disp32 = 1;
5797 bigdisp.bitfield.disp32s = 1;
5798 }
5799 }
5800 else
e05278af
JB		 5801 {
5802 if (!override)
5803 override = (i.suffix == (flag_code != CODE_16BIT
5804 ? WORD_MNEM_SUFFIX
5805 : LONG_MNEM_SUFFIX));
40fb9820
L		 5806 bigdisp.bitfield.disp32 = 1;
5807 if ((flag_code == CODE_16BIT) ^ override)
5808 {
5809 bigdisp.bitfield.disp32 = 0;
5810 bigdisp.bitfield.disp16 = 1;
5811 }
e05278af 5812 }
e05278af 5813 }
c6fb90c8
L		 5814 i.types[this_operand] = operand_type_or (i.types[this_operand],
5815 bigdisp);
252b5132
RH		 5816
5817 exp = &disp_expressions[i.disp_operands];
520dc8e8 5818 i.op[this_operand].disps = exp;
252b5132
RH		 5819 i.disp_operands++;
5820 save_input_line_pointer = input_line_pointer;
5821 input_line_pointer = disp_start;
5822 END_STRING_AND_SAVE (disp_end);
5823
5824#ifndef GCC_ASM_O_HACK
5825#define GCC_ASM_O_HACK 0
5826#endif
5827#if GCC_ASM_O_HACK
5828 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5829 if (i.types[this_operand].bitfield.baseIndex
24eab124 5830 && displacement_string_end[-1] == '+')
252b5132
RH		 5831 {
5832 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5833 constraint within gcc asm statements.
5834 For instance:
5835
5836 #define _set_tssldt_desc(n,addr,limit,type) \
5837 __asm__ __volatile__ ( \
5838 "movw %w2,%0\n\t" \
5839 "movw %w1,2+%0\n\t" \
5840 "rorl $16,%1\n\t" \
5841 "movb %b1,4+%0\n\t" \
5842 "movb %4,5+%0\n\t" \
5843 "movb $0,6+%0\n\t" \
5844 "movb %h1,7+%0\n\t" \
5845 "rorl $16,%1" \
5846 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5847
5848 This works great except that the output assembler ends
5849 up looking a bit weird if it turns out that there is
5850 no offset. You end up producing code that looks like:
5851
5852 #APP
5853 movw $235,(%eax)
5854 movw %dx,2+(%eax)
5855 rorl $16,%edx
5856 movb %dl,4+(%eax)
5857 movb $137,5+(%eax)
5858 movb $0,6+(%eax)
5859 movb %dh,7+(%eax)
5860 rorl $16,%edx
5861 #NO_APP
5862
47926f60 5863 So here we provide the missing zero. */
24eab124
AM		 5864
5865 *displacement_string_end = '0';
252b5132
RH		 5866 }
5867#endif
3956db08 5868 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5869 if (gotfree_input_line)
5870 input_line_pointer = gotfree_input_line;
252b5132 5871
24eab124 5872 exp_seg = expression (exp);
252b5132 5873
636c26b0
AM		 5874 SKIP_WHITESPACE ();
5875 if (*input_line_pointer)
5876 as_bad (_("junk `%s' after expression"), input_line_pointer);
5877#if GCC_ASM_O_HACK
5878 RESTORE_END_STRING (disp_end + 1);
5879#endif
636c26b0 5880 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5881 if (gotfree_input_line)
5882 free (gotfree_input_line);
3992d3b7 5883 ret = 1;
636c26b0 5884
24eab124
AM		 5885 /* We do this to make sure that the section symbol is in
5886 the symbol table. We will ultimately change the relocation
47926f60 5887 to be relative to the beginning of the section. */
1ae12ab7 5888 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5889 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5890 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5891 {
636c26b0 5892 if (exp->X_op != O_symbol)
3992d3b7 5893 goto inv_disp;
636c26b0 5894
e5cb08ac 5895 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5896 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5897 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5898 exp->X_op = O_subtract;
5899 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5900 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5901 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5902 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5903 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5904 else
29b0f896 5905 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5906 }
252b5132 5907
3992d3b7
AM		 5908 else if (exp->X_op == O_absent
5909 || exp->X_op == O_illegal
5910 || exp->X_op == O_big
5911 || (gotfree_input_line
5912 && (exp->X_op == O_constant
5913 || exp->X_op == O_register)))
2daf4fd8 5914 {
3992d3b7
AM		 5915 inv_disp:
5916 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5917 disp_start);
3992d3b7 5918 ret = 0;
2daf4fd8
AM		 5919 }
5920
4c63da97 5921#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5922 else if (exp->X_op != O_constant
5923 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5924 && exp_seg != absolute_section
5925 && exp_seg != text_section
5926 && exp_seg != data_section
5927 && exp_seg != bss_section
5928 && exp_seg != undefined_section
5929 && !bfd_is_com_section (exp_seg))
24eab124 5930 {
d0b47220 5931 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5932 ret = 0;
24eab124 5933 }
252b5132 5934#endif
3956db08 5935
3992d3b7
AM		 5936 RESTORE_END_STRING (disp_end);
5937
40fb9820
L		 5938 /* Check if this is a displacement only operand. */
5939 bigdisp = i.types[this_operand];
5940 bigdisp.bitfield.disp8 = 0;
5941 bigdisp.bitfield.disp16 = 0;
5942 bigdisp.bitfield.disp32 = 0;
5943 bigdisp.bitfield.disp32s = 0;
5944 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5945 if (UINTS_ALL_ZERO (bigdisp))
5946 i.types[this_operand] = operand_type_and (i.types[this_operand],
5947 types);
3956db08 5948
3992d3b7 5949 return ret;
252b5132
RH		 5950}
5951
eecb386c 5952/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5953 Return 1 on success, 0 on a failure. */
5954
252b5132 5955static int
e3bb37b5 5956i386_index_check (const char *operand_string)
252b5132 5957{
3e73aa7c 5958 int ok;
24eab124 5959#if INFER_ADDR_PREFIX
eecb386c
AM		 5960 int fudged = 0;
5961
24eab124
AM		 5962 tryprefix:
5963#endif
3e73aa7c 5964 ok = 1;
75178d9d 5965 if (flag_code == CODE_64BIT)
64e74474 5966 {
64e74474 5967 if ((i.base_reg
40fb9820
L		 5968 && ((i.prefix[ADDR_PREFIX] == 0
5969 && !i.base_reg->reg_type.bitfield.reg64)
5970 || (i.prefix[ADDR_PREFIX]
5971 && !i.base_reg->reg_type.bitfield.reg32))
5972 && (i.index_reg
9a04903e
JB		 5973 || i.base_reg->reg_num !=
5974 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 5975 || (i.index_reg
40fb9820
L		 5976 && (!i.index_reg->reg_type.bitfield.baseindex
5977 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 5978 && i.index_reg->reg_num != RegRiz
5979 && !i.index_reg->reg_type.bitfield.reg64
5980 )
40fb9820 5981 || (i.prefix[ADDR_PREFIX]
db51cc60 5982 && i.index_reg->reg_num != RegEiz
40fb9820 5983 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5984 ok = 0;
3e73aa7c
JH		 5985 }
5986 else
5987 {
5988 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5989 {
5990 /* 16bit checks. */
5991 if ((i.base_reg
40fb9820
L		 5992 && (!i.base_reg->reg_type.bitfield.reg16
5993 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 5994 || (i.index_reg
40fb9820
L		 5995 && (!i.index_reg->reg_type.bitfield.reg16
5996 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 5997 || !(i.base_reg
5998 && i.base_reg->reg_num < 6
5999 && i.index_reg->reg_num >= 6
6000 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6001 ok = 0;
6002 }
6003 else
e5cb08ac 6004 {
3e73aa7c
JH		 6005 /* 32bit checks. */
6006 if ((i.base_reg
40fb9820 6007 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6008 || (i.index_reg
db51cc60
L		 6009 && ((!i.index_reg->reg_type.bitfield.reg32
6010 && i.index_reg->reg_num != RegEiz)
40fb9820 6011 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6012 ok = 0;
3e73aa7c
JH		 6013 }
6014 }
6015 if (!ok)
24eab124
AM		 6016 {
6017#if INFER_ADDR_PREFIX
20f0a1fc 6018 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6019 {
6020 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6021 i.prefixes += 1;
b23bac36
AM		 6022 /* Change the size of any displacement too. At most one of
6023 Disp16 or Disp32 is set.
6024 FIXME. There doesn't seem to be any real need for separate
6025 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6026 Removing them would probably clean up the code quite a lot. */
4eed87de 6027 if (flag_code != CODE_64BIT
40fb9820
L		 6028 && (i.types[this_operand].bitfield.disp16
6029 || i.types[this_operand].bitfield.disp32))
6030 i.types[this_operand]
c6fb90c8 6031 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6032 fudged = 1;
24eab124
AM		 6033 goto tryprefix;
6034 }
eecb386c
AM		 6035 if (fudged)
6036 as_bad (_("`%s' is not a valid base/index expression"),
6037 operand_string);
6038 else
c388dee8 6039#endif
eecb386c
AM		 6040 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6041 operand_string,
3e73aa7c 6042 flag_code_names[flag_code]);
24eab124 6043 }
20f0a1fc 6044 return ok;
24eab124 6045}
252b5132 6046
252b5132 6047/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6048 on error. */
252b5132 6049
252b5132 6050static int
e3bb37b5 6051i386_operand (char *operand_string)
252b5132 6052{
af6bdddf
AM		 6053 const reg_entry *r;
6054 char *end_op;
24eab124 6055 char *op_string = operand_string;
252b5132 6056
24eab124 6057 if (is_space_char (*op_string))
252b5132
RH		 6058 ++op_string;
6059
24eab124 6060 /* We check for an absolute prefix (differentiating,
47926f60 6061 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6062 if (*op_string == ABSOLUTE_PREFIX)
6063 {
6064 ++op_string;
6065 if (is_space_char (*op_string))
6066 ++op_string;
40fb9820 6067 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6068 }
252b5132 6069
47926f60 6070 /* Check if operand is a register. */
4d1bb795 6071 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6072 {
40fb9820
L		 6073 i386_operand_type temp;
6074
24eab124
AM		 6075 /* Check for a segment override by searching for ':' after a
6076 segment register. */
6077 op_string = end_op;
6078 if (is_space_char (*op_string))
6079 ++op_string;
40fb9820
L		 6080 if (*op_string == ':'
6081 && (r->reg_type.bitfield.sreg2
6082 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6083 {
6084 switch (r->reg_num)
6085 {
6086 case 0:
6087 i.seg[i.mem_operands] = &es;
6088 break;
6089 case 1:
6090 i.seg[i.mem_operands] = &cs;
6091 break;
6092 case 2:
6093 i.seg[i.mem_operands] = &ss;
6094 break;
6095 case 3:
6096 i.seg[i.mem_operands] = &ds;
6097 break;
6098 case 4:
6099 i.seg[i.mem_operands] = &fs;
6100 break;
6101 case 5:
6102 i.seg[i.mem_operands] = &gs;
6103 break;
6104 }
252b5132 6105
24eab124 6106 /* Skip the ':' and whitespace. */
252b5132
RH		 6107 ++op_string;
6108 if (is_space_char (*op_string))
24eab124 6109 ++op_string;
252b5132 6110
24eab124
AM		 6111 if (!is_digit_char (*op_string)
6112 && !is_identifier_char (*op_string)
6113 && *op_string != '('
6114 && *op_string != ABSOLUTE_PREFIX)
6115 {
6116 as_bad (_("bad memory operand `%s'"), op_string);
6117 return 0;
6118 }
47926f60 6119 /* Handle case of %es:*foo. */
24eab124
AM		 6120 if (*op_string == ABSOLUTE_PREFIX)
6121 {
6122 ++op_string;
6123 if (is_space_char (*op_string))
6124 ++op_string;
40fb9820 6125 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6126 }
6127 goto do_memory_reference;
6128 }
6129 if (*op_string)
6130 {
d0b47220 6131 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6132 return 0;
6133 }
40fb9820
L		 6134 temp = r->reg_type;
6135 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6136 i.types[this_operand] = operand_type_or (i.types[this_operand],
6137 temp);
520dc8e8 6138 i.op[this_operand].regs = r;
24eab124
AM		 6139 i.reg_operands++;
6140 }
af6bdddf
AM		 6141 else if (*op_string == REGISTER_PREFIX)
6142 {
6143 as_bad (_("bad register name `%s'"), op_string);
6144 return 0;
6145 }
24eab124 6146 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6147 {
24eab124 6148 ++op_string;
40fb9820 6149 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6150 {
d0b47220 6151 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6152 return 0;
6153 }
6154 if (!i386_immediate (op_string))
6155 return 0;
6156 }
6157 else if (is_digit_char (*op_string)
6158 || is_identifier_char (*op_string)
e5cb08ac 6159 || *op_string == '(')
24eab124 6160 {
47926f60 6161 /* This is a memory reference of some sort. */
af6bdddf 6162 char *base_string;
252b5132 6163
47926f60 6164 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6165 char *displacement_string_start;
6166 char *displacement_string_end;
252b5132 6167
24eab124 6168 do_memory_reference:
24eab124 6169 if ((i.mem_operands == 1
40fb9820 6170 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6171 || i.mem_operands == 2)
6172 {
6173 as_bad (_("too many memory references for `%s'"),
6174 current_templates->start->name);
6175 return 0;
6176 }
252b5132 6177
24eab124
AM		 6178 /* Check for base index form. We detect the base index form by
6179 looking for an ')' at the end of the operand, searching
6180 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6181 after the '('. */
af6bdddf 6182 base_string = op_string + strlen (op_string);
c3332e24 6183
af6bdddf
AM		 6184 --base_string;
6185 if (is_space_char (*base_string))
6186 --base_string;
252b5132 6187
47926f60 6188 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6189 displacement_string_start = op_string;
6190 displacement_string_end = base_string + 1;
252b5132 6191
24eab124
AM		 6192 if (*base_string == ')')
6193 {
af6bdddf 6194 char *temp_string;
24eab124
AM		 6195 unsigned int parens_balanced = 1;
6196 /* We've already checked that the number of left & right ()'s are
47926f60 6197 equal, so this loop will not be infinite. */
24eab124
AM		 6198 do
6199 {
6200 base_string--;
6201 if (*base_string == ')')
6202 parens_balanced++;
6203 if (*base_string == '(')
6204 parens_balanced--;
6205 }
6206 while (parens_balanced);
c3332e24 6207
af6bdddf 6208 temp_string = base_string;
c3332e24 6209
24eab124 6210 /* Skip past '(' and whitespace. */
252b5132
RH		 6211 ++base_string;
6212 if (is_space_char (*base_string))
24eab124 6213 ++base_string;
252b5132 6214
af6bdddf 6215 if (*base_string == ','
4eed87de
AM		 6216 || ((i.base_reg = parse_register (base_string, &end_op))
6217 != NULL))
252b5132 6218 {
af6bdddf 6219 displacement_string_end = temp_string;
252b5132 6220
40fb9820 6221 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6222
af6bdddf 6223 if (i.base_reg)
24eab124 6224 {
24eab124
AM		 6225 base_string = end_op;
6226 if (is_space_char (*base_string))
6227 ++base_string;
af6bdddf
AM		 6228 }
6229
6230 /* There may be an index reg or scale factor here. */
6231 if (*base_string == ',')
6232 {
6233 ++base_string;
6234 if (is_space_char (*base_string))
6235 ++base_string;
6236
4eed87de
AM		 6237 if ((i.index_reg = parse_register (base_string, &end_op))
6238 != NULL)
24eab124 6239 {
af6bdddf 6240 base_string = end_op;
24eab124
AM		 6241 if (is_space_char (*base_string))
6242 ++base_string;
af6bdddf
AM		 6243 if (*base_string == ',')
6244 {
6245 ++base_string;
6246 if (is_space_char (*base_string))
6247 ++base_string;
6248 }
e5cb08ac 6249 else if (*base_string != ')')
af6bdddf 6250 {
4eed87de
AM		 6251 as_bad (_("expecting `,' or `)' "
6252 "after index register in `%s'"),
af6bdddf
AM		 6253 operand_string);
6254 return 0;
6255 }
24eab124 6256 }
af6bdddf 6257 else if (*base_string == REGISTER_PREFIX)
24eab124 6258 {
af6bdddf 6259 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6260 return 0;
6261 }
252b5132 6262
47926f60 6263 /* Check for scale factor. */
551c1ca1 6264 if (*base_string != ')')
af6bdddf 6265 {
551c1ca1
AM		 6266 char *end_scale = i386_scale (base_string);
6267
6268 if (!end_scale)
af6bdddf 6269 return 0;
24eab124 6270
551c1ca1 6271 base_string = end_scale;
af6bdddf
AM		 6272 if (is_space_char (*base_string))
6273 ++base_string;
6274 if (*base_string != ')')
6275 {
4eed87de
AM		 6276 as_bad (_("expecting `)' "
6277 "after scale factor in `%s'"),
af6bdddf
AM		 6278 operand_string);
6279 return 0;
6280 }
6281 }
6282 else if (!i.index_reg)
24eab124 6283 {
4eed87de
AM		 6284 as_bad (_("expecting index register or scale factor "
6285 "after `,'; got '%c'"),
af6bdddf 6286 *base_string);
24eab124
AM		 6287 return 0;
6288 }
6289 }
af6bdddf 6290 else if (*base_string != ')')
24eab124 6291 {
4eed87de
AM		 6292 as_bad (_("expecting `,' or `)' "
6293 "after base register in `%s'"),
af6bdddf 6294 operand_string);
24eab124
AM		 6295 return 0;
6296 }
c3332e24 6297 }
af6bdddf 6298 else if (*base_string == REGISTER_PREFIX)
c3332e24 6299 {
af6bdddf 6300 as_bad (_("bad register name `%s'"), base_string);
24eab124 6301 return 0;
c3332e24 6302 }
24eab124
AM		 6303 }
6304
6305 /* If there's an expression beginning the operand, parse it,
6306 assuming displacement_string_start and
6307 displacement_string_end are meaningful. */
6308 if (displacement_string_start != displacement_string_end)
6309 {
6310 if (!i386_displacement (displacement_string_start,
6311 displacement_string_end))
6312 return 0;
6313 }
6314
6315 /* Special case for (%dx) while doing input/output op. */
6316 if (i.base_reg
c6fb90c8 6317 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6318 && i.index_reg == 0
6319 && i.log2_scale_factor == 0
6320 && i.seg[i.mem_operands] == 0
40fb9820 6321 && !operand_type_check (i.types[this_operand], disp))
24eab124 6322 {
c6fb90c8 6323 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6324 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6325 return 1;
6326 }
6327
eecb386c
AM		 6328 if (i386_index_check (operand_string) == 0)
6329 return 0;
24eab124
AM		 6330 i.mem_operands++;
6331 }
6332 else
ce8a8b2f
AM		 6333 {
6334 /* It's not a memory operand; argh! */
24eab124
AM		 6335 as_bad (_("invalid char %s beginning operand %d `%s'"),
6336 output_invalid (*op_string),
6337 this_operand + 1,
6338 op_string);
6339 return 0;
6340 }
47926f60 6341 return 1; /* Normal return. */
252b5132
RH		 6342}
6343\f
ee7fcc42
AM		 6344/* md_estimate_size_before_relax()
6345
6346 Called just before relax() for rs_machine_dependent frags. The x86
6347 assembler uses these frags to handle variable size jump
6348 instructions.
6349
6350 Any symbol that is now undefined will not become defined.
6351 Return the correct fr_subtype in the frag.
6352 Return the initial "guess for variable size of frag" to caller.
6353 The guess is actually the growth beyond the fixed part. Whatever
6354 we do to grow the fixed or variable part contributes to our
6355 returned value. */
6356
252b5132
RH		 6357int
6358md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6359 fragS *fragP;
6360 segT segment;
252b5132 6361{
252b5132 6362 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6363 check for un-relaxable symbols. On an ELF system, we can't relax
6364 an externally visible symbol, because it may be overridden by a
6365 shared library. */
6366 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6367#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6368 || (IS_ELF
31312f95
AM		 6369 && (S_IS_EXTERNAL (fragP->fr_symbol)
6370 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6371#endif
6372 )
252b5132 6373 {
b98ef147
AM		 6374 /* Symbol is undefined in this segment, or we need to keep a
6375 reloc so that weak symbols can be overridden. */
6376 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6377 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6378 unsigned char *opcode;
6379 int old_fr_fix;
f6af82bd 6380
ee7fcc42
AM		 6381 if (fragP->fr_var != NO_RELOC)
6382 reloc_type = fragP->fr_var;
b98ef147 6383 else if (size == 2)
f6af82bd
AM		 6384 reloc_type = BFD_RELOC_16_PCREL;
6385 else
6386 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6387
ee7fcc42
AM		 6388 old_fr_fix = fragP->fr_fix;
6389 opcode = (unsigned char *) fragP->fr_opcode;
6390
fddf5b5b 6391 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6392 {
fddf5b5b
AM		 6393 case UNCOND_JUMP:
6394 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6395 opcode[0] = 0xe9;
252b5132 6396 fragP->fr_fix += size;
062cd5e7
AS		 6397 fix_new (fragP, old_fr_fix, size,
6398 fragP->fr_symbol,
6399 fragP->fr_offset, 1,
6400 reloc_type);
252b5132
RH		 6401 break;
6402
fddf5b5b 6403 case COND_JUMP86:
412167cb
AM		 6404 if (size == 2
6405 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6406 {
6407 /* Negate the condition, and branch past an
6408 unconditional jump. */
6409 opcode[0] ^= 1;
6410 opcode[1] = 3;
6411 /* Insert an unconditional jump. */
6412 opcode[2] = 0xe9;
6413 /* We added two extra opcode bytes, and have a two byte
6414 offset. */
6415 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6416 fix_new (fragP, old_fr_fix + 2, 2,
6417 fragP->fr_symbol,
6418 fragP->fr_offset, 1,
6419 reloc_type);
fddf5b5b
AM		 6420 break;
6421 }
6422 /* Fall through. */
6423
6424 case COND_JUMP:
412167cb
AM		 6425 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6426 {
3e02c1cc
AM		 6427 fixS *fixP;
6428
412167cb 6429 fragP->fr_fix += 1;
3e02c1cc
AM		 6430 fixP = fix_new (fragP, old_fr_fix, 1,
6431 fragP->fr_symbol,
6432 fragP->fr_offset, 1,
6433 BFD_RELOC_8_PCREL);
6434 fixP->fx_signed = 1;
412167cb
AM		 6435 break;
6436 }
93c2a809 6437
24eab124 6438 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6439 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6440 opcode[1] = opcode[0] + 0x10;
f6af82bd 6441 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6442 /* We've added an opcode byte. */
6443 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6444 fix_new (fragP, old_fr_fix + 1, size,
6445 fragP->fr_symbol,
6446 fragP->fr_offset, 1,
6447 reloc_type);
252b5132 6448 break;
fddf5b5b
AM		 6449
6450 default:
6451 BAD_CASE (fragP->fr_subtype);
6452 break;
252b5132
RH		 6453 }
6454 frag_wane (fragP);
ee7fcc42 6455 return fragP->fr_fix - old_fr_fix;
252b5132 6456 }
93c2a809 6457
93c2a809
AM		 6458 /* Guess size depending on current relax state. Initially the relax
6459 state will correspond to a short jump and we return 1, because
6460 the variable part of the frag (the branch offset) is one byte
6461 long. However, we can relax a section more than once and in that
6462 case we must either set fr_subtype back to the unrelaxed state,
6463 or return the value for the appropriate branch. */
6464 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6465}
6466
47926f60
KH		 6467/* Called after relax() is finished.
6468
6469 In: Address of frag.
6470 fr_type == rs_machine_dependent.
6471 fr_subtype is what the address relaxed to.
6472
6473 Out: Any fixSs and constants are set up.
6474 Caller will turn frag into a ".space 0". */
6475
252b5132
RH		 6476void
6477md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6478 bfd *abfd ATTRIBUTE_UNUSED;
6479 segT sec ATTRIBUTE_UNUSED;
29b0f896 6480 fragS *fragP;
252b5132 6481{
29b0f896 6482 unsigned char *opcode;
252b5132 6483 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6484 offsetT target_address;
6485 offsetT opcode_address;
252b5132 6486 unsigned int extension = 0;
847f7ad4 6487 offsetT displacement_from_opcode_start;
252b5132
RH		 6488
6489 opcode = (unsigned char *) fragP->fr_opcode;
6490
47926f60 6491 /* Address we want to reach in file space. */
252b5132 6492 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6493
47926f60 6494 /* Address opcode resides at in file space. */
252b5132
RH		 6495 opcode_address = fragP->fr_address + fragP->fr_fix;
6496
47926f60 6497 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6498 displacement_from_opcode_start = target_address - opcode_address;
6499
fddf5b5b 6500 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6501 {
47926f60
KH		 6502 /* Don't have to change opcode. */
6503 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6504 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6505 }
6506 else
6507 {
6508 if (no_cond_jump_promotion
6509 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6510 as_warn_where (fragP->fr_file, fragP->fr_line,
6511 _("long jump required"));
252b5132 6512
fddf5b5b
AM		 6513 switch (fragP->fr_subtype)
6514 {
6515 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6516 extension = 4; /* 1 opcode + 4 displacement */
6517 opcode[0] = 0xe9;
6518 where_to_put_displacement = &opcode[1];
6519 break;
252b5132 6520
fddf5b5b
AM		 6521 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6522 extension = 2; /* 1 opcode + 2 displacement */
6523 opcode[0] = 0xe9;
6524 where_to_put_displacement = &opcode[1];
6525 break;
252b5132 6526
fddf5b5b
AM		 6527 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6528 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6529 extension = 5; /* 2 opcode + 4 displacement */
6530 opcode[1] = opcode[0] + 0x10;
6531 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6532 where_to_put_displacement = &opcode[2];
6533 break;
252b5132 6534
fddf5b5b
AM		 6535 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6536 extension = 3; /* 2 opcode + 2 displacement */
6537 opcode[1] = opcode[0] + 0x10;
6538 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6539 where_to_put_displacement = &opcode[2];
6540 break;
252b5132 6541
fddf5b5b
AM		 6542 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6543 extension = 4;
6544 opcode[0] ^= 1;
6545 opcode[1] = 3;
6546 opcode[2] = 0xe9;
6547 where_to_put_displacement = &opcode[3];
6548 break;
6549
6550 default:
6551 BAD_CASE (fragP->fr_subtype);
6552 break;
6553 }
252b5132 6554 }
fddf5b5b 6555
7b81dfbb
AJ		 6556 /* If size if less then four we are sure that the operand fits,
6557 but if it's 4, then it could be that the displacement is larger
6558 then -/+ 2GB. */
6559 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6560 && object_64bit
6561 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6562 + ((addressT) 1 << 31))
6563 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6564 {
6565 as_bad_where (fragP->fr_file, fragP->fr_line,
6566 _("jump target out of range"));
6567 /* Make us emit 0. */
6568 displacement_from_opcode_start = extension;
6569 }
47926f60 6570 /* Now put displacement after opcode. */
252b5132
RH		 6571 md_number_to_chars ((char *) where_to_put_displacement,
6572 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6573 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6574 fragP->fr_fix += extension;
6575}
6576\f
47926f60
KH		 6577/* Size of byte displacement jmp. */
6578int md_short_jump_size = 2;
6579
6580/* Size of dword displacement jmp. */
6581int md_long_jump_size = 5;
252b5132 6582
252b5132
RH		 6583void
6584md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6585 char *ptr;
6586 addressT from_addr, to_addr;
ab9da554
ILT		 6587 fragS *frag ATTRIBUTE_UNUSED;
6588 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6589{
847f7ad4 6590 offsetT offset;
252b5132
RH		 6591
6592 offset = to_addr - (from_addr + 2);
47926f60
KH		 6593 /* Opcode for byte-disp jump. */
6594 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6595 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6596}
6597
6598void
6599md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6600 char *ptr;
6601 addressT from_addr, to_addr;
a38cf1db
AM		 6602 fragS *frag ATTRIBUTE_UNUSED;
6603 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6604{
847f7ad4 6605 offsetT offset;
252b5132 6606
a38cf1db
AM		 6607 offset = to_addr - (from_addr + 5);
6608 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6609 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6610}
6611\f
6612/* Apply a fixup (fixS) to segment data, once it has been determined
6613 by our caller that we have all the info we need to fix it up.
6614
6615 On the 386, immediates, displacements, and data pointers are all in
6616 the same (little-endian) format, so we don't need to care about which
6617 we are handling. */
6618
94f592af 6619void
55cf6793 6620md_apply_fix (fixP, valP, seg)
47926f60
KH		 6621 /* The fix we're to put in. */
6622 fixS *fixP;
47926f60 6623 /* Pointer to the value of the bits. */
c6682705 6624 valueT *valP;
47926f60
KH		 6625 /* Segment fix is from. */
6626 segT seg ATTRIBUTE_UNUSED;
252b5132 6627{
94f592af 6628 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6629 valueT value = *valP;
252b5132 6630
f86103b7 6631#if !defined (TE_Mach)
93382f6d
AM		 6632 if (fixP->fx_pcrel)
6633 {
6634 switch (fixP->fx_r_type)
6635 {
5865bb77
ILT		 6636 default:
6637 break;
6638
d6ab8113
JB		 6639 case BFD_RELOC_64:
6640 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6641 break;
93382f6d 6642 case BFD_RELOC_32:
ae8887b5 6643 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6644 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6645 break;
6646 case BFD_RELOC_16:
6647 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6648 break;
6649 case BFD_RELOC_8:
6650 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6651 break;
6652 }
6653 }
252b5132 6654
a161fe53 6655 if (fixP->fx_addsy != NULL
31312f95 6656 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6657 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6658 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6659 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6660 && !use_rela_relocations)
252b5132 6661 {
31312f95
AM		 6662 /* This is a hack. There should be a better way to handle this.
6663 This covers for the fact that bfd_install_relocation will
6664 subtract the current location (for partial_inplace, PC relative
6665 relocations); see more below. */
252b5132 6666#ifndef OBJ_AOUT
718ddfc0 6667 if (IS_ELF
252b5132
RH		 6668#ifdef TE_PE
6669 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6670#endif
6671 )
6672 value += fixP->fx_where + fixP->fx_frag->fr_address;
6673#endif
6674#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6675 if (IS_ELF)
252b5132 6676 {
6539b54b 6677 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6678
6539b54b 6679 if ((sym_seg == seg
2f66722d 6680 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6681 && sym_seg != absolute_section))
ae6063d4 6682 && !generic_force_reloc (fixP))
2f66722d
AM		 6683 {
6684 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6685 bfd_install_relocation subtracts them out again. I think
6686 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6687 it. FIXME. */
6688 value += fixP->fx_where + fixP->fx_frag->fr_address;
6689 }
252b5132
RH		 6690 }
6691#endif
6692#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6693 /* For some reason, the PE format does not store a
6694 section address offset for a PC relative symbol. */
6695 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6696 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6697 value += md_pcrel_from (fixP);
6698#endif
6699 }
6700
6701 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6702 and we must not disappoint it. */
252b5132 6703#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6704 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6705 switch (fixP->fx_r_type)
6706 {
6707 case BFD_RELOC_386_PLT32:
3e73aa7c 6708 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6709 /* Make the jump instruction point to the address of the operand. At
6710 runtime we merely add the offset to the actual PLT entry. */
6711 value = -4;
6712 break;
31312f95 6713
13ae64f3
JJ		 6714 case BFD_RELOC_386_TLS_GD:
6715 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6716 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6717 case BFD_RELOC_386_TLS_IE:
6718 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6719 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6720 case BFD_RELOC_X86_64_TLSGD:
6721 case BFD_RELOC_X86_64_TLSLD:
6722 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6723 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6724 value = 0; /* Fully resolved at runtime. No addend. */
6725 /* Fallthrough */
6726 case BFD_RELOC_386_TLS_LE:
6727 case BFD_RELOC_386_TLS_LDO_32:
6728 case BFD_RELOC_386_TLS_LE_32:
6729 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6730 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6731 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6732 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6733 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6734 break;
6735
67a4f2b7
AO		 6736 case BFD_RELOC_386_TLS_DESC_CALL:
6737 case BFD_RELOC_X86_64_TLSDESC_CALL:
6738 value = 0; /* Fully resolved at runtime. No addend. */
6739 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6740 fixP->fx_done = 0;
6741 return;
6742
00f7efb6
JJ		 6743 case BFD_RELOC_386_GOT32:
6744 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6745 value = 0; /* Fully resolved at runtime. No addend. */
6746 break;
47926f60
KH		 6747
6748 case BFD_RELOC_VTABLE_INHERIT:
6749 case BFD_RELOC_VTABLE_ENTRY:
6750 fixP->fx_done = 0;
94f592af 6751 return;
47926f60
KH		 6752
6753 default:
6754 break;
6755 }
6756#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6757 *valP = value;
f86103b7 6758#endif /* !defined (TE_Mach) */
3e73aa7c 6759
3e73aa7c 6760 /* Are we finished with this relocation now? */
c6682705 6761 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6762 fixP->fx_done = 1;
6763 else if (use_rela_relocations)
6764 {
6765 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6766 /* Remember value for tc_gen_reloc. */
6767 fixP->fx_addnumber = value;
3e73aa7c
JH		 6768 value = 0;
6769 }
f86103b7 6770
94f592af 6771 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6772}
252b5132 6773\f
252b5132 6774char *
499ac353 6775md_atof (int type, char *litP, int *sizeP)
252b5132 6776{
499ac353
NC		 6777 /* This outputs the LITTLENUMs in REVERSE order;
6778 in accord with the bigendian 386. */
6779 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6780}
6781\f
2d545b82 6782static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6783
252b5132 6784static char *
e3bb37b5 6785output_invalid (int c)
252b5132 6786{
3882b010 6787 if (ISPRINT (c))
f9f21a03
L		 6788 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6789 "'%c'", c);
252b5132 6790 else
f9f21a03 6791 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6792 "(0x%x)", (unsigned char) c);
252b5132
RH		 6793 return output_invalid_buf;
6794}
6795
af6bdddf 6796/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6797
6798static const reg_entry *
4d1bb795 6799parse_real_register (char *reg_string, char **end_op)
252b5132 6800{
af6bdddf
AM		 6801 char *s = reg_string;
6802 char *p;
252b5132
RH		 6803 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6804 const reg_entry *r;
6805
6806 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6807 if (*s == REGISTER_PREFIX)
6808 ++s;
6809
6810 if (is_space_char (*s))
6811 ++s;
6812
6813 p = reg_name_given;
af6bdddf 6814 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6815 {
6816 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6817 return (const reg_entry *) NULL;
6818 s++;
252b5132
RH		 6819 }
6820
6588847e
DN		 6821 /* For naked regs, make sure that we are not dealing with an identifier.
6822 This prevents confusing an identifier like `eax_var' with register
6823 `eax'. */
6824 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6825 return (const reg_entry *) NULL;
6826
af6bdddf 6827 *end_op = s;
252b5132
RH		 6828
6829 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6830
5f47d35b 6831 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6832 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6833 {
5f47d35b
AM		 6834 if (is_space_char (*s))
6835 ++s;
6836 if (*s == '(')
6837 {
af6bdddf 6838 ++s;
5f47d35b
AM		 6839 if (is_space_char (*s))
6840 ++s;
6841 if (*s >= '0' && *s <= '7')
6842 {
db557034 6843 int fpr = *s - '0';
af6bdddf 6844 ++s;
5f47d35b
AM		 6845 if (is_space_char (*s))
6846 ++s;
6847 if (*s == ')')
6848 {
6849 *end_op = s + 1;
db557034
AM		 6850 r = hash_find (reg_hash, "st(0)");
6851 know (r);
6852 return r + fpr;
5f47d35b 6853 }
5f47d35b 6854 }
47926f60 6855 /* We have "%st(" then garbage. */
5f47d35b
AM		 6856 return (const reg_entry *) NULL;
6857 }
6858 }
6859
db51cc60
L		 6860 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6861 if (r != NULL
6862 && !allow_index_reg
6863 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6864 return (const reg_entry *) NULL;
6865
1ae00879 6866 if (r != NULL
d946b91f 6867 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6868 || r->reg_type.bitfield.reg64)
6869 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6870 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6871 && flag_code != CODE_64BIT)
20f0a1fc 6872 return (const reg_entry *) NULL;
1ae00879 6873
252b5132
RH		 6874 return r;
6875}
4d1bb795
JB		 6876
6877/* REG_STRING starts *before* REGISTER_PREFIX. */
6878
6879static const reg_entry *
6880parse_register (char *reg_string, char **end_op)
6881{
6882 const reg_entry *r;
6883
6884 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6885 r = parse_real_register (reg_string, end_op);
6886 else
6887 r = NULL;
6888 if (!r)
6889 {
6890 char *save = input_line_pointer;
6891 char c;
6892 symbolS *symbolP;
6893
6894 input_line_pointer = reg_string;
6895 c = get_symbol_end ();
6896 symbolP = symbol_find (reg_string);
6897 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6898 {
6899 const expressionS *e = symbol_get_value_expression (symbolP);
6900
6901 know (e->X_op == O_register);
4eed87de 6902 know (e->X_add_number >= 0
c3fe08fa 6903 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6904 r = i386_regtab + e->X_add_number;
6905 *end_op = input_line_pointer;
6906 }
6907 *input_line_pointer = c;
6908 input_line_pointer = save;
6909 }
6910 return r;
6911}
6912
6913int
6914i386_parse_name (char *name, expressionS *e, char *nextcharP)
6915{
6916 const reg_entry *r;
6917 char *end = input_line_pointer;
6918
6919 *end = *nextcharP;
6920 r = parse_register (name, &input_line_pointer);
6921 if (r && end <= input_line_pointer)
6922 {
6923 *nextcharP = *input_line_pointer;
6924 *input_line_pointer = 0;
6925 e->X_op = O_register;
6926 e->X_add_number = r - i386_regtab;
6927 return 1;
6928 }
6929 input_line_pointer = end;
6930 *end = 0;
6931 return 0;
6932}
6933
6934void
6935md_operand (expressionS *e)
6936{
6937 if (*input_line_pointer == REGISTER_PREFIX)
6938 {
6939 char *end;
6940 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6941
6942 if (r)
6943 {
6944 e->X_op = O_register;
6945 e->X_add_number = r - i386_regtab;
6946 input_line_pointer = end;
6947 }
6948 }
6949}
6950
252b5132 6951\f
4cc782b5 6952#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6953const char *md_shortopts = "kVQ:sqn";
252b5132 6954#else
12b55ccc 6955const char *md_shortopts = "qn";
252b5132 6956#endif
6e0b89ee 6957
3e73aa7c 6958#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6959#define OPTION_64 (OPTION_MD_BASE + 1)
6960#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6961#define OPTION_MARCH (OPTION_MD_BASE + 3)
6962#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 6963
99ad8390
NC		 6964struct option md_longopts[] =
6965{
3e73aa7c 6966 {"32", no_argument, NULL, OPTION_32},
99ad8390 6967#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6968 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6969#endif
b3b91714 6970 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6971 {"march", required_argument, NULL, OPTION_MARCH},
6972 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 6973 {NULL, no_argument, NULL, 0}
6974};
6975size_t md_longopts_size = sizeof (md_longopts);
6976
6977int
9103f4f4 6978md_parse_option (int c, char *arg)
252b5132 6979{
9103f4f4
L		 6980 unsigned int i;
6981
252b5132
RH		 6982 switch (c)
6983 {
12b55ccc
L		 6984 case 'n':
6985 optimize_align_code = 0;
6986 break;
6987
a38cf1db
AM		 6988 case 'q':
6989 quiet_warnings = 1;
252b5132
RH		 6990 break;
6991
6992#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 6993 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6994 should be emitted or not. FIXME: Not implemented. */
6995 case 'Q':
252b5132
RH		 6996 break;
6997
6998 /* -V: SVR4 argument to print version ID. */
6999 case 'V':
7000 print_version_id ();
7001 break;
7002
a38cf1db
AM		 7003 /* -k: Ignore for FreeBSD compatibility. */
7004 case 'k':
252b5132 7005 break;
4cc782b5
ILT		 7006
7007 case 's':
7008 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7009 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7010 break;
99ad8390
NC		 7011#endif
7012#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7013 case OPTION_64:
7014 {
7015 const char **list, **l;
7016
3e73aa7c
JH		 7017 list = bfd_target_list ();
7018 for (l = list; *l != NULL; l++)
8620418b 7019 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7020 || strcmp (*l, "coff-x86-64") == 0
7021 || strcmp (*l, "pe-x86-64") == 0
7022 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7023 {
7024 default_arch = "x86_64";
7025 break;
7026 }
3e73aa7c 7027 if (*l == NULL)
6e0b89ee 7028 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7029 free (list);
7030 }
7031 break;
7032#endif
252b5132 7033
6e0b89ee
AM		 7034 case OPTION_32:
7035 default_arch = "i386";
7036 break;
7037
b3b91714
AM		 7038 case OPTION_DIVIDE:
7039#ifdef SVR4_COMMENT_CHARS
7040 {
7041 char *n, *t;
7042 const char *s;
7043
7044 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7045 t = n;
7046 for (s = i386_comment_chars; *s != '\0'; s++)
7047 if (*s != '/')
7048 *t++ = *s;
7049 *t = '\0';
7050 i386_comment_chars = n;
7051 }
7052#endif
7053 break;
7054
9103f4f4
L		 7055 case OPTION_MARCH:
7056 if (*arg == '.')
7057 as_fatal (_("Invalid -march= option: `%s'"), arg);
7058 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7059 {
7060 if (strcmp (arg, cpu_arch [i].name) == 0)
7061 {
ccc9c027 7062 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7063 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7064 if (!cpu_arch_tune_set)
7065 {
7066 cpu_arch_tune = cpu_arch_isa;
7067 cpu_arch_tune_flags = cpu_arch_isa_flags;
7068 }
9103f4f4
L		 7069 break;
7070 }
7071 }
7072 if (i >= ARRAY_SIZE (cpu_arch))
7073 as_fatal (_("Invalid -march= option: `%s'"), arg);
7074 break;
7075
7076 case OPTION_MTUNE:
7077 if (*arg == '.')
7078 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7079 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7080 {
7081 if (strcmp (arg, cpu_arch [i].name) == 0)
7082 {
ccc9c027 7083 cpu_arch_tune_set = 1;
9103f4f4
L		 7084 cpu_arch_tune = cpu_arch [i].type;
7085 cpu_arch_tune_flags = cpu_arch[i].flags;
7086 break;
7087 }
7088 }
7089 if (i >= ARRAY_SIZE (cpu_arch))
7090 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7091 break;
7092
252b5132
RH		 7093 default:
7094 return 0;
7095 }
7096 return 1;
7097}
7098
7099void
7100md_show_usage (stream)
7101 FILE *stream;
7102{
4cc782b5
ILT		 7103#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7104 fprintf (stream, _("\
a38cf1db
AM		 7105 -Q ignored\n\
7106 -V print assembler version number\n\
b3b91714
AM		 7107 -k ignored\n"));
7108#endif
7109 fprintf (stream, _("\
12b55ccc 7110 -n Do not optimize code alignment\n\
b3b91714
AM		 7111 -q quieten some warnings\n"));
7112#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7113 fprintf (stream, _("\
a38cf1db 7114 -s ignored\n"));
b3b91714 7115#endif
751d281c
L		 7116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7117 fprintf (stream, _("\
7118 --32/--64 generate 32bit/64bit code\n"));
7119#endif
b3b91714
AM		 7120#ifdef SVR4_COMMENT_CHARS
7121 fprintf (stream, _("\
7122 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7123#else
7124 fprintf (stream, _("\
b3b91714 7125 --divide ignored\n"));
4cc782b5 7126#endif
9103f4f4
L		 7127 fprintf (stream, _("\
7128 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7129 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7130 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 7131
252b5132
RH		 7132}
7133
3e73aa7c 7134#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7135 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7136
7137/* Pick the target format to use. */
7138
47926f60 7139const char *
e3bb37b5 7140i386_target_format (void)
252b5132 7141{
3e73aa7c 7142 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7143 {
7144 set_code_flag (CODE_64BIT);
c6fb90c8 7145 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7146 {
7147 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7148 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7149 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7150 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7151 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7152 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7153 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7154 cpu_arch_isa_flags.bitfield.cpummx= 1;
7155 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7156 cpu_arch_isa_flags.bitfield.cpusse = 1;
7157 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7158 }
c6fb90c8 7159 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7160 {
7161 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7162 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7163 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7164 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7165 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7166 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7167 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7168 cpu_arch_tune_flags.bitfield.cpummx= 1;
7169 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7170 cpu_arch_tune_flags.bitfield.cpusse = 1;
7171 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7172 }
9103f4f4 7173 }
3e73aa7c 7174 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7175 {
7176 set_code_flag (CODE_32BIT);
c6fb90c8 7177 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7178 {
7179 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7180 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7181 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7182 }
c6fb90c8 7183 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7184 {
7185 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7186 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7187 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7188 }
9103f4f4 7189 }
3e73aa7c
JH		 7190 else
7191 as_fatal (_("Unknown architecture"));
252b5132
RH		 7192 switch (OUTPUT_FLAVOR)
7193 {
872ce6ff
L		 7194#ifdef TE_PEP
7195 case bfd_target_coff_flavour:
7196 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7197 break;
7198#endif
4c63da97
AM		 7199#ifdef OBJ_MAYBE_AOUT
7200 case bfd_target_aout_flavour:
47926f60 7201 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7202#endif
7203#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7204 case bfd_target_coff_flavour:
7205 return "coff-i386";
4c63da97 7206#endif
3e73aa7c 7207#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7208 case bfd_target_elf_flavour:
3e73aa7c 7209 {
e5cb08ac 7210 if (flag_code == CODE_64BIT)
4fa24527
JB		 7211 {
7212 object_64bit = 1;
7213 use_rela_relocations = 1;
7214 }
9d7cbccd 7215 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7216 }
4c63da97 7217#endif
252b5132
RH		 7218 default:
7219 abort ();
7220 return NULL;
7221 }
7222}
7223
47926f60 7224#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7225
7226#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7227void
7228i386_elf_emit_arch_note (void)
a847613f 7229{
718ddfc0 7230 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7231 {
7232 char *p;
7233 asection *seg = now_seg;
7234 subsegT subseg = now_subseg;
7235 Elf_Internal_Note i_note;
7236 Elf_External_Note e_note;
7237 asection *note_secp;
7238 int len;
7239
7240 /* Create the .note section. */
7241 note_secp = subseg_new (".note", 0);
7242 bfd_set_section_flags (stdoutput,
7243 note_secp,
7244 SEC_HAS_CONTENTS | SEC_READONLY);
7245
7246 /* Process the arch string. */
7247 len = strlen (cpu_arch_name);
7248
7249 i_note.namesz = len + 1;
7250 i_note.descsz = 0;
7251 i_note.type = NT_ARCH;
7252 p = frag_more (sizeof (e_note.namesz));
7253 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7254 p = frag_more (sizeof (e_note.descsz));
7255 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7256 p = frag_more (sizeof (e_note.type));
7257 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7258 p = frag_more (len + 1);
7259 strcpy (p, cpu_arch_name);
7260
7261 frag_align (2, 0, 0);
7262
7263 subseg_set (seg, subseg);
7264 }
7265}
7266#endif
252b5132 7267\f
252b5132
RH		 7268symbolS *
7269md_undefined_symbol (name)
7270 char *name;
7271{
18dc2407
ILT		 7272 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7273 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7274 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7275 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7276 {
7277 if (!GOT_symbol)
7278 {
7279 if (symbol_find (name))
7280 as_bad (_("GOT already in symbol table"));
7281 GOT_symbol = symbol_new (name, undefined_section,
7282 (valueT) 0, &zero_address_frag);
7283 };
7284 return GOT_symbol;
7285 }
252b5132
RH		 7286 return 0;
7287}
7288
7289/* Round up a section size to the appropriate boundary. */
47926f60 7290
252b5132
RH		 7291valueT
7292md_section_align (segment, size)
ab9da554 7293 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7294 valueT size;
7295{
4c63da97
AM		 7296#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7297 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7298 {
7299 /* For a.out, force the section size to be aligned. If we don't do
7300 this, BFD will align it for us, but it will not write out the
7301 final bytes of the section. This may be a bug in BFD, but it is
7302 easier to fix it here since that is how the other a.out targets
7303 work. */
7304 int align;
7305
7306 align = bfd_get_section_alignment (stdoutput, segment);
7307 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7308 }
252b5132
RH		 7309#endif
7310
7311 return size;
7312}
7313
7314/* On the i386, PC-relative offsets are relative to the start of the
7315 next instruction. That is, the address of the offset, plus its
7316 size, since the offset is always the last part of the insn. */
7317
7318long
e3bb37b5 7319md_pcrel_from (fixS *fixP)
252b5132
RH		 7320{
7321 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7322}
7323
7324#ifndef I386COFF
7325
7326static void
e3bb37b5 7327s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7328{
29b0f896 7329 int temp;
252b5132 7330
8a75718c
JB		 7331#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7332 if (IS_ELF)
7333 obj_elf_section_change_hook ();
7334#endif
252b5132
RH		 7335 temp = get_absolute_expression ();
7336 subseg_set (bss_section, (subsegT) temp);
7337 demand_empty_rest_of_line ();
7338}
7339
7340#endif
7341
252b5132 7342void
e3bb37b5 7343i386_validate_fix (fixS *fixp)
252b5132
RH		 7344{
7345 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7346 {
23df1078
JH		 7347 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7348 {
4fa24527 7349 if (!object_64bit)
23df1078
JH		 7350 abort ();
7351 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7352 }
7353 else
7354 {
4fa24527 7355 if (!object_64bit)
d6ab8113
JB		 7356 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7357 else
7358 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7359 }
252b5132
RH		 7360 fixp->fx_subsy = 0;
7361 }
7362}
7363
252b5132
RH		 7364arelent *
7365tc_gen_reloc (section, fixp)
ab9da554 7366 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7367 fixS *fixp;
7368{
7369 arelent *rel;
7370 bfd_reloc_code_real_type code;
7371
7372 switch (fixp->fx_r_type)
7373 {
3e73aa7c
JH		 7374 case BFD_RELOC_X86_64_PLT32:
7375 case BFD_RELOC_X86_64_GOT32:
7376 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7377 case BFD_RELOC_386_PLT32:
7378 case BFD_RELOC_386_GOT32:
7379 case BFD_RELOC_386_GOTOFF:
7380 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7381 case BFD_RELOC_386_TLS_GD:
7382 case BFD_RELOC_386_TLS_LDM:
7383 case BFD_RELOC_386_TLS_LDO_32:
7384 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7385 case BFD_RELOC_386_TLS_IE:
7386 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7387 case BFD_RELOC_386_TLS_LE_32:
7388 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7389 case BFD_RELOC_386_TLS_GOTDESC:
7390 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7391 case BFD_RELOC_X86_64_TLSGD:
7392 case BFD_RELOC_X86_64_TLSLD:
7393 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7394 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7395 case BFD_RELOC_X86_64_GOTTPOFF:
7396 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7397 case BFD_RELOC_X86_64_TPOFF64:
7398 case BFD_RELOC_X86_64_GOTOFF64:
7399 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7400 case BFD_RELOC_X86_64_GOT64:
7401 case BFD_RELOC_X86_64_GOTPCREL64:
7402 case BFD_RELOC_X86_64_GOTPC64:
7403 case BFD_RELOC_X86_64_GOTPLT64:
7404 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7405 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7406 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7407 case BFD_RELOC_RVA:
7408 case BFD_RELOC_VTABLE_ENTRY:
7409 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7410#ifdef TE_PE
7411 case BFD_RELOC_32_SECREL:
7412#endif
252b5132
RH		 7413 code = fixp->fx_r_type;
7414 break;
dbbaec26
L		 7415 case BFD_RELOC_X86_64_32S:
7416 if (!fixp->fx_pcrel)
7417 {
7418 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7419 code = fixp->fx_r_type;
7420 break;
7421 }
252b5132 7422 default:
93382f6d 7423 if (fixp->fx_pcrel)
252b5132 7424 {
93382f6d
AM		 7425 switch (fixp->fx_size)
7426 {
7427 default:
b091f402
AM		 7428 as_bad_where (fixp->fx_file, fixp->fx_line,
7429 _("can not do %d byte pc-relative relocation"),
7430 fixp->fx_size);
93382f6d
AM		 7431 code = BFD_RELOC_32_PCREL;
7432 break;
7433 case 1: code = BFD_RELOC_8_PCREL; break;
7434 case 2: code = BFD_RELOC_16_PCREL; break;
7435 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7436#ifdef BFD64
7437 case 8: code = BFD_RELOC_64_PCREL; break;
7438#endif
93382f6d
AM		 7439 }
7440 }
7441 else
7442 {
7443 switch (fixp->fx_size)
7444 {
7445 default:
b091f402
AM		 7446 as_bad_where (fixp->fx_file, fixp->fx_line,
7447 _("can not do %d byte relocation"),
7448 fixp->fx_size);
93382f6d
AM		 7449 code = BFD_RELOC_32;
7450 break;
7451 case 1: code = BFD_RELOC_8; break;
7452 case 2: code = BFD_RELOC_16; break;
7453 case 4: code = BFD_RELOC_32; break;
937149dd 7454#ifdef BFD64
3e73aa7c 7455 case 8: code = BFD_RELOC_64; break;
937149dd 7456#endif
93382f6d 7457 }
252b5132
RH		 7458 }
7459 break;
7460 }
252b5132 7461
d182319b
JB		 7462 if ((code == BFD_RELOC_32
7463 || code == BFD_RELOC_32_PCREL
7464 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7465 && GOT_symbol
7466 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7467 {
4fa24527 7468 if (!object_64bit)
d6ab8113
JB		 7469 code = BFD_RELOC_386_GOTPC;
7470 else
7471 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7472 }
7b81dfbb
AJ		 7473 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7474 && GOT_symbol
7475 && fixp->fx_addsy == GOT_symbol)
7476 {
7477 code = BFD_RELOC_X86_64_GOTPC64;
7478 }
252b5132
RH		 7479
7480 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7481 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7482 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7483
7484 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7485
3e73aa7c
JH		 7486 if (!use_rela_relocations)
7487 {
7488 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7489 vtable entry to be used in the relocation's section offset. */
7490 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7491 rel->address = fixp->fx_offset;
252b5132 7492
c6682705 7493 rel->addend = 0;
3e73aa7c
JH		 7494 }
7495 /* Use the rela in 64bit mode. */
252b5132 7496 else
3e73aa7c 7497 {
062cd5e7
AS		 7498 if (!fixp->fx_pcrel)
7499 rel->addend = fixp->fx_offset;
7500 else
7501 switch (code)
7502 {
7503 case BFD_RELOC_X86_64_PLT32:
7504 case BFD_RELOC_X86_64_GOT32:
7505 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7506 case BFD_RELOC_X86_64_TLSGD:
7507 case BFD_RELOC_X86_64_TLSLD:
7508 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7509 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7510 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7511 rel->addend = fixp->fx_offset - fixp->fx_size;
7512 break;
7513 default:
7514 rel->addend = (section->vma
7515 - fixp->fx_size
7516 + fixp->fx_addnumber
7517 + md_pcrel_from (fixp));
7518 break;
7519 }
3e73aa7c
JH		 7520 }
7521
252b5132
RH		 7522 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7523 if (rel->howto == NULL)
7524 {
7525 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7526 _("cannot represent relocation type %s"),
252b5132
RH		 7527 bfd_get_reloc_code_name (code));
7528 /* Set howto to a garbage value so that we can keep going. */
7529 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7530 assert (rel->howto != NULL);
7531 }
7532
7533 return rel;
7534}
7535
64a0c779
DN		 7536\f
7537/* Parse operands using Intel syntax. This implements a recursive descent
7538 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7539 Programmer's Guide.
7540
7541 FIXME: We do not recognize the full operand grammar defined in the MASM
7542 documentation. In particular, all the structure/union and
7543 high-level macro operands are missing.
7544
7545 Uppercase words are terminals, lower case words are non-terminals.
7546 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7547 bars '|' denote choices. Most grammar productions are implemented in
7548 functions called 'intel_<production>'.
7549
7550 Initial production is 'expr'.
7551
9306ca4a 7552 addOp + | -
64a0c779
DN		 7553
7554 alpha [a-zA-Z]
7555
9306ca4a
JB		 7556 binOp & | AND | \| | OR | ^ | XOR
7557
64a0c779
DN		 7558 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7559
7560 constant digits [[ radixOverride ]]
7561
9306ca4a 7562 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7563
7564 digits decdigit
b77a7acd
AJ		 7565 | digits decdigit
7566 | digits hexdigit
64a0c779
DN		 7567
7568 decdigit [0-9]
7569
9306ca4a
JB		 7570 e04 e04 addOp e05
7571 | e05
7572
7573 e05 e05 binOp e06
b77a7acd 7574 | e06
64a0c779
DN		 7575
7576 e06 e06 mulOp e09
b77a7acd 7577 | e09
64a0c779
DN		 7578
7579 e09 OFFSET e10
a724f0f4
JB		 7580 | SHORT e10
7581 | + e10
7582 | - e10
9306ca4a
JB		 7583 | ~ e10
7584 | NOT e10
64a0c779
DN		 7585 | e09 PTR e10
7586 | e09 : e10
7587 | e10
7588
7589 e10 e10 [ expr ]
b77a7acd 7590 | e11
64a0c779
DN		 7591
7592 e11 ( expr )
b77a7acd 7593 | [ expr ]
64a0c779
DN		 7594 | constant
7595 | dataType
7596 | id
7597 | $
7598 | register
7599
a724f0f4 7600 => expr expr cmpOp e04
9306ca4a 7601 | e04
64a0c779
DN		 7602
7603 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7604 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7605
7606 hexdigit a | b | c | d | e | f
b77a7acd 7607 | A | B | C | D | E | F
64a0c779
DN		 7608
7609 id alpha
b77a7acd 7610 | id alpha
64a0c779
DN		 7611 | id decdigit
7612
9306ca4a 7613 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7614
7615 quote " | '
7616
7617 register specialRegister
b77a7acd 7618 | gpRegister
64a0c779
DN		 7619 | byteRegister
7620
7621 segmentRegister CS | DS | ES | FS | GS | SS
7622
9306ca4a 7623 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7624 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7625 | TR3 | TR4 | TR5 | TR6 | TR7
7626
64a0c779
DN		 7627 We simplify the grammar in obvious places (e.g., register parsing is
7628 done by calling parse_register) and eliminate immediate left recursion
7629 to implement a recursive-descent parser.
7630
a724f0f4
JB		 7631 expr e04 expr'
7632
7633 expr' cmpOp e04 expr'
7634 | Empty
9306ca4a
JB		 7635
7636 e04 e05 e04'
7637
7638 e04' addOp e05 e04'
7639 | Empty
64a0c779
DN		 7640
7641 e05 e06 e05'
7642
9306ca4a 7643 e05' binOp e06 e05'
b77a7acd 7644 | Empty
64a0c779
DN		 7645
7646 e06 e09 e06'
7647
7648 e06' mulOp e09 e06'
b77a7acd 7649 | Empty
64a0c779
DN		 7650
7651 e09 OFFSET e10 e09'
a724f0f4
JB		 7652 | SHORT e10'
7653 | + e10'
7654 | - e10'
7655 | ~ e10'
7656 | NOT e10'
b77a7acd 7657 | e10 e09'
64a0c779
DN		 7658
7659 e09' PTR e10 e09'
b77a7acd 7660 | : e10 e09'
64a0c779
DN		 7661 | Empty
7662
7663 e10 e11 e10'
7664
7665 e10' [ expr ] e10'
b77a7acd 7666 | Empty
64a0c779
DN		 7667
7668 e11 ( expr )
b77a7acd 7669 | [ expr ]
64a0c779
DN		 7670 | BYTE
7671 | WORD
7672 | DWORD
9306ca4a 7673 | FWORD
64a0c779 7674 | QWORD
9306ca4a
JB		 7675 | TBYTE
7676 | OWORD
7677 | XMMWORD
64a0c779
DN		 7678 | .
7679 | $
7680 | register
7681 | id
7682 | constant */
7683
7684/* Parsing structure for the intel syntax parser. Used to implement the
7685 semantic actions for the operand grammar. */
7686struct intel_parser_s
7687 {
7688 char *op_string; /* The string being parsed. */
7689 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7690 int op_modifier; /* Operand modifier. */
64a0c779 7691 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7692 int in_offset; /* >=1 if parsing operand of offset. */
7693 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7694 const reg_entry *reg; /* Last register reference found. */
7695 char *disp; /* Displacement string being built. */
a724f0f4 7696 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7697 };
7698
7699static struct intel_parser_s intel_parser;
7700
7701/* Token structure for parsing intel syntax. */
7702struct intel_token
7703 {
7704 int code; /* Token code. */
7705 const reg_entry *reg; /* Register entry for register tokens. */
7706 char *str; /* String representation. */
7707 };
7708
7709static struct intel_token cur_token, prev_token;
7710
50705ef4
AM		 7711/* Token codes for the intel parser. Since T_SHORT is already used
7712 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7713#define T_NIL -1
7714#define T_CONST 1
7715#define T_REG 2
7716#define T_BYTE 3
7717#define T_WORD 4
9306ca4a
JB		 7718#define T_DWORD 5
7719#define T_FWORD 6
7720#define T_QWORD 7
7721#define T_TBYTE 8
7722#define T_XMMWORD 9
50705ef4 7723#undef T_SHORT
9306ca4a
JB		 7724#define T_SHORT 10
7725#define T_OFFSET 11
7726#define T_PTR 12
7727#define T_ID 13
7728#define T_SHL 14
7729#define T_SHR 15
64a0c779
DN		 7730
7731/* Prototypes for intel parser functions. */
e3bb37b5
L		 7732static int intel_match_token (int);
7733static void intel_putback_token (void);
7734static void intel_get_token (void);
7735static int intel_expr (void);
7736static int intel_e04 (void);
7737static int intel_e05 (void);
7738static int intel_e06 (void);
7739static int intel_e09 (void);
7740static int intel_e10 (void);
7741static int intel_e11 (void);
64a0c779 7742
64a0c779 7743static int
e3bb37b5 7744i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7745{
7746 int ret;
7747 char *p;
7748
a724f0f4
JB		 7749 p = intel_parser.op_string = xstrdup (operand_string);
7750 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7751
7752 for (;;)
64a0c779 7753 {
a724f0f4
JB		 7754 /* Initialize token holders. */
7755 cur_token.code = prev_token.code = T_NIL;
7756 cur_token.reg = prev_token.reg = NULL;
7757 cur_token.str = prev_token.str = NULL;
7758
7759 /* Initialize parser structure. */
7760 intel_parser.got_a_float = got_a_float;
7761 intel_parser.op_modifier = 0;
7762 intel_parser.is_mem = 0;
7763 intel_parser.in_offset = 0;
7764 intel_parser.in_bracket = 0;
7765 intel_parser.reg = NULL;
7766 intel_parser.disp[0] = '\0';
7767 intel_parser.next_operand = NULL;
7768
7769 /* Read the first token and start the parser. */
7770 intel_get_token ();
7771 ret = intel_expr ();
7772
7773 if (!ret)
7774 break;
7775
9306ca4a
JB		 7776 if (cur_token.code != T_NIL)
7777 {
7778 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7779 current_templates->start->name, cur_token.str);
7780 ret = 0;
7781 }
64a0c779
DN		 7782 /* If we found a memory reference, hand it over to i386_displacement
7783 to fill in the rest of the operand fields. */
9306ca4a 7784 else if (intel_parser.is_mem)
64a0c779
DN		 7785 {
7786 if ((i.mem_operands == 1
40fb9820 7787 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7788 || i.mem_operands == 2)
7789 {
7790 as_bad (_("too many memory references for '%s'"),
7791 current_templates->start->name);
7792 ret = 0;
7793 }
7794 else
7795 {
7796 char *s = intel_parser.disp;
7797 i.mem_operands++;
7798
a724f0f4
JB		 7799 if (!quiet_warnings && intel_parser.is_mem < 0)
7800 /* See the comments in intel_bracket_expr. */
7801 as_warn (_("Treating `%s' as memory reference"), operand_string);
7802
64a0c779
DN		 7803 /* Add the displacement expression. */
7804 if (*s != '\0')
a4622f40
AM		 7805 ret = i386_displacement (s, s + strlen (s));
7806 if (ret)
a724f0f4
JB		 7807 {
7808 /* Swap base and index in 16-bit memory operands like
7809 [si+bx]. Since i386_index_check is also used in AT&T
7810 mode we have to do that here. */
7811 if (i.base_reg
7812 && i.index_reg
40fb9820
L		 7813 && i.base_reg->reg_type.bitfield.reg16
7814 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7815 && i.base_reg->reg_num >= 6
7816 && i.index_reg->reg_num < 6)
7817 {
7818 const reg_entry *base = i.index_reg;
7819
7820 i.index_reg = i.base_reg;
7821 i.base_reg = base;
7822 }
7823 ret = i386_index_check (operand_string);
7824 }
64a0c779
DN		 7825 }
7826 }
7827
7828 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7829 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7830 || intel_parser.reg == NULL)
7831 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7832
7833 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7834 ret = 0;
a724f0f4
JB		 7835 if (!ret || !intel_parser.next_operand)
7836 break;
7837 intel_parser.op_string = intel_parser.next_operand;
7838 this_operand = i.operands++;
64a0c779
DN		 7839 }
7840
7841 free (p);
7842 free (intel_parser.disp);
7843
7844 return ret;
7845}
7846
a724f0f4
JB		 7847#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7848
7849/* expr e04 expr'
7850
7851 expr' cmpOp e04 expr'
7852 | Empty */
64a0c779 7853static int
e3bb37b5 7854intel_expr (void)
64a0c779 7855{
a724f0f4
JB		 7856 /* XXX Implement the comparison operators. */
7857 return intel_e04 ();
9306ca4a
JB		 7858}
7859
a724f0f4 7860/* e04 e05 e04'
9306ca4a 7861
a724f0f4 7862 e04' addOp e05 e04'
9306ca4a
JB		 7863 | Empty */
7864static int
e3bb37b5 7865intel_e04 (void)
9306ca4a 7866{
a724f0f4 7867 int nregs = -1;
9306ca4a 7868
a724f0f4 7869 for (;;)
9306ca4a 7870 {
a724f0f4
JB		 7871 if (!intel_e05())
7872 return 0;
9306ca4a 7873
a724f0f4
JB		 7874 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7875 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7876
a724f0f4
JB		 7877 if (cur_token.code == '+')
7878 nregs = -1;
7879 else if (cur_token.code == '-')
7880 nregs = NUM_ADDRESS_REGS;
7881 else
7882 return 1;
64a0c779 7883
a724f0f4
JB		 7884 strcat (intel_parser.disp, cur_token.str);
7885 intel_match_token (cur_token.code);
7886 }
64a0c779
DN		 7887}
7888
64a0c779
DN		 7889/* e05 e06 e05'
7890
9306ca4a 7891 e05' binOp e06 e05'
64a0c779
DN		 7892 | Empty */
7893static int
e3bb37b5 7894intel_e05 (void)
64a0c779 7895{
a724f0f4 7896 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7897
a724f0f4 7898 for (;;)
64a0c779 7899 {
a724f0f4
JB		 7900 if (!intel_e06())
7901 return 0;
7902
4eed87de
AM		 7903 if (cur_token.code == '&'
7904 || cur_token.code == '|'
7905 || cur_token.code == '^')
a724f0f4
JB		 7906 {
7907 char str[2];
7908
7909 str[0] = cur_token.code;
7910 str[1] = 0;
7911 strcat (intel_parser.disp, str);
7912 }
7913 else
7914 break;
9306ca4a 7915
64a0c779
DN		 7916 intel_match_token (cur_token.code);
7917
a724f0f4
JB		 7918 if (nregs < 0)
7919 nregs = ~nregs;
64a0c779 7920 }
a724f0f4
JB		 7921 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7922 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7923 return 1;
4a1805b1 7924}
64a0c779
DN		 7925
7926/* e06 e09 e06'
7927
7928 e06' mulOp e09 e06'
b77a7acd 7929 | Empty */
64a0c779 7930static int
e3bb37b5 7931intel_e06 (void)
64a0c779 7932{
a724f0f4 7933 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7934
a724f0f4 7935 for (;;)
64a0c779 7936 {
a724f0f4
JB		 7937 if (!intel_e09())
7938 return 0;
9306ca4a 7939
4eed87de
AM		 7940 if (cur_token.code == '*'
7941 || cur_token.code == '/'
7942 || cur_token.code == '%')
a724f0f4
JB		 7943 {
7944 char str[2];
9306ca4a 7945
a724f0f4
JB		 7946 str[0] = cur_token.code;
7947 str[1] = 0;
7948 strcat (intel_parser.disp, str);
7949 }
7950 else if (cur_token.code == T_SHL)
7951 strcat (intel_parser.disp, "<<");
7952 else if (cur_token.code == T_SHR)
7953 strcat (intel_parser.disp, ">>");
7954 else
7955 break;
9306ca4a 7956
64e74474 7957 intel_match_token (cur_token.code);
64a0c779 7958
a724f0f4
JB		 7959 if (nregs < 0)
7960 nregs = ~nregs;
64a0c779 7961 }
a724f0f4
JB		 7962 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7963 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
7964 return 1;
64a0c779
DN		 7965}
7966
a724f0f4
JB		 7967/* e09 OFFSET e09
7968 | SHORT e09
7969 | + e09
7970 | - e09
7971 | ~ e09
7972 | NOT e09
9306ca4a
JB		 7973 | e10 e09'
7974
64a0c779 7975 e09' PTR e10 e09'
b77a7acd 7976 | : e10 e09'
64a0c779
DN		 7977 | Empty */
7978static int
e3bb37b5 7979intel_e09 (void)
64a0c779 7980{
a724f0f4
JB		 7981 int nregs = ~NUM_ADDRESS_REGS;
7982 int in_offset = 0;
7983
7984 for (;;)
64a0c779 7985 {
a724f0f4
JB		 7986 /* Don't consume constants here. */
7987 if (cur_token.code == '+' || cur_token.code == '-')
7988 {
7989 /* Need to look one token ahead - if the next token
7990 is a constant, the current token is its sign. */
7991 int next_code;
7992
7993 intel_match_token (cur_token.code);
7994 next_code = cur_token.code;
7995 intel_putback_token ();
7996 if (next_code == T_CONST)
7997 break;
7998 }
7999
8000 /* e09 OFFSET e09 */
8001 if (cur_token.code == T_OFFSET)
8002 {
8003 if (!in_offset++)
8004 ++intel_parser.in_offset;
8005 }
8006
8007 /* e09 SHORT e09 */
8008 else if (cur_token.code == T_SHORT)
8009 intel_parser.op_modifier |= 1 << T_SHORT;
8010
8011 /* e09 + e09 */
8012 else if (cur_token.code == '+')
8013 strcat (intel_parser.disp, "+");
8014
8015 /* e09 - e09
8016 | ~ e09
8017 | NOT e09 */
8018 else if (cur_token.code == '-' || cur_token.code == '~')
8019 {
8020 char str[2];
64a0c779 8021
a724f0f4
JB		 8022 if (nregs < 0)
8023 nregs = ~nregs;
8024 str[0] = cur_token.code;
8025 str[1] = 0;
8026 strcat (intel_parser.disp, str);
8027 }
8028
8029 /* e09 e10 e09' */
8030 else
8031 break;
8032
8033 intel_match_token (cur_token.code);
64a0c779
DN		 8034 }
8035
a724f0f4 8036 for (;;)
9306ca4a 8037 {
a724f0f4
JB		 8038 if (!intel_e10 ())
8039 return 0;
9306ca4a 8040
a724f0f4
JB		 8041 /* e09' PTR e10 e09' */
8042 if (cur_token.code == T_PTR)
8043 {
8044 char suffix;
9306ca4a 8045
a724f0f4
JB		 8046 if (prev_token.code == T_BYTE)
8047 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 8048
a724f0f4
JB		 8049 else if (prev_token.code == T_WORD)
8050 {
8051 if (current_templates->start->name[0] == 'l'
8052 && current_templates->start->name[2] == 's'
8053 && current_templates->start->name[3] == 0)
8054 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8055 else if (intel_parser.got_a_float == 2) /* "fi..." */
8056 suffix = SHORT_MNEM_SUFFIX;
8057 else
8058 suffix = WORD_MNEM_SUFFIX;
8059 }
64a0c779 8060
a724f0f4
JB		 8061 else if (prev_token.code == T_DWORD)
8062 {
8063 if (current_templates->start->name[0] == 'l'
8064 && current_templates->start->name[2] == 's'
8065 && current_templates->start->name[3] == 0)
8066 suffix = WORD_MNEM_SUFFIX;
8067 else if (flag_code == CODE_16BIT
40fb9820
L		 8068 && (current_templates->start->opcode_modifier.jump
8069 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8070 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8071 else if (intel_parser.got_a_float == 1) /* "f..." */
8072 suffix = SHORT_MNEM_SUFFIX;
8073 else
8074 suffix = LONG_MNEM_SUFFIX;
8075 }
9306ca4a 8076
a724f0f4
JB		 8077 else if (prev_token.code == T_FWORD)
8078 {
8079 if (current_templates->start->name[0] == 'l'
8080 && current_templates->start->name[2] == 's'
8081 && current_templates->start->name[3] == 0)
8082 suffix = LONG_MNEM_SUFFIX;
8083 else if (!intel_parser.got_a_float)
8084 {
8085 if (flag_code == CODE_16BIT)
8086 add_prefix (DATA_PREFIX_OPCODE);
8087 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8088 }
8089 else
8090 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8091 }
64a0c779 8092
a724f0f4
JB		 8093 else if (prev_token.code == T_QWORD)
8094 {
8095 if (intel_parser.got_a_float == 1) /* "f..." */
8096 suffix = LONG_MNEM_SUFFIX;
8097 else
8098 suffix = QWORD_MNEM_SUFFIX;
8099 }
64a0c779 8100
a724f0f4
JB		 8101 else if (prev_token.code == T_TBYTE)
8102 {
8103 if (intel_parser.got_a_float == 1)
8104 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8105 else
8106 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8107 }
9306ca4a 8108
a724f0f4 8109 else if (prev_token.code == T_XMMWORD)
9306ca4a 8110 {
a724f0f4
JB		 8111 /* XXX ignored for now, but accepted since gcc uses it */
8112 suffix = 0;
9306ca4a 8113 }
64a0c779 8114
f16b83df 8115 else
a724f0f4
JB		 8116 {
8117 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8118 return 0;
8119 }
8120
435acd52
JB		 8121 /* Operands for jump/call using 'ptr' notation denote absolute
8122 addresses. */
40fb9820
L		 8123 if (current_templates->start->opcode_modifier.jump
8124 || current_templates->start->opcode_modifier.jumpdword)
8125 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8126
a724f0f4
JB		 8127 if (current_templates->start->base_opcode == 0x8d /* lea */)
8128 ;
8129 else if (!i.suffix)
8130 i.suffix = suffix;
8131 else if (i.suffix != suffix)
8132 {
8133 as_bad (_("Conflicting operand modifiers"));
8134 return 0;
8135 }
64a0c779 8136
9306ca4a
JB		 8137 }
8138
a724f0f4
JB		 8139 /* e09' : e10 e09' */
8140 else if (cur_token.code == ':')
9306ca4a 8141 {
a724f0f4
JB		 8142 if (prev_token.code != T_REG)
8143 {
8144 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8145 segment/group identifier (which we don't have), using comma
8146 as the operand separator there is even less consistent, since
8147 there all branches only have a single operand. */
8148 if (this_operand != 0
8149 || intel_parser.in_offset
8150 || intel_parser.in_bracket
40fb9820
L		 8151 || (!current_templates->start->opcode_modifier.jump
8152 && !current_templates->start->opcode_modifier.jumpdword
8153 && !current_templates->start->opcode_modifier.jumpintersegment
8154 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8155 return intel_match_token (T_NIL);
8156 /* Remember the start of the 2nd operand and terminate 1st
8157 operand here.
8158 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8159 another expression), but it gets at least the simplest case
8160 (a plain number or symbol on the left side) right. */
8161 intel_parser.next_operand = intel_parser.op_string;
8162 *--intel_parser.op_string = '\0';
8163 return intel_match_token (':');
8164 }
9306ca4a 8165 }
64a0c779 8166
a724f0f4 8167 /* e09' Empty */
64a0c779 8168 else
a724f0f4 8169 break;
64a0c779 8170
a724f0f4
JB		 8171 intel_match_token (cur_token.code);
8172
8173 }
8174
8175 if (in_offset)
8176 {
8177 --intel_parser.in_offset;
8178 if (nregs < 0)
8179 nregs = ~nregs;
8180 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8181 {
a724f0f4 8182 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8183 return 0;
8184 }
a724f0f4
JB		 8185 intel_parser.op_modifier |= 1 << T_OFFSET;
8186 }
9306ca4a 8187
a724f0f4
JB		 8188 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8189 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8190 return 1;
8191}
64a0c779 8192
a724f0f4 8193static int
e3bb37b5 8194intel_bracket_expr (void)
a724f0f4
JB		 8195{
8196 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8197 const char *start = intel_parser.op_string;
8198 int len;
8199
8200 if (i.op[this_operand].regs)
8201 return intel_match_token (T_NIL);
8202
8203 intel_match_token ('[');
8204
8205 /* Mark as a memory operand only if it's not already known to be an
8206 offset expression. If it's an offset expression, we need to keep
8207 the brace in. */
8208 if (!intel_parser.in_offset)
8209 {
8210 ++intel_parser.in_bracket;
435acd52
JB		 8211
8212 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8213 if (current_templates->start->opcode_modifier.jump
8214 || current_templates->start->opcode_modifier.jumpdword)
8215 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8216
a724f0f4
JB		 8217 /* Unfortunately gas always diverged from MASM in a respect that can't
8218 be easily fixed without risking to break code sequences likely to be
8219 encountered (the testsuite even check for this): MASM doesn't consider
8220 an expression inside brackets unconditionally as a memory reference.
8221 When that is e.g. a constant, an offset expression, or the sum of the
8222 two, this is still taken as a constant load. gas, however, always
8223 treated these as memory references. As a compromise, we'll try to make
8224 offset expressions inside brackets work the MASM way (since that's
8225 less likely to be found in real world code), but make constants alone
8226 continue to work the traditional gas way. In either case, issue a
8227 warning. */
8228 intel_parser.op_modifier &= ~was_offset;
64a0c779 8229 }
a724f0f4 8230 else
64e74474 8231 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8232
8233 /* Add a '+' to the displacement string if necessary. */
8234 if (*intel_parser.disp != '\0'
8235 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8236 strcat (intel_parser.disp, "+");
64a0c779 8237
a724f0f4
JB		 8238 if (intel_expr ()
8239 && (len = intel_parser.op_string - start - 1,
8240 intel_match_token (']')))
64a0c779 8241 {
a724f0f4
JB		 8242 /* Preserve brackets when the operand is an offset expression. */
8243 if (intel_parser.in_offset)
8244 strcat (intel_parser.disp, "]");
8245 else
8246 {
8247 --intel_parser.in_bracket;
8248 if (i.base_reg || i.index_reg)
8249 intel_parser.is_mem = 1;
8250 if (!intel_parser.is_mem)
8251 {
8252 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8253 /* Defer the warning until all of the operand was parsed. */
8254 intel_parser.is_mem = -1;
8255 else if (!quiet_warnings)
4eed87de
AM		 8256 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8257 len, start, len, start);
a724f0f4
JB		 8258 }
8259 }
8260 intel_parser.op_modifier |= was_offset;
64a0c779 8261
a724f0f4 8262 return 1;
64a0c779 8263 }
a724f0f4 8264 return 0;
64a0c779
DN		 8265}
8266
8267/* e10 e11 e10'
8268
8269 e10' [ expr ] e10'
b77a7acd 8270 | Empty */
64a0c779 8271static int
e3bb37b5 8272intel_e10 (void)
64a0c779 8273{
a724f0f4
JB		 8274 if (!intel_e11 ())
8275 return 0;
64a0c779 8276
a724f0f4 8277 while (cur_token.code == '[')
64a0c779 8278 {
a724f0f4 8279 if (!intel_bracket_expr ())
21d6c4af 8280 return 0;
64a0c779
DN		 8281 }
8282
a724f0f4 8283 return 1;
64a0c779
DN		 8284}
8285
64a0c779 8286/* e11 ( expr )
b77a7acd 8287 | [ expr ]
64a0c779
DN		 8288 | BYTE
8289 | WORD
8290 | DWORD
9306ca4a 8291 | FWORD
64a0c779 8292 | QWORD
9306ca4a
JB		 8293 | TBYTE
8294 | OWORD
8295 | XMMWORD
4a1805b1 8296 | $
64a0c779
DN		 8297 | .
8298 | register
8299 | id
8300 | constant */
8301static int
e3bb37b5 8302intel_e11 (void)
64a0c779 8303{
a724f0f4 8304 switch (cur_token.code)
64a0c779 8305 {
a724f0f4
JB		 8306 /* e11 ( expr ) */
8307 case '(':
64a0c779
DN		 8308 intel_match_token ('(');
8309 strcat (intel_parser.disp, "(");
8310
8311 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8312 {
8313 strcat (intel_parser.disp, ")");
8314 return 1;
8315 }
a724f0f4 8316 return 0;
4a1805b1 8317
a724f0f4
JB		 8318 /* e11 [ expr ] */
8319 case '[':
a724f0f4 8320 return intel_bracket_expr ();
64a0c779 8321
a724f0f4
JB		 8322 /* e11 $
8323 | . */
8324 case '.':
64a0c779
DN		 8325 strcat (intel_parser.disp, cur_token.str);
8326 intel_match_token (cur_token.code);
21d6c4af
DN		 8327
8328 /* Mark as a memory operand only if it's not already known to be an
8329 offset expression. */
a724f0f4 8330 if (!intel_parser.in_offset)
21d6c4af 8331 intel_parser.is_mem = 1;
64a0c779
DN		 8332
8333 return 1;
64a0c779 8334
a724f0f4
JB		 8335 /* e11 register */
8336 case T_REG:
8337 {
8338 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8339
a724f0f4 8340 intel_match_token (T_REG);
64a0c779 8341
a724f0f4
JB		 8342 /* Check for segment change. */
8343 if (cur_token.code == ':')
8344 {
40fb9820
L		 8345 if (!reg->reg_type.bitfield.sreg2
8346 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8347 {
4eed87de
AM		 8348 as_bad (_("`%s' is not a valid segment register"),
8349 reg->reg_name);
a724f0f4
JB		 8350 return 0;
8351 }
8352 else if (i.seg[i.mem_operands])
8353 as_warn (_("Extra segment override ignored"));
8354 else
8355 {
8356 if (!intel_parser.in_offset)
8357 intel_parser.is_mem = 1;
8358 switch (reg->reg_num)
8359 {
8360 case 0:
8361 i.seg[i.mem_operands] = &es;
8362 break;
8363 case 1:
8364 i.seg[i.mem_operands] = &cs;
8365 break;
8366 case 2:
8367 i.seg[i.mem_operands] = &ss;
8368 break;
8369 case 3:
8370 i.seg[i.mem_operands] = &ds;
8371 break;
8372 case 4:
8373 i.seg[i.mem_operands] = &fs;
8374 break;
8375 case 5:
8376 i.seg[i.mem_operands] = &gs;
8377 break;
8378 }
8379 }
8380 }
64a0c779 8381
a724f0f4
JB		 8382 /* Not a segment register. Check for register scaling. */
8383 else if (cur_token.code == '*')
8384 {
8385 if (!intel_parser.in_bracket)
8386 {
8387 as_bad (_("Register scaling only allowed in memory operands"));
8388 return 0;
8389 }
64a0c779 8390
40fb9820 8391 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8392 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8393 else if (i.index_reg)
8394 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8395
a724f0f4
JB		 8396 /* What follows must be a valid scale. */
8397 intel_match_token ('*');
8398 i.index_reg = reg;
40fb9820 8399 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8400
a724f0f4
JB		 8401 /* Set the scale after setting the register (otherwise,
8402 i386_scale will complain) */
8403 if (cur_token.code == '+' || cur_token.code == '-')
8404 {
8405 char *str, sign = cur_token.code;
8406 intel_match_token (cur_token.code);
8407 if (cur_token.code != T_CONST)
8408 {
8409 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8410 cur_token.str);
8411 return 0;
8412 }
8413 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8414 strcpy (str + 1, cur_token.str);
8415 *str = sign;
8416 if (!i386_scale (str))
8417 return 0;
8418 free (str);
8419 }
8420 else if (!i386_scale (cur_token.str))
64a0c779 8421 return 0;
a724f0f4
JB		 8422 intel_match_token (cur_token.code);
8423 }
64a0c779 8424
a724f0f4
JB		 8425 /* No scaling. If this is a memory operand, the register is either a
8426 base register (first occurrence) or an index register (second
8427 occurrence). */
7b0441f6 8428 else if (intel_parser.in_bracket)
a724f0f4 8429 {
64a0c779 8430
a724f0f4
JB		 8431 if (!i.base_reg)
8432 i.base_reg = reg;
8433 else if (!i.index_reg)
8434 i.index_reg = reg;
8435 else
8436 {
8437 as_bad (_("Too many register references in memory operand"));
8438 return 0;
8439 }
64a0c779 8440
40fb9820 8441 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8442 }
4a1805b1 8443
4d1bb795
JB		 8444 /* It's neither base nor index. */
8445 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8446 {
40fb9820
L		 8447 i386_operand_type temp = reg->reg_type;
8448 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8449 i.types[this_operand] = operand_type_or (i.types[this_operand],
8450 temp);
a724f0f4
JB		 8451 i.op[this_operand].regs = reg;
8452 i.reg_operands++;
8453 }
8454 else
8455 {
8456 as_bad (_("Invalid use of register"));
8457 return 0;
8458 }
64a0c779 8459
a724f0f4
JB		 8460 /* Since registers are not part of the displacement string (except
8461 when we're parsing offset operands), we may need to remove any
8462 preceding '+' from the displacement string. */
8463 if (*intel_parser.disp != '\0'
8464 && !intel_parser.in_offset)
8465 {
8466 char *s = intel_parser.disp;
8467 s += strlen (s) - 1;
8468 if (*s == '+')
8469 *s = '\0';
8470 }
4a1805b1 8471
a724f0f4
JB		 8472 return 1;
8473 }
8474
8475 /* e11 BYTE
8476 | WORD
8477 | DWORD
8478 | FWORD
8479 | QWORD
8480 | TBYTE
8481 | OWORD
8482 | XMMWORD */
8483 case T_BYTE:
8484 case T_WORD:
8485 case T_DWORD:
8486 case T_FWORD:
8487 case T_QWORD:
8488 case T_TBYTE:
8489 case T_XMMWORD:
8490 intel_match_token (cur_token.code);
64a0c779 8491
a724f0f4
JB		 8492 if (cur_token.code == T_PTR)
8493 return 1;
8494
8495 /* It must have been an identifier. */
8496 intel_putback_token ();
8497 cur_token.code = T_ID;
8498 /* FALLTHRU */
8499
8500 /* e11 id
8501 | constant */
8502 case T_ID:
8503 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8504 {
8505 symbolS *symbolP;
8506
a724f0f4
JB		 8507 /* The identifier represents a memory reference only if it's not
8508 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8509 symbolP = symbol_find(cur_token.str);
8510 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8511 intel_parser.is_mem = 1;
8512 }
a724f0f4 8513 /* FALLTHRU */
64a0c779 8514
a724f0f4
JB		 8515 case T_CONST:
8516 case '-':
8517 case '+':
8518 {
8519 char *save_str, sign = 0;
64a0c779 8520
a724f0f4
JB		 8521 /* Allow constants that start with `+' or `-'. */
8522 if (cur_token.code == '-' || cur_token.code == '+')
8523 {
8524 sign = cur_token.code;
8525 intel_match_token (cur_token.code);
8526 if (cur_token.code != T_CONST)
8527 {
8528 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8529 cur_token.str);
8530 return 0;
8531 }
8532 }
64a0c779 8533
a724f0f4
JB		 8534 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8535 strcpy (save_str + !!sign, cur_token.str);
8536 if (sign)
8537 *save_str = sign;
64a0c779 8538
a724f0f4
JB		 8539 /* Get the next token to check for register scaling. */
8540 intel_match_token (cur_token.code);
64a0c779 8541
4eed87de
AM		 8542 /* Check if this constant is a scaling factor for an
8543 index register. */
a724f0f4
JB		 8544 if (cur_token.code == '*')
8545 {
8546 if (intel_match_token ('*') && cur_token.code == T_REG)
8547 {
8548 const reg_entry *reg = cur_token.reg;
8549
8550 if (!intel_parser.in_bracket)
8551 {
4eed87de
AM		 8552 as_bad (_("Register scaling only allowed "
8553 "in memory operands"));
a724f0f4
JB		 8554 return 0;
8555 }
8556
4eed87de
AM		 8557 /* Disallow things like [1*si].
8558 sp and esp are invalid as index. */
40fb9820 8559 if (reg->reg_type.bitfield.reg16)
4eed87de 8560 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8561 else if (i.index_reg)
4eed87de 8562 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8563
8564 /* The constant is followed by `* reg', so it must be
8565 a valid scale. */
8566 i.index_reg = reg;
40fb9820 8567 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8568
8569 /* Set the scale after setting the register (otherwise,
8570 i386_scale will complain) */
8571 if (!i386_scale (save_str))
64a0c779 8572 return 0;
a724f0f4
JB		 8573 intel_match_token (T_REG);
8574
8575 /* Since registers are not part of the displacement
8576 string, we may need to remove any preceding '+' from
8577 the displacement string. */
8578 if (*intel_parser.disp != '\0')
8579 {
8580 char *s = intel_parser.disp;
8581 s += strlen (s) - 1;
8582 if (*s == '+')
8583 *s = '\0';
8584 }
8585
8586 free (save_str);
8587
8588 return 1;
8589 }
64a0c779 8590
a724f0f4
JB		 8591 /* The constant was not used for register scaling. Since we have
8592 already consumed the token following `*' we now need to put it
8593 back in the stream. */
64a0c779 8594 intel_putback_token ();
a724f0f4 8595 }
64a0c779 8596
a724f0f4
JB		 8597 /* Add the constant to the displacement string. */
8598 strcat (intel_parser.disp, save_str);
8599 free (save_str);
64a0c779 8600
a724f0f4
JB		 8601 return 1;
8602 }
64a0c779
DN		 8603 }
8604
64a0c779
DN		 8605 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8606 return 0;
8607}
8608
64a0c779
DN		 8609/* Match the given token against cur_token. If they match, read the next
8610 token from the operand string. */
8611static int
e3bb37b5 8612intel_match_token (int code)
64a0c779
DN		 8613{
8614 if (cur_token.code == code)
8615 {
8616 intel_get_token ();
8617 return 1;
8618 }
8619 else
8620 {
0477af35 8621 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8622 return 0;
8623 }
8624}
8625
64a0c779
DN		 8626/* Read a new token from intel_parser.op_string and store it in cur_token. */
8627static void
e3bb37b5 8628intel_get_token (void)
64a0c779
DN		 8629{
8630 char *end_op;
8631 const reg_entry *reg;
8632 struct intel_token new_token;
8633
8634 new_token.code = T_NIL;
8635 new_token.reg = NULL;
8636 new_token.str = NULL;
8637
4a1805b1 8638 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8639 cur_token to prev_token. */
8640 if (prev_token.str)
8641 free (prev_token.str);
8642
8643 prev_token = cur_token;
8644
8645 /* Skip whitespace. */
8646 while (is_space_char (*intel_parser.op_string))
8647 intel_parser.op_string++;
8648
8649 /* Return an empty token if we find nothing else on the line. */
8650 if (*intel_parser.op_string == '\0')
8651 {
8652 cur_token = new_token;
8653 return;
8654 }
8655
8656 /* The new token cannot be larger than the remainder of the operand
8657 string. */
a724f0f4 8658 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8659 new_token.str[0] = '\0';
8660
8661 if (strchr ("0123456789", *intel_parser.op_string))
8662 {
8663 char *p = new_token.str;
8664 char *q = intel_parser.op_string;
8665 new_token.code = T_CONST;
8666
8667 /* Allow any kind of identifier char to encompass floating point and
8668 hexadecimal numbers. */
8669 while (is_identifier_char (*q))
8670 *p++ = *q++;
8671 *p = '\0';
8672
8673 /* Recognize special symbol names [0-9][bf]. */
8674 if (strlen (intel_parser.op_string) == 2
4a1805b1 8675 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8676 || intel_parser.op_string[1] == 'f'))
8677 new_token.code = T_ID;
8678 }
8679
4d1bb795 8680 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8681 {
4d1bb795
JB		 8682 size_t len = end_op - intel_parser.op_string;
8683
64a0c779
DN		 8684 new_token.code = T_REG;
8685 new_token.reg = reg;
8686
4d1bb795
JB		 8687 memcpy (new_token.str, intel_parser.op_string, len);
8688 new_token.str[len] = '\0';
64a0c779
DN		 8689 }
8690
8691 else if (is_identifier_char (*intel_parser.op_string))
8692 {
8693 char *p = new_token.str;
8694 char *q = intel_parser.op_string;
8695
8696 /* A '.' or '$' followed by an identifier char is an identifier.
8697 Otherwise, it's operator '.' followed by an expression. */
8698 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8699 {
9306ca4a
JB		 8700 new_token.code = '.';
8701 new_token.str[0] = '.';
64a0c779
DN		 8702 new_token.str[1] = '\0';
8703 }
8704 else
8705 {
8706 while (is_identifier_char (*q) || *q == '@')
8707 *p++ = *q++;
8708 *p = '\0';
8709
9306ca4a
JB		 8710 if (strcasecmp (new_token.str, "NOT") == 0)
8711 new_token.code = '~';
8712
8713 else if (strcasecmp (new_token.str, "MOD") == 0)
8714 new_token.code = '%';
8715
8716 else if (strcasecmp (new_token.str, "AND") == 0)
8717 new_token.code = '&';
8718
8719 else if (strcasecmp (new_token.str, "OR") == 0)
8720 new_token.code = '|';
8721
8722 else if (strcasecmp (new_token.str, "XOR") == 0)
8723 new_token.code = '^';
8724
8725 else if (strcasecmp (new_token.str, "SHL") == 0)
8726 new_token.code = T_SHL;
8727
8728 else if (strcasecmp (new_token.str, "SHR") == 0)
8729 new_token.code = T_SHR;
8730
8731 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8732 new_token.code = T_BYTE;
8733
8734 else if (strcasecmp (new_token.str, "WORD") == 0)
8735 new_token.code = T_WORD;
8736
8737 else if (strcasecmp (new_token.str, "DWORD") == 0)
8738 new_token.code = T_DWORD;
8739
9306ca4a
JB		 8740 else if (strcasecmp (new_token.str, "FWORD") == 0)
8741 new_token.code = T_FWORD;
8742
64a0c779
DN		 8743 else if (strcasecmp (new_token.str, "QWORD") == 0)
8744 new_token.code = T_QWORD;
8745
9306ca4a
JB		 8746 else if (strcasecmp (new_token.str, "TBYTE") == 0
8747 /* XXX remove (gcc still uses it) */
8748 || strcasecmp (new_token.str, "XWORD") == 0)
8749 new_token.code = T_TBYTE;
8750
8751 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8752 || strcasecmp (new_token.str, "OWORD") == 0)
8753 new_token.code = T_XMMWORD;
64a0c779
DN		 8754
8755 else if (strcasecmp (new_token.str, "PTR") == 0)
8756 new_token.code = T_PTR;
8757
8758 else if (strcasecmp (new_token.str, "SHORT") == 0)
8759 new_token.code = T_SHORT;
8760
8761 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8762 {
8763 new_token.code = T_OFFSET;
8764
8765 /* ??? This is not mentioned in the MASM grammar but gcc
8766 makes use of it with -mintel-syntax. OFFSET may be
8767 followed by FLAT: */
8768 if (strncasecmp (q, " FLAT:", 6) == 0)
8769 strcat (new_token.str, " FLAT:");
8770 }
8771
8772 /* ??? This is not mentioned in the MASM grammar. */
8773 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8774 {
8775 new_token.code = T_OFFSET;
8776 if (*q == ':')
8777 strcat (new_token.str, ":");
8778 else
8779 as_bad (_("`:' expected"));
8780 }
64a0c779
DN		 8781
8782 else
8783 new_token.code = T_ID;
8784 }
8785 }
8786
9306ca4a
JB		 8787 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8788 {
8789 new_token.code = *intel_parser.op_string;
8790 new_token.str[0] = *intel_parser.op_string;
8791 new_token.str[1] = '\0';
8792 }
8793
8794 else if (strchr ("<>", *intel_parser.op_string)
8795 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8796 {
8797 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8798 new_token.str[0] = *intel_parser.op_string;
8799 new_token.str[1] = *intel_parser.op_string;
8800 new_token.str[2] = '\0';
8801 }
8802
64a0c779 8803 else
0477af35 8804 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8805
8806 intel_parser.op_string += strlen (new_token.str);
8807 cur_token = new_token;
8808}
8809
64a0c779
DN		 8810/* Put cur_token back into the token stream and make cur_token point to
8811 prev_token. */
8812static void
e3bb37b5 8813intel_putback_token (void)
64a0c779 8814{
a724f0f4
JB		 8815 if (cur_token.code != T_NIL)
8816 {
8817 intel_parser.op_string -= strlen (cur_token.str);
8818 free (cur_token.str);
8819 }
64a0c779 8820 cur_token = prev_token;
4a1805b1 8821
64a0c779
DN		 8822 /* Forget prev_token. */
8823 prev_token.code = T_NIL;
8824 prev_token.reg = NULL;
8825 prev_token.str = NULL;
8826}
54cfded0 8827
a4447b93 8828int
1df69f4f 8829tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8830{
8831 unsigned int regnum;
8832 unsigned int regnames_count;
089dfecd 8833 static const char *const regnames_32[] =
54cfded0 8834 {
a4447b93
RH		 8835 "eax", "ecx", "edx", "ebx",
8836 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8837 "eip", "eflags", NULL,
8838 "st0", "st1", "st2", "st3",
8839 "st4", "st5", "st6", "st7",
8840 NULL, NULL,
8841 "xmm0", "xmm1", "xmm2", "xmm3",
8842 "xmm4", "xmm5", "xmm6", "xmm7",
8843 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8844 "mm4", "mm5", "mm6", "mm7",
8845 "fcw", "fsw", "mxcsr",
8846 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8847 "tr", "ldtr"
54cfded0 8848 };
089dfecd 8849 static const char *const regnames_64[] =
54cfded0 8850 {
089dfecd
JB		 8851 "rax", "rdx", "rcx", "rbx",
8852 "rsi", "rdi", "rbp", "rsp",
8853 "r8", "r9", "r10", "r11",
54cfded0 8854 "r12", "r13", "r14", "r15",
089dfecd
JB		 8855 "rip",
8856 "xmm0", "xmm1", "xmm2", "xmm3",
8857 "xmm4", "xmm5", "xmm6", "xmm7",
8858 "xmm8", "xmm9", "xmm10", "xmm11",
8859 "xmm12", "xmm13", "xmm14", "xmm15",
8860 "st0", "st1", "st2", "st3",
8861 "st4", "st5", "st6", "st7",
8862 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8863 "mm4", "mm5", "mm6", "mm7",
8864 "rflags",
8865 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8866 "fs.base", "gs.base", NULL, NULL,
8867 "tr", "ldtr",
8868 "mxcsr", "fcw", "fsw"
54cfded0 8869 };
089dfecd 8870 const char *const *regnames;
54cfded0
AM		 8871
8872 if (flag_code == CODE_64BIT)
8873 {
8874 regnames = regnames_64;
0cea6190 8875 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8876 }
8877 else
8878 {
8879 regnames = regnames_32;
0cea6190 8880 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8881 }
8882
8883 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8884 if (regnames[regnum] != NULL
8885 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8886 return regnum;
8887
54cfded0
AM		 8888 return -1;
8889}
8890
8891void
8892tc_x86_frame_initial_instructions (void)
8893{
a4447b93
RH		 8894 static unsigned int sp_regno;
8895
8896 if (!sp_regno)
8897 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8898 ? "rsp" : "esp");
8899
8900 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8901 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8902}
d2b2c203
DJ		 8903
8904int
8905i386_elf_section_type (const char *str, size_t len)
8906{
8907 if (flag_code == CODE_64BIT
8908 && len == sizeof ("unwind") - 1
8909 && strncmp (str, "unwind", 6) == 0)
8910 return SHT_X86_64_UNWIND;
8911
8912 return -1;
8913}
bb41ade5
AM		 8914
8915#ifdef TE_PE
8916void
8917tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8918{
8919 expressionS expr;
8920
8921 expr.X_op = O_secrel;
8922 expr.X_add_symbol = symbol;
8923 expr.X_add_number = 0;
8924 emit_expr (&expr, size);
8925}
8926#endif
3b22753a
L		 8927
8928#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8929/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8930
8931int
8932x86_64_section_letter (int letter, char **ptr_msg)
8933{
8934 if (flag_code == CODE_64BIT)
8935 {
8936 if (letter == 'l')
8937 return SHF_X86_64_LARGE;
8938
8939 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8940 }
3b22753a 8941 else
64e74474 8942 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8943 return -1;
8944}
8945
8946int
8947x86_64_section_word (char *str, size_t len)
8948{
8620418b 8949 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8950 return SHF_X86_64_LARGE;
8951
8952 return -1;
8953}
8954
8955static void
8956handle_large_common (int small ATTRIBUTE_UNUSED)
8957{
8958 if (flag_code != CODE_64BIT)
8959 {
8960 s_comm_internal (0, elf_common_parse);
8961 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8962 }
8963 else
8964 {
8965 static segT lbss_section;
8966 asection *saved_com_section_ptr = elf_com_section_ptr;
8967 asection *saved_bss_section = bss_section;
8968
8969 if (lbss_section == NULL)
8970 {
8971 flagword applicable;
8972 segT seg = now_seg;
8973 subsegT subseg = now_subseg;
8974
8975 /* The .lbss section is for local .largecomm symbols. */
8976 lbss_section = subseg_new (".lbss", 0);
8977 applicable = bfd_applicable_section_flags (stdoutput);
8978 bfd_set_section_flags (stdoutput, lbss_section,
8979 applicable & SEC_ALLOC);
8980 seg_info (lbss_section)->bss = 1;
8981
8982 subseg_set (seg, subseg);
8983 }
8984
8985 elf_com_section_ptr = &_bfd_elf_large_com_section;
8986 bss_section = lbss_section;
8987
8988 s_comm_internal (0, elf_common_parse);
8989
8990 elf_com_section_ptr = saved_com_section_ptr;
8991 bss_section = saved_bss_section;
8992 }
8993}
8994#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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