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* Makefile.in (tmp-ld-decode): Fix dependencies.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
92static void optimize_imm PARAMS ((void));
93static void optimize_disp PARAMS ((void));
94static int match_template PARAMS ((void));
95static int check_string PARAMS ((void));
96static int process_suffix PARAMS ((void));
97static int check_byte_reg PARAMS ((void));
98static int check_long_reg PARAMS ((void));
99static int check_qword_reg PARAMS ((void));
100static int check_word_reg PARAMS ((void));
101static int finalize_imm PARAMS ((void));
102static int process_operands PARAMS ((void));
103static const seg_entry *build_modrm_byte PARAMS ((void));
104static void output_insn PARAMS ((void));
105static void output_branch PARAMS ((void));
106static void output_jump PARAMS ((void));
107static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 108static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
29b0f896
AM		 112#ifndef I386COFF
113static void s_bss PARAMS ((int));
252b5132 114#endif
17d4e2a2
L		 115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116static void handle_large_common (int small ATTRIBUTE_UNUSED);
117#endif
252b5132 118
a847613f 119static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 120
252b5132 121/* 'md_assemble ()' gathers together information and puts it into a
47926f60 122 i386_insn. */
252b5132 123
520dc8e8
AM		 124union i386_op
125 {
126 expressionS *disps;
127 expressionS *imms;
128 const reg_entry *regs;
129 };
130
252b5132
RH		 131struct _i386_insn
132 {
47926f60 133 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 134 template tm;
135
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
138 char suffix;
139
47926f60 140 /* OPERANDS gives the number of given operands. */
252b5132
RH		 141 unsigned int operands;
142
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
47926f60 145 operands. */
252b5132
RH		 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147
148 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 149 use OP[i] for the corresponding operand. */
252b5132
RH		 150 unsigned int types[MAX_OPERANDS];
151
520dc8e8
AM		 152 /* Displacement expression, immediate expression, or register for each
153 operand. */
154 union i386_op op[MAX_OPERANDS];
252b5132 155
3e73aa7c
JH		 156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158#define Operand_PCrel 1
159
252b5132 160 /* Relocation type for operand */
f86103b7 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 162
252b5132
RH		 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
168
169 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 170 explicit segment overrides are given. */
ce8a8b2f 171 const seg_entry *seg[2];
252b5132
RH		 172
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
177
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
180
181 modrm_byte rm;
3e73aa7c 182 rex_byte rex;
252b5132
RH		 183 sib_byte sib;
184 };
185
186typedef struct _i386_insn i386_insn;
187
188/* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
32137342 190const char extra_symbol_chars[] = "*%-(["
252b5132 191#ifdef LEX_AT
32137342
NC		 192 "@"
193#endif
194#ifdef LEX_QM
195 "?"
252b5132 196#endif
32137342 197 ;
252b5132 198
29b0f896
AM		 199#if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 201 && !defined (TE_GNU) \
29b0f896 202 && !defined (TE_LINUX) \
32137342 203 && !defined (TE_NETWARE) \
29b0f896
AM		 204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
252b5132 206/* This array holds the chars that always start a comment. If the
b3b91714
AM		 207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209const char *i386_comment_chars = "#/";
210#define SVR4_COMMENT_CHARS 1
252b5132 211#define PREFIX_SEPARATOR '\\'
252b5132 212
b3b91714
AM		 213#else
214const char *i386_comment_chars = "#";
215#define PREFIX_SEPARATOR '/'
216#endif
217
252b5132
RH		 218/* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 222 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
252b5132 225 '/' isn't otherwise defined. */
b3b91714 226const char line_comment_chars[] = "#/";
252b5132 227
63a0b638 228const char line_separator_chars[] = ";";
252b5132 229
ce8a8b2f
AM		 230/* Chars that can be used to separate mant from exp in floating point
231 nums. */
252b5132
RH		 232const char EXP_CHARS[] = "eE";
233
ce8a8b2f
AM		 234/* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
252b5132
RH		 237const char FLT_CHARS[] = "fFdDxX";
238
ce8a8b2f 239/* Tables for lexical analysis. */
252b5132
RH		 240static char mnemonic_chars[256];
241static char register_chars[256];
242static char operand_chars[256];
243static char identifier_chars[256];
244static char digit_chars[256];
245
ce8a8b2f 246/* Lexical macros. */
252b5132
RH		 247#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248#define is_operand_char(x) (operand_chars[(unsigned char) x])
249#define is_register_char(x) (register_chars[(unsigned char) x])
250#define is_space_char(x) ((x) == ' ')
251#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252#define is_digit_char(x) (digit_chars[(unsigned char) x])
253
0234cb7c 254/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 255static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257/* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
47926f60 260 assembler instruction). */
252b5132 261static char save_stack[32];
ce8a8b2f 262static char *save_stack_p;
252b5132
RH		 263#define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265#define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
47926f60 268/* The instruction we're assembling. */
252b5132
RH		 269static i386_insn i;
270
271/* Possible templates for current insn. */
272static const templates *current_templates;
273
47926f60 274/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 275static expressionS disp_expressions[2], im_expressions[2];
276
47926f60
KH		 277/* Current operand we are working on. */
278static int this_operand;
252b5132 279
3e73aa7c
JH		 280/* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
f3c180ae 287#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 288
289static enum flag_code flag_code;
4fa24527 290static unsigned int object_64bit;
3e73aa7c
JH		 291static int use_rela_relocations = 0;
292
293/* The names used to print error messages. */
b77a7acd 294static const char *flag_code_names[] =
3e73aa7c
JH		 295 {
296 "32",
297 "16",
298 "64"
299 };
252b5132 300
47926f60
KH		 301/* 1 for intel syntax,
302 0 if att syntax. */
303static int intel_syntax = 0;
252b5132 304
47926f60
KH		 305/* 1 if register prefix % not required. */
306static int allow_naked_reg = 0;
252b5132 307
47926f60
KH		 308/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311static char stackop_size = '\0';
eecb386c 312
12b55ccc
L		 313/* Non-zero to optimize code alignment. */
314int optimize_align_code = 1;
315
47926f60
KH		 316/* Non-zero to quieten some warnings. */
317static int quiet_warnings = 0;
a38cf1db 318
47926f60
KH		 319/* CPU name. */
320static const char *cpu_arch_name = NULL;
5c6af06e 321static const char *cpu_sub_arch_name = NULL;
a38cf1db 322
47926f60 323/* CPU feature flags. */
29b0f896 324static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 325
fddf5b5b
AM		 326/* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328static unsigned int no_cond_jump_promotion = 0;
329
29b0f896 330/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 331static symbolS *GOT_symbol;
29b0f896 332
a4447b93
RH		 333/* The dwarf2 return column, adjusted for 32 or 64 bit. */
334unsigned int x86_dwarf2_return_column;
335
336/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337int x86_cie_data_alignment;
338
252b5132 339/* Interface to relax_segment.
fddf5b5b
AM		 340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
252b5132 343
47926f60 344/* Types. */
93c2a809
AM		 345#define UNCOND_JUMP 0
346#define COND_JUMP 1
347#define COND_JUMP86 2
fddf5b5b 348
47926f60 349/* Sizes. */
252b5132
RH		 350#define CODE16 1
351#define SMALL 0
29b0f896 352#define SMALL16 (SMALL | CODE16)
252b5132 353#define BIG 2
29b0f896 354#define BIG16 (BIG | CODE16)
252b5132
RH		 355
356#ifndef INLINE
357#ifdef __GNUC__
358#define INLINE __inline__
359#else
360#define INLINE
361#endif
362#endif
363
fddf5b5b
AM		 364#define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366#define TYPE_FROM_RELAX_STATE(s) \
367 ((s) >> 2)
368#define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 370
371/* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
378
379const relax_typeS md_relax_table[] =
380{
24eab124
AM		 381 /* The fields are:
382 1) most positive reach of this state,
383 2) most negative reach of this state,
93c2a809 384 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 385 4) which index into the table to try if we can't fit into this one. */
252b5132 386
fddf5b5b 387 /* UNCOND_JUMP states. */
93c2a809
AM		 388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
252b5132 392 {0, 0, 4, 0},
93c2a809
AM		 393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 395 {0, 0, 2, 0},
396
93c2a809
AM		 397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
402 {0, 0, 5, 0},
fddf5b5b 403 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 404 1 extra opcode byte, 2 displacement bytes. */
405 {0, 0, 3, 0},
406
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
415 {0, 0, 4, 0}
252b5132
RH		 416};
417
e413e4e9
AM		 418static const arch_entry cpu_arch[] = {
419 {"i8086", Cpu086 },
420 {"i186", Cpu086|Cpu186 },
421 {"i286", Cpu086|Cpu186|Cpu286 },
422 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
423 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 424 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
425 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
426 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
427 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
428 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
429 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
430 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
431 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
432 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
433 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
434 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
435 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 436 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 437 {".mmx", CpuMMX },
438 {".sse", CpuMMX|CpuMMX2|CpuSSE },
439 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 440 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 441 {".3dnow", CpuMMX|Cpu3dnow },
442 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
443 {".padlock", CpuPadLock },
30123838
JB		 444 {".pacifica", CpuSVME },
445 {".svme", CpuSVME },
e413e4e9
AM		 446 {NULL, 0 }
447};
448
29b0f896
AM		 449const pseudo_typeS md_pseudo_table[] =
450{
451#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes, 0},
453#else
454 {"align", s_align_ptwo, 0},
455#endif
456 {"arch", set_cpu_arch, 0},
457#ifndef I386COFF
458 {"bss", s_bss, 0},
459#endif
460 {"ffloat", float_cons, 'f'},
461 {"dfloat", float_cons, 'd'},
462 {"tfloat", float_cons, 'x'},
463 {"value", cons, 2},
d182319b 464 {"slong", signed_cons, 4},
29b0f896
AM		 465 {"noopt", s_ignore, 0},
466 {"optim", s_ignore, 0},
467 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
468 {"code16", set_code_flag, CODE_16BIT},
469 {"code32", set_code_flag, CODE_32BIT},
470 {"code64", set_code_flag, CODE_64BIT},
471 {"intel_syntax", set_intel_syntax, 1},
472 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 473#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 475#else
476 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
477 {"loc", dwarf2_directive_loc, 0},
478 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 479#endif
6482c264
NC		 480#ifdef TE_PE
481 {"secrel32", pe_directive_secrel, 0},
482#endif
29b0f896
AM		 483 {0, 0, 0}
484};
485
486/* For interface with expression (). */
487extern char *input_line_pointer;
488
489/* Hash table for instruction mnemonic lookup. */
490static struct hash_control *op_hash;
491
492/* Hash table for register lookup. */
493static struct hash_control *reg_hash;
494\f
252b5132
RH		 495void
496i386_align_code (fragP, count)
497 fragS *fragP;
498 int count;
499{
ce8a8b2f
AM		 500 /* Various efficient no-op patterns for aligning code labels.
501 Note: Don't try to assemble the instructions in the comments.
502 0L and 0w are not legal. */
252b5132
RH		 503 static const char f32_1[] =
504 {0x90}; /* nop */
505 static const char f32_2[] =
506 {0x89,0xf6}; /* movl %esi,%esi */
507 static const char f32_3[] =
508 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
509 static const char f32_4[] =
510 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_5[] =
512 {0x90, /* nop */
513 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
514 static const char f32_6[] =
515 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
516 static const char f32_7[] =
517 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_8[] =
519 {0x90, /* nop */
520 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
521 static const char f32_9[] =
522 {0x89,0xf6, /* movl %esi,%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_10[] =
525 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_11[] =
528 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_12[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
533 static const char f32_13[] =
534 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_14[] =
537 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
538 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
539 static const char f32_15[] =
540 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
541 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 542 static const char f16_3[] =
543 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 544 static const char f16_4[] =
545 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_5[] =
547 {0x90, /* nop */
548 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
549 static const char f16_6[] =
550 {0x89,0xf6, /* mov %si,%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_7[] =
553 {0x8d,0x74,0x00, /* lea 0(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char f16_8[] =
556 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
557 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
558 static const char *const f32_patt[] = {
559 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
560 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
561 };
562 static const char *const f16_patt[] = {
c3332e24 563 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 564 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
565 };
566
33fef721
JH		 567 if (count <= 0 || count > 15)
568 return;
3e73aa7c 569
33fef721
JH		 570 /* The recommended way to pad 64bit code is to use NOPs preceded by
571 maximally four 0x66 prefixes. Balance the size of nops. */
572 if (flag_code == CODE_64BIT)
252b5132 573 {
33fef721
JH		 574 int i;
575 int nnops = (count + 3) / 4;
576 int len = count / nnops;
577 int remains = count - nnops * len;
578 int pos = 0;
579
580 for (i = 0; i < remains; i++)
252b5132 581 {
33fef721
JH		 582 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
583 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
584 pos += len + 1;
585 }
586 for (; i < nnops; i++)
587 {
588 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
589 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
590 pos += len;
252b5132 591 }
252b5132 592 }
33fef721
JH		 593 else
594 if (flag_code == CODE_16BIT)
595 {
596 memcpy (fragP->fr_literal + fragP->fr_fix,
597 f16_patt[count - 1], count);
598 if (count > 8)
599 /* Adjust jump offset. */
600 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
601 }
602 else
603 memcpy (fragP->fr_literal + fragP->fr_fix,
604 f32_patt[count - 1], count);
605 fragP->fr_var = count;
252b5132
RH		 606}
607
252b5132
RH		 608static INLINE unsigned int
609mode_from_disp_size (t)
610 unsigned int t;
611{
3e73aa7c 612 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 613}
614
615static INLINE int
616fits_in_signed_byte (num)
847f7ad4 617 offsetT num;
252b5132
RH		 618{
619 return (num >= -128) && (num <= 127);
47926f60 620}
252b5132
RH		 621
622static INLINE int
623fits_in_unsigned_byte (num)
847f7ad4 624 offsetT num;
252b5132
RH		 625{
626 return (num & 0xff) == num;
47926f60 627}
252b5132
RH		 628
629static INLINE int
630fits_in_unsigned_word (num)
847f7ad4 631 offsetT num;
252b5132
RH		 632{
633 return (num & 0xffff) == num;
47926f60 634}
252b5132
RH		 635
636static INLINE int
637fits_in_signed_word (num)
847f7ad4 638 offsetT num;
252b5132
RH		 639{
640 return (-32768 <= num) && (num <= 32767);
47926f60 641}
3e73aa7c
JH		 642static INLINE int
643fits_in_signed_long (num)
644 offsetT num ATTRIBUTE_UNUSED;
645{
646#ifndef BFD64
647 return 1;
648#else
649 return (!(((offsetT) -1 << 31) & num)
650 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
651#endif
652} /* fits_in_signed_long() */
653static INLINE int
654fits_in_unsigned_long (num)
655 offsetT num ATTRIBUTE_UNUSED;
656{
657#ifndef BFD64
658 return 1;
659#else
660 return (num & (((offsetT) 2 << 31) - 1)) == num;
661#endif
662} /* fits_in_unsigned_long() */
252b5132
RH		 663
664static int
665smallest_imm_type (num)
847f7ad4 666 offsetT num;
252b5132 667{
a847613f 668 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 669 {
670 /* This code is disabled on the 486 because all the Imm1 forms
671 in the opcode table are slower on the i486. They're the
672 versions with the implicitly specified single-position
673 displacement, which has another syntax if you really want to
674 use that form. */
675 if (num == 1)
3e73aa7c 676 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 677 }
252b5132 678 return (fits_in_signed_byte (num)
3e73aa7c 679 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 680 : fits_in_unsigned_byte (num)
3e73aa7c 681 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 682 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 683 ? (Imm16 | Imm32 | Imm32S | Imm64)
684 : fits_in_signed_long (num)
685 ? (Imm32 | Imm32S | Imm64)
686 : fits_in_unsigned_long (num)
687 ? (Imm32 | Imm64)
688 : Imm64);
47926f60 689}
252b5132 690
847f7ad4
AM		 691static offsetT
692offset_in_range (val, size)
693 offsetT val;
694 int size;
695{
508866be 696 addressT mask;
ba2adb93 697
847f7ad4
AM		 698 switch (size)
699 {
508866be
L		 700 case 1: mask = ((addressT) 1 << 8) - 1; break;
701 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 702 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 703#ifdef BFD64
704 case 8: mask = ((addressT) 2 << 63) - 1; break;
705#endif
47926f60 706 default: abort ();
847f7ad4
AM		 707 }
708
ba2adb93 709 /* If BFD64, sign extend val. */
3e73aa7c
JH		 710 if (!use_rela_relocations)
711 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
712 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 713
47926f60 714 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 715 {
716 char buf1[40], buf2[40];
717
718 sprint_value (buf1, val);
719 sprint_value (buf2, val & mask);
720 as_warn (_("%s shortened to %s"), buf1, buf2);
721 }
722 return val & mask;
723}
724
252b5132
RH		 725/* Returns 0 if attempting to add a prefix where one from the same
726 class already exists, 1 if non rep/repne added, 2 if rep/repne
727 added. */
728static int
729add_prefix (prefix)
730 unsigned int prefix;
731{
732 int ret = 1;
b1905489 733 unsigned int q;
252b5132 734
29b0f896
AM		 735 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
736 && flag_code == CODE_64BIT)
b1905489
JB		 737 {
738 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
739 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
740 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
741 ret = 0;
742 q = REX_PREFIX;
743 }
3e73aa7c 744 else
b1905489
JB		 745 {
746 switch (prefix)
747 {
748 default:
749 abort ();
750
751 case CS_PREFIX_OPCODE:
752 case DS_PREFIX_OPCODE:
753 case ES_PREFIX_OPCODE:
754 case FS_PREFIX_OPCODE:
755 case GS_PREFIX_OPCODE:
756 case SS_PREFIX_OPCODE:
757 q = SEG_PREFIX;
758 break;
759
760 case REPNE_PREFIX_OPCODE:
761 case REPE_PREFIX_OPCODE:
762 ret = 2;
763 /* fall thru */
764 case LOCK_PREFIX_OPCODE:
765 q = LOCKREP_PREFIX;
766 break;
767
768 case FWAIT_OPCODE:
769 q = WAIT_PREFIX;
770 break;
771
772 case ADDR_PREFIX_OPCODE:
773 q = ADDR_PREFIX;
774 break;
775
776 case DATA_PREFIX_OPCODE:
777 q = DATA_PREFIX;
778 break;
779 }
780 if (i.prefix[q] != 0)
781 ret = 0;
782 }
252b5132 783
b1905489 784 if (ret)
252b5132 785 {
b1905489
JB		 786 if (!i.prefix[q])
787 ++i.prefixes;
788 i.prefix[q] |= prefix;
252b5132 789 }
b1905489
JB		 790 else
791 as_bad (_("same type of prefix used twice"));
252b5132 792
252b5132
RH		 793 return ret;
794}
795
796static void
3e73aa7c 797set_code_flag (value)
e5cb08ac 798 int value;
eecb386c 799{
3e73aa7c
JH		 800 flag_code = value;
801 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
802 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
803 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
804 {
805 as_bad (_("64bit mode not supported on this CPU."));
806 }
807 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
808 {
809 as_bad (_("32bit mode not supported on this CPU."));
810 }
eecb386c
AM		 811 stackop_size = '\0';
812}
813
814static void
3e73aa7c
JH		 815set_16bit_gcc_code_flag (new_code_flag)
816 int new_code_flag;
252b5132 817{
3e73aa7c
JH		 818 flag_code = new_code_flag;
819 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
820 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 821 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 822}
823
824static void
825set_intel_syntax (syntax_flag)
eecb386c 826 int syntax_flag;
252b5132
RH		 827{
828 /* Find out if register prefixing is specified. */
829 int ask_naked_reg = 0;
830
831 SKIP_WHITESPACE ();
29b0f896 832 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 833 {
834 char *string = input_line_pointer;
835 int e = get_symbol_end ();
836
47926f60 837 if (strcmp (string, "prefix") == 0)
252b5132 838 ask_naked_reg = 1;
47926f60 839 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 840 ask_naked_reg = -1;
841 else
d0b47220 842 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 843 *input_line_pointer = e;
844 }
845 demand_empty_rest_of_line ();
c3332e24 846
252b5132
RH		 847 intel_syntax = syntax_flag;
848
849 if (ask_naked_reg == 0)
f86103b7
AM		 850 allow_naked_reg = (intel_syntax
851 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 852 else
853 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 854
855 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
856 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 857}
858
e413e4e9
AM		 859static void
860set_cpu_arch (dummy)
47926f60 861 int dummy ATTRIBUTE_UNUSED;
e413e4e9 862{
47926f60 863 SKIP_WHITESPACE ();
e413e4e9 864
29b0f896 865 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 866 {
867 char *string = input_line_pointer;
868 int e = get_symbol_end ();
869 int i;
870
871 for (i = 0; cpu_arch[i].name; i++)
872 {
873 if (strcmp (string, cpu_arch[i].name) == 0)
874 {
5c6af06e
JB		 875 if (*string != '.')
876 {
877 cpu_arch_name = cpu_arch[i].name;
878 cpu_sub_arch_name = NULL;
879 cpu_arch_flags = (cpu_arch[i].flags
880 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
881 break;
882 }
883 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
884 {
885 cpu_sub_arch_name = cpu_arch[i].name;
886 cpu_arch_flags |= cpu_arch[i].flags;
887 }
888 *input_line_pointer = e;
889 demand_empty_rest_of_line ();
890 return;
e413e4e9
AM		 891 }
892 }
893 if (!cpu_arch[i].name)
894 as_bad (_("no such architecture: `%s'"), string);
895
896 *input_line_pointer = e;
897 }
898 else
899 as_bad (_("missing cpu architecture"));
900
fddf5b5b
AM		 901 no_cond_jump_promotion = 0;
902 if (*input_line_pointer == ','
29b0f896 903 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 904 {
905 char *string = ++input_line_pointer;
906 int e = get_symbol_end ();
907
908 if (strcmp (string, "nojumps") == 0)
909 no_cond_jump_promotion = 1;
910 else if (strcmp (string, "jumps") == 0)
911 ;
912 else
913 as_bad (_("no such architecture modifier: `%s'"), string);
914
915 *input_line_pointer = e;
916 }
917
e413e4e9
AM		 918 demand_empty_rest_of_line ();
919}
920
b9d79e03
JH		 921unsigned long
922i386_mach ()
923{
924 if (!strcmp (default_arch, "x86_64"))
925 return bfd_mach_x86_64;
926 else if (!strcmp (default_arch, "i386"))
927 return bfd_mach_i386_i386;
928 else
929 as_fatal (_("Unknown architecture"));
930}
b9d79e03 931\f
252b5132
RH		 932void
933md_begin ()
934{
935 const char *hash_err;
936
47926f60 937 /* Initialize op_hash hash table. */
252b5132
RH		 938 op_hash = hash_new ();
939
940 {
29b0f896
AM		 941 const template *optab;
942 templates *core_optab;
252b5132 943
47926f60
KH		 944 /* Setup for loop. */
945 optab = i386_optab;
252b5132
RH		 946 core_optab = (templates *) xmalloc (sizeof (templates));
947 core_optab->start = optab;
948
949 while (1)
950 {
951 ++optab;
952 if (optab->name == NULL
953 || strcmp (optab->name, (optab - 1)->name) != 0)
954 {
955 /* different name --> ship out current template list;
47926f60 956 add to hash table; & begin anew. */
252b5132
RH		 957 core_optab->end = optab;
958 hash_err = hash_insert (op_hash,
959 (optab - 1)->name,
960 (PTR) core_optab);
961 if (hash_err)
962 {
252b5132
RH		 963 as_fatal (_("Internal Error: Can't hash %s: %s"),
964 (optab - 1)->name,
965 hash_err);
966 }
967 if (optab->name == NULL)
968 break;
969 core_optab = (templates *) xmalloc (sizeof (templates));
970 core_optab->start = optab;
971 }
972 }
973 }
974
47926f60 975 /* Initialize reg_hash hash table. */
252b5132
RH		 976 reg_hash = hash_new ();
977 {
29b0f896 978 const reg_entry *regtab;
252b5132
RH		 979
980 for (regtab = i386_regtab;
981 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
982 regtab++)
983 {
984 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
985 if (hash_err)
3e73aa7c
JH		 986 as_fatal (_("Internal Error: Can't hash %s: %s"),
987 regtab->reg_name,
988 hash_err);
252b5132
RH		 989 }
990 }
991
47926f60 992 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 993 {
29b0f896
AM		 994 int c;
995 char *p;
252b5132
RH		 996
997 for (c = 0; c < 256; c++)
998 {
3882b010 999 if (ISDIGIT (c))
252b5132
RH		 1000 {
1001 digit_chars[c] = c;
1002 mnemonic_chars[c] = c;
1003 register_chars[c] = c;
1004 operand_chars[c] = c;
1005 }
3882b010 1006 else if (ISLOWER (c))
252b5132
RH		 1007 {
1008 mnemonic_chars[c] = c;
1009 register_chars[c] = c;
1010 operand_chars[c] = c;
1011 }
3882b010 1012 else if (ISUPPER (c))
252b5132 1013 {
3882b010 1014 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1015 register_chars[c] = mnemonic_chars[c];
1016 operand_chars[c] = c;
1017 }
1018
3882b010 1019 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1020 identifier_chars[c] = c;
1021 else if (c >= 128)
1022 {
1023 identifier_chars[c] = c;
1024 operand_chars[c] = c;
1025 }
1026 }
1027
1028#ifdef LEX_AT
1029 identifier_chars['@'] = '@';
32137342
NC		 1030#endif
1031#ifdef LEX_QM
1032 identifier_chars['?'] = '?';
1033 operand_chars['?'] = '?';
252b5132 1034#endif
252b5132 1035 digit_chars['-'] = '-';
791fe849 1036 mnemonic_chars['-'] = '-';
252b5132
RH		 1037 identifier_chars['_'] = '_';
1038 identifier_chars['.'] = '.';
1039
1040 for (p = operand_special_chars; *p != '\0'; p++)
1041 operand_chars[(unsigned char) *p] = *p;
1042 }
1043
1044#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1045 if (IS_ELF)
252b5132
RH		 1046 {
1047 record_alignment (text_section, 2);
1048 record_alignment (data_section, 2);
1049 record_alignment (bss_section, 2);
1050 }
1051#endif
a4447b93
RH		 1052
1053 if (flag_code == CODE_64BIT)
1054 {
1055 x86_dwarf2_return_column = 16;
1056 x86_cie_data_alignment = -8;
1057 }
1058 else
1059 {
1060 x86_dwarf2_return_column = 8;
1061 x86_cie_data_alignment = -4;
1062 }
252b5132
RH		 1063}
1064
1065void
1066i386_print_statistics (file)
1067 FILE *file;
1068{
1069 hash_print_statistics (file, "i386 opcode", op_hash);
1070 hash_print_statistics (file, "i386 register", reg_hash);
1071}
1072\f
252b5132
RH		 1073#ifdef DEBUG386
1074
ce8a8b2f 1075/* Debugging routines for md_assemble. */
252b5132
RH		 1076static void pi PARAMS ((char *, i386_insn *));
1077static void pte PARAMS ((template *));
1078static void pt PARAMS ((unsigned int));
1079static void pe PARAMS ((expressionS *));
1080static void ps PARAMS ((symbolS *));
1081
1082static void
1083pi (line, x)
1084 char *line;
1085 i386_insn *x;
1086{
09f131f2 1087 unsigned int i;
252b5132
RH		 1088
1089 fprintf (stdout, "%s: template ", line);
1090 pte (&x->tm);
09f131f2
JH		 1091 fprintf (stdout, " address: base %s index %s scale %x\n",
1092 x->base_reg ? x->base_reg->reg_name : "none",
1093 x->index_reg ? x->index_reg->reg_name : "none",
1094 x->log2_scale_factor);
1095 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1096 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1097 fprintf (stdout, " sib: base %x index %x scale %x\n",
1098 x->sib.base, x->sib.index, x->sib.scale);
1099 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1100 (x->rex & REX_MODE64) != 0,
1101 (x->rex & REX_EXTX) != 0,
1102 (x->rex & REX_EXTY) != 0,
1103 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1104 for (i = 0; i < x->operands; i++)
1105 {
1106 fprintf (stdout, " #%d: ", i + 1);
1107 pt (x->types[i]);
1108 fprintf (stdout, "\n");
1109 if (x->types[i]
3f4438ab 1110 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1111 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1112 if (x->types[i] & Imm)
520dc8e8 1113 pe (x->op[i].imms);
252b5132 1114 if (x->types[i] & Disp)
520dc8e8 1115 pe (x->op[i].disps);
252b5132
RH		 1116 }
1117}
1118
1119static void
1120pte (t)
1121 template *t;
1122{
09f131f2 1123 unsigned int i;
252b5132 1124 fprintf (stdout, " %d operands ", t->operands);
47926f60 1125 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1126 if (t->extension_opcode != None)
1127 fprintf (stdout, "ext %x ", t->extension_opcode);
1128 if (t->opcode_modifier & D)
1129 fprintf (stdout, "D");
1130 if (t->opcode_modifier & W)
1131 fprintf (stdout, "W");
1132 fprintf (stdout, "\n");
1133 for (i = 0; i < t->operands; i++)
1134 {
1135 fprintf (stdout, " #%d type ", i + 1);
1136 pt (t->operand_types[i]);
1137 fprintf (stdout, "\n");
1138 }
1139}
1140
1141static void
1142pe (e)
1143 expressionS *e;
1144{
24eab124 1145 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1146 fprintf (stdout, " add_number %ld (%lx)\n",
1147 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1148 if (e->X_add_symbol)
1149 {
1150 fprintf (stdout, " add_symbol ");
1151 ps (e->X_add_symbol);
1152 fprintf (stdout, "\n");
1153 }
1154 if (e->X_op_symbol)
1155 {
1156 fprintf (stdout, " op_symbol ");
1157 ps (e->X_op_symbol);
1158 fprintf (stdout, "\n");
1159 }
1160}
1161
1162static void
1163ps (s)
1164 symbolS *s;
1165{
1166 fprintf (stdout, "%s type %s%s",
1167 S_GET_NAME (s),
1168 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1169 segment_name (S_GET_SEGMENT (s)));
1170}
1171
7b81dfbb 1172static struct type_name
252b5132
RH		 1173 {
1174 unsigned int mask;
1175 char *tname;
1176 }
7b81dfbb 1177const type_names[] =
252b5132
RH		 1178{
1179 { Reg8, "r8" },
1180 { Reg16, "r16" },
1181 { Reg32, "r32" },
09f131f2 1182 { Reg64, "r64" },
252b5132
RH		 1183 { Imm8, "i8" },
1184 { Imm8S, "i8s" },
1185 { Imm16, "i16" },
1186 { Imm32, "i32" },
09f131f2
JH		 1187 { Imm32S, "i32s" },
1188 { Imm64, "i64" },
252b5132
RH		 1189 { Imm1, "i1" },
1190 { BaseIndex, "BaseIndex" },
1191 { Disp8, "d8" },
1192 { Disp16, "d16" },
1193 { Disp32, "d32" },
09f131f2
JH		 1194 { Disp32S, "d32s" },
1195 { Disp64, "d64" },
252b5132
RH		 1196 { InOutPortReg, "InOutPortReg" },
1197 { ShiftCount, "ShiftCount" },
1198 { Control, "control reg" },
1199 { Test, "test reg" },
1200 { Debug, "debug reg" },
1201 { FloatReg, "FReg" },
1202 { FloatAcc, "FAcc" },
1203 { SReg2, "SReg2" },
1204 { SReg3, "SReg3" },
1205 { Acc, "Acc" },
1206 { JumpAbsolute, "Jump Absolute" },
1207 { RegMMX, "rMMX" },
3f4438ab 1208 { RegXMM, "rXMM" },
252b5132
RH		 1209 { EsSeg, "es" },
1210 { 0, "" }
1211};
1212
1213static void
1214pt (t)
1215 unsigned int t;
1216{
29b0f896 1217 const struct type_name *ty;
252b5132 1218
09f131f2
JH		 1219 for (ty = type_names; ty->mask; ty++)
1220 if (t & ty->mask)
1221 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1222 fflush (stdout);
1223}
1224
1225#endif /* DEBUG386 */
1226\f
252b5132 1227static bfd_reloc_code_real_type
3956db08 1228reloc (unsigned int size,
64e74474
AM		 1229 int pcrel,
1230 int sign,
1231 bfd_reloc_code_real_type other)
252b5132 1232{
47926f60 1233 if (other != NO_RELOC)
3956db08
JB		 1234 {
1235 reloc_howto_type *reloc;
1236
1237 if (size == 8)
1238 switch (other)
1239 {
64e74474
AM		 1240 case BFD_RELOC_X86_64_GOT32:
1241 return BFD_RELOC_X86_64_GOT64;
1242 break;
1243 case BFD_RELOC_X86_64_PLTOFF64:
1244 return BFD_RELOC_X86_64_PLTOFF64;
1245 break;
1246 case BFD_RELOC_X86_64_GOTPC32:
1247 other = BFD_RELOC_X86_64_GOTPC64;
1248 break;
1249 case BFD_RELOC_X86_64_GOTPCREL:
1250 other = BFD_RELOC_X86_64_GOTPCREL64;
1251 break;
1252 case BFD_RELOC_X86_64_TPOFF32:
1253 other = BFD_RELOC_X86_64_TPOFF64;
1254 break;
1255 case BFD_RELOC_X86_64_DTPOFF32:
1256 other = BFD_RELOC_X86_64_DTPOFF64;
1257 break;
1258 default:
1259 break;
3956db08 1260 }
e05278af
JB		 1261
1262 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1263 if (size == 4 && flag_code != CODE_64BIT)
1264 sign = -1;
1265
3956db08
JB		 1266 reloc = bfd_reloc_type_lookup (stdoutput, other);
1267 if (!reloc)
1268 as_bad (_("unknown relocation (%u)"), other);
1269 else if (size != bfd_get_reloc_size (reloc))
1270 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1271 bfd_get_reloc_size (reloc),
1272 size);
1273 else if (pcrel && !reloc->pc_relative)
1274 as_bad (_("non-pc-relative relocation for pc-relative field"));
1275 else if ((reloc->complain_on_overflow == complain_overflow_signed
1276 && !sign)
1277 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1278 && sign > 0))
3956db08
JB		 1279 as_bad (_("relocated field and relocation type differ in signedness"));
1280 else
1281 return other;
1282 return NO_RELOC;
1283 }
252b5132
RH		 1284
1285 if (pcrel)
1286 {
3e73aa7c 1287 if (!sign)
3956db08 1288 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1289 switch (size)
1290 {
1291 case 1: return BFD_RELOC_8_PCREL;
1292 case 2: return BFD_RELOC_16_PCREL;
1293 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1294 case 8: return BFD_RELOC_64_PCREL;
252b5132 1295 }
3956db08 1296 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1297 }
1298 else
1299 {
3956db08 1300 if (sign > 0)
e5cb08ac 1301 switch (size)
3e73aa7c
JH		 1302 {
1303 case 4: return BFD_RELOC_X86_64_32S;
1304 }
1305 else
1306 switch (size)
1307 {
1308 case 1: return BFD_RELOC_8;
1309 case 2: return BFD_RELOC_16;
1310 case 4: return BFD_RELOC_32;
1311 case 8: return BFD_RELOC_64;
1312 }
3956db08
JB		 1313 as_bad (_("cannot do %s %u byte relocation"),
1314 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1315 }
1316
bfb32b52 1317 abort ();
252b5132
RH		 1318 return BFD_RELOC_NONE;
1319}
1320
47926f60
KH		 1321/* Here we decide which fixups can be adjusted to make them relative to
1322 the beginning of the section instead of the symbol. Basically we need
1323 to make sure that the dynamic relocations are done correctly, so in
1324 some cases we force the original symbol to be used. */
1325
252b5132 1326int
c0c949c7 1327tc_i386_fix_adjustable (fixP)
31312f95 1328 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1329{
6d249963 1330#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1331 if (!IS_ELF)
31312f95
AM		 1332 return 1;
1333
a161fe53
AM		 1334 /* Don't adjust pc-relative references to merge sections in 64-bit
1335 mode. */
1336 if (use_rela_relocations
1337 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1338 && fixP->fx_pcrel)
252b5132 1339 return 0;
31312f95 1340
8d01d9a9
AJ		 1341 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1342 and changed later by validate_fix. */
1343 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1344 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1345 return 0;
1346
ce8a8b2f 1347 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1348 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1349 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1350 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1351 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1352 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1353 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1354 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1355 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1356 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1357 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1358 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1359 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1360 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1361 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1362 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1363 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1364 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1365 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1366 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1367 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1368 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1369 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1370 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1371 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1372 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1373 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1374 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1375 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1376 return 0;
31312f95 1377#endif
252b5132
RH		 1378 return 1;
1379}
252b5132 1380
29b0f896 1381static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1382
1383static int
252b5132 1384intel_float_operand (mnemonic)
29b0f896 1385 const char *mnemonic;
252b5132 1386{
9306ca4a
JB		 1387 /* Note that the value returned is meaningful only for opcodes with (memory)
1388 operands, hence the code here is free to improperly handle opcodes that
1389 have no operands (for better performance and smaller code). */
1390
1391 if (mnemonic[0] != 'f')
1392 return 0; /* non-math */
1393
1394 switch (mnemonic[1])
1395 {
1396 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1397 the fs segment override prefix not currently handled because no
1398 call path can make opcodes without operands get here */
1399 case 'i':
1400 return 2 /* integer op */;
1401 case 'l':
1402 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1403 return 3; /* fldcw/fldenv */
1404 break;
1405 case 'n':
1406 if (mnemonic[2] != 'o' /* fnop */)
1407 return 3; /* non-waiting control op */
1408 break;
1409 case 'r':
1410 if (mnemonic[2] == 's')
1411 return 3; /* frstor/frstpm */
1412 break;
1413 case 's':
1414 if (mnemonic[2] == 'a')
1415 return 3; /* fsave */
1416 if (mnemonic[2] == 't')
1417 {
1418 switch (mnemonic[3])
1419 {
1420 case 'c': /* fstcw */
1421 case 'd': /* fstdw */
1422 case 'e': /* fstenv */
1423 case 's': /* fsts[gw] */
1424 return 3;
1425 }
1426 }
1427 break;
1428 case 'x':
1429 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1430 return 0; /* fxsave/fxrstor are not really math ops */
1431 break;
1432 }
252b5132 1433
9306ca4a 1434 return 1;
252b5132
RH		 1435}
1436
1437/* This is the guts of the machine-dependent assembler. LINE points to a
1438 machine dependent instruction. This function is supposed to emit
1439 the frags/bytes it assembles to. */
1440
1441void
1442md_assemble (line)
1443 char *line;
1444{
252b5132 1445 int j;
252b5132
RH		 1446 char mnemonic[MAX_MNEM_SIZE];
1447
47926f60 1448 /* Initialize globals. */
252b5132
RH		 1449 memset (&i, '\0', sizeof (i));
1450 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1451 i.reloc[j] = NO_RELOC;
252b5132
RH		 1452 memset (disp_expressions, '\0', sizeof (disp_expressions));
1453 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1454 save_stack_p = save_stack;
252b5132
RH		 1455
1456 /* First parse an instruction mnemonic & call i386_operand for the operands.
1457 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1458 start of a (possibly prefixed) mnemonic. */
252b5132 1459
29b0f896
AM		 1460 line = parse_insn (line, mnemonic);
1461 if (line == NULL)
1462 return;
252b5132 1463
29b0f896
AM		 1464 line = parse_operands (line, mnemonic);
1465 if (line == NULL)
1466 return;
252b5132 1467
29b0f896
AM		 1468 /* Now we've parsed the mnemonic into a set of templates, and have the
1469 operands at hand. */
1470
1471 /* All intel opcodes have reversed operands except for "bound" and
1472 "enter". We also don't reverse intersegment "jmp" and "call"
1473 instructions with 2 immediate operands so that the immediate segment
1474 precedes the offset, as it does when in AT&T mode. "enter" and the
1475 intersegment "jmp" and "call" instructions are the only ones that
1476 have two immediate operands. */
1477 if (intel_syntax && i.operands > 1
1478 && (strcmp (mnemonic, "bound") != 0)
30123838 1479 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1480 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1481 swap_operands ();
1482
1483 if (i.imm_operands)
1484 optimize_imm ();
1485
b300c311
L		 1486 /* Don't optimize displacement for movabs since it only takes 64bit
1487 displacement. */
1488 if (i.disp_operands
1489 && (flag_code != CODE_64BIT
1490 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1491 optimize_disp ();
1492
1493 /* Next, we find a template that matches the given insn,
1494 making sure the overlap of the given operands types is consistent
1495 with the template operand types. */
252b5132 1496
29b0f896
AM		 1497 if (!match_template ())
1498 return;
252b5132 1499
cd61ebfe
AM		 1500 if (intel_syntax)
1501 {
1502 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1503 if (SYSV386_COMPAT
1504 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1505 i.tm.base_opcode ^= FloatR;
1506
1507 /* Zap movzx and movsx suffix. The suffix may have been set from
1508 "word ptr" or "byte ptr" on the source operand, but we'll use
1509 the suffix later to choose the destination register. */
1510 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1511 {
1512 if (i.reg_operands < 2
1513 && !i.suffix
1514 && (~i.tm.opcode_modifier
1515 & (No_bSuf
1516 | No_wSuf
1517 | No_lSuf
1518 | No_sSuf
1519 | No_xSuf
1520 | No_qSuf)))
1521 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1522
1523 i.suffix = 0;
1524 }
cd61ebfe 1525 }
24eab124 1526
29b0f896
AM		 1527 if (i.tm.opcode_modifier & FWait)
1528 if (!add_prefix (FWAIT_OPCODE))
1529 return;
252b5132 1530
29b0f896
AM		 1531 /* Check string instruction segment overrides. */
1532 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1533 {
1534 if (!check_string ())
5dd0794d 1535 return;
29b0f896 1536 }
5dd0794d 1537
29b0f896
AM		 1538 if (!process_suffix ())
1539 return;
e413e4e9 1540
29b0f896
AM		 1541 /* Make still unresolved immediate matches conform to size of immediate
1542 given in i.suffix. */
1543 if (!finalize_imm ())
1544 return;
252b5132 1545
29b0f896
AM		 1546 if (i.types[0] & Imm1)
1547 i.imm_operands = 0; /* kludge for shift insns. */
1548 if (i.types[0] & ImplicitRegister)
1549 i.reg_operands--;
1550 if (i.types[1] & ImplicitRegister)
1551 i.reg_operands--;
1552 if (i.types[2] & ImplicitRegister)
1553 i.reg_operands--;
252b5132 1554
29b0f896
AM		 1555 if (i.tm.opcode_modifier & ImmExt)
1556 {
02fc3089
L		 1557 expressionS *exp;
1558
ca164297
L		 1559 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1560 {
67c1ffbe 1561 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1562 operands with an opcode suffix which is coded in the same
1563 place as an 8-bit immediate field would be. Here we check
1564 those operands and remove them afterwards. */
1565 unsigned int x;
1566
a4622f40 1567 for (x = 0; x < i.operands; x++)
ca164297
L		 1568 if (i.op[x].regs->reg_num != x)
1569 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1570 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1571 i.operands = 0;
1572 }
1573
29b0f896
AM		 1574 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1575 opcode suffix which is coded in the same place as an 8-bit
1576 immediate field would be. Here we fake an 8-bit immediate
1577 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1578
29b0f896 1579 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1580
29b0f896
AM		 1581 exp = &im_expressions[i.imm_operands++];
1582 i.op[i.operands].imms = exp;
1583 i.types[i.operands++] = Imm8;
1584 exp->X_op = O_constant;
1585 exp->X_add_number = i.tm.extension_opcode;
1586 i.tm.extension_opcode = None;
1587 }
252b5132 1588
29b0f896
AM		 1589 /* For insns with operands there are more diddles to do to the opcode. */
1590 if (i.operands)
1591 {
1592 if (!process_operands ())
1593 return;
1594 }
1595 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1596 {
1597 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1598 as_warn (_("translating to `%sp'"), i.tm.name);
1599 }
252b5132 1600
29b0f896
AM		 1601 /* Handle conversion of 'int $3' --> special int3 insn. */
1602 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1603 {
1604 i.tm.base_opcode = INT3_OPCODE;
1605 i.imm_operands = 0;
1606 }
252b5132 1607
29b0f896
AM		 1608 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1609 && i.op[0].disps->X_op == O_constant)
1610 {
1611 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1612 the absolute address given by the constant. Since ix86 jumps and
1613 calls are pc relative, we need to generate a reloc. */
1614 i.op[0].disps->X_add_symbol = &abs_symbol;
1615 i.op[0].disps->X_op = O_symbol;
1616 }
252b5132 1617
29b0f896
AM		 1618 if ((i.tm.opcode_modifier & Rex64) != 0)
1619 i.rex |= REX_MODE64;
252b5132 1620
29b0f896
AM		 1621 /* For 8 bit registers we need an empty rex prefix. Also if the
1622 instruction already has a prefix, we need to convert old
1623 registers to new ones. */
773f551c 1624
29b0f896
AM		 1625 if (((i.types[0] & Reg8) != 0
1626 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1627 || ((i.types[1] & Reg8) != 0
1628 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1629 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1630 && i.rex != 0))
1631 {
1632 int x;
726c5dcd 1633
29b0f896
AM		 1634 i.rex |= REX_OPCODE;
1635 for (x = 0; x < 2; x++)
1636 {
1637 /* Look for 8 bit operand that uses old registers. */
1638 if ((i.types[x] & Reg8) != 0
1639 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1640 {
29b0f896
AM		 1641 /* In case it is "hi" register, give up. */
1642 if (i.op[x].regs->reg_num > 3)
0477af35 1643 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1644 i.op[x].regs->reg_name);
773f551c 1645
29b0f896
AM		 1646 /* Otherwise it is equivalent to the extended register.
1647 Since the encoding doesn't change this is merely
1648 cosmetic cleanup for debug output. */
1649
1650 i.op[x].regs = i.op[x].regs + 8;
773f551c 1651 }
29b0f896
AM		 1652 }
1653 }
773f551c 1654
29b0f896
AM		 1655 if (i.rex != 0)
1656 add_prefix (REX_OPCODE | i.rex);
1657
1658 /* We are ready to output the insn. */
1659 output_insn ();
1660}
1661
1662static char *
1663parse_insn (line, mnemonic)
1664 char *line;
1665 char *mnemonic;
1666{
1667 char *l = line;
1668 char *token_start = l;
1669 char *mnem_p;
5c6af06e
JB		 1670 int supported;
1671 const template *t;
29b0f896
AM		 1672
1673 /* Non-zero if we found a prefix only acceptable with string insns. */
1674 const char *expecting_string_instruction = NULL;
45288df1 1675
29b0f896
AM		 1676 while (1)
1677 {
1678 mnem_p = mnemonic;
1679 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1680 {
1681 mnem_p++;
1682 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1683 {
29b0f896
AM		 1684 as_bad (_("no such instruction: `%s'"), token_start);
1685 return NULL;
1686 }
1687 l++;
1688 }
1689 if (!is_space_char (*l)
1690 && *l != END_OF_INSN
e44823cf
JB		 1691 && (intel_syntax
1692 || (*l != PREFIX_SEPARATOR
1693 && *l != ',')))
29b0f896
AM		 1694 {
1695 as_bad (_("invalid character %s in mnemonic"),
1696 output_invalid (*l));
1697 return NULL;
1698 }
1699 if (token_start == l)
1700 {
e44823cf 1701 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1702 as_bad (_("expecting prefix; got nothing"));
1703 else
1704 as_bad (_("expecting mnemonic; got nothing"));
1705 return NULL;
1706 }
45288df1 1707
29b0f896
AM		 1708 /* Look up instruction (or prefix) via hash table. */
1709 current_templates = hash_find (op_hash, mnemonic);
47926f60 1710
29b0f896
AM		 1711 if (*l != END_OF_INSN
1712 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1713 && current_templates
1714 && (current_templates->start->opcode_modifier & IsPrefix))
1715 {
2dd88dca
JB		 1716 if (current_templates->start->cpu_flags
1717 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1718 {
1719 as_bad ((flag_code != CODE_64BIT
1720 ? _("`%s' is only supported in 64-bit mode")
1721 : _("`%s' is not supported in 64-bit mode")),
1722 current_templates->start->name);
1723 return NULL;
1724 }
29b0f896
AM		 1725 /* If we are in 16-bit mode, do not allow addr16 or data16.
1726 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1727 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1728 && flag_code != CODE_64BIT
1729 && (((current_templates->start->opcode_modifier & Size32) != 0)
1730 ^ (flag_code == CODE_16BIT)))
1731 {
1732 as_bad (_("redundant %s prefix"),
1733 current_templates->start->name);
1734 return NULL;
45288df1 1735 }
29b0f896
AM		 1736 /* Add prefix, checking for repeated prefixes. */
1737 switch (add_prefix (current_templates->start->base_opcode))
1738 {
1739 case 0:
1740 return NULL;
1741 case 2:
1742 expecting_string_instruction = current_templates->start->name;
1743 break;
1744 }
1745 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1746 token_start = ++l;
1747 }
1748 else
1749 break;
1750 }
45288df1 1751
29b0f896
AM		 1752 if (!current_templates)
1753 {
1754 /* See if we can get a match by trimming off a suffix. */
1755 switch (mnem_p[-1])
1756 {
1757 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1758 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1759 i.suffix = SHORT_MNEM_SUFFIX;
1760 else
29b0f896
AM		 1761 case BYTE_MNEM_SUFFIX:
1762 case QWORD_MNEM_SUFFIX:
1763 i.suffix = mnem_p[-1];
1764 mnem_p[-1] = '\0';
1765 current_templates = hash_find (op_hash, mnemonic);
1766 break;
1767 case SHORT_MNEM_SUFFIX:
1768 case LONG_MNEM_SUFFIX:
1769 if (!intel_syntax)
1770 {
1771 i.suffix = mnem_p[-1];
1772 mnem_p[-1] = '\0';
1773 current_templates = hash_find (op_hash, mnemonic);
1774 }
1775 break;
252b5132 1776
29b0f896
AM		 1777 /* Intel Syntax. */
1778 case 'd':
1779 if (intel_syntax)
1780 {
9306ca4a 1781 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1782 i.suffix = SHORT_MNEM_SUFFIX;
1783 else
1784 i.suffix = LONG_MNEM_SUFFIX;
1785 mnem_p[-1] = '\0';
1786 current_templates = hash_find (op_hash, mnemonic);
1787 }
1788 break;
1789 }
1790 if (!current_templates)
1791 {
1792 as_bad (_("no such instruction: `%s'"), token_start);
1793 return NULL;
1794 }
1795 }
252b5132 1796
29b0f896
AM		 1797 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1798 {
1799 /* Check for a branch hint. We allow ",pt" and ",pn" for
1800 predict taken and predict not taken respectively.
1801 I'm not sure that branch hints actually do anything on loop
1802 and jcxz insns (JumpByte) for current Pentium4 chips. They
1803 may work in the future and it doesn't hurt to accept them
1804 now. */
1805 if (l[0] == ',' && l[1] == 'p')
1806 {
1807 if (l[2] == 't')
1808 {
1809 if (!add_prefix (DS_PREFIX_OPCODE))
1810 return NULL;
1811 l += 3;
1812 }
1813 else if (l[2] == 'n')
1814 {
1815 if (!add_prefix (CS_PREFIX_OPCODE))
1816 return NULL;
1817 l += 3;
1818 }
1819 }
1820 }
1821 /* Any other comma loses. */
1822 if (*l == ',')
1823 {
1824 as_bad (_("invalid character %s in mnemonic"),
1825 output_invalid (*l));
1826 return NULL;
1827 }
252b5132 1828
29b0f896 1829 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1830 supported = 0;
1831 for (t = current_templates->start; t < current_templates->end; ++t)
1832 {
1833 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1834 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 1835 supported |= 1;
5c6af06e 1836 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 1837 supported |= 2;
5c6af06e
JB		 1838 }
1839 if (!(supported & 2))
1840 {
1841 as_bad (flag_code == CODE_64BIT
1842 ? _("`%s' is not supported in 64-bit mode")
1843 : _("`%s' is only supported in 64-bit mode"),
1844 current_templates->start->name);
1845 return NULL;
1846 }
1847 if (!(supported & 1))
29b0f896 1848 {
5c6af06e
JB		 1849 as_warn (_("`%s' is not supported on `%s%s'"),
1850 current_templates->start->name,
1851 cpu_arch_name,
1852 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1853 }
1854 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1855 {
1856 as_warn (_("use .code16 to ensure correct addressing mode"));
1857 }
252b5132 1858
29b0f896 1859 /* Check for rep/repne without a string instruction. */
f41bbced 1860 if (expecting_string_instruction)
29b0f896 1861 {
f41bbced
JB		 1862 static templates override;
1863
1864 for (t = current_templates->start; t < current_templates->end; ++t)
1865 if (t->opcode_modifier & IsString)
1866 break;
1867 if (t >= current_templates->end)
1868 {
1869 as_bad (_("expecting string instruction after `%s'"),
64e74474 1870 expecting_string_instruction);
f41bbced
JB		 1871 return NULL;
1872 }
1873 for (override.start = t; t < current_templates->end; ++t)
1874 if (!(t->opcode_modifier & IsString))
1875 break;
1876 override.end = t;
1877 current_templates = &override;
29b0f896 1878 }
252b5132 1879
29b0f896
AM		 1880 return l;
1881}
252b5132 1882
29b0f896
AM		 1883static char *
1884parse_operands (l, mnemonic)
1885 char *l;
1886 const char *mnemonic;
1887{
1888 char *token_start;
3138f287 1889
29b0f896
AM		 1890 /* 1 if operand is pending after ','. */
1891 unsigned int expecting_operand = 0;
252b5132 1892
29b0f896
AM		 1893 /* Non-zero if operand parens not balanced. */
1894 unsigned int paren_not_balanced;
1895
1896 while (*l != END_OF_INSN)
1897 {
1898 /* Skip optional white space before operand. */
1899 if (is_space_char (*l))
1900 ++l;
1901 if (!is_operand_char (*l) && *l != END_OF_INSN)
1902 {
1903 as_bad (_("invalid character %s before operand %d"),
1904 output_invalid (*l),
1905 i.operands + 1);
1906 return NULL;
1907 }
1908 token_start = l; /* after white space */
1909 paren_not_balanced = 0;
1910 while (paren_not_balanced || *l != ',')
1911 {
1912 if (*l == END_OF_INSN)
1913 {
1914 if (paren_not_balanced)
1915 {
1916 if (!intel_syntax)
1917 as_bad (_("unbalanced parenthesis in operand %d."),
1918 i.operands + 1);
1919 else
1920 as_bad (_("unbalanced brackets in operand %d."),
1921 i.operands + 1);
1922 return NULL;
1923 }
1924 else
1925 break; /* we are done */
1926 }
1927 else if (!is_operand_char (*l) && !is_space_char (*l))
1928 {
1929 as_bad (_("invalid character %s in operand %d"),
1930 output_invalid (*l),
1931 i.operands + 1);
1932 return NULL;
1933 }
1934 if (!intel_syntax)
1935 {
1936 if (*l == '(')
1937 ++paren_not_balanced;
1938 if (*l == ')')
1939 --paren_not_balanced;
1940 }
1941 else
1942 {
1943 if (*l == '[')
1944 ++paren_not_balanced;
1945 if (*l == ']')
1946 --paren_not_balanced;
1947 }
1948 l++;
1949 }
1950 if (l != token_start)
1951 { /* Yes, we've read in another operand. */
1952 unsigned int operand_ok;
1953 this_operand = i.operands++;
1954 if (i.operands > MAX_OPERANDS)
1955 {
1956 as_bad (_("spurious operands; (%d operands/instruction max)"),
1957 MAX_OPERANDS);
1958 return NULL;
1959 }
1960 /* Now parse operand adding info to 'i' as we go along. */
1961 END_STRING_AND_SAVE (l);
1962
1963 if (intel_syntax)
1964 operand_ok =
1965 i386_intel_operand (token_start,
1966 intel_float_operand (mnemonic));
1967 else
1968 operand_ok = i386_operand (token_start);
1969
1970 RESTORE_END_STRING (l);
1971 if (!operand_ok)
1972 return NULL;
1973 }
1974 else
1975 {
1976 if (expecting_operand)
1977 {
1978 expecting_operand_after_comma:
1979 as_bad (_("expecting operand after ','; got nothing"));
1980 return NULL;
1981 }
1982 if (*l == ',')
1983 {
1984 as_bad (_("expecting operand before ','; got nothing"));
1985 return NULL;
1986 }
1987 }
7f3f1ea2 1988
29b0f896
AM		 1989 /* Now *l must be either ',' or END_OF_INSN. */
1990 if (*l == ',')
1991 {
1992 if (*++l == END_OF_INSN)
1993 {
1994 /* Just skip it, if it's \n complain. */
1995 goto expecting_operand_after_comma;
1996 }
1997 expecting_operand = 1;
1998 }
1999 }
2000 return l;
2001}
7f3f1ea2 2002
29b0f896
AM		 2003static void
2004swap_operands ()
2005{
2006 union i386_op temp_op;
2007 unsigned int temp_type;
f86103b7 2008 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2009 int xchg1 = 0;
2010 int xchg2 = 0;
252b5132 2011
29b0f896
AM		 2012 if (i.operands == 2)
2013 {
2014 xchg1 = 0;
2015 xchg2 = 1;
2016 }
2017 else if (i.operands == 3)
2018 {
2019 xchg1 = 0;
2020 xchg2 = 2;
2021 }
2022 temp_type = i.types[xchg2];
2023 i.types[xchg2] = i.types[xchg1];
2024 i.types[xchg1] = temp_type;
2025 temp_op = i.op[xchg2];
2026 i.op[xchg2] = i.op[xchg1];
2027 i.op[xchg1] = temp_op;
2028 temp_reloc = i.reloc[xchg2];
2029 i.reloc[xchg2] = i.reloc[xchg1];
2030 i.reloc[xchg1] = temp_reloc;
2031
2032 if (i.mem_operands == 2)
2033 {
2034 const seg_entry *temp_seg;
2035 temp_seg = i.seg[0];
2036 i.seg[0] = i.seg[1];
2037 i.seg[1] = temp_seg;
2038 }
2039}
252b5132 2040
29b0f896
AM		 2041/* Try to ensure constant immediates are represented in the smallest
2042 opcode possible. */
2043static void
2044optimize_imm ()
2045{
2046 char guess_suffix = 0;
2047 int op;
252b5132 2048
29b0f896
AM		 2049 if (i.suffix)
2050 guess_suffix = i.suffix;
2051 else if (i.reg_operands)
2052 {
2053 /* Figure out a suffix from the last register operand specified.
2054 We can't do this properly yet, ie. excluding InOutPortReg,
2055 but the following works for instructions with immediates.
2056 In any case, we can't set i.suffix yet. */
2057 for (op = i.operands; --op >= 0;)
2058 if (i.types[op] & Reg)
252b5132 2059 {
29b0f896
AM		 2060 if (i.types[op] & Reg8)
2061 guess_suffix = BYTE_MNEM_SUFFIX;
2062 else if (i.types[op] & Reg16)
2063 guess_suffix = WORD_MNEM_SUFFIX;
2064 else if (i.types[op] & Reg32)
2065 guess_suffix = LONG_MNEM_SUFFIX;
2066 else if (i.types[op] & Reg64)
2067 guess_suffix = QWORD_MNEM_SUFFIX;
2068 break;
252b5132 2069 }
29b0f896
AM		 2070 }
2071 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2072 guess_suffix = WORD_MNEM_SUFFIX;
2073
2074 for (op = i.operands; --op >= 0;)
2075 if (i.types[op] & Imm)
2076 {
2077 switch (i.op[op].imms->X_op)
252b5132 2078 {
29b0f896
AM		 2079 case O_constant:
2080 /* If a suffix is given, this operand may be shortened. */
2081 switch (guess_suffix)
252b5132 2082 {
29b0f896
AM		 2083 case LONG_MNEM_SUFFIX:
2084 i.types[op] |= Imm32 | Imm64;
2085 break;
2086 case WORD_MNEM_SUFFIX:
2087 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2088 break;
2089 case BYTE_MNEM_SUFFIX:
2090 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2091 break;
252b5132 2092 }
252b5132 2093
29b0f896
AM		 2094 /* If this operand is at most 16 bits, convert it
2095 to a signed 16 bit number before trying to see
2096 whether it will fit in an even smaller size.
2097 This allows a 16-bit operand such as $0xffe0 to
2098 be recognised as within Imm8S range. */
2099 if ((i.types[op] & Imm16)
2100 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2101 {
29b0f896
AM		 2102 i.op[op].imms->X_add_number =
2103 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2104 }
2105 if ((i.types[op] & Imm32)
2106 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2107 == 0))
2108 {
2109 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2110 ^ ((offsetT) 1 << 31))
2111 - ((offsetT) 1 << 31));
2112 }
2113 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2114
29b0f896
AM		 2115 /* We must avoid matching of Imm32 templates when 64bit
2116 only immediate is available. */
2117 if (guess_suffix == QWORD_MNEM_SUFFIX)
2118 i.types[op] &= ~Imm32;
2119 break;
252b5132 2120
29b0f896
AM		 2121 case O_absent:
2122 case O_register:
2123 abort ();
2124
2125 /* Symbols and expressions. */
2126 default:
9cd96992
JB		 2127 /* Convert symbolic operand to proper sizes for matching, but don't
2128 prevent matching a set of insns that only supports sizes other
2129 than those matching the insn suffix. */
2130 {
2131 unsigned int mask, allowed = 0;
2132 const template *t;
2133
2134 for (t = current_templates->start; t < current_templates->end; ++t)
2135 allowed |= t->operand_types[op];
2136 switch (guess_suffix)
2137 {
2138 case QWORD_MNEM_SUFFIX:
2139 mask = Imm64 | Imm32S;
2140 break;
2141 case LONG_MNEM_SUFFIX:
2142 mask = Imm32;
2143 break;
2144 case WORD_MNEM_SUFFIX:
2145 mask = Imm16;
2146 break;
2147 case BYTE_MNEM_SUFFIX:
2148 mask = Imm8;
2149 break;
2150 default:
2151 mask = 0;
2152 break;
2153 }
64e74474
AM		 2154 if (mask & allowed)
2155 i.types[op] &= mask;
9cd96992 2156 }
29b0f896 2157 break;
252b5132 2158 }
29b0f896
AM		 2159 }
2160}
47926f60 2161
29b0f896
AM		 2162/* Try to use the smallest displacement type too. */
2163static void
2164optimize_disp ()
2165{
2166 int op;
3e73aa7c 2167
29b0f896 2168 for (op = i.operands; --op >= 0;)
b300c311 2169 if (i.types[op] & Disp)
252b5132 2170 {
b300c311 2171 if (i.op[op].disps->X_op == O_constant)
252b5132 2172 {
b300c311 2173 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2174
b300c311
L		 2175 if ((i.types[op] & Disp16)
2176 && (disp & ~(offsetT) 0xffff) == 0)
2177 {
2178 /* If this operand is at most 16 bits, convert
2179 to a signed 16 bit number and don't use 64bit
2180 displacement. */
2181 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2182 i.types[op] &= ~Disp64;
2183 }
2184 if ((i.types[op] & Disp32)
2185 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2186 {
2187 /* If this operand is at most 32 bits, convert
2188 to a signed 32 bit number and don't use 64bit
2189 displacement. */
2190 disp &= (((offsetT) 2 << 31) - 1);
2191 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2192 i.types[op] &= ~Disp64;
2193 }
2194 if (!disp && (i.types[op] & BaseIndex))
2195 {
2196 i.types[op] &= ~Disp;
2197 i.op[op].disps = 0;
2198 i.disp_operands--;
2199 }
2200 else if (flag_code == CODE_64BIT)
2201 {
2202 if (fits_in_signed_long (disp))
28a9d8f5
L		 2203 {
2204 i.types[op] &= ~Disp64;
2205 i.types[op] |= Disp32S;
2206 }
b300c311
L		 2207 if (fits_in_unsigned_long (disp))
2208 i.types[op] |= Disp32;
2209 }
2210 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2211 && fits_in_signed_byte (disp))
2212 i.types[op] |= Disp8;
252b5132 2213 }
67a4f2b7
AO		 2214 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2215 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2216 {
2217 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2218 i.op[op].disps, 0, i.reloc[op]);
2219 i.types[op] &= ~Disp;
2220 }
2221 else
b300c311
L		 2222 /* We only support 64bit displacement on constants. */
2223 i.types[op] &= ~Disp64;
252b5132 2224 }
29b0f896
AM		 2225}
2226
2227static int
2228match_template ()
2229{
2230 /* Points to template once we've found it. */
2231 const template *t;
2232 unsigned int overlap0, overlap1, overlap2;
2233 unsigned int found_reverse_match;
2234 int suffix_check;
2235
2236#define MATCH(overlap, given, template) \
2237 ((overlap & ~JumpAbsolute) \
2238 && (((given) & (BaseIndex | JumpAbsolute)) \
2239 == ((overlap) & (BaseIndex | JumpAbsolute))))
2240
2241 /* If given types r0 and r1 are registers they must be of the same type
2242 unless the expected operand type register overlap is null.
2243 Note that Acc in a template matches every size of reg. */
2244#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2245 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2246 || ((g0) & Reg) == ((g1) & Reg) \
2247 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2248
2249 overlap0 = 0;
2250 overlap1 = 0;
2251 overlap2 = 0;
2252 found_reverse_match = 0;
2253 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2254 ? No_bSuf
2255 : (i.suffix == WORD_MNEM_SUFFIX
2256 ? No_wSuf
2257 : (i.suffix == SHORT_MNEM_SUFFIX
2258 ? No_sSuf
2259 : (i.suffix == LONG_MNEM_SUFFIX
2260 ? No_lSuf
2261 : (i.suffix == QWORD_MNEM_SUFFIX
2262 ? No_qSuf
2263 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2264 ? No_xSuf : 0))))));
2265
45aa61fe 2266 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896
AM		 2267 {
2268 /* Must have right number of operands. */
2269 if (i.operands != t->operands)
2270 continue;
2271
2272 /* Check the suffix, except for some instructions in intel mode. */
2273 if ((t->opcode_modifier & suffix_check)
2274 && !(intel_syntax
9306ca4a 2275 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2276 continue;
2277
45aa61fe
AM		 2278 /* In general, don't allow 64-bit operands in 32-bit mode. */
2279 if (i.suffix == QWORD_MNEM_SUFFIX
2280 && flag_code != CODE_64BIT
2281 && (intel_syntax
2282 ? (!(t->opcode_modifier & IgnoreSize)
2283 && !intel_float_operand (t->name))
2284 : intel_float_operand (t->name) != 2)
2285 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2286 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2287 && (t->base_opcode != 0x0fc7
2288 || t->extension_opcode != 1 /* cmpxchg8b */))
2289 continue;
2290
29b0f896
AM		 2291 /* Do not verify operands when there are none. */
2292 else if (!t->operands)
2293 {
2294 if (t->cpu_flags & ~cpu_arch_flags)
2295 continue;
2296 /* We've found a match; break out of loop. */
2297 break;
2298 }
252b5132 2299
29b0f896
AM		 2300 overlap0 = i.types[0] & t->operand_types[0];
2301 switch (t->operands)
2302 {
2303 case 1:
2304 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2305 continue;
2306 break;
2307 case 2:
2308 case 3:
2309 overlap1 = i.types[1] & t->operand_types[1];
2310 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2311 || !MATCH (overlap1, i.types[1], t->operand_types[1])
cb712a9e
L		 2312 /* monitor in SSE3 is a very special case. The first
2313 register and the second register may have differnet
2314 sizes. */
2315 || !((t->base_opcode == 0x0f01
2316 && t->extension_opcode == 0xc8)
2317 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2318 t->operand_types[0],
2319 overlap1, i.types[1],
2320 t->operand_types[1])))
29b0f896
AM		 2321 {
2322 /* Check if other direction is valid ... */
2323 if ((t->opcode_modifier & (D | FloatD)) == 0)
2324 continue;
2325
2326 /* Try reversing direction of operands. */
2327 overlap0 = i.types[0] & t->operand_types[1];
2328 overlap1 = i.types[1] & t->operand_types[0];
2329 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2330 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2331 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2332 t->operand_types[1],
2333 overlap1, i.types[1],
2334 t->operand_types[0]))
2335 {
2336 /* Does not match either direction. */
2337 continue;
2338 }
2339 /* found_reverse_match holds which of D or FloatDR
2340 we've found. */
2341 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2342 }
2343 /* Found a forward 2 operand match here. */
2344 else if (t->operands == 3)
2345 {
2346 /* Here we make use of the fact that there are no
2347 reverse match 3 operand instructions, and all 3
2348 operand instructions only need to be checked for
2349 register consistency between operands 2 and 3. */
2350 overlap2 = i.types[2] & t->operand_types[2];
2351 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2352 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2353 t->operand_types[1],
2354 overlap2, i.types[2],
2355 t->operand_types[2]))
2356
2357 continue;
2358 }
2359 /* Found either forward/reverse 2 or 3 operand match here:
2360 slip through to break. */
2361 }
2362 if (t->cpu_flags & ~cpu_arch_flags)
2363 {
2364 found_reverse_match = 0;
2365 continue;
2366 }
2367 /* We've found a match; break out of loop. */
2368 break;
2369 }
2370
2371 if (t == current_templates->end)
2372 {
2373 /* We found no match. */
2374 as_bad (_("suffix or operands invalid for `%s'"),
2375 current_templates->start->name);
2376 return 0;
2377 }
252b5132 2378
29b0f896
AM		 2379 if (!quiet_warnings)
2380 {
2381 if (!intel_syntax
2382 && ((i.types[0] & JumpAbsolute)
2383 != (t->operand_types[0] & JumpAbsolute)))
2384 {
2385 as_warn (_("indirect %s without `*'"), t->name);
2386 }
2387
2388 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2389 == (IsPrefix | IgnoreSize))
2390 {
2391 /* Warn them that a data or address size prefix doesn't
2392 affect assembly of the next line of code. */
2393 as_warn (_("stand-alone `%s' prefix"), t->name);
2394 }
2395 }
2396
2397 /* Copy the template we found. */
2398 i.tm = *t;
2399 if (found_reverse_match)
2400 {
2401 /* If we found a reverse match we must alter the opcode
2402 direction bit. found_reverse_match holds bits to change
2403 (different for int & float insns). */
2404
2405 i.tm.base_opcode ^= found_reverse_match;
2406
2407 i.tm.operand_types[0] = t->operand_types[1];
2408 i.tm.operand_types[1] = t->operand_types[0];
2409 }
2410
2411 return 1;
2412}
2413
2414static int
2415check_string ()
2416{
2417 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2418 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2419 {
2420 if (i.seg[0] != NULL && i.seg[0] != &es)
2421 {
2422 as_bad (_("`%s' operand %d must use `%%es' segment"),
2423 i.tm.name,
2424 mem_op + 1);
2425 return 0;
2426 }
2427 /* There's only ever one segment override allowed per instruction.
2428 This instruction possibly has a legal segment override on the
2429 second operand, so copy the segment to where non-string
2430 instructions store it, allowing common code. */
2431 i.seg[0] = i.seg[1];
2432 }
2433 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2434 {
2435 if (i.seg[1] != NULL && i.seg[1] != &es)
2436 {
2437 as_bad (_("`%s' operand %d must use `%%es' segment"),
2438 i.tm.name,
2439 mem_op + 2);
2440 return 0;
2441 }
2442 }
2443 return 1;
2444}
2445
2446static int
543613e9 2447process_suffix (void)
29b0f896
AM		 2448{
2449 /* If matched instruction specifies an explicit instruction mnemonic
2450 suffix, use it. */
2451 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2452 {
2453 if (i.tm.opcode_modifier & Size16)
2454 i.suffix = WORD_MNEM_SUFFIX;
2455 else if (i.tm.opcode_modifier & Size64)
2456 i.suffix = QWORD_MNEM_SUFFIX;
2457 else
2458 i.suffix = LONG_MNEM_SUFFIX;
2459 }
2460 else if (i.reg_operands)
2461 {
2462 /* If there's no instruction mnemonic suffix we try to invent one
2463 based on register operands. */
2464 if (!i.suffix)
2465 {
2466 /* We take i.suffix from the last register operand specified,
2467 Destination register type is more significant than source
2468 register type. */
2469 int op;
543613e9 2470
29b0f896
AM		 2471 for (op = i.operands; --op >= 0;)
2472 if ((i.types[op] & Reg)
2473 && !(i.tm.operand_types[op] & InOutPortReg))
2474 {
2475 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2476 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2477 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2478 LONG_MNEM_SUFFIX);
2479 break;
2480 }
2481 }
2482 else if (i.suffix == BYTE_MNEM_SUFFIX)
2483 {
2484 if (!check_byte_reg ())
2485 return 0;
2486 }
2487 else if (i.suffix == LONG_MNEM_SUFFIX)
2488 {
2489 if (!check_long_reg ())
2490 return 0;
2491 }
2492 else if (i.suffix == QWORD_MNEM_SUFFIX)
2493 {
2494 if (!check_qword_reg ())
2495 return 0;
2496 }
2497 else if (i.suffix == WORD_MNEM_SUFFIX)
2498 {
2499 if (!check_word_reg ())
2500 return 0;
2501 }
2502 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2503 /* Do nothing if the instruction is going to ignore the prefix. */
2504 ;
2505 else
2506 abort ();
2507 }
9306ca4a
JB		 2508 else if ((i.tm.opcode_modifier & DefaultSize)
2509 && !i.suffix
2510 /* exclude fldenv/frstor/fsave/fstenv */
2511 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2512 {
2513 i.suffix = stackop_size;
2514 }
9306ca4a
JB		 2515 else if (intel_syntax
2516 && !i.suffix
2517 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2518 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2519 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2520 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2521 {
2522 switch (flag_code)
2523 {
2524 case CODE_64BIT:
2525 if (!(i.tm.opcode_modifier & No_qSuf))
2526 {
2527 i.suffix = QWORD_MNEM_SUFFIX;
2528 break;
2529 }
2530 case CODE_32BIT:
2531 if (!(i.tm.opcode_modifier & No_lSuf))
2532 i.suffix = LONG_MNEM_SUFFIX;
2533 break;
2534 case CODE_16BIT:
2535 if (!(i.tm.opcode_modifier & No_wSuf))
2536 i.suffix = WORD_MNEM_SUFFIX;
2537 break;
2538 }
2539 }
252b5132 2540
9306ca4a 2541 if (!i.suffix)
29b0f896 2542 {
9306ca4a
JB		 2543 if (!intel_syntax)
2544 {
2545 if (i.tm.opcode_modifier & W)
2546 {
2547 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2548 return 0;
2549 }
2550 }
2551 else
2552 {
64e74474
AM		 2553 unsigned int suffixes = (~i.tm.opcode_modifier
2554 & (No_bSuf
2555 | No_wSuf
2556 | No_lSuf
2557 | No_sSuf
2558 | No_xSuf
2559 | No_qSuf));
9306ca4a
JB		 2560
2561 if ((i.tm.opcode_modifier & W)
2562 || ((suffixes & (suffixes - 1))
2563 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2564 {
2565 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2566 return 0;
2567 }
2568 }
29b0f896 2569 }
252b5132 2570
9306ca4a
JB		 2571 /* Change the opcode based on the operand size given by i.suffix;
2572 We don't need to change things for byte insns. */
2573
29b0f896
AM		 2574 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2575 {
2576 /* It's not a byte, select word/dword operation. */
2577 if (i.tm.opcode_modifier & W)
2578 {
2579 if (i.tm.opcode_modifier & ShortForm)
2580 i.tm.base_opcode |= 8;
2581 else
2582 i.tm.base_opcode |= 1;
2583 }
0f3f3d8b 2584
29b0f896
AM		 2585 /* Now select between word & dword operations via the operand
2586 size prefix, except for instructions that will ignore this
2587 prefix anyway. */
cb712a9e
L		 2588 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2589 {
2590 /* monitor in SSE3 is a very special case. The default size
2591 of AX is the size of mode. The address size override
2592 prefix will change the size of AX. */
2593 if (i.op->regs[0].reg_type &
2594 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2595 if (!add_prefix (ADDR_PREFIX_OPCODE))
2596 return 0;
2597 }
2598 else if (i.suffix != QWORD_MNEM_SUFFIX
2599 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2600 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2601 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2602 || (flag_code == CODE_64BIT
2603 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2604 {
2605 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2606
29b0f896
AM		 2607 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2608 prefix = ADDR_PREFIX_OPCODE;
252b5132 2609
29b0f896
AM		 2610 if (!add_prefix (prefix))
2611 return 0;
24eab124 2612 }
252b5132 2613
29b0f896
AM		 2614 /* Set mode64 for an operand. */
2615 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2616 && flag_code == CODE_64BIT
29b0f896 2617 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2618 i.rex |= REX_MODE64;
3e73aa7c 2619
29b0f896
AM		 2620 /* Size floating point instruction. */
2621 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2622 if (i.tm.opcode_modifier & FloatMF)
2623 i.tm.base_opcode ^= 4;
29b0f896 2624 }
7ecd2f8b 2625
29b0f896
AM		 2626 return 1;
2627}
3e73aa7c 2628
29b0f896 2629static int
543613e9 2630check_byte_reg (void)
29b0f896
AM		 2631{
2632 int op;
543613e9 2633
29b0f896
AM		 2634 for (op = i.operands; --op >= 0;)
2635 {
2636 /* If this is an eight bit register, it's OK. If it's the 16 or
2637 32 bit version of an eight bit register, we will just use the
2638 low portion, and that's OK too. */
2639 if (i.types[op] & Reg8)
2640 continue;
2641
2642 /* movzx and movsx should not generate this warning. */
2643 if (intel_syntax
2644 && (i.tm.base_opcode == 0xfb7
2645 || i.tm.base_opcode == 0xfb6
2646 || i.tm.base_opcode == 0x63
2647 || i.tm.base_opcode == 0xfbe
2648 || i.tm.base_opcode == 0xfbf))
2649 continue;
2650
65ec77d2 2651 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2652 {
2653 /* Prohibit these changes in the 64bit mode, since the
2654 lowering is more complicated. */
2655 if (flag_code == CODE_64BIT
2656 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2657 {
0f3f3d8b 2658 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2659 i.op[op].regs->reg_name,
2660 i.suffix);
2661 return 0;
2662 }
2663#if REGISTER_WARNINGS
2664 if (!quiet_warnings
2665 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2666 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2667 (i.op[op].regs + (i.types[op] & Reg16
2668 ? REGNAM_AL - REGNAM_AX
2669 : REGNAM_AL - REGNAM_EAX))->reg_name,
2670 i.op[op].regs->reg_name,
2671 i.suffix);
2672#endif
2673 continue;
2674 }
2675 /* Any other register is bad. */
2676 if (i.types[op] & (Reg | RegMMX | RegXMM
2677 | SReg2 | SReg3
2678 | Control | Debug | Test
2679 | FloatReg | FloatAcc))
2680 {
2681 as_bad (_("`%%%s' not allowed with `%s%c'"),
2682 i.op[op].regs->reg_name,
2683 i.tm.name,
2684 i.suffix);
2685 return 0;
2686 }
2687 }
2688 return 1;
2689}
2690
2691static int
2692check_long_reg ()
2693{
2694 int op;
2695
2696 for (op = i.operands; --op >= 0;)
2697 /* Reject eight bit registers, except where the template requires
2698 them. (eg. movzb) */
2699 if ((i.types[op] & Reg8) != 0
2700 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2701 {
2702 as_bad (_("`%%%s' not allowed with `%s%c'"),
2703 i.op[op].regs->reg_name,
2704 i.tm.name,
2705 i.suffix);
2706 return 0;
2707 }
2708 /* Warn if the e prefix on a general reg is missing. */
2709 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2710 && (i.types[op] & Reg16) != 0
2711 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2712 {
2713 /* Prohibit these changes in the 64bit mode, since the
2714 lowering is more complicated. */
2715 if (flag_code == CODE_64BIT)
252b5132 2716 {
0f3f3d8b 2717 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2718 i.op[op].regs->reg_name,
2719 i.suffix);
2720 return 0;
252b5132 2721 }
29b0f896
AM		 2722#if REGISTER_WARNINGS
2723 else
2724 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2725 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2726 i.op[op].regs->reg_name,
2727 i.suffix);
2728#endif
252b5132 2729 }
29b0f896
AM		 2730 /* Warn if the r prefix on a general reg is missing. */
2731 else if ((i.types[op] & Reg64) != 0
2732 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2733 {
0f3f3d8b 2734 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2735 i.op[op].regs->reg_name,
2736 i.suffix);
2737 return 0;
2738 }
2739 return 1;
2740}
252b5132 2741
29b0f896
AM		 2742static int
2743check_qword_reg ()
2744{
2745 int op;
252b5132 2746
29b0f896
AM		 2747 for (op = i.operands; --op >= 0; )
2748 /* Reject eight bit registers, except where the template requires
2749 them. (eg. movzb) */
2750 if ((i.types[op] & Reg8) != 0
2751 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2752 {
2753 as_bad (_("`%%%s' not allowed with `%s%c'"),
2754 i.op[op].regs->reg_name,
2755 i.tm.name,
2756 i.suffix);
2757 return 0;
2758 }
2759 /* Warn if the e prefix on a general reg is missing. */
2760 else if (((i.types[op] & Reg16) != 0
2761 || (i.types[op] & Reg32) != 0)
2762 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2763 {
2764 /* Prohibit these changes in the 64bit mode, since the
2765 lowering is more complicated. */
0f3f3d8b 2766 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2767 i.op[op].regs->reg_name,
2768 i.suffix);
2769 return 0;
252b5132 2770 }
29b0f896
AM		 2771 return 1;
2772}
252b5132 2773
29b0f896
AM		 2774static int
2775check_word_reg ()
2776{
2777 int op;
2778 for (op = i.operands; --op >= 0;)
2779 /* Reject eight bit registers, except where the template requires
2780 them. (eg. movzb) */
2781 if ((i.types[op] & Reg8) != 0
2782 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2783 {
2784 as_bad (_("`%%%s' not allowed with `%s%c'"),
2785 i.op[op].regs->reg_name,
2786 i.tm.name,
2787 i.suffix);
2788 return 0;
2789 }
2790 /* Warn if the e prefix on a general reg is present. */
2791 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2792 && (i.types[op] & Reg32) != 0
2793 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2794 {
29b0f896
AM		 2795 /* Prohibit these changes in the 64bit mode, since the
2796 lowering is more complicated. */
2797 if (flag_code == CODE_64BIT)
252b5132 2798 {
0f3f3d8b 2799 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2800 i.op[op].regs->reg_name,
2801 i.suffix);
2802 return 0;
252b5132 2803 }
29b0f896
AM		 2804 else
2805#if REGISTER_WARNINGS
2806 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2807 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2808 i.op[op].regs->reg_name,
2809 i.suffix);
2810#endif
2811 }
2812 return 1;
2813}
252b5132 2814
29b0f896
AM		 2815static int
2816finalize_imm ()
2817{
2818 unsigned int overlap0, overlap1, overlap2;
2819
2820 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2821 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2822 && overlap0 != Imm8 && overlap0 != Imm8S
2823 && overlap0 != Imm16 && overlap0 != Imm32S
2824 && overlap0 != Imm32 && overlap0 != Imm64)
2825 {
2826 if (i.suffix)
2827 {
2828 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2829 ? Imm8 | Imm8S
2830 : (i.suffix == WORD_MNEM_SUFFIX
2831 ? Imm16
2832 : (i.suffix == QWORD_MNEM_SUFFIX
2833 ? Imm64 | Imm32S
2834 : Imm32)));
2835 }
2836 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2837 || overlap0 == (Imm16 | Imm32)
2838 || overlap0 == (Imm16 | Imm32S))
2839 {
2840 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2841 ? Imm16 : Imm32S);
2842 }
2843 if (overlap0 != Imm8 && overlap0 != Imm8S
2844 && overlap0 != Imm16 && overlap0 != Imm32S
2845 && overlap0 != Imm32 && overlap0 != Imm64)
2846 {
2847 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2848 return 0;
2849 }
2850 }
2851 i.types[0] = overlap0;
2852
2853 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2854 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2855 && overlap1 != Imm8 && overlap1 != Imm8S
2856 && overlap1 != Imm16 && overlap1 != Imm32S
2857 && overlap1 != Imm32 && overlap1 != Imm64)
2858 {
2859 if (i.suffix)
2860 {
2861 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2862 ? Imm8 | Imm8S
2863 : (i.suffix == WORD_MNEM_SUFFIX
2864 ? Imm16
2865 : (i.suffix == QWORD_MNEM_SUFFIX
2866 ? Imm64 | Imm32S
2867 : Imm32)));
2868 }
2869 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2870 || overlap1 == (Imm16 | Imm32)
2871 || overlap1 == (Imm16 | Imm32S))
2872 {
2873 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2874 ? Imm16 : Imm32S);
2875 }
2876 if (overlap1 != Imm8 && overlap1 != Imm8S
2877 && overlap1 != Imm16 && overlap1 != Imm32S
2878 && overlap1 != Imm32 && overlap1 != Imm64)
2879 {
2880 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2881 return 0;
2882 }
2883 }
2884 i.types[1] = overlap1;
2885
2886 overlap2 = i.types[2] & i.tm.operand_types[2];
2887 assert ((overlap2 & Imm) == 0);
2888 i.types[2] = overlap2;
2889
2890 return 1;
2891}
2892
2893static int
2894process_operands ()
2895{
2896 /* Default segment register this instruction will use for memory
2897 accesses. 0 means unknown. This is only for optimizing out
2898 unnecessary segment overrides. */
2899 const seg_entry *default_seg = 0;
2900
2901 /* The imul $imm, %reg instruction is converted into
2902 imul $imm, %reg, %reg, and the clr %reg instruction
2903 is converted into xor %reg, %reg. */
2904 if (i.tm.opcode_modifier & regKludge)
2905 {
2906 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2907 /* Pretend we saw the extra register operand. */
2908 assert (i.op[first_reg_op + 1].regs == 0);
2909 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2910 i.types[first_reg_op + 1] = i.types[first_reg_op];
2911 i.reg_operands = 2;
2912 }
2913
2914 if (i.tm.opcode_modifier & ShortForm)
2915 {
2916 /* The register or float register operand is in operand 0 or 1. */
2917 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2918 /* Register goes in low 3 bits of opcode. */
2919 i.tm.base_opcode |= i.op[op].regs->reg_num;
2920 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2921 i.rex |= REX_EXTZ;
2922 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2923 {
2924 /* Warn about some common errors, but press on regardless.
2925 The first case can be generated by gcc (<= 2.8.1). */
2926 if (i.operands == 2)
2927 {
2928 /* Reversed arguments on faddp, fsubp, etc. */
2929 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2930 i.op[1].regs->reg_name,
2931 i.op[0].regs->reg_name);
2932 }
2933 else
2934 {
2935 /* Extraneous `l' suffix on fp insn. */
2936 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2937 i.op[0].regs->reg_name);
2938 }
2939 }
2940 }
2941 else if (i.tm.opcode_modifier & Modrm)
2942 {
2943 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2944 must be put into the modrm byte). Now, we make the modrm and
2945 index base bytes based on all the info we've collected. */
29b0f896
AM		 2946
2947 default_seg = build_modrm_byte ();
2948 }
2949 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2950 {
2951 if (i.tm.base_opcode == POP_SEG_SHORT
2952 && i.op[0].regs->reg_num == 1)
2953 {
2954 as_bad (_("you can't `pop %%cs'"));
2955 return 0;
2956 }
2957 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2958 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2959 i.rex |= REX_EXTZ;
2960 }
2961 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2962 {
2963 default_seg = &ds;
2964 }
2965 else if ((i.tm.opcode_modifier & IsString) != 0)
2966 {
2967 /* For the string instructions that allow a segment override
2968 on one of their operands, the default segment is ds. */
2969 default_seg = &ds;
2970 }
2971
30123838
JB		 2972 if ((i.tm.base_opcode == 0x8d /* lea */
2973 || (i.tm.cpu_flags & CpuSVME))
2974 && i.seg[0] && !quiet_warnings)
2975 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2976
2977 /* If a segment was explicitly specified, and the specified segment
2978 is not the default, use an opcode prefix to select it. If we
2979 never figured out what the default segment is, then default_seg
2980 will be zero at this point, and the specified segment prefix will
2981 always be used. */
29b0f896
AM		 2982 if ((i.seg[0]) && (i.seg[0] != default_seg))
2983 {
2984 if (!add_prefix (i.seg[0]->seg_prefix))
2985 return 0;
2986 }
2987 return 1;
2988}
2989
2990static const seg_entry *
2991build_modrm_byte ()
2992{
2993 const seg_entry *default_seg = 0;
2994
2995 /* i.reg_operands MUST be the number of real register operands;
2996 implicit registers do not count. */
2997 if (i.reg_operands == 2)
2998 {
2999 unsigned int source, dest;
3000 source = ((i.types[0]
3001 & (Reg | RegMMX | RegXMM
3002 | SReg2 | SReg3
3003 | Control | Debug | Test))
3004 ? 0 : 1);
3005 dest = source + 1;
3006
3007 i.rm.mode = 3;
3008 /* One of the register operands will be encoded in the i.tm.reg
3009 field, the other in the combined i.tm.mode and i.tm.regmem
3010 fields. If no form of this instruction supports a memory
3011 destination operand, then we assume the source operand may
3012 sometimes be a memory operand and so we need to store the
3013 destination in the i.rm.reg field. */
3014 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3015 {
3016 i.rm.reg = i.op[dest].regs->reg_num;
3017 i.rm.regmem = i.op[source].regs->reg_num;
3018 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3019 i.rex |= REX_EXTX;
3020 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3021 i.rex |= REX_EXTZ;
3022 }
3023 else
3024 {
3025 i.rm.reg = i.op[source].regs->reg_num;
3026 i.rm.regmem = i.op[dest].regs->reg_num;
3027 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3028 i.rex |= REX_EXTZ;
3029 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3030 i.rex |= REX_EXTX;
3031 }
c4a530c5
JB		 3032 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3033 {
3034 if (!((i.types[0] | i.types[1]) & Control))
3035 abort ();
3036 i.rex &= ~(REX_EXTX | REX_EXTZ);
3037 add_prefix (LOCK_PREFIX_OPCODE);
3038 }
29b0f896
AM		 3039 }
3040 else
3041 { /* If it's not 2 reg operands... */
3042 if (i.mem_operands)
3043 {
3044 unsigned int fake_zero_displacement = 0;
3045 unsigned int op = ((i.types[0] & AnyMem)
3046 ? 0
3047 : (i.types[1] & AnyMem) ? 1 : 2);
3048
3049 default_seg = &ds;
3050
3051 if (i.base_reg == 0)
3052 {
3053 i.rm.mode = 0;
3054 if (!i.disp_operands)
3055 fake_zero_displacement = 1;
3056 if (i.index_reg == 0)
3057 {
3058 /* Operand is just <disp> */
20f0a1fc 3059 if (flag_code == CODE_64BIT)
29b0f896
AM		 3060 {
3061 /* 64bit mode overwrites the 32bit absolute
3062 addressing by RIP relative addressing and
3063 absolute addressing is encoded by one of the
3064 redundant SIB forms. */
3065 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3066 i.sib.base = NO_BASE_REGISTER;
3067 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3068 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3069 }
3070 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3071 {
3072 i.rm.regmem = NO_BASE_REGISTER_16;
3073 i.types[op] = Disp16;
3074 }
3075 else
3076 {
3077 i.rm.regmem = NO_BASE_REGISTER;
3078 i.types[op] = Disp32;
29b0f896
AM		 3079 }
3080 }
3081 else /* !i.base_reg && i.index_reg */
3082 {
3083 i.sib.index = i.index_reg->reg_num;
3084 i.sib.base = NO_BASE_REGISTER;
3085 i.sib.scale = i.log2_scale_factor;
3086 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3087 i.types[op] &= ~Disp;
3088 if (flag_code != CODE_64BIT)
3089 i.types[op] |= Disp32; /* Must be 32 bit */
3090 else
3091 i.types[op] |= Disp32S;
3092 if ((i.index_reg->reg_flags & RegRex) != 0)
3093 i.rex |= REX_EXTY;
3094 }
3095 }
3096 /* RIP addressing for 64bit mode. */
3097 else if (i.base_reg->reg_type == BaseIndex)
3098 {
3099 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3100 i.types[op] &= ~ Disp;
29b0f896
AM		 3101 i.types[op] |= Disp32S;
3102 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3103 if (! i.disp_operands)
3104 fake_zero_displacement = 1;
29b0f896
AM		 3105 }
3106 else if (i.base_reg->reg_type & Reg16)
3107 {
3108 switch (i.base_reg->reg_num)
3109 {
3110 case 3: /* (%bx) */
3111 if (i.index_reg == 0)
3112 i.rm.regmem = 7;
3113 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3114 i.rm.regmem = i.index_reg->reg_num - 6;
3115 break;
3116 case 5: /* (%bp) */
3117 default_seg = &ss;
3118 if (i.index_reg == 0)
3119 {
3120 i.rm.regmem = 6;
3121 if ((i.types[op] & Disp) == 0)
3122 {
3123 /* fake (%bp) into 0(%bp) */
3124 i.types[op] |= Disp8;
252b5132 3125 fake_zero_displacement = 1;
29b0f896
AM		 3126 }
3127 }
3128 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3129 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3130 break;
3131 default: /* (%si) -> 4 or (%di) -> 5 */
3132 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3133 }
3134 i.rm.mode = mode_from_disp_size (i.types[op]);
3135 }
3136 else /* i.base_reg and 32/64 bit mode */
3137 {
3138 if (flag_code == CODE_64BIT
3139 && (i.types[op] & Disp))
20f0a1fc
NC		 3140 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3141
29b0f896
AM		 3142 i.rm.regmem = i.base_reg->reg_num;
3143 if ((i.base_reg->reg_flags & RegRex) != 0)
3144 i.rex |= REX_EXTZ;
3145 i.sib.base = i.base_reg->reg_num;
3146 /* x86-64 ignores REX prefix bit here to avoid decoder
3147 complications. */
3148 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3149 {
3150 default_seg = &ss;
3151 if (i.disp_operands == 0)
3152 {
3153 fake_zero_displacement = 1;
3154 i.types[op] |= Disp8;
3155 }
3156 }
3157 else if (i.base_reg->reg_num == ESP_REG_NUM)
3158 {
3159 default_seg = &ss;
3160 }
3161 i.sib.scale = i.log2_scale_factor;
3162 if (i.index_reg == 0)
3163 {
3164 /* <disp>(%esp) becomes two byte modrm with no index
3165 register. We've already stored the code for esp
3166 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3167 Any base register besides %esp will not use the
3168 extra modrm byte. */
3169 i.sib.index = NO_INDEX_REGISTER;
3170#if !SCALE1_WHEN_NO_INDEX
3171 /* Another case where we force the second modrm byte. */
3172 if (i.log2_scale_factor)
3173 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3174#endif
29b0f896
AM		 3175 }
3176 else
3177 {
3178 i.sib.index = i.index_reg->reg_num;
3179 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3180 if ((i.index_reg->reg_flags & RegRex) != 0)
3181 i.rex |= REX_EXTY;
3182 }
67a4f2b7
AO		 3183
3184 if (i.disp_operands
3185 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3186 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3187 i.rm.mode = 0;
3188 else
3189 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3190 }
252b5132 3191
29b0f896
AM		 3192 if (fake_zero_displacement)
3193 {
3194 /* Fakes a zero displacement assuming that i.types[op]
3195 holds the correct displacement size. */
3196 expressionS *exp;
3197
3198 assert (i.op[op].disps == 0);
3199 exp = &disp_expressions[i.disp_operands++];
3200 i.op[op].disps = exp;
3201 exp->X_op = O_constant;
3202 exp->X_add_number = 0;
3203 exp->X_add_symbol = (symbolS *) 0;
3204 exp->X_op_symbol = (symbolS *) 0;
3205 }
3206 }
252b5132 3207
29b0f896
AM		 3208 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3209 (if any) based on i.tm.extension_opcode. Again, we must be
3210 careful to make sure that segment/control/debug/test/MMX
3211 registers are coded into the i.rm.reg field. */
3212 if (i.reg_operands)
3213 {
3214 unsigned int op =
3215 ((i.types[0]
3216 & (Reg | RegMMX | RegXMM
3217 | SReg2 | SReg3
3218 | Control | Debug | Test))
3219 ? 0
3220 : ((i.types[1]
3221 & (Reg | RegMMX | RegXMM
3222 | SReg2 | SReg3
3223 | Control | Debug | Test))
3224 ? 1
3225 : 2));
3226 /* If there is an extension opcode to put here, the register
3227 number must be put into the regmem field. */
3228 if (i.tm.extension_opcode != None)
3229 {
3230 i.rm.regmem = i.op[op].regs->reg_num;
3231 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3232 i.rex |= REX_EXTZ;
3233 }
3234 else
3235 {
3236 i.rm.reg = i.op[op].regs->reg_num;
3237 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3238 i.rex |= REX_EXTX;
3239 }
252b5132 3240
29b0f896
AM		 3241 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3242 must set it to 3 to indicate this is a register operand
3243 in the regmem field. */
3244 if (!i.mem_operands)
3245 i.rm.mode = 3;
3246 }
252b5132 3247
29b0f896
AM		 3248 /* Fill in i.rm.reg field with extension opcode (if any). */
3249 if (i.tm.extension_opcode != None)
3250 i.rm.reg = i.tm.extension_opcode;
3251 }
3252 return default_seg;
3253}
252b5132 3254
29b0f896
AM		 3255static void
3256output_branch ()
3257{
3258 char *p;
3259 int code16;
3260 int prefix;
3261 relax_substateT subtype;
3262 symbolS *sym;
3263 offsetT off;
3264
3265 code16 = 0;
3266 if (flag_code == CODE_16BIT)
3267 code16 = CODE16;
3268
3269 prefix = 0;
3270 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3271 {
29b0f896
AM		 3272 prefix = 1;
3273 i.prefixes -= 1;
3274 code16 ^= CODE16;
252b5132 3275 }
29b0f896
AM		 3276 /* Pentium4 branch hints. */
3277 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3278 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3279 {
29b0f896
AM		 3280 prefix++;
3281 i.prefixes--;
3282 }
3283 if (i.prefix[REX_PREFIX] != 0)
3284 {
3285 prefix++;
3286 i.prefixes--;
2f66722d
AM		 3287 }
3288
29b0f896
AM		 3289 if (i.prefixes != 0 && !intel_syntax)
3290 as_warn (_("skipping prefixes on this instruction"));
3291
3292 /* It's always a symbol; End frag & setup for relax.
3293 Make sure there is enough room in this frag for the largest
3294 instruction we may generate in md_convert_frag. This is 2
3295 bytes for the opcode and room for the prefix and largest
3296 displacement. */
3297 frag_grow (prefix + 2 + 4);
3298 /* Prefix and 1 opcode byte go in fr_fix. */
3299 p = frag_more (prefix + 1);
3300 if (i.prefix[DATA_PREFIX] != 0)
3301 *p++ = DATA_PREFIX_OPCODE;
3302 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3303 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3304 *p++ = i.prefix[SEG_PREFIX];
3305 if (i.prefix[REX_PREFIX] != 0)
3306 *p++ = i.prefix[REX_PREFIX];
3307 *p = i.tm.base_opcode;
3308
3309 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3310 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3311 else if ((cpu_arch_flags & Cpu386) != 0)
3312 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3313 else
3314 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3315 subtype |= code16;
3e73aa7c 3316
29b0f896
AM		 3317 sym = i.op[0].disps->X_add_symbol;
3318 off = i.op[0].disps->X_add_number;
3e73aa7c 3319
29b0f896
AM		 3320 if (i.op[0].disps->X_op != O_constant
3321 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3322 {
29b0f896
AM		 3323 /* Handle complex expressions. */
3324 sym = make_expr_symbol (i.op[0].disps);
3325 off = 0;
3326 }
3e73aa7c 3327
29b0f896
AM		 3328 /* 1 possible extra opcode + 4 byte displacement go in var part.
3329 Pass reloc in fr_var. */
3330 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3331}
3e73aa7c 3332
29b0f896
AM		 3333static void
3334output_jump ()
3335{
3336 char *p;
3337 int size;
3e02c1cc 3338 fixS *fixP;
29b0f896
AM		 3339
3340 if (i.tm.opcode_modifier & JumpByte)
3341 {
3342 /* This is a loop or jecxz type instruction. */
3343 size = 1;
3344 if (i.prefix[ADDR_PREFIX] != 0)
3345 {
3346 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3347 i.prefixes -= 1;
3348 }
3349 /* Pentium4 branch hints. */
3350 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3351 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3352 {
3353 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3354 i.prefixes--;
3e73aa7c
JH		 3355 }
3356 }
29b0f896
AM		 3357 else
3358 {
3359 int code16;
3e73aa7c 3360
29b0f896
AM		 3361 code16 = 0;
3362 if (flag_code == CODE_16BIT)
3363 code16 = CODE16;
3e73aa7c 3364
29b0f896
AM		 3365 if (i.prefix[DATA_PREFIX] != 0)
3366 {
3367 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3368 i.prefixes -= 1;
3369 code16 ^= CODE16;
3370 }
252b5132 3371
29b0f896
AM		 3372 size = 4;
3373 if (code16)
3374 size = 2;
3375 }
9fcc94b6 3376
29b0f896
AM		 3377 if (i.prefix[REX_PREFIX] != 0)
3378 {
3379 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3380 i.prefixes -= 1;
3381 }
252b5132 3382
29b0f896
AM		 3383 if (i.prefixes != 0 && !intel_syntax)
3384 as_warn (_("skipping prefixes on this instruction"));
e0890092 3385
29b0f896
AM		 3386 p = frag_more (1 + size);
3387 *p++ = i.tm.base_opcode;
e0890092 3388
3e02c1cc
AM		 3389 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3390 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3391
3392 /* All jumps handled here are signed, but don't use a signed limit
3393 check for 32 and 16 bit jumps as we want to allow wrap around at
3394 4G and 64k respectively. */
3395 if (size == 1)
3396 fixP->fx_signed = 1;
29b0f896 3397}
e0890092 3398
29b0f896
AM		 3399static void
3400output_interseg_jump ()
3401{
3402 char *p;
3403 int size;
3404 int prefix;
3405 int code16;
252b5132 3406
29b0f896
AM		 3407 code16 = 0;
3408 if (flag_code == CODE_16BIT)
3409 code16 = CODE16;
a217f122 3410
29b0f896
AM		 3411 prefix = 0;
3412 if (i.prefix[DATA_PREFIX] != 0)
3413 {
3414 prefix = 1;
3415 i.prefixes -= 1;
3416 code16 ^= CODE16;
3417 }
3418 if (i.prefix[REX_PREFIX] != 0)
3419 {
3420 prefix++;
3421 i.prefixes -= 1;
3422 }
252b5132 3423
29b0f896
AM		 3424 size = 4;
3425 if (code16)
3426 size = 2;
252b5132 3427
29b0f896
AM		 3428 if (i.prefixes != 0 && !intel_syntax)
3429 as_warn (_("skipping prefixes on this instruction"));
252b5132 3430
29b0f896
AM		 3431 /* 1 opcode; 2 segment; offset */
3432 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3433
29b0f896
AM		 3434 if (i.prefix[DATA_PREFIX] != 0)
3435 *p++ = DATA_PREFIX_OPCODE;
252b5132 3436
29b0f896
AM		 3437 if (i.prefix[REX_PREFIX] != 0)
3438 *p++ = i.prefix[REX_PREFIX];
252b5132 3439
29b0f896
AM		 3440 *p++ = i.tm.base_opcode;
3441 if (i.op[1].imms->X_op == O_constant)
3442 {
3443 offsetT n = i.op[1].imms->X_add_number;
252b5132 3444
29b0f896
AM		 3445 if (size == 2
3446 && !fits_in_unsigned_word (n)
3447 && !fits_in_signed_word (n))
3448 {
3449 as_bad (_("16-bit jump out of range"));
3450 return;
3451 }
3452 md_number_to_chars (p, n, size);
3453 }
3454 else
3455 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3456 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3457 if (i.op[0].imms->X_op != O_constant)
3458 as_bad (_("can't handle non absolute segment in `%s'"),
3459 i.tm.name);
3460 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3461}
a217f122 3462
29b0f896
AM		 3463static void
3464output_insn ()
3465{
2bbd9c25
JJ		 3466 fragS *insn_start_frag;
3467 offsetT insn_start_off;
3468
29b0f896
AM		 3469 /* Tie dwarf2 debug info to the address at the start of the insn.
3470 We can't do this after the insn has been output as the current
3471 frag may have been closed off. eg. by frag_var. */
3472 dwarf2_emit_insn (0);
3473
2bbd9c25
JJ		 3474 insn_start_frag = frag_now;
3475 insn_start_off = frag_now_fix ();
3476
29b0f896
AM		 3477 /* Output jumps. */
3478 if (i.tm.opcode_modifier & Jump)
3479 output_branch ();
3480 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3481 output_jump ();
3482 else if (i.tm.opcode_modifier & JumpInterSegment)
3483 output_interseg_jump ();
3484 else
3485 {
3486 /* Output normal instructions here. */
3487 char *p;
3488 unsigned char *q;
331d2d0d 3489 unsigned int prefix;
252b5132 3490
331d2d0d
L		 3491 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3492 Instructions have 3 bytes. We may use one more higher byte
3493 to specify a prefix the instruction requires. */
3494 if ((i.tm.cpu_flags & CpuMNI) != 0)
bc4bd9ab 3495 {
331d2d0d
L		 3496 if (i.tm.base_opcode & 0xff000000)
3497 {
3498 prefix = (i.tm.base_opcode >> 24) & 0xff;
3499 goto check_prefix;
3500 }
3501 }
3502 else if ((i.tm.base_opcode & 0xff0000) != 0)
3503 {
3504 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3505 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3506 {
64e74474 3507 check_prefix:
bc4bd9ab
MK		 3508 if (prefix != REPE_PREFIX_OPCODE
3509 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3510 add_prefix (prefix);
3511 }
3512 else
331d2d0d 3513 add_prefix (prefix);
0f10071e 3514 }
252b5132 3515
29b0f896
AM		 3516 /* The prefix bytes. */
3517 for (q = i.prefix;
3518 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3519 q++)
3520 {
3521 if (*q)
3522 {
3523 p = frag_more (1);
3524 md_number_to_chars (p, (valueT) *q, 1);
3525 }
3526 }
252b5132 3527
29b0f896
AM		 3528 /* Now the opcode; be careful about word order here! */
3529 if (fits_in_unsigned_byte (i.tm.base_opcode))
3530 {
3531 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3532 }
3533 else
3534 {
331d2d0d
L		 3535 if ((i.tm.cpu_flags & CpuMNI) != 0)
3536 {
3537 p = frag_more (3);
3538 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3539 }
3540 else
3541 p = frag_more (2);
0f10071e 3542
29b0f896
AM		 3543 /* Put out high byte first: can't use md_number_to_chars! */
3544 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3545 *p = i.tm.base_opcode & 0xff;
3546 }
3e73aa7c 3547
29b0f896
AM		 3548 /* Now the modrm byte and sib byte (if present). */
3549 if (i.tm.opcode_modifier & Modrm)
3550 {
3551 p = frag_more (1);
3552 md_number_to_chars (p,
3553 (valueT) (i.rm.regmem << 0
3554 | i.rm.reg << 3
3555 | i.rm.mode << 6),
3556 1);
3557 /* If i.rm.regmem == ESP (4)
3558 && i.rm.mode != (Register mode)
3559 && not 16 bit
3560 ==> need second modrm byte. */
3561 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3562 && i.rm.mode != 3
3563 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3564 {
3565 p = frag_more (1);
3566 md_number_to_chars (p,
3567 (valueT) (i.sib.base << 0
3568 | i.sib.index << 3
3569 | i.sib.scale << 6),
3570 1);
3571 }
3572 }
3e73aa7c 3573
29b0f896 3574 if (i.disp_operands)
2bbd9c25 3575 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3576
29b0f896 3577 if (i.imm_operands)
2bbd9c25 3578 output_imm (insn_start_frag, insn_start_off);
29b0f896 3579 }
252b5132 3580
29b0f896
AM		 3581#ifdef DEBUG386
3582 if (flag_debug)
3583 {
7b81dfbb 3584 pi ("" /*line*/, &i);
29b0f896
AM		 3585 }
3586#endif /* DEBUG386 */
3587}
252b5132 3588
29b0f896 3589static void
64e74474 3590output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3591{
3592 char *p;
3593 unsigned int n;
252b5132 3594
29b0f896
AM		 3595 for (n = 0; n < i.operands; n++)
3596 {
3597 if (i.types[n] & Disp)
3598 {
3599 if (i.op[n].disps->X_op == O_constant)
3600 {
3601 int size;
3602 offsetT val;
252b5132 3603
29b0f896
AM		 3604 size = 4;
3605 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3606 {
3607 size = 2;
3608 if (i.types[n] & Disp8)
3609 size = 1;
3610 if (i.types[n] & Disp64)
3611 size = 8;
3612 }
3613 val = offset_in_range (i.op[n].disps->X_add_number,
3614 size);
3615 p = frag_more (size);
3616 md_number_to_chars (p, val, size);
3617 }
3618 else
3619 {
f86103b7 3620 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3621 int size = 4;
3622 int sign = 0;
3623 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3624
3625 /* The PC relative address is computed relative
3626 to the instruction boundary, so in case immediate
3627 fields follows, we need to adjust the value. */
3628 if (pcrel && i.imm_operands)
3629 {
3630 int imm_size = 4;
3631 unsigned int n1;
252b5132 3632
29b0f896
AM		 3633 for (n1 = 0; n1 < i.operands; n1++)
3634 if (i.types[n1] & Imm)
252b5132 3635 {
29b0f896 3636 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3637 {
29b0f896
AM		 3638 imm_size = 2;
3639 if (i.types[n1] & (Imm8 | Imm8S))
3640 imm_size = 1;
3641 if (i.types[n1] & Imm64)
3642 imm_size = 8;
252b5132 3643 }
29b0f896 3644 break;
252b5132 3645 }
29b0f896
AM		 3646 /* We should find the immediate. */
3647 if (n1 == i.operands)
3648 abort ();
3649 i.op[n].disps->X_add_number -= imm_size;
3650 }
520dc8e8 3651
29b0f896
AM		 3652 if (i.types[n] & Disp32S)
3653 sign = 1;
3e73aa7c 3654
29b0f896
AM		 3655 if (i.types[n] & (Disp16 | Disp64))
3656 {
3657 size = 2;
3658 if (i.types[n] & Disp64)
3659 size = 8;
3660 }
520dc8e8 3661
29b0f896 3662 p = frag_more (size);
2bbd9c25 3663 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3664 if (GOT_symbol
2bbd9c25 3665 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 3666 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 3667 || reloc_type == BFD_RELOC_X86_64_32S
3668 || (reloc_type == BFD_RELOC_64
3669 && object_64bit))
d6ab8113
JB		 3670 && (i.op[n].disps->X_op == O_symbol
3671 || (i.op[n].disps->X_op == O_add
3672 && ((symbol_get_value_expression
3673 (i.op[n].disps->X_op_symbol)->X_op)
3674 == O_subtract))))
3675 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3676 {
3677 offsetT add;
3678
3679 if (insn_start_frag == frag_now)
3680 add = (p - frag_now->fr_literal) - insn_start_off;
3681 else
3682 {
3683 fragS *fr;
3684
3685 add = insn_start_frag->fr_fix - insn_start_off;
3686 for (fr = insn_start_frag->fr_next;
3687 fr && fr != frag_now; fr = fr->fr_next)
3688 add += fr->fr_fix;
3689 add += p - frag_now->fr_literal;
3690 }
3691
4fa24527 3692 if (!object_64bit)
7b81dfbb
AJ		 3693 {
3694 reloc_type = BFD_RELOC_386_GOTPC;
3695 i.op[n].imms->X_add_number += add;
3696 }
3697 else if (reloc_type == BFD_RELOC_64)
3698 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 3699 else
7b81dfbb
AJ		 3700 /* Don't do the adjustment for x86-64, as there
3701 the pcrel addressing is relative to the _next_
3702 insn, and that is taken care of in other code. */
d6ab8113 3703 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3704 }
062cd5e7 3705 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3706 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3707 }
3708 }
3709 }
3710}
252b5132 3711
29b0f896 3712static void
64e74474 3713output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3714{
3715 char *p;
3716 unsigned int n;
252b5132 3717
29b0f896
AM		 3718 for (n = 0; n < i.operands; n++)
3719 {
3720 if (i.types[n] & Imm)
3721 {
3722 if (i.op[n].imms->X_op == O_constant)
3723 {
3724 int size;
3725 offsetT val;
b4cac588 3726
29b0f896
AM		 3727 size = 4;
3728 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3729 {
3730 size = 2;
3731 if (i.types[n] & (Imm8 | Imm8S))
3732 size = 1;
3733 else if (i.types[n] & Imm64)
3734 size = 8;
3735 }
3736 val = offset_in_range (i.op[n].imms->X_add_number,
3737 size);
3738 p = frag_more (size);
3739 md_number_to_chars (p, val, size);
3740 }
3741 else
3742 {
3743 /* Not absolute_section.
3744 Need a 32-bit fixup (don't support 8bit
3745 non-absolute imms). Try to support other
3746 sizes ... */
f86103b7 3747 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3748 int size = 4;
3749 int sign = 0;
3750
3751 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3752 && (i.suffix == QWORD_MNEM_SUFFIX
3753 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3754 sign = 1;
3755 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3756 {
3757 size = 2;
3758 if (i.types[n] & (Imm8 | Imm8S))
3759 size = 1;
3760 if (i.types[n] & Imm64)
3761 size = 8;
3762 }
520dc8e8 3763
29b0f896
AM		 3764 p = frag_more (size);
3765 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3766
2bbd9c25
JJ		 3767 /* This is tough to explain. We end up with this one if we
3768 * have operands that look like
3769 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3770 * obtain the absolute address of the GOT, and it is strongly
3771 * preferable from a performance point of view to avoid using
3772 * a runtime relocation for this. The actual sequence of
3773 * instructions often look something like:
3774 *
3775 * call .L66
3776 * .L66:
3777 * popl %ebx
3778 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3779 *
3780 * The call and pop essentially return the absolute address
3781 * of the label .L66 and store it in %ebx. The linker itself
3782 * will ultimately change the first operand of the addl so
3783 * that %ebx points to the GOT, but to keep things simple, the
3784 * .o file must have this operand set so that it generates not
3785 * the absolute address of .L66, but the absolute address of
3786 * itself. This allows the linker itself simply treat a GOTPC
3787 * relocation as asking for a pcrel offset to the GOT to be
3788 * added in, and the addend of the relocation is stored in the
3789 * operand field for the instruction itself.
3790 *
3791 * Our job here is to fix the operand so that it would add
3792 * the correct offset so that %ebx would point to itself. The
3793 * thing that is tricky is that .-.L66 will point to the
3794 * beginning of the instruction, so we need to further modify
3795 * the operand so that it will point to itself. There are
3796 * other cases where you have something like:
3797 *
3798 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3799 *
3800 * and here no correction would be required. Internally in
3801 * the assembler we treat operands of this form as not being
3802 * pcrel since the '.' is explicitly mentioned, and I wonder
3803 * whether it would simplify matters to do it this way. Who
3804 * knows. In earlier versions of the PIC patches, the
3805 * pcrel_adjust field was used to store the correction, but
3806 * since the expression is not pcrel, I felt it would be
3807 * confusing to do it this way. */
3808
d6ab8113 3809 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 3810 || reloc_type == BFD_RELOC_X86_64_32S
3811 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 3812 && GOT_symbol
3813 && GOT_symbol == i.op[n].imms->X_add_symbol
3814 && (i.op[n].imms->X_op == O_symbol
3815 || (i.op[n].imms->X_op == O_add
3816 && ((symbol_get_value_expression
3817 (i.op[n].imms->X_op_symbol)->X_op)
3818 == O_subtract))))
3819 {
2bbd9c25
JJ		 3820 offsetT add;
3821
3822 if (insn_start_frag == frag_now)
3823 add = (p - frag_now->fr_literal) - insn_start_off;
3824 else
3825 {
3826 fragS *fr;
3827
3828 add = insn_start_frag->fr_fix - insn_start_off;
3829 for (fr = insn_start_frag->fr_next;
3830 fr && fr != frag_now; fr = fr->fr_next)
3831 add += fr->fr_fix;
3832 add += p - frag_now->fr_literal;
3833 }
3834
4fa24527 3835 if (!object_64bit)
d6ab8113 3836 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 3837 else if (size == 4)
d6ab8113 3838 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 3839 else if (size == 8)
3840 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 3841 i.op[n].imms->X_add_number += add;
29b0f896 3842 }
29b0f896
AM		 3843 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3844 i.op[n].imms, 0, reloc_type);
3845 }
3846 }
3847 }
252b5132
RH		 3848}
3849\f
d182319b
JB		 3850/* x86_cons_fix_new is called via the expression parsing code when a
3851 reloc is needed. We use this hook to get the correct .got reloc. */
3852static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3853static int cons_sign = -1;
3854
3855void
3856x86_cons_fix_new (fragS *frag,
64e74474
AM		 3857 unsigned int off,
3858 unsigned int len,
3859 expressionS *exp)
d182319b
JB		 3860{
3861 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3862
3863 got_reloc = NO_RELOC;
3864
3865#ifdef TE_PE
3866 if (exp->X_op == O_secrel)
3867 {
3868 exp->X_op = O_symbol;
3869 r = BFD_RELOC_32_SECREL;
3870 }
3871#endif
3872
3873 fix_new_exp (frag, off, len, exp, 0, r);
3874}
3875
718ddfc0
JB		 3876#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3877# define lex_got(reloc, adjust, types) NULL
3878#else
f3c180ae
AM		 3879/* Parse operands of the form
3880 <symbol>@GOTOFF+<nnn>
3881 and similar .plt or .got references.
3882
3883 If we find one, set up the correct relocation in RELOC and copy the
3884 input string, minus the `@GOTOFF' into a malloc'd buffer for
3885 parsing by the calling routine. Return this buffer, and if ADJUST
3886 is non-null set it to the length of the string we removed from the
3887 input line. Otherwise return NULL. */
3888static char *
3956db08 3889lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 3890 int *adjust,
3891 unsigned int *types)
f3c180ae 3892{
7b81dfbb
AJ		 3893 /* Some of the relocations depend on the size of what field is to
3894 be relocated. But in our callers i386_immediate and i386_displacement
3895 we don't yet know the operand size (this will be set by insn
3896 matching). Hence we record the word32 relocation here,
3897 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 3898 static const struct {
3899 const char *str;
4fa24527 3900 const enum bfd_reloc_code_real rel[2];
3956db08 3901 const unsigned int types64;
f3c180ae 3902 } gotrel[] = {
7b81dfbb 3903 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 3904 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 3905 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 3906 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3907 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3908 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3909 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3910 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3911 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3912 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3913 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3914 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3915 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3916 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 3917 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 3918 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
3919 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3920 };
3921 char *cp;
3922 unsigned int j;
3923
718ddfc0
JB		 3924 if (!IS_ELF)
3925 return NULL;
3926
f3c180ae
AM		 3927 for (cp = input_line_pointer; *cp != '@'; cp++)
3928 if (is_end_of_line[(unsigned char) *cp])
3929 return NULL;
3930
3931 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3932 {
3933 int len;
3934
3935 len = strlen (gotrel[j].str);
28f81592 3936 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 3937 {
4fa24527 3938 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 3939 {
28f81592
AM		 3940 int first, second;
3941 char *tmpbuf, *past_reloc;
f3c180ae 3942
4fa24527 3943 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 3944 if (adjust)
3945 *adjust = len;
f3c180ae 3946
3956db08
JB		 3947 if (types)
3948 {
3949 if (flag_code != CODE_64BIT)
3950 *types = Imm32|Disp32;
3951 else
3952 *types = gotrel[j].types64;
3953 }
3954
f3c180ae
AM		 3955 if (GOT_symbol == NULL)
3956 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3957
3958 /* Replace the relocation token with ' ', so that
3959 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3960
3961 /* The length of the first part of our input line. */
f3c180ae 3962 first = cp - input_line_pointer;
28f81592
AM		 3963
3964 /* The second part goes from after the reloc token until
3965 (and including) an end_of_line char. Don't use strlen
3966 here as the end_of_line char may not be a NUL. */
3967 past_reloc = cp + 1 + len;
3968 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3969 ;
3970 second = cp - past_reloc;
3971
3972 /* Allocate and copy string. The trailing NUL shouldn't
3973 be necessary, but be safe. */
3974 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3975 memcpy (tmpbuf, input_line_pointer, first);
3976 tmpbuf[first] = ' ';
28f81592
AM		 3977 memcpy (tmpbuf + first + 1, past_reloc, second);
3978 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3979 return tmpbuf;
3980 }
3981
4fa24527
JB		 3982 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3983 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 3984 return NULL;
3985 }
3986 }
3987
3988 /* Might be a symbol version string. Don't as_bad here. */
3989 return NULL;
3990}
3991
f3c180ae
AM		 3992void
3993x86_cons (exp, size)
3994 expressionS *exp;
3995 int size;
3996{
4fa24527 3997 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 3998 {
3999 /* Handle @GOTOFF and the like in an expression. */
4000 char *save;
4001 char *gotfree_input_line;
4002 int adjust;
4003
4004 save = input_line_pointer;
3956db08 4005 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4006 if (gotfree_input_line)
4007 input_line_pointer = gotfree_input_line;
4008
4009 expression (exp);
4010
4011 if (gotfree_input_line)
4012 {
4013 /* expression () has merrily parsed up to the end of line,
4014 or a comma - in the wrong buffer. Transfer how far
4015 input_line_pointer has moved to the right buffer. */
4016 input_line_pointer = (save
4017 + (input_line_pointer - gotfree_input_line)
4018 + adjust);
4019 free (gotfree_input_line);
4020 }
4021 }
4022 else
4023 expression (exp);
4024}
4025#endif
4026
d182319b 4027static void signed_cons (int size)
6482c264 4028{
d182319b
JB		 4029 if (flag_code == CODE_64BIT)
4030 cons_sign = 1;
4031 cons (size);
4032 cons_sign = -1;
6482c264
NC		 4033}
4034
d182319b 4035#ifdef TE_PE
6482c264
NC		 4036static void
4037pe_directive_secrel (dummy)
4038 int dummy ATTRIBUTE_UNUSED;
4039{
4040 expressionS exp;
4041
4042 do
4043 {
4044 expression (&exp);
4045 if (exp.X_op == O_symbol)
4046 exp.X_op = O_secrel;
4047
4048 emit_expr (&exp, 4);
4049 }
4050 while (*input_line_pointer++ == ',');
4051
4052 input_line_pointer--;
4053 demand_empty_rest_of_line ();
4054}
6482c264
NC		 4055#endif
4056
252b5132
RH		 4057static int i386_immediate PARAMS ((char *));
4058
4059static int
4060i386_immediate (imm_start)
4061 char *imm_start;
4062{
4063 char *save_input_line_pointer;
f3c180ae 4064 char *gotfree_input_line;
252b5132 4065 segT exp_seg = 0;
47926f60 4066 expressionS *exp;
3956db08 4067 unsigned int types = ~0U;
252b5132
RH		 4068
4069 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4070 {
d0b47220 4071 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4072 return 0;
4073 }
4074
4075 exp = &im_expressions[i.imm_operands++];
520dc8e8 4076 i.op[this_operand].imms = exp;
252b5132
RH		 4077
4078 if (is_space_char (*imm_start))
4079 ++imm_start;
4080
4081 save_input_line_pointer = input_line_pointer;
4082 input_line_pointer = imm_start;
4083
3956db08 4084 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4085 if (gotfree_input_line)
4086 input_line_pointer = gotfree_input_line;
252b5132
RH		 4087
4088 exp_seg = expression (exp);
4089
83183c0c 4090 SKIP_WHITESPACE ();
252b5132 4091 if (*input_line_pointer)
f3c180ae 4092 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4093
4094 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4095 if (gotfree_input_line)
4096 free (gotfree_input_line);
252b5132 4097
2daf4fd8 4098 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4099 {
47926f60 4100 /* Missing or bad expr becomes absolute 0. */
d0b47220 4101 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4102 imm_start);
252b5132
RH		 4103 exp->X_op = O_constant;
4104 exp->X_add_number = 0;
4105 exp->X_add_symbol = (symbolS *) 0;
4106 exp->X_op_symbol = (symbolS *) 0;
252b5132 4107 }
3e73aa7c 4108 else if (exp->X_op == O_constant)
252b5132 4109 {
47926f60 4110 /* Size it properly later. */
3e73aa7c
JH		 4111 i.types[this_operand] |= Imm64;
4112 /* If BFD64, sign extend val. */
4113 if (!use_rela_relocations)
4114 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4115 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4116 }
4c63da97 4117#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4118 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4119 && exp_seg != absolute_section
47926f60 4120 && exp_seg != text_section
24eab124
AM		 4121 && exp_seg != data_section
4122 && exp_seg != bss_section
4123 && exp_seg != undefined_section
f86103b7 4124 && !bfd_is_com_section (exp_seg))
252b5132 4125 {
d0b47220 4126 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4127 return 0;
4128 }
4129#endif
bb8f5920
L		 4130 else if (!intel_syntax && exp->X_op == O_register)
4131 {
4132 as_bad (_("illegal immediate register operand %s"), imm_start);
4133 return 0;
4134 }
252b5132
RH		 4135 else
4136 {
4137 /* This is an address. The size of the address will be
24eab124 4138 determined later, depending on destination register,
3e73aa7c
JH		 4139 suffix, or the default for the section. */
4140 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4141 i.types[this_operand] &= types;
252b5132
RH		 4142 }
4143
4144 return 1;
4145}
4146
551c1ca1 4147static char *i386_scale PARAMS ((char *));
252b5132 4148
551c1ca1 4149static char *
252b5132
RH		 4150i386_scale (scale)
4151 char *scale;
4152{
551c1ca1
AM		 4153 offsetT val;
4154 char *save = input_line_pointer;
252b5132 4155
551c1ca1
AM		 4156 input_line_pointer = scale;
4157 val = get_absolute_expression ();
4158
4159 switch (val)
252b5132 4160 {
551c1ca1 4161 case 1:
252b5132
RH		 4162 i.log2_scale_factor = 0;
4163 break;
551c1ca1 4164 case 2:
252b5132
RH		 4165 i.log2_scale_factor = 1;
4166 break;
551c1ca1 4167 case 4:
252b5132
RH		 4168 i.log2_scale_factor = 2;
4169 break;
551c1ca1 4170 case 8:
252b5132
RH		 4171 i.log2_scale_factor = 3;
4172 break;
4173 default:
a724f0f4
JB		 4174 {
4175 char sep = *input_line_pointer;
4176
4177 *input_line_pointer = '\0';
4178 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4179 scale);
4180 *input_line_pointer = sep;
4181 input_line_pointer = save;
4182 return NULL;
4183 }
252b5132 4184 }
29b0f896 4185 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4186 {
4187 as_warn (_("scale factor of %d without an index register"),
24eab124 4188 1 << i.log2_scale_factor);
252b5132
RH		 4189#if SCALE1_WHEN_NO_INDEX
4190 i.log2_scale_factor = 0;
4191#endif
4192 }
551c1ca1
AM		 4193 scale = input_line_pointer;
4194 input_line_pointer = save;
4195 return scale;
252b5132
RH		 4196}
4197
4198static int i386_displacement PARAMS ((char *, char *));
4199
4200static int
4201i386_displacement (disp_start, disp_end)
4202 char *disp_start;
4203 char *disp_end;
4204{
29b0f896 4205 expressionS *exp;
252b5132
RH		 4206 segT exp_seg = 0;
4207 char *save_input_line_pointer;
f3c180ae 4208 char *gotfree_input_line;
e05278af 4209 int bigdisp, override;
3956db08 4210 unsigned int types = Disp;
252b5132 4211
e05278af
JB		 4212 if ((i.types[this_operand] & JumpAbsolute)
4213 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4214 {
4215 bigdisp = Disp32;
4216 override = (i.prefix[ADDR_PREFIX] != 0);
4217 }
4218 else
4219 {
4220 /* For PC-relative branches, the width of the displacement
4221 is dependent upon data size, not address size. */
4222 bigdisp = 0;
4223 override = (i.prefix[DATA_PREFIX] != 0);
4224 }
3e73aa7c 4225 if (flag_code == CODE_64BIT)
7ecd2f8b 4226 {
e05278af 4227 if (!bigdisp)
64e74474
AM		 4228 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4229 ? Disp16
4230 : Disp32S | Disp32);
e05278af 4231 else if (!override)
3956db08 4232 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4233 }
e05278af
JB		 4234 else
4235 {
4236 if (!bigdisp)
4237 {
4238 if (!override)
4239 override = (i.suffix == (flag_code != CODE_16BIT
4240 ? WORD_MNEM_SUFFIX
4241 : LONG_MNEM_SUFFIX));
4242 bigdisp = Disp32;
4243 }
4244 if ((flag_code == CODE_16BIT) ^ override)
4245 bigdisp = Disp16;
4246 }
252b5132
RH		 4247 i.types[this_operand] |= bigdisp;
4248
4249 exp = &disp_expressions[i.disp_operands];
520dc8e8 4250 i.op[this_operand].disps = exp;
252b5132
RH		 4251 i.disp_operands++;
4252 save_input_line_pointer = input_line_pointer;
4253 input_line_pointer = disp_start;
4254 END_STRING_AND_SAVE (disp_end);
4255
4256#ifndef GCC_ASM_O_HACK
4257#define GCC_ASM_O_HACK 0
4258#endif
4259#if GCC_ASM_O_HACK
4260 END_STRING_AND_SAVE (disp_end + 1);
4261 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4262 && displacement_string_end[-1] == '+')
252b5132
RH		 4263 {
4264 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4265 constraint within gcc asm statements.
4266 For instance:
4267
4268 #define _set_tssldt_desc(n,addr,limit,type) \
4269 __asm__ __volatile__ ( \
4270 "movw %w2,%0\n\t" \
4271 "movw %w1,2+%0\n\t" \
4272 "rorl $16,%1\n\t" \
4273 "movb %b1,4+%0\n\t" \
4274 "movb %4,5+%0\n\t" \
4275 "movb $0,6+%0\n\t" \
4276 "movb %h1,7+%0\n\t" \
4277 "rorl $16,%1" \
4278 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4279
4280 This works great except that the output assembler ends
4281 up looking a bit weird if it turns out that there is
4282 no offset. You end up producing code that looks like:
4283
4284 #APP
4285 movw $235,(%eax)
4286 movw %dx,2+(%eax)
4287 rorl $16,%edx
4288 movb %dl,4+(%eax)
4289 movb $137,5+(%eax)
4290 movb $0,6+(%eax)
4291 movb %dh,7+(%eax)
4292 rorl $16,%edx
4293 #NO_APP
4294
47926f60 4295 So here we provide the missing zero. */
24eab124
AM		 4296
4297 *displacement_string_end = '0';
252b5132
RH		 4298 }
4299#endif
3956db08 4300 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4301 if (gotfree_input_line)
4302 input_line_pointer = gotfree_input_line;
252b5132 4303
24eab124 4304 exp_seg = expression (exp);
252b5132 4305
636c26b0
AM		 4306 SKIP_WHITESPACE ();
4307 if (*input_line_pointer)
4308 as_bad (_("junk `%s' after expression"), input_line_pointer);
4309#if GCC_ASM_O_HACK
4310 RESTORE_END_STRING (disp_end + 1);
4311#endif
4312 RESTORE_END_STRING (disp_end);
4313 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4314 if (gotfree_input_line)
4315 free (gotfree_input_line);
636c26b0 4316
24eab124
AM		 4317 /* We do this to make sure that the section symbol is in
4318 the symbol table. We will ultimately change the relocation
47926f60 4319 to be relative to the beginning of the section. */
1ae12ab7 4320 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4321 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4322 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4323 {
636c26b0
AM		 4324 if (exp->X_op != O_symbol)
4325 {
4326 as_bad (_("bad expression used with @%s"),
4327 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4328 ? "GOTPCREL"
4329 : "GOTOFF"));
4330 return 0;
4331 }
4332
e5cb08ac 4333 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4334 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4335 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4336 exp->X_op = O_subtract;
4337 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4338 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4339 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4340 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4341 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4342 else
29b0f896 4343 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4344 }
252b5132 4345
2daf4fd8
AM		 4346 if (exp->X_op == O_absent || exp->X_op == O_big)
4347 {
47926f60 4348 /* Missing or bad expr becomes absolute 0. */
d0b47220 4349 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4350 disp_start);
4351 exp->X_op = O_constant;
4352 exp->X_add_number = 0;
4353 exp->X_add_symbol = (symbolS *) 0;
4354 exp->X_op_symbol = (symbolS *) 0;
4355 }
4356
4c63da97 4357#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4358 if (exp->X_op != O_constant
45288df1 4359 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4360 && exp_seg != absolute_section
45288df1
AM		 4361 && exp_seg != text_section
4362 && exp_seg != data_section
4363 && exp_seg != bss_section
31312f95 4364 && exp_seg != undefined_section
f86103b7 4365 && !bfd_is_com_section (exp_seg))
24eab124 4366 {
d0b47220 4367 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4368 return 0;
4369 }
252b5132 4370#endif
3956db08
JB		 4371
4372 if (!(i.types[this_operand] & ~Disp))
4373 i.types[this_operand] &= types;
4374
252b5132
RH		 4375 return 1;
4376}
4377
e5cb08ac 4378static int i386_index_check PARAMS ((const char *));
252b5132 4379
eecb386c 4380/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4381 Return 1 on success, 0 on a failure. */
4382
252b5132 4383static int
eecb386c
AM		 4384i386_index_check (operand_string)
4385 const char *operand_string;
252b5132 4386{
3e73aa7c 4387 int ok;
24eab124 4388#if INFER_ADDR_PREFIX
eecb386c
AM		 4389 int fudged = 0;
4390
24eab124
AM		 4391 tryprefix:
4392#endif
3e73aa7c 4393 ok = 1;
30123838
JB		 4394 if ((current_templates->start->cpu_flags & CpuSVME)
4395 && current_templates->end[-1].operand_types[0] == AnyMem)
4396 {
4397 /* Memory operands of SVME insns are special in that they only allow
4398 rAX as their memory address and ignore any segment override. */
4399 unsigned RegXX;
4400
4401 /* SKINIT is even more restrictive: it always requires EAX. */
4402 if (strcmp (current_templates->start->name, "skinit") == 0)
4403 RegXX = Reg32;
4404 else if (flag_code == CODE_64BIT)
4405 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4406 else
64e74474
AM		 4407 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4408 ? Reg16
4409 : Reg32);
30123838
JB		 4410 if (!i.base_reg
4411 || !(i.base_reg->reg_type & Acc)
4412 || !(i.base_reg->reg_type & RegXX)
4413 || i.index_reg
4414 || (i.types[0] & Disp))
4415 ok = 0;
4416 }
4417 else if (flag_code == CODE_64BIT)
64e74474
AM		 4418 {
4419 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4420
4421 if ((i.base_reg
4422 && ((i.base_reg->reg_type & RegXX) == 0)
4423 && (i.base_reg->reg_type != BaseIndex
4424 || i.index_reg))
4425 || (i.index_reg
4426 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4427 != (RegXX | BaseIndex))))
4428 ok = 0;
3e73aa7c
JH		 4429 }
4430 else
4431 {
4432 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4433 {
4434 /* 16bit checks. */
4435 if ((i.base_reg
29b0f896
AM		 4436 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4437 != (Reg16 | BaseIndex)))
3e73aa7c 4438 || (i.index_reg
29b0f896
AM		 4439 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4440 != (Reg16 | BaseIndex))
4441 || !(i.base_reg
4442 && i.base_reg->reg_num < 6
4443 && i.index_reg->reg_num >= 6
4444 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4445 ok = 0;
4446 }
4447 else
e5cb08ac 4448 {
3e73aa7c
JH		 4449 /* 32bit checks. */
4450 if ((i.base_reg
4451 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4452 || (i.index_reg
29b0f896
AM		 4453 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4454 != (Reg32 | BaseIndex))))
e5cb08ac 4455 ok = 0;
3e73aa7c
JH		 4456 }
4457 }
4458 if (!ok)
24eab124
AM		 4459 {
4460#if INFER_ADDR_PREFIX
20f0a1fc 4461 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4462 {
4463 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4464 i.prefixes += 1;
b23bac36
AM		 4465 /* Change the size of any displacement too. At most one of
4466 Disp16 or Disp32 is set.
4467 FIXME. There doesn't seem to be any real need for separate
4468 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4469 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4470 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4471 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4472 fudged = 1;
24eab124
AM		 4473 goto tryprefix;
4474 }
eecb386c
AM		 4475 if (fudged)
4476 as_bad (_("`%s' is not a valid base/index expression"),
4477 operand_string);
4478 else
c388dee8 4479#endif
eecb386c
AM		 4480 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4481 operand_string,
3e73aa7c 4482 flag_code_names[flag_code]);
24eab124 4483 }
20f0a1fc 4484 return ok;
24eab124 4485}
252b5132 4486
252b5132 4487/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4488 on error. */
252b5132 4489
252b5132
RH		 4490static int
4491i386_operand (operand_string)
4492 char *operand_string;
4493{
af6bdddf
AM		 4494 const reg_entry *r;
4495 char *end_op;
24eab124 4496 char *op_string = operand_string;
252b5132 4497
24eab124 4498 if (is_space_char (*op_string))
252b5132
RH		 4499 ++op_string;
4500
24eab124 4501 /* We check for an absolute prefix (differentiating,
47926f60 4502 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4503 if (*op_string == ABSOLUTE_PREFIX)
4504 {
4505 ++op_string;
4506 if (is_space_char (*op_string))
4507 ++op_string;
4508 i.types[this_operand] |= JumpAbsolute;
4509 }
252b5132 4510
47926f60 4511 /* Check if operand is a register. */
4d1bb795 4512 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4513 {
24eab124
AM		 4514 /* Check for a segment override by searching for ':' after a
4515 segment register. */
4516 op_string = end_op;
4517 if (is_space_char (*op_string))
4518 ++op_string;
4519 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4520 {
4521 switch (r->reg_num)
4522 {
4523 case 0:
4524 i.seg[i.mem_operands] = &es;
4525 break;
4526 case 1:
4527 i.seg[i.mem_operands] = &cs;
4528 break;
4529 case 2:
4530 i.seg[i.mem_operands] = &ss;
4531 break;
4532 case 3:
4533 i.seg[i.mem_operands] = &ds;
4534 break;
4535 case 4:
4536 i.seg[i.mem_operands] = &fs;
4537 break;
4538 case 5:
4539 i.seg[i.mem_operands] = &gs;
4540 break;
4541 }
252b5132 4542
24eab124 4543 /* Skip the ':' and whitespace. */
252b5132
RH		 4544 ++op_string;
4545 if (is_space_char (*op_string))
24eab124 4546 ++op_string;
252b5132 4547
24eab124
AM		 4548 if (!is_digit_char (*op_string)
4549 && !is_identifier_char (*op_string)
4550 && *op_string != '('
4551 && *op_string != ABSOLUTE_PREFIX)
4552 {
4553 as_bad (_("bad memory operand `%s'"), op_string);
4554 return 0;
4555 }
47926f60 4556 /* Handle case of %es:*foo. */
24eab124
AM		 4557 if (*op_string == ABSOLUTE_PREFIX)
4558 {
4559 ++op_string;
4560 if (is_space_char (*op_string))
4561 ++op_string;
4562 i.types[this_operand] |= JumpAbsolute;
4563 }
4564 goto do_memory_reference;
4565 }
4566 if (*op_string)
4567 {
d0b47220 4568 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4569 return 0;
4570 }
4571 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4572 i.op[this_operand].regs = r;
24eab124
AM		 4573 i.reg_operands++;
4574 }
af6bdddf
AM		 4575 else if (*op_string == REGISTER_PREFIX)
4576 {
4577 as_bad (_("bad register name `%s'"), op_string);
4578 return 0;
4579 }
24eab124 4580 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4581 {
24eab124
AM		 4582 ++op_string;
4583 if (i.types[this_operand] & JumpAbsolute)
4584 {
d0b47220 4585 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4586 return 0;
4587 }
4588 if (!i386_immediate (op_string))
4589 return 0;
4590 }
4591 else if (is_digit_char (*op_string)
4592 || is_identifier_char (*op_string)
e5cb08ac 4593 || *op_string == '(')
24eab124 4594 {
47926f60 4595 /* This is a memory reference of some sort. */
af6bdddf 4596 char *base_string;
252b5132 4597
47926f60 4598 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4599 char *displacement_string_start;
4600 char *displacement_string_end;
252b5132 4601
24eab124 4602 do_memory_reference:
24eab124
AM		 4603 if ((i.mem_operands == 1
4604 && (current_templates->start->opcode_modifier & IsString) == 0)
4605 || i.mem_operands == 2)
4606 {
4607 as_bad (_("too many memory references for `%s'"),
4608 current_templates->start->name);
4609 return 0;
4610 }
252b5132 4611
24eab124
AM		 4612 /* Check for base index form. We detect the base index form by
4613 looking for an ')' at the end of the operand, searching
4614 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4615 after the '('. */
af6bdddf 4616 base_string = op_string + strlen (op_string);
c3332e24 4617
af6bdddf
AM		 4618 --base_string;
4619 if (is_space_char (*base_string))
4620 --base_string;
252b5132 4621
47926f60 4622 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4623 displacement_string_start = op_string;
4624 displacement_string_end = base_string + 1;
252b5132 4625
24eab124
AM		 4626 if (*base_string == ')')
4627 {
af6bdddf 4628 char *temp_string;
24eab124
AM		 4629 unsigned int parens_balanced = 1;
4630 /* We've already checked that the number of left & right ()'s are
47926f60 4631 equal, so this loop will not be infinite. */
24eab124
AM		 4632 do
4633 {
4634 base_string--;
4635 if (*base_string == ')')
4636 parens_balanced++;
4637 if (*base_string == '(')
4638 parens_balanced--;
4639 }
4640 while (parens_balanced);
c3332e24 4641
af6bdddf 4642 temp_string = base_string;
c3332e24 4643
24eab124 4644 /* Skip past '(' and whitespace. */
252b5132
RH		 4645 ++base_string;
4646 if (is_space_char (*base_string))
24eab124 4647 ++base_string;
252b5132 4648
af6bdddf 4649 if (*base_string == ','
4d1bb795 4650 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4651 {
af6bdddf 4652 displacement_string_end = temp_string;
252b5132 4653
af6bdddf 4654 i.types[this_operand] |= BaseIndex;
252b5132 4655
af6bdddf 4656 if (i.base_reg)
24eab124 4657 {
24eab124
AM		 4658 base_string = end_op;
4659 if (is_space_char (*base_string))
4660 ++base_string;
af6bdddf
AM		 4661 }
4662
4663 /* There may be an index reg or scale factor here. */
4664 if (*base_string == ',')
4665 {
4666 ++base_string;
4667 if (is_space_char (*base_string))
4668 ++base_string;
4669
4d1bb795 4670 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4671 {
af6bdddf 4672 base_string = end_op;
24eab124
AM		 4673 if (is_space_char (*base_string))
4674 ++base_string;
af6bdddf
AM		 4675 if (*base_string == ',')
4676 {
4677 ++base_string;
4678 if (is_space_char (*base_string))
4679 ++base_string;
4680 }
e5cb08ac 4681 else if (*base_string != ')')
af6bdddf
AM		 4682 {
4683 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4684 operand_string);
4685 return 0;
4686 }
24eab124 4687 }
af6bdddf 4688 else if (*base_string == REGISTER_PREFIX)
24eab124 4689 {
af6bdddf 4690 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4691 return 0;
4692 }
252b5132 4693
47926f60 4694 /* Check for scale factor. */
551c1ca1 4695 if (*base_string != ')')
af6bdddf 4696 {
551c1ca1
AM		 4697 char *end_scale = i386_scale (base_string);
4698
4699 if (!end_scale)
af6bdddf 4700 return 0;
24eab124 4701
551c1ca1 4702 base_string = end_scale;
af6bdddf
AM		 4703 if (is_space_char (*base_string))
4704 ++base_string;
4705 if (*base_string != ')')
4706 {
4707 as_bad (_("expecting `)' after scale factor in `%s'"),
4708 operand_string);
4709 return 0;
4710 }
4711 }
4712 else if (!i.index_reg)
24eab124 4713 {
af6bdddf
AM		 4714 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4715 *base_string);
24eab124
AM		 4716 return 0;
4717 }
4718 }
af6bdddf 4719 else if (*base_string != ')')
24eab124 4720 {
af6bdddf
AM		 4721 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4722 operand_string);
24eab124
AM		 4723 return 0;
4724 }
c3332e24 4725 }
af6bdddf 4726 else if (*base_string == REGISTER_PREFIX)
c3332e24 4727 {
af6bdddf 4728 as_bad (_("bad register name `%s'"), base_string);
24eab124 4729 return 0;
c3332e24 4730 }
24eab124
AM		 4731 }
4732
4733 /* If there's an expression beginning the operand, parse it,
4734 assuming displacement_string_start and
4735 displacement_string_end are meaningful. */
4736 if (displacement_string_start != displacement_string_end)
4737 {
4738 if (!i386_displacement (displacement_string_start,
4739 displacement_string_end))
4740 return 0;
4741 }
4742
4743 /* Special case for (%dx) while doing input/output op. */
4744 if (i.base_reg
4745 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4746 && i.index_reg == 0
4747 && i.log2_scale_factor == 0
4748 && i.seg[i.mem_operands] == 0
4749 && (i.types[this_operand] & Disp) == 0)
4750 {
4751 i.types[this_operand] = InOutPortReg;
4752 return 1;
4753 }
4754
eecb386c
AM		 4755 if (i386_index_check (operand_string) == 0)
4756 return 0;
24eab124
AM		 4757 i.mem_operands++;
4758 }
4759 else
ce8a8b2f
AM		 4760 {
4761 /* It's not a memory operand; argh! */
24eab124
AM		 4762 as_bad (_("invalid char %s beginning operand %d `%s'"),
4763 output_invalid (*op_string),
4764 this_operand + 1,
4765 op_string);
4766 return 0;
4767 }
47926f60 4768 return 1; /* Normal return. */
252b5132
RH		 4769}
4770\f
ee7fcc42
AM		 4771/* md_estimate_size_before_relax()
4772
4773 Called just before relax() for rs_machine_dependent frags. The x86
4774 assembler uses these frags to handle variable size jump
4775 instructions.
4776
4777 Any symbol that is now undefined will not become defined.
4778 Return the correct fr_subtype in the frag.
4779 Return the initial "guess for variable size of frag" to caller.
4780 The guess is actually the growth beyond the fixed part. Whatever
4781 we do to grow the fixed or variable part contributes to our
4782 returned value. */
4783
252b5132
RH		 4784int
4785md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4786 fragS *fragP;
4787 segT segment;
252b5132 4788{
252b5132 4789 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4790 check for un-relaxable symbols. On an ELF system, we can't relax
4791 an externally visible symbol, because it may be overridden by a
4792 shared library. */
4793 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4794#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4795 || (IS_ELF
31312f95
AM		 4796 && (S_IS_EXTERNAL (fragP->fr_symbol)
4797 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4798#endif
4799 )
252b5132 4800 {
b98ef147
AM		 4801 /* Symbol is undefined in this segment, or we need to keep a
4802 reloc so that weak symbols can be overridden. */
4803 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4804 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4805 unsigned char *opcode;
4806 int old_fr_fix;
f6af82bd 4807
ee7fcc42
AM		 4808 if (fragP->fr_var != NO_RELOC)
4809 reloc_type = fragP->fr_var;
b98ef147 4810 else if (size == 2)
f6af82bd
AM		 4811 reloc_type = BFD_RELOC_16_PCREL;
4812 else
4813 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4814
ee7fcc42
AM		 4815 old_fr_fix = fragP->fr_fix;
4816 opcode = (unsigned char *) fragP->fr_opcode;
4817
fddf5b5b 4818 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4819 {
fddf5b5b
AM		 4820 case UNCOND_JUMP:
4821 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4822 opcode[0] = 0xe9;
252b5132 4823 fragP->fr_fix += size;
062cd5e7
AS		 4824 fix_new (fragP, old_fr_fix, size,
4825 fragP->fr_symbol,
4826 fragP->fr_offset, 1,
4827 reloc_type);
252b5132
RH		 4828 break;
4829
fddf5b5b 4830 case COND_JUMP86:
412167cb
AM		 4831 if (size == 2
4832 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4833 {
4834 /* Negate the condition, and branch past an
4835 unconditional jump. */
4836 opcode[0] ^= 1;
4837 opcode[1] = 3;
4838 /* Insert an unconditional jump. */
4839 opcode[2] = 0xe9;
4840 /* We added two extra opcode bytes, and have a two byte
4841 offset. */
4842 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4843 fix_new (fragP, old_fr_fix + 2, 2,
4844 fragP->fr_symbol,
4845 fragP->fr_offset, 1,
4846 reloc_type);
fddf5b5b
AM		 4847 break;
4848 }
4849 /* Fall through. */
4850
4851 case COND_JUMP:
412167cb
AM		 4852 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4853 {
3e02c1cc
AM		 4854 fixS *fixP;
4855
412167cb 4856 fragP->fr_fix += 1;
3e02c1cc
AM		 4857 fixP = fix_new (fragP, old_fr_fix, 1,
4858 fragP->fr_symbol,
4859 fragP->fr_offset, 1,
4860 BFD_RELOC_8_PCREL);
4861 fixP->fx_signed = 1;
412167cb
AM		 4862 break;
4863 }
93c2a809 4864
24eab124 4865 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4866 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4867 opcode[1] = opcode[0] + 0x10;
f6af82bd 4868 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4869 /* We've added an opcode byte. */
4870 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4871 fix_new (fragP, old_fr_fix + 1, size,
4872 fragP->fr_symbol,
4873 fragP->fr_offset, 1,
4874 reloc_type);
252b5132 4875 break;
fddf5b5b
AM		 4876
4877 default:
4878 BAD_CASE (fragP->fr_subtype);
4879 break;
252b5132
RH		 4880 }
4881 frag_wane (fragP);
ee7fcc42 4882 return fragP->fr_fix - old_fr_fix;
252b5132 4883 }
93c2a809 4884
93c2a809
AM		 4885 /* Guess size depending on current relax state. Initially the relax
4886 state will correspond to a short jump and we return 1, because
4887 the variable part of the frag (the branch offset) is one byte
4888 long. However, we can relax a section more than once and in that
4889 case we must either set fr_subtype back to the unrelaxed state,
4890 or return the value for the appropriate branch. */
4891 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4892}
4893
47926f60
KH		 4894/* Called after relax() is finished.
4895
4896 In: Address of frag.
4897 fr_type == rs_machine_dependent.
4898 fr_subtype is what the address relaxed to.
4899
4900 Out: Any fixSs and constants are set up.
4901 Caller will turn frag into a ".space 0". */
4902
252b5132
RH		 4903void
4904md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4905 bfd *abfd ATTRIBUTE_UNUSED;
4906 segT sec ATTRIBUTE_UNUSED;
29b0f896 4907 fragS *fragP;
252b5132 4908{
29b0f896 4909 unsigned char *opcode;
252b5132 4910 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4911 offsetT target_address;
4912 offsetT opcode_address;
252b5132 4913 unsigned int extension = 0;
847f7ad4 4914 offsetT displacement_from_opcode_start;
252b5132
RH		 4915
4916 opcode = (unsigned char *) fragP->fr_opcode;
4917
47926f60 4918 /* Address we want to reach in file space. */
252b5132 4919 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4920
47926f60 4921 /* Address opcode resides at in file space. */
252b5132
RH		 4922 opcode_address = fragP->fr_address + fragP->fr_fix;
4923
47926f60 4924 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4925 displacement_from_opcode_start = target_address - opcode_address;
4926
fddf5b5b 4927 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4928 {
47926f60
KH		 4929 /* Don't have to change opcode. */
4930 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4931 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4932 }
4933 else
4934 {
4935 if (no_cond_jump_promotion
4936 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4937 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4938
fddf5b5b
AM		 4939 switch (fragP->fr_subtype)
4940 {
4941 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4942 extension = 4; /* 1 opcode + 4 displacement */
4943 opcode[0] = 0xe9;
4944 where_to_put_displacement = &opcode[1];
4945 break;
252b5132 4946
fddf5b5b
AM		 4947 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4948 extension = 2; /* 1 opcode + 2 displacement */
4949 opcode[0] = 0xe9;
4950 where_to_put_displacement = &opcode[1];
4951 break;
252b5132 4952
fddf5b5b
AM		 4953 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4954 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4955 extension = 5; /* 2 opcode + 4 displacement */
4956 opcode[1] = opcode[0] + 0x10;
4957 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4958 where_to_put_displacement = &opcode[2];
4959 break;
252b5132 4960
fddf5b5b
AM		 4961 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4962 extension = 3; /* 2 opcode + 2 displacement */
4963 opcode[1] = opcode[0] + 0x10;
4964 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4965 where_to_put_displacement = &opcode[2];
4966 break;
252b5132 4967
fddf5b5b
AM		 4968 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4969 extension = 4;
4970 opcode[0] ^= 1;
4971 opcode[1] = 3;
4972 opcode[2] = 0xe9;
4973 where_to_put_displacement = &opcode[3];
4974 break;
4975
4976 default:
4977 BAD_CASE (fragP->fr_subtype);
4978 break;
4979 }
252b5132 4980 }
fddf5b5b 4981
7b81dfbb
AJ		 4982 /* If size if less then four we are sure that the operand fits,
4983 but if it's 4, then it could be that the displacement is larger
4984 then -/+ 2GB. */
4985 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
4986 && object_64bit
4987 && ((addressT) (displacement_from_opcode_start - extension
4988 + ((addressT) 1 << 31))
4989 > (((addressT) 2 << 31) - 1)))
4990 {
4991 as_bad_where (fragP->fr_file, fragP->fr_line,
4992 _("jump target out of range"));
4993 /* Make us emit 0. */
4994 displacement_from_opcode_start = extension;
4995 }
47926f60 4996 /* Now put displacement after opcode. */
252b5132
RH		 4997 md_number_to_chars ((char *) where_to_put_displacement,
4998 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4999 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5000 fragP->fr_fix += extension;
5001}
5002\f
47926f60
KH		 5003/* Size of byte displacement jmp. */
5004int md_short_jump_size = 2;
5005
5006/* Size of dword displacement jmp. */
5007int md_long_jump_size = 5;
252b5132 5008
252b5132
RH		 5009void
5010md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5011 char *ptr;
5012 addressT from_addr, to_addr;
ab9da554
ILT		 5013 fragS *frag ATTRIBUTE_UNUSED;
5014 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5015{
847f7ad4 5016 offsetT offset;
252b5132
RH		 5017
5018 offset = to_addr - (from_addr + 2);
47926f60
KH		 5019 /* Opcode for byte-disp jump. */
5020 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5021 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5022}
5023
5024void
5025md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5026 char *ptr;
5027 addressT from_addr, to_addr;
a38cf1db
AM		 5028 fragS *frag ATTRIBUTE_UNUSED;
5029 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5030{
847f7ad4 5031 offsetT offset;
252b5132 5032
a38cf1db
AM		 5033 offset = to_addr - (from_addr + 5);
5034 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5035 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5036}
5037\f
5038/* Apply a fixup (fixS) to segment data, once it has been determined
5039 by our caller that we have all the info we need to fix it up.
5040
5041 On the 386, immediates, displacements, and data pointers are all in
5042 the same (little-endian) format, so we don't need to care about which
5043 we are handling. */
5044
94f592af 5045void
55cf6793 5046md_apply_fix (fixP, valP, seg)
47926f60
KH		 5047 /* The fix we're to put in. */
5048 fixS *fixP;
47926f60 5049 /* Pointer to the value of the bits. */
c6682705 5050 valueT *valP;
47926f60
KH		 5051 /* Segment fix is from. */
5052 segT seg ATTRIBUTE_UNUSED;
252b5132 5053{
94f592af 5054 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5055 valueT value = *valP;
252b5132 5056
f86103b7 5057#if !defined (TE_Mach)
93382f6d
AM		 5058 if (fixP->fx_pcrel)
5059 {
5060 switch (fixP->fx_r_type)
5061 {
5865bb77
ILT		 5062 default:
5063 break;
5064
d6ab8113
JB		 5065 case BFD_RELOC_64:
5066 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5067 break;
93382f6d 5068 case BFD_RELOC_32:
ae8887b5 5069 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5070 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5071 break;
5072 case BFD_RELOC_16:
5073 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5074 break;
5075 case BFD_RELOC_8:
5076 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5077 break;
5078 }
5079 }
252b5132 5080
a161fe53 5081 if (fixP->fx_addsy != NULL
31312f95 5082 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5083 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5084 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5085 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5086 && !use_rela_relocations)
252b5132 5087 {
31312f95
AM		 5088 /* This is a hack. There should be a better way to handle this.
5089 This covers for the fact that bfd_install_relocation will
5090 subtract the current location (for partial_inplace, PC relative
5091 relocations); see more below. */
252b5132 5092#ifndef OBJ_AOUT
718ddfc0 5093 if (IS_ELF
252b5132
RH		 5094#ifdef TE_PE
5095 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5096#endif
5097 )
5098 value += fixP->fx_where + fixP->fx_frag->fr_address;
5099#endif
5100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5101 if (IS_ELF)
252b5132 5102 {
6539b54b 5103 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5104
6539b54b 5105 if ((sym_seg == seg
2f66722d 5106 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5107 && sym_seg != absolute_section))
ae6063d4 5108 && !generic_force_reloc (fixP))
2f66722d
AM		 5109 {
5110 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5111 bfd_install_relocation subtracts them out again. I think
5112 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5113 it. FIXME. */
5114 value += fixP->fx_where + fixP->fx_frag->fr_address;
5115 }
252b5132
RH		 5116 }
5117#endif
5118#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5119 /* For some reason, the PE format does not store a
5120 section address offset for a PC relative symbol. */
5121 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5122 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5123 value += md_pcrel_from (fixP);
5124#endif
5125 }
5126
5127 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5128 and we must not disappoint it. */
252b5132 5129#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5130 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5131 switch (fixP->fx_r_type)
5132 {
5133 case BFD_RELOC_386_PLT32:
3e73aa7c 5134 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5135 /* Make the jump instruction point to the address of the operand. At
5136 runtime we merely add the offset to the actual PLT entry. */
5137 value = -4;
5138 break;
31312f95 5139
13ae64f3
JJ		 5140 case BFD_RELOC_386_TLS_GD:
5141 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5142 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5143 case BFD_RELOC_386_TLS_IE:
5144 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5145 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5146 case BFD_RELOC_X86_64_TLSGD:
5147 case BFD_RELOC_X86_64_TLSLD:
5148 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5149 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5150 value = 0; /* Fully resolved at runtime. No addend. */
5151 /* Fallthrough */
5152 case BFD_RELOC_386_TLS_LE:
5153 case BFD_RELOC_386_TLS_LDO_32:
5154 case BFD_RELOC_386_TLS_LE_32:
5155 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5156 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5157 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5158 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5159 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5160 break;
5161
67a4f2b7
AO		 5162 case BFD_RELOC_386_TLS_DESC_CALL:
5163 case BFD_RELOC_X86_64_TLSDESC_CALL:
5164 value = 0; /* Fully resolved at runtime. No addend. */
5165 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5166 fixP->fx_done = 0;
5167 return;
5168
00f7efb6
JJ		 5169 case BFD_RELOC_386_GOT32:
5170 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5171 value = 0; /* Fully resolved at runtime. No addend. */
5172 break;
47926f60
KH		 5173
5174 case BFD_RELOC_VTABLE_INHERIT:
5175 case BFD_RELOC_VTABLE_ENTRY:
5176 fixP->fx_done = 0;
94f592af 5177 return;
47926f60
KH		 5178
5179 default:
5180 break;
5181 }
5182#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5183 *valP = value;
f86103b7 5184#endif /* !defined (TE_Mach) */
3e73aa7c 5185
3e73aa7c 5186 /* Are we finished with this relocation now? */
c6682705 5187 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5188 fixP->fx_done = 1;
5189 else if (use_rela_relocations)
5190 {
5191 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5192 /* Remember value for tc_gen_reloc. */
5193 fixP->fx_addnumber = value;
3e73aa7c
JH		 5194 value = 0;
5195 }
f86103b7 5196
94f592af 5197 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5198}
252b5132 5199\f
252b5132
RH		 5200#define MAX_LITTLENUMS 6
5201
47926f60
KH		 5202/* Turn the string pointed to by litP into a floating point constant
5203 of type TYPE, and emit the appropriate bytes. The number of
5204 LITTLENUMS emitted is stored in *SIZEP. An error message is
5205 returned, or NULL on OK. */
5206
252b5132
RH		 5207char *
5208md_atof (type, litP, sizeP)
2ab9b79e 5209 int type;
252b5132
RH		 5210 char *litP;
5211 int *sizeP;
5212{
5213 int prec;
5214 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5215 LITTLENUM_TYPE *wordP;
5216 char *t;
5217
5218 switch (type)
5219 {
5220 case 'f':
5221 case 'F':
5222 prec = 2;
5223 break;
5224
5225 case 'd':
5226 case 'D':
5227 prec = 4;
5228 break;
5229
5230 case 'x':
5231 case 'X':
5232 prec = 5;
5233 break;
5234
5235 default:
5236 *sizeP = 0;
5237 return _("Bad call to md_atof ()");
5238 }
5239 t = atof_ieee (input_line_pointer, type, words);
5240 if (t)
5241 input_line_pointer = t;
5242
5243 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5244 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5245 the bigendian 386. */
5246 for (wordP = words + prec - 1; prec--;)
5247 {
5248 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5249 litP += sizeof (LITTLENUM_TYPE);
5250 }
5251 return 0;
5252}
5253\f
87c245cc 5254static char output_invalid_buf[8];
252b5132 5255
252b5132
RH		 5256static char *
5257output_invalid (c)
5258 int c;
5259{
3882b010 5260 if (ISPRINT (c))
252b5132
RH		 5261 sprintf (output_invalid_buf, "'%c'", c);
5262 else
5263 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5264 return output_invalid_buf;
5265}
5266
af6bdddf 5267/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5268
5269static const reg_entry *
4d1bb795 5270parse_real_register (char *reg_string, char **end_op)
252b5132 5271{
af6bdddf
AM		 5272 char *s = reg_string;
5273 char *p;
252b5132
RH		 5274 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5275 const reg_entry *r;
5276
5277 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5278 if (*s == REGISTER_PREFIX)
5279 ++s;
5280
5281 if (is_space_char (*s))
5282 ++s;
5283
5284 p = reg_name_given;
af6bdddf 5285 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5286 {
5287 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5288 return (const reg_entry *) NULL;
5289 s++;
252b5132
RH		 5290 }
5291
6588847e
DN		 5292 /* For naked regs, make sure that we are not dealing with an identifier.
5293 This prevents confusing an identifier like `eax_var' with register
5294 `eax'. */
5295 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5296 return (const reg_entry *) NULL;
5297
af6bdddf 5298 *end_op = s;
252b5132
RH		 5299
5300 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5301
5f47d35b 5302 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5303 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5304 {
5f47d35b
AM		 5305 if (is_space_char (*s))
5306 ++s;
5307 if (*s == '(')
5308 {
af6bdddf 5309 ++s;
5f47d35b
AM		 5310 if (is_space_char (*s))
5311 ++s;
5312 if (*s >= '0' && *s <= '7')
5313 {
5314 r = &i386_float_regtab[*s - '0'];
af6bdddf 5315 ++s;
5f47d35b
AM		 5316 if (is_space_char (*s))
5317 ++s;
5318 if (*s == ')')
5319 {
5320 *end_op = s + 1;
5321 return r;
5322 }
5f47d35b 5323 }
47926f60 5324 /* We have "%st(" then garbage. */
5f47d35b
AM		 5325 return (const reg_entry *) NULL;
5326 }
5327 }
5328
1ae00879 5329 if (r != NULL
20f0a1fc 5330 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5331 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5332 && flag_code != CODE_64BIT)
20f0a1fc 5333 return (const reg_entry *) NULL;
1ae00879 5334
252b5132
RH		 5335 return r;
5336}
4d1bb795
JB		 5337
5338/* REG_STRING starts *before* REGISTER_PREFIX. */
5339
5340static const reg_entry *
5341parse_register (char *reg_string, char **end_op)
5342{
5343 const reg_entry *r;
5344
5345 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5346 r = parse_real_register (reg_string, end_op);
5347 else
5348 r = NULL;
5349 if (!r)
5350 {
5351 char *save = input_line_pointer;
5352 char c;
5353 symbolS *symbolP;
5354
5355 input_line_pointer = reg_string;
5356 c = get_symbol_end ();
5357 symbolP = symbol_find (reg_string);
5358 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5359 {
5360 const expressionS *e = symbol_get_value_expression (symbolP);
5361
5362 know (e->X_op == O_register);
5363 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5364 r = i386_regtab + e->X_add_number;
5365 *end_op = input_line_pointer;
5366 }
5367 *input_line_pointer = c;
5368 input_line_pointer = save;
5369 }
5370 return r;
5371}
5372
5373int
5374i386_parse_name (char *name, expressionS *e, char *nextcharP)
5375{
5376 const reg_entry *r;
5377 char *end = input_line_pointer;
5378
5379 *end = *nextcharP;
5380 r = parse_register (name, &input_line_pointer);
5381 if (r && end <= input_line_pointer)
5382 {
5383 *nextcharP = *input_line_pointer;
5384 *input_line_pointer = 0;
5385 e->X_op = O_register;
5386 e->X_add_number = r - i386_regtab;
5387 return 1;
5388 }
5389 input_line_pointer = end;
5390 *end = 0;
5391 return 0;
5392}
5393
5394void
5395md_operand (expressionS *e)
5396{
5397 if (*input_line_pointer == REGISTER_PREFIX)
5398 {
5399 char *end;
5400 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5401
5402 if (r)
5403 {
5404 e->X_op = O_register;
5405 e->X_add_number = r - i386_regtab;
5406 input_line_pointer = end;
5407 }
5408 }
5409}
5410
252b5132 5411\f
4cc782b5 5412#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5413const char *md_shortopts = "kVQ:sqn";
252b5132 5414#else
12b55ccc 5415const char *md_shortopts = "qn";
252b5132 5416#endif
6e0b89ee 5417
3e73aa7c 5418#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5419#define OPTION_64 (OPTION_MD_BASE + 1)
5420#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5421
5422struct option md_longopts[] = {
3e73aa7c 5423 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5424#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c 5425 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5426#endif
b3b91714 5427 {"divide", no_argument, NULL, OPTION_DIVIDE},
252b5132
RH		 5428 {NULL, no_argument, NULL, 0}
5429};
5430size_t md_longopts_size = sizeof (md_longopts);
5431
5432int
5433md_parse_option (c, arg)
5434 int c;
ab9da554 5435 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5436{
5437 switch (c)
5438 {
12b55ccc
L		 5439 case 'n':
5440 optimize_align_code = 0;
5441 break;
5442
a38cf1db
AM		 5443 case 'q':
5444 quiet_warnings = 1;
252b5132
RH		 5445 break;
5446
5447#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5448 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5449 should be emitted or not. FIXME: Not implemented. */
5450 case 'Q':
252b5132
RH		 5451 break;
5452
5453 /* -V: SVR4 argument to print version ID. */
5454 case 'V':
5455 print_version_id ();
5456 break;
5457
a38cf1db
AM		 5458 /* -k: Ignore for FreeBSD compatibility. */
5459 case 'k':
252b5132 5460 break;
4cc782b5
ILT		 5461
5462 case 's':
5463 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5464 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5465 break;
6e0b89ee 5466
3e73aa7c
JH		 5467 case OPTION_64:
5468 {
5469 const char **list, **l;
5470
3e73aa7c
JH		 5471 list = bfd_target_list ();
5472 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5473 if (strcmp (*l, "elf64-x86-64") == 0)
5474 {
5475 default_arch = "x86_64";
5476 break;
5477 }
3e73aa7c 5478 if (*l == NULL)
6e0b89ee 5479 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5480 free (list);
5481 }
5482 break;
5483#endif
252b5132 5484
6e0b89ee
AM		 5485 case OPTION_32:
5486 default_arch = "i386";
5487 break;
5488
b3b91714
AM		 5489 case OPTION_DIVIDE:
5490#ifdef SVR4_COMMENT_CHARS
5491 {
5492 char *n, *t;
5493 const char *s;
5494
5495 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5496 t = n;
5497 for (s = i386_comment_chars; *s != '\0'; s++)
5498 if (*s != '/')
5499 *t++ = *s;
5500 *t = '\0';
5501 i386_comment_chars = n;
5502 }
5503#endif
5504 break;
5505
252b5132
RH		 5506 default:
5507 return 0;
5508 }
5509 return 1;
5510}
5511
5512void
5513md_show_usage (stream)
5514 FILE *stream;
5515{
4cc782b5
ILT		 5516#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5517 fprintf (stream, _("\
a38cf1db
AM		 5518 -Q ignored\n\
5519 -V print assembler version number\n\
b3b91714
AM		 5520 -k ignored\n"));
5521#endif
5522 fprintf (stream, _("\
12b55ccc 5523 -n Do not optimize code alignment\n\
b3b91714
AM		 5524 -q quieten some warnings\n"));
5525#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5526 fprintf (stream, _("\
a38cf1db 5527 -s ignored\n"));
b3b91714
AM		 5528#endif
5529#ifdef SVR4_COMMENT_CHARS
5530 fprintf (stream, _("\
5531 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5532#else
5533 fprintf (stream, _("\
b3b91714 5534 --divide ignored\n"));
4cc782b5 5535#endif
252b5132
RH		 5536}
5537
3e73aa7c
JH		 5538#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5539 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5540
5541/* Pick the target format to use. */
5542
47926f60 5543const char *
252b5132
RH		 5544i386_target_format ()
5545{
3e73aa7c
JH		 5546 if (!strcmp (default_arch, "x86_64"))
5547 set_code_flag (CODE_64BIT);
5548 else if (!strcmp (default_arch, "i386"))
5549 set_code_flag (CODE_32BIT);
5550 else
5551 as_fatal (_("Unknown architecture"));
252b5132
RH		 5552 switch (OUTPUT_FLAVOR)
5553 {
4c63da97
AM		 5554#ifdef OBJ_MAYBE_AOUT
5555 case bfd_target_aout_flavour:
47926f60 5556 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5557#endif
5558#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5559 case bfd_target_coff_flavour:
5560 return "coff-i386";
4c63da97 5561#endif
3e73aa7c 5562#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5563 case bfd_target_elf_flavour:
3e73aa7c 5564 {
e5cb08ac 5565 if (flag_code == CODE_64BIT)
4fa24527
JB		 5566 {
5567 object_64bit = 1;
5568 use_rela_relocations = 1;
5569 }
4ada7262 5570 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5571 }
4c63da97 5572#endif
252b5132
RH		 5573 default:
5574 abort ();
5575 return NULL;
5576 }
5577}
5578
47926f60 5579#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5580
5581#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5582void i386_elf_emit_arch_note ()
5583{
718ddfc0 5584 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5585 {
5586 char *p;
5587 asection *seg = now_seg;
5588 subsegT subseg = now_subseg;
5589 Elf_Internal_Note i_note;
5590 Elf_External_Note e_note;
5591 asection *note_secp;
5592 int len;
5593
5594 /* Create the .note section. */
5595 note_secp = subseg_new (".note", 0);
5596 bfd_set_section_flags (stdoutput,
5597 note_secp,
5598 SEC_HAS_CONTENTS | SEC_READONLY);
5599
5600 /* Process the arch string. */
5601 len = strlen (cpu_arch_name);
5602
5603 i_note.namesz = len + 1;
5604 i_note.descsz = 0;
5605 i_note.type = NT_ARCH;
5606 p = frag_more (sizeof (e_note.namesz));
5607 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5608 p = frag_more (sizeof (e_note.descsz));
5609 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5610 p = frag_more (sizeof (e_note.type));
5611 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5612 p = frag_more (len + 1);
5613 strcpy (p, cpu_arch_name);
5614
5615 frag_align (2, 0, 0);
5616
5617 subseg_set (seg, subseg);
5618 }
5619}
5620#endif
252b5132 5621\f
252b5132
RH		 5622symbolS *
5623md_undefined_symbol (name)
5624 char *name;
5625{
18dc2407
ILT		 5626 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5627 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5628 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5629 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5630 {
5631 if (!GOT_symbol)
5632 {
5633 if (symbol_find (name))
5634 as_bad (_("GOT already in symbol table"));
5635 GOT_symbol = symbol_new (name, undefined_section,
5636 (valueT) 0, &zero_address_frag);
5637 };
5638 return GOT_symbol;
5639 }
252b5132
RH		 5640 return 0;
5641}
5642
5643/* Round up a section size to the appropriate boundary. */
47926f60 5644
252b5132
RH		 5645valueT
5646md_section_align (segment, size)
ab9da554 5647 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5648 valueT size;
5649{
4c63da97
AM		 5650#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5651 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5652 {
5653 /* For a.out, force the section size to be aligned. If we don't do
5654 this, BFD will align it for us, but it will not write out the
5655 final bytes of the section. This may be a bug in BFD, but it is
5656 easier to fix it here since that is how the other a.out targets
5657 work. */
5658 int align;
5659
5660 align = bfd_get_section_alignment (stdoutput, segment);
5661 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5662 }
252b5132
RH		 5663#endif
5664
5665 return size;
5666}
5667
5668/* On the i386, PC-relative offsets are relative to the start of the
5669 next instruction. That is, the address of the offset, plus its
5670 size, since the offset is always the last part of the insn. */
5671
5672long
5673md_pcrel_from (fixP)
5674 fixS *fixP;
5675{
5676 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5677}
5678
5679#ifndef I386COFF
5680
5681static void
5682s_bss (ignore)
ab9da554 5683 int ignore ATTRIBUTE_UNUSED;
252b5132 5684{
29b0f896 5685 int temp;
252b5132 5686
8a75718c
JB		 5687#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5688 if (IS_ELF)
5689 obj_elf_section_change_hook ();
5690#endif
252b5132
RH		 5691 temp = get_absolute_expression ();
5692 subseg_set (bss_section, (subsegT) temp);
5693 demand_empty_rest_of_line ();
5694}
5695
5696#endif
5697
252b5132
RH		 5698void
5699i386_validate_fix (fixp)
5700 fixS *fixp;
5701{
5702 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5703 {
23df1078
JH		 5704 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5705 {
4fa24527 5706 if (!object_64bit)
23df1078
JH		 5707 abort ();
5708 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5709 }
5710 else
5711 {
4fa24527 5712 if (!object_64bit)
d6ab8113
JB		 5713 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5714 else
5715 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5716 }
252b5132
RH		 5717 fixp->fx_subsy = 0;
5718 }
5719}
5720
252b5132
RH		 5721arelent *
5722tc_gen_reloc (section, fixp)
ab9da554 5723 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5724 fixS *fixp;
5725{
5726 arelent *rel;
5727 bfd_reloc_code_real_type code;
5728
5729 switch (fixp->fx_r_type)
5730 {
3e73aa7c
JH		 5731 case BFD_RELOC_X86_64_PLT32:
5732 case BFD_RELOC_X86_64_GOT32:
5733 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5734 case BFD_RELOC_386_PLT32:
5735 case BFD_RELOC_386_GOT32:
5736 case BFD_RELOC_386_GOTOFF:
5737 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5738 case BFD_RELOC_386_TLS_GD:
5739 case BFD_RELOC_386_TLS_LDM:
5740 case BFD_RELOC_386_TLS_LDO_32:
5741 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5742 case BFD_RELOC_386_TLS_IE:
5743 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5744 case BFD_RELOC_386_TLS_LE_32:
5745 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 5746 case BFD_RELOC_386_TLS_GOTDESC:
5747 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 5748 case BFD_RELOC_X86_64_TLSGD:
5749 case BFD_RELOC_X86_64_TLSLD:
5750 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5751 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5752 case BFD_RELOC_X86_64_GOTTPOFF:
5753 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5754 case BFD_RELOC_X86_64_TPOFF64:
5755 case BFD_RELOC_X86_64_GOTOFF64:
5756 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 5757 case BFD_RELOC_X86_64_GOT64:
5758 case BFD_RELOC_X86_64_GOTPCREL64:
5759 case BFD_RELOC_X86_64_GOTPC64:
5760 case BFD_RELOC_X86_64_GOTPLT64:
5761 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 5762 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5763 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 5764 case BFD_RELOC_RVA:
5765 case BFD_RELOC_VTABLE_ENTRY:
5766 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5767#ifdef TE_PE
5768 case BFD_RELOC_32_SECREL:
5769#endif
252b5132
RH		 5770 code = fixp->fx_r_type;
5771 break;
dbbaec26
L		 5772 case BFD_RELOC_X86_64_32S:
5773 if (!fixp->fx_pcrel)
5774 {
5775 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5776 code = fixp->fx_r_type;
5777 break;
5778 }
252b5132 5779 default:
93382f6d 5780 if (fixp->fx_pcrel)
252b5132 5781 {
93382f6d
AM		 5782 switch (fixp->fx_size)
5783 {
5784 default:
b091f402
AM		 5785 as_bad_where (fixp->fx_file, fixp->fx_line,
5786 _("can not do %d byte pc-relative relocation"),
5787 fixp->fx_size);
93382f6d
AM		 5788 code = BFD_RELOC_32_PCREL;
5789 break;
5790 case 1: code = BFD_RELOC_8_PCREL; break;
5791 case 2: code = BFD_RELOC_16_PCREL; break;
5792 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5793#ifdef BFD64
5794 case 8: code = BFD_RELOC_64_PCREL; break;
5795#endif
93382f6d
AM		 5796 }
5797 }
5798 else
5799 {
5800 switch (fixp->fx_size)
5801 {
5802 default:
b091f402
AM		 5803 as_bad_where (fixp->fx_file, fixp->fx_line,
5804 _("can not do %d byte relocation"),
5805 fixp->fx_size);
93382f6d
AM		 5806 code = BFD_RELOC_32;
5807 break;
5808 case 1: code = BFD_RELOC_8; break;
5809 case 2: code = BFD_RELOC_16; break;
5810 case 4: code = BFD_RELOC_32; break;
937149dd 5811#ifdef BFD64
3e73aa7c 5812 case 8: code = BFD_RELOC_64; break;
937149dd 5813#endif
93382f6d 5814 }
252b5132
RH		 5815 }
5816 break;
5817 }
252b5132 5818
d182319b
JB		 5819 if ((code == BFD_RELOC_32
5820 || code == BFD_RELOC_32_PCREL
5821 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 5822 && GOT_symbol
5823 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5824 {
4fa24527 5825 if (!object_64bit)
d6ab8113
JB		 5826 code = BFD_RELOC_386_GOTPC;
5827 else
5828 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5829 }
7b81dfbb
AJ		 5830 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
5831 && GOT_symbol
5832 && fixp->fx_addsy == GOT_symbol)
5833 {
5834 code = BFD_RELOC_X86_64_GOTPC64;
5835 }
252b5132
RH		 5836
5837 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5838 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5839 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5840
5841 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5842
3e73aa7c
JH		 5843 if (!use_rela_relocations)
5844 {
5845 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5846 vtable entry to be used in the relocation's section offset. */
5847 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5848 rel->address = fixp->fx_offset;
252b5132 5849
c6682705 5850 rel->addend = 0;
3e73aa7c
JH		 5851 }
5852 /* Use the rela in 64bit mode. */
252b5132 5853 else
3e73aa7c 5854 {
062cd5e7
AS		 5855 if (!fixp->fx_pcrel)
5856 rel->addend = fixp->fx_offset;
5857 else
5858 switch (code)
5859 {
5860 case BFD_RELOC_X86_64_PLT32:
5861 case BFD_RELOC_X86_64_GOT32:
5862 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5863 case BFD_RELOC_X86_64_TLSGD:
5864 case BFD_RELOC_X86_64_TLSLD:
5865 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 5866 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5867 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 5868 rel->addend = fixp->fx_offset - fixp->fx_size;
5869 break;
5870 default:
5871 rel->addend = (section->vma
5872 - fixp->fx_size
5873 + fixp->fx_addnumber
5874 + md_pcrel_from (fixp));
5875 break;
5876 }
3e73aa7c
JH		 5877 }
5878
252b5132
RH		 5879 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5880 if (rel->howto == NULL)
5881 {
5882 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5883 _("cannot represent relocation type %s"),
252b5132
RH		 5884 bfd_get_reloc_code_name (code));
5885 /* Set howto to a garbage value so that we can keep going. */
5886 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5887 assert (rel->howto != NULL);
5888 }
5889
5890 return rel;
5891}
5892
64a0c779
DN		 5893\f
5894/* Parse operands using Intel syntax. This implements a recursive descent
5895 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5896 Programmer's Guide.
5897
5898 FIXME: We do not recognize the full operand grammar defined in the MASM
5899 documentation. In particular, all the structure/union and
5900 high-level macro operands are missing.
5901
5902 Uppercase words are terminals, lower case words are non-terminals.
5903 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5904 bars '|' denote choices. Most grammar productions are implemented in
5905 functions called 'intel_<production>'.
5906
5907 Initial production is 'expr'.
5908
9306ca4a 5909 addOp + | -
64a0c779
DN		 5910
5911 alpha [a-zA-Z]
5912
9306ca4a
JB		 5913 binOp & | AND | \| | OR | ^ | XOR
5914
64a0c779
DN		 5915 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5916
5917 constant digits [[ radixOverride ]]
5918
9306ca4a 5919 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5920
5921 digits decdigit
b77a7acd
AJ		 5922 | digits decdigit
5923 | digits hexdigit
64a0c779
DN		 5924
5925 decdigit [0-9]
5926
9306ca4a
JB		 5927 e04 e04 addOp e05
5928 | e05
5929
5930 e05 e05 binOp e06
b77a7acd 5931 | e06
64a0c779
DN		 5932
5933 e06 e06 mulOp e09
b77a7acd 5934 | e09
64a0c779
DN		 5935
5936 e09 OFFSET e10
a724f0f4
JB		 5937 | SHORT e10
5938 | + e10
5939 | - e10
9306ca4a
JB		 5940 | ~ e10
5941 | NOT e10
64a0c779
DN		 5942 | e09 PTR e10
5943 | e09 : e10
5944 | e10
5945
5946 e10 e10 [ expr ]
b77a7acd 5947 | e11
64a0c779
DN		 5948
5949 e11 ( expr )
b77a7acd 5950 | [ expr ]
64a0c779
DN		 5951 | constant
5952 | dataType
5953 | id
5954 | $
5955 | register
5956
a724f0f4 5957 => expr expr cmpOp e04
9306ca4a 5958 | e04
64a0c779
DN		 5959
5960 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5961 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5962
5963 hexdigit a | b | c | d | e | f
b77a7acd 5964 | A | B | C | D | E | F
64a0c779
DN		 5965
5966 id alpha
b77a7acd 5967 | id alpha
64a0c779
DN		 5968 | id decdigit
5969
9306ca4a 5970 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5971
5972 quote " | '
5973
5974 register specialRegister
b77a7acd 5975 | gpRegister
64a0c779
DN		 5976 | byteRegister
5977
5978 segmentRegister CS | DS | ES | FS | GS | SS
5979
9306ca4a 5980 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5981 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5982 | TR3 | TR4 | TR5 | TR6 | TR7
5983
64a0c779
DN		 5984 We simplify the grammar in obvious places (e.g., register parsing is
5985 done by calling parse_register) and eliminate immediate left recursion
5986 to implement a recursive-descent parser.
5987
a724f0f4
JB		 5988 expr e04 expr'
5989
5990 expr' cmpOp e04 expr'
5991 | Empty
9306ca4a
JB		 5992
5993 e04 e05 e04'
5994
5995 e04' addOp e05 e04'
5996 | Empty
64a0c779
DN		 5997
5998 e05 e06 e05'
5999
9306ca4a 6000 e05' binOp e06 e05'
b77a7acd 6001 | Empty
64a0c779
DN		 6002
6003 e06 e09 e06'
6004
6005 e06' mulOp e09 e06'
b77a7acd 6006 | Empty
64a0c779
DN		 6007
6008 e09 OFFSET e10 e09'
a724f0f4
JB		 6009 | SHORT e10'
6010 | + e10'
6011 | - e10'
6012 | ~ e10'
6013 | NOT e10'
b77a7acd 6014 | e10 e09'
64a0c779
DN		 6015
6016 e09' PTR e10 e09'
b77a7acd 6017 | : e10 e09'
64a0c779
DN		 6018 | Empty
6019
6020 e10 e11 e10'
6021
6022 e10' [ expr ] e10'
b77a7acd 6023 | Empty
64a0c779
DN		 6024
6025 e11 ( expr )
b77a7acd 6026 | [ expr ]
64a0c779
DN		 6027 | BYTE
6028 | WORD
6029 | DWORD
9306ca4a 6030 | FWORD
64a0c779 6031 | QWORD
9306ca4a
JB		 6032 | TBYTE
6033 | OWORD
6034 | XMMWORD
64a0c779
DN		 6035 | .
6036 | $
6037 | register
6038 | id
6039 | constant */
6040
6041/* Parsing structure for the intel syntax parser. Used to implement the
6042 semantic actions for the operand grammar. */
6043struct intel_parser_s
6044 {
6045 char *op_string; /* The string being parsed. */
6046 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6047 int op_modifier; /* Operand modifier. */
64a0c779 6048 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6049 int in_offset; /* >=1 if parsing operand of offset. */
6050 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6051 const reg_entry *reg; /* Last register reference found. */
6052 char *disp; /* Displacement string being built. */
a724f0f4 6053 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6054 };
6055
6056static struct intel_parser_s intel_parser;
6057
6058/* Token structure for parsing intel syntax. */
6059struct intel_token
6060 {
6061 int code; /* Token code. */
6062 const reg_entry *reg; /* Register entry for register tokens. */
6063 char *str; /* String representation. */
6064 };
6065
6066static struct intel_token cur_token, prev_token;
6067
50705ef4
AM		 6068/* Token codes for the intel parser. Since T_SHORT is already used
6069 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6070#define T_NIL -1
6071#define T_CONST 1
6072#define T_REG 2
6073#define T_BYTE 3
6074#define T_WORD 4
9306ca4a
JB		 6075#define T_DWORD 5
6076#define T_FWORD 6
6077#define T_QWORD 7
6078#define T_TBYTE 8
6079#define T_XMMWORD 9
50705ef4 6080#undef T_SHORT
9306ca4a
JB		 6081#define T_SHORT 10
6082#define T_OFFSET 11
6083#define T_PTR 12
6084#define T_ID 13
6085#define T_SHL 14
6086#define T_SHR 15
64a0c779
DN		 6087
6088/* Prototypes for intel parser functions. */
6089static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6090static void intel_get_token PARAMS ((void));
6091static void intel_putback_token PARAMS ((void));
6092static int intel_expr PARAMS ((void));
9306ca4a 6093static int intel_e04 PARAMS ((void));
cce0cbdc 6094static int intel_e05 PARAMS ((void));
cce0cbdc 6095static int intel_e06 PARAMS ((void));
cce0cbdc 6096static int intel_e09 PARAMS ((void));
a724f0f4 6097static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6098static int intel_e10 PARAMS ((void));
cce0cbdc 6099static int intel_e11 PARAMS ((void));
64a0c779 6100
64a0c779
DN		 6101static int
6102i386_intel_operand (operand_string, got_a_float)
6103 char *operand_string;
6104 int got_a_float;
6105{
6106 int ret;
6107 char *p;
6108
a724f0f4
JB		 6109 p = intel_parser.op_string = xstrdup (operand_string);
6110 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6111
6112 for (;;)
64a0c779 6113 {
a724f0f4
JB		 6114 /* Initialize token holders. */
6115 cur_token.code = prev_token.code = T_NIL;
6116 cur_token.reg = prev_token.reg = NULL;
6117 cur_token.str = prev_token.str = NULL;
6118
6119 /* Initialize parser structure. */
6120 intel_parser.got_a_float = got_a_float;
6121 intel_parser.op_modifier = 0;
6122 intel_parser.is_mem = 0;
6123 intel_parser.in_offset = 0;
6124 intel_parser.in_bracket = 0;
6125 intel_parser.reg = NULL;
6126 intel_parser.disp[0] = '\0';
6127 intel_parser.next_operand = NULL;
6128
6129 /* Read the first token and start the parser. */
6130 intel_get_token ();
6131 ret = intel_expr ();
6132
6133 if (!ret)
6134 break;
6135
9306ca4a
JB		 6136 if (cur_token.code != T_NIL)
6137 {
6138 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6139 current_templates->start->name, cur_token.str);
6140 ret = 0;
6141 }
64a0c779
DN		 6142 /* If we found a memory reference, hand it over to i386_displacement
6143 to fill in the rest of the operand fields. */
9306ca4a 6144 else if (intel_parser.is_mem)
64a0c779
DN		 6145 {
6146 if ((i.mem_operands == 1
6147 && (current_templates->start->opcode_modifier & IsString) == 0)
6148 || i.mem_operands == 2)
6149 {
6150 as_bad (_("too many memory references for '%s'"),
6151 current_templates->start->name);
6152 ret = 0;
6153 }
6154 else
6155 {
6156 char *s = intel_parser.disp;
6157 i.mem_operands++;
6158
a724f0f4
JB		 6159 if (!quiet_warnings && intel_parser.is_mem < 0)
6160 /* See the comments in intel_bracket_expr. */
6161 as_warn (_("Treating `%s' as memory reference"), operand_string);
6162
64a0c779
DN		 6163 /* Add the displacement expression. */
6164 if (*s != '\0')
a4622f40
AM		 6165 ret = i386_displacement (s, s + strlen (s));
6166 if (ret)
a724f0f4
JB		 6167 {
6168 /* Swap base and index in 16-bit memory operands like
6169 [si+bx]. Since i386_index_check is also used in AT&T
6170 mode we have to do that here. */
6171 if (i.base_reg
6172 && i.index_reg
6173 && (i.base_reg->reg_type & Reg16)
6174 && (i.index_reg->reg_type & Reg16)
6175 && i.base_reg->reg_num >= 6
6176 && i.index_reg->reg_num < 6)
6177 {
6178 const reg_entry *base = i.index_reg;
6179
6180 i.index_reg = i.base_reg;
6181 i.base_reg = base;
6182 }
6183 ret = i386_index_check (operand_string);
6184 }
64a0c779
DN		 6185 }
6186 }
6187
6188 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6189 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6190 || intel_parser.reg == NULL)
6191 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6192
6193 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6194 ret = 0;
6195 if (!ret || !intel_parser.next_operand)
6196 break;
6197 intel_parser.op_string = intel_parser.next_operand;
6198 this_operand = i.operands++;
64a0c779
DN		 6199 }
6200
6201 free (p);
6202 free (intel_parser.disp);
6203
6204 return ret;
6205}
6206
a724f0f4
JB		 6207#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6208
6209/* expr e04 expr'
6210
6211 expr' cmpOp e04 expr'
6212 | Empty */
64a0c779
DN		 6213static int
6214intel_expr ()
6215{
a724f0f4
JB		 6216 /* XXX Implement the comparison operators. */
6217 return intel_e04 ();
9306ca4a
JB		 6218}
6219
a724f0f4 6220/* e04 e05 e04'
9306ca4a 6221
a724f0f4 6222 e04' addOp e05 e04'
9306ca4a
JB		 6223 | Empty */
6224static int
6225intel_e04 ()
6226{
a724f0f4 6227 int nregs = -1;
9306ca4a 6228
a724f0f4 6229 for (;;)
9306ca4a 6230 {
a724f0f4
JB		 6231 if (!intel_e05())
6232 return 0;
9306ca4a 6233
a724f0f4
JB		 6234 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6235 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6236
a724f0f4
JB		 6237 if (cur_token.code == '+')
6238 nregs = -1;
6239 else if (cur_token.code == '-')
6240 nregs = NUM_ADDRESS_REGS;
6241 else
6242 return 1;
64a0c779 6243
a724f0f4
JB		 6244 strcat (intel_parser.disp, cur_token.str);
6245 intel_match_token (cur_token.code);
6246 }
64a0c779
DN		 6247}
6248
64a0c779
DN		 6249/* e05 e06 e05'
6250
9306ca4a 6251 e05' binOp e06 e05'
64a0c779
DN		 6252 | Empty */
6253static int
6254intel_e05 ()
6255{
a724f0f4 6256 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6257
a724f0f4 6258 for (;;)
64a0c779 6259 {
a724f0f4
JB		 6260 if (!intel_e06())
6261 return 0;
6262
6263 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6264 {
6265 char str[2];
6266
6267 str[0] = cur_token.code;
6268 str[1] = 0;
6269 strcat (intel_parser.disp, str);
6270 }
6271 else
6272 break;
9306ca4a 6273
64a0c779
DN		 6274 intel_match_token (cur_token.code);
6275
a724f0f4
JB		 6276 if (nregs < 0)
6277 nregs = ~nregs;
64a0c779 6278 }
a724f0f4
JB		 6279 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6280 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6281 return 1;
4a1805b1 6282}
64a0c779
DN		 6283
6284/* e06 e09 e06'
6285
6286 e06' mulOp e09 e06'
b77a7acd 6287 | Empty */
64a0c779
DN		 6288static int
6289intel_e06 ()
6290{
a724f0f4 6291 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6292
a724f0f4 6293 for (;;)
64a0c779 6294 {
a724f0f4
JB		 6295 if (!intel_e09())
6296 return 0;
9306ca4a 6297
a724f0f4
JB		 6298 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6299 {
6300 char str[2];
9306ca4a 6301
a724f0f4
JB		 6302 str[0] = cur_token.code;
6303 str[1] = 0;
6304 strcat (intel_parser.disp, str);
6305 }
6306 else if (cur_token.code == T_SHL)
6307 strcat (intel_parser.disp, "<<");
6308 else if (cur_token.code == T_SHR)
6309 strcat (intel_parser.disp, ">>");
6310 else
6311 break;
9306ca4a 6312
64e74474 6313 intel_match_token (cur_token.code);
64a0c779 6314
a724f0f4
JB		 6315 if (nregs < 0)
6316 nregs = ~nregs;
64a0c779 6317 }
a724f0f4
JB		 6318 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6319 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6320 return 1;
64a0c779
DN		 6321}
6322
a724f0f4
JB		 6323/* e09 OFFSET e09
6324 | SHORT e09
6325 | + e09
6326 | - e09
6327 | ~ e09
6328 | NOT e09
9306ca4a
JB		 6329 | e10 e09'
6330
64a0c779 6331 e09' PTR e10 e09'
b77a7acd 6332 | : e10 e09'
64a0c779
DN		 6333 | Empty */
6334static int
6335intel_e09 ()
6336{
a724f0f4
JB		 6337 int nregs = ~NUM_ADDRESS_REGS;
6338 int in_offset = 0;
6339
6340 for (;;)
64a0c779 6341 {
a724f0f4
JB		 6342 /* Don't consume constants here. */
6343 if (cur_token.code == '+' || cur_token.code == '-')
6344 {
6345 /* Need to look one token ahead - if the next token
6346 is a constant, the current token is its sign. */
6347 int next_code;
6348
6349 intel_match_token (cur_token.code);
6350 next_code = cur_token.code;
6351 intel_putback_token ();
6352 if (next_code == T_CONST)
6353 break;
6354 }
6355
6356 /* e09 OFFSET e09 */
6357 if (cur_token.code == T_OFFSET)
6358 {
6359 if (!in_offset++)
6360 ++intel_parser.in_offset;
6361 }
6362
6363 /* e09 SHORT e09 */
6364 else if (cur_token.code == T_SHORT)
6365 intel_parser.op_modifier |= 1 << T_SHORT;
6366
6367 /* e09 + e09 */
6368 else if (cur_token.code == '+')
6369 strcat (intel_parser.disp, "+");
6370
6371 /* e09 - e09
6372 | ~ e09
6373 | NOT e09 */
6374 else if (cur_token.code == '-' || cur_token.code == '~')
6375 {
6376 char str[2];
64a0c779 6377
a724f0f4
JB		 6378 if (nregs < 0)
6379 nregs = ~nregs;
6380 str[0] = cur_token.code;
6381 str[1] = 0;
6382 strcat (intel_parser.disp, str);
6383 }
6384
6385 /* e09 e10 e09' */
6386 else
6387 break;
6388
6389 intel_match_token (cur_token.code);
64a0c779
DN		 6390 }
6391
a724f0f4 6392 for (;;)
9306ca4a 6393 {
a724f0f4
JB		 6394 if (!intel_e10 ())
6395 return 0;
9306ca4a 6396
a724f0f4
JB		 6397 /* e09' PTR e10 e09' */
6398 if (cur_token.code == T_PTR)
6399 {
6400 char suffix;
9306ca4a 6401
a724f0f4
JB		 6402 if (prev_token.code == T_BYTE)
6403 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6404
a724f0f4
JB		 6405 else if (prev_token.code == T_WORD)
6406 {
6407 if (current_templates->start->name[0] == 'l'
6408 && current_templates->start->name[2] == 's'
6409 && current_templates->start->name[3] == 0)
6410 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6411 else if (intel_parser.got_a_float == 2) /* "fi..." */
6412 suffix = SHORT_MNEM_SUFFIX;
6413 else
6414 suffix = WORD_MNEM_SUFFIX;
6415 }
64a0c779 6416
a724f0f4
JB		 6417 else if (prev_token.code == T_DWORD)
6418 {
6419 if (current_templates->start->name[0] == 'l'
6420 && current_templates->start->name[2] == 's'
6421 && current_templates->start->name[3] == 0)
6422 suffix = WORD_MNEM_SUFFIX;
6423 else if (flag_code == CODE_16BIT
6424 && (current_templates->start->opcode_modifier
435acd52 6425 & (Jump | JumpDword)))
a724f0f4
JB		 6426 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6427 else if (intel_parser.got_a_float == 1) /* "f..." */
6428 suffix = SHORT_MNEM_SUFFIX;
6429 else
6430 suffix = LONG_MNEM_SUFFIX;
6431 }
9306ca4a 6432
a724f0f4
JB		 6433 else if (prev_token.code == T_FWORD)
6434 {
6435 if (current_templates->start->name[0] == 'l'
6436 && current_templates->start->name[2] == 's'
6437 && current_templates->start->name[3] == 0)
6438 suffix = LONG_MNEM_SUFFIX;
6439 else if (!intel_parser.got_a_float)
6440 {
6441 if (flag_code == CODE_16BIT)
6442 add_prefix (DATA_PREFIX_OPCODE);
6443 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6444 }
6445 else
6446 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6447 }
64a0c779 6448
a724f0f4
JB		 6449 else if (prev_token.code == T_QWORD)
6450 {
6451 if (intel_parser.got_a_float == 1) /* "f..." */
6452 suffix = LONG_MNEM_SUFFIX;
6453 else
6454 suffix = QWORD_MNEM_SUFFIX;
6455 }
64a0c779 6456
a724f0f4
JB		 6457 else if (prev_token.code == T_TBYTE)
6458 {
6459 if (intel_parser.got_a_float == 1)
6460 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6461 else
6462 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6463 }
9306ca4a 6464
a724f0f4 6465 else if (prev_token.code == T_XMMWORD)
9306ca4a 6466 {
a724f0f4
JB		 6467 /* XXX ignored for now, but accepted since gcc uses it */
6468 suffix = 0;
9306ca4a 6469 }
64a0c779 6470
f16b83df 6471 else
a724f0f4
JB		 6472 {
6473 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6474 return 0;
6475 }
6476
435acd52
JB		 6477 /* Operands for jump/call using 'ptr' notation denote absolute
6478 addresses. */
6479 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6480 i.types[this_operand] |= JumpAbsolute;
6481
a724f0f4
JB		 6482 if (current_templates->start->base_opcode == 0x8d /* lea */)
6483 ;
6484 else if (!i.suffix)
6485 i.suffix = suffix;
6486 else if (i.suffix != suffix)
6487 {
6488 as_bad (_("Conflicting operand modifiers"));
6489 return 0;
6490 }
64a0c779 6491
9306ca4a
JB		 6492 }
6493
a724f0f4
JB		 6494 /* e09' : e10 e09' */
6495 else if (cur_token.code == ':')
9306ca4a 6496 {
a724f0f4
JB		 6497 if (prev_token.code != T_REG)
6498 {
6499 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6500 segment/group identifier (which we don't have), using comma
6501 as the operand separator there is even less consistent, since
6502 there all branches only have a single operand. */
6503 if (this_operand != 0
6504 || intel_parser.in_offset
6505 || intel_parser.in_bracket
6506 || (!(current_templates->start->opcode_modifier
6507 & (Jump|JumpDword|JumpInterSegment))
6508 && !(current_templates->start->operand_types[0]
6509 & JumpAbsolute)))
6510 return intel_match_token (T_NIL);
6511 /* Remember the start of the 2nd operand and terminate 1st
6512 operand here.
6513 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6514 another expression), but it gets at least the simplest case
6515 (a plain number or symbol on the left side) right. */
6516 intel_parser.next_operand = intel_parser.op_string;
6517 *--intel_parser.op_string = '\0';
6518 return intel_match_token (':');
6519 }
9306ca4a 6520 }
64a0c779 6521
a724f0f4 6522 /* e09' Empty */
64a0c779 6523 else
a724f0f4 6524 break;
64a0c779 6525
a724f0f4
JB		 6526 intel_match_token (cur_token.code);
6527
6528 }
6529
6530 if (in_offset)
6531 {
6532 --intel_parser.in_offset;
6533 if (nregs < 0)
6534 nregs = ~nregs;
6535 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6536 {
a724f0f4 6537 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6538 return 0;
6539 }
a724f0f4
JB		 6540 intel_parser.op_modifier |= 1 << T_OFFSET;
6541 }
9306ca4a 6542
a724f0f4
JB		 6543 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6544 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6545 return 1;
6546}
64a0c779 6547
a724f0f4
JB		 6548static int
6549intel_bracket_expr ()
6550{
6551 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6552 const char *start = intel_parser.op_string;
6553 int len;
6554
6555 if (i.op[this_operand].regs)
6556 return intel_match_token (T_NIL);
6557
6558 intel_match_token ('[');
6559
6560 /* Mark as a memory operand only if it's not already known to be an
6561 offset expression. If it's an offset expression, we need to keep
6562 the brace in. */
6563 if (!intel_parser.in_offset)
6564 {
6565 ++intel_parser.in_bracket;
435acd52
JB		 6566
6567 /* Operands for jump/call inside brackets denote absolute addresses. */
6568 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6569 i.types[this_operand] |= JumpAbsolute;
6570
a724f0f4
JB		 6571 /* Unfortunately gas always diverged from MASM in a respect that can't
6572 be easily fixed without risking to break code sequences likely to be
6573 encountered (the testsuite even check for this): MASM doesn't consider
6574 an expression inside brackets unconditionally as a memory reference.
6575 When that is e.g. a constant, an offset expression, or the sum of the
6576 two, this is still taken as a constant load. gas, however, always
6577 treated these as memory references. As a compromise, we'll try to make
6578 offset expressions inside brackets work the MASM way (since that's
6579 less likely to be found in real world code), but make constants alone
6580 continue to work the traditional gas way. In either case, issue a
6581 warning. */
6582 intel_parser.op_modifier &= ~was_offset;
64a0c779 6583 }
a724f0f4 6584 else
64e74474 6585 strcat (intel_parser.disp, "[");
a724f0f4
JB		 6586
6587 /* Add a '+' to the displacement string if necessary. */
6588 if (*intel_parser.disp != '\0'
6589 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6590 strcat (intel_parser.disp, "+");
64a0c779 6591
a724f0f4
JB		 6592 if (intel_expr ()
6593 && (len = intel_parser.op_string - start - 1,
6594 intel_match_token (']')))
64a0c779 6595 {
a724f0f4
JB		 6596 /* Preserve brackets when the operand is an offset expression. */
6597 if (intel_parser.in_offset)
6598 strcat (intel_parser.disp, "]");
6599 else
6600 {
6601 --intel_parser.in_bracket;
6602 if (i.base_reg || i.index_reg)
6603 intel_parser.is_mem = 1;
6604 if (!intel_parser.is_mem)
6605 {
6606 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6607 /* Defer the warning until all of the operand was parsed. */
6608 intel_parser.is_mem = -1;
6609 else if (!quiet_warnings)
6610 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6611 }
6612 }
6613 intel_parser.op_modifier |= was_offset;
64a0c779 6614
a724f0f4 6615 return 1;
64a0c779 6616 }
a724f0f4 6617 return 0;
64a0c779
DN		 6618}
6619
6620/* e10 e11 e10'
6621
6622 e10' [ expr ] e10'
b77a7acd 6623 | Empty */
64a0c779
DN		 6624static int
6625intel_e10 ()
6626{
a724f0f4
JB		 6627 if (!intel_e11 ())
6628 return 0;
64a0c779 6629
a724f0f4 6630 while (cur_token.code == '[')
64a0c779 6631 {
a724f0f4 6632 if (!intel_bracket_expr ())
21d6c4af 6633 return 0;
64a0c779
DN		 6634 }
6635
a724f0f4 6636 return 1;
64a0c779
DN		 6637}
6638
64a0c779 6639/* e11 ( expr )
b77a7acd 6640 | [ expr ]
64a0c779
DN		 6641 | BYTE
6642 | WORD
6643 | DWORD
9306ca4a 6644 | FWORD
64a0c779 6645 | QWORD
9306ca4a
JB		 6646 | TBYTE
6647 | OWORD
6648 | XMMWORD
4a1805b1 6649 | $
64a0c779
DN		 6650 | .
6651 | register
6652 | id
6653 | constant */
6654static int
6655intel_e11 ()
6656{
a724f0f4 6657 switch (cur_token.code)
64a0c779 6658 {
a724f0f4
JB		 6659 /* e11 ( expr ) */
6660 case '(':
64a0c779
DN		 6661 intel_match_token ('(');
6662 strcat (intel_parser.disp, "(");
6663
6664 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6665 {
6666 strcat (intel_parser.disp, ")");
6667 return 1;
6668 }
a724f0f4 6669 return 0;
4a1805b1 6670
a724f0f4
JB		 6671 /* e11 [ expr ] */
6672 case '[':
a724f0f4 6673 return intel_bracket_expr ();
64a0c779 6674
a724f0f4
JB		 6675 /* e11 $
6676 | . */
6677 case '.':
64a0c779
DN		 6678 strcat (intel_parser.disp, cur_token.str);
6679 intel_match_token (cur_token.code);
21d6c4af
DN		 6680
6681 /* Mark as a memory operand only if it's not already known to be an
6682 offset expression. */
a724f0f4 6683 if (!intel_parser.in_offset)
21d6c4af 6684 intel_parser.is_mem = 1;
64a0c779
DN		 6685
6686 return 1;
64a0c779 6687
a724f0f4
JB		 6688 /* e11 register */
6689 case T_REG:
6690 {
6691 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6692
a724f0f4 6693 intel_match_token (T_REG);
64a0c779 6694
a724f0f4
JB		 6695 /* Check for segment change. */
6696 if (cur_token.code == ':')
6697 {
6698 if (!(reg->reg_type & (SReg2 | SReg3)))
6699 {
6700 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6701 return 0;
6702 }
6703 else if (i.seg[i.mem_operands])
6704 as_warn (_("Extra segment override ignored"));
6705 else
6706 {
6707 if (!intel_parser.in_offset)
6708 intel_parser.is_mem = 1;
6709 switch (reg->reg_num)
6710 {
6711 case 0:
6712 i.seg[i.mem_operands] = &es;
6713 break;
6714 case 1:
6715 i.seg[i.mem_operands] = &cs;
6716 break;
6717 case 2:
6718 i.seg[i.mem_operands] = &ss;
6719 break;
6720 case 3:
6721 i.seg[i.mem_operands] = &ds;
6722 break;
6723 case 4:
6724 i.seg[i.mem_operands] = &fs;
6725 break;
6726 case 5:
6727 i.seg[i.mem_operands] = &gs;
6728 break;
6729 }
6730 }
6731 }
64a0c779 6732
a724f0f4
JB		 6733 /* Not a segment register. Check for register scaling. */
6734 else if (cur_token.code == '*')
6735 {
6736 if (!intel_parser.in_bracket)
6737 {
6738 as_bad (_("Register scaling only allowed in memory operands"));
6739 return 0;
6740 }
64a0c779 6741
a724f0f4
JB		 6742 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6743 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6744 else if (i.index_reg)
6745 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6746
a724f0f4
JB		 6747 /* What follows must be a valid scale. */
6748 intel_match_token ('*');
6749 i.index_reg = reg;
6750 i.types[this_operand] |= BaseIndex;
64a0c779 6751
a724f0f4
JB		 6752 /* Set the scale after setting the register (otherwise,
6753 i386_scale will complain) */
6754 if (cur_token.code == '+' || cur_token.code == '-')
6755 {
6756 char *str, sign = cur_token.code;
6757 intel_match_token (cur_token.code);
6758 if (cur_token.code != T_CONST)
6759 {
6760 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6761 cur_token.str);
6762 return 0;
6763 }
6764 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6765 strcpy (str + 1, cur_token.str);
6766 *str = sign;
6767 if (!i386_scale (str))
6768 return 0;
6769 free (str);
6770 }
6771 else if (!i386_scale (cur_token.str))
64a0c779 6772 return 0;
a724f0f4
JB		 6773 intel_match_token (cur_token.code);
6774 }
64a0c779 6775
a724f0f4
JB		 6776 /* No scaling. If this is a memory operand, the register is either a
6777 base register (first occurrence) or an index register (second
6778 occurrence). */
7b0441f6 6779 else if (intel_parser.in_bracket)
a724f0f4 6780 {
64a0c779 6781
a724f0f4
JB		 6782 if (!i.base_reg)
6783 i.base_reg = reg;
6784 else if (!i.index_reg)
6785 i.index_reg = reg;
6786 else
6787 {
6788 as_bad (_("Too many register references in memory operand"));
6789 return 0;
6790 }
64a0c779 6791
a724f0f4
JB		 6792 i.types[this_operand] |= BaseIndex;
6793 }
4a1805b1 6794
4d1bb795
JB		 6795 /* It's neither base nor index. */
6796 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 6797 {
6798 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6799 i.op[this_operand].regs = reg;
6800 i.reg_operands++;
6801 }
6802 else
6803 {
6804 as_bad (_("Invalid use of register"));
6805 return 0;
6806 }
64a0c779 6807
a724f0f4
JB		 6808 /* Since registers are not part of the displacement string (except
6809 when we're parsing offset operands), we may need to remove any
6810 preceding '+' from the displacement string. */
6811 if (*intel_parser.disp != '\0'
6812 && !intel_parser.in_offset)
6813 {
6814 char *s = intel_parser.disp;
6815 s += strlen (s) - 1;
6816 if (*s == '+')
6817 *s = '\0';
6818 }
4a1805b1 6819
a724f0f4
JB		 6820 return 1;
6821 }
6822
6823 /* e11 BYTE
6824 | WORD
6825 | DWORD
6826 | FWORD
6827 | QWORD
6828 | TBYTE
6829 | OWORD
6830 | XMMWORD */
6831 case T_BYTE:
6832 case T_WORD:
6833 case T_DWORD:
6834 case T_FWORD:
6835 case T_QWORD:
6836 case T_TBYTE:
6837 case T_XMMWORD:
6838 intel_match_token (cur_token.code);
64a0c779 6839
a724f0f4
JB		 6840 if (cur_token.code == T_PTR)
6841 return 1;
6842
6843 /* It must have been an identifier. */
6844 intel_putback_token ();
6845 cur_token.code = T_ID;
6846 /* FALLTHRU */
6847
6848 /* e11 id
6849 | constant */
6850 case T_ID:
6851 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6852 {
6853 symbolS *symbolP;
6854
a724f0f4
JB		 6855 /* The identifier represents a memory reference only if it's not
6856 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6857 symbolP = symbol_find(cur_token.str);
6858 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6859 intel_parser.is_mem = 1;
6860 }
a724f0f4 6861 /* FALLTHRU */
64a0c779 6862
a724f0f4
JB		 6863 case T_CONST:
6864 case '-':
6865 case '+':
6866 {
6867 char *save_str, sign = 0;
64a0c779 6868
a724f0f4
JB		 6869 /* Allow constants that start with `+' or `-'. */
6870 if (cur_token.code == '-' || cur_token.code == '+')
6871 {
6872 sign = cur_token.code;
6873 intel_match_token (cur_token.code);
6874 if (cur_token.code != T_CONST)
6875 {
6876 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6877 cur_token.str);
6878 return 0;
6879 }
6880 }
64a0c779 6881
a724f0f4
JB		 6882 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6883 strcpy (save_str + !!sign, cur_token.str);
6884 if (sign)
6885 *save_str = sign;
64a0c779 6886
a724f0f4
JB		 6887 /* Get the next token to check for register scaling. */
6888 intel_match_token (cur_token.code);
64a0c779 6889
a724f0f4
JB		 6890 /* Check if this constant is a scaling factor for an index register. */
6891 if (cur_token.code == '*')
6892 {
6893 if (intel_match_token ('*') && cur_token.code == T_REG)
6894 {
6895 const reg_entry *reg = cur_token.reg;
6896
6897 if (!intel_parser.in_bracket)
6898 {
6899 as_bad (_("Register scaling only allowed in memory operands"));
6900 return 0;
6901 }
6902
6903 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6904 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6905 else if (i.index_reg)
6906 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6907
6908 /* The constant is followed by `* reg', so it must be
6909 a valid scale. */
6910 i.index_reg = reg;
6911 i.types[this_operand] |= BaseIndex;
6912
6913 /* Set the scale after setting the register (otherwise,
6914 i386_scale will complain) */
6915 if (!i386_scale (save_str))
64a0c779 6916 return 0;
a724f0f4
JB		 6917 intel_match_token (T_REG);
6918
6919 /* Since registers are not part of the displacement
6920 string, we may need to remove any preceding '+' from
6921 the displacement string. */
6922 if (*intel_parser.disp != '\0')
6923 {
6924 char *s = intel_parser.disp;
6925 s += strlen (s) - 1;
6926 if (*s == '+')
6927 *s = '\0';
6928 }
6929
6930 free (save_str);
6931
6932 return 1;
6933 }
64a0c779 6934
a724f0f4
JB		 6935 /* The constant was not used for register scaling. Since we have
6936 already consumed the token following `*' we now need to put it
6937 back in the stream. */
64a0c779 6938 intel_putback_token ();
a724f0f4 6939 }
64a0c779 6940
a724f0f4
JB		 6941 /* Add the constant to the displacement string. */
6942 strcat (intel_parser.disp, save_str);
6943 free (save_str);
64a0c779 6944
a724f0f4
JB		 6945 return 1;
6946 }
64a0c779
DN		 6947 }
6948
64a0c779
DN		 6949 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6950 return 0;
6951}
6952
64a0c779
DN		 6953/* Match the given token against cur_token. If they match, read the next
6954 token from the operand string. */
6955static int
6956intel_match_token (code)
e5cb08ac 6957 int code;
64a0c779
DN		 6958{
6959 if (cur_token.code == code)
6960 {
6961 intel_get_token ();
6962 return 1;
6963 }
6964 else
6965 {
0477af35 6966 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6967 return 0;
6968 }
6969}
6970
64a0c779
DN		 6971/* Read a new token from intel_parser.op_string and store it in cur_token. */
6972static void
6973intel_get_token ()
6974{
6975 char *end_op;
6976 const reg_entry *reg;
6977 struct intel_token new_token;
6978
6979 new_token.code = T_NIL;
6980 new_token.reg = NULL;
6981 new_token.str = NULL;
6982
4a1805b1 6983 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6984 cur_token to prev_token. */
6985 if (prev_token.str)
6986 free (prev_token.str);
6987
6988 prev_token = cur_token;
6989
6990 /* Skip whitespace. */
6991 while (is_space_char (*intel_parser.op_string))
6992 intel_parser.op_string++;
6993
6994 /* Return an empty token if we find nothing else on the line. */
6995 if (*intel_parser.op_string == '\0')
6996 {
6997 cur_token = new_token;
6998 return;
6999 }
7000
7001 /* The new token cannot be larger than the remainder of the operand
7002 string. */
a724f0f4 7003 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7004 new_token.str[0] = '\0';
7005
7006 if (strchr ("0123456789", *intel_parser.op_string))
7007 {
7008 char *p = new_token.str;
7009 char *q = intel_parser.op_string;
7010 new_token.code = T_CONST;
7011
7012 /* Allow any kind of identifier char to encompass floating point and
7013 hexadecimal numbers. */
7014 while (is_identifier_char (*q))
7015 *p++ = *q++;
7016 *p = '\0';
7017
7018 /* Recognize special symbol names [0-9][bf]. */
7019 if (strlen (intel_parser.op_string) == 2
4a1805b1 7020 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7021 || intel_parser.op_string[1] == 'f'))
7022 new_token.code = T_ID;
7023 }
7024
4d1bb795 7025 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7026 {
4d1bb795
JB		 7027 size_t len = end_op - intel_parser.op_string;
7028
64a0c779
DN		 7029 new_token.code = T_REG;
7030 new_token.reg = reg;
7031
4d1bb795
JB		 7032 memcpy (new_token.str, intel_parser.op_string, len);
7033 new_token.str[len] = '\0';
64a0c779
DN		 7034 }
7035
7036 else if (is_identifier_char (*intel_parser.op_string))
7037 {
7038 char *p = new_token.str;
7039 char *q = intel_parser.op_string;
7040
7041 /* A '.' or '$' followed by an identifier char is an identifier.
7042 Otherwise, it's operator '.' followed by an expression. */
7043 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7044 {
9306ca4a
JB		 7045 new_token.code = '.';
7046 new_token.str[0] = '.';
64a0c779
DN		 7047 new_token.str[1] = '\0';
7048 }
7049 else
7050 {
7051 while (is_identifier_char (*q) || *q == '@')
7052 *p++ = *q++;
7053 *p = '\0';
7054
9306ca4a
JB		 7055 if (strcasecmp (new_token.str, "NOT") == 0)
7056 new_token.code = '~';
7057
7058 else if (strcasecmp (new_token.str, "MOD") == 0)
7059 new_token.code = '%';
7060
7061 else if (strcasecmp (new_token.str, "AND") == 0)
7062 new_token.code = '&';
7063
7064 else if (strcasecmp (new_token.str, "OR") == 0)
7065 new_token.code = '|';
7066
7067 else if (strcasecmp (new_token.str, "XOR") == 0)
7068 new_token.code = '^';
7069
7070 else if (strcasecmp (new_token.str, "SHL") == 0)
7071 new_token.code = T_SHL;
7072
7073 else if (strcasecmp (new_token.str, "SHR") == 0)
7074 new_token.code = T_SHR;
7075
7076 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7077 new_token.code = T_BYTE;
7078
7079 else if (strcasecmp (new_token.str, "WORD") == 0)
7080 new_token.code = T_WORD;
7081
7082 else if (strcasecmp (new_token.str, "DWORD") == 0)
7083 new_token.code = T_DWORD;
7084
9306ca4a
JB		 7085 else if (strcasecmp (new_token.str, "FWORD") == 0)
7086 new_token.code = T_FWORD;
7087
64a0c779
DN		 7088 else if (strcasecmp (new_token.str, "QWORD") == 0)
7089 new_token.code = T_QWORD;
7090
9306ca4a
JB		 7091 else if (strcasecmp (new_token.str, "TBYTE") == 0
7092 /* XXX remove (gcc still uses it) */
7093 || strcasecmp (new_token.str, "XWORD") == 0)
7094 new_token.code = T_TBYTE;
7095
7096 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7097 || strcasecmp (new_token.str, "OWORD") == 0)
7098 new_token.code = T_XMMWORD;
64a0c779
DN		 7099
7100 else if (strcasecmp (new_token.str, "PTR") == 0)
7101 new_token.code = T_PTR;
7102
7103 else if (strcasecmp (new_token.str, "SHORT") == 0)
7104 new_token.code = T_SHORT;
7105
7106 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7107 {
7108 new_token.code = T_OFFSET;
7109
7110 /* ??? This is not mentioned in the MASM grammar but gcc
7111 makes use of it with -mintel-syntax. OFFSET may be
7112 followed by FLAT: */
7113 if (strncasecmp (q, " FLAT:", 6) == 0)
7114 strcat (new_token.str, " FLAT:");
7115 }
7116
7117 /* ??? This is not mentioned in the MASM grammar. */
7118 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7119 {
7120 new_token.code = T_OFFSET;
7121 if (*q == ':')
7122 strcat (new_token.str, ":");
7123 else
7124 as_bad (_("`:' expected"));
7125 }
64a0c779
DN		 7126
7127 else
7128 new_token.code = T_ID;
7129 }
7130 }
7131
9306ca4a
JB		 7132 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7133 {
7134 new_token.code = *intel_parser.op_string;
7135 new_token.str[0] = *intel_parser.op_string;
7136 new_token.str[1] = '\0';
7137 }
7138
7139 else if (strchr ("<>", *intel_parser.op_string)
7140 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7141 {
7142 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7143 new_token.str[0] = *intel_parser.op_string;
7144 new_token.str[1] = *intel_parser.op_string;
7145 new_token.str[2] = '\0';
7146 }
7147
64a0c779 7148 else
0477af35 7149 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7150
7151 intel_parser.op_string += strlen (new_token.str);
7152 cur_token = new_token;
7153}
7154
64a0c779
DN		 7155/* Put cur_token back into the token stream and make cur_token point to
7156 prev_token. */
7157static void
7158intel_putback_token ()
7159{
a724f0f4
JB		 7160 if (cur_token.code != T_NIL)
7161 {
7162 intel_parser.op_string -= strlen (cur_token.str);
7163 free (cur_token.str);
7164 }
64a0c779 7165 cur_token = prev_token;
4a1805b1 7166
64a0c779
DN		 7167 /* Forget prev_token. */
7168 prev_token.code = T_NIL;
7169 prev_token.reg = NULL;
7170 prev_token.str = NULL;
7171}
54cfded0 7172
a4447b93 7173int
54cfded0
AM		 7174tc_x86_regname_to_dw2regnum (const char *regname)
7175{
7176 unsigned int regnum;
7177 unsigned int regnames_count;
089dfecd 7178 static const char *const regnames_32[] =
54cfded0 7179 {
a4447b93
RH		 7180 "eax", "ecx", "edx", "ebx",
7181 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7182 "eip", "eflags", NULL,
7183 "st0", "st1", "st2", "st3",
7184 "st4", "st5", "st6", "st7",
7185 NULL, NULL,
7186 "xmm0", "xmm1", "xmm2", "xmm3",
7187 "xmm4", "xmm5", "xmm6", "xmm7",
7188 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7189 "mm4", "mm5", "mm6", "mm7",
7190 "fcw", "fsw", "mxcsr",
7191 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7192 "tr", "ldtr"
54cfded0 7193 };
089dfecd 7194 static const char *const regnames_64[] =
54cfded0 7195 {
089dfecd
JB		 7196 "rax", "rdx", "rcx", "rbx",
7197 "rsi", "rdi", "rbp", "rsp",
7198 "r8", "r9", "r10", "r11",
54cfded0 7199 "r12", "r13", "r14", "r15",
089dfecd
JB		 7200 "rip",
7201 "xmm0", "xmm1", "xmm2", "xmm3",
7202 "xmm4", "xmm5", "xmm6", "xmm7",
7203 "xmm8", "xmm9", "xmm10", "xmm11",
7204 "xmm12", "xmm13", "xmm14", "xmm15",
7205 "st0", "st1", "st2", "st3",
7206 "st4", "st5", "st6", "st7",
7207 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7208 "mm4", "mm5", "mm6", "mm7",
7209 "rflags",
7210 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7211 "fs.base", "gs.base", NULL, NULL,
7212 "tr", "ldtr",
7213 "mxcsr", "fcw", "fsw"
54cfded0 7214 };
089dfecd 7215 const char *const *regnames;
54cfded0
AM		 7216
7217 if (flag_code == CODE_64BIT)
7218 {
7219 regnames = regnames_64;
0cea6190 7220 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7221 }
7222 else
7223 {
7224 regnames = regnames_32;
0cea6190 7225 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7226 }
7227
7228 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7229 if (regnames[regnum] != NULL
7230 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7231 return regnum;
7232
54cfded0
AM		 7233 return -1;
7234}
7235
7236void
7237tc_x86_frame_initial_instructions (void)
7238{
a4447b93
RH		 7239 static unsigned int sp_regno;
7240
7241 if (!sp_regno)
7242 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7243 ? "rsp" : "esp");
7244
7245 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7246 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7247}
d2b2c203
DJ		 7248
7249int
7250i386_elf_section_type (const char *str, size_t len)
7251{
7252 if (flag_code == CODE_64BIT
7253 && len == sizeof ("unwind") - 1
7254 && strncmp (str, "unwind", 6) == 0)
7255 return SHT_X86_64_UNWIND;
7256
7257 return -1;
7258}
bb41ade5
AM		 7259
7260#ifdef TE_PE
7261void
7262tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7263{
7264 expressionS expr;
7265
7266 expr.X_op = O_secrel;
7267 expr.X_add_symbol = symbol;
7268 expr.X_add_number = 0;
7269 emit_expr (&expr, size);
7270}
7271#endif
3b22753a
L		 7272
7273#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7274/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7275
7276int
7277x86_64_section_letter (int letter, char **ptr_msg)
7278{
7279 if (flag_code == CODE_64BIT)
7280 {
7281 if (letter == 'l')
7282 return SHF_X86_64_LARGE;
7283
7284 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7285 }
3b22753a 7286 else
64e74474 7287 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7288 return -1;
7289}
7290
7291int
7292x86_64_section_word (char *str, size_t len)
7293{
7294 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7295 return SHF_X86_64_LARGE;
7296
7297 return -1;
7298}
7299
7300static void
7301handle_large_common (int small ATTRIBUTE_UNUSED)
7302{
7303 if (flag_code != CODE_64BIT)
7304 {
7305 s_comm_internal (0, elf_common_parse);
7306 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7307 }
7308 else
7309 {
7310 static segT lbss_section;
7311 asection *saved_com_section_ptr = elf_com_section_ptr;
7312 asection *saved_bss_section = bss_section;
7313
7314 if (lbss_section == NULL)
7315 {
7316 flagword applicable;
7317 segT seg = now_seg;
7318 subsegT subseg = now_subseg;
7319
7320 /* The .lbss section is for local .largecomm symbols. */
7321 lbss_section = subseg_new (".lbss", 0);
7322 applicable = bfd_applicable_section_flags (stdoutput);
7323 bfd_set_section_flags (stdoutput, lbss_section,
7324 applicable & SEC_ALLOC);
7325 seg_info (lbss_section)->bss = 1;
7326
7327 subseg_set (seg, subseg);
7328 }
7329
7330 elf_com_section_ptr = &_bfd_elf_large_com_section;
7331 bss_section = lbss_section;
7332
7333 s_comm_internal (0, elf_common_parse);
7334
7335 elf_com_section_ptr = saved_com_section_ptr;
7336 bss_section = saved_bss_section;
7337 }
7338}
7339#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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