projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* configure.ac (TOPLEVEL_CONFIGURE_ARGUMENTS): Fix m4 quoting
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
9103f4f4 434 {"i386", PROCESSOR_GENERIC32,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4
L		 501 {".3dnow", PROCESSOR_UNKNOWN,
502 CpuMMX|Cpu3dnow},
503 {".3dnowa", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
505 {".padlock", PROCESSOR_UNKNOWN,
506 CpuPadLock},
507 {".pacifica", PROCESSOR_UNKNOWN,
508 CpuSVME},
509 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 510 CpuSVME},
511 {".sse4a", PROCESSOR_UNKNOWN,
512 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
513 {".abm", PROCESSOR_UNKNOWN,
514 CpuABM}
e413e4e9
AM		 515};
516
29b0f896
AM		 517const pseudo_typeS md_pseudo_table[] =
518{
519#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
520 {"align", s_align_bytes, 0},
521#else
522 {"align", s_align_ptwo, 0},
523#endif
524 {"arch", set_cpu_arch, 0},
525#ifndef I386COFF
526 {"bss", s_bss, 0},
527#endif
528 {"ffloat", float_cons, 'f'},
529 {"dfloat", float_cons, 'd'},
530 {"tfloat", float_cons, 'x'},
531 {"value", cons, 2},
d182319b 532 {"slong", signed_cons, 4},
29b0f896
AM		 533 {"noopt", s_ignore, 0},
534 {"optim", s_ignore, 0},
535 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
536 {"code16", set_code_flag, CODE_16BIT},
537 {"code32", set_code_flag, CODE_32BIT},
538 {"code64", set_code_flag, CODE_64BIT},
539 {"intel_syntax", set_intel_syntax, 1},
540 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 541#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
542 {"largecomm", handle_large_common, 0},
07a53e5c 543#else
e3bb37b5 544 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 545 {"loc", dwarf2_directive_loc, 0},
546 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 547#endif
6482c264
NC		 548#ifdef TE_PE
549 {"secrel32", pe_directive_secrel, 0},
550#endif
29b0f896
AM		 551 {0, 0, 0}
552};
553
554/* For interface with expression (). */
555extern char *input_line_pointer;
556
557/* Hash table for instruction mnemonic lookup. */
558static struct hash_control *op_hash;
559
560/* Hash table for register lookup. */
561static struct hash_control *reg_hash;
562\f
252b5132 563void
e3bb37b5 564i386_align_code (fragS *fragP, int count)
252b5132 565{
ce8a8b2f
AM		 566 /* Various efficient no-op patterns for aligning code labels.
567 Note: Don't try to assemble the instructions in the comments.
568 0L and 0w are not legal. */
252b5132
RH		 569 static const char f32_1[] =
570 {0x90}; /* nop */
571 static const char f32_2[] =
ccc9c027 572 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 573 static const char f32_3[] =
574 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
575 static const char f32_4[] =
576 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
577 static const char f32_5[] =
578 {0x90, /* nop */
579 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
580 static const char f32_6[] =
581 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
582 static const char f32_7[] =
583 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
584 static const char f32_8[] =
585 {0x90, /* nop */
586 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
587 static const char f32_9[] =
588 {0x89,0xf6, /* movl %esi,%esi */
589 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
590 static const char f32_10[] =
591 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
592 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
593 static const char f32_11[] =
594 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_12[] =
597 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
598 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
599 static const char f32_13[] =
600 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_14[] =
603 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
604 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
605 static const char f32_15[] =
606 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
607 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 608 static const char f16_3[] =
609 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 610 static const char f16_4[] =
611 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
612 static const char f16_5[] =
613 {0x90, /* nop */
614 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_6[] =
616 {0x89,0xf6, /* mov %si,%si */
617 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
618 static const char f16_7[] =
619 {0x8d,0x74,0x00, /* lea 0(%si),%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_8[] =
622 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char *const f32_patt[] = {
625 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
626 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
627 };
628 static const char *const f16_patt[] = {
c3332e24 629 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 630 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
631 };
ccc9c027
L		 632 /* nopl (%[re]ax) */
633 static const char alt_3[] =
634 {0x0f,0x1f,0x00};
635 /* nopl 0(%[re]ax) */
636 static const char alt_4[] =
637 {0x0f,0x1f,0x40,0x00};
638 /* nopl 0(%[re]ax,%[re]ax,1) */
639 static const char alt_5[] =
640 {0x0f,0x1f,0x44,0x00,0x00};
641 /* nopw 0(%[re]ax,%[re]ax,1) */
642 static const char alt_6[] =
643 {0x66,0x0f,0x1f,0x44,0x00,0x00};
644 /* nopl 0L(%[re]ax) */
645 static const char alt_7[] =
646 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
647 /* nopl 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_8[] =
649 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw 0L(%[re]ax,%[re]ax,1) */
651 static const char alt_9[] =
652 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
654 static const char alt_10[] =
655 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* data16
657 nopw %cs:0L(%[re]ax,%[re]ax,1) */
658 static const char alt_long_11[] =
659 {0x66,
660 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
661 /* data16
662 data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_12[] =
665 {0x66,
666 0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 data16
671 nopw %cs:0L(%[re]ax,%[re]ax,1) */
672 static const char alt_long_13[] =
673 {0x66,
674 0x66,
675 0x66,
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 /* data16
678 data16
679 data16
680 data16
681 nopw %cs:0L(%[re]ax,%[re]ax,1) */
682 static const char alt_long_14[] =
683 {0x66,
684 0x66,
685 0x66,
686 0x66,
687 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 /* data16
689 data16
690 data16
691 data16
692 data16
693 nopw %cs:0L(%[re]ax,%[re]ax,1) */
694 static const char alt_long_15[] =
695 {0x66,
696 0x66,
697 0x66,
698 0x66,
699 0x66,
700 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
701 /* nopl 0(%[re]ax,%[re]ax,1)
702 nopw 0(%[re]ax,%[re]ax,1) */
703 static const char alt_short_11[] =
704 {0x0f,0x1f,0x44,0x00,0x00,
705 0x66,0x0f,0x1f,0x44,0x00,0x00};
706 /* nopw 0(%[re]ax,%[re]ax,1)
707 nopw 0(%[re]ax,%[re]ax,1) */
708 static const char alt_short_12[] =
709 {0x66,0x0f,0x1f,0x44,0x00,0x00,
710 0x66,0x0f,0x1f,0x44,0x00,0x00};
711 /* nopw 0(%[re]ax,%[re]ax,1)
712 nopl 0L(%[re]ax) */
713 static const char alt_short_13[] =
714 {0x66,0x0f,0x1f,0x44,0x00,0x00,
715 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
716 /* nopl 0L(%[re]ax)
717 nopl 0L(%[re]ax) */
718 static const char alt_short_14[] =
719 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
720 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
721 /* nopl 0L(%[re]ax)
722 nopl 0L(%[re]ax,%[re]ax,1) */
723 static const char alt_short_15[] =
724 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
725 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
726 static const char *const alt_short_patt[] = {
727 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
728 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
729 alt_short_14, alt_short_15
730 };
731 static const char *const alt_long_patt[] = {
732 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
733 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
734 alt_long_14, alt_long_15
735 };
252b5132 736
33fef721
JH		 737 if (count <= 0 || count > 15)
738 return;
3e73aa7c 739
ccc9c027
L		 740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
4eed87de 742
ccc9c027
L		 743 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
744 f32_patt will be used.
4eed87de
AM		 745 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
746 0x66 prefix will be used.
ef05d495 747 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 748 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 749 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 750 and PROCESSOR_GENERIC64, alt_short_patt will be used.
751
752 When -mtune= isn't used, alt_short_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
754
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
757
758 if (flag_code == CODE_16BIT)
759 {
760 memcpy (fragP->fr_literal + fragP->fr_fix,
761 f16_patt[count - 1], count);
762 if (count > 8)
763 /* Adjust jump offset. */
764 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
765 }
766 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 767 {
33fef721
JH		 768 int i;
769 int nnops = (count + 3) / 4;
770 int len = count / nnops;
771 int remains = count - nnops * len;
772 int pos = 0;
773
ccc9c027 774 /* The recommended way to pad 64bit code is to use NOPs preceded
4eed87de 775 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 776 for (i = 0; i < remains; i++)
252b5132 777 {
33fef721
JH		 778 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
779 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
780 pos += len + 1;
781 }
782 for (; i < nnops; i++)
783 {
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
785 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
786 pos += len;
252b5132 787 }
252b5132 788 }
33fef721 789 else
ccc9c027
L		 790 {
791 const char *const *patt = NULL;
792
793 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
794 {
795 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
796 switch (cpu_arch_tune)
797 {
798 case PROCESSOR_UNKNOWN:
799 /* We use cpu_arch_isa_flags to check if we SHOULD
800 optimize for Cpu686. */
801 if ((cpu_arch_isa_flags & Cpu686) != 0)
802 patt = alt_short_patt;
803 else
804 patt = f32_patt;
805 break;
ef05d495 806 case PROCESSOR_CORE2:
ccc9c027
L		 807 patt = alt_long_patt;
808 break;
809 case PROCESSOR_PENTIUMPRO:
810 case PROCESSOR_PENTIUM4:
811 case PROCESSOR_NOCONA:
ef05d495 812 case PROCESSOR_CORE:
ccc9c027
L		 813 case PROCESSOR_K6:
814 case PROCESSOR_ATHLON:
815 case PROCESSOR_K8:
816 case PROCESSOR_GENERIC64:
4eed87de 817 case PROCESSOR_AMDFAM10:
ccc9c027
L		 818 patt = alt_short_patt;
819 break;
820 case PROCESSOR_I486:
821 case PROCESSOR_PENTIUM:
822 case PROCESSOR_GENERIC32:
823 patt = f32_patt;
824 break;
4eed87de 825 }
ccc9c027
L		 826 }
827 else
828 {
829 switch (cpu_arch_tune)
830 {
831 case PROCESSOR_UNKNOWN:
832 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
833 PROCESSOR_UNKNOWN. */
834 abort ();
835 break;
836
837 case PROCESSOR_I486:
838 case PROCESSOR_PENTIUM:
839 case PROCESSOR_PENTIUMPRO:
840 case PROCESSOR_PENTIUM4:
841 case PROCESSOR_NOCONA:
ef05d495 842 case PROCESSOR_CORE:
ccc9c027
L		 843 case PROCESSOR_K6:
844 case PROCESSOR_ATHLON:
845 case PROCESSOR_K8:
4eed87de 846 case PROCESSOR_AMDFAM10:
ccc9c027
L		 847 case PROCESSOR_GENERIC32:
848 /* We use cpu_arch_isa_flags to check if we CAN optimize
849 for Cpu686. */
850 if ((cpu_arch_isa_flags & Cpu686) != 0)
851 patt = alt_short_patt;
852 else
853 patt = f32_patt;
854 break;
ef05d495 855 case PROCESSOR_CORE2:
ccc9c027
L		 856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_long_patt;
858 else
859 patt = f32_patt;
860 break;
861 case PROCESSOR_GENERIC64:
862 patt = alt_short_patt;
863 break;
4eed87de 864 }
ccc9c027
L		 865 }
866
33fef721 867 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 868 patt[count - 1], count);
869 }
33fef721 870 fragP->fr_var = count;
252b5132
RH		 871}
872
252b5132 873static INLINE unsigned int
e3bb37b5 874mode_from_disp_size (unsigned int t)
252b5132 875{
3e73aa7c 876 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 877}
878
879static INLINE int
e3bb37b5 880fits_in_signed_byte (offsetT num)
252b5132
RH		 881{
882 return (num >= -128) && (num <= 127);
47926f60 883}
252b5132
RH		 884
885static INLINE int
e3bb37b5 886fits_in_unsigned_byte (offsetT num)
252b5132
RH		 887{
888 return (num & 0xff) == num;
47926f60 889}
252b5132
RH		 890
891static INLINE int
e3bb37b5 892fits_in_unsigned_word (offsetT num)
252b5132
RH		 893{
894 return (num & 0xffff) == num;
47926f60 895}
252b5132
RH		 896
897static INLINE int
e3bb37b5 898fits_in_signed_word (offsetT num)
252b5132
RH		 899{
900 return (-32768 <= num) && (num <= 32767);
47926f60 901}
2a962e6d 902
3e73aa7c 903static INLINE int
e3bb37b5 904fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 905{
906#ifndef BFD64
907 return 1;
908#else
909 return (!(((offsetT) -1 << 31) & num)
910 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
911#endif
912} /* fits_in_signed_long() */
2a962e6d 913
3e73aa7c 914static INLINE int
e3bb37b5 915fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 916{
917#ifndef BFD64
918 return 1;
919#else
920 return (num & (((offsetT) 2 << 31) - 1)) == num;
921#endif
922} /* fits_in_unsigned_long() */
252b5132 923
1509aa9a 924static unsigned int
e3bb37b5 925smallest_imm_type (offsetT num)
252b5132 926{
d32cad65 927 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 928 {
929 /* This code is disabled on the 486 because all the Imm1 forms
930 in the opcode table are slower on the i486. They're the
931 versions with the implicitly specified single-position
932 displacement, which has another syntax if you really want to
933 use that form. */
934 if (num == 1)
3e73aa7c 935 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 936 }
252b5132 937 return (fits_in_signed_byte (num)
3e73aa7c 938 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 939 : fits_in_unsigned_byte (num)
3e73aa7c 940 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 941 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 942 ? (Imm16 | Imm32 | Imm32S | Imm64)
943 : fits_in_signed_long (num)
944 ? (Imm32 | Imm32S | Imm64)
945 : fits_in_unsigned_long (num)
946 ? (Imm32 | Imm64)
947 : Imm64);
47926f60 948}
252b5132 949
847f7ad4 950static offsetT
e3bb37b5 951offset_in_range (offsetT val, int size)
847f7ad4 952{
508866be 953 addressT mask;
ba2adb93 954
847f7ad4
AM		 955 switch (size)
956 {
508866be
L		 957 case 1: mask = ((addressT) 1 << 8) - 1; break;
958 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 959 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 960#ifdef BFD64
961 case 8: mask = ((addressT) 2 << 63) - 1; break;
962#endif
47926f60 963 default: abort ();
847f7ad4
AM		 964 }
965
ba2adb93 966 /* If BFD64, sign extend val. */
3e73aa7c
JH		 967 if (!use_rela_relocations)
968 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
969 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 970
47926f60 971 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 972 {
973 char buf1[40], buf2[40];
974
975 sprint_value (buf1, val);
976 sprint_value (buf2, val & mask);
977 as_warn (_("%s shortened to %s"), buf1, buf2);
978 }
979 return val & mask;
980}
981
252b5132
RH		 982/* Returns 0 if attempting to add a prefix where one from the same
983 class already exists, 1 if non rep/repne added, 2 if rep/repne
984 added. */
985static int
e3bb37b5 986add_prefix (unsigned int prefix)
252b5132
RH		 987{
988 int ret = 1;
b1905489 989 unsigned int q;
252b5132 990
29b0f896
AM		 991 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
992 && flag_code == CODE_64BIT)
b1905489
JB		 993 {
994 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
995 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
996 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
997 ret = 0;
998 q = REX_PREFIX;
999 }
3e73aa7c 1000 else
b1905489
JB		 1001 {
1002 switch (prefix)
1003 {
1004 default:
1005 abort ();
1006
1007 case CS_PREFIX_OPCODE:
1008 case DS_PREFIX_OPCODE:
1009 case ES_PREFIX_OPCODE:
1010 case FS_PREFIX_OPCODE:
1011 case GS_PREFIX_OPCODE:
1012 case SS_PREFIX_OPCODE:
1013 q = SEG_PREFIX;
1014 break;
1015
1016 case REPNE_PREFIX_OPCODE:
1017 case REPE_PREFIX_OPCODE:
1018 ret = 2;
1019 /* fall thru */
1020 case LOCK_PREFIX_OPCODE:
1021 q = LOCKREP_PREFIX;
1022 break;
1023
1024 case FWAIT_OPCODE:
1025 q = WAIT_PREFIX;
1026 break;
1027
1028 case ADDR_PREFIX_OPCODE:
1029 q = ADDR_PREFIX;
1030 break;
1031
1032 case DATA_PREFIX_OPCODE:
1033 q = DATA_PREFIX;
1034 break;
1035 }
1036 if (i.prefix[q] != 0)
1037 ret = 0;
1038 }
252b5132 1039
b1905489 1040 if (ret)
252b5132 1041 {
b1905489
JB		 1042 if (!i.prefix[q])
1043 ++i.prefixes;
1044 i.prefix[q] |= prefix;
252b5132 1045 }
b1905489
JB		 1046 else
1047 as_bad (_("same type of prefix used twice"));
252b5132 1048
252b5132
RH		 1049 return ret;
1050}
1051
1052static void
e3bb37b5 1053set_code_flag (int value)
eecb386c 1054{
3e73aa7c
JH		 1055 flag_code = value;
1056 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1057 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1058 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1059 {
1060 as_bad (_("64bit mode not supported on this CPU."));
1061 }
1062 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1063 {
1064 as_bad (_("32bit mode not supported on this CPU."));
1065 }
eecb386c
AM		 1066 stackop_size = '\0';
1067}
1068
1069static void
e3bb37b5 1070set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1071{
3e73aa7c
JH		 1072 flag_code = new_code_flag;
1073 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1074 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1075 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1076}
1077
1078static void
e3bb37b5 1079set_intel_syntax (int syntax_flag)
252b5132
RH		 1080{
1081 /* Find out if register prefixing is specified. */
1082 int ask_naked_reg = 0;
1083
1084 SKIP_WHITESPACE ();
29b0f896 1085 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1086 {
1087 char *string = input_line_pointer;
1088 int e = get_symbol_end ();
1089
47926f60 1090 if (strcmp (string, "prefix") == 0)
252b5132 1091 ask_naked_reg = 1;
47926f60 1092 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1093 ask_naked_reg = -1;
1094 else
d0b47220 1095 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1096 *input_line_pointer = e;
1097 }
1098 demand_empty_rest_of_line ();
c3332e24 1099
252b5132
RH		 1100 intel_syntax = syntax_flag;
1101
1102 if (ask_naked_reg == 0)
f86103b7
AM		 1103 allow_naked_reg = (intel_syntax
1104 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1105 else
1106 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1107
e4a3b5a4 1108 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1109 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1110 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1111}
1112
e413e4e9 1113static void
e3bb37b5 1114set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1115{
47926f60 1116 SKIP_WHITESPACE ();
e413e4e9 1117
29b0f896 1118 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1119 {
1120 char *string = input_line_pointer;
1121 int e = get_symbol_end ();
9103f4f4 1122 unsigned int i;
e413e4e9 1123
9103f4f4 1124 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1125 {
1126 if (strcmp (string, cpu_arch[i].name) == 0)
1127 {
5c6af06e
JB		 1128 if (*string != '.')
1129 {
1130 cpu_arch_name = cpu_arch[i].name;
1131 cpu_sub_arch_name = NULL;
1132 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1133 | (flag_code == CODE_64BIT
1134 ? Cpu64 : CpuNo64));
ccc9c027 1135 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1136 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1137 if (!cpu_arch_tune_set)
1138 {
1139 cpu_arch_tune = cpu_arch_isa;
1140 cpu_arch_tune_flags = cpu_arch_isa_flags;
1141 }
5c6af06e
JB		 1142 break;
1143 }
1144 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1145 {
1146 cpu_sub_arch_name = cpu_arch[i].name;
1147 cpu_arch_flags |= cpu_arch[i].flags;
1148 }
1149 *input_line_pointer = e;
1150 demand_empty_rest_of_line ();
1151 return;
e413e4e9
AM		 1152 }
1153 }
9103f4f4 1154 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1155 as_bad (_("no such architecture: `%s'"), string);
1156
1157 *input_line_pointer = e;
1158 }
1159 else
1160 as_bad (_("missing cpu architecture"));
1161
fddf5b5b
AM		 1162 no_cond_jump_promotion = 0;
1163 if (*input_line_pointer == ','
29b0f896 1164 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1165 {
1166 char *string = ++input_line_pointer;
1167 int e = get_symbol_end ();
1168
1169 if (strcmp (string, "nojumps") == 0)
1170 no_cond_jump_promotion = 1;
1171 else if (strcmp (string, "jumps") == 0)
1172 ;
1173 else
1174 as_bad (_("no such architecture modifier: `%s'"), string);
1175
1176 *input_line_pointer = e;
1177 }
1178
e413e4e9
AM		 1179 demand_empty_rest_of_line ();
1180}
1181
b9d79e03
JH		 1182unsigned long
1183i386_mach ()
1184{
1185 if (!strcmp (default_arch, "x86_64"))
1186 return bfd_mach_x86_64;
1187 else if (!strcmp (default_arch, "i386"))
1188 return bfd_mach_i386_i386;
1189 else
1190 as_fatal (_("Unknown architecture"));
1191}
b9d79e03 1192\f
252b5132
RH		 1193void
1194md_begin ()
1195{
1196 const char *hash_err;
1197
47926f60 1198 /* Initialize op_hash hash table. */
252b5132
RH		 1199 op_hash = hash_new ();
1200
1201 {
29b0f896
AM		 1202 const template *optab;
1203 templates *core_optab;
252b5132 1204
47926f60
KH		 1205 /* Setup for loop. */
1206 optab = i386_optab;
252b5132
RH		 1207 core_optab = (templates *) xmalloc (sizeof (templates));
1208 core_optab->start = optab;
1209
1210 while (1)
1211 {
1212 ++optab;
1213 if (optab->name == NULL
1214 || strcmp (optab->name, (optab - 1)->name) != 0)
1215 {
1216 /* different name --> ship out current template list;
47926f60 1217 add to hash table; & begin anew. */
252b5132
RH		 1218 core_optab->end = optab;
1219 hash_err = hash_insert (op_hash,
1220 (optab - 1)->name,
1221 (PTR) core_optab);
1222 if (hash_err)
1223 {
252b5132
RH		 1224 as_fatal (_("Internal Error: Can't hash %s: %s"),
1225 (optab - 1)->name,
1226 hash_err);
1227 }
1228 if (optab->name == NULL)
1229 break;
1230 core_optab = (templates *) xmalloc (sizeof (templates));
1231 core_optab->start = optab;
1232 }
1233 }
1234 }
1235
47926f60 1236 /* Initialize reg_hash hash table. */
252b5132
RH		 1237 reg_hash = hash_new ();
1238 {
29b0f896 1239 const reg_entry *regtab;
c3fe08fa 1240 unsigned int regtab_size = i386_regtab_size;
252b5132 1241
c3fe08fa 1242 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1243 {
1244 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1245 if (hash_err)
3e73aa7c
JH		 1246 as_fatal (_("Internal Error: Can't hash %s: %s"),
1247 regtab->reg_name,
1248 hash_err);
252b5132
RH		 1249 }
1250 }
1251
47926f60 1252 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1253 {
29b0f896
AM		 1254 int c;
1255 char *p;
252b5132
RH		 1256
1257 for (c = 0; c < 256; c++)
1258 {
3882b010 1259 if (ISDIGIT (c))
252b5132
RH		 1260 {
1261 digit_chars[c] = c;
1262 mnemonic_chars[c] = c;
1263 register_chars[c] = c;
1264 operand_chars[c] = c;
1265 }
3882b010 1266 else if (ISLOWER (c))
252b5132
RH		 1267 {
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1271 }
3882b010 1272 else if (ISUPPER (c))
252b5132 1273 {
3882b010 1274 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1275 register_chars[c] = mnemonic_chars[c];
1276 operand_chars[c] = c;
1277 }
1278
3882b010 1279 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1280 identifier_chars[c] = c;
1281 else if (c >= 128)
1282 {
1283 identifier_chars[c] = c;
1284 operand_chars[c] = c;
1285 }
1286 }
1287
1288#ifdef LEX_AT
1289 identifier_chars['@'] = '@';
32137342
NC		 1290#endif
1291#ifdef LEX_QM
1292 identifier_chars['?'] = '?';
1293 operand_chars['?'] = '?';
252b5132 1294#endif
252b5132 1295 digit_chars['-'] = '-';
791fe849 1296 mnemonic_chars['-'] = '-';
252b5132
RH		 1297 identifier_chars['_'] = '_';
1298 identifier_chars['.'] = '.';
1299
1300 for (p = operand_special_chars; *p != '\0'; p++)
1301 operand_chars[(unsigned char) *p] = *p;
1302 }
1303
1304#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1305 if (IS_ELF)
252b5132
RH		 1306 {
1307 record_alignment (text_section, 2);
1308 record_alignment (data_section, 2);
1309 record_alignment (bss_section, 2);
1310 }
1311#endif
a4447b93
RH		 1312
1313 if (flag_code == CODE_64BIT)
1314 {
1315 x86_dwarf2_return_column = 16;
1316 x86_cie_data_alignment = -8;
1317 }
1318 else
1319 {
1320 x86_dwarf2_return_column = 8;
1321 x86_cie_data_alignment = -4;
1322 }
252b5132
RH		 1323}
1324
1325void
e3bb37b5 1326i386_print_statistics (FILE *file)
252b5132
RH		 1327{
1328 hash_print_statistics (file, "i386 opcode", op_hash);
1329 hash_print_statistics (file, "i386 register", reg_hash);
1330}
1331\f
252b5132
RH		 1332#ifdef DEBUG386
1333
ce8a8b2f 1334/* Debugging routines for md_assemble. */
e3bb37b5
L		 1335static void pte (template *);
1336static void pt (unsigned int);
1337static void pe (expressionS *);
1338static void ps (symbolS *);
252b5132
RH		 1339
1340static void
e3bb37b5 1341pi (char *line, i386_insn *x)
252b5132 1342{
09f131f2 1343 unsigned int i;
252b5132
RH		 1344
1345 fprintf (stdout, "%s: template ", line);
1346 pte (&x->tm);
09f131f2
JH		 1347 fprintf (stdout, " address: base %s index %s scale %x\n",
1348 x->base_reg ? x->base_reg->reg_name : "none",
1349 x->index_reg ? x->index_reg->reg_name : "none",
1350 x->log2_scale_factor);
1351 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1352 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1353 fprintf (stdout, " sib: base %x index %x scale %x\n",
1354 x->sib.base, x->sib.index, x->sib.scale);
1355 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1356 (x->rex & REX_MODE64) != 0,
1357 (x->rex & REX_EXTX) != 0,
1358 (x->rex & REX_EXTY) != 0,
1359 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1360 for (i = 0; i < x->operands; i++)
1361 {
1362 fprintf (stdout, " #%d: ", i + 1);
1363 pt (x->types[i]);
1364 fprintf (stdout, "\n");
1365 if (x->types[i]
3f4438ab 1366 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1367 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1368 if (x->types[i] & Imm)
520dc8e8 1369 pe (x->op[i].imms);
252b5132 1370 if (x->types[i] & Disp)
520dc8e8 1371 pe (x->op[i].disps);
252b5132
RH		 1372 }
1373}
1374
1375static void
e3bb37b5 1376pte (template *t)
252b5132 1377{
09f131f2 1378 unsigned int i;
252b5132 1379 fprintf (stdout, " %d operands ", t->operands);
47926f60 1380 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1381 if (t->extension_opcode != None)
1382 fprintf (stdout, "ext %x ", t->extension_opcode);
1383 if (t->opcode_modifier & D)
1384 fprintf (stdout, "D");
1385 if (t->opcode_modifier & W)
1386 fprintf (stdout, "W");
1387 fprintf (stdout, "\n");
1388 for (i = 0; i < t->operands; i++)
1389 {
1390 fprintf (stdout, " #%d type ", i + 1);
1391 pt (t->operand_types[i]);
1392 fprintf (stdout, "\n");
1393 }
1394}
1395
1396static void
e3bb37b5 1397pe (expressionS *e)
252b5132 1398{
24eab124 1399 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1400 fprintf (stdout, " add_number %ld (%lx)\n",
1401 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1402 if (e->X_add_symbol)
1403 {
1404 fprintf (stdout, " add_symbol ");
1405 ps (e->X_add_symbol);
1406 fprintf (stdout, "\n");
1407 }
1408 if (e->X_op_symbol)
1409 {
1410 fprintf (stdout, " op_symbol ");
1411 ps (e->X_op_symbol);
1412 fprintf (stdout, "\n");
1413 }
1414}
1415
1416static void
e3bb37b5 1417ps (symbolS *s)
252b5132
RH		 1418{
1419 fprintf (stdout, "%s type %s%s",
1420 S_GET_NAME (s),
1421 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1422 segment_name (S_GET_SEGMENT (s)));
1423}
1424
7b81dfbb 1425static struct type_name
252b5132
RH		 1426 {
1427 unsigned int mask;
1428 char *tname;
1429 }
7b81dfbb 1430const type_names[] =
252b5132
RH		 1431{
1432 { Reg8, "r8" },
1433 { Reg16, "r16" },
1434 { Reg32, "r32" },
09f131f2 1435 { Reg64, "r64" },
252b5132
RH		 1436 { Imm8, "i8" },
1437 { Imm8S, "i8s" },
1438 { Imm16, "i16" },
1439 { Imm32, "i32" },
09f131f2
JH		 1440 { Imm32S, "i32s" },
1441 { Imm64, "i64" },
252b5132
RH		 1442 { Imm1, "i1" },
1443 { BaseIndex, "BaseIndex" },
1444 { Disp8, "d8" },
1445 { Disp16, "d16" },
1446 { Disp32, "d32" },
09f131f2
JH		 1447 { Disp32S, "d32s" },
1448 { Disp64, "d64" },
252b5132
RH		 1449 { InOutPortReg, "InOutPortReg" },
1450 { ShiftCount, "ShiftCount" },
1451 { Control, "control reg" },
1452 { Test, "test reg" },
1453 { Debug, "debug reg" },
1454 { FloatReg, "FReg" },
1455 { FloatAcc, "FAcc" },
1456 { SReg2, "SReg2" },
1457 { SReg3, "SReg3" },
1458 { Acc, "Acc" },
1459 { JumpAbsolute, "Jump Absolute" },
1460 { RegMMX, "rMMX" },
3f4438ab 1461 { RegXMM, "rXMM" },
252b5132
RH		 1462 { EsSeg, "es" },
1463 { 0, "" }
1464};
1465
1466static void
1467pt (t)
1468 unsigned int t;
1469{
29b0f896 1470 const struct type_name *ty;
252b5132 1471
09f131f2
JH		 1472 for (ty = type_names; ty->mask; ty++)
1473 if (t & ty->mask)
1474 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1475 fflush (stdout);
1476}
1477
1478#endif /* DEBUG386 */
1479\f
252b5132 1480static bfd_reloc_code_real_type
3956db08 1481reloc (unsigned int size,
64e74474
AM		 1482 int pcrel,
1483 int sign,
1484 bfd_reloc_code_real_type other)
252b5132 1485{
47926f60 1486 if (other != NO_RELOC)
3956db08
JB		 1487 {
1488 reloc_howto_type *reloc;
1489
1490 if (size == 8)
1491 switch (other)
1492 {
64e74474
AM		 1493 case BFD_RELOC_X86_64_GOT32:
1494 return BFD_RELOC_X86_64_GOT64;
1495 break;
1496 case BFD_RELOC_X86_64_PLTOFF64:
1497 return BFD_RELOC_X86_64_PLTOFF64;
1498 break;
1499 case BFD_RELOC_X86_64_GOTPC32:
1500 other = BFD_RELOC_X86_64_GOTPC64;
1501 break;
1502 case BFD_RELOC_X86_64_GOTPCREL:
1503 other = BFD_RELOC_X86_64_GOTPCREL64;
1504 break;
1505 case BFD_RELOC_X86_64_TPOFF32:
1506 other = BFD_RELOC_X86_64_TPOFF64;
1507 break;
1508 case BFD_RELOC_X86_64_DTPOFF32:
1509 other = BFD_RELOC_X86_64_DTPOFF64;
1510 break;
1511 default:
1512 break;
3956db08 1513 }
e05278af
JB		 1514
1515 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1516 if (size == 4 && flag_code != CODE_64BIT)
1517 sign = -1;
1518
3956db08
JB		 1519 reloc = bfd_reloc_type_lookup (stdoutput, other);
1520 if (!reloc)
1521 as_bad (_("unknown relocation (%u)"), other);
1522 else if (size != bfd_get_reloc_size (reloc))
1523 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1524 bfd_get_reloc_size (reloc),
1525 size);
1526 else if (pcrel && !reloc->pc_relative)
1527 as_bad (_("non-pc-relative relocation for pc-relative field"));
1528 else if ((reloc->complain_on_overflow == complain_overflow_signed
1529 && !sign)
1530 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1531 && sign > 0))
3956db08
JB		 1532 as_bad (_("relocated field and relocation type differ in signedness"));
1533 else
1534 return other;
1535 return NO_RELOC;
1536 }
252b5132
RH		 1537
1538 if (pcrel)
1539 {
3e73aa7c 1540 if (!sign)
3956db08 1541 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1542 switch (size)
1543 {
1544 case 1: return BFD_RELOC_8_PCREL;
1545 case 2: return BFD_RELOC_16_PCREL;
1546 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1547 case 8: return BFD_RELOC_64_PCREL;
252b5132 1548 }
3956db08 1549 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1550 }
1551 else
1552 {
3956db08 1553 if (sign > 0)
e5cb08ac 1554 switch (size)
3e73aa7c
JH		 1555 {
1556 case 4: return BFD_RELOC_X86_64_32S;
1557 }
1558 else
1559 switch (size)
1560 {
1561 case 1: return BFD_RELOC_8;
1562 case 2: return BFD_RELOC_16;
1563 case 4: return BFD_RELOC_32;
1564 case 8: return BFD_RELOC_64;
1565 }
3956db08
JB		 1566 as_bad (_("cannot do %s %u byte relocation"),
1567 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1568 }
1569
bfb32b52 1570 abort ();
252b5132
RH		 1571 return BFD_RELOC_NONE;
1572}
1573
47926f60
KH		 1574/* Here we decide which fixups can be adjusted to make them relative to
1575 the beginning of the section instead of the symbol. Basically we need
1576 to make sure that the dynamic relocations are done correctly, so in
1577 some cases we force the original symbol to be used. */
1578
252b5132 1579int
e3bb37b5 1580tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1581{
6d249963 1582#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1583 if (!IS_ELF)
31312f95
AM		 1584 return 1;
1585
a161fe53
AM		 1586 /* Don't adjust pc-relative references to merge sections in 64-bit
1587 mode. */
1588 if (use_rela_relocations
1589 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1590 && fixP->fx_pcrel)
252b5132 1591 return 0;
31312f95 1592
8d01d9a9
AJ		 1593 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1594 and changed later by validate_fix. */
1595 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1596 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1597 return 0;
1598
ce8a8b2f 1599 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1600 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1601 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1602 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1603 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1604 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1605 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1613 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1614 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1615 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1616 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1618 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1619 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1624 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1626 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1627 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1628 return 0;
31312f95 1629#endif
252b5132
RH		 1630 return 1;
1631}
252b5132 1632
b4cac588 1633static int
e3bb37b5 1634intel_float_operand (const char *mnemonic)
252b5132 1635{
9306ca4a
JB		 1636 /* Note that the value returned is meaningful only for opcodes with (memory)
1637 operands, hence the code here is free to improperly handle opcodes that
1638 have no operands (for better performance and smaller code). */
1639
1640 if (mnemonic[0] != 'f')
1641 return 0; /* non-math */
1642
1643 switch (mnemonic[1])
1644 {
1645 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1646 the fs segment override prefix not currently handled because no
1647 call path can make opcodes without operands get here */
1648 case 'i':
1649 return 2 /* integer op */;
1650 case 'l':
1651 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1652 return 3; /* fldcw/fldenv */
1653 break;
1654 case 'n':
1655 if (mnemonic[2] != 'o' /* fnop */)
1656 return 3; /* non-waiting control op */
1657 break;
1658 case 'r':
1659 if (mnemonic[2] == 's')
1660 return 3; /* frstor/frstpm */
1661 break;
1662 case 's':
1663 if (mnemonic[2] == 'a')
1664 return 3; /* fsave */
1665 if (mnemonic[2] == 't')
1666 {
1667 switch (mnemonic[3])
1668 {
1669 case 'c': /* fstcw */
1670 case 'd': /* fstdw */
1671 case 'e': /* fstenv */
1672 case 's': /* fsts[gw] */
1673 return 3;
1674 }
1675 }
1676 break;
1677 case 'x':
1678 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1679 return 0; /* fxsave/fxrstor are not really math ops */
1680 break;
1681 }
252b5132 1682
9306ca4a 1683 return 1;
252b5132
RH		 1684}
1685
1686/* This is the guts of the machine-dependent assembler. LINE points to a
1687 machine dependent instruction. This function is supposed to emit
1688 the frags/bytes it assembles to. */
1689
1690void
1691md_assemble (line)
1692 char *line;
1693{
252b5132 1694 int j;
252b5132
RH		 1695 char mnemonic[MAX_MNEM_SIZE];
1696
47926f60 1697 /* Initialize globals. */
252b5132
RH		 1698 memset (&i, '\0', sizeof (i));
1699 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1700 i.reloc[j] = NO_RELOC;
252b5132
RH		 1701 memset (disp_expressions, '\0', sizeof (disp_expressions));
1702 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1703 save_stack_p = save_stack;
252b5132
RH		 1704
1705 /* First parse an instruction mnemonic & call i386_operand for the operands.
1706 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1707 start of a (possibly prefixed) mnemonic. */
252b5132 1708
29b0f896
AM		 1709 line = parse_insn (line, mnemonic);
1710 if (line == NULL)
1711 return;
252b5132 1712
29b0f896
AM		 1713 line = parse_operands (line, mnemonic);
1714 if (line == NULL)
1715 return;
252b5132 1716
4eed87de 1717 /* The order of the immediates should be reversed
050dfa73 1718 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1719 if ((i.imm_operands == 2)
1720 && ((strcmp (mnemonic, "extrq") == 0)
1721 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1722 {
4eed87de
AM		 1723 swap_2_operands (0, 1);
1724 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1725 have to be reversed even though they have two immediate operands.
1726 */
1727 if (intel_syntax)
1728 swap_operands ();
1729 }
1730
29b0f896
AM		 1731 /* Now we've parsed the mnemonic into a set of templates, and have the
1732 operands at hand. */
1733
1734 /* All intel opcodes have reversed operands except for "bound" and
1735 "enter". We also don't reverse intersegment "jmp" and "call"
1736 instructions with 2 immediate operands so that the immediate segment
050dfa73 1737 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1738 if (intel_syntax
1739 && i.operands > 1
29b0f896 1740 && (strcmp (mnemonic, "bound") != 0)
30123838 1741 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1742 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1743 swap_operands ();
1744
1745 if (i.imm_operands)
1746 optimize_imm ();
1747
b300c311
L		 1748 /* Don't optimize displacement for movabs since it only takes 64bit
1749 displacement. */
1750 if (i.disp_operands
1751 && (flag_code != CODE_64BIT
1752 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1753 optimize_disp ();
1754
1755 /* Next, we find a template that matches the given insn,
1756 making sure the overlap of the given operands types is consistent
1757 with the template operand types. */
252b5132 1758
29b0f896
AM		 1759 if (!match_template ())
1760 return;
252b5132 1761
cd61ebfe
AM		 1762 if (intel_syntax)
1763 {
1764 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1765 if (SYSV386_COMPAT
1766 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1767 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1768
1769 /* Zap movzx and movsx suffix. The suffix may have been set from
1770 "word ptr" or "byte ptr" on the source operand, but we'll use
1771 the suffix later to choose the destination register. */
1772 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1773 {
1774 if (i.reg_operands < 2
1775 && !i.suffix
1776 && (~i.tm.opcode_modifier
1777 & (No_bSuf
1778 | No_wSuf
1779 | No_lSuf
1780 | No_sSuf
1781 | No_xSuf
1782 | No_qSuf)))
1783 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1784
1785 i.suffix = 0;
1786 }
cd61ebfe 1787 }
24eab124 1788
29b0f896
AM		 1789 if (i.tm.opcode_modifier & FWait)
1790 if (!add_prefix (FWAIT_OPCODE))
1791 return;
252b5132 1792
29b0f896
AM		 1793 /* Check string instruction segment overrides. */
1794 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1795 {
1796 if (!check_string ())
5dd0794d 1797 return;
29b0f896 1798 }
5dd0794d 1799
29b0f896
AM		 1800 if (!process_suffix ())
1801 return;
e413e4e9 1802
29b0f896
AM		 1803 /* Make still unresolved immediate matches conform to size of immediate
1804 given in i.suffix. */
1805 if (!finalize_imm ())
1806 return;
252b5132 1807
29b0f896
AM		 1808 if (i.types[0] & Imm1)
1809 i.imm_operands = 0; /* kludge for shift insns. */
1810 if (i.types[0] & ImplicitRegister)
1811 i.reg_operands--;
1812 if (i.types[1] & ImplicitRegister)
1813 i.reg_operands--;
1814 if (i.types[2] & ImplicitRegister)
1815 i.reg_operands--;
252b5132 1816
29b0f896
AM		 1817 if (i.tm.opcode_modifier & ImmExt)
1818 {
02fc3089
L		 1819 expressionS *exp;
1820
b7d9ef37 1821 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1822 {
b7d9ef37 1823 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1824 operands with an opcode suffix which is coded in the same
1825 place as an 8-bit immediate field would be. Here we check
1826 those operands and remove them afterwards. */
1827 unsigned int x;
1828
a4622f40 1829 for (x = 0; x < i.operands; x++)
ca164297
L		 1830 if (i.op[x].regs->reg_num != x)
1831 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1832 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1833 i.operands = 0;
1834 }
1835
29b0f896
AM		 1836 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1837 opcode suffix which is coded in the same place as an 8-bit
1838 immediate field would be. Here we fake an 8-bit immediate
1839 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1840
29b0f896 1841 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1842
29b0f896
AM		 1843 exp = &im_expressions[i.imm_operands++];
1844 i.op[i.operands].imms = exp;
1845 i.types[i.operands++] = Imm8;
1846 exp->X_op = O_constant;
1847 exp->X_add_number = i.tm.extension_opcode;
1848 i.tm.extension_opcode = None;
1849 }
252b5132 1850
29b0f896
AM		 1851 /* For insns with operands there are more diddles to do to the opcode. */
1852 if (i.operands)
1853 {
1854 if (!process_operands ())
1855 return;
1856 }
1857 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1858 {
1859 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1860 as_warn (_("translating to `%sp'"), i.tm.name);
1861 }
252b5132 1862
29b0f896
AM		 1863 /* Handle conversion of 'int $3' --> special int3 insn. */
1864 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1865 {
1866 i.tm.base_opcode = INT3_OPCODE;
1867 i.imm_operands = 0;
1868 }
252b5132 1869
29b0f896
AM		 1870 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1871 && i.op[0].disps->X_op == O_constant)
1872 {
1873 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1874 the absolute address given by the constant. Since ix86 jumps and
1875 calls are pc relative, we need to generate a reloc. */
1876 i.op[0].disps->X_add_symbol = &abs_symbol;
1877 i.op[0].disps->X_op = O_symbol;
1878 }
252b5132 1879
29b0f896
AM		 1880 if ((i.tm.opcode_modifier & Rex64) != 0)
1881 i.rex |= REX_MODE64;
252b5132 1882
29b0f896
AM		 1883 /* For 8 bit registers we need an empty rex prefix. Also if the
1884 instruction already has a prefix, we need to convert old
1885 registers to new ones. */
773f551c 1886
29b0f896
AM		 1887 if (((i.types[0] & Reg8) != 0
1888 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1889 || ((i.types[1] & Reg8) != 0
1890 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1891 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1892 && i.rex != 0))
1893 {
1894 int x;
726c5dcd 1895
29b0f896
AM		 1896 i.rex |= REX_OPCODE;
1897 for (x = 0; x < 2; x++)
1898 {
1899 /* Look for 8 bit operand that uses old registers. */
1900 if ((i.types[x] & Reg8) != 0
1901 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1902 {
29b0f896
AM		 1903 /* In case it is "hi" register, give up. */
1904 if (i.op[x].regs->reg_num > 3)
4eed87de
AM		 1905 as_bad (_("can't encode register '%%%s' in an "
1906 "instruction requiring REX prefix."),
29b0f896 1907 i.op[x].regs->reg_name);
773f551c 1908
29b0f896
AM		 1909 /* Otherwise it is equivalent to the extended register.
1910 Since the encoding doesn't change this is merely
1911 cosmetic cleanup for debug output. */
1912
1913 i.op[x].regs = i.op[x].regs + 8;
773f551c 1914 }
29b0f896
AM		 1915 }
1916 }
773f551c 1917
29b0f896
AM		 1918 if (i.rex != 0)
1919 add_prefix (REX_OPCODE | i.rex);
1920
1921 /* We are ready to output the insn. */
1922 output_insn ();
1923}
1924
1925static char *
e3bb37b5 1926parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1927{
1928 char *l = line;
1929 char *token_start = l;
1930 char *mnem_p;
5c6af06e
JB		 1931 int supported;
1932 const template *t;
29b0f896
AM		 1933
1934 /* Non-zero if we found a prefix only acceptable with string insns. */
1935 const char *expecting_string_instruction = NULL;
45288df1 1936
29b0f896
AM		 1937 while (1)
1938 {
1939 mnem_p = mnemonic;
1940 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1941 {
1942 mnem_p++;
1943 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1944 {
29b0f896
AM		 1945 as_bad (_("no such instruction: `%s'"), token_start);
1946 return NULL;
1947 }
1948 l++;
1949 }
1950 if (!is_space_char (*l)
1951 && *l != END_OF_INSN
e44823cf
JB		 1952 && (intel_syntax
1953 || (*l != PREFIX_SEPARATOR
1954 && *l != ',')))
29b0f896
AM		 1955 {
1956 as_bad (_("invalid character %s in mnemonic"),
1957 output_invalid (*l));
1958 return NULL;
1959 }
1960 if (token_start == l)
1961 {
e44823cf 1962 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1963 as_bad (_("expecting prefix; got nothing"));
1964 else
1965 as_bad (_("expecting mnemonic; got nothing"));
1966 return NULL;
1967 }
45288df1 1968
29b0f896
AM		 1969 /* Look up instruction (or prefix) via hash table. */
1970 current_templates = hash_find (op_hash, mnemonic);
47926f60 1971
29b0f896
AM		 1972 if (*l != END_OF_INSN
1973 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1974 && current_templates
1975 && (current_templates->start->opcode_modifier & IsPrefix))
1976 {
2dd88dca
JB		 1977 if (current_templates->start->cpu_flags
1978 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1979 {
1980 as_bad ((flag_code != CODE_64BIT
1981 ? _("`%s' is only supported in 64-bit mode")
1982 : _("`%s' is not supported in 64-bit mode")),
1983 current_templates->start->name);
1984 return NULL;
1985 }
29b0f896
AM		 1986 /* If we are in 16-bit mode, do not allow addr16 or data16.
1987 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1988 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1989 && flag_code != CODE_64BIT
1990 && (((current_templates->start->opcode_modifier & Size32) != 0)
1991 ^ (flag_code == CODE_16BIT)))
1992 {
1993 as_bad (_("redundant %s prefix"),
1994 current_templates->start->name);
1995 return NULL;
45288df1 1996 }
29b0f896
AM		 1997 /* Add prefix, checking for repeated prefixes. */
1998 switch (add_prefix (current_templates->start->base_opcode))
1999 {
2000 case 0:
2001 return NULL;
2002 case 2:
2003 expecting_string_instruction = current_templates->start->name;
2004 break;
2005 }
2006 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2007 token_start = ++l;
2008 }
2009 else
2010 break;
2011 }
45288df1 2012
29b0f896
AM		 2013 if (!current_templates)
2014 {
2015 /* See if we can get a match by trimming off a suffix. */
2016 switch (mnem_p[-1])
2017 {
2018 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2019 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2020 i.suffix = SHORT_MNEM_SUFFIX;
2021 else
29b0f896
AM		 2022 case BYTE_MNEM_SUFFIX:
2023 case QWORD_MNEM_SUFFIX:
2024 i.suffix = mnem_p[-1];
2025 mnem_p[-1] = '\0';
2026 current_templates = hash_find (op_hash, mnemonic);
2027 break;
2028 case SHORT_MNEM_SUFFIX:
2029 case LONG_MNEM_SUFFIX:
2030 if (!intel_syntax)
2031 {
2032 i.suffix = mnem_p[-1];
2033 mnem_p[-1] = '\0';
2034 current_templates = hash_find (op_hash, mnemonic);
2035 }
2036 break;
252b5132 2037
29b0f896
AM		 2038 /* Intel Syntax. */
2039 case 'd':
2040 if (intel_syntax)
2041 {
9306ca4a 2042 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2043 i.suffix = SHORT_MNEM_SUFFIX;
2044 else
2045 i.suffix = LONG_MNEM_SUFFIX;
2046 mnem_p[-1] = '\0';
2047 current_templates = hash_find (op_hash, mnemonic);
2048 }
2049 break;
2050 }
2051 if (!current_templates)
2052 {
2053 as_bad (_("no such instruction: `%s'"), token_start);
2054 return NULL;
2055 }
2056 }
252b5132 2057
29b0f896
AM		 2058 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2059 {
2060 /* Check for a branch hint. We allow ",pt" and ",pn" for
2061 predict taken and predict not taken respectively.
2062 I'm not sure that branch hints actually do anything on loop
2063 and jcxz insns (JumpByte) for current Pentium4 chips. They
2064 may work in the future and it doesn't hurt to accept them
2065 now. */
2066 if (l[0] == ',' && l[1] == 'p')
2067 {
2068 if (l[2] == 't')
2069 {
2070 if (!add_prefix (DS_PREFIX_OPCODE))
2071 return NULL;
2072 l += 3;
2073 }
2074 else if (l[2] == 'n')
2075 {
2076 if (!add_prefix (CS_PREFIX_OPCODE))
2077 return NULL;
2078 l += 3;
2079 }
2080 }
2081 }
2082 /* Any other comma loses. */
2083 if (*l == ',')
2084 {
2085 as_bad (_("invalid character %s in mnemonic"),
2086 output_invalid (*l));
2087 return NULL;
2088 }
252b5132 2089
29b0f896 2090 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2091 supported = 0;
2092 for (t = current_templates->start; t < current_templates->end; ++t)
2093 {
2094 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2095 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2096 supported |= 1;
5c6af06e 2097 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2098 supported |= 2;
5c6af06e
JB		 2099 }
2100 if (!(supported & 2))
2101 {
2102 as_bad (flag_code == CODE_64BIT
2103 ? _("`%s' is not supported in 64-bit mode")
2104 : _("`%s' is only supported in 64-bit mode"),
2105 current_templates->start->name);
2106 return NULL;
2107 }
2108 if (!(supported & 1))
29b0f896 2109 {
5c6af06e
JB		 2110 as_warn (_("`%s' is not supported on `%s%s'"),
2111 current_templates->start->name,
2112 cpu_arch_name,
2113 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2114 }
2115 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2116 {
2117 as_warn (_("use .code16 to ensure correct addressing mode"));
2118 }
252b5132 2119
29b0f896 2120 /* Check for rep/repne without a string instruction. */
f41bbced 2121 if (expecting_string_instruction)
29b0f896 2122 {
f41bbced
JB		 2123 static templates override;
2124
2125 for (t = current_templates->start; t < current_templates->end; ++t)
2126 if (t->opcode_modifier & IsString)
2127 break;
2128 if (t >= current_templates->end)
2129 {
2130 as_bad (_("expecting string instruction after `%s'"),
64e74474 2131 expecting_string_instruction);
f41bbced
JB		 2132 return NULL;
2133 }
2134 for (override.start = t; t < current_templates->end; ++t)
2135 if (!(t->opcode_modifier & IsString))
2136 break;
2137 override.end = t;
2138 current_templates = &override;
29b0f896 2139 }
252b5132 2140
29b0f896
AM		 2141 return l;
2142}
252b5132 2143
29b0f896 2144static char *
e3bb37b5 2145parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2146{
2147 char *token_start;
3138f287 2148
29b0f896
AM		 2149 /* 1 if operand is pending after ','. */
2150 unsigned int expecting_operand = 0;
252b5132 2151
29b0f896
AM		 2152 /* Non-zero if operand parens not balanced. */
2153 unsigned int paren_not_balanced;
2154
2155 while (*l != END_OF_INSN)
2156 {
2157 /* Skip optional white space before operand. */
2158 if (is_space_char (*l))
2159 ++l;
2160 if (!is_operand_char (*l) && *l != END_OF_INSN)
2161 {
2162 as_bad (_("invalid character %s before operand %d"),
2163 output_invalid (*l),
2164 i.operands + 1);
2165 return NULL;
2166 }
2167 token_start = l; /* after white space */
2168 paren_not_balanced = 0;
2169 while (paren_not_balanced || *l != ',')
2170 {
2171 if (*l == END_OF_INSN)
2172 {
2173 if (paren_not_balanced)
2174 {
2175 if (!intel_syntax)
2176 as_bad (_("unbalanced parenthesis in operand %d."),
2177 i.operands + 1);
2178 else
2179 as_bad (_("unbalanced brackets in operand %d."),
2180 i.operands + 1);
2181 return NULL;
2182 }
2183 else
2184 break; /* we are done */
2185 }
2186 else if (!is_operand_char (*l) && !is_space_char (*l))
2187 {
2188 as_bad (_("invalid character %s in operand %d"),
2189 output_invalid (*l),
2190 i.operands + 1);
2191 return NULL;
2192 }
2193 if (!intel_syntax)
2194 {
2195 if (*l == '(')
2196 ++paren_not_balanced;
2197 if (*l == ')')
2198 --paren_not_balanced;
2199 }
2200 else
2201 {
2202 if (*l == '[')
2203 ++paren_not_balanced;
2204 if (*l == ']')
2205 --paren_not_balanced;
2206 }
2207 l++;
2208 }
2209 if (l != token_start)
2210 { /* Yes, we've read in another operand. */
2211 unsigned int operand_ok;
2212 this_operand = i.operands++;
2213 if (i.operands > MAX_OPERANDS)
2214 {
2215 as_bad (_("spurious operands; (%d operands/instruction max)"),
2216 MAX_OPERANDS);
2217 return NULL;
2218 }
2219 /* Now parse operand adding info to 'i' as we go along. */
2220 END_STRING_AND_SAVE (l);
2221
2222 if (intel_syntax)
2223 operand_ok =
2224 i386_intel_operand (token_start,
2225 intel_float_operand (mnemonic));
2226 else
2227 operand_ok = i386_operand (token_start);
2228
2229 RESTORE_END_STRING (l);
2230 if (!operand_ok)
2231 return NULL;
2232 }
2233 else
2234 {
2235 if (expecting_operand)
2236 {
2237 expecting_operand_after_comma:
2238 as_bad (_("expecting operand after ','; got nothing"));
2239 return NULL;
2240 }
2241 if (*l == ',')
2242 {
2243 as_bad (_("expecting operand before ','; got nothing"));
2244 return NULL;
2245 }
2246 }
7f3f1ea2 2247
29b0f896
AM		 2248 /* Now *l must be either ',' or END_OF_INSN. */
2249 if (*l == ',')
2250 {
2251 if (*++l == END_OF_INSN)
2252 {
2253 /* Just skip it, if it's \n complain. */
2254 goto expecting_operand_after_comma;
2255 }
2256 expecting_operand = 1;
2257 }
2258 }
2259 return l;
2260}
7f3f1ea2 2261
050dfa73 2262static void
4d456e3d 2263swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2264{
2265 union i386_op temp_op;
2266 unsigned int temp_type;
2267 enum bfd_reloc_code_real temp_reloc;
4eed87de 2268
050dfa73
MM		 2269 temp_type = i.types[xchg2];
2270 i.types[xchg2] = i.types[xchg1];
2271 i.types[xchg1] = temp_type;
2272 temp_op = i.op[xchg2];
2273 i.op[xchg2] = i.op[xchg1];
2274 i.op[xchg1] = temp_op;
2275 temp_reloc = i.reloc[xchg2];
2276 i.reloc[xchg2] = i.reloc[xchg1];
2277 i.reloc[xchg1] = temp_reloc;
2278}
2279
29b0f896 2280static void
e3bb37b5 2281swap_operands (void)
29b0f896 2282{
b7c61d9a 2283 switch (i.operands)
050dfa73 2284 {
b7c61d9a 2285 case 4:
4d456e3d 2286 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2287 case 3:
2288 case 2:
4d456e3d 2289 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2290 break;
2291 default:
2292 abort ();
29b0f896 2293 }
29b0f896
AM		 2294
2295 if (i.mem_operands == 2)
2296 {
2297 const seg_entry *temp_seg;
2298 temp_seg = i.seg[0];
2299 i.seg[0] = i.seg[1];
2300 i.seg[1] = temp_seg;
2301 }
2302}
252b5132 2303
29b0f896
AM		 2304/* Try to ensure constant immediates are represented in the smallest
2305 opcode possible. */
2306static void
e3bb37b5 2307optimize_imm (void)
29b0f896
AM		 2308{
2309 char guess_suffix = 0;
2310 int op;
252b5132 2311
29b0f896
AM		 2312 if (i.suffix)
2313 guess_suffix = i.suffix;
2314 else if (i.reg_operands)
2315 {
2316 /* Figure out a suffix from the last register operand specified.
2317 We can't do this properly yet, ie. excluding InOutPortReg,
2318 but the following works for instructions with immediates.
2319 In any case, we can't set i.suffix yet. */
2320 for (op = i.operands; --op >= 0;)
2321 if (i.types[op] & Reg)
252b5132 2322 {
29b0f896
AM		 2323 if (i.types[op] & Reg8)
2324 guess_suffix = BYTE_MNEM_SUFFIX;
2325 else if (i.types[op] & Reg16)
2326 guess_suffix = WORD_MNEM_SUFFIX;
2327 else if (i.types[op] & Reg32)
2328 guess_suffix = LONG_MNEM_SUFFIX;
2329 else if (i.types[op] & Reg64)
2330 guess_suffix = QWORD_MNEM_SUFFIX;
2331 break;
252b5132 2332 }
29b0f896
AM		 2333 }
2334 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2335 guess_suffix = WORD_MNEM_SUFFIX;
2336
2337 for (op = i.operands; --op >= 0;)
2338 if (i.types[op] & Imm)
2339 {
2340 switch (i.op[op].imms->X_op)
252b5132 2341 {
29b0f896
AM		 2342 case O_constant:
2343 /* If a suffix is given, this operand may be shortened. */
2344 switch (guess_suffix)
252b5132 2345 {
29b0f896
AM		 2346 case LONG_MNEM_SUFFIX:
2347 i.types[op] |= Imm32 | Imm64;
2348 break;
2349 case WORD_MNEM_SUFFIX:
2350 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2351 break;
2352 case BYTE_MNEM_SUFFIX:
2353 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2354 break;
252b5132 2355 }
252b5132 2356
29b0f896
AM		 2357 /* If this operand is at most 16 bits, convert it
2358 to a signed 16 bit number before trying to see
2359 whether it will fit in an even smaller size.
2360 This allows a 16-bit operand such as $0xffe0 to
2361 be recognised as within Imm8S range. */
2362 if ((i.types[op] & Imm16)
2363 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2364 {
29b0f896
AM		 2365 i.op[op].imms->X_add_number =
2366 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2367 }
2368 if ((i.types[op] & Imm32)
2369 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2370 == 0))
2371 {
2372 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2373 ^ ((offsetT) 1 << 31))
2374 - ((offsetT) 1 << 31));
2375 }
2376 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2377
29b0f896
AM		 2378 /* We must avoid matching of Imm32 templates when 64bit
2379 only immediate is available. */
2380 if (guess_suffix == QWORD_MNEM_SUFFIX)
2381 i.types[op] &= ~Imm32;
2382 break;
252b5132 2383
29b0f896
AM		 2384 case O_absent:
2385 case O_register:
2386 abort ();
2387
2388 /* Symbols and expressions. */
2389 default:
9cd96992
JB		 2390 /* Convert symbolic operand to proper sizes for matching, but don't
2391 prevent matching a set of insns that only supports sizes other
2392 than those matching the insn suffix. */
2393 {
2394 unsigned int mask, allowed = 0;
2395 const template *t;
2396
4eed87de
AM		 2397 for (t = current_templates->start;
2398 t < current_templates->end;
2399 ++t)
2400 allowed |= t->operand_types[op];
9cd96992
JB		 2401 switch (guess_suffix)
2402 {
2403 case QWORD_MNEM_SUFFIX:
2404 mask = Imm64 | Imm32S;
2405 break;
2406 case LONG_MNEM_SUFFIX:
2407 mask = Imm32;
2408 break;
2409 case WORD_MNEM_SUFFIX:
2410 mask = Imm16;
2411 break;
2412 case BYTE_MNEM_SUFFIX:
2413 mask = Imm8;
2414 break;
2415 default:
2416 mask = 0;
2417 break;
2418 }
64e74474
AM		 2419 if (mask & allowed)
2420 i.types[op] &= mask;
9cd96992 2421 }
29b0f896 2422 break;
252b5132 2423 }
29b0f896
AM		 2424 }
2425}
47926f60 2426
29b0f896
AM		 2427/* Try to use the smallest displacement type too. */
2428static void
e3bb37b5 2429optimize_disp (void)
29b0f896
AM		 2430{
2431 int op;
3e73aa7c 2432
29b0f896 2433 for (op = i.operands; --op >= 0;)
b300c311 2434 if (i.types[op] & Disp)
252b5132 2435 {
b300c311 2436 if (i.op[op].disps->X_op == O_constant)
252b5132 2437 {
b300c311 2438 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2439
b300c311
L		 2440 if ((i.types[op] & Disp16)
2441 && (disp & ~(offsetT) 0xffff) == 0)
2442 {
2443 /* If this operand is at most 16 bits, convert
2444 to a signed 16 bit number and don't use 64bit
2445 displacement. */
2446 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2447 i.types[op] &= ~Disp64;
2448 }
2449 if ((i.types[op] & Disp32)
2450 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2451 {
2452 /* If this operand is at most 32 bits, convert
2453 to a signed 32 bit number and don't use 64bit
2454 displacement. */
2455 disp &= (((offsetT) 2 << 31) - 1);
2456 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2457 i.types[op] &= ~Disp64;
2458 }
2459 if (!disp && (i.types[op] & BaseIndex))
2460 {
2461 i.types[op] &= ~Disp;
2462 i.op[op].disps = 0;
2463 i.disp_operands--;
2464 }
2465 else if (flag_code == CODE_64BIT)
2466 {
2467 if (fits_in_signed_long (disp))
28a9d8f5
L		 2468 {
2469 i.types[op] &= ~Disp64;
2470 i.types[op] |= Disp32S;
2471 }
b300c311
L		 2472 if (fits_in_unsigned_long (disp))
2473 i.types[op] |= Disp32;
2474 }
2475 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2476 && fits_in_signed_byte (disp))
2477 i.types[op] |= Disp8;
252b5132 2478 }
67a4f2b7
AO		 2479 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2480 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2481 {
2482 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2483 i.op[op].disps, 0, i.reloc[op]);
2484 i.types[op] &= ~Disp;
2485 }
2486 else
b300c311
L		 2487 /* We only support 64bit displacement on constants. */
2488 i.types[op] &= ~Disp64;
252b5132 2489 }
29b0f896
AM		 2490}
2491
2492static int
e3bb37b5 2493match_template (void)
29b0f896
AM		 2494{
2495 /* Points to template once we've found it. */
2496 const template *t;
f48ff2ae 2497 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2498 unsigned int found_reverse_match;
2499 int suffix_check;
f48ff2ae 2500 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2501 int addr_prefix_disp;
a5c311ca 2502 unsigned int j;
29b0f896 2503
f48ff2ae
L		 2504#if MAX_OPERANDS != 4
2505# error "MAX_OPERANDS must be 4."
2506#endif
2507
29b0f896
AM		 2508#define MATCH(overlap, given, template) \
2509 ((overlap & ~JumpAbsolute) \
2510 && (((given) & (BaseIndex | JumpAbsolute)) \
2511 == ((overlap) & (BaseIndex | JumpAbsolute))))
2512
2513 /* If given types r0 and r1 are registers they must be of the same type
2514 unless the expected operand type register overlap is null.
2515 Note that Acc in a template matches every size of reg. */
2516#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2517 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2518 || ((g0) & Reg) == ((g1) & Reg) \
2519 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2520
2521 overlap0 = 0;
2522 overlap1 = 0;
2523 overlap2 = 0;
f48ff2ae 2524 overlap3 = 0;
29b0f896 2525 found_reverse_match = 0;
a5c311ca
L		 2526 for (j = 0; j < MAX_OPERANDS; j++)
2527 operand_types [j] = 0;
539e75ad 2528 addr_prefix_disp = -1;
29b0f896
AM		 2529 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2530 ? No_bSuf
2531 : (i.suffix == WORD_MNEM_SUFFIX
2532 ? No_wSuf
2533 : (i.suffix == SHORT_MNEM_SUFFIX
2534 ? No_sSuf
2535 : (i.suffix == LONG_MNEM_SUFFIX
2536 ? No_lSuf
2537 : (i.suffix == QWORD_MNEM_SUFFIX
2538 ? No_qSuf
2539 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2540 ? No_xSuf : 0))))));
2541
45aa61fe 2542 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2543 {
539e75ad
L		 2544 addr_prefix_disp = -1;
2545
29b0f896
AM		 2546 /* Must have right number of operands. */
2547 if (i.operands != t->operands)
2548 continue;
2549
2550 /* Check the suffix, except for some instructions in intel mode. */
2551 if ((t->opcode_modifier & suffix_check)
2552 && !(intel_syntax
9306ca4a 2553 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2554 continue;
2555
a5c311ca
L		 2556 for (j = 0; j < MAX_OPERANDS; j++)
2557 operand_types [j] = t->operand_types [j];
539e75ad 2558
45aa61fe
AM		 2559 /* In general, don't allow 64-bit operands in 32-bit mode. */
2560 if (i.suffix == QWORD_MNEM_SUFFIX
2561 && flag_code != CODE_64BIT
2562 && (intel_syntax
2563 ? (!(t->opcode_modifier & IgnoreSize)
2564 && !intel_float_operand (t->name))
2565 : intel_float_operand (t->name) != 2)
539e75ad
L		 2566 && (!(operand_types[0] & (RegMMX | RegXMM))
2567 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2568 && (t->base_opcode != 0x0fc7
2569 || t->extension_opcode != 1 /* cmpxchg8b */))
2570 continue;
2571
29b0f896
AM		 2572 /* Do not verify operands when there are none. */
2573 else if (!t->operands)
2574 {
2575 if (t->cpu_flags & ~cpu_arch_flags)
2576 continue;
2577 /* We've found a match; break out of loop. */
2578 break;
2579 }
252b5132 2580
539e75ad
L		 2581 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2582 into Disp32/Disp16/Disp32 operand. */
2583 if (i.prefix[ADDR_PREFIX] != 0)
2584 {
a5c311ca 2585 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2586
2587 switch (flag_code)
2588 {
2589 case CODE_16BIT:
2590 DispOn = Disp32;
2591 DispOff = Disp16;
2592 break;
2593 case CODE_32BIT:
2594 DispOn = Disp16;
2595 DispOff = Disp32;
2596 break;
2597 case CODE_64BIT:
2598 DispOn = Disp32;
2599 DispOff = Disp64;
2600 break;
2601 }
2602
f48ff2ae 2603 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2604 {
2605 /* There should be only one Disp operand. */
2606 if ((operand_types[j] & DispOff))
2607 {
2608 addr_prefix_disp = j;
2609 operand_types[j] |= DispOn;
2610 operand_types[j] &= ~DispOff;
2611 break;
2612 }
2613 }
2614 }
2615
2616 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2617 switch (t->operands)
2618 {
2619 case 1:
539e75ad 2620 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2621 continue;
2622 break;
2623 case 2:
2624 case 3:
f48ff2ae 2625 case 4:
539e75ad
L		 2626 overlap1 = i.types[1] & operand_types[1];
2627 if (!MATCH (overlap0, i.types[0], operand_types[0])
2628 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2629 /* monitor in SSE3 is a very special case. The first
708587a4 2630 register and the second register may have different
cb712a9e
L		 2631 sizes. */
2632 || !((t->base_opcode == 0x0f01
2633 && t->extension_opcode == 0xc8)
2634 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2635 operand_types[0],
cb712a9e 2636 overlap1, i.types[1],
539e75ad 2637 operand_types[1])))
29b0f896
AM		 2638 {
2639 /* Check if other direction is valid ... */
2640 if ((t->opcode_modifier & (D | FloatD)) == 0)
2641 continue;
2642
2643 /* Try reversing direction of operands. */
539e75ad
L		 2644 overlap0 = i.types[0] & operand_types[1];
2645 overlap1 = i.types[1] & operand_types[0];
2646 if (!MATCH (overlap0, i.types[0], operand_types[1])
2647 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2648 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2649 operand_types[1],
29b0f896 2650 overlap1, i.types[1],
539e75ad 2651 operand_types[0]))
29b0f896
AM		 2652 {
2653 /* Does not match either direction. */
2654 continue;
2655 }
2656 /* found_reverse_match holds which of D or FloatDR
2657 we've found. */
8a2ed489
L		 2658 if ((t->opcode_modifier & D))
2659 found_reverse_match = Opcode_D;
2660 else if ((t->opcode_modifier & FloatD))
2661 found_reverse_match = Opcode_FloatD;
2662 else
2663 found_reverse_match = 0;
2664 if ((t->opcode_modifier & FloatR))
2665 found_reverse_match |= Opcode_FloatR;
29b0f896 2666 }
f48ff2ae 2667 else
29b0f896 2668 {
f48ff2ae 2669 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2670 switch (t->operands)
2671 {
2672 case 4:
2673 overlap3 = i.types[3] & operand_types[3];
2674 case 3:
2675 overlap2 = i.types[2] & operand_types[2];
2676 break;
2677 }
29b0f896 2678
f48ff2ae
L		 2679 switch (t->operands)
2680 {
2681 case 4:
2682 if (!MATCH (overlap3, i.types[3], operand_types[3])
2683 || !CONSISTENT_REGISTER_MATCH (overlap2,
2684 i.types[2],
2685 operand_types[2],
2686 overlap3,
2687 i.types[3],
2688 operand_types[3]))
2689 continue;
2690 case 3:
2691 /* Here we make use of the fact that there are no
2692 reverse match 3 operand instructions, and all 3
2693 operand instructions only need to be checked for
2694 register consistency between operands 2 and 3. */
2695 if (!MATCH (overlap2, i.types[2], operand_types[2])
2696 || !CONSISTENT_REGISTER_MATCH (overlap1,
2697 i.types[1],
2698 operand_types[1],
2699 overlap2,
2700 i.types[2],
2701 operand_types[2]))
2702 continue;
2703 break;
2704 }
29b0f896 2705 }
f48ff2ae 2706 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2707 slip through to break. */
2708 }
2709 if (t->cpu_flags & ~cpu_arch_flags)
2710 {
2711 found_reverse_match = 0;
2712 continue;
2713 }
2714 /* We've found a match; break out of loop. */
2715 break;
2716 }
2717
2718 if (t == current_templates->end)
2719 {
2720 /* We found no match. */
2721 as_bad (_("suffix or operands invalid for `%s'"),
2722 current_templates->start->name);
2723 return 0;
2724 }
252b5132 2725
29b0f896
AM		 2726 if (!quiet_warnings)
2727 {
2728 if (!intel_syntax
2729 && ((i.types[0] & JumpAbsolute)
539e75ad 2730 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2731 {
2732 as_warn (_("indirect %s without `*'"), t->name);
2733 }
2734
2735 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2736 == (IsPrefix | IgnoreSize))
2737 {
2738 /* Warn them that a data or address size prefix doesn't
2739 affect assembly of the next line of code. */
2740 as_warn (_("stand-alone `%s' prefix"), t->name);
2741 }
2742 }
2743
2744 /* Copy the template we found. */
2745 i.tm = *t;
539e75ad
L		 2746
2747 if (addr_prefix_disp != -1)
2748 i.tm.operand_types[addr_prefix_disp]
2749 = operand_types[addr_prefix_disp];
2750
29b0f896
AM		 2751 if (found_reverse_match)
2752 {
2753 /* If we found a reverse match we must alter the opcode
2754 direction bit. found_reverse_match holds bits to change
2755 (different for int & float insns). */
2756
2757 i.tm.base_opcode ^= found_reverse_match;
2758
539e75ad
L		 2759 i.tm.operand_types[0] = operand_types[1];
2760 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2761 }
2762
2763 return 1;
2764}
2765
2766static int
e3bb37b5 2767check_string (void)
29b0f896
AM		 2768{
2769 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2770 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2771 {
2772 if (i.seg[0] != NULL && i.seg[0] != &es)
2773 {
2774 as_bad (_("`%s' operand %d must use `%%es' segment"),
2775 i.tm.name,
2776 mem_op + 1);
2777 return 0;
2778 }
2779 /* There's only ever one segment override allowed per instruction.
2780 This instruction possibly has a legal segment override on the
2781 second operand, so copy the segment to where non-string
2782 instructions store it, allowing common code. */
2783 i.seg[0] = i.seg[1];
2784 }
2785 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2786 {
2787 if (i.seg[1] != NULL && i.seg[1] != &es)
2788 {
2789 as_bad (_("`%s' operand %d must use `%%es' segment"),
2790 i.tm.name,
2791 mem_op + 2);
2792 return 0;
2793 }
2794 }
2795 return 1;
2796}
2797
2798static int
543613e9 2799process_suffix (void)
29b0f896
AM		 2800{
2801 /* If matched instruction specifies an explicit instruction mnemonic
2802 suffix, use it. */
2803 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2804 {
2805 if (i.tm.opcode_modifier & Size16)
2806 i.suffix = WORD_MNEM_SUFFIX;
2807 else if (i.tm.opcode_modifier & Size64)
2808 i.suffix = QWORD_MNEM_SUFFIX;
2809 else
2810 i.suffix = LONG_MNEM_SUFFIX;
2811 }
2812 else if (i.reg_operands)
2813 {
2814 /* If there's no instruction mnemonic suffix we try to invent one
2815 based on register operands. */
2816 if (!i.suffix)
2817 {
2818 /* We take i.suffix from the last register operand specified,
2819 Destination register type is more significant than source
2820 register type. */
2821 int op;
543613e9 2822
29b0f896
AM		 2823 for (op = i.operands; --op >= 0;)
2824 if ((i.types[op] & Reg)
2825 && !(i.tm.operand_types[op] & InOutPortReg))
2826 {
2827 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2828 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2829 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2830 LONG_MNEM_SUFFIX);
2831 break;
2832 }
2833 }
2834 else if (i.suffix == BYTE_MNEM_SUFFIX)
2835 {
2836 if (!check_byte_reg ())
2837 return 0;
2838 }
2839 else if (i.suffix == LONG_MNEM_SUFFIX)
2840 {
2841 if (!check_long_reg ())
2842 return 0;
2843 }
2844 else if (i.suffix == QWORD_MNEM_SUFFIX)
2845 {
2846 if (!check_qword_reg ())
2847 return 0;
2848 }
2849 else if (i.suffix == WORD_MNEM_SUFFIX)
2850 {
2851 if (!check_word_reg ())
2852 return 0;
2853 }
2854 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2855 /* Do nothing if the instruction is going to ignore the prefix. */
2856 ;
2857 else
2858 abort ();
2859 }
9306ca4a
JB		 2860 else if ((i.tm.opcode_modifier & DefaultSize)
2861 && !i.suffix
2862 /* exclude fldenv/frstor/fsave/fstenv */
2863 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2864 {
2865 i.suffix = stackop_size;
2866 }
9306ca4a
JB		 2867 else if (intel_syntax
2868 && !i.suffix
2869 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2870 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2871 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2872 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2873 {
2874 switch (flag_code)
2875 {
2876 case CODE_64BIT:
2877 if (!(i.tm.opcode_modifier & No_qSuf))
2878 {
2879 i.suffix = QWORD_MNEM_SUFFIX;
2880 break;
2881 }
2882 case CODE_32BIT:
2883 if (!(i.tm.opcode_modifier & No_lSuf))
2884 i.suffix = LONG_MNEM_SUFFIX;
2885 break;
2886 case CODE_16BIT:
2887 if (!(i.tm.opcode_modifier & No_wSuf))
2888 i.suffix = WORD_MNEM_SUFFIX;
2889 break;
2890 }
2891 }
252b5132 2892
9306ca4a 2893 if (!i.suffix)
29b0f896 2894 {
9306ca4a
JB		 2895 if (!intel_syntax)
2896 {
2897 if (i.tm.opcode_modifier & W)
2898 {
4eed87de
AM		 2899 as_bad (_("no instruction mnemonic suffix given and "
2900 "no register operands; can't size instruction"));
9306ca4a
JB		 2901 return 0;
2902 }
2903 }
2904 else
2905 {
64e74474
AM		 2906 unsigned int suffixes = (~i.tm.opcode_modifier
2907 & (No_bSuf
2908 | No_wSuf
2909 | No_lSuf
2910 | No_sSuf
2911 | No_xSuf
2912 | No_qSuf));
9306ca4a
JB		 2913
2914 if ((i.tm.opcode_modifier & W)
2915 || ((suffixes & (suffixes - 1))
2916 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2917 {
2918 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2919 return 0;
2920 }
2921 }
29b0f896 2922 }
252b5132 2923
9306ca4a
JB		 2924 /* Change the opcode based on the operand size given by i.suffix;
2925 We don't need to change things for byte insns. */
2926
29b0f896
AM		 2927 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2928 {
2929 /* It's not a byte, select word/dword operation. */
2930 if (i.tm.opcode_modifier & W)
2931 {
2932 if (i.tm.opcode_modifier & ShortForm)
2933 i.tm.base_opcode |= 8;
2934 else
2935 i.tm.base_opcode |= 1;
2936 }
0f3f3d8b 2937
29b0f896
AM		 2938 /* Now select between word & dword operations via the operand
2939 size prefix, except for instructions that will ignore this
2940 prefix anyway. */
cb712a9e
L		 2941 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2942 {
2943 /* monitor in SSE3 is a very special case. The default size
2944 of AX is the size of mode. The address size override
2945 prefix will change the size of AX. */
2946 if (i.op->regs[0].reg_type &
2947 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2948 if (!add_prefix (ADDR_PREFIX_OPCODE))
2949 return 0;
2950 }
2951 else if (i.suffix != QWORD_MNEM_SUFFIX
2952 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2953 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2954 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2955 || (flag_code == CODE_64BIT
2956 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2957 {
2958 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2959
29b0f896
AM		 2960 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2961 prefix = ADDR_PREFIX_OPCODE;
252b5132 2962
29b0f896
AM		 2963 if (!add_prefix (prefix))
2964 return 0;
24eab124 2965 }
252b5132 2966
29b0f896
AM		 2967 /* Set mode64 for an operand. */
2968 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2969 && flag_code == CODE_64BIT
29b0f896 2970 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2971 {
2972 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2973 need rex64. */
2974 if (i.operands != 2
2975 || i.types [0] != (Acc | Reg64)
2976 || i.types [1] != (Acc | Reg64)
2977 || strcmp (i.tm.name, "xchg") != 0)
2978 i.rex |= REX_MODE64;
2979 }
3e73aa7c 2980
29b0f896
AM		 2981 /* Size floating point instruction. */
2982 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2983 if (i.tm.opcode_modifier & FloatMF)
2984 i.tm.base_opcode ^= 4;
29b0f896 2985 }
7ecd2f8b 2986
29b0f896
AM		 2987 return 1;
2988}
3e73aa7c 2989
29b0f896 2990static int
543613e9 2991check_byte_reg (void)
29b0f896
AM		 2992{
2993 int op;
543613e9 2994
29b0f896
AM		 2995 for (op = i.operands; --op >= 0;)
2996 {
2997 /* If this is an eight bit register, it's OK. If it's the 16 or
2998 32 bit version of an eight bit register, we will just use the
2999 low portion, and that's OK too. */
3000 if (i.types[op] & Reg8)
3001 continue;
3002
3003 /* movzx and movsx should not generate this warning. */
3004 if (intel_syntax
3005 && (i.tm.base_opcode == 0xfb7
3006 || i.tm.base_opcode == 0xfb6
3007 || i.tm.base_opcode == 0x63
3008 || i.tm.base_opcode == 0xfbe
3009 || i.tm.base_opcode == 0xfbf))
3010 continue;
3011
65ec77d2 3012 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3013 {
3014 /* Prohibit these changes in the 64bit mode, since the
3015 lowering is more complicated. */
3016 if (flag_code == CODE_64BIT
3017 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3018 {
2ca3ace5
L		 3019 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3020 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3021 i.suffix);
3022 return 0;
3023 }
3024#if REGISTER_WARNINGS
3025 if (!quiet_warnings
3026 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3027 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3028 (i.op[op].regs + (i.types[op] & Reg16
3029 ? REGNAM_AL - REGNAM_AX
3030 : REGNAM_AL - REGNAM_EAX))->reg_name,
3031 i.op[op].regs->reg_name,
3032 i.suffix);
3033#endif
3034 continue;
3035 }
3036 /* Any other register is bad. */
3037 if (i.types[op] & (Reg | RegMMX | RegXMM
3038 | SReg2 | SReg3
3039 | Control | Debug | Test
3040 | FloatReg | FloatAcc))
3041 {
3042 as_bad (_("`%%%s' not allowed with `%s%c'"),
3043 i.op[op].regs->reg_name,
3044 i.tm.name,
3045 i.suffix);
3046 return 0;
3047 }
3048 }
3049 return 1;
3050}
3051
3052static int
e3bb37b5 3053check_long_reg (void)
29b0f896
AM		 3054{
3055 int op;
3056
3057 for (op = i.operands; --op >= 0;)
3058 /* Reject eight bit registers, except where the template requires
3059 them. (eg. movzb) */
3060 if ((i.types[op] & Reg8) != 0
3061 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3062 {
3063 as_bad (_("`%%%s' not allowed with `%s%c'"),
3064 i.op[op].regs->reg_name,
3065 i.tm.name,
3066 i.suffix);
3067 return 0;
3068 }
3069 /* Warn if the e prefix on a general reg is missing. */
3070 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3071 && (i.types[op] & Reg16) != 0
3072 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3073 {
3074 /* Prohibit these changes in the 64bit mode, since the
3075 lowering is more complicated. */
3076 if (flag_code == CODE_64BIT)
252b5132 3077 {
2ca3ace5
L		 3078 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3079 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3080 i.suffix);
3081 return 0;
252b5132 3082 }
29b0f896
AM		 3083#if REGISTER_WARNINGS
3084 else
3085 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3086 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3087 i.op[op].regs->reg_name,
3088 i.suffix);
3089#endif
252b5132 3090 }
29b0f896
AM		 3091 /* Warn if the r prefix on a general reg is missing. */
3092 else if ((i.types[op] & Reg64) != 0
3093 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3094 {
2ca3ace5
L		 3095 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3096 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3097 i.suffix);
3098 return 0;
3099 }
3100 return 1;
3101}
252b5132 3102
29b0f896 3103static int
e3bb37b5 3104check_qword_reg (void)
29b0f896
AM		 3105{
3106 int op;
252b5132 3107
29b0f896
AM		 3108 for (op = i.operands; --op >= 0; )
3109 /* Reject eight bit registers, except where the template requires
3110 them. (eg. movzb) */
3111 if ((i.types[op] & Reg8) != 0
3112 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3113 {
3114 as_bad (_("`%%%s' not allowed with `%s%c'"),
3115 i.op[op].regs->reg_name,
3116 i.tm.name,
3117 i.suffix);
3118 return 0;
3119 }
3120 /* Warn if the e prefix on a general reg is missing. */
3121 else if (((i.types[op] & Reg16) != 0
3122 || (i.types[op] & Reg32) != 0)
3123 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3124 {
3125 /* Prohibit these changes in the 64bit mode, since the
3126 lowering is more complicated. */
2ca3ace5
L		 3127 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3128 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3129 i.suffix);
3130 return 0;
252b5132 3131 }
29b0f896
AM		 3132 return 1;
3133}
252b5132 3134
29b0f896 3135static int
e3bb37b5 3136check_word_reg (void)
29b0f896
AM		 3137{
3138 int op;
3139 for (op = i.operands; --op >= 0;)
3140 /* Reject eight bit registers, except where the template requires
3141 them. (eg. movzb) */
3142 if ((i.types[op] & Reg8) != 0
3143 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3144 {
3145 as_bad (_("`%%%s' not allowed with `%s%c'"),
3146 i.op[op].regs->reg_name,
3147 i.tm.name,
3148 i.suffix);
3149 return 0;
3150 }
3151 /* Warn if the e prefix on a general reg is present. */
3152 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3153 && (i.types[op] & Reg32) != 0
3154 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3155 {
29b0f896
AM		 3156 /* Prohibit these changes in the 64bit mode, since the
3157 lowering is more complicated. */
3158 if (flag_code == CODE_64BIT)
252b5132 3159 {
2ca3ace5
L		 3160 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3161 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3162 i.suffix);
3163 return 0;
252b5132 3164 }
29b0f896
AM		 3165 else
3166#if REGISTER_WARNINGS
3167 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3168 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3169 i.op[op].regs->reg_name,
3170 i.suffix);
3171#endif
3172 }
3173 return 1;
3174}
252b5132 3175
29b0f896 3176static int
e3bb37b5 3177finalize_imm (void)
29b0f896
AM		 3178{
3179 unsigned int overlap0, overlap1, overlap2;
3180
3181 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3182 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3183 && overlap0 != Imm8 && overlap0 != Imm8S
3184 && overlap0 != Imm16 && overlap0 != Imm32S
3185 && overlap0 != Imm32 && overlap0 != Imm64)
3186 {
3187 if (i.suffix)
3188 {
3189 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3190 ? Imm8 | Imm8S
3191 : (i.suffix == WORD_MNEM_SUFFIX
3192 ? Imm16
3193 : (i.suffix == QWORD_MNEM_SUFFIX
3194 ? Imm64 | Imm32S
3195 : Imm32)));
3196 }
3197 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3198 || overlap0 == (Imm16 | Imm32)
3199 || overlap0 == (Imm16 | Imm32S))
3200 {
3201 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3202 ? Imm16 : Imm32S);
3203 }
3204 if (overlap0 != Imm8 && overlap0 != Imm8S
3205 && overlap0 != Imm16 && overlap0 != Imm32S
3206 && overlap0 != Imm32 && overlap0 != Imm64)
3207 {
4eed87de
AM		 3208 as_bad (_("no instruction mnemonic suffix given; "
3209 "can't determine immediate size"));
29b0f896
AM		 3210 return 0;
3211 }
3212 }
3213 i.types[0] = overlap0;
3214
3215 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3216 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3217 && overlap1 != Imm8 && overlap1 != Imm8S
3218 && overlap1 != Imm16 && overlap1 != Imm32S
3219 && overlap1 != Imm32 && overlap1 != Imm64)
3220 {
3221 if (i.suffix)
3222 {
3223 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3224 ? Imm8 | Imm8S
3225 : (i.suffix == WORD_MNEM_SUFFIX
3226 ? Imm16
3227 : (i.suffix == QWORD_MNEM_SUFFIX
3228 ? Imm64 | Imm32S
3229 : Imm32)));
3230 }
3231 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3232 || overlap1 == (Imm16 | Imm32)
3233 || overlap1 == (Imm16 | Imm32S))
3234 {
3235 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3236 ? Imm16 : Imm32S);
3237 }
3238 if (overlap1 != Imm8 && overlap1 != Imm8S
3239 && overlap1 != Imm16 && overlap1 != Imm32S
3240 && overlap1 != Imm32 && overlap1 != Imm64)
3241 {
4eed87de
AM		 3242 as_bad (_("no instruction mnemonic suffix given; "
3243 "can't determine immediate size %x %c"),
3244 overlap1, i.suffix);
29b0f896
AM		 3245 return 0;
3246 }
3247 }
3248 i.types[1] = overlap1;
3249
3250 overlap2 = i.types[2] & i.tm.operand_types[2];
3251 assert ((overlap2 & Imm) == 0);
3252 i.types[2] = overlap2;
3253
3254 return 1;
3255}
3256
3257static int
e3bb37b5 3258process_operands (void)
29b0f896
AM		 3259{
3260 /* Default segment register this instruction will use for memory
3261 accesses. 0 means unknown. This is only for optimizing out
3262 unnecessary segment overrides. */
3263 const seg_entry *default_seg = 0;
3264
3265 /* The imul $imm, %reg instruction is converted into
3266 imul $imm, %reg, %reg, and the clr %reg instruction
3267 is converted into xor %reg, %reg. */
3268 if (i.tm.opcode_modifier & regKludge)
3269 {
3270 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3271 /* Pretend we saw the extra register operand. */
cab737b9
L		 3272 assert (i.reg_operands == 1
3273 && i.op[first_reg_op + 1].regs == 0);
29b0f896
AM		 3274 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3275 i.types[first_reg_op + 1] = i.types[first_reg_op];
cab737b9
L		 3276 i.operands++;
3277 i.reg_operands++;
29b0f896
AM		 3278 }
3279
3280 if (i.tm.opcode_modifier & ShortForm)
3281 {
4eed87de 3282 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3283 {
4eed87de
AM		 3284 if (i.tm.base_opcode == POP_SEG_SHORT
3285 && i.op[0].regs->reg_num == 1)
29b0f896 3286 {
4eed87de
AM		 3287 as_bad (_("you can't `pop %%cs'"));
3288 return 0;
29b0f896 3289 }
4eed87de
AM		 3290 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3291 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3292 i.rex |= REX_EXTZ;
3293 }
3294 else
3295 {
3296 /* The register or float register operand is in operand 0 or 1. */
3297 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3298 /* Register goes in low 3 bits of opcode. */
3299 i.tm.base_opcode |= i.op[op].regs->reg_num;
3300 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3301 i.rex |= REX_EXTZ;
3302 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3303 {
4eed87de
AM		 3304 /* Warn about some common errors, but press on regardless.
3305 The first case can be generated by gcc (<= 2.8.1). */
3306 if (i.operands == 2)
3307 {
3308 /* Reversed arguments on faddp, fsubp, etc. */
3309 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3310 i.op[1].regs->reg_name,
3311 i.op[0].regs->reg_name);
3312 }
3313 else
3314 {
3315 /* Extraneous `l' suffix on fp insn. */
3316 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3317 i.op[0].regs->reg_name);
3318 }
29b0f896
AM		 3319 }
3320 }
3321 }
3322 else if (i.tm.opcode_modifier & Modrm)
3323 {
3324 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3325 must be put into the modrm byte). Now, we make the modrm and
3326 index base bytes based on all the info we've collected. */
29b0f896
AM		 3327
3328 default_seg = build_modrm_byte ();
3329 }
8a2ed489 3330 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3331 {
3332 default_seg = &ds;
3333 }
3334 else if ((i.tm.opcode_modifier & IsString) != 0)
3335 {
3336 /* For the string instructions that allow a segment override
3337 on one of their operands, the default segment is ds. */
3338 default_seg = &ds;
3339 }
3340
30123838
JB		 3341 if ((i.tm.base_opcode == 0x8d /* lea */
3342 || (i.tm.cpu_flags & CpuSVME))
3343 && i.seg[0] && !quiet_warnings)
3344 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3345
3346 /* If a segment was explicitly specified, and the specified segment
3347 is not the default, use an opcode prefix to select it. If we
3348 never figured out what the default segment is, then default_seg
3349 will be zero at this point, and the specified segment prefix will
3350 always be used. */
29b0f896
AM		 3351 if ((i.seg[0]) && (i.seg[0] != default_seg))
3352 {
3353 if (!add_prefix (i.seg[0]->seg_prefix))
3354 return 0;
3355 }
3356 return 1;
3357}
3358
3359static const seg_entry *
e3bb37b5 3360build_modrm_byte (void)
29b0f896
AM		 3361{
3362 const seg_entry *default_seg = 0;
3363
3364 /* i.reg_operands MUST be the number of real register operands;
3365 implicit registers do not count. */
3366 if (i.reg_operands == 2)
3367 {
3368 unsigned int source, dest;
cab737b9
L		 3369
3370 switch (i.operands)
3371 {
3372 case 2:
3373 source = 0;
3374 break;
3375 case 3:
c81128dc
L		 3376 /* When there are 3 operands, one of them may be immediate,
3377 which may be the first or the last operand. Otherwise,
3378 the first operand must be shift count register (cl). */
3379 assert (i.imm_operands == 1
3380 || (i.imm_operands == 0
3381 && (i.types[0] & ShiftCount)));
3382 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3383 break;
3384 case 4:
3385 /* When there are 4 operands, the first two must be immediate
3386 operands. The source operand will be the 3rd one. */
3387 assert (i.imm_operands == 2
3388 && (i.types[0] & Imm)
3389 && (i.types[1] & Imm));
3390 source = 2;
3391 break;
3392 default:
3393 abort ();
3394 }
3395
29b0f896
AM		 3396 dest = source + 1;
3397
3398 i.rm.mode = 3;
3399 /* One of the register operands will be encoded in the i.tm.reg
3400 field, the other in the combined i.tm.mode and i.tm.regmem
3401 fields. If no form of this instruction supports a memory
3402 destination operand, then we assume the source operand may
3403 sometimes be a memory operand and so we need to store the
3404 destination in the i.rm.reg field. */
3405 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3406 {
3407 i.rm.reg = i.op[dest].regs->reg_num;
3408 i.rm.regmem = i.op[source].regs->reg_num;
3409 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3410 i.rex |= REX_EXTX;
3411 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3412 i.rex |= REX_EXTZ;
3413 }
3414 else
3415 {
3416 i.rm.reg = i.op[source].regs->reg_num;
3417 i.rm.regmem = i.op[dest].regs->reg_num;
3418 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3419 i.rex |= REX_EXTZ;
3420 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3421 i.rex |= REX_EXTX;
3422 }
c4a530c5
JB		 3423 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3424 {
3425 if (!((i.types[0] | i.types[1]) & Control))
3426 abort ();
3427 i.rex &= ~(REX_EXTX | REX_EXTZ);
3428 add_prefix (LOCK_PREFIX_OPCODE);
3429 }
29b0f896
AM		 3430 }
3431 else
3432 { /* If it's not 2 reg operands... */
3433 if (i.mem_operands)
3434 {
3435 unsigned int fake_zero_displacement = 0;
99018f42 3436 unsigned int op;
4eed87de 3437
99018f42
L		 3438 for (op = 0; op < i.operands; op++)
3439 if ((i.types[op] & AnyMem))
3440 break;
3441 assert (op < i.operands);
29b0f896
AM		 3442
3443 default_seg = &ds;
3444
3445 if (i.base_reg == 0)
3446 {
3447 i.rm.mode = 0;
3448 if (!i.disp_operands)
3449 fake_zero_displacement = 1;
3450 if (i.index_reg == 0)
3451 {
3452 /* Operand is just <disp> */
20f0a1fc 3453 if (flag_code == CODE_64BIT)
29b0f896
AM		 3454 {
3455 /* 64bit mode overwrites the 32bit absolute
3456 addressing by RIP relative addressing and
3457 absolute addressing is encoded by one of the
3458 redundant SIB forms. */
3459 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3460 i.sib.base = NO_BASE_REGISTER;
3461 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3462 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3463 ? Disp32S : Disp32);
20f0a1fc 3464 }
fc225355
L		 3465 else if ((flag_code == CODE_16BIT)
3466 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3467 {
3468 i.rm.regmem = NO_BASE_REGISTER_16;
3469 i.types[op] = Disp16;
3470 }
3471 else
3472 {
3473 i.rm.regmem = NO_BASE_REGISTER;
3474 i.types[op] = Disp32;
29b0f896
AM		 3475 }
3476 }
3477 else /* !i.base_reg && i.index_reg */
3478 {
3479 i.sib.index = i.index_reg->reg_num;
3480 i.sib.base = NO_BASE_REGISTER;
3481 i.sib.scale = i.log2_scale_factor;
3482 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3483 i.types[op] &= ~Disp;
3484 if (flag_code != CODE_64BIT)
3485 i.types[op] |= Disp32; /* Must be 32 bit */
3486 else
3487 i.types[op] |= Disp32S;
3488 if ((i.index_reg->reg_flags & RegRex) != 0)
3489 i.rex |= REX_EXTY;
3490 }
3491 }
3492 /* RIP addressing for 64bit mode. */
3493 else if (i.base_reg->reg_type == BaseIndex)
3494 {
3495 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3496 i.types[op] &= ~ Disp;
29b0f896 3497 i.types[op] |= Disp32S;
71903a11 3498 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3499 if (! i.disp_operands)
3500 fake_zero_displacement = 1;
29b0f896
AM		 3501 }
3502 else if (i.base_reg->reg_type & Reg16)
3503 {
3504 switch (i.base_reg->reg_num)
3505 {
3506 case 3: /* (%bx) */
3507 if (i.index_reg == 0)
3508 i.rm.regmem = 7;
3509 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3510 i.rm.regmem = i.index_reg->reg_num - 6;
3511 break;
3512 case 5: /* (%bp) */
3513 default_seg = &ss;
3514 if (i.index_reg == 0)
3515 {
3516 i.rm.regmem = 6;
3517 if ((i.types[op] & Disp) == 0)
3518 {
3519 /* fake (%bp) into 0(%bp) */
3520 i.types[op] |= Disp8;
252b5132 3521 fake_zero_displacement = 1;
29b0f896
AM		 3522 }
3523 }
3524 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3525 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3526 break;
3527 default: /* (%si) -> 4 or (%di) -> 5 */
3528 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3529 }
3530 i.rm.mode = mode_from_disp_size (i.types[op]);
3531 }
3532 else /* i.base_reg and 32/64 bit mode */
3533 {
3534 if (flag_code == CODE_64BIT
3535 && (i.types[op] & Disp))
fc225355
L		 3536 i.types[op] = ((i.types[op] & Disp8)
3537 | (i.prefix[ADDR_PREFIX] == 0
3538 ? Disp32S : Disp32));
20f0a1fc 3539
29b0f896
AM		 3540 i.rm.regmem = i.base_reg->reg_num;
3541 if ((i.base_reg->reg_flags & RegRex) != 0)
3542 i.rex |= REX_EXTZ;
3543 i.sib.base = i.base_reg->reg_num;
3544 /* x86-64 ignores REX prefix bit here to avoid decoder
3545 complications. */
3546 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3547 {
3548 default_seg = &ss;
3549 if (i.disp_operands == 0)
3550 {
3551 fake_zero_displacement = 1;
3552 i.types[op] |= Disp8;
3553 }
3554 }
3555 else if (i.base_reg->reg_num == ESP_REG_NUM)
3556 {
3557 default_seg = &ss;
3558 }
3559 i.sib.scale = i.log2_scale_factor;
3560 if (i.index_reg == 0)
3561 {
3562 /* <disp>(%esp) becomes two byte modrm with no index
3563 register. We've already stored the code for esp
3564 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3565 Any base register besides %esp will not use the
3566 extra modrm byte. */
3567 i.sib.index = NO_INDEX_REGISTER;
3568#if !SCALE1_WHEN_NO_INDEX
3569 /* Another case where we force the second modrm byte. */
3570 if (i.log2_scale_factor)
3571 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3572#endif
29b0f896
AM		 3573 }
3574 else
3575 {
3576 i.sib.index = i.index_reg->reg_num;
3577 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3578 if ((i.index_reg->reg_flags & RegRex) != 0)
3579 i.rex |= REX_EXTY;
3580 }
67a4f2b7
AO		 3581
3582 if (i.disp_operands
3583 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3584 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3585 i.rm.mode = 0;
3586 else
3587 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3588 }
252b5132 3589
29b0f896
AM		 3590 if (fake_zero_displacement)
3591 {
3592 /* Fakes a zero displacement assuming that i.types[op]
3593 holds the correct displacement size. */
3594 expressionS *exp;
3595
3596 assert (i.op[op].disps == 0);
3597 exp = &disp_expressions[i.disp_operands++];
3598 i.op[op].disps = exp;
3599 exp->X_op = O_constant;
3600 exp->X_add_number = 0;
3601 exp->X_add_symbol = (symbolS *) 0;
3602 exp->X_op_symbol = (symbolS *) 0;
3603 }
3604 }
252b5132 3605
29b0f896
AM		 3606 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3607 (if any) based on i.tm.extension_opcode. Again, we must be
3608 careful to make sure that segment/control/debug/test/MMX
3609 registers are coded into the i.rm.reg field. */
3610 if (i.reg_operands)
3611 {
99018f42
L		 3612 unsigned int op;
3613
3614 for (op = 0; op < i.operands; op++)
3615 if ((i.types[op] & (Reg | RegMMX | RegXMM
3616 | SReg2 | SReg3
3617 | Control | Debug | Test)))
3618 break;
3619 assert (op < i.operands);
3620
29b0f896
AM		 3621 /* If there is an extension opcode to put here, the register
3622 number must be put into the regmem field. */
3623 if (i.tm.extension_opcode != None)
3624 {
3625 i.rm.regmem = i.op[op].regs->reg_num;
3626 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3627 i.rex |= REX_EXTZ;
3628 }
3629 else
3630 {
3631 i.rm.reg = i.op[op].regs->reg_num;
3632 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3633 i.rex |= REX_EXTX;
3634 }
252b5132 3635
29b0f896
AM		 3636 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3637 must set it to 3 to indicate this is a register operand
3638 in the regmem field. */
3639 if (!i.mem_operands)
3640 i.rm.mode = 3;
3641 }
252b5132 3642
29b0f896
AM		 3643 /* Fill in i.rm.reg field with extension opcode (if any). */
3644 if (i.tm.extension_opcode != None)
3645 i.rm.reg = i.tm.extension_opcode;
3646 }
3647 return default_seg;
3648}
252b5132 3649
29b0f896 3650static void
e3bb37b5 3651output_branch (void)
29b0f896
AM		 3652{
3653 char *p;
3654 int code16;
3655 int prefix;
3656 relax_substateT subtype;
3657 symbolS *sym;
3658 offsetT off;
3659
3660 code16 = 0;
3661 if (flag_code == CODE_16BIT)
3662 code16 = CODE16;
3663
3664 prefix = 0;
3665 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3666 {
29b0f896
AM		 3667 prefix = 1;
3668 i.prefixes -= 1;
3669 code16 ^= CODE16;
252b5132 3670 }
29b0f896
AM		 3671 /* Pentium4 branch hints. */
3672 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3673 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3674 {
29b0f896
AM		 3675 prefix++;
3676 i.prefixes--;
3677 }
3678 if (i.prefix[REX_PREFIX] != 0)
3679 {
3680 prefix++;
3681 i.prefixes--;
2f66722d
AM		 3682 }
3683
29b0f896
AM		 3684 if (i.prefixes != 0 && !intel_syntax)
3685 as_warn (_("skipping prefixes on this instruction"));
3686
3687 /* It's always a symbol; End frag & setup for relax.
3688 Make sure there is enough room in this frag for the largest
3689 instruction we may generate in md_convert_frag. This is 2
3690 bytes for the opcode and room for the prefix and largest
3691 displacement. */
3692 frag_grow (prefix + 2 + 4);
3693 /* Prefix and 1 opcode byte go in fr_fix. */
3694 p = frag_more (prefix + 1);
3695 if (i.prefix[DATA_PREFIX] != 0)
3696 *p++ = DATA_PREFIX_OPCODE;
3697 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3698 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3699 *p++ = i.prefix[SEG_PREFIX];
3700 if (i.prefix[REX_PREFIX] != 0)
3701 *p++ = i.prefix[REX_PREFIX];
3702 *p = i.tm.base_opcode;
3703
3704 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3705 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3706 else if ((cpu_arch_flags & Cpu386) != 0)
3707 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3708 else
3709 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3710 subtype |= code16;
3e73aa7c 3711
29b0f896
AM		 3712 sym = i.op[0].disps->X_add_symbol;
3713 off = i.op[0].disps->X_add_number;
3e73aa7c 3714
29b0f896
AM		 3715 if (i.op[0].disps->X_op != O_constant
3716 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3717 {
29b0f896
AM		 3718 /* Handle complex expressions. */
3719 sym = make_expr_symbol (i.op[0].disps);
3720 off = 0;
3721 }
3e73aa7c 3722
29b0f896
AM		 3723 /* 1 possible extra opcode + 4 byte displacement go in var part.
3724 Pass reloc in fr_var. */
3725 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3726}
3e73aa7c 3727
29b0f896 3728static void
e3bb37b5 3729output_jump (void)
29b0f896
AM		 3730{
3731 char *p;
3732 int size;
3e02c1cc 3733 fixS *fixP;
29b0f896
AM		 3734
3735 if (i.tm.opcode_modifier & JumpByte)
3736 {
3737 /* This is a loop or jecxz type instruction. */
3738 size = 1;
3739 if (i.prefix[ADDR_PREFIX] != 0)
3740 {
3741 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3742 i.prefixes -= 1;
3743 }
3744 /* Pentium4 branch hints. */
3745 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3746 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3747 {
3748 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3749 i.prefixes--;
3e73aa7c
JH		 3750 }
3751 }
29b0f896
AM		 3752 else
3753 {
3754 int code16;
3e73aa7c 3755
29b0f896
AM		 3756 code16 = 0;
3757 if (flag_code == CODE_16BIT)
3758 code16 = CODE16;
3e73aa7c 3759
29b0f896
AM		 3760 if (i.prefix[DATA_PREFIX] != 0)
3761 {
3762 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3763 i.prefixes -= 1;
3764 code16 ^= CODE16;
3765 }
252b5132 3766
29b0f896
AM		 3767 size = 4;
3768 if (code16)
3769 size = 2;
3770 }
9fcc94b6 3771
29b0f896
AM		 3772 if (i.prefix[REX_PREFIX] != 0)
3773 {
3774 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3775 i.prefixes -= 1;
3776 }
252b5132 3777
29b0f896
AM		 3778 if (i.prefixes != 0 && !intel_syntax)
3779 as_warn (_("skipping prefixes on this instruction"));
e0890092 3780
29b0f896
AM		 3781 p = frag_more (1 + size);
3782 *p++ = i.tm.base_opcode;
e0890092 3783
3e02c1cc
AM		 3784 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3785 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3786
3787 /* All jumps handled here are signed, but don't use a signed limit
3788 check for 32 and 16 bit jumps as we want to allow wrap around at
3789 4G and 64k respectively. */
3790 if (size == 1)
3791 fixP->fx_signed = 1;
29b0f896 3792}
e0890092 3793
29b0f896 3794static void
e3bb37b5 3795output_interseg_jump (void)
29b0f896
AM		 3796{
3797 char *p;
3798 int size;
3799 int prefix;
3800 int code16;
252b5132 3801
29b0f896
AM		 3802 code16 = 0;
3803 if (flag_code == CODE_16BIT)
3804 code16 = CODE16;
a217f122 3805
29b0f896
AM		 3806 prefix = 0;
3807 if (i.prefix[DATA_PREFIX] != 0)
3808 {
3809 prefix = 1;
3810 i.prefixes -= 1;
3811 code16 ^= CODE16;
3812 }
3813 if (i.prefix[REX_PREFIX] != 0)
3814 {
3815 prefix++;
3816 i.prefixes -= 1;
3817 }
252b5132 3818
29b0f896
AM		 3819 size = 4;
3820 if (code16)
3821 size = 2;
252b5132 3822
29b0f896
AM		 3823 if (i.prefixes != 0 && !intel_syntax)
3824 as_warn (_("skipping prefixes on this instruction"));
252b5132 3825
29b0f896
AM		 3826 /* 1 opcode; 2 segment; offset */
3827 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3828
29b0f896
AM		 3829 if (i.prefix[DATA_PREFIX] != 0)
3830 *p++ = DATA_PREFIX_OPCODE;
252b5132 3831
29b0f896
AM		 3832 if (i.prefix[REX_PREFIX] != 0)
3833 *p++ = i.prefix[REX_PREFIX];
252b5132 3834
29b0f896
AM		 3835 *p++ = i.tm.base_opcode;
3836 if (i.op[1].imms->X_op == O_constant)
3837 {
3838 offsetT n = i.op[1].imms->X_add_number;
252b5132 3839
29b0f896
AM		 3840 if (size == 2
3841 && !fits_in_unsigned_word (n)
3842 && !fits_in_signed_word (n))
3843 {
3844 as_bad (_("16-bit jump out of range"));
3845 return;
3846 }
3847 md_number_to_chars (p, n, size);
3848 }
3849 else
3850 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3851 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3852 if (i.op[0].imms->X_op != O_constant)
3853 as_bad (_("can't handle non absolute segment in `%s'"),
3854 i.tm.name);
3855 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3856}
a217f122 3857
29b0f896 3858static void
e3bb37b5 3859output_insn (void)
29b0f896 3860{
2bbd9c25
JJ		 3861 fragS *insn_start_frag;
3862 offsetT insn_start_off;
3863
29b0f896
AM		 3864 /* Tie dwarf2 debug info to the address at the start of the insn.
3865 We can't do this after the insn has been output as the current
3866 frag may have been closed off. eg. by frag_var. */
3867 dwarf2_emit_insn (0);
3868
2bbd9c25
JJ		 3869 insn_start_frag = frag_now;
3870 insn_start_off = frag_now_fix ();
3871
29b0f896
AM		 3872 /* Output jumps. */
3873 if (i.tm.opcode_modifier & Jump)
3874 output_branch ();
3875 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3876 output_jump ();
3877 else if (i.tm.opcode_modifier & JumpInterSegment)
3878 output_interseg_jump ();
3879 else
3880 {
3881 /* Output normal instructions here. */
3882 char *p;
3883 unsigned char *q;
331d2d0d 3884 unsigned int prefix;
252b5132 3885
ef05d495
L		 3886 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3887 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3888 use one more higher byte to specify a prefix the instruction
3889 requires. */
3890 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
bc4bd9ab 3891 {
331d2d0d
L		 3892 if (i.tm.base_opcode & 0xff000000)
3893 {
3894 prefix = (i.tm.base_opcode >> 24) & 0xff;
3895 goto check_prefix;
3896 }
3897 }
3898 else if ((i.tm.base_opcode & 0xff0000) != 0)
3899 {
3900 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3901 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3902 {
64e74474 3903 check_prefix:
bc4bd9ab
MK		 3904 if (prefix != REPE_PREFIX_OPCODE
3905 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3906 add_prefix (prefix);
3907 }
3908 else
331d2d0d 3909 add_prefix (prefix);
0f10071e 3910 }
252b5132 3911
29b0f896
AM		 3912 /* The prefix bytes. */
3913 for (q = i.prefix;
3914 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3915 q++)
3916 {
3917 if (*q)
3918 {
3919 p = frag_more (1);
3920 md_number_to_chars (p, (valueT) *q, 1);
3921 }
3922 }
252b5132 3923
29b0f896
AM		 3924 /* Now the opcode; be careful about word order here! */
3925 if (fits_in_unsigned_byte (i.tm.base_opcode))
3926 {
3927 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3928 }
3929 else
3930 {
ef05d495 3931 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
331d2d0d
L		 3932 {
3933 p = frag_more (3);
3934 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3935 }
3936 else
3937 p = frag_more (2);
0f10071e 3938
29b0f896
AM		 3939 /* Put out high byte first: can't use md_number_to_chars! */
3940 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3941 *p = i.tm.base_opcode & 0xff;
3942 }
3e73aa7c 3943
29b0f896
AM		 3944 /* Now the modrm byte and sib byte (if present). */
3945 if (i.tm.opcode_modifier & Modrm)
3946 {
3947 p = frag_more (1);
3948 md_number_to_chars (p,
3949 (valueT) (i.rm.regmem << 0
3950 | i.rm.reg << 3
3951 | i.rm.mode << 6),
3952 1);
3953 /* If i.rm.regmem == ESP (4)
3954 && i.rm.mode != (Register mode)
3955 && not 16 bit
3956 ==> need second modrm byte. */
3957 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3958 && i.rm.mode != 3
3959 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3960 {
3961 p = frag_more (1);
3962 md_number_to_chars (p,
3963 (valueT) (i.sib.base << 0
3964 | i.sib.index << 3
3965 | i.sib.scale << 6),
3966 1);
3967 }
3968 }
3e73aa7c 3969
29b0f896 3970 if (i.disp_operands)
2bbd9c25 3971 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3972
29b0f896 3973 if (i.imm_operands)
2bbd9c25 3974 output_imm (insn_start_frag, insn_start_off);
29b0f896 3975 }
252b5132 3976
29b0f896
AM		 3977#ifdef DEBUG386
3978 if (flag_debug)
3979 {
7b81dfbb 3980 pi ("" /*line*/, &i);
29b0f896
AM		 3981 }
3982#endif /* DEBUG386 */
3983}
252b5132 3984
29b0f896 3985static void
64e74474 3986output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3987{
3988 char *p;
3989 unsigned int n;
252b5132 3990
29b0f896
AM		 3991 for (n = 0; n < i.operands; n++)
3992 {
3993 if (i.types[n] & Disp)
3994 {
3995 if (i.op[n].disps->X_op == O_constant)
3996 {
3997 int size;
3998 offsetT val;
252b5132 3999
29b0f896
AM		 4000 size = 4;
4001 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4002 {
4003 size = 2;
4004 if (i.types[n] & Disp8)
4005 size = 1;
4006 if (i.types[n] & Disp64)
4007 size = 8;
4008 }
4009 val = offset_in_range (i.op[n].disps->X_add_number,
4010 size);
4011 p = frag_more (size);
4012 md_number_to_chars (p, val, size);
4013 }
4014 else
4015 {
f86103b7 4016 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4017 int size = 4;
4018 int sign = 0;
4019 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4020
4021 /* The PC relative address is computed relative
4022 to the instruction boundary, so in case immediate
4023 fields follows, we need to adjust the value. */
4024 if (pcrel && i.imm_operands)
4025 {
4026 int imm_size = 4;
4027 unsigned int n1;
252b5132 4028
29b0f896
AM		 4029 for (n1 = 0; n1 < i.operands; n1++)
4030 if (i.types[n1] & Imm)
252b5132 4031 {
29b0f896 4032 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4033 {
29b0f896
AM		 4034 imm_size = 2;
4035 if (i.types[n1] & (Imm8 | Imm8S))
4036 imm_size = 1;
4037 if (i.types[n1] & Imm64)
4038 imm_size = 8;
252b5132 4039 }
29b0f896 4040 break;
252b5132 4041 }
29b0f896
AM		 4042 /* We should find the immediate. */
4043 if (n1 == i.operands)
4044 abort ();
4045 i.op[n].disps->X_add_number -= imm_size;
4046 }
520dc8e8 4047
29b0f896
AM		 4048 if (i.types[n] & Disp32S)
4049 sign = 1;
3e73aa7c 4050
29b0f896
AM		 4051 if (i.types[n] & (Disp16 | Disp64))
4052 {
4053 size = 2;
4054 if (i.types[n] & Disp64)
4055 size = 8;
4056 }
520dc8e8 4057
29b0f896 4058 p = frag_more (size);
2bbd9c25 4059 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4060 if (GOT_symbol
2bbd9c25 4061 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4062 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4063 || reloc_type == BFD_RELOC_X86_64_32S
4064 || (reloc_type == BFD_RELOC_64
4065 && object_64bit))
d6ab8113
JB		 4066 && (i.op[n].disps->X_op == O_symbol
4067 || (i.op[n].disps->X_op == O_add
4068 && ((symbol_get_value_expression
4069 (i.op[n].disps->X_op_symbol)->X_op)
4070 == O_subtract))))
4071 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4072 {
4073 offsetT add;
4074
4075 if (insn_start_frag == frag_now)
4076 add = (p - frag_now->fr_literal) - insn_start_off;
4077 else
4078 {
4079 fragS *fr;
4080
4081 add = insn_start_frag->fr_fix - insn_start_off;
4082 for (fr = insn_start_frag->fr_next;
4083 fr && fr != frag_now; fr = fr->fr_next)
4084 add += fr->fr_fix;
4085 add += p - frag_now->fr_literal;
4086 }
4087
4fa24527 4088 if (!object_64bit)
7b81dfbb
AJ		 4089 {
4090 reloc_type = BFD_RELOC_386_GOTPC;
4091 i.op[n].imms->X_add_number += add;
4092 }
4093 else if (reloc_type == BFD_RELOC_64)
4094 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4095 else
7b81dfbb
AJ		 4096 /* Don't do the adjustment for x86-64, as there
4097 the pcrel addressing is relative to the _next_
4098 insn, and that is taken care of in other code. */
d6ab8113 4099 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4100 }
062cd5e7 4101 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4102 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4103 }
4104 }
4105 }
4106}
252b5132 4107
29b0f896 4108static void
64e74474 4109output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4110{
4111 char *p;
4112 unsigned int n;
252b5132 4113
29b0f896
AM		 4114 for (n = 0; n < i.operands; n++)
4115 {
4116 if (i.types[n] & Imm)
4117 {
4118 if (i.op[n].imms->X_op == O_constant)
4119 {
4120 int size;
4121 offsetT val;
b4cac588 4122
29b0f896
AM		 4123 size = 4;
4124 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4125 {
4126 size = 2;
4127 if (i.types[n] & (Imm8 | Imm8S))
4128 size = 1;
4129 else if (i.types[n] & Imm64)
4130 size = 8;
4131 }
4132 val = offset_in_range (i.op[n].imms->X_add_number,
4133 size);
4134 p = frag_more (size);
4135 md_number_to_chars (p, val, size);
4136 }
4137 else
4138 {
4139 /* Not absolute_section.
4140 Need a 32-bit fixup (don't support 8bit
4141 non-absolute imms). Try to support other
4142 sizes ... */
f86103b7 4143 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4144 int size = 4;
4145 int sign = 0;
4146
4147 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4148 && (i.suffix == QWORD_MNEM_SUFFIX
4149 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4150 sign = 1;
4151 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4152 {
4153 size = 2;
4154 if (i.types[n] & (Imm8 | Imm8S))
4155 size = 1;
4156 if (i.types[n] & Imm64)
4157 size = 8;
4158 }
520dc8e8 4159
29b0f896
AM		 4160 p = frag_more (size);
4161 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4162
2bbd9c25
JJ		 4163 /* This is tough to explain. We end up with this one if we
4164 * have operands that look like
4165 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4166 * obtain the absolute address of the GOT, and it is strongly
4167 * preferable from a performance point of view to avoid using
4168 * a runtime relocation for this. The actual sequence of
4169 * instructions often look something like:
4170 *
4171 * call .L66
4172 * .L66:
4173 * popl %ebx
4174 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4175 *
4176 * The call and pop essentially return the absolute address
4177 * of the label .L66 and store it in %ebx. The linker itself
4178 * will ultimately change the first operand of the addl so
4179 * that %ebx points to the GOT, but to keep things simple, the
4180 * .o file must have this operand set so that it generates not
4181 * the absolute address of .L66, but the absolute address of
4182 * itself. This allows the linker itself simply treat a GOTPC
4183 * relocation as asking for a pcrel offset to the GOT to be
4184 * added in, and the addend of the relocation is stored in the
4185 * operand field for the instruction itself.
4186 *
4187 * Our job here is to fix the operand so that it would add
4188 * the correct offset so that %ebx would point to itself. The
4189 * thing that is tricky is that .-.L66 will point to the
4190 * beginning of the instruction, so we need to further modify
4191 * the operand so that it will point to itself. There are
4192 * other cases where you have something like:
4193 *
4194 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4195 *
4196 * and here no correction would be required. Internally in
4197 * the assembler we treat operands of this form as not being
4198 * pcrel since the '.' is explicitly mentioned, and I wonder
4199 * whether it would simplify matters to do it this way. Who
4200 * knows. In earlier versions of the PIC patches, the
4201 * pcrel_adjust field was used to store the correction, but
4202 * since the expression is not pcrel, I felt it would be
4203 * confusing to do it this way. */
4204
d6ab8113 4205 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4206 || reloc_type == BFD_RELOC_X86_64_32S
4207 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4208 && GOT_symbol
4209 && GOT_symbol == i.op[n].imms->X_add_symbol
4210 && (i.op[n].imms->X_op == O_symbol
4211 || (i.op[n].imms->X_op == O_add
4212 && ((symbol_get_value_expression
4213 (i.op[n].imms->X_op_symbol)->X_op)
4214 == O_subtract))))
4215 {
2bbd9c25
JJ		 4216 offsetT add;
4217
4218 if (insn_start_frag == frag_now)
4219 add = (p - frag_now->fr_literal) - insn_start_off;
4220 else
4221 {
4222 fragS *fr;
4223
4224 add = insn_start_frag->fr_fix - insn_start_off;
4225 for (fr = insn_start_frag->fr_next;
4226 fr && fr != frag_now; fr = fr->fr_next)
4227 add += fr->fr_fix;
4228 add += p - frag_now->fr_literal;
4229 }
4230
4fa24527 4231 if (!object_64bit)
d6ab8113 4232 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4233 else if (size == 4)
d6ab8113 4234 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4235 else if (size == 8)
4236 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4237 i.op[n].imms->X_add_number += add;
29b0f896 4238 }
29b0f896
AM		 4239 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4240 i.op[n].imms, 0, reloc_type);
4241 }
4242 }
4243 }
252b5132
RH		 4244}
4245\f
d182319b
JB		 4246/* x86_cons_fix_new is called via the expression parsing code when a
4247 reloc is needed. We use this hook to get the correct .got reloc. */
4248static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4249static int cons_sign = -1;
4250
4251void
e3bb37b5 4252x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4253 expressionS *exp)
d182319b
JB		 4254{
4255 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4256
4257 got_reloc = NO_RELOC;
4258
4259#ifdef TE_PE
4260 if (exp->X_op == O_secrel)
4261 {
4262 exp->X_op = O_symbol;
4263 r = BFD_RELOC_32_SECREL;
4264 }
4265#endif
4266
4267 fix_new_exp (frag, off, len, exp, 0, r);
4268}
4269
718ddfc0
JB		 4270#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4271# define lex_got(reloc, adjust, types) NULL
4272#else
f3c180ae
AM		 4273/* Parse operands of the form
4274 <symbol>@GOTOFF+<nnn>
4275 and similar .plt or .got references.
4276
4277 If we find one, set up the correct relocation in RELOC and copy the
4278 input string, minus the `@GOTOFF' into a malloc'd buffer for
4279 parsing by the calling routine. Return this buffer, and if ADJUST
4280 is non-null set it to the length of the string we removed from the
4281 input line. Otherwise return NULL. */
4282static char *
3956db08 4283lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4284 int *adjust,
4285 unsigned int *types)
f3c180ae 4286{
7b81dfbb
AJ		 4287 /* Some of the relocations depend on the size of what field is to
4288 be relocated. But in our callers i386_immediate and i386_displacement
4289 we don't yet know the operand size (this will be set by insn
4290 matching). Hence we record the word32 relocation here,
4291 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4292 static const struct {
4293 const char *str;
4fa24527 4294 const enum bfd_reloc_code_real rel[2];
3956db08 4295 const unsigned int types64;
f3c180ae 4296 } gotrel[] = {
4eed87de
AM		 4297 { "PLTOFF", { 0,
4298 BFD_RELOC_X86_64_PLTOFF64 },
4299 Imm64 },
4300 { "PLT", { BFD_RELOC_386_PLT32,
4301 BFD_RELOC_X86_64_PLT32 },
4302 Imm32 | Imm32S | Disp32 },
4303 { "GOTPLT", { 0,
4304 BFD_RELOC_X86_64_GOTPLT64 },
4305 Imm64 | Disp64 },
4306 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4307 BFD_RELOC_X86_64_GOTOFF64 },
4308 Imm64 | Disp64 },
4309 { "GOTPCREL", { 0,
4310 BFD_RELOC_X86_64_GOTPCREL },
4311 Imm32 | Imm32S | Disp32 },
4312 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4313 BFD_RELOC_X86_64_TLSGD },
4314 Imm32 | Imm32S | Disp32 },
4315 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4316 0 },
4317 0 },
4318 { "TLSLD", { 0,
4319 BFD_RELOC_X86_64_TLSLD },
4320 Imm32 | Imm32S | Disp32 },
4321 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4322 BFD_RELOC_X86_64_GOTTPOFF },
4323 Imm32 | Imm32S | Disp32 },
4324 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4325 BFD_RELOC_X86_64_TPOFF32 },
4326 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4327 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4328 0 },
4329 0 },
4330 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4331 BFD_RELOC_X86_64_DTPOFF32 },
4332 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4333 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4334 0 },
4335 0 },
4336 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4337 0 },
4338 0 },
4339 { "GOT", { BFD_RELOC_386_GOT32,
4340 BFD_RELOC_X86_64_GOT32 },
4341 Imm32 | Imm32S | Disp32 | Imm64 },
4342 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4343 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4344 Imm32 | Imm32S | Disp32 },
4345 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4346 BFD_RELOC_X86_64_TLSDESC_CALL },
4347 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4348 };
4349 char *cp;
4350 unsigned int j;
4351
718ddfc0
JB		 4352 if (!IS_ELF)
4353 return NULL;
4354
f3c180ae
AM		 4355 for (cp = input_line_pointer; *cp != '@'; cp++)
4356 if (is_end_of_line[(unsigned char) *cp])
4357 return NULL;
4358
4359 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4360 {
4361 int len;
4362
4363 len = strlen (gotrel[j].str);
28f81592 4364 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4365 {
4fa24527 4366 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4367 {
28f81592
AM		 4368 int first, second;
4369 char *tmpbuf, *past_reloc;
f3c180ae 4370
4fa24527 4371 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4372 if (adjust)
4373 *adjust = len;
f3c180ae 4374
3956db08
JB		 4375 if (types)
4376 {
4377 if (flag_code != CODE_64BIT)
4eed87de 4378 *types = Imm32 | Disp32;
3956db08
JB		 4379 else
4380 *types = gotrel[j].types64;
4381 }
4382
f3c180ae
AM		 4383 if (GOT_symbol == NULL)
4384 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4385
4386 /* Replace the relocation token with ' ', so that
4387 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4388
4389 /* The length of the first part of our input line. */
f3c180ae 4390 first = cp - input_line_pointer;
28f81592
AM		 4391
4392 /* The second part goes from after the reloc token until
4393 (and including) an end_of_line char. Don't use strlen
4394 here as the end_of_line char may not be a NUL. */
4395 past_reloc = cp + 1 + len;
4396 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4397 ;
4398 second = cp - past_reloc;
4399
4400 /* Allocate and copy string. The trailing NUL shouldn't
4401 be necessary, but be safe. */
4402 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4403 memcpy (tmpbuf, input_line_pointer, first);
4404 tmpbuf[first] = ' ';
28f81592
AM		 4405 memcpy (tmpbuf + first + 1, past_reloc, second);
4406 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4407 return tmpbuf;
4408 }
4409
4fa24527
JB		 4410 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4411 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4412 return NULL;
4413 }
4414 }
4415
4416 /* Might be a symbol version string. Don't as_bad here. */
4417 return NULL;
4418}
4419
f3c180ae 4420void
e3bb37b5 4421x86_cons (expressionS *exp, int size)
f3c180ae 4422{
4fa24527 4423 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4424 {
4425 /* Handle @GOTOFF and the like in an expression. */
4426 char *save;
4427 char *gotfree_input_line;
4428 int adjust;
4429
4430 save = input_line_pointer;
3956db08 4431 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4432 if (gotfree_input_line)
4433 input_line_pointer = gotfree_input_line;
4434
4435 expression (exp);
4436
4437 if (gotfree_input_line)
4438 {
4439 /* expression () has merrily parsed up to the end of line,
4440 or a comma - in the wrong buffer. Transfer how far
4441 input_line_pointer has moved to the right buffer. */
4442 input_line_pointer = (save
4443 + (input_line_pointer - gotfree_input_line)
4444 + adjust);
4445 free (gotfree_input_line);
4446 }
4447 }
4448 else
4449 expression (exp);
4450}
4451#endif
4452
d182319b 4453static void signed_cons (int size)
6482c264 4454{
d182319b
JB		 4455 if (flag_code == CODE_64BIT)
4456 cons_sign = 1;
4457 cons (size);
4458 cons_sign = -1;
6482c264
NC		 4459}
4460
d182319b 4461#ifdef TE_PE
6482c264
NC		 4462static void
4463pe_directive_secrel (dummy)
4464 int dummy ATTRIBUTE_UNUSED;
4465{
4466 expressionS exp;
4467
4468 do
4469 {
4470 expression (&exp);
4471 if (exp.X_op == O_symbol)
4472 exp.X_op = O_secrel;
4473
4474 emit_expr (&exp, 4);
4475 }
4476 while (*input_line_pointer++ == ',');
4477
4478 input_line_pointer--;
4479 demand_empty_rest_of_line ();
4480}
6482c264
NC		 4481#endif
4482
252b5132 4483static int
70e41ade 4484i386_immediate (char *imm_start)
252b5132
RH		 4485{
4486 char *save_input_line_pointer;
f3c180ae 4487 char *gotfree_input_line;
252b5132 4488 segT exp_seg = 0;
47926f60 4489 expressionS *exp;
3956db08 4490 unsigned int types = ~0U;
252b5132
RH		 4491
4492 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4493 {
31b2323c
L		 4494 as_bad (_("at most %d immediate operands are allowed"),
4495 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4496 return 0;
4497 }
4498
4499 exp = &im_expressions[i.imm_operands++];
520dc8e8 4500 i.op[this_operand].imms = exp;
252b5132
RH		 4501
4502 if (is_space_char (*imm_start))
4503 ++imm_start;
4504
4505 save_input_line_pointer = input_line_pointer;
4506 input_line_pointer = imm_start;
4507
3956db08 4508 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4509 if (gotfree_input_line)
4510 input_line_pointer = gotfree_input_line;
252b5132
RH		 4511
4512 exp_seg = expression (exp);
4513
83183c0c 4514 SKIP_WHITESPACE ();
252b5132 4515 if (*input_line_pointer)
f3c180ae 4516 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4517
4518 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4519 if (gotfree_input_line)
4520 free (gotfree_input_line);
252b5132 4521
2daf4fd8 4522 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4523 {
47926f60 4524 /* Missing or bad expr becomes absolute 0. */
d0b47220 4525 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4526 imm_start);
252b5132
RH		 4527 exp->X_op = O_constant;
4528 exp->X_add_number = 0;
4529 exp->X_add_symbol = (symbolS *) 0;
4530 exp->X_op_symbol = (symbolS *) 0;
252b5132 4531 }
3e73aa7c 4532 else if (exp->X_op == O_constant)
252b5132 4533 {
47926f60 4534 /* Size it properly later. */
3e73aa7c
JH		 4535 i.types[this_operand] |= Imm64;
4536 /* If BFD64, sign extend val. */
4eed87de
AM		 4537 if (!use_rela_relocations
4538 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4539 exp->X_add_number
4540 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4541 }
4c63da97 4542#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4543 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4544 && exp_seg != absolute_section
47926f60 4545 && exp_seg != text_section
24eab124
AM		 4546 && exp_seg != data_section
4547 && exp_seg != bss_section
4548 && exp_seg != undefined_section
f86103b7 4549 && !bfd_is_com_section (exp_seg))
252b5132 4550 {
d0b47220 4551 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4552 return 0;
4553 }
4554#endif
bb8f5920
L		 4555 else if (!intel_syntax && exp->X_op == O_register)
4556 {
4557 as_bad (_("illegal immediate register operand %s"), imm_start);
4558 return 0;
4559 }
252b5132
RH		 4560 else
4561 {
4562 /* This is an address. The size of the address will be
24eab124 4563 determined later, depending on destination register,
3e73aa7c
JH		 4564 suffix, or the default for the section. */
4565 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4566 i.types[this_operand] &= types;
252b5132
RH		 4567 }
4568
4569 return 1;
4570}
4571
551c1ca1 4572static char *
e3bb37b5 4573i386_scale (char *scale)
252b5132 4574{
551c1ca1
AM		 4575 offsetT val;
4576 char *save = input_line_pointer;
252b5132 4577
551c1ca1
AM		 4578 input_line_pointer = scale;
4579 val = get_absolute_expression ();
4580
4581 switch (val)
252b5132 4582 {
551c1ca1 4583 case 1:
252b5132
RH		 4584 i.log2_scale_factor = 0;
4585 break;
551c1ca1 4586 case 2:
252b5132
RH		 4587 i.log2_scale_factor = 1;
4588 break;
551c1ca1 4589 case 4:
252b5132
RH		 4590 i.log2_scale_factor = 2;
4591 break;
551c1ca1 4592 case 8:
252b5132
RH		 4593 i.log2_scale_factor = 3;
4594 break;
4595 default:
a724f0f4
JB		 4596 {
4597 char sep = *input_line_pointer;
4598
4599 *input_line_pointer = '\0';
4600 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4601 scale);
4602 *input_line_pointer = sep;
4603 input_line_pointer = save;
4604 return NULL;
4605 }
252b5132 4606 }
29b0f896 4607 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4608 {
4609 as_warn (_("scale factor of %d without an index register"),
24eab124 4610 1 << i.log2_scale_factor);
252b5132
RH		 4611#if SCALE1_WHEN_NO_INDEX
4612 i.log2_scale_factor = 0;
4613#endif
4614 }
551c1ca1
AM		 4615 scale = input_line_pointer;
4616 input_line_pointer = save;
4617 return scale;
252b5132
RH		 4618}
4619
252b5132 4620static int
e3bb37b5 4621i386_displacement (char *disp_start, char *disp_end)
252b5132 4622{
29b0f896 4623 expressionS *exp;
252b5132
RH		 4624 segT exp_seg = 0;
4625 char *save_input_line_pointer;
f3c180ae 4626 char *gotfree_input_line;
e05278af 4627 int bigdisp, override;
3956db08 4628 unsigned int types = Disp;
252b5132 4629
31b2323c
L		 4630 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4631 {
4632 as_bad (_("at most %d displacement operands are allowed"),
4633 MAX_MEMORY_OPERANDS);
4634 return 0;
4635 }
4636
e05278af
JB		 4637 if ((i.types[this_operand] & JumpAbsolute)
4638 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4639 {
4640 bigdisp = Disp32;
4641 override = (i.prefix[ADDR_PREFIX] != 0);
4642 }
4643 else
4644 {
4645 /* For PC-relative branches, the width of the displacement
4646 is dependent upon data size, not address size. */
4647 bigdisp = 0;
4648 override = (i.prefix[DATA_PREFIX] != 0);
4649 }
3e73aa7c 4650 if (flag_code == CODE_64BIT)
7ecd2f8b 4651 {
e05278af 4652 if (!bigdisp)
64e74474
AM		 4653 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4654 ? Disp16
4655 : Disp32S | Disp32);
e05278af 4656 else if (!override)
3956db08 4657 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4658 }
e05278af
JB		 4659 else
4660 {
4661 if (!bigdisp)
4662 {
4663 if (!override)
4664 override = (i.suffix == (flag_code != CODE_16BIT
4665 ? WORD_MNEM_SUFFIX
4666 : LONG_MNEM_SUFFIX));
4667 bigdisp = Disp32;
4668 }
4669 if ((flag_code == CODE_16BIT) ^ override)
4670 bigdisp = Disp16;
4671 }
252b5132
RH		 4672 i.types[this_operand] |= bigdisp;
4673
4674 exp = &disp_expressions[i.disp_operands];
520dc8e8 4675 i.op[this_operand].disps = exp;
252b5132
RH		 4676 i.disp_operands++;
4677 save_input_line_pointer = input_line_pointer;
4678 input_line_pointer = disp_start;
4679 END_STRING_AND_SAVE (disp_end);
4680
4681#ifndef GCC_ASM_O_HACK
4682#define GCC_ASM_O_HACK 0
4683#endif
4684#if GCC_ASM_O_HACK
4685 END_STRING_AND_SAVE (disp_end + 1);
4686 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4687 && displacement_string_end[-1] == '+')
252b5132
RH		 4688 {
4689 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4690 constraint within gcc asm statements.
4691 For instance:
4692
4693 #define _set_tssldt_desc(n,addr,limit,type) \
4694 __asm__ __volatile__ ( \
4695 "movw %w2,%0\n\t" \
4696 "movw %w1,2+%0\n\t" \
4697 "rorl $16,%1\n\t" \
4698 "movb %b1,4+%0\n\t" \
4699 "movb %4,5+%0\n\t" \
4700 "movb $0,6+%0\n\t" \
4701 "movb %h1,7+%0\n\t" \
4702 "rorl $16,%1" \
4703 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4704
4705 This works great except that the output assembler ends
4706 up looking a bit weird if it turns out that there is
4707 no offset. You end up producing code that looks like:
4708
4709 #APP
4710 movw $235,(%eax)
4711 movw %dx,2+(%eax)
4712 rorl $16,%edx
4713 movb %dl,4+(%eax)
4714 movb $137,5+(%eax)
4715 movb $0,6+(%eax)
4716 movb %dh,7+(%eax)
4717 rorl $16,%edx
4718 #NO_APP
4719
47926f60 4720 So here we provide the missing zero. */
24eab124
AM		 4721
4722 *displacement_string_end = '0';
252b5132
RH		 4723 }
4724#endif
3956db08 4725 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4726 if (gotfree_input_line)
4727 input_line_pointer = gotfree_input_line;
252b5132 4728
24eab124 4729 exp_seg = expression (exp);
252b5132 4730
636c26b0
AM		 4731 SKIP_WHITESPACE ();
4732 if (*input_line_pointer)
4733 as_bad (_("junk `%s' after expression"), input_line_pointer);
4734#if GCC_ASM_O_HACK
4735 RESTORE_END_STRING (disp_end + 1);
4736#endif
4737 RESTORE_END_STRING (disp_end);
4738 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4739 if (gotfree_input_line)
4740 free (gotfree_input_line);
636c26b0 4741
24eab124
AM		 4742 /* We do this to make sure that the section symbol is in
4743 the symbol table. We will ultimately change the relocation
47926f60 4744 to be relative to the beginning of the section. */
1ae12ab7 4745 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4746 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4747 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4748 {
636c26b0
AM		 4749 if (exp->X_op != O_symbol)
4750 {
4751 as_bad (_("bad expression used with @%s"),
4752 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4753 ? "GOTPCREL"
4754 : "GOTOFF"));
4755 return 0;
4756 }
4757
e5cb08ac 4758 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4759 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4760 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4761 exp->X_op = O_subtract;
4762 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4763 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4764 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4765 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4766 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4767 else
29b0f896 4768 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4769 }
252b5132 4770
2daf4fd8
AM		 4771 if (exp->X_op == O_absent || exp->X_op == O_big)
4772 {
47926f60 4773 /* Missing or bad expr becomes absolute 0. */
d0b47220 4774 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4775 disp_start);
4776 exp->X_op = O_constant;
4777 exp->X_add_number = 0;
4778 exp->X_add_symbol = (symbolS *) 0;
4779 exp->X_op_symbol = (symbolS *) 0;
4780 }
4781
4c63da97 4782#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4783 if (exp->X_op != O_constant
45288df1 4784 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4785 && exp_seg != absolute_section
45288df1
AM		 4786 && exp_seg != text_section
4787 && exp_seg != data_section
4788 && exp_seg != bss_section
31312f95 4789 && exp_seg != undefined_section
f86103b7 4790 && !bfd_is_com_section (exp_seg))
24eab124 4791 {
d0b47220 4792 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4793 return 0;
4794 }
252b5132 4795#endif
3956db08
JB		 4796
4797 if (!(i.types[this_operand] & ~Disp))
4798 i.types[this_operand] &= types;
4799
252b5132
RH		 4800 return 1;
4801}
4802
eecb386c 4803/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4804 Return 1 on success, 0 on a failure. */
4805
252b5132 4806static int
e3bb37b5 4807i386_index_check (const char *operand_string)
252b5132 4808{
3e73aa7c 4809 int ok;
24eab124 4810#if INFER_ADDR_PREFIX
eecb386c
AM		 4811 int fudged = 0;
4812
24eab124
AM		 4813 tryprefix:
4814#endif
3e73aa7c 4815 ok = 1;
30123838
JB		 4816 if ((current_templates->start->cpu_flags & CpuSVME)
4817 && current_templates->end[-1].operand_types[0] == AnyMem)
4818 {
4819 /* Memory operands of SVME insns are special in that they only allow
4820 rAX as their memory address and ignore any segment override. */
4821 unsigned RegXX;
4822
4823 /* SKINIT is even more restrictive: it always requires EAX. */
4824 if (strcmp (current_templates->start->name, "skinit") == 0)
4825 RegXX = Reg32;
4826 else if (flag_code == CODE_64BIT)
4827 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4828 else
64e74474
AM		 4829 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4830 ? Reg16
4831 : Reg32);
30123838
JB		 4832 if (!i.base_reg
4833 || !(i.base_reg->reg_type & Acc)
4834 || !(i.base_reg->reg_type & RegXX)
4835 || i.index_reg
4836 || (i.types[0] & Disp))
4837 ok = 0;
4838 }
4839 else if (flag_code == CODE_64BIT)
64e74474
AM		 4840 {
4841 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4842
4843 if ((i.base_reg
4844 && ((i.base_reg->reg_type & RegXX) == 0)
4845 && (i.base_reg->reg_type != BaseIndex
4846 || i.index_reg))
4847 || (i.index_reg
4848 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4849 != (RegXX | BaseIndex))))
4850 ok = 0;
3e73aa7c
JH		 4851 }
4852 else
4853 {
4854 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4855 {
4856 /* 16bit checks. */
4857 if ((i.base_reg
29b0f896
AM		 4858 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4859 != (Reg16 | BaseIndex)))
3e73aa7c 4860 || (i.index_reg
29b0f896
AM		 4861 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4862 != (Reg16 | BaseIndex))
4863 || !(i.base_reg
4864 && i.base_reg->reg_num < 6
4865 && i.index_reg->reg_num >= 6
4866 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4867 ok = 0;
4868 }
4869 else
e5cb08ac 4870 {
3e73aa7c
JH		 4871 /* 32bit checks. */
4872 if ((i.base_reg
4873 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4874 || (i.index_reg
29b0f896
AM		 4875 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4876 != (Reg32 | BaseIndex))))
e5cb08ac 4877 ok = 0;
3e73aa7c
JH		 4878 }
4879 }
4880 if (!ok)
24eab124
AM		 4881 {
4882#if INFER_ADDR_PREFIX
20f0a1fc 4883 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4884 {
4885 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4886 i.prefixes += 1;
b23bac36
AM		 4887 /* Change the size of any displacement too. At most one of
4888 Disp16 or Disp32 is set.
4889 FIXME. There doesn't seem to be any real need for separate
4890 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4891 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 4892 if (flag_code != CODE_64BIT
4893 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4894 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4895 fudged = 1;
24eab124
AM		 4896 goto tryprefix;
4897 }
eecb386c
AM		 4898 if (fudged)
4899 as_bad (_("`%s' is not a valid base/index expression"),
4900 operand_string);
4901 else
c388dee8 4902#endif
eecb386c
AM		 4903 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4904 operand_string,
3e73aa7c 4905 flag_code_names[flag_code]);
24eab124 4906 }
20f0a1fc 4907 return ok;
24eab124 4908}
252b5132 4909
252b5132 4910/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4911 on error. */
252b5132 4912
252b5132 4913static int
e3bb37b5 4914i386_operand (char *operand_string)
252b5132 4915{
af6bdddf
AM		 4916 const reg_entry *r;
4917 char *end_op;
24eab124 4918 char *op_string = operand_string;
252b5132 4919
24eab124 4920 if (is_space_char (*op_string))
252b5132
RH		 4921 ++op_string;
4922
24eab124 4923 /* We check for an absolute prefix (differentiating,
47926f60 4924 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4925 if (*op_string == ABSOLUTE_PREFIX)
4926 {
4927 ++op_string;
4928 if (is_space_char (*op_string))
4929 ++op_string;
4930 i.types[this_operand] |= JumpAbsolute;
4931 }
252b5132 4932
47926f60 4933 /* Check if operand is a register. */
4d1bb795 4934 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4935 {
24eab124
AM		 4936 /* Check for a segment override by searching for ':' after a
4937 segment register. */
4938 op_string = end_op;
4939 if (is_space_char (*op_string))
4940 ++op_string;
4941 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4942 {
4943 switch (r->reg_num)
4944 {
4945 case 0:
4946 i.seg[i.mem_operands] = &es;
4947 break;
4948 case 1:
4949 i.seg[i.mem_operands] = &cs;
4950 break;
4951 case 2:
4952 i.seg[i.mem_operands] = &ss;
4953 break;
4954 case 3:
4955 i.seg[i.mem_operands] = &ds;
4956 break;
4957 case 4:
4958 i.seg[i.mem_operands] = &fs;
4959 break;
4960 case 5:
4961 i.seg[i.mem_operands] = &gs;
4962 break;
4963 }
252b5132 4964
24eab124 4965 /* Skip the ':' and whitespace. */
252b5132
RH		 4966 ++op_string;
4967 if (is_space_char (*op_string))
24eab124 4968 ++op_string;
252b5132 4969
24eab124
AM		 4970 if (!is_digit_char (*op_string)
4971 && !is_identifier_char (*op_string)
4972 && *op_string != '('
4973 && *op_string != ABSOLUTE_PREFIX)
4974 {
4975 as_bad (_("bad memory operand `%s'"), op_string);
4976 return 0;
4977 }
47926f60 4978 /* Handle case of %es:*foo. */
24eab124
AM		 4979 if (*op_string == ABSOLUTE_PREFIX)
4980 {
4981 ++op_string;
4982 if (is_space_char (*op_string))
4983 ++op_string;
4984 i.types[this_operand] |= JumpAbsolute;
4985 }
4986 goto do_memory_reference;
4987 }
4988 if (*op_string)
4989 {
d0b47220 4990 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4991 return 0;
4992 }
4993 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4994 i.op[this_operand].regs = r;
24eab124
AM		 4995 i.reg_operands++;
4996 }
af6bdddf
AM		 4997 else if (*op_string == REGISTER_PREFIX)
4998 {
4999 as_bad (_("bad register name `%s'"), op_string);
5000 return 0;
5001 }
24eab124 5002 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5003 {
24eab124
AM		 5004 ++op_string;
5005 if (i.types[this_operand] & JumpAbsolute)
5006 {
d0b47220 5007 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5008 return 0;
5009 }
5010 if (!i386_immediate (op_string))
5011 return 0;
5012 }
5013 else if (is_digit_char (*op_string)
5014 || is_identifier_char (*op_string)
e5cb08ac 5015 || *op_string == '(')
24eab124 5016 {
47926f60 5017 /* This is a memory reference of some sort. */
af6bdddf 5018 char *base_string;
252b5132 5019
47926f60 5020 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5021 char *displacement_string_start;
5022 char *displacement_string_end;
252b5132 5023
24eab124 5024 do_memory_reference:
24eab124
AM		 5025 if ((i.mem_operands == 1
5026 && (current_templates->start->opcode_modifier & IsString) == 0)
5027 || i.mem_operands == 2)
5028 {
5029 as_bad (_("too many memory references for `%s'"),
5030 current_templates->start->name);
5031 return 0;
5032 }
252b5132 5033
24eab124
AM		 5034 /* Check for base index form. We detect the base index form by
5035 looking for an ')' at the end of the operand, searching
5036 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5037 after the '('. */
af6bdddf 5038 base_string = op_string + strlen (op_string);
c3332e24 5039
af6bdddf
AM		 5040 --base_string;
5041 if (is_space_char (*base_string))
5042 --base_string;
252b5132 5043
47926f60 5044 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5045 displacement_string_start = op_string;
5046 displacement_string_end = base_string + 1;
252b5132 5047
24eab124
AM		 5048 if (*base_string == ')')
5049 {
af6bdddf 5050 char *temp_string;
24eab124
AM		 5051 unsigned int parens_balanced = 1;
5052 /* We've already checked that the number of left & right ()'s are
47926f60 5053 equal, so this loop will not be infinite. */
24eab124
AM		 5054 do
5055 {
5056 base_string--;
5057 if (*base_string == ')')
5058 parens_balanced++;
5059 if (*base_string == '(')
5060 parens_balanced--;
5061 }
5062 while (parens_balanced);
c3332e24 5063
af6bdddf 5064 temp_string = base_string;
c3332e24 5065
24eab124 5066 /* Skip past '(' and whitespace. */
252b5132
RH		 5067 ++base_string;
5068 if (is_space_char (*base_string))
24eab124 5069 ++base_string;
252b5132 5070
af6bdddf 5071 if (*base_string == ','
4eed87de
AM		 5072 || ((i.base_reg = parse_register (base_string, &end_op))
5073 != NULL))
252b5132 5074 {
af6bdddf 5075 displacement_string_end = temp_string;
252b5132 5076
af6bdddf 5077 i.types[this_operand] |= BaseIndex;
252b5132 5078
af6bdddf 5079 if (i.base_reg)
24eab124 5080 {
24eab124
AM		 5081 base_string = end_op;
5082 if (is_space_char (*base_string))
5083 ++base_string;
af6bdddf
AM		 5084 }
5085
5086 /* There may be an index reg or scale factor here. */
5087 if (*base_string == ',')
5088 {
5089 ++base_string;
5090 if (is_space_char (*base_string))
5091 ++base_string;
5092
4eed87de
AM		 5093 if ((i.index_reg = parse_register (base_string, &end_op))
5094 != NULL)
24eab124 5095 {
af6bdddf 5096 base_string = end_op;
24eab124
AM		 5097 if (is_space_char (*base_string))
5098 ++base_string;
af6bdddf
AM		 5099 if (*base_string == ',')
5100 {
5101 ++base_string;
5102 if (is_space_char (*base_string))
5103 ++base_string;
5104 }
e5cb08ac 5105 else if (*base_string != ')')
af6bdddf 5106 {
4eed87de
AM		 5107 as_bad (_("expecting `,' or `)' "
5108 "after index register in `%s'"),
af6bdddf
AM		 5109 operand_string);
5110 return 0;
5111 }
24eab124 5112 }
af6bdddf 5113 else if (*base_string == REGISTER_PREFIX)
24eab124 5114 {
af6bdddf 5115 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5116 return 0;
5117 }
252b5132 5118
47926f60 5119 /* Check for scale factor. */
551c1ca1 5120 if (*base_string != ')')
af6bdddf 5121 {
551c1ca1
AM		 5122 char *end_scale = i386_scale (base_string);
5123
5124 if (!end_scale)
af6bdddf 5125 return 0;
24eab124 5126
551c1ca1 5127 base_string = end_scale;
af6bdddf
AM		 5128 if (is_space_char (*base_string))
5129 ++base_string;
5130 if (*base_string != ')')
5131 {
4eed87de
AM		 5132 as_bad (_("expecting `)' "
5133 "after scale factor in `%s'"),
af6bdddf
AM		 5134 operand_string);
5135 return 0;
5136 }
5137 }
5138 else if (!i.index_reg)
24eab124 5139 {
4eed87de
AM		 5140 as_bad (_("expecting index register or scale factor "
5141 "after `,'; got '%c'"),
af6bdddf 5142 *base_string);
24eab124
AM		 5143 return 0;
5144 }
5145 }
af6bdddf 5146 else if (*base_string != ')')
24eab124 5147 {
4eed87de
AM		 5148 as_bad (_("expecting `,' or `)' "
5149 "after base register in `%s'"),
af6bdddf 5150 operand_string);
24eab124
AM		 5151 return 0;
5152 }
c3332e24 5153 }
af6bdddf 5154 else if (*base_string == REGISTER_PREFIX)
c3332e24 5155 {
af6bdddf 5156 as_bad (_("bad register name `%s'"), base_string);
24eab124 5157 return 0;
c3332e24 5158 }
24eab124
AM		 5159 }
5160
5161 /* If there's an expression beginning the operand, parse it,
5162 assuming displacement_string_start and
5163 displacement_string_end are meaningful. */
5164 if (displacement_string_start != displacement_string_end)
5165 {
5166 if (!i386_displacement (displacement_string_start,
5167 displacement_string_end))
5168 return 0;
5169 }
5170
5171 /* Special case for (%dx) while doing input/output op. */
5172 if (i.base_reg
5173 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5174 && i.index_reg == 0
5175 && i.log2_scale_factor == 0
5176 && i.seg[i.mem_operands] == 0
5177 && (i.types[this_operand] & Disp) == 0)
5178 {
5179 i.types[this_operand] = InOutPortReg;
5180 return 1;
5181 }
5182
eecb386c
AM		 5183 if (i386_index_check (operand_string) == 0)
5184 return 0;
24eab124
AM		 5185 i.mem_operands++;
5186 }
5187 else
ce8a8b2f
AM		 5188 {
5189 /* It's not a memory operand; argh! */
24eab124
AM		 5190 as_bad (_("invalid char %s beginning operand %d `%s'"),
5191 output_invalid (*op_string),
5192 this_operand + 1,
5193 op_string);
5194 return 0;
5195 }
47926f60 5196 return 1; /* Normal return. */
252b5132
RH		 5197}
5198\f
ee7fcc42
AM		 5199/* md_estimate_size_before_relax()
5200
5201 Called just before relax() for rs_machine_dependent frags. The x86
5202 assembler uses these frags to handle variable size jump
5203 instructions.
5204
5205 Any symbol that is now undefined will not become defined.
5206 Return the correct fr_subtype in the frag.
5207 Return the initial "guess for variable size of frag" to caller.
5208 The guess is actually the growth beyond the fixed part. Whatever
5209 we do to grow the fixed or variable part contributes to our
5210 returned value. */
5211
252b5132
RH		 5212int
5213md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5214 fragS *fragP;
5215 segT segment;
252b5132 5216{
252b5132 5217 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5218 check for un-relaxable symbols. On an ELF system, we can't relax
5219 an externally visible symbol, because it may be overridden by a
5220 shared library. */
5221 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5223 || (IS_ELF
31312f95
AM		 5224 && (S_IS_EXTERNAL (fragP->fr_symbol)
5225 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5226#endif
5227 )
252b5132 5228 {
b98ef147
AM		 5229 /* Symbol is undefined in this segment, or we need to keep a
5230 reloc so that weak symbols can be overridden. */
5231 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5232 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5233 unsigned char *opcode;
5234 int old_fr_fix;
f6af82bd 5235
ee7fcc42
AM		 5236 if (fragP->fr_var != NO_RELOC)
5237 reloc_type = fragP->fr_var;
b98ef147 5238 else if (size == 2)
f6af82bd
AM		 5239 reloc_type = BFD_RELOC_16_PCREL;
5240 else
5241 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5242
ee7fcc42
AM		 5243 old_fr_fix = fragP->fr_fix;
5244 opcode = (unsigned char *) fragP->fr_opcode;
5245
fddf5b5b 5246 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5247 {
fddf5b5b
AM		 5248 case UNCOND_JUMP:
5249 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5250 opcode[0] = 0xe9;
252b5132 5251 fragP->fr_fix += size;
062cd5e7
AS		 5252 fix_new (fragP, old_fr_fix, size,
5253 fragP->fr_symbol,
5254 fragP->fr_offset, 1,
5255 reloc_type);
252b5132
RH		 5256 break;
5257
fddf5b5b 5258 case COND_JUMP86:
412167cb
AM		 5259 if (size == 2
5260 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5261 {
5262 /* Negate the condition, and branch past an
5263 unconditional jump. */
5264 opcode[0] ^= 1;
5265 opcode[1] = 3;
5266 /* Insert an unconditional jump. */
5267 opcode[2] = 0xe9;
5268 /* We added two extra opcode bytes, and have a two byte
5269 offset. */
5270 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5271 fix_new (fragP, old_fr_fix + 2, 2,
5272 fragP->fr_symbol,
5273 fragP->fr_offset, 1,
5274 reloc_type);
fddf5b5b
AM		 5275 break;
5276 }
5277 /* Fall through. */
5278
5279 case COND_JUMP:
412167cb
AM		 5280 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5281 {
3e02c1cc
AM		 5282 fixS *fixP;
5283
412167cb 5284 fragP->fr_fix += 1;
3e02c1cc
AM		 5285 fixP = fix_new (fragP, old_fr_fix, 1,
5286 fragP->fr_symbol,
5287 fragP->fr_offset, 1,
5288 BFD_RELOC_8_PCREL);
5289 fixP->fx_signed = 1;
412167cb
AM		 5290 break;
5291 }
93c2a809 5292
24eab124 5293 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5294 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5295 opcode[1] = opcode[0] + 0x10;
f6af82bd 5296 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5297 /* We've added an opcode byte. */
5298 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5299 fix_new (fragP, old_fr_fix + 1, size,
5300 fragP->fr_symbol,
5301 fragP->fr_offset, 1,
5302 reloc_type);
252b5132 5303 break;
fddf5b5b
AM		 5304
5305 default:
5306 BAD_CASE (fragP->fr_subtype);
5307 break;
252b5132
RH		 5308 }
5309 frag_wane (fragP);
ee7fcc42 5310 return fragP->fr_fix - old_fr_fix;
252b5132 5311 }
93c2a809 5312
93c2a809
AM		 5313 /* Guess size depending on current relax state. Initially the relax
5314 state will correspond to a short jump and we return 1, because
5315 the variable part of the frag (the branch offset) is one byte
5316 long. However, we can relax a section more than once and in that
5317 case we must either set fr_subtype back to the unrelaxed state,
5318 or return the value for the appropriate branch. */
5319 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5320}
5321
47926f60
KH		 5322/* Called after relax() is finished.
5323
5324 In: Address of frag.
5325 fr_type == rs_machine_dependent.
5326 fr_subtype is what the address relaxed to.
5327
5328 Out: Any fixSs and constants are set up.
5329 Caller will turn frag into a ".space 0". */
5330
252b5132
RH		 5331void
5332md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5333 bfd *abfd ATTRIBUTE_UNUSED;
5334 segT sec ATTRIBUTE_UNUSED;
29b0f896 5335 fragS *fragP;
252b5132 5336{
29b0f896 5337 unsigned char *opcode;
252b5132 5338 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5339 offsetT target_address;
5340 offsetT opcode_address;
252b5132 5341 unsigned int extension = 0;
847f7ad4 5342 offsetT displacement_from_opcode_start;
252b5132
RH		 5343
5344 opcode = (unsigned char *) fragP->fr_opcode;
5345
47926f60 5346 /* Address we want to reach in file space. */
252b5132 5347 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5348
47926f60 5349 /* Address opcode resides at in file space. */
252b5132
RH		 5350 opcode_address = fragP->fr_address + fragP->fr_fix;
5351
47926f60 5352 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5353 displacement_from_opcode_start = target_address - opcode_address;
5354
fddf5b5b 5355 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5356 {
47926f60
KH		 5357 /* Don't have to change opcode. */
5358 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5359 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5360 }
5361 else
5362 {
5363 if (no_cond_jump_promotion
5364 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5365 as_warn_where (fragP->fr_file, fragP->fr_line,
5366 _("long jump required"));
252b5132 5367
fddf5b5b
AM		 5368 switch (fragP->fr_subtype)
5369 {
5370 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5371 extension = 4; /* 1 opcode + 4 displacement */
5372 opcode[0] = 0xe9;
5373 where_to_put_displacement = &opcode[1];
5374 break;
252b5132 5375
fddf5b5b
AM		 5376 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5377 extension = 2; /* 1 opcode + 2 displacement */
5378 opcode[0] = 0xe9;
5379 where_to_put_displacement = &opcode[1];
5380 break;
252b5132 5381
fddf5b5b
AM		 5382 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5383 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5384 extension = 5; /* 2 opcode + 4 displacement */
5385 opcode[1] = opcode[0] + 0x10;
5386 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5387 where_to_put_displacement = &opcode[2];
5388 break;
252b5132 5389
fddf5b5b
AM		 5390 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5391 extension = 3; /* 2 opcode + 2 displacement */
5392 opcode[1] = opcode[0] + 0x10;
5393 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5394 where_to_put_displacement = &opcode[2];
5395 break;
252b5132 5396
fddf5b5b
AM		 5397 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5398 extension = 4;
5399 opcode[0] ^= 1;
5400 opcode[1] = 3;
5401 opcode[2] = 0xe9;
5402 where_to_put_displacement = &opcode[3];
5403 break;
5404
5405 default:
5406 BAD_CASE (fragP->fr_subtype);
5407 break;
5408 }
252b5132 5409 }
fddf5b5b 5410
7b81dfbb
AJ		 5411 /* If size if less then four we are sure that the operand fits,
5412 but if it's 4, then it could be that the displacement is larger
5413 then -/+ 2GB. */
5414 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5415 && object_64bit
5416 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5417 + ((addressT) 1 << 31))
5418 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5419 {
5420 as_bad_where (fragP->fr_file, fragP->fr_line,
5421 _("jump target out of range"));
5422 /* Make us emit 0. */
5423 displacement_from_opcode_start = extension;
5424 }
47926f60 5425 /* Now put displacement after opcode. */
252b5132
RH		 5426 md_number_to_chars ((char *) where_to_put_displacement,
5427 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5428 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5429 fragP->fr_fix += extension;
5430}
5431\f
47926f60
KH		 5432/* Size of byte displacement jmp. */
5433int md_short_jump_size = 2;
5434
5435/* Size of dword displacement jmp. */
5436int md_long_jump_size = 5;
252b5132 5437
252b5132
RH		 5438void
5439md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5440 char *ptr;
5441 addressT from_addr, to_addr;
ab9da554
ILT		 5442 fragS *frag ATTRIBUTE_UNUSED;
5443 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5444{
847f7ad4 5445 offsetT offset;
252b5132
RH		 5446
5447 offset = to_addr - (from_addr + 2);
47926f60
KH		 5448 /* Opcode for byte-disp jump. */
5449 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5450 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5451}
5452
5453void
5454md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5455 char *ptr;
5456 addressT from_addr, to_addr;
a38cf1db
AM		 5457 fragS *frag ATTRIBUTE_UNUSED;
5458 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5459{
847f7ad4 5460 offsetT offset;
252b5132 5461
a38cf1db
AM		 5462 offset = to_addr - (from_addr + 5);
5463 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5464 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5465}
5466\f
5467/* Apply a fixup (fixS) to segment data, once it has been determined
5468 by our caller that we have all the info we need to fix it up.
5469
5470 On the 386, immediates, displacements, and data pointers are all in
5471 the same (little-endian) format, so we don't need to care about which
5472 we are handling. */
5473
94f592af 5474void
55cf6793 5475md_apply_fix (fixP, valP, seg)
47926f60
KH		 5476 /* The fix we're to put in. */
5477 fixS *fixP;
47926f60 5478 /* Pointer to the value of the bits. */
c6682705 5479 valueT *valP;
47926f60
KH		 5480 /* Segment fix is from. */
5481 segT seg ATTRIBUTE_UNUSED;
252b5132 5482{
94f592af 5483 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5484 valueT value = *valP;
252b5132 5485
f86103b7 5486#if !defined (TE_Mach)
93382f6d
AM		 5487 if (fixP->fx_pcrel)
5488 {
5489 switch (fixP->fx_r_type)
5490 {
5865bb77
ILT		 5491 default:
5492 break;
5493
d6ab8113
JB		 5494 case BFD_RELOC_64:
5495 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5496 break;
93382f6d 5497 case BFD_RELOC_32:
ae8887b5 5498 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5499 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5500 break;
5501 case BFD_RELOC_16:
5502 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5503 break;
5504 case BFD_RELOC_8:
5505 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5506 break;
5507 }
5508 }
252b5132 5509
a161fe53 5510 if (fixP->fx_addsy != NULL
31312f95 5511 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5512 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5513 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5514 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5515 && !use_rela_relocations)
252b5132 5516 {
31312f95
AM		 5517 /* This is a hack. There should be a better way to handle this.
5518 This covers for the fact that bfd_install_relocation will
5519 subtract the current location (for partial_inplace, PC relative
5520 relocations); see more below. */
252b5132 5521#ifndef OBJ_AOUT
718ddfc0 5522 if (IS_ELF
252b5132
RH		 5523#ifdef TE_PE
5524 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5525#endif
5526 )
5527 value += fixP->fx_where + fixP->fx_frag->fr_address;
5528#endif
5529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5530 if (IS_ELF)
252b5132 5531 {
6539b54b 5532 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5533
6539b54b 5534 if ((sym_seg == seg
2f66722d 5535 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5536 && sym_seg != absolute_section))
ae6063d4 5537 && !generic_force_reloc (fixP))
2f66722d
AM		 5538 {
5539 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5540 bfd_install_relocation subtracts them out again. I think
5541 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5542 it. FIXME. */
5543 value += fixP->fx_where + fixP->fx_frag->fr_address;
5544 }
252b5132
RH		 5545 }
5546#endif
5547#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5548 /* For some reason, the PE format does not store a
5549 section address offset for a PC relative symbol. */
5550 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5551 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5552 value += md_pcrel_from (fixP);
5553#endif
5554 }
5555
5556 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5557 and we must not disappoint it. */
252b5132 5558#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5559 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5560 switch (fixP->fx_r_type)
5561 {
5562 case BFD_RELOC_386_PLT32:
3e73aa7c 5563 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5564 /* Make the jump instruction point to the address of the operand. At
5565 runtime we merely add the offset to the actual PLT entry. */
5566 value = -4;
5567 break;
31312f95 5568
13ae64f3
JJ		 5569 case BFD_RELOC_386_TLS_GD:
5570 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5571 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5572 case BFD_RELOC_386_TLS_IE:
5573 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5574 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5575 case BFD_RELOC_X86_64_TLSGD:
5576 case BFD_RELOC_X86_64_TLSLD:
5577 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5578 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5579 value = 0; /* Fully resolved at runtime. No addend. */
5580 /* Fallthrough */
5581 case BFD_RELOC_386_TLS_LE:
5582 case BFD_RELOC_386_TLS_LDO_32:
5583 case BFD_RELOC_386_TLS_LE_32:
5584 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5585 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5586 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5587 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5588 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5589 break;
5590
67a4f2b7
AO		 5591 case BFD_RELOC_386_TLS_DESC_CALL:
5592 case BFD_RELOC_X86_64_TLSDESC_CALL:
5593 value = 0; /* Fully resolved at runtime. No addend. */
5594 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5595 fixP->fx_done = 0;
5596 return;
5597
00f7efb6
JJ		 5598 case BFD_RELOC_386_GOT32:
5599 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5600 value = 0; /* Fully resolved at runtime. No addend. */
5601 break;
47926f60
KH		 5602
5603 case BFD_RELOC_VTABLE_INHERIT:
5604 case BFD_RELOC_VTABLE_ENTRY:
5605 fixP->fx_done = 0;
94f592af 5606 return;
47926f60
KH		 5607
5608 default:
5609 break;
5610 }
5611#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5612 *valP = value;
f86103b7 5613#endif /* !defined (TE_Mach) */
3e73aa7c 5614
3e73aa7c 5615 /* Are we finished with this relocation now? */
c6682705 5616 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5617 fixP->fx_done = 1;
5618 else if (use_rela_relocations)
5619 {
5620 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5621 /* Remember value for tc_gen_reloc. */
5622 fixP->fx_addnumber = value;
3e73aa7c
JH		 5623 value = 0;
5624 }
f86103b7 5625
94f592af 5626 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5627}
252b5132 5628\f
252b5132
RH		 5629#define MAX_LITTLENUMS 6
5630
47926f60
KH		 5631/* Turn the string pointed to by litP into a floating point constant
5632 of type TYPE, and emit the appropriate bytes. The number of
5633 LITTLENUMS emitted is stored in *SIZEP. An error message is
5634 returned, or NULL on OK. */
5635
252b5132
RH		 5636char *
5637md_atof (type, litP, sizeP)
2ab9b79e 5638 int type;
252b5132
RH		 5639 char *litP;
5640 int *sizeP;
5641{
5642 int prec;
5643 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5644 LITTLENUM_TYPE *wordP;
5645 char *t;
5646
5647 switch (type)
5648 {
5649 case 'f':
5650 case 'F':
5651 prec = 2;
5652 break;
5653
5654 case 'd':
5655 case 'D':
5656 prec = 4;
5657 break;
5658
5659 case 'x':
5660 case 'X':
5661 prec = 5;
5662 break;
5663
5664 default:
5665 *sizeP = 0;
5666 return _("Bad call to md_atof ()");
5667 }
5668 t = atof_ieee (input_line_pointer, type, words);
5669 if (t)
5670 input_line_pointer = t;
5671
5672 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5673 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5674 the bigendian 386. */
5675 for (wordP = words + prec - 1; prec--;)
5676 {
5677 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5678 litP += sizeof (LITTLENUM_TYPE);
5679 }
5680 return 0;
5681}
5682\f
2d545b82 5683static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5684
252b5132 5685static char *
e3bb37b5 5686output_invalid (int c)
252b5132 5687{
3882b010 5688 if (ISPRINT (c))
f9f21a03
L		 5689 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5690 "'%c'", c);
252b5132 5691 else
f9f21a03 5692 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5693 "(0x%x)", (unsigned char) c);
252b5132
RH		 5694 return output_invalid_buf;
5695}
5696
af6bdddf 5697/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5698
5699static const reg_entry *
4d1bb795 5700parse_real_register (char *reg_string, char **end_op)
252b5132 5701{
af6bdddf
AM		 5702 char *s = reg_string;
5703 char *p;
252b5132
RH		 5704 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5705 const reg_entry *r;
5706
5707 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5708 if (*s == REGISTER_PREFIX)
5709 ++s;
5710
5711 if (is_space_char (*s))
5712 ++s;
5713
5714 p = reg_name_given;
af6bdddf 5715 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5716 {
5717 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5718 return (const reg_entry *) NULL;
5719 s++;
252b5132
RH		 5720 }
5721
6588847e
DN		 5722 /* For naked regs, make sure that we are not dealing with an identifier.
5723 This prevents confusing an identifier like `eax_var' with register
5724 `eax'. */
5725 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5726 return (const reg_entry *) NULL;
5727
af6bdddf 5728 *end_op = s;
252b5132
RH		 5729
5730 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5731
5f47d35b 5732 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5733 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5734 {
5f47d35b
AM		 5735 if (is_space_char (*s))
5736 ++s;
5737 if (*s == '(')
5738 {
af6bdddf 5739 ++s;
5f47d35b
AM		 5740 if (is_space_char (*s))
5741 ++s;
5742 if (*s >= '0' && *s <= '7')
5743 {
5744 r = &i386_float_regtab[*s - '0'];
af6bdddf 5745 ++s;
5f47d35b
AM		 5746 if (is_space_char (*s))
5747 ++s;
5748 if (*s == ')')
5749 {
5750 *end_op = s + 1;
5751 return r;
5752 }
5f47d35b 5753 }
47926f60 5754 /* We have "%st(" then garbage. */
5f47d35b
AM		 5755 return (const reg_entry *) NULL;
5756 }
5757 }
5758
1ae00879 5759 if (r != NULL
20f0a1fc 5760 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5761 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5762 && flag_code != CODE_64BIT)
20f0a1fc 5763 return (const reg_entry *) NULL;
1ae00879 5764
252b5132
RH		 5765 return r;
5766}
4d1bb795
JB		 5767
5768/* REG_STRING starts *before* REGISTER_PREFIX. */
5769
5770static const reg_entry *
5771parse_register (char *reg_string, char **end_op)
5772{
5773 const reg_entry *r;
5774
5775 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5776 r = parse_real_register (reg_string, end_op);
5777 else
5778 r = NULL;
5779 if (!r)
5780 {
5781 char *save = input_line_pointer;
5782 char c;
5783 symbolS *symbolP;
5784
5785 input_line_pointer = reg_string;
5786 c = get_symbol_end ();
5787 symbolP = symbol_find (reg_string);
5788 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5789 {
5790 const expressionS *e = symbol_get_value_expression (symbolP);
5791
5792 know (e->X_op == O_register);
4eed87de 5793 know (e->X_add_number >= 0
c3fe08fa 5794 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5795 r = i386_regtab + e->X_add_number;
5796 *end_op = input_line_pointer;
5797 }
5798 *input_line_pointer = c;
5799 input_line_pointer = save;
5800 }
5801 return r;
5802}
5803
5804int
5805i386_parse_name (char *name, expressionS *e, char *nextcharP)
5806{
5807 const reg_entry *r;
5808 char *end = input_line_pointer;
5809
5810 *end = *nextcharP;
5811 r = parse_register (name, &input_line_pointer);
5812 if (r && end <= input_line_pointer)
5813 {
5814 *nextcharP = *input_line_pointer;
5815 *input_line_pointer = 0;
5816 e->X_op = O_register;
5817 e->X_add_number = r - i386_regtab;
5818 return 1;
5819 }
5820 input_line_pointer = end;
5821 *end = 0;
5822 return 0;
5823}
5824
5825void
5826md_operand (expressionS *e)
5827{
5828 if (*input_line_pointer == REGISTER_PREFIX)
5829 {
5830 char *end;
5831 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5832
5833 if (r)
5834 {
5835 e->X_op = O_register;
5836 e->X_add_number = r - i386_regtab;
5837 input_line_pointer = end;
5838 }
5839 }
5840}
5841
252b5132 5842\f
4cc782b5 5843#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5844const char *md_shortopts = "kVQ:sqn";
252b5132 5845#else
12b55ccc 5846const char *md_shortopts = "qn";
252b5132 5847#endif
6e0b89ee 5848
3e73aa7c 5849#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5850#define OPTION_64 (OPTION_MD_BASE + 1)
5851#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5852#define OPTION_MARCH (OPTION_MD_BASE + 3)
5853#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5854
99ad8390
NC		 5855struct option md_longopts[] =
5856{
3e73aa7c 5857 {"32", no_argument, NULL, OPTION_32},
99ad8390 5858#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5859 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5860#endif
b3b91714 5861 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5862 {"march", required_argument, NULL, OPTION_MARCH},
5863 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5864 {NULL, no_argument, NULL, 0}
5865};
5866size_t md_longopts_size = sizeof (md_longopts);
5867
5868int
9103f4f4 5869md_parse_option (int c, char *arg)
252b5132 5870{
9103f4f4
L		 5871 unsigned int i;
5872
252b5132
RH		 5873 switch (c)
5874 {
12b55ccc
L		 5875 case 'n':
5876 optimize_align_code = 0;
5877 break;
5878
a38cf1db
AM		 5879 case 'q':
5880 quiet_warnings = 1;
252b5132
RH		 5881 break;
5882
5883#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5884 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5885 should be emitted or not. FIXME: Not implemented. */
5886 case 'Q':
252b5132
RH		 5887 break;
5888
5889 /* -V: SVR4 argument to print version ID. */
5890 case 'V':
5891 print_version_id ();
5892 break;
5893
a38cf1db
AM		 5894 /* -k: Ignore for FreeBSD compatibility. */
5895 case 'k':
252b5132 5896 break;
4cc782b5
ILT		 5897
5898 case 's':
5899 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5900 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5901 break;
99ad8390
NC		 5902#endif
5903#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5904 case OPTION_64:
5905 {
5906 const char **list, **l;
5907
3e73aa7c
JH		 5908 list = bfd_target_list ();
5909 for (l = list; *l != NULL; l++)
8620418b 5910 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5911 || strcmp (*l, "coff-x86-64") == 0
5912 || strcmp (*l, "pe-x86-64") == 0
5913 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5914 {
5915 default_arch = "x86_64";
5916 break;
5917 }
3e73aa7c 5918 if (*l == NULL)
6e0b89ee 5919 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5920 free (list);
5921 }
5922 break;
5923#endif
252b5132 5924
6e0b89ee
AM		 5925 case OPTION_32:
5926 default_arch = "i386";
5927 break;
5928
b3b91714
AM		 5929 case OPTION_DIVIDE:
5930#ifdef SVR4_COMMENT_CHARS
5931 {
5932 char *n, *t;
5933 const char *s;
5934
5935 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5936 t = n;
5937 for (s = i386_comment_chars; *s != '\0'; s++)
5938 if (*s != '/')
5939 *t++ = *s;
5940 *t = '\0';
5941 i386_comment_chars = n;
5942 }
5943#endif
5944 break;
5945
9103f4f4
L		 5946 case OPTION_MARCH:
5947 if (*arg == '.')
5948 as_fatal (_("Invalid -march= option: `%s'"), arg);
5949 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5950 {
5951 if (strcmp (arg, cpu_arch [i].name) == 0)
5952 {
ccc9c027 5953 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5954 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5955 if (!cpu_arch_tune_set)
5956 {
5957 cpu_arch_tune = cpu_arch_isa;
5958 cpu_arch_tune_flags = cpu_arch_isa_flags;
5959 }
9103f4f4
L		 5960 break;
5961 }
5962 }
5963 if (i >= ARRAY_SIZE (cpu_arch))
5964 as_fatal (_("Invalid -march= option: `%s'"), arg);
5965 break;
5966
5967 case OPTION_MTUNE:
5968 if (*arg == '.')
5969 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5970 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5971 {
5972 if (strcmp (arg, cpu_arch [i].name) == 0)
5973 {
ccc9c027 5974 cpu_arch_tune_set = 1;
9103f4f4
L		 5975 cpu_arch_tune = cpu_arch [i].type;
5976 cpu_arch_tune_flags = cpu_arch[i].flags;
5977 break;
5978 }
5979 }
5980 if (i >= ARRAY_SIZE (cpu_arch))
5981 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5982 break;
5983
252b5132
RH		 5984 default:
5985 return 0;
5986 }
5987 return 1;
5988}
5989
5990void
5991md_show_usage (stream)
5992 FILE *stream;
5993{
4cc782b5
ILT		 5994#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5995 fprintf (stream, _("\
a38cf1db
AM		 5996 -Q ignored\n\
5997 -V print assembler version number\n\
b3b91714
AM		 5998 -k ignored\n"));
5999#endif
6000 fprintf (stream, _("\
12b55ccc 6001 -n Do not optimize code alignment\n\
b3b91714
AM		 6002 -q quieten some warnings\n"));
6003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6004 fprintf (stream, _("\
a38cf1db 6005 -s ignored\n"));
b3b91714 6006#endif
751d281c
L		 6007#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6008 fprintf (stream, _("\
6009 --32/--64 generate 32bit/64bit code\n"));
6010#endif
b3b91714
AM		 6011#ifdef SVR4_COMMENT_CHARS
6012 fprintf (stream, _("\
6013 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6014#else
6015 fprintf (stream, _("\
b3b91714 6016 --divide ignored\n"));
4cc782b5 6017#endif
9103f4f4
L		 6018 fprintf (stream, _("\
6019 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6020 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6021 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6022
252b5132
RH		 6023}
6024
99ad8390
NC		 6025#if defined(TE_PEP)
6026const char *
6027x86_64_target_format (void)
6028{
6029 if (strcmp (default_arch, "x86_64") == 0)
6030 {
6031 set_code_flag (CODE_64BIT);
6032 return COFF_TARGET_FORMAT;
6033 }
6034 else if (strcmp (default_arch, "i386") == 0)
6035 {
6036 set_code_flag (CODE_32BIT);
6037 return "coff-i386";
6038 }
6039
6040 as_fatal (_("Unknown architecture"));
6041 return NULL;
6042}
6043#endif
6044
3e73aa7c
JH		 6045#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6046 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6047
6048/* Pick the target format to use. */
6049
47926f60 6050const char *
e3bb37b5 6051i386_target_format (void)
252b5132 6052{
3e73aa7c 6053 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6054 {
6055 set_code_flag (CODE_64BIT);
6056 if (cpu_arch_isa_flags == 0)
d32cad65 6057 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6058 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6059 |CpuSSE|CpuSSE2;
ccc9c027 6060 if (cpu_arch_tune_flags == 0)
d32cad65 6061 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6062 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6063 |CpuSSE|CpuSSE2;
9103f4f4 6064 }
3e73aa7c 6065 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6066 {
6067 set_code_flag (CODE_32BIT);
6068 if (cpu_arch_isa_flags == 0)
d32cad65 6069 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6070 if (cpu_arch_tune_flags == 0)
d32cad65 6071 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6072 }
3e73aa7c
JH		 6073 else
6074 as_fatal (_("Unknown architecture"));
252b5132
RH		 6075 switch (OUTPUT_FLAVOR)
6076 {
4c63da97
AM		 6077#ifdef OBJ_MAYBE_AOUT
6078 case bfd_target_aout_flavour:
47926f60 6079 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6080#endif
6081#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6082 case bfd_target_coff_flavour:
6083 return "coff-i386";
4c63da97 6084#endif
3e73aa7c 6085#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6086 case bfd_target_elf_flavour:
3e73aa7c 6087 {
e5cb08ac 6088 if (flag_code == CODE_64BIT)
4fa24527
JB		 6089 {
6090 object_64bit = 1;
6091 use_rela_relocations = 1;
6092 }
9d7cbccd 6093 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6094 }
4c63da97 6095#endif
252b5132
RH		 6096 default:
6097 abort ();
6098 return NULL;
6099 }
6100}
6101
47926f60 6102#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6103
6104#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6105void
6106i386_elf_emit_arch_note (void)
a847613f 6107{
718ddfc0 6108 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6109 {
6110 char *p;
6111 asection *seg = now_seg;
6112 subsegT subseg = now_subseg;
6113 Elf_Internal_Note i_note;
6114 Elf_External_Note e_note;
6115 asection *note_secp;
6116 int len;
6117
6118 /* Create the .note section. */
6119 note_secp = subseg_new (".note", 0);
6120 bfd_set_section_flags (stdoutput,
6121 note_secp,
6122 SEC_HAS_CONTENTS | SEC_READONLY);
6123
6124 /* Process the arch string. */
6125 len = strlen (cpu_arch_name);
6126
6127 i_note.namesz = len + 1;
6128 i_note.descsz = 0;
6129 i_note.type = NT_ARCH;
6130 p = frag_more (sizeof (e_note.namesz));
6131 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6132 p = frag_more (sizeof (e_note.descsz));
6133 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6134 p = frag_more (sizeof (e_note.type));
6135 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6136 p = frag_more (len + 1);
6137 strcpy (p, cpu_arch_name);
6138
6139 frag_align (2, 0, 0);
6140
6141 subseg_set (seg, subseg);
6142 }
6143}
6144#endif
252b5132 6145\f
252b5132
RH		 6146symbolS *
6147md_undefined_symbol (name)
6148 char *name;
6149{
18dc2407
ILT		 6150 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6151 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6152 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6153 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6154 {
6155 if (!GOT_symbol)
6156 {
6157 if (symbol_find (name))
6158 as_bad (_("GOT already in symbol table"));
6159 GOT_symbol = symbol_new (name, undefined_section,
6160 (valueT) 0, &zero_address_frag);
6161 };
6162 return GOT_symbol;
6163 }
252b5132
RH		 6164 return 0;
6165}
6166
6167/* Round up a section size to the appropriate boundary. */
47926f60 6168
252b5132
RH		 6169valueT
6170md_section_align (segment, size)
ab9da554 6171 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6172 valueT size;
6173{
4c63da97
AM		 6174#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6175 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6176 {
6177 /* For a.out, force the section size to be aligned. If we don't do
6178 this, BFD will align it for us, but it will not write out the
6179 final bytes of the section. This may be a bug in BFD, but it is
6180 easier to fix it here since that is how the other a.out targets
6181 work. */
6182 int align;
6183
6184 align = bfd_get_section_alignment (stdoutput, segment);
6185 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6186 }
252b5132
RH		 6187#endif
6188
6189 return size;
6190}
6191
6192/* On the i386, PC-relative offsets are relative to the start of the
6193 next instruction. That is, the address of the offset, plus its
6194 size, since the offset is always the last part of the insn. */
6195
6196long
e3bb37b5 6197md_pcrel_from (fixS *fixP)
252b5132
RH		 6198{
6199 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6200}
6201
6202#ifndef I386COFF
6203
6204static void
e3bb37b5 6205s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6206{
29b0f896 6207 int temp;
252b5132 6208
8a75718c
JB		 6209#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6210 if (IS_ELF)
6211 obj_elf_section_change_hook ();
6212#endif
252b5132
RH		 6213 temp = get_absolute_expression ();
6214 subseg_set (bss_section, (subsegT) temp);
6215 demand_empty_rest_of_line ();
6216}
6217
6218#endif
6219
252b5132 6220void
e3bb37b5 6221i386_validate_fix (fixS *fixp)
252b5132
RH		 6222{
6223 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6224 {
23df1078
JH		 6225 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6226 {
4fa24527 6227 if (!object_64bit)
23df1078
JH		 6228 abort ();
6229 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6230 }
6231 else
6232 {
4fa24527 6233 if (!object_64bit)
d6ab8113
JB		 6234 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6235 else
6236 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6237 }
252b5132
RH		 6238 fixp->fx_subsy = 0;
6239 }
6240}
6241
252b5132
RH		 6242arelent *
6243tc_gen_reloc (section, fixp)
ab9da554 6244 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6245 fixS *fixp;
6246{
6247 arelent *rel;
6248 bfd_reloc_code_real_type code;
6249
6250 switch (fixp->fx_r_type)
6251 {
3e73aa7c
JH		 6252 case BFD_RELOC_X86_64_PLT32:
6253 case BFD_RELOC_X86_64_GOT32:
6254 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6255 case BFD_RELOC_386_PLT32:
6256 case BFD_RELOC_386_GOT32:
6257 case BFD_RELOC_386_GOTOFF:
6258 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6259 case BFD_RELOC_386_TLS_GD:
6260 case BFD_RELOC_386_TLS_LDM:
6261 case BFD_RELOC_386_TLS_LDO_32:
6262 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6263 case BFD_RELOC_386_TLS_IE:
6264 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6265 case BFD_RELOC_386_TLS_LE_32:
6266 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6267 case BFD_RELOC_386_TLS_GOTDESC:
6268 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6269 case BFD_RELOC_X86_64_TLSGD:
6270 case BFD_RELOC_X86_64_TLSLD:
6271 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6272 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6273 case BFD_RELOC_X86_64_GOTTPOFF:
6274 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6275 case BFD_RELOC_X86_64_TPOFF64:
6276 case BFD_RELOC_X86_64_GOTOFF64:
6277 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6278 case BFD_RELOC_X86_64_GOT64:
6279 case BFD_RELOC_X86_64_GOTPCREL64:
6280 case BFD_RELOC_X86_64_GOTPC64:
6281 case BFD_RELOC_X86_64_GOTPLT64:
6282 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6283 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6284 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6285 case BFD_RELOC_RVA:
6286 case BFD_RELOC_VTABLE_ENTRY:
6287 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6288#ifdef TE_PE
6289 case BFD_RELOC_32_SECREL:
6290#endif
252b5132
RH		 6291 code = fixp->fx_r_type;
6292 break;
dbbaec26
L		 6293 case BFD_RELOC_X86_64_32S:
6294 if (!fixp->fx_pcrel)
6295 {
6296 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6297 code = fixp->fx_r_type;
6298 break;
6299 }
252b5132 6300 default:
93382f6d 6301 if (fixp->fx_pcrel)
252b5132 6302 {
93382f6d
AM		 6303 switch (fixp->fx_size)
6304 {
6305 default:
b091f402
AM		 6306 as_bad_where (fixp->fx_file, fixp->fx_line,
6307 _("can not do %d byte pc-relative relocation"),
6308 fixp->fx_size);
93382f6d
AM		 6309 code = BFD_RELOC_32_PCREL;
6310 break;
6311 case 1: code = BFD_RELOC_8_PCREL; break;
6312 case 2: code = BFD_RELOC_16_PCREL; break;
6313 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6314#ifdef BFD64
6315 case 8: code = BFD_RELOC_64_PCREL; break;
6316#endif
93382f6d
AM		 6317 }
6318 }
6319 else
6320 {
6321 switch (fixp->fx_size)
6322 {
6323 default:
b091f402
AM		 6324 as_bad_where (fixp->fx_file, fixp->fx_line,
6325 _("can not do %d byte relocation"),
6326 fixp->fx_size);
93382f6d
AM		 6327 code = BFD_RELOC_32;
6328 break;
6329 case 1: code = BFD_RELOC_8; break;
6330 case 2: code = BFD_RELOC_16; break;
6331 case 4: code = BFD_RELOC_32; break;
937149dd 6332#ifdef BFD64
3e73aa7c 6333 case 8: code = BFD_RELOC_64; break;
937149dd 6334#endif
93382f6d 6335 }
252b5132
RH		 6336 }
6337 break;
6338 }
252b5132 6339
d182319b
JB		 6340 if ((code == BFD_RELOC_32
6341 || code == BFD_RELOC_32_PCREL
6342 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6343 && GOT_symbol
6344 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6345 {
4fa24527 6346 if (!object_64bit)
d6ab8113
JB		 6347 code = BFD_RELOC_386_GOTPC;
6348 else
6349 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6350 }
7b81dfbb
AJ		 6351 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6352 && GOT_symbol
6353 && fixp->fx_addsy == GOT_symbol)
6354 {
6355 code = BFD_RELOC_X86_64_GOTPC64;
6356 }
252b5132
RH		 6357
6358 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6359 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6360 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6361
6362 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6363
3e73aa7c
JH		 6364 if (!use_rela_relocations)
6365 {
6366 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6367 vtable entry to be used in the relocation's section offset. */
6368 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6369 rel->address = fixp->fx_offset;
252b5132 6370
c6682705 6371 rel->addend = 0;
3e73aa7c
JH		 6372 }
6373 /* Use the rela in 64bit mode. */
252b5132 6374 else
3e73aa7c 6375 {
062cd5e7
AS		 6376 if (!fixp->fx_pcrel)
6377 rel->addend = fixp->fx_offset;
6378 else
6379 switch (code)
6380 {
6381 case BFD_RELOC_X86_64_PLT32:
6382 case BFD_RELOC_X86_64_GOT32:
6383 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6384 case BFD_RELOC_X86_64_TLSGD:
6385 case BFD_RELOC_X86_64_TLSLD:
6386 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6387 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6388 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6389 rel->addend = fixp->fx_offset - fixp->fx_size;
6390 break;
6391 default:
6392 rel->addend = (section->vma
6393 - fixp->fx_size
6394 + fixp->fx_addnumber
6395 + md_pcrel_from (fixp));
6396 break;
6397 }
3e73aa7c
JH		 6398 }
6399
252b5132
RH		 6400 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6401 if (rel->howto == NULL)
6402 {
6403 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6404 _("cannot represent relocation type %s"),
252b5132
RH		 6405 bfd_get_reloc_code_name (code));
6406 /* Set howto to a garbage value so that we can keep going. */
6407 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6408 assert (rel->howto != NULL);
6409 }
6410
6411 return rel;
6412}
6413
64a0c779
DN		 6414\f
6415/* Parse operands using Intel syntax. This implements a recursive descent
6416 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6417 Programmer's Guide.
6418
6419 FIXME: We do not recognize the full operand grammar defined in the MASM
6420 documentation. In particular, all the structure/union and
6421 high-level macro operands are missing.
6422
6423 Uppercase words are terminals, lower case words are non-terminals.
6424 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6425 bars '|' denote choices. Most grammar productions are implemented in
6426 functions called 'intel_<production>'.
6427
6428 Initial production is 'expr'.
6429
9306ca4a 6430 addOp + | -
64a0c779
DN		 6431
6432 alpha [a-zA-Z]
6433
9306ca4a
JB		 6434 binOp & | AND | \| | OR | ^ | XOR
6435
64a0c779
DN		 6436 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6437
6438 constant digits [[ radixOverride ]]
6439
9306ca4a 6440 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6441
6442 digits decdigit
b77a7acd
AJ		 6443 | digits decdigit
6444 | digits hexdigit
64a0c779
DN		 6445
6446 decdigit [0-9]
6447
9306ca4a
JB		 6448 e04 e04 addOp e05
6449 | e05
6450
6451 e05 e05 binOp e06
b77a7acd 6452 | e06
64a0c779
DN		 6453
6454 e06 e06 mulOp e09
b77a7acd 6455 | e09
64a0c779
DN		 6456
6457 e09 OFFSET e10
a724f0f4
JB		 6458 | SHORT e10
6459 | + e10
6460 | - e10
9306ca4a
JB		 6461 | ~ e10
6462 | NOT e10
64a0c779
DN		 6463 | e09 PTR e10
6464 | e09 : e10
6465 | e10
6466
6467 e10 e10 [ expr ]
b77a7acd 6468 | e11
64a0c779
DN		 6469
6470 e11 ( expr )
b77a7acd 6471 | [ expr ]
64a0c779
DN		 6472 | constant
6473 | dataType
6474 | id
6475 | $
6476 | register
6477
a724f0f4 6478 => expr expr cmpOp e04
9306ca4a 6479 | e04
64a0c779
DN		 6480
6481 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6482 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6483
6484 hexdigit a | b | c | d | e | f
b77a7acd 6485 | A | B | C | D | E | F
64a0c779
DN		 6486
6487 id alpha
b77a7acd 6488 | id alpha
64a0c779
DN		 6489 | id decdigit
6490
9306ca4a 6491 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6492
6493 quote " | '
6494
6495 register specialRegister
b77a7acd 6496 | gpRegister
64a0c779
DN		 6497 | byteRegister
6498
6499 segmentRegister CS | DS | ES | FS | GS | SS
6500
9306ca4a 6501 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6502 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6503 | TR3 | TR4 | TR5 | TR6 | TR7
6504
64a0c779
DN		 6505 We simplify the grammar in obvious places (e.g., register parsing is
6506 done by calling parse_register) and eliminate immediate left recursion
6507 to implement a recursive-descent parser.
6508
a724f0f4
JB		 6509 expr e04 expr'
6510
6511 expr' cmpOp e04 expr'
6512 | Empty
9306ca4a
JB		 6513
6514 e04 e05 e04'
6515
6516 e04' addOp e05 e04'
6517 | Empty
64a0c779
DN		 6518
6519 e05 e06 e05'
6520
9306ca4a 6521 e05' binOp e06 e05'
b77a7acd 6522 | Empty
64a0c779
DN		 6523
6524 e06 e09 e06'
6525
6526 e06' mulOp e09 e06'
b77a7acd 6527 | Empty
64a0c779
DN		 6528
6529 e09 OFFSET e10 e09'
a724f0f4
JB		 6530 | SHORT e10'
6531 | + e10'
6532 | - e10'
6533 | ~ e10'
6534 | NOT e10'
b77a7acd 6535 | e10 e09'
64a0c779
DN		 6536
6537 e09' PTR e10 e09'
b77a7acd 6538 | : e10 e09'
64a0c779
DN		 6539 | Empty
6540
6541 e10 e11 e10'
6542
6543 e10' [ expr ] e10'
b77a7acd 6544 | Empty
64a0c779
DN		 6545
6546 e11 ( expr )
b77a7acd 6547 | [ expr ]
64a0c779
DN		 6548 | BYTE
6549 | WORD
6550 | DWORD
9306ca4a 6551 | FWORD
64a0c779 6552 | QWORD
9306ca4a
JB		 6553 | TBYTE
6554 | OWORD
6555 | XMMWORD
64a0c779
DN		 6556 | .
6557 | $
6558 | register
6559 | id
6560 | constant */
6561
6562/* Parsing structure for the intel syntax parser. Used to implement the
6563 semantic actions for the operand grammar. */
6564struct intel_parser_s
6565 {
6566 char *op_string; /* The string being parsed. */
6567 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6568 int op_modifier; /* Operand modifier. */
64a0c779 6569 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6570 int in_offset; /* >=1 if parsing operand of offset. */
6571 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6572 const reg_entry *reg; /* Last register reference found. */
6573 char *disp; /* Displacement string being built. */
a724f0f4 6574 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6575 };
6576
6577static struct intel_parser_s intel_parser;
6578
6579/* Token structure for parsing intel syntax. */
6580struct intel_token
6581 {
6582 int code; /* Token code. */
6583 const reg_entry *reg; /* Register entry for register tokens. */
6584 char *str; /* String representation. */
6585 };
6586
6587static struct intel_token cur_token, prev_token;
6588
50705ef4
AM		 6589/* Token codes for the intel parser. Since T_SHORT is already used
6590 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6591#define T_NIL -1
6592#define T_CONST 1
6593#define T_REG 2
6594#define T_BYTE 3
6595#define T_WORD 4
9306ca4a
JB		 6596#define T_DWORD 5
6597#define T_FWORD 6
6598#define T_QWORD 7
6599#define T_TBYTE 8
6600#define T_XMMWORD 9
50705ef4 6601#undef T_SHORT
9306ca4a
JB		 6602#define T_SHORT 10
6603#define T_OFFSET 11
6604#define T_PTR 12
6605#define T_ID 13
6606#define T_SHL 14
6607#define T_SHR 15
64a0c779
DN		 6608
6609/* Prototypes for intel parser functions. */
e3bb37b5
L		 6610static int intel_match_token (int);
6611static void intel_putback_token (void);
6612static void intel_get_token (void);
6613static int intel_expr (void);
6614static int intel_e04 (void);
6615static int intel_e05 (void);
6616static int intel_e06 (void);
6617static int intel_e09 (void);
6618static int intel_e10 (void);
6619static int intel_e11 (void);
64a0c779 6620
64a0c779 6621static int
e3bb37b5 6622i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6623{
6624 int ret;
6625 char *p;
6626
a724f0f4
JB		 6627 p = intel_parser.op_string = xstrdup (operand_string);
6628 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6629
6630 for (;;)
64a0c779 6631 {
a724f0f4
JB		 6632 /* Initialize token holders. */
6633 cur_token.code = prev_token.code = T_NIL;
6634 cur_token.reg = prev_token.reg = NULL;
6635 cur_token.str = prev_token.str = NULL;
6636
6637 /* Initialize parser structure. */
6638 intel_parser.got_a_float = got_a_float;
6639 intel_parser.op_modifier = 0;
6640 intel_parser.is_mem = 0;
6641 intel_parser.in_offset = 0;
6642 intel_parser.in_bracket = 0;
6643 intel_parser.reg = NULL;
6644 intel_parser.disp[0] = '\0';
6645 intel_parser.next_operand = NULL;
6646
6647 /* Read the first token and start the parser. */
6648 intel_get_token ();
6649 ret = intel_expr ();
6650
6651 if (!ret)
6652 break;
6653
9306ca4a
JB		 6654 if (cur_token.code != T_NIL)
6655 {
6656 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6657 current_templates->start->name, cur_token.str);
6658 ret = 0;
6659 }
64a0c779
DN		 6660 /* If we found a memory reference, hand it over to i386_displacement
6661 to fill in the rest of the operand fields. */
9306ca4a 6662 else if (intel_parser.is_mem)
64a0c779
DN		 6663 {
6664 if ((i.mem_operands == 1
6665 && (current_templates->start->opcode_modifier & IsString) == 0)
6666 || i.mem_operands == 2)
6667 {
6668 as_bad (_("too many memory references for '%s'"),
6669 current_templates->start->name);
6670 ret = 0;
6671 }
6672 else
6673 {
6674 char *s = intel_parser.disp;
6675 i.mem_operands++;
6676
a724f0f4
JB		 6677 if (!quiet_warnings && intel_parser.is_mem < 0)
6678 /* See the comments in intel_bracket_expr. */
6679 as_warn (_("Treating `%s' as memory reference"), operand_string);
6680
64a0c779
DN		 6681 /* Add the displacement expression. */
6682 if (*s != '\0')
a4622f40
AM		 6683 ret = i386_displacement (s, s + strlen (s));
6684 if (ret)
a724f0f4
JB		 6685 {
6686 /* Swap base and index in 16-bit memory operands like
6687 [si+bx]. Since i386_index_check is also used in AT&T
6688 mode we have to do that here. */
6689 if (i.base_reg
6690 && i.index_reg
6691 && (i.base_reg->reg_type & Reg16)
6692 && (i.index_reg->reg_type & Reg16)
6693 && i.base_reg->reg_num >= 6
6694 && i.index_reg->reg_num < 6)
6695 {
6696 const reg_entry *base = i.index_reg;
6697
6698 i.index_reg = i.base_reg;
6699 i.base_reg = base;
6700 }
6701 ret = i386_index_check (operand_string);
6702 }
64a0c779
DN		 6703 }
6704 }
6705
6706 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6707 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6708 || intel_parser.reg == NULL)
6709 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6710
6711 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6712 ret = 0;
a724f0f4
JB		 6713 if (!ret || !intel_parser.next_operand)
6714 break;
6715 intel_parser.op_string = intel_parser.next_operand;
6716 this_operand = i.operands++;
64a0c779
DN		 6717 }
6718
6719 free (p);
6720 free (intel_parser.disp);
6721
6722 return ret;
6723}
6724
a724f0f4
JB		 6725#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6726
6727/* expr e04 expr'
6728
6729 expr' cmpOp e04 expr'
6730 | Empty */
64a0c779 6731static int
e3bb37b5 6732intel_expr (void)
64a0c779 6733{
a724f0f4
JB		 6734 /* XXX Implement the comparison operators. */
6735 return intel_e04 ();
9306ca4a
JB		 6736}
6737
a724f0f4 6738/* e04 e05 e04'
9306ca4a 6739
a724f0f4 6740 e04' addOp e05 e04'
9306ca4a
JB		 6741 | Empty */
6742static int
e3bb37b5 6743intel_e04 (void)
9306ca4a 6744{
a724f0f4 6745 int nregs = -1;
9306ca4a 6746
a724f0f4 6747 for (;;)
9306ca4a 6748 {
a724f0f4
JB		 6749 if (!intel_e05())
6750 return 0;
9306ca4a 6751
a724f0f4
JB		 6752 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6753 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6754
a724f0f4
JB		 6755 if (cur_token.code == '+')
6756 nregs = -1;
6757 else if (cur_token.code == '-')
6758 nregs = NUM_ADDRESS_REGS;
6759 else
6760 return 1;
64a0c779 6761
a724f0f4
JB		 6762 strcat (intel_parser.disp, cur_token.str);
6763 intel_match_token (cur_token.code);
6764 }
64a0c779
DN		 6765}
6766
64a0c779
DN		 6767/* e05 e06 e05'
6768
9306ca4a 6769 e05' binOp e06 e05'
64a0c779
DN		 6770 | Empty */
6771static int
e3bb37b5 6772intel_e05 (void)
64a0c779 6773{
a724f0f4 6774 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6775
a724f0f4 6776 for (;;)
64a0c779 6777 {
a724f0f4
JB		 6778 if (!intel_e06())
6779 return 0;
6780
4eed87de
AM		 6781 if (cur_token.code == '&'
6782 || cur_token.code == '|'
6783 || cur_token.code == '^')
a724f0f4
JB		 6784 {
6785 char str[2];
6786
6787 str[0] = cur_token.code;
6788 str[1] = 0;
6789 strcat (intel_parser.disp, str);
6790 }
6791 else
6792 break;
9306ca4a 6793
64a0c779
DN		 6794 intel_match_token (cur_token.code);
6795
a724f0f4
JB		 6796 if (nregs < 0)
6797 nregs = ~nregs;
64a0c779 6798 }
a724f0f4
JB		 6799 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6800 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6801 return 1;
4a1805b1 6802}
64a0c779
DN		 6803
6804/* e06 e09 e06'
6805
6806 e06' mulOp e09 e06'
b77a7acd 6807 | Empty */
64a0c779 6808static int
e3bb37b5 6809intel_e06 (void)
64a0c779 6810{
a724f0f4 6811 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6812
a724f0f4 6813 for (;;)
64a0c779 6814 {
a724f0f4
JB		 6815 if (!intel_e09())
6816 return 0;
9306ca4a 6817
4eed87de
AM		 6818 if (cur_token.code == '*'
6819 || cur_token.code == '/'
6820 || cur_token.code == '%')
a724f0f4
JB		 6821 {
6822 char str[2];
9306ca4a 6823
a724f0f4
JB		 6824 str[0] = cur_token.code;
6825 str[1] = 0;
6826 strcat (intel_parser.disp, str);
6827 }
6828 else if (cur_token.code == T_SHL)
6829 strcat (intel_parser.disp, "<<");
6830 else if (cur_token.code == T_SHR)
6831 strcat (intel_parser.disp, ">>");
6832 else
6833 break;
9306ca4a 6834
64e74474 6835 intel_match_token (cur_token.code);
64a0c779 6836
a724f0f4
JB		 6837 if (nregs < 0)
6838 nregs = ~nregs;
64a0c779 6839 }
a724f0f4
JB		 6840 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6841 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6842 return 1;
64a0c779
DN		 6843}
6844
a724f0f4
JB		 6845/* e09 OFFSET e09
6846 | SHORT e09
6847 | + e09
6848 | - e09
6849 | ~ e09
6850 | NOT e09
9306ca4a
JB		 6851 | e10 e09'
6852
64a0c779 6853 e09' PTR e10 e09'
b77a7acd 6854 | : e10 e09'
64a0c779
DN		 6855 | Empty */
6856static int
e3bb37b5 6857intel_e09 (void)
64a0c779 6858{
a724f0f4
JB		 6859 int nregs = ~NUM_ADDRESS_REGS;
6860 int in_offset = 0;
6861
6862 for (;;)
64a0c779 6863 {
a724f0f4
JB		 6864 /* Don't consume constants here. */
6865 if (cur_token.code == '+' || cur_token.code == '-')
6866 {
6867 /* Need to look one token ahead - if the next token
6868 is a constant, the current token is its sign. */
6869 int next_code;
6870
6871 intel_match_token (cur_token.code);
6872 next_code = cur_token.code;
6873 intel_putback_token ();
6874 if (next_code == T_CONST)
6875 break;
6876 }
6877
6878 /* e09 OFFSET e09 */
6879 if (cur_token.code == T_OFFSET)
6880 {
6881 if (!in_offset++)
6882 ++intel_parser.in_offset;
6883 }
6884
6885 /* e09 SHORT e09 */
6886 else if (cur_token.code == T_SHORT)
6887 intel_parser.op_modifier |= 1 << T_SHORT;
6888
6889 /* e09 + e09 */
6890 else if (cur_token.code == '+')
6891 strcat (intel_parser.disp, "+");
6892
6893 /* e09 - e09
6894 | ~ e09
6895 | NOT e09 */
6896 else if (cur_token.code == '-' || cur_token.code == '~')
6897 {
6898 char str[2];
64a0c779 6899
a724f0f4
JB		 6900 if (nregs < 0)
6901 nregs = ~nregs;
6902 str[0] = cur_token.code;
6903 str[1] = 0;
6904 strcat (intel_parser.disp, str);
6905 }
6906
6907 /* e09 e10 e09' */
6908 else
6909 break;
6910
6911 intel_match_token (cur_token.code);
64a0c779
DN		 6912 }
6913
a724f0f4 6914 for (;;)
9306ca4a 6915 {
a724f0f4
JB		 6916 if (!intel_e10 ())
6917 return 0;
9306ca4a 6918
a724f0f4
JB		 6919 /* e09' PTR e10 e09' */
6920 if (cur_token.code == T_PTR)
6921 {
6922 char suffix;
9306ca4a 6923
a724f0f4
JB		 6924 if (prev_token.code == T_BYTE)
6925 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6926
a724f0f4
JB		 6927 else if (prev_token.code == T_WORD)
6928 {
6929 if (current_templates->start->name[0] == 'l'
6930 && current_templates->start->name[2] == 's'
6931 && current_templates->start->name[3] == 0)
6932 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6933 else if (intel_parser.got_a_float == 2) /* "fi..." */
6934 suffix = SHORT_MNEM_SUFFIX;
6935 else
6936 suffix = WORD_MNEM_SUFFIX;
6937 }
64a0c779 6938
a724f0f4
JB		 6939 else if (prev_token.code == T_DWORD)
6940 {
6941 if (current_templates->start->name[0] == 'l'
6942 && current_templates->start->name[2] == 's'
6943 && current_templates->start->name[3] == 0)
6944 suffix = WORD_MNEM_SUFFIX;
6945 else if (flag_code == CODE_16BIT
6946 && (current_templates->start->opcode_modifier
435acd52 6947 & (Jump | JumpDword)))
a724f0f4
JB		 6948 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6949 else if (intel_parser.got_a_float == 1) /* "f..." */
6950 suffix = SHORT_MNEM_SUFFIX;
6951 else
6952 suffix = LONG_MNEM_SUFFIX;
6953 }
9306ca4a 6954
a724f0f4
JB		 6955 else if (prev_token.code == T_FWORD)
6956 {
6957 if (current_templates->start->name[0] == 'l'
6958 && current_templates->start->name[2] == 's'
6959 && current_templates->start->name[3] == 0)
6960 suffix = LONG_MNEM_SUFFIX;
6961 else if (!intel_parser.got_a_float)
6962 {
6963 if (flag_code == CODE_16BIT)
6964 add_prefix (DATA_PREFIX_OPCODE);
6965 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6966 }
6967 else
6968 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6969 }
64a0c779 6970
a724f0f4
JB		 6971 else if (prev_token.code == T_QWORD)
6972 {
6973 if (intel_parser.got_a_float == 1) /* "f..." */
6974 suffix = LONG_MNEM_SUFFIX;
6975 else
6976 suffix = QWORD_MNEM_SUFFIX;
6977 }
64a0c779 6978
a724f0f4
JB		 6979 else if (prev_token.code == T_TBYTE)
6980 {
6981 if (intel_parser.got_a_float == 1)
6982 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6983 else
6984 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6985 }
9306ca4a 6986
a724f0f4 6987 else if (prev_token.code == T_XMMWORD)
9306ca4a 6988 {
a724f0f4
JB		 6989 /* XXX ignored for now, but accepted since gcc uses it */
6990 suffix = 0;
9306ca4a 6991 }
64a0c779 6992
f16b83df 6993 else
a724f0f4
JB		 6994 {
6995 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6996 return 0;
6997 }
6998
435acd52
JB		 6999 /* Operands for jump/call using 'ptr' notation denote absolute
7000 addresses. */
7001 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7002 i.types[this_operand] |= JumpAbsolute;
7003
a724f0f4
JB		 7004 if (current_templates->start->base_opcode == 0x8d /* lea */)
7005 ;
7006 else if (!i.suffix)
7007 i.suffix = suffix;
7008 else if (i.suffix != suffix)
7009 {
7010 as_bad (_("Conflicting operand modifiers"));
7011 return 0;
7012 }
64a0c779 7013
9306ca4a
JB		 7014 }
7015
a724f0f4
JB		 7016 /* e09' : e10 e09' */
7017 else if (cur_token.code == ':')
9306ca4a 7018 {
a724f0f4
JB		 7019 if (prev_token.code != T_REG)
7020 {
7021 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7022 segment/group identifier (which we don't have), using comma
7023 as the operand separator there is even less consistent, since
7024 there all branches only have a single operand. */
7025 if (this_operand != 0
7026 || intel_parser.in_offset
7027 || intel_parser.in_bracket
7028 || (!(current_templates->start->opcode_modifier
7029 & (Jump|JumpDword|JumpInterSegment))
7030 && !(current_templates->start->operand_types[0]
7031 & JumpAbsolute)))
7032 return intel_match_token (T_NIL);
7033 /* Remember the start of the 2nd operand and terminate 1st
7034 operand here.
7035 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7036 another expression), but it gets at least the simplest case
7037 (a plain number or symbol on the left side) right. */
7038 intel_parser.next_operand = intel_parser.op_string;
7039 *--intel_parser.op_string = '\0';
7040 return intel_match_token (':');
7041 }
9306ca4a 7042 }
64a0c779 7043
a724f0f4 7044 /* e09' Empty */
64a0c779 7045 else
a724f0f4 7046 break;
64a0c779 7047
a724f0f4
JB		 7048 intel_match_token (cur_token.code);
7049
7050 }
7051
7052 if (in_offset)
7053 {
7054 --intel_parser.in_offset;
7055 if (nregs < 0)
7056 nregs = ~nregs;
7057 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7058 {
a724f0f4 7059 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7060 return 0;
7061 }
a724f0f4
JB		 7062 intel_parser.op_modifier |= 1 << T_OFFSET;
7063 }
9306ca4a 7064
a724f0f4
JB		 7065 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7066 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7067 return 1;
7068}
64a0c779 7069
a724f0f4 7070static int
e3bb37b5 7071intel_bracket_expr (void)
a724f0f4
JB		 7072{
7073 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7074 const char *start = intel_parser.op_string;
7075 int len;
7076
7077 if (i.op[this_operand].regs)
7078 return intel_match_token (T_NIL);
7079
7080 intel_match_token ('[');
7081
7082 /* Mark as a memory operand only if it's not already known to be an
7083 offset expression. If it's an offset expression, we need to keep
7084 the brace in. */
7085 if (!intel_parser.in_offset)
7086 {
7087 ++intel_parser.in_bracket;
435acd52
JB		 7088
7089 /* Operands for jump/call inside brackets denote absolute addresses. */
7090 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7091 i.types[this_operand] |= JumpAbsolute;
7092
a724f0f4
JB		 7093 /* Unfortunately gas always diverged from MASM in a respect that can't
7094 be easily fixed without risking to break code sequences likely to be
7095 encountered (the testsuite even check for this): MASM doesn't consider
7096 an expression inside brackets unconditionally as a memory reference.
7097 When that is e.g. a constant, an offset expression, or the sum of the
7098 two, this is still taken as a constant load. gas, however, always
7099 treated these as memory references. As a compromise, we'll try to make
7100 offset expressions inside brackets work the MASM way (since that's
7101 less likely to be found in real world code), but make constants alone
7102 continue to work the traditional gas way. In either case, issue a
7103 warning. */
7104 intel_parser.op_modifier &= ~was_offset;
64a0c779 7105 }
a724f0f4 7106 else
64e74474 7107 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7108
7109 /* Add a '+' to the displacement string if necessary. */
7110 if (*intel_parser.disp != '\0'
7111 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7112 strcat (intel_parser.disp, "+");
64a0c779 7113
a724f0f4
JB		 7114 if (intel_expr ()
7115 && (len = intel_parser.op_string - start - 1,
7116 intel_match_token (']')))
64a0c779 7117 {
a724f0f4
JB		 7118 /* Preserve brackets when the operand is an offset expression. */
7119 if (intel_parser.in_offset)
7120 strcat (intel_parser.disp, "]");
7121 else
7122 {
7123 --intel_parser.in_bracket;
7124 if (i.base_reg || i.index_reg)
7125 intel_parser.is_mem = 1;
7126 if (!intel_parser.is_mem)
7127 {
7128 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7129 /* Defer the warning until all of the operand was parsed. */
7130 intel_parser.is_mem = -1;
7131 else if (!quiet_warnings)
4eed87de
AM		 7132 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7133 len, start, len, start);
a724f0f4
JB		 7134 }
7135 }
7136 intel_parser.op_modifier |= was_offset;
64a0c779 7137
a724f0f4 7138 return 1;
64a0c779 7139 }
a724f0f4 7140 return 0;
64a0c779
DN		 7141}
7142
7143/* e10 e11 e10'
7144
7145 e10' [ expr ] e10'
b77a7acd 7146 | Empty */
64a0c779 7147static int
e3bb37b5 7148intel_e10 (void)
64a0c779 7149{
a724f0f4
JB		 7150 if (!intel_e11 ())
7151 return 0;
64a0c779 7152
a724f0f4 7153 while (cur_token.code == '[')
64a0c779 7154 {
a724f0f4 7155 if (!intel_bracket_expr ())
21d6c4af 7156 return 0;
64a0c779
DN		 7157 }
7158
a724f0f4 7159 return 1;
64a0c779
DN		 7160}
7161
64a0c779 7162/* e11 ( expr )
b77a7acd 7163 | [ expr ]
64a0c779
DN		 7164 | BYTE
7165 | WORD
7166 | DWORD
9306ca4a 7167 | FWORD
64a0c779 7168 | QWORD
9306ca4a
JB		 7169 | TBYTE
7170 | OWORD
7171 | XMMWORD
4a1805b1 7172 | $
64a0c779
DN		 7173 | .
7174 | register
7175 | id
7176 | constant */
7177static int
e3bb37b5 7178intel_e11 (void)
64a0c779 7179{
a724f0f4 7180 switch (cur_token.code)
64a0c779 7181 {
a724f0f4
JB		 7182 /* e11 ( expr ) */
7183 case '(':
64a0c779
DN		 7184 intel_match_token ('(');
7185 strcat (intel_parser.disp, "(");
7186
7187 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7188 {
7189 strcat (intel_parser.disp, ")");
7190 return 1;
7191 }
a724f0f4 7192 return 0;
4a1805b1 7193
a724f0f4
JB		 7194 /* e11 [ expr ] */
7195 case '[':
a724f0f4 7196 return intel_bracket_expr ();
64a0c779 7197
a724f0f4
JB		 7198 /* e11 $
7199 | . */
7200 case '.':
64a0c779
DN		 7201 strcat (intel_parser.disp, cur_token.str);
7202 intel_match_token (cur_token.code);
21d6c4af
DN		 7203
7204 /* Mark as a memory operand only if it's not already known to be an
7205 offset expression. */
a724f0f4 7206 if (!intel_parser.in_offset)
21d6c4af 7207 intel_parser.is_mem = 1;
64a0c779
DN		 7208
7209 return 1;
64a0c779 7210
a724f0f4
JB		 7211 /* e11 register */
7212 case T_REG:
7213 {
7214 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7215
a724f0f4 7216 intel_match_token (T_REG);
64a0c779 7217
a724f0f4
JB		 7218 /* Check for segment change. */
7219 if (cur_token.code == ':')
7220 {
7221 if (!(reg->reg_type & (SReg2 | SReg3)))
7222 {
4eed87de
AM		 7223 as_bad (_("`%s' is not a valid segment register"),
7224 reg->reg_name);
a724f0f4
JB		 7225 return 0;
7226 }
7227 else if (i.seg[i.mem_operands])
7228 as_warn (_("Extra segment override ignored"));
7229 else
7230 {
7231 if (!intel_parser.in_offset)
7232 intel_parser.is_mem = 1;
7233 switch (reg->reg_num)
7234 {
7235 case 0:
7236 i.seg[i.mem_operands] = &es;
7237 break;
7238 case 1:
7239 i.seg[i.mem_operands] = &cs;
7240 break;
7241 case 2:
7242 i.seg[i.mem_operands] = &ss;
7243 break;
7244 case 3:
7245 i.seg[i.mem_operands] = &ds;
7246 break;
7247 case 4:
7248 i.seg[i.mem_operands] = &fs;
7249 break;
7250 case 5:
7251 i.seg[i.mem_operands] = &gs;
7252 break;
7253 }
7254 }
7255 }
64a0c779 7256
a724f0f4
JB		 7257 /* Not a segment register. Check for register scaling. */
7258 else if (cur_token.code == '*')
7259 {
7260 if (!intel_parser.in_bracket)
7261 {
7262 as_bad (_("Register scaling only allowed in memory operands"));
7263 return 0;
7264 }
64a0c779 7265
a724f0f4
JB		 7266 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7267 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7268 else if (i.index_reg)
7269 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7270
a724f0f4
JB		 7271 /* What follows must be a valid scale. */
7272 intel_match_token ('*');
7273 i.index_reg = reg;
7274 i.types[this_operand] |= BaseIndex;
64a0c779 7275
a724f0f4
JB		 7276 /* Set the scale after setting the register (otherwise,
7277 i386_scale will complain) */
7278 if (cur_token.code == '+' || cur_token.code == '-')
7279 {
7280 char *str, sign = cur_token.code;
7281 intel_match_token (cur_token.code);
7282 if (cur_token.code != T_CONST)
7283 {
7284 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7285 cur_token.str);
7286 return 0;
7287 }
7288 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7289 strcpy (str + 1, cur_token.str);
7290 *str = sign;
7291 if (!i386_scale (str))
7292 return 0;
7293 free (str);
7294 }
7295 else if (!i386_scale (cur_token.str))
64a0c779 7296 return 0;
a724f0f4
JB		 7297 intel_match_token (cur_token.code);
7298 }
64a0c779 7299
a724f0f4
JB		 7300 /* No scaling. If this is a memory operand, the register is either a
7301 base register (first occurrence) or an index register (second
7302 occurrence). */
7b0441f6 7303 else if (intel_parser.in_bracket)
a724f0f4 7304 {
64a0c779 7305
a724f0f4
JB		 7306 if (!i.base_reg)
7307 i.base_reg = reg;
7308 else if (!i.index_reg)
7309 i.index_reg = reg;
7310 else
7311 {
7312 as_bad (_("Too many register references in memory operand"));
7313 return 0;
7314 }
64a0c779 7315
a724f0f4
JB		 7316 i.types[this_operand] |= BaseIndex;
7317 }
4a1805b1 7318
4d1bb795
JB		 7319 /* It's neither base nor index. */
7320 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7321 {
7322 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7323 i.op[this_operand].regs = reg;
7324 i.reg_operands++;
7325 }
7326 else
7327 {
7328 as_bad (_("Invalid use of register"));
7329 return 0;
7330 }
64a0c779 7331
a724f0f4
JB		 7332 /* Since registers are not part of the displacement string (except
7333 when we're parsing offset operands), we may need to remove any
7334 preceding '+' from the displacement string. */
7335 if (*intel_parser.disp != '\0'
7336 && !intel_parser.in_offset)
7337 {
7338 char *s = intel_parser.disp;
7339 s += strlen (s) - 1;
7340 if (*s == '+')
7341 *s = '\0';
7342 }
4a1805b1 7343
a724f0f4
JB		 7344 return 1;
7345 }
7346
7347 /* e11 BYTE
7348 | WORD
7349 | DWORD
7350 | FWORD
7351 | QWORD
7352 | TBYTE
7353 | OWORD
7354 | XMMWORD */
7355 case T_BYTE:
7356 case T_WORD:
7357 case T_DWORD:
7358 case T_FWORD:
7359 case T_QWORD:
7360 case T_TBYTE:
7361 case T_XMMWORD:
7362 intel_match_token (cur_token.code);
64a0c779 7363
a724f0f4
JB		 7364 if (cur_token.code == T_PTR)
7365 return 1;
7366
7367 /* It must have been an identifier. */
7368 intel_putback_token ();
7369 cur_token.code = T_ID;
7370 /* FALLTHRU */
7371
7372 /* e11 id
7373 | constant */
7374 case T_ID:
7375 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7376 {
7377 symbolS *symbolP;
7378
a724f0f4
JB		 7379 /* The identifier represents a memory reference only if it's not
7380 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7381 symbolP = symbol_find(cur_token.str);
7382 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7383 intel_parser.is_mem = 1;
7384 }
a724f0f4 7385 /* FALLTHRU */
64a0c779 7386
a724f0f4
JB		 7387 case T_CONST:
7388 case '-':
7389 case '+':
7390 {
7391 char *save_str, sign = 0;
64a0c779 7392
a724f0f4
JB		 7393 /* Allow constants that start with `+' or `-'. */
7394 if (cur_token.code == '-' || cur_token.code == '+')
7395 {
7396 sign = cur_token.code;
7397 intel_match_token (cur_token.code);
7398 if (cur_token.code != T_CONST)
7399 {
7400 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7401 cur_token.str);
7402 return 0;
7403 }
7404 }
64a0c779 7405
a724f0f4
JB		 7406 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7407 strcpy (save_str + !!sign, cur_token.str);
7408 if (sign)
7409 *save_str = sign;
64a0c779 7410
a724f0f4
JB		 7411 /* Get the next token to check for register scaling. */
7412 intel_match_token (cur_token.code);
64a0c779 7413
4eed87de
AM		 7414 /* Check if this constant is a scaling factor for an
7415 index register. */
a724f0f4
JB		 7416 if (cur_token.code == '*')
7417 {
7418 if (intel_match_token ('*') && cur_token.code == T_REG)
7419 {
7420 const reg_entry *reg = cur_token.reg;
7421
7422 if (!intel_parser.in_bracket)
7423 {
4eed87de
AM		 7424 as_bad (_("Register scaling only allowed "
7425 "in memory operands"));
a724f0f4
JB		 7426 return 0;
7427 }
7428
4eed87de
AM		 7429 /* Disallow things like [1*si].
7430 sp and esp are invalid as index. */
7431 if (reg->reg_type & Reg16)
7432 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7433 else if (i.index_reg)
4eed87de 7434 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7435
7436 /* The constant is followed by `* reg', so it must be
7437 a valid scale. */
7438 i.index_reg = reg;
7439 i.types[this_operand] |= BaseIndex;
7440
7441 /* Set the scale after setting the register (otherwise,
7442 i386_scale will complain) */
7443 if (!i386_scale (save_str))
64a0c779 7444 return 0;
a724f0f4
JB		 7445 intel_match_token (T_REG);
7446
7447 /* Since registers are not part of the displacement
7448 string, we may need to remove any preceding '+' from
7449 the displacement string. */
7450 if (*intel_parser.disp != '\0')
7451 {
7452 char *s = intel_parser.disp;
7453 s += strlen (s) - 1;
7454 if (*s == '+')
7455 *s = '\0';
7456 }
7457
7458 free (save_str);
7459
7460 return 1;
7461 }
64a0c779 7462
a724f0f4
JB		 7463 /* The constant was not used for register scaling. Since we have
7464 already consumed the token following `*' we now need to put it
7465 back in the stream. */
64a0c779 7466 intel_putback_token ();
a724f0f4 7467 }
64a0c779 7468
a724f0f4
JB		 7469 /* Add the constant to the displacement string. */
7470 strcat (intel_parser.disp, save_str);
7471 free (save_str);
64a0c779 7472
a724f0f4
JB		 7473 return 1;
7474 }
64a0c779
DN		 7475 }
7476
64a0c779
DN		 7477 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7478 return 0;
7479}
7480
64a0c779
DN		 7481/* Match the given token against cur_token. If they match, read the next
7482 token from the operand string. */
7483static int
e3bb37b5 7484intel_match_token (int code)
64a0c779
DN		 7485{
7486 if (cur_token.code == code)
7487 {
7488 intel_get_token ();
7489 return 1;
7490 }
7491 else
7492 {
0477af35 7493 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7494 return 0;
7495 }
7496}
7497
64a0c779
DN		 7498/* Read a new token from intel_parser.op_string and store it in cur_token. */
7499static void
e3bb37b5 7500intel_get_token (void)
64a0c779
DN		 7501{
7502 char *end_op;
7503 const reg_entry *reg;
7504 struct intel_token new_token;
7505
7506 new_token.code = T_NIL;
7507 new_token.reg = NULL;
7508 new_token.str = NULL;
7509
4a1805b1 7510 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7511 cur_token to prev_token. */
7512 if (prev_token.str)
7513 free (prev_token.str);
7514
7515 prev_token = cur_token;
7516
7517 /* Skip whitespace. */
7518 while (is_space_char (*intel_parser.op_string))
7519 intel_parser.op_string++;
7520
7521 /* Return an empty token if we find nothing else on the line. */
7522 if (*intel_parser.op_string == '\0')
7523 {
7524 cur_token = new_token;
7525 return;
7526 }
7527
7528 /* The new token cannot be larger than the remainder of the operand
7529 string. */
a724f0f4 7530 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7531 new_token.str[0] = '\0';
7532
7533 if (strchr ("0123456789", *intel_parser.op_string))
7534 {
7535 char *p = new_token.str;
7536 char *q = intel_parser.op_string;
7537 new_token.code = T_CONST;
7538
7539 /* Allow any kind of identifier char to encompass floating point and
7540 hexadecimal numbers. */
7541 while (is_identifier_char (*q))
7542 *p++ = *q++;
7543 *p = '\0';
7544
7545 /* Recognize special symbol names [0-9][bf]. */
7546 if (strlen (intel_parser.op_string) == 2
4a1805b1 7547 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7548 || intel_parser.op_string[1] == 'f'))
7549 new_token.code = T_ID;
7550 }
7551
4d1bb795 7552 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7553 {
4d1bb795
JB		 7554 size_t len = end_op - intel_parser.op_string;
7555
64a0c779
DN		 7556 new_token.code = T_REG;
7557 new_token.reg = reg;
7558
4d1bb795
JB		 7559 memcpy (new_token.str, intel_parser.op_string, len);
7560 new_token.str[len] = '\0';
64a0c779
DN		 7561 }
7562
7563 else if (is_identifier_char (*intel_parser.op_string))
7564 {
7565 char *p = new_token.str;
7566 char *q = intel_parser.op_string;
7567
7568 /* A '.' or '$' followed by an identifier char is an identifier.
7569 Otherwise, it's operator '.' followed by an expression. */
7570 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7571 {
9306ca4a
JB		 7572 new_token.code = '.';
7573 new_token.str[0] = '.';
64a0c779
DN		 7574 new_token.str[1] = '\0';
7575 }
7576 else
7577 {
7578 while (is_identifier_char (*q) || *q == '@')
7579 *p++ = *q++;
7580 *p = '\0';
7581
9306ca4a
JB		 7582 if (strcasecmp (new_token.str, "NOT") == 0)
7583 new_token.code = '~';
7584
7585 else if (strcasecmp (new_token.str, "MOD") == 0)
7586 new_token.code = '%';
7587
7588 else if (strcasecmp (new_token.str, "AND") == 0)
7589 new_token.code = '&';
7590
7591 else if (strcasecmp (new_token.str, "OR") == 0)
7592 new_token.code = '|';
7593
7594 else if (strcasecmp (new_token.str, "XOR") == 0)
7595 new_token.code = '^';
7596
7597 else if (strcasecmp (new_token.str, "SHL") == 0)
7598 new_token.code = T_SHL;
7599
7600 else if (strcasecmp (new_token.str, "SHR") == 0)
7601 new_token.code = T_SHR;
7602
7603 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7604 new_token.code = T_BYTE;
7605
7606 else if (strcasecmp (new_token.str, "WORD") == 0)
7607 new_token.code = T_WORD;
7608
7609 else if (strcasecmp (new_token.str, "DWORD") == 0)
7610 new_token.code = T_DWORD;
7611
9306ca4a
JB		 7612 else if (strcasecmp (new_token.str, "FWORD") == 0)
7613 new_token.code = T_FWORD;
7614
64a0c779
DN		 7615 else if (strcasecmp (new_token.str, "QWORD") == 0)
7616 new_token.code = T_QWORD;
7617
9306ca4a
JB		 7618 else if (strcasecmp (new_token.str, "TBYTE") == 0
7619 /* XXX remove (gcc still uses it) */
7620 || strcasecmp (new_token.str, "XWORD") == 0)
7621 new_token.code = T_TBYTE;
7622
7623 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7624 || strcasecmp (new_token.str, "OWORD") == 0)
7625 new_token.code = T_XMMWORD;
64a0c779
DN		 7626
7627 else if (strcasecmp (new_token.str, "PTR") == 0)
7628 new_token.code = T_PTR;
7629
7630 else if (strcasecmp (new_token.str, "SHORT") == 0)
7631 new_token.code = T_SHORT;
7632
7633 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7634 {
7635 new_token.code = T_OFFSET;
7636
7637 /* ??? This is not mentioned in the MASM grammar but gcc
7638 makes use of it with -mintel-syntax. OFFSET may be
7639 followed by FLAT: */
7640 if (strncasecmp (q, " FLAT:", 6) == 0)
7641 strcat (new_token.str, " FLAT:");
7642 }
7643
7644 /* ??? This is not mentioned in the MASM grammar. */
7645 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7646 {
7647 new_token.code = T_OFFSET;
7648 if (*q == ':')
7649 strcat (new_token.str, ":");
7650 else
7651 as_bad (_("`:' expected"));
7652 }
64a0c779
DN		 7653
7654 else
7655 new_token.code = T_ID;
7656 }
7657 }
7658
9306ca4a
JB		 7659 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7660 {
7661 new_token.code = *intel_parser.op_string;
7662 new_token.str[0] = *intel_parser.op_string;
7663 new_token.str[1] = '\0';
7664 }
7665
7666 else if (strchr ("<>", *intel_parser.op_string)
7667 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7668 {
7669 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7670 new_token.str[0] = *intel_parser.op_string;
7671 new_token.str[1] = *intel_parser.op_string;
7672 new_token.str[2] = '\0';
7673 }
7674
64a0c779 7675 else
0477af35 7676 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7677
7678 intel_parser.op_string += strlen (new_token.str);
7679 cur_token = new_token;
7680}
7681
64a0c779
DN		 7682/* Put cur_token back into the token stream and make cur_token point to
7683 prev_token. */
7684static void
e3bb37b5 7685intel_putback_token (void)
64a0c779 7686{
a724f0f4
JB		 7687 if (cur_token.code != T_NIL)
7688 {
7689 intel_parser.op_string -= strlen (cur_token.str);
7690 free (cur_token.str);
7691 }
64a0c779 7692 cur_token = prev_token;
4a1805b1 7693
64a0c779
DN		 7694 /* Forget prev_token. */
7695 prev_token.code = T_NIL;
7696 prev_token.reg = NULL;
7697 prev_token.str = NULL;
7698}
54cfded0 7699
a4447b93 7700int
1df69f4f 7701tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7702{
7703 unsigned int regnum;
7704 unsigned int regnames_count;
089dfecd 7705 static const char *const regnames_32[] =
54cfded0 7706 {
a4447b93
RH		 7707 "eax", "ecx", "edx", "ebx",
7708 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7709 "eip", "eflags", NULL,
7710 "st0", "st1", "st2", "st3",
7711 "st4", "st5", "st6", "st7",
7712 NULL, NULL,
7713 "xmm0", "xmm1", "xmm2", "xmm3",
7714 "xmm4", "xmm5", "xmm6", "xmm7",
7715 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7716 "mm4", "mm5", "mm6", "mm7",
7717 "fcw", "fsw", "mxcsr",
7718 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7719 "tr", "ldtr"
54cfded0 7720 };
089dfecd 7721 static const char *const regnames_64[] =
54cfded0 7722 {
089dfecd
JB		 7723 "rax", "rdx", "rcx", "rbx",
7724 "rsi", "rdi", "rbp", "rsp",
7725 "r8", "r9", "r10", "r11",
54cfded0 7726 "r12", "r13", "r14", "r15",
089dfecd
JB		 7727 "rip",
7728 "xmm0", "xmm1", "xmm2", "xmm3",
7729 "xmm4", "xmm5", "xmm6", "xmm7",
7730 "xmm8", "xmm9", "xmm10", "xmm11",
7731 "xmm12", "xmm13", "xmm14", "xmm15",
7732 "st0", "st1", "st2", "st3",
7733 "st4", "st5", "st6", "st7",
7734 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7735 "mm4", "mm5", "mm6", "mm7",
7736 "rflags",
7737 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7738 "fs.base", "gs.base", NULL, NULL,
7739 "tr", "ldtr",
7740 "mxcsr", "fcw", "fsw"
54cfded0 7741 };
089dfecd 7742 const char *const *regnames;
54cfded0
AM		 7743
7744 if (flag_code == CODE_64BIT)
7745 {
7746 regnames = regnames_64;
0cea6190 7747 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7748 }
7749 else
7750 {
7751 regnames = regnames_32;
0cea6190 7752 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7753 }
7754
7755 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7756 if (regnames[regnum] != NULL
7757 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7758 return regnum;
7759
54cfded0
AM		 7760 return -1;
7761}
7762
7763void
7764tc_x86_frame_initial_instructions (void)
7765{
a4447b93
RH		 7766 static unsigned int sp_regno;
7767
7768 if (!sp_regno)
7769 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7770 ? "rsp" : "esp");
7771
7772 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7773 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7774}
d2b2c203
DJ		 7775
7776int
7777i386_elf_section_type (const char *str, size_t len)
7778{
7779 if (flag_code == CODE_64BIT
7780 && len == sizeof ("unwind") - 1
7781 && strncmp (str, "unwind", 6) == 0)
7782 return SHT_X86_64_UNWIND;
7783
7784 return -1;
7785}
bb41ade5
AM		 7786
7787#ifdef TE_PE
7788void
7789tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7790{
7791 expressionS expr;
7792
7793 expr.X_op = O_secrel;
7794 expr.X_add_symbol = symbol;
7795 expr.X_add_number = 0;
7796 emit_expr (&expr, size);
7797}
7798#endif
3b22753a
L		 7799
7800#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7801/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7802
7803int
7804x86_64_section_letter (int letter, char **ptr_msg)
7805{
7806 if (flag_code == CODE_64BIT)
7807 {
7808 if (letter == 'l')
7809 return SHF_X86_64_LARGE;
7810
7811 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7812 }
3b22753a 7813 else
64e74474 7814 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7815 return -1;
7816}
7817
7818int
7819x86_64_section_word (char *str, size_t len)
7820{
8620418b 7821 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7822 return SHF_X86_64_LARGE;
7823
7824 return -1;
7825}
7826
7827static void
7828handle_large_common (int small ATTRIBUTE_UNUSED)
7829{
7830 if (flag_code != CODE_64BIT)
7831 {
7832 s_comm_internal (0, elf_common_parse);
7833 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7834 }
7835 else
7836 {
7837 static segT lbss_section;
7838 asection *saved_com_section_ptr = elf_com_section_ptr;
7839 asection *saved_bss_section = bss_section;
7840
7841 if (lbss_section == NULL)
7842 {
7843 flagword applicable;
7844 segT seg = now_seg;
7845 subsegT subseg = now_subseg;
7846
7847 /* The .lbss section is for local .largecomm symbols. */
7848 lbss_section = subseg_new (".lbss", 0);
7849 applicable = bfd_applicable_section_flags (stdoutput);
7850 bfd_set_section_flags (stdoutput, lbss_section,
7851 applicable & SEC_ALLOC);
7852 seg_info (lbss_section)->bss = 1;
7853
7854 subseg_set (seg, subseg);
7855 }
7856
7857 elf_com_section_ptr = &_bfd_elf_large_com_section;
7858 bss_section = lbss_section;
7859
7860 s_comm_internal (0, elf_common_parse);
7861
7862 elf_com_section_ptr = saved_com_section_ptr;
7863 bss_section = saved_bss_section;
7864 }
7865}
7866#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.036988 seconds and 4 git commands to generate.