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* s390-dis.c: Fix formatting.
[deliverable/binutils-gdb.git] / gas / config / tc-ia64.c
CommitLineData
800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
f7e42eb4 2 Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
800eeca4
JW		 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
800eeca4
JW		 35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
542d6675
KH		 38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
800eeca4
JW		 42
43 */
44
45#include "as.h"
46#include "dwarf2dbg.h"
47#include "subsegs.h"
48
49#include "opcode/ia64.h"
50
51#include "elf/ia64.h"
52
53#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54#define MIN(a,b) ((a) < (b) ? (a) : (b))
55
56#define NUM_SLOTS 4
57#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58#define CURR_SLOT md.slot[md.curr_slot]
59
60#define O_pseudo_fixup (O_max + 1)
61
62enum special_section
63 {
557debba 64 /* IA-64 ABI section pseudo-ops. */
800eeca4
JW		 65 SPECIAL_SECTION_BSS = 0,
66 SPECIAL_SECTION_SBSS,
67 SPECIAL_SECTION_SDATA,
68 SPECIAL_SECTION_RODATA,
69 SPECIAL_SECTION_COMMENT,
70 SPECIAL_SECTION_UNWIND,
557debba
JW		 71 SPECIAL_SECTION_UNWIND_INFO,
72 /* HPUX specific section pseudo-ops. */
73 SPECIAL_SECTION_INIT_ARRAY,
74 SPECIAL_SECTION_FINI_ARRAY,
800eeca4
JW		 75 };
76
77enum reloc_func
78 {
79 FUNC_FPTR_RELATIVE,
80 FUNC_GP_RELATIVE,
81 FUNC_LT_RELATIVE,
c67e42c9 82 FUNC_PC_RELATIVE,
800eeca4
JW		 83 FUNC_PLT_RELATIVE,
84 FUNC_SEC_RELATIVE,
85 FUNC_SEG_RELATIVE,
86 FUNC_LTV_RELATIVE,
87 FUNC_LT_FPTR_RELATIVE,
88 };
89
90enum reg_symbol
91 {
92 REG_GR = 0,
93 REG_FR = (REG_GR + 128),
94 REG_AR = (REG_FR + 128),
95 REG_CR = (REG_AR + 128),
96 REG_P = (REG_CR + 128),
97 REG_BR = (REG_P + 64),
98 REG_IP = (REG_BR + 8),
99 REG_CFM,
100 REG_PR,
101 REG_PR_ROT,
102 REG_PSR,
103 REG_PSR_L,
104 REG_PSR_UM,
105 /* The following are pseudo-registers for use by gas only. */
106 IND_CPUID,
107 IND_DBR,
108 IND_DTR,
109 IND_ITR,
110 IND_IBR,
111 IND_MEM,
112 IND_MSR,
113 IND_PKR,
114 IND_PMC,
115 IND_PMD,
116 IND_RR,
542d6675 117 /* The following pseudo-registers are used for unwind directives only: */
e0c9811a
JW		 118 REG_PSP,
119 REG_PRIUNAT,
800eeca4
JW		 120 REG_NUM
121 };
122
123enum dynreg_type
124 {
125 DYNREG_GR = 0, /* dynamic general purpose register */
126 DYNREG_FR, /* dynamic floating point register */
127 DYNREG_PR, /* dynamic predicate register */
128 DYNREG_NUM_TYPES
129 };
130
87f8eb97
JW		 131enum operand_match_result
132 {
133 OPERAND_MATCH,
134 OPERAND_OUT_OF_RANGE,
135 OPERAND_MISMATCH
136 };
137
800eeca4
JW		 138/* On the ia64, we can't know the address of a text label until the
139 instructions are packed into a bundle. To handle this, we keep
140 track of the list of labels that appear in front of each
141 instruction. */
142struct label_fix
542d6675
KH		 143{
144 struct label_fix *next;
145 struct symbol *sym;
146};
800eeca4
JW		 147
148extern int target_big_endian;
149
150/* Characters which always start a comment. */
151const char comment_chars[] = "";
152
153/* Characters which start a comment at the beginning of a line. */
154const char line_comment_chars[] = "#";
155
156/* Characters which may be used to separate multiple commands on a
157 single line. */
158const char line_separator_chars[] = ";";
159
160/* Characters which are used to indicate an exponent in a floating
161 point number. */
162const char EXP_CHARS[] = "eE";
163
164/* Characters which mean that a number is a floating point constant,
165 as in 0d1.0. */
166const char FLT_CHARS[] = "rRsSfFdDxXpP";
167
542d6675 168/* ia64-specific option processing: */
800eeca4 169
44f5c83a 170const char *md_shortopts = "m:N:x::";
800eeca4
JW		 171
172struct option md_longopts[] =
173 {
c43c2cc5
JW		 174#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
175 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
176#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
177 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
800eeca4
JW		 178 };
179
180size_t md_longopts_size = sizeof (md_longopts);
181
182static struct
183 {
184 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
185 struct hash_control *reg_hash; /* register name hash table */
186 struct hash_control *dynreg_hash; /* dynamic register hash table */
187 struct hash_control *const_hash; /* constant hash table */
188 struct hash_control *entry_hash; /* code entry hint hash table */
189
190 symbolS *regsym[REG_NUM];
191
192 /* If X_op is != O_absent, the registername for the instruction's
193 qualifying predicate. If NULL, p0 is assumed for instructions
194 that are predicatable. */
195 expressionS qp;
196
197 unsigned int
197865e8 198 manual_bundling : 1,
800eeca4
JW		 199 debug_dv: 1,
200 detect_dv: 1,
201 explicit_mode : 1, /* which mode we're in */
202 default_explicit_mode : 1, /* which mode is the default */
203 mode_explicitly_set : 1, /* was the current mode explicitly set? */
4d5a53ff
JW		 204 auto_align : 1,
205 keep_pending_output : 1;
800eeca4
JW		 206
207 /* Each bundle consists of up to three instructions. We keep
208 track of four most recent instructions so we can correctly set
197865e8 209 the end_of_insn_group for the last instruction in a bundle. */
800eeca4
JW		 210 int curr_slot;
211 int num_slots_in_use;
212 struct slot
213 {
214 unsigned int
215 end_of_insn_group : 1,
216 manual_bundling_on : 1,
217 manual_bundling_off : 1;
218 signed char user_template; /* user-selected template, if any */
219 unsigned char qp_regno; /* qualifying predicate */
220 /* This duplicates a good fraction of "struct fix" but we
221 can't use a "struct fix" instead since we can't call
222 fix_new_exp() until we know the address of the instruction. */
223 int num_fixups;
224 struct insn_fix
225 {
226 bfd_reloc_code_real_type code;
227 enum ia64_opnd opnd; /* type of operand in need of fix */
228 unsigned int is_pcrel : 1; /* is operand pc-relative? */
229 expressionS expr; /* the value to be inserted */
230 }
231 fixup[2]; /* at most two fixups per insn */
232 struct ia64_opcode *idesc;
233 struct label_fix *label_fixups;
f1bcba5b 234 struct label_fix *tag_fixups;
800eeca4
JW		 235 struct unw_rec_list *unwind_record; /* Unwind directive. */
236 expressionS opnd[6];
237 char *src_file;
238 unsigned int src_line;
239 struct dwarf2_line_info debug_line;
240 }
241 slot[NUM_SLOTS];
242
243 segT last_text_seg;
244
245 struct dynreg
246 {
247 struct dynreg *next; /* next dynamic register */
248 const char *name;
249 unsigned short base; /* the base register number */
250 unsigned short num_regs; /* # of registers in this set */
251 }
252 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
253
254 flagword flags; /* ELF-header flags */
255
256 struct mem_offset {
257 unsigned hint:1; /* is this hint currently valid? */
258 bfd_vma offset; /* mem.offset offset */
259 bfd_vma base; /* mem.offset base */
260 } mem_offset;
261
262 int path; /* number of alt. entry points seen */
263 const char **entry_labels; /* labels of all alternate paths in
542d6675 264 the current DV-checking block. */
800eeca4 265 int maxpaths; /* size currently allocated for
542d6675 266 entry_labels */
88be23ec
BS		 267 /* Support for hardware errata workarounds. */
268
269 /* Record data about the last three insn groups. */
270 struct group
271 {
272 /* B-step workaround.
273 For each predicate register, this is set if the corresponding insn
274 group conditionally sets this register with one of the affected
275 instructions. */
276 int p_reg_set[64];
277 /* B-step workaround.
278 For each general register, this is set if the corresponding insn
279 a) is conditional one one of the predicate registers for which
280 P_REG_SET is 1 in the corresponding entry of the previous group,
281 b) sets this general register with one of the affected
282 instructions. */
283 int g_reg_set_conditionally[128];
284 } last_groups[3];
285 int group_idx;
557debba
JW		 286
287 int pointer_size; /* size in bytes of a pointer */
288 int pointer_size_shift; /* shift size of a pointer for alignment */
800eeca4
JW		 289 }
290md;
291
542d6675 292/* application registers: */
800eeca4 293
e0c9811a
JW		 294#define AR_K0 0
295#define AR_K7 7
296#define AR_RSC 16
297#define AR_BSP 17
298#define AR_BSPSTORE 18
299#define AR_RNAT 19
300#define AR_UNAT 36
301#define AR_FPSR 40
302#define AR_ITC 44
303#define AR_PFS 64
304#define AR_LC 65
800eeca4
JW		 305
306static const struct
307 {
308 const char *name;
309 int regnum;
310 }
311ar[] =
312 {
313 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
314 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
315 {"ar.rsc", 16}, {"ar.bsp", 17},
316 {"ar.bspstore", 18}, {"ar.rnat", 19},
317 {"ar.fcr", 21}, {"ar.eflag", 24},
318 {"ar.csd", 25}, {"ar.ssd", 26},
319 {"ar.cflg", 27}, {"ar.fsr", 28},
320 {"ar.fir", 29}, {"ar.fdr", 30},
321 {"ar.ccv", 32}, {"ar.unat", 36},
322 {"ar.fpsr", 40}, {"ar.itc", 44},
323 {"ar.pfs", 64}, {"ar.lc", 65},
197865e8 324 {"ar.ec", 66},
800eeca4
JW		 325 };
326
327#define CR_IPSR 16
328#define CR_ISR 17
329#define CR_IIP 19
330#define CR_IFA 20
331#define CR_ITIR 21
332#define CR_IIPA 22
333#define CR_IFS 23
334#define CR_IIM 24
335#define CR_IHA 25
336#define CR_IVR 65
337#define CR_TPR 66
338#define CR_EOI 67
339#define CR_IRR0 68
340#define CR_IRR3 71
341#define CR_LRR0 80
342#define CR_LRR1 81
343
542d6675 344/* control registers: */
800eeca4
JW		 345static const struct
346 {
347 const char *name;
348 int regnum;
349 }
350cr[] =
351 {
352 {"cr.dcr", 0},
353 {"cr.itm", 1},
354 {"cr.iva", 2},
355 {"cr.pta", 8},
356 {"cr.gpta", 9},
357 {"cr.ipsr", 16},
358 {"cr.isr", 17},
359 {"cr.iip", 19},
360 {"cr.ifa", 20},
361 {"cr.itir", 21},
362 {"cr.iipa", 22},
363 {"cr.ifs", 23},
364 {"cr.iim", 24},
365 {"cr.iha", 25},
366 {"cr.lid", 64},
367 {"cr.ivr", 65},
368 {"cr.tpr", 66},
369 {"cr.eoi", 67},
370 {"cr.irr0", 68},
371 {"cr.irr1", 69},
372 {"cr.irr2", 70},
373 {"cr.irr3", 71},
374 {"cr.itv", 72},
375 {"cr.pmv", 73},
376 {"cr.cmcv", 74},
377 {"cr.lrr0", 80},
378 {"cr.lrr1", 81}
379 };
380
381#define PSR_MFL 4
382#define PSR_IC 13
383#define PSR_DFL 18
384#define PSR_CPL 32
385
386static const struct const_desc
387 {
388 const char *name;
389 valueT value;
390 }
391const_bits[] =
392 {
542d6675 393 /* PSR constant masks: */
800eeca4
JW		 394
395 /* 0: reserved */
396 {"psr.be", ((valueT) 1) << 1},
397 {"psr.up", ((valueT) 1) << 2},
398 {"psr.ac", ((valueT) 1) << 3},
399 {"psr.mfl", ((valueT) 1) << 4},
400 {"psr.mfh", ((valueT) 1) << 5},
401 /* 6-12: reserved */
402 {"psr.ic", ((valueT) 1) << 13},
403 {"psr.i", ((valueT) 1) << 14},
404 {"psr.pk", ((valueT) 1) << 15},
405 /* 16: reserved */
406 {"psr.dt", ((valueT) 1) << 17},
407 {"psr.dfl", ((valueT) 1) << 18},
408 {"psr.dfh", ((valueT) 1) << 19},
409 {"psr.sp", ((valueT) 1) << 20},
410 {"psr.pp", ((valueT) 1) << 21},
411 {"psr.di", ((valueT) 1) << 22},
412 {"psr.si", ((valueT) 1) << 23},
413 {"psr.db", ((valueT) 1) << 24},
414 {"psr.lp", ((valueT) 1) << 25},
415 {"psr.tb", ((valueT) 1) << 26},
416 {"psr.rt", ((valueT) 1) << 27},
417 /* 28-31: reserved */
418 /* 32-33: cpl (current privilege level) */
419 {"psr.is", ((valueT) 1) << 34},
420 {"psr.mc", ((valueT) 1) << 35},
421 {"psr.it", ((valueT) 1) << 36},
422 {"psr.id", ((valueT) 1) << 37},
423 {"psr.da", ((valueT) 1) << 38},
424 {"psr.dd", ((valueT) 1) << 39},
425 {"psr.ss", ((valueT) 1) << 40},
426 /* 41-42: ri (restart instruction) */
427 {"psr.ed", ((valueT) 1) << 43},
428 {"psr.bn", ((valueT) 1) << 44},
429 };
430
542d6675 431/* indirect register-sets/memory: */
800eeca4
JW		 432
433static const struct
434 {
435 const char *name;
436 int regnum;
437 }
438indirect_reg[] =
439 {
440 { "CPUID", IND_CPUID },
441 { "cpuid", IND_CPUID },
442 { "dbr", IND_DBR },
443 { "dtr", IND_DTR },
444 { "itr", IND_ITR },
445 { "ibr", IND_IBR },
446 { "msr", IND_MSR },
447 { "pkr", IND_PKR },
448 { "pmc", IND_PMC },
449 { "pmd", IND_PMD },
450 { "rr", IND_RR },
451 };
452
453/* Pseudo functions used to indicate relocation types (these functions
454 start with an at sign (@). */
455static struct
456 {
457 const char *name;
458 enum pseudo_type
459 {
460 PSEUDO_FUNC_NONE,
461 PSEUDO_FUNC_RELOC,
462 PSEUDO_FUNC_CONST,
e0c9811a 463 PSEUDO_FUNC_REG,
800eeca4
JW		 464 PSEUDO_FUNC_FLOAT
465 }
466 type;
467 union
468 {
469 unsigned long ival;
470 symbolS *sym;
471 }
472 u;
473 }
474pseudo_func[] =
475 {
542d6675 476 /* reloc pseudo functions (these must come first!): */
2434f565
JW		 477 { "fptr", PSEUDO_FUNC_RELOC, { 0 } },
478 { "gprel", PSEUDO_FUNC_RELOC, { 0 } },
479 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } },
480 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } },
481 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } },
482 { "secrel", PSEUDO_FUNC_RELOC, { 0 } },
483 { "segrel", PSEUDO_FUNC_RELOC, { 0 } },
484 { "ltv", PSEUDO_FUNC_RELOC, { 0 } },
485 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
800eeca4 486
542d6675 487 /* mbtype4 constants: */
800eeca4
JW		 488 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
489 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
490 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
491 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
492 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
493
542d6675 494 /* fclass constants: */
bf3ca999 495 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
800eeca4
JW		 496 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
497 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
498 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
499 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
500 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
501 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
502 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
503 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
TW		 504
505 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a 506
542d6675 507 /* unwind-related constants: */
e0c9811a
JW		 508 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
509 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
510 { "nt", PSEUDO_FUNC_CONST, { 2 } },
511
542d6675 512 /* unwind-related registers: */
e0c9811a 513 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
800eeca4
JW		 514 };
515
542d6675 516/* 41-bit nop opcodes (one per unit): */
800eeca4
JW		 517static const bfd_vma nop[IA64_NUM_UNITS] =
518 {
519 0x0000000000LL, /* NIL => break 0 */
520 0x0008000000LL, /* I-unit nop */
521 0x0008000000LL, /* M-unit nop */
522 0x4000000000LL, /* B-unit nop */
523 0x0008000000LL, /* F-unit nop */
524 0x0008000000LL, /* L-"unit" nop */
525 0x0008000000LL, /* X-unit nop */
526 };
527
528/* Can't be `const' as it's passed to input routines (which have the
529 habit of setting temporary sentinels. */
530static char special_section_name[][20] =
531 {
532 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
557debba
JW		 533 {".IA_64.unwind"}, {".IA_64.unwind_info"},
534 {".init_array"}, {".fini_array"}
800eeca4
JW		 535 };
536
579f31ac
JJ		 537static char *special_linkonce_name[] =
538 {
539 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
540 };
541
800eeca4
JW		 542/* The best template for a particular sequence of up to three
543 instructions: */
544#define N IA64_NUM_TYPES
545static unsigned char best_template[N][N][N];
546#undef N
547
548/* Resource dependencies currently in effect */
549static struct rsrc {
550 int depind; /* dependency index */
551 const struct ia64_dependency *dependency; /* actual dependency */
552 unsigned specific:1, /* is this a specific bit/regno? */
553 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
554 int index; /* specific regno/bit within dependency */
555 int note; /* optional qualifying note (0 if none) */
556#define STATE_NONE 0
557#define STATE_STOP 1
558#define STATE_SRLZ 2
559 int insn_srlz; /* current insn serialization state */
560 int data_srlz; /* current data serialization state */
561 int qp_regno; /* qualifying predicate for this usage */
562 char *file; /* what file marked this dependency */
2434f565 563 unsigned int line; /* what line marked this dependency */
800eeca4 564 struct mem_offset mem_offset; /* optional memory offset hint */
7484b8e6 565 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
800eeca4
JW		 566 int path; /* corresponding code entry index */
567} *regdeps = NULL;
568static int regdepslen = 0;
569static int regdepstotlen = 0;
570static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
571static const char *dv_sem[] = { "none", "implied", "impliedf",
139368c9 572 "data", "instr", "specific", "stop", "other" };
7484b8e6 573static const char *dv_cmp_type[] = { "none", "OR", "AND" };
800eeca4
JW		 574
575/* Current state of PR mutexation */
576static struct qpmutex {
577 valueT prmask;
578 int path;
579} *qp_mutexes = NULL; /* QP mutex bitmasks */
580static int qp_mutexeslen = 0;
581static int qp_mutexestotlen = 0;
197865e8 582static valueT qp_safe_across_calls = 0;
800eeca4
JW		 583
584/* Current state of PR implications */
585static struct qp_imply {
586 unsigned p1:6;
587 unsigned p2:6;
588 unsigned p2_branched:1;
589 int path;
590} *qp_implies = NULL;
591static int qp_implieslen = 0;
592static int qp_impliestotlen = 0;
593
197865e8
KH		 594/* Keep track of static GR values so that indirect register usage can
595 sometimes be tracked. */
800eeca4
JW		 596static struct gr {
597 unsigned known:1;
598 int path;
599 valueT value;
2434f565 600} gr_values[128] = {{ 1, 0, 0 }};
800eeca4
JW		 601
602/* These are the routines required to output the various types of
603 unwind records. */
604
f5a30c2e
JW		 605/* A slot_number is a frag address plus the slot index (0-2). We use the
606 frag address here so that if there is a section switch in the middle of
607 a function, then instructions emitted to a different section are not
608 counted. Since there may be more than one frag for a function, this
609 means we also need to keep track of which frag this address belongs to
610 so we can compute inter-frag distances. This also nicely solves the
611 problem with nops emitted for align directives, which can't easily be
612 counted, but can easily be derived from frag sizes. */
613
800eeca4
JW		 614typedef struct unw_rec_list {
615 unwind_record r;
e0c9811a 616 unsigned long slot_number;
f5a30c2e 617 fragS *slot_frag;
800eeca4
JW		 618 struct unw_rec_list *next;
619} unw_rec_list;
620
2434f565 621#define SLOT_NUM_NOT_SET (unsigned)-1
800eeca4 622
e0c9811a
JW		 623static struct
624{
625 unsigned long next_slot_number;
f5a30c2e 626 fragS *next_slot_frag;
e0c9811a
JW		 627
628 /* Maintain a list of unwind entries for the current function. */
629 unw_rec_list *list;
630 unw_rec_list *tail;
800eeca4 631
e0c9811a
JW		 632 /* Any unwind entires that should be attached to the current slot
633 that an insn is being constructed for. */
634 unw_rec_list *current_entry;
800eeca4 635
e0c9811a
JW		 636 /* These are used to create the unwind table entry for this function. */
637 symbolS *proc_start;
638 symbolS *proc_end;
639 symbolS *info; /* pointer to unwind info */
640 symbolS *personality_routine;
91a2ae2a
RH		 641 segT saved_text_seg;
642 subsegT saved_text_subseg;
643 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */
800eeca4 644
e0c9811a
JW		 645 /* TRUE if processing unwind directives in a prologue region. */
646 int prologue;
30d25259 647 int prologue_mask;
33d01f33 648 unsigned int prologue_count; /* number of .prologues seen so far */
e0c9811a 649} unwind;
800eeca4
JW		 650
651typedef void (*vbyte_func) PARAMS ((int, char *, char *));
652
542d6675 653/* Forward delarations: */
800eeca4
JW		 654static int ar_is_in_integer_unit PARAMS ((int regnum));
655static void set_section PARAMS ((char *name));
656static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
657 unsigned int, unsigned int));
658static void dot_radix PARAMS ((int));
659static void dot_special_section PARAMS ((int));
660static void dot_proc PARAMS ((int));
661static void dot_fframe PARAMS ((int));
662static void dot_vframe PARAMS ((int));
150f24a2
JW		 663static void dot_vframesp PARAMS ((int));
664static void dot_vframepsp PARAMS ((int));
800eeca4
JW		 665static void dot_save PARAMS ((int));
666static void dot_restore PARAMS ((int));
150f24a2
JW		 667static void dot_restorereg PARAMS ((int));
668static void dot_restorereg_p PARAMS ((int));
800eeca4
JW		 669static void dot_handlerdata PARAMS ((int));
670static void dot_unwentry PARAMS ((int));
671static void dot_altrp PARAMS ((int));
e0c9811a 672static void dot_savemem PARAMS ((int));
800eeca4
JW		 673static void dot_saveg PARAMS ((int));
674static void dot_savef PARAMS ((int));
675static void dot_saveb PARAMS ((int));
676static void dot_savegf PARAMS ((int));
677static void dot_spill PARAMS ((int));
150f24a2
JW		 678static void dot_spillreg PARAMS ((int));
679static void dot_spillmem PARAMS ((int));
680static void dot_spillreg_p PARAMS ((int));
681static void dot_spillmem_p PARAMS ((int));
682static void dot_label_state PARAMS ((int));
683static void dot_copy_state PARAMS ((int));
800eeca4
JW		 684static void dot_unwabi PARAMS ((int));
685static void dot_personality PARAMS ((int));
686static void dot_body PARAMS ((int));
687static void dot_prologue PARAMS ((int));
688static void dot_endp PARAMS ((int));
689static void dot_template PARAMS ((int));
690static void dot_regstk PARAMS ((int));
691static void dot_rot PARAMS ((int));
692static void dot_byteorder PARAMS ((int));
693static void dot_psr PARAMS ((int));
694static void dot_alias PARAMS ((int));
695static void dot_ln PARAMS ((int));
696static char *parse_section_name PARAMS ((void));
697static void dot_xdata PARAMS ((int));
698static void stmt_float_cons PARAMS ((int));
699static void stmt_cons_ua PARAMS ((int));
700static void dot_xfloat_cons PARAMS ((int));
701static void dot_xstringer PARAMS ((int));
702static void dot_xdata_ua PARAMS ((int));
703static void dot_xfloat_cons_ua PARAMS ((int));
150f24a2 704static void print_prmask PARAMS ((valueT mask));
800eeca4
JW		 705static void dot_pred_rel PARAMS ((int));
706static void dot_reg_val PARAMS ((int));
707static void dot_dv_mode PARAMS ((int));
708static void dot_entry PARAMS ((int));
709static void dot_mem_offset PARAMS ((int));
e0c9811a 710static void add_unwind_entry PARAMS((unw_rec_list *ptr));
542d6675 711static symbolS *declare_register PARAMS ((const char *name, int regnum));
800eeca4
JW		 712static void declare_register_set PARAMS ((const char *, int, int));
713static unsigned int operand_width PARAMS ((enum ia64_opnd));
87f8eb97
JW		 714static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc,
715 int index,
716 expressionS *e));
800eeca4
JW		 717static int parse_operand PARAMS ((expressionS *e));
718static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
719static void build_insn PARAMS ((struct slot *, bfd_vma *));
720static void emit_one_bundle PARAMS ((void));
721static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
197865e8 722static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
800eeca4
JW		 723 bfd_reloc_code_real_type r_type));
724static void insn_group_break PARAMS ((int, int, int));
150f24a2
JW		 725static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
726 struct rsrc *, int depind, int path));
800eeca4
JW		 727static void add_qp_mutex PARAMS((valueT mask));
728static void add_qp_imply PARAMS((int p1, int p2));
729static void clear_qp_branch_flag PARAMS((valueT mask));
730static void clear_qp_mutex PARAMS((valueT mask));
731static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
732static void clear_register_values PARAMS ((void));
733static void print_dependency PARAMS ((const char *action, int depind));
150f24a2
JW		 734static void instruction_serialization PARAMS ((void));
735static void data_serialization PARAMS ((void));
736static void remove_marked_resource PARAMS ((struct rsrc *));
800eeca4 737static int is_conditional_branch PARAMS ((struct ia64_opcode *));
150f24a2 738static int is_taken_branch PARAMS ((struct ia64_opcode *));
800eeca4 739static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
150f24a2
JW		 740static int depends_on PARAMS ((int, struct ia64_opcode *));
741static int specify_resource PARAMS ((const struct ia64_dependency *,
742 struct ia64_opcode *, int, struct rsrc [], int, int));
800eeca4
JW		 743static int check_dv PARAMS((struct ia64_opcode *idesc));
744static void check_dependencies PARAMS((struct ia64_opcode *));
745static void mark_resources PARAMS((struct ia64_opcode *));
746static void update_dependencies PARAMS((struct ia64_opcode *));
747static void note_register_values PARAMS((struct ia64_opcode *));
150f24a2
JW		 748static int qp_mutex PARAMS ((int, int, int));
749static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
750static void output_vbyte_mem PARAMS ((int, char *, char *));
751static void count_output PARAMS ((int, char *, char *));
752static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
753static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
800eeca4 754static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 755static void output_P1_format PARAMS ((vbyte_func, int));
756static void output_P2_format PARAMS ((vbyte_func, int, int));
757static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
758static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
759static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
760static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
761static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
762static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
763static void output_P9_format PARAMS ((vbyte_func, int, int));
764static void output_P10_format PARAMS ((vbyte_func, int, int));
765static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
766static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800eeca4
JW		 767static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
768static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 769static char format_ab_reg PARAMS ((int, int));
770static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
771 unsigned long));
772static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
773static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
774 unsigned long));
775static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
776static void free_list_records PARAMS ((unw_rec_list *));
777static unw_rec_list *output_prologue PARAMS ((void));
778static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
779static unw_rec_list *output_body PARAMS ((void));
780static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
781static unw_rec_list *output_mem_stack_v PARAMS ((void));
782static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
783static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
784static unw_rec_list *output_rp_when PARAMS ((void));
785static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
786static unw_rec_list *output_rp_br PARAMS ((unsigned int));
787static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
788static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
789static unw_rec_list *output_pfs_when PARAMS ((void));
790static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
791static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
792static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
793static unw_rec_list *output_preds_when PARAMS ((void));
794static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
795static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
796static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
797static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
798static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
799static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
800static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
801static unw_rec_list *output_br_mem PARAMS ((unsigned int));
802static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
803static unw_rec_list *output_spill_base PARAMS ((unsigned int));
804static unw_rec_list *output_unat_when PARAMS ((void));
805static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
806static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
807static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
808static unw_rec_list *output_lc_when PARAMS ((void));
809static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
810static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
811static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
812static unw_rec_list *output_fpsr_when PARAMS ((void));
813static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
814static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
815static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
816static unw_rec_list *output_priunat_when_gr PARAMS ((void));
817static unw_rec_list *output_priunat_when_mem PARAMS ((void));
818static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
819static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
820static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
821static unw_rec_list *output_bsp_when PARAMS ((void));
822static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
823static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
824static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
825static unw_rec_list *output_bspstore_when PARAMS ((void));
826static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
827static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
828static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
829static unw_rec_list *output_rnat_when PARAMS ((void));
830static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
831static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
832static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
833static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
834static unw_rec_list *output_epilogue PARAMS ((unsigned long));
835static unw_rec_list *output_label_state PARAMS ((unsigned long));
836static unw_rec_list *output_copy_state PARAMS ((unsigned long));
837static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
838static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
839static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
840 unsigned int));
841static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
842 unsigned int));
843static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
844 unsigned int));
845static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
846 unsigned int, unsigned int));
847static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
848static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
849static int calc_record_size PARAMS ((unw_rec_list *));
850static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
851static int count_bits PARAMS ((unsigned long));
f5a30c2e
JW		 852static unsigned long slot_index PARAMS ((unsigned long, fragS *,
853 unsigned long, fragS *));
91a2ae2a 854static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *));
150f24a2
JW		 855static void fixup_unw_records PARAMS ((unw_rec_list *));
856static int output_unw_records PARAMS ((unw_rec_list *, void **));
857static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
858static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
91a2ae2a
RH		 859static int generate_unwind_image PARAMS ((const char *));
860
861/* Build the unwind section name by appending the (possibly stripped)
862 text section NAME to the unwind PREFIX. The resulting string
863 pointer is assigned to RESULT. The string is allocated on the
864 stack, so this must be a macro... */
865#define make_unw_section_name(special, text_name, result) \
866 { \
867 char *_prefix = special_section_name[special]; \
579f31ac
JJ		 868 char *_suffix = text_name; \
869 size_t _prefix_len, _suffix_len; \
870 char *_result; \
871 if (strncmp (text_name, ".gnu.linkonce.t.", \
872 sizeof (".gnu.linkonce.t.") - 1) == 0) \
873 { \
874 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
875 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
876 } \
877 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
878 _result = alloca (_prefix_len + _suffix_len + 1); \
91a2ae2a 879 memcpy(_result, _prefix, _prefix_len); \
579f31ac
JJ		 880 memcpy(_result + _prefix_len, _suffix, _suffix_len); \
881 _result[_prefix_len + _suffix_len] = '\0'; \
91a2ae2a
RH		 882 result = _result; \
883 } \
884while (0)
800eeca4
JW		 885
886/* Determine if application register REGNUM resides in the integer
887 unit (as opposed to the memory unit). */
888static int
889ar_is_in_integer_unit (reg)
890 int reg;
891{
892 reg -= REG_AR;
893
894 return (reg == 64 /* pfs */
895 || reg == 65 /* lc */
896 || reg == 66 /* ec */
897 /* ??? ias accepts and puts these in the integer unit. */
898 || (reg >= 112 && reg <= 127));
899}
900
901/* Switch to section NAME and create section if necessary. It's
902 rather ugly that we have to manipulate input_line_pointer but I
903 don't see any other way to accomplish the same thing without
904 changing obj-elf.c (which may be the Right Thing, in the end). */
905static void
906set_section (name)
907 char *name;
908{
909 char *saved_input_line_pointer;
910
911 saved_input_line_pointer = input_line_pointer;
912 input_line_pointer = name;
913 obj_elf_section (0);
914 input_line_pointer = saved_input_line_pointer;
915}
916
917/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
918
919flagword
920ia64_elf_section_flags (flags, attr, type)
921 flagword flags;
2434f565 922 int attr, type ATTRIBUTE_UNUSED;
800eeca4
JW		 923{
924 if (attr & SHF_IA_64_SHORT)
925 flags |= SEC_SMALL_DATA;
926 return flags;
927}
928
91a2ae2a
RH		 929int
930ia64_elf_section_type (str, len)
931 const char *str;
932 size_t len;
933{
934 len = sizeof (ELF_STRING_ia64_unwind_info) - 1;
935 if (strncmp (str, ELF_STRING_ia64_unwind_info, len) == 0)
936 return SHT_PROGBITS;
937
579f31ac
JJ		 938 len = sizeof (ELF_STRING_ia64_unwind_info_once) - 1;
939 if (strncmp (str, ELF_STRING_ia64_unwind_info_once, len) == 0)
940 return SHT_PROGBITS;
941
91a2ae2a
RH		 942 len = sizeof (ELF_STRING_ia64_unwind) - 1;
943 if (strncmp (str, ELF_STRING_ia64_unwind, len) == 0)
944 return SHT_IA_64_UNWIND;
945
579f31ac
JJ		 946 len = sizeof (ELF_STRING_ia64_unwind_once) - 1;
947 if (strncmp (str, ELF_STRING_ia64_unwind_once, len) == 0)
948 return SHT_IA_64_UNWIND;
949
91a2ae2a
RH		 950 return -1;
951}
952
800eeca4
JW		 953static unsigned int
954set_regstack (ins, locs, outs, rots)
955 unsigned int ins, locs, outs, rots;
956{
542d6675
KH		 957 /* Size of frame. */
958 unsigned int sof;
800eeca4
JW		 959
960 sof = ins + locs + outs;
961 if (sof > 96)
962 {
963 as_bad ("Size of frame exceeds maximum of 96 registers");
964 return 0;
965 }
966 if (rots > sof)
967 {
968 as_warn ("Size of rotating registers exceeds frame size");
969 return 0;
970 }
971 md.in.base = REG_GR + 32;
972 md.loc.base = md.in.base + ins;
973 md.out.base = md.loc.base + locs;
974
975 md.in.num_regs = ins;
976 md.loc.num_regs = locs;
977 md.out.num_regs = outs;
978 md.rot.num_regs = rots;
979 return sof;
980}
981
982void
983ia64_flush_insns ()
984{
985 struct label_fix *lfix;
986 segT saved_seg;
987 subsegT saved_subseg;
b44b1b85 988 unw_rec_list *ptr;
800eeca4
JW		 989
990 if (!md.last_text_seg)
991 return;
992
993 saved_seg = now_seg;
994 saved_subseg = now_subseg;
995
996 subseg_set (md.last_text_seg, 0);
997
998 while (md.num_slots_in_use > 0)
999 emit_one_bundle (); /* force out queued instructions */
1000
1001 /* In case there are labels following the last instruction, resolve
542d6675 1002 those now: */
800eeca4
JW		 1003 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
1004 {
1005 S_SET_VALUE (lfix->sym, frag_now_fix ());
1006 symbol_set_frag (lfix->sym, frag_now);
1007 }
1008 CURR_SLOT.label_fixups = 0;
f1bcba5b
JW		 1009 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
1010 {
1011 S_SET_VALUE (lfix->sym, frag_now_fix ());
1012 symbol_set_frag (lfix->sym, frag_now);
1013 }
1014 CURR_SLOT.tag_fixups = 0;
800eeca4 1015
b44b1b85
JW		 1016 /* In case there are unwind directives following the last instruction,
1017 resolve those now. We only handle body and prologue directives here.
1018 Give an error for others. */
1019 for (ptr = unwind.current_entry; ptr; ptr = ptr->next)
1020 {
1021 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
1022 || ptr->r.type == body)
1023 {
1024 ptr->slot_number = (unsigned long) frag_more (0);
1025 ptr->slot_frag = frag_now;
1026 }
1027 else
1028 as_bad (_("Unwind directive not followed by an instruction."));
1029 }
1030 unwind.current_entry = NULL;
1031
800eeca4 1032 subseg_set (saved_seg, saved_subseg);
f1bcba5b
JW		 1033
1034 if (md.qp.X_op == O_register)
1035 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW		 1036}
1037
1038void
1039ia64_do_align (nbytes)
1040 int nbytes;
1041{
1042 char *saved_input_line_pointer = input_line_pointer;
1043
1044 input_line_pointer = "";
1045 s_align_bytes (nbytes);
1046 input_line_pointer = saved_input_line_pointer;
1047}
1048
1049void
1050ia64_cons_align (nbytes)
1051 int nbytes;
1052{
1053 if (md.auto_align)
1054 {
1055 char *saved_input_line_pointer = input_line_pointer;
1056 input_line_pointer = "";
1057 s_align_bytes (nbytes);
1058 input_line_pointer = saved_input_line_pointer;
1059 }
1060}
1061
1062/* Output COUNT bytes to a memory location. */
1063static unsigned char *vbyte_mem_ptr = NULL;
1064
197865e8 1065void
800eeca4
JW		 1066output_vbyte_mem (count, ptr, comment)
1067 int count;
1068 char *ptr;
2434f565 1069 char *comment ATTRIBUTE_UNUSED;
800eeca4
JW		 1070{
1071 int x;
1072 if (vbyte_mem_ptr == NULL)
1073 abort ();
1074
1075 if (count == 0)
1076 return;
1077 for (x = 0; x < count; x++)
1078 *(vbyte_mem_ptr++) = ptr[x];
1079}
1080
1081/* Count the number of bytes required for records. */
1082static int vbyte_count = 0;
197865e8 1083void
800eeca4
JW		 1084count_output (count, ptr, comment)
1085 int count;
2434f565
JW		 1086 char *ptr ATTRIBUTE_UNUSED;
1087 char *comment ATTRIBUTE_UNUSED;
800eeca4
JW		 1088{
1089 vbyte_count += count;
1090}
1091
1092static void
1093output_R1_format (f, rtype, rlen)
1094 vbyte_func f;
1095 unw_record_type rtype;
1096 int rlen;
1097{
e0c9811a 1098 int r = 0;
800eeca4
JW		 1099 char byte;
1100 if (rlen > 0x1f)
1101 {
1102 output_R3_format (f, rtype, rlen);
1103 return;
1104 }
197865e8 1105
e0c9811a
JW		 1106 if (rtype == body)
1107 r = 1;
1108 else if (rtype != prologue)
1109 as_bad ("record type is not valid");
1110
800eeca4
JW		 1111 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
1112 (*f) (1, &byte, NULL);
1113}
1114
1115static void
1116output_R2_format (f, mask, grsave, rlen)
1117 vbyte_func f;
1118 int mask, grsave;
1119 unsigned long rlen;
1120{
1121 char bytes[20];
1122 int count = 2;
1123 mask = (mask & 0x0f);
1124 grsave = (grsave & 0x7f);
1125
1126 bytes[0] = (UNW_R2 | (mask >> 1));
1127 bytes[1] = (((mask & 0x01) << 7) | grsave);
1128 count += output_leb128 (bytes + 2, rlen, 0);
1129 (*f) (count, bytes, NULL);
1130}
1131
1132static void
1133output_R3_format (f, rtype, rlen)
1134 vbyte_func f;
1135 unw_record_type rtype;
1136 unsigned long rlen;
1137{
e0c9811a 1138 int r = 0, count;
800eeca4
JW		 1139 char bytes[20];
1140 if (rlen <= 0x1f)
1141 {
1142 output_R1_format (f, rtype, rlen);
1143 return;
1144 }
197865e8 1145
e0c9811a
JW		 1146 if (rtype == body)
1147 r = 1;
1148 else if (rtype != prologue)
1149 as_bad ("record type is not valid");
800eeca4
JW		 1150 bytes[0] = (UNW_R3 | r);
1151 count = output_leb128 (bytes + 1, rlen, 0);
1152 (*f) (count + 1, bytes, NULL);
1153}
1154
1155static void
1156output_P1_format (f, brmask)
1157 vbyte_func f;
1158 int brmask;
1159{
1160 char byte;
1161 byte = UNW_P1 | (brmask & 0x1f);
1162 (*f) (1, &byte, NULL);
1163}
1164
1165static void
1166output_P2_format (f, brmask, gr)
1167 vbyte_func f;
1168 int brmask;
1169 int gr;
1170{
1171 char bytes[2];
1172 brmask = (brmask & 0x1f);
1173 bytes[0] = UNW_P2 | (brmask >> 1);
1174 bytes[1] = (((brmask & 1) << 7) | gr);
1175 (*f) (2, bytes, NULL);
1176}
1177
1178static void
1179output_P3_format (f, rtype, reg)
1180 vbyte_func f;
1181 unw_record_type rtype;
1182 int reg;
1183{
1184 char bytes[2];
e0c9811a 1185 int r = 0;
800eeca4
JW		 1186 reg = (reg & 0x7f);
1187 switch (rtype)
542d6675 1188 {
800eeca4
JW		 1189 case psp_gr:
1190 r = 0;
1191 break;
1192 case rp_gr:
1193 r = 1;
1194 break;
1195 case pfs_gr:
1196 r = 2;
1197 break;
1198 case preds_gr:
1199 r = 3;
1200 break;
1201 case unat_gr:
1202 r = 4;
1203 break;
1204 case lc_gr:
1205 r = 5;
1206 break;
1207 case rp_br:
1208 r = 6;
1209 break;
1210 case rnat_gr:
1211 r = 7;
1212 break;
1213 case bsp_gr:
1214 r = 8;
1215 break;
1216 case bspstore_gr:
1217 r = 9;
1218 break;
1219 case fpsr_gr:
1220 r = 10;
1221 break;
1222 case priunat_gr:
1223 r = 11;
1224 break;
1225 default:
1226 as_bad ("Invalid record type for P3 format.");
542d6675 1227 }
800eeca4
JW		 1228 bytes[0] = (UNW_P3 | (r >> 1));
1229 bytes[1] = (((r & 1) << 7) | reg);
1230 (*f) (2, bytes, NULL);
1231}
1232
800eeca4 1233static void
e0c9811a 1234output_P4_format (f, imask, imask_size)
800eeca4 1235 vbyte_func f;
e0c9811a
JW		 1236 unsigned char *imask;
1237 unsigned long imask_size;
800eeca4 1238{
e0c9811a
JW		 1239 imask[0] = UNW_P4;
1240 (*f) (imask_size, imask, NULL);
800eeca4
JW		 1241}
1242
1243static void
1244output_P5_format (f, grmask, frmask)
1245 vbyte_func f;
1246 int grmask;
1247 unsigned long frmask;
1248{
1249 char bytes[4];
1250 grmask = (grmask & 0x0f);
1251
1252 bytes[0] = UNW_P5;
1253 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1254 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1255 bytes[3] = (frmask & 0x000000ff);
1256 (*f) (4, bytes, NULL);
1257}
1258
1259static void
1260output_P6_format (f, rtype, rmask)
1261 vbyte_func f;
1262 unw_record_type rtype;
1263 int rmask;
1264{
1265 char byte;
e0c9811a 1266 int r = 0;
197865e8 1267
e0c9811a
JW		 1268 if (rtype == gr_mem)
1269 r = 1;
1270 else if (rtype != fr_mem)
1271 as_bad ("Invalid record type for format P6");
800eeca4
JW		 1272 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1273 (*f) (1, &byte, NULL);
1274}
1275
1276static void
1277output_P7_format (f, rtype, w1, w2)
1278 vbyte_func f;
1279 unw_record_type rtype;
1280 unsigned long w1;
1281 unsigned long w2;
1282{
1283 char bytes[20];
1284 int count = 1;
e0c9811a 1285 int r = 0;
800eeca4
JW		 1286 count += output_leb128 (bytes + 1, w1, 0);
1287 switch (rtype)
1288 {
542d6675
KH		 1289 case mem_stack_f:
1290 r = 0;
1291 count += output_leb128 (bytes + count, w2 >> 4, 0);
1292 break;
1293 case mem_stack_v:
1294 r = 1;
1295 break;
1296 case spill_base:
1297 r = 2;
1298 break;
1299 case psp_sprel:
1300 r = 3;
1301 break;
1302 case rp_when:
1303 r = 4;
1304 break;
1305 case rp_psprel:
1306 r = 5;
1307 break;
1308 case pfs_when:
1309 r = 6;
1310 break;
1311 case pfs_psprel:
1312 r = 7;
1313 break;
1314 case preds_when:
1315 r = 8;
1316 break;
1317 case preds_psprel:
1318 r = 9;
1319 break;
1320 case lc_when:
1321 r = 10;
1322 break;
1323 case lc_psprel:
1324 r = 11;
1325 break;
1326 case unat_when:
1327 r = 12;
1328 break;
1329 case unat_psprel:
1330 r = 13;
1331 break;
1332 case fpsr_when:
1333 r = 14;
1334 break;
1335 case fpsr_psprel:
1336 r = 15;
1337 break;
1338 default:
1339 break;
800eeca4
JW		 1340 }
1341 bytes[0] = (UNW_P7 | r);
1342 (*f) (count, bytes, NULL);
1343}
1344
1345static void
1346output_P8_format (f, rtype, t)
1347 vbyte_func f;
1348 unw_record_type rtype;
1349 unsigned long t;
1350{
1351 char bytes[20];
e0c9811a 1352 int r = 0;
800eeca4
JW		 1353 int count = 2;
1354 bytes[0] = UNW_P8;
1355 switch (rtype)
1356 {
542d6675
KH		 1357 case rp_sprel:
1358 r = 1;
1359 break;
1360 case pfs_sprel:
1361 r = 2;
1362 break;
1363 case preds_sprel:
1364 r = 3;
1365 break;
1366 case lc_sprel:
1367 r = 4;
1368 break;
1369 case unat_sprel:
1370 r = 5;
1371 break;
1372 case fpsr_sprel:
1373 r = 6;
1374 break;
1375 case bsp_when:
1376 r = 7;
1377 break;
1378 case bsp_psprel:
1379 r = 8;
1380 break;
1381 case bsp_sprel:
1382 r = 9;
1383 break;
1384 case bspstore_when:
1385 r = 10;
1386 break;
1387 case bspstore_psprel:
1388 r = 11;
1389 break;
1390 case bspstore_sprel:
1391 r = 12;
1392 break;
1393 case rnat_when:
1394 r = 13;
1395 break;
1396 case rnat_psprel:
1397 r = 14;
1398 break;
1399 case rnat_sprel:
1400 r = 15;
1401 break;
1402 case priunat_when_gr:
1403 r = 16;
1404 break;
1405 case priunat_psprel:
1406 r = 17;
1407 break;
1408 case priunat_sprel:
1409 r = 18;
1410 break;
1411 case priunat_when_mem:
1412 r = 19;
1413 break;
1414 default:
1415 break;
800eeca4
JW		 1416 }
1417 bytes[1] = r;
1418 count += output_leb128 (bytes + 2, t, 0);
1419 (*f) (count, bytes, NULL);
1420}
1421
1422static void
1423output_P9_format (f, grmask, gr)
1424 vbyte_func f;
1425 int grmask;
1426 int gr;
1427{
1428 char bytes[3];
1429 bytes[0] = UNW_P9;
1430 bytes[1] = (grmask & 0x0f);
1431 bytes[2] = (gr & 0x7f);
1432 (*f) (3, bytes, NULL);
1433}
1434
1435static void
1436output_P10_format (f, abi, context)
1437 vbyte_func f;
1438 int abi;
1439 int context;
1440{
1441 char bytes[3];
1442 bytes[0] = UNW_P10;
1443 bytes[1] = (abi & 0xff);
1444 bytes[2] = (context & 0xff);
1445 (*f) (3, bytes, NULL);
1446}
1447
1448static void
1449output_B1_format (f, rtype, label)
1450 vbyte_func f;
1451 unw_record_type rtype;
1452 unsigned long label;
1453{
1454 char byte;
e0c9811a 1455 int r = 0;
197865e8 1456 if (label > 0x1f)
800eeca4
JW		 1457 {
1458 output_B4_format (f, rtype, label);
1459 return;
1460 }
e0c9811a
JW		 1461 if (rtype == copy_state)
1462 r = 1;
1463 else if (rtype != label_state)
1464 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1465
1466 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1467 (*f) (1, &byte, NULL);
1468}
1469
1470static void
1471output_B2_format (f, ecount, t)
1472 vbyte_func f;
1473 unsigned long ecount;
1474 unsigned long t;
1475{
1476 char bytes[20];
1477 int count = 1;
1478 if (ecount > 0x1f)
1479 {
1480 output_B3_format (f, ecount, t);
1481 return;
1482 }
1483 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1484 count += output_leb128 (bytes + 1, t, 0);
1485 (*f) (count, bytes, NULL);
1486}
1487
1488static void
1489output_B3_format (f, ecount, t)
1490 vbyte_func f;
1491 unsigned long ecount;
1492 unsigned long t;
1493{
1494 char bytes[20];
1495 int count = 1;
1496 if (ecount <= 0x1f)
1497 {
1498 output_B2_format (f, ecount, t);
1499 return;
1500 }
1501 bytes[0] = UNW_B3;
1502 count += output_leb128 (bytes + 1, t, 0);
1503 count += output_leb128 (bytes + count, ecount, 0);
1504 (*f) (count, bytes, NULL);
1505}
1506
1507static void
1508output_B4_format (f, rtype, label)
1509 vbyte_func f;
1510 unw_record_type rtype;
1511 unsigned long label;
1512{
1513 char bytes[20];
e0c9811a 1514 int r = 0;
800eeca4 1515 int count = 1;
197865e8 1516 if (label <= 0x1f)
800eeca4
JW		 1517 {
1518 output_B1_format (f, rtype, label);
1519 return;
1520 }
197865e8 1521
e0c9811a
JW		 1522 if (rtype == copy_state)
1523 r = 1;
1524 else if (rtype != label_state)
1525 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1526
1527 bytes[0] = (UNW_B4 | (r << 3));
1528 count += output_leb128 (bytes + 1, label, 0);
1529 (*f) (count, bytes, NULL);
1530}
1531
1532static char
e0c9811a 1533format_ab_reg (ab, reg)
542d6675
KH		 1534 int ab;
1535 int reg;
800eeca4
JW		 1536{
1537 int ret;
e0c9811a 1538 ab = (ab & 3);
800eeca4 1539 reg = (reg & 0x1f);
e0c9811a 1540 ret = (ab << 5) | reg;
800eeca4
JW		 1541 return ret;
1542}
1543
1544static void
e0c9811a 1545output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW		 1546 vbyte_func f;
1547 unw_record_type rtype;
e0c9811a 1548 int ab, reg;
800eeca4
JW		 1549 unsigned long t;
1550 unsigned long w1;
1551{
1552 char bytes[20];
e0c9811a 1553 int r = 0;
800eeca4
JW		 1554 int count = 2;
1555 bytes[0] = UNW_X1;
197865e8 1556
e0c9811a
JW		 1557 if (rtype == spill_sprel)
1558 r = 1;
1559 else if (rtype != spill_psprel)
1560 as_bad ("Invalid record type for format X1");
1561 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1562 count += output_leb128 (bytes + 2, t, 0);
1563 count += output_leb128 (bytes + count, w1, 0);
1564 (*f) (count, bytes, NULL);
1565}
1566
1567static void
e0c9811a 1568output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1569 vbyte_func f;
e0c9811a 1570 int ab, reg;
800eeca4
JW		 1571 int x, y, treg;
1572 unsigned long t;
1573{
1574 char bytes[20];
800eeca4
JW		 1575 int count = 3;
1576 bytes[0] = UNW_X2;
e0c9811a 1577 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1578 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1579 count += output_leb128 (bytes + 3, t, 0);
1580 (*f) (count, bytes, NULL);
1581}
1582
1583static void
e0c9811a 1584output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW		 1585 vbyte_func f;
1586 unw_record_type rtype;
1587 int qp;
e0c9811a 1588 int ab, reg;
800eeca4
JW		 1589 unsigned long t;
1590 unsigned long w1;
1591{
1592 char bytes[20];
e0c9811a 1593 int r = 0;
800eeca4 1594 int count = 3;
e0c9811a
JW		 1595 bytes[0] = UNW_X3;
1596
1597 if (rtype == spill_sprel_p)
1598 r = 1;
1599 else if (rtype != spill_psprel_p)
1600 as_bad ("Invalid record type for format X3");
800eeca4 1601 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1602 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW		 1603 count += output_leb128 (bytes + 3, t, 0);
1604 count += output_leb128 (bytes + count, w1, 0);
1605 (*f) (count, bytes, NULL);
1606}
1607
1608static void
e0c9811a 1609output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW		 1610 vbyte_func f;
1611 int qp;
e0c9811a 1612 int ab, reg;
800eeca4
JW		 1613 int x, y, treg;
1614 unsigned long t;
1615{
1616 char bytes[20];
800eeca4 1617 int count = 4;
e0c9811a 1618 bytes[0] = UNW_X4;
800eeca4 1619 bytes[1] = (qp & 0x3f);
e0c9811a 1620 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1621 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1622 count += output_leb128 (bytes + 4, t, 0);
1623 (*f) (count, bytes, NULL);
1624}
1625
1626/* This function allocates a record list structure, and initializes fields. */
542d6675 1627
800eeca4 1628static unw_rec_list *
197865e8 1629alloc_record (unw_record_type t)
800eeca4
JW		 1630{
1631 unw_rec_list *ptr;
1632 ptr = xmalloc (sizeof (*ptr));
1633 ptr->next = NULL;
1634 ptr->slot_number = SLOT_NUM_NOT_SET;
1635 ptr->r.type = t;
1636 return ptr;
1637}
1638
800eeca4 1639/* This function frees an entire list of record structures. */
542d6675 1640
800eeca4
JW		 1641void
1642free_list_records (unw_rec_list *first)
1643{
1644 unw_rec_list *ptr;
542d6675 1645 for (ptr = first; ptr != NULL;)
800eeca4
JW		 1646 {
1647 unw_rec_list *tmp = ptr;
e0c9811a
JW		 1648
1649 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1650 && tmp->r.record.r.mask.i)
1651 free (tmp->r.record.r.mask.i);
1652
800eeca4
JW		 1653 ptr = ptr->next;
1654 free (tmp);
1655 }
1656}
1657
1658static unw_rec_list *
1659output_prologue ()
1660{
1661 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1662 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW		 1663 return ptr;
1664}
1665
1666static unw_rec_list *
1667output_prologue_gr (saved_mask, reg)
1668 unsigned int saved_mask;
1669 unsigned int reg;
1670{
1671 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW		 1672 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1673 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW		 1674 ptr->r.record.r.grsave = reg;
1675 return ptr;
1676}
1677
1678static unw_rec_list *
1679output_body ()
1680{
1681 unw_rec_list *ptr = alloc_record (body);
1682 return ptr;
1683}
1684
1685static unw_rec_list *
1686output_mem_stack_f (size)
1687 unsigned int size;
1688{
1689 unw_rec_list *ptr = alloc_record (mem_stack_f);
1690 ptr->r.record.p.size = size;
1691 return ptr;
1692}
1693
1694static unw_rec_list *
1695output_mem_stack_v ()
1696{
1697 unw_rec_list *ptr = alloc_record (mem_stack_v);
1698 return ptr;
1699}
1700
1701static unw_rec_list *
1702output_psp_gr (gr)
1703 unsigned int gr;
1704{
1705 unw_rec_list *ptr = alloc_record (psp_gr);
1706 ptr->r.record.p.gr = gr;
1707 return ptr;
1708}
1709
1710static unw_rec_list *
1711output_psp_sprel (offset)
1712 unsigned int offset;
1713{
1714 unw_rec_list *ptr = alloc_record (psp_sprel);
542d6675 1715 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1716 return ptr;
1717}
1718
1719static unw_rec_list *
1720output_rp_when ()
1721{
1722 unw_rec_list *ptr = alloc_record (rp_when);
1723 return ptr;
1724}
1725
1726static unw_rec_list *
1727output_rp_gr (gr)
1728 unsigned int gr;
1729{
1730 unw_rec_list *ptr = alloc_record (rp_gr);
1731 ptr->r.record.p.gr = gr;
1732 return ptr;
1733}
1734
1735static unw_rec_list *
1736output_rp_br (br)
1737 unsigned int br;
1738{
1739 unw_rec_list *ptr = alloc_record (rp_br);
1740 ptr->r.record.p.br = br;
1741 return ptr;
1742}
1743
1744static unw_rec_list *
1745output_rp_psprel (offset)
1746 unsigned int offset;
1747{
1748 unw_rec_list *ptr = alloc_record (rp_psprel);
542d6675 1749 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1750 return ptr;
1751}
1752
1753static unw_rec_list *
1754output_rp_sprel (offset)
1755 unsigned int offset;
1756{
1757 unw_rec_list *ptr = alloc_record (rp_sprel);
542d6675 1758 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1759 return ptr;
1760}
1761
1762static unw_rec_list *
1763output_pfs_when ()
1764{
1765 unw_rec_list *ptr = alloc_record (pfs_when);
1766 return ptr;
1767}
1768
1769static unw_rec_list *
1770output_pfs_gr (gr)
1771 unsigned int gr;
1772{
1773 unw_rec_list *ptr = alloc_record (pfs_gr);
1774 ptr->r.record.p.gr = gr;
1775 return ptr;
1776}
1777
1778static unw_rec_list *
1779output_pfs_psprel (offset)
1780 unsigned int offset;
1781{
1782 unw_rec_list *ptr = alloc_record (pfs_psprel);
542d6675 1783 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1784 return ptr;
1785}
1786
1787static unw_rec_list *
1788output_pfs_sprel (offset)
1789 unsigned int offset;
1790{
1791 unw_rec_list *ptr = alloc_record (pfs_sprel);
542d6675 1792 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1793 return ptr;
1794}
1795
1796static unw_rec_list *
1797output_preds_when ()
1798{
1799 unw_rec_list *ptr = alloc_record (preds_when);
1800 return ptr;
1801}
1802
1803static unw_rec_list *
1804output_preds_gr (gr)
1805 unsigned int gr;
1806{
1807 unw_rec_list *ptr = alloc_record (preds_gr);
1808 ptr->r.record.p.gr = gr;
1809 return ptr;
1810}
1811
1812static unw_rec_list *
1813output_preds_psprel (offset)
1814 unsigned int offset;
1815{
1816 unw_rec_list *ptr = alloc_record (preds_psprel);
542d6675 1817 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1818 return ptr;
1819}
1820
1821static unw_rec_list *
1822output_preds_sprel (offset)
1823 unsigned int offset;
1824{
1825 unw_rec_list *ptr = alloc_record (preds_sprel);
542d6675 1826 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1827 return ptr;
1828}
1829
1830static unw_rec_list *
1831output_fr_mem (mask)
1832 unsigned int mask;
1833{
1834 unw_rec_list *ptr = alloc_record (fr_mem);
1835 ptr->r.record.p.rmask = mask;
1836 return ptr;
1837}
1838
1839static unw_rec_list *
1840output_frgr_mem (gr_mask, fr_mask)
1841 unsigned int gr_mask;
1842 unsigned int fr_mask;
1843{
1844 unw_rec_list *ptr = alloc_record (frgr_mem);
1845 ptr->r.record.p.grmask = gr_mask;
1846 ptr->r.record.p.frmask = fr_mask;
1847 return ptr;
1848}
1849
1850static unw_rec_list *
1851output_gr_gr (mask, reg)
1852 unsigned int mask;
1853 unsigned int reg;
1854{
1855 unw_rec_list *ptr = alloc_record (gr_gr);
1856 ptr->r.record.p.grmask = mask;
1857 ptr->r.record.p.gr = reg;
1858 return ptr;
1859}
1860
1861static unw_rec_list *
1862output_gr_mem (mask)
1863 unsigned int mask;
1864{
1865 unw_rec_list *ptr = alloc_record (gr_mem);
1866 ptr->r.record.p.rmask = mask;
1867 return ptr;
1868}
1869
1870static unw_rec_list *
1871output_br_mem (unsigned int mask)
1872{
1873 unw_rec_list *ptr = alloc_record (br_mem);
1874 ptr->r.record.p.brmask = mask;
1875 return ptr;
1876}
1877
1878static unw_rec_list *
1879output_br_gr (save_mask, reg)
1880 unsigned int save_mask;
1881 unsigned int reg;
1882{
1883 unw_rec_list *ptr = alloc_record (br_gr);
1884 ptr->r.record.p.brmask = save_mask;
1885 ptr->r.record.p.gr = reg;
1886 return ptr;
1887}
1888
1889static unw_rec_list *
1890output_spill_base (offset)
1891 unsigned int offset;
1892{
1893 unw_rec_list *ptr = alloc_record (spill_base);
542d6675 1894 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1895 return ptr;
1896}
1897
1898static unw_rec_list *
1899output_unat_when ()
1900{
1901 unw_rec_list *ptr = alloc_record (unat_when);
1902 return ptr;
1903}
1904
1905static unw_rec_list *
1906output_unat_gr (gr)
1907 unsigned int gr;
1908{
1909 unw_rec_list *ptr = alloc_record (unat_gr);
1910 ptr->r.record.p.gr = gr;
1911 return ptr;
1912}
1913
1914static unw_rec_list *
1915output_unat_psprel (offset)
1916 unsigned int offset;
1917{
1918 unw_rec_list *ptr = alloc_record (unat_psprel);
542d6675 1919 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1920 return ptr;
1921}
1922
1923static unw_rec_list *
1924output_unat_sprel (offset)
1925 unsigned int offset;
1926{
1927 unw_rec_list *ptr = alloc_record (unat_sprel);
542d6675 1928 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1929 return ptr;
1930}
1931
1932static unw_rec_list *
1933output_lc_when ()
1934{
1935 unw_rec_list *ptr = alloc_record (lc_when);
1936 return ptr;
1937}
1938
1939static unw_rec_list *
1940output_lc_gr (gr)
1941 unsigned int gr;
1942{
1943 unw_rec_list *ptr = alloc_record (lc_gr);
1944 ptr->r.record.p.gr = gr;
1945 return ptr;
1946}
1947
1948static unw_rec_list *
1949output_lc_psprel (offset)
1950 unsigned int offset;
1951{
1952 unw_rec_list *ptr = alloc_record (lc_psprel);
542d6675 1953 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1954 return ptr;
1955}
1956
1957static unw_rec_list *
1958output_lc_sprel (offset)
1959 unsigned int offset;
1960{
1961 unw_rec_list *ptr = alloc_record (lc_sprel);
542d6675 1962 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1963 return ptr;
1964}
1965
1966static unw_rec_list *
1967output_fpsr_when ()
1968{
1969 unw_rec_list *ptr = alloc_record (fpsr_when);
1970 return ptr;
1971}
1972
1973static unw_rec_list *
1974output_fpsr_gr (gr)
1975 unsigned int gr;
1976{
1977 unw_rec_list *ptr = alloc_record (fpsr_gr);
1978 ptr->r.record.p.gr = gr;
1979 return ptr;
1980}
1981
1982static unw_rec_list *
1983output_fpsr_psprel (offset)
1984 unsigned int offset;
1985{
1986 unw_rec_list *ptr = alloc_record (fpsr_psprel);
542d6675 1987 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1988 return ptr;
1989}
1990
1991static unw_rec_list *
1992output_fpsr_sprel (offset)
1993 unsigned int offset;
1994{
1995 unw_rec_list *ptr = alloc_record (fpsr_sprel);
542d6675 1996 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1997 return ptr;
1998}
1999
2000static unw_rec_list *
2001output_priunat_when_gr ()
2002{
2003 unw_rec_list *ptr = alloc_record (priunat_when_gr);
2004 return ptr;
2005}
2006
2007static unw_rec_list *
2008output_priunat_when_mem ()
2009{
2010 unw_rec_list *ptr = alloc_record (priunat_when_mem);
2011 return ptr;
2012}
2013
2014static unw_rec_list *
2015output_priunat_gr (gr)
2016 unsigned int gr;
2017{
2018 unw_rec_list *ptr = alloc_record (priunat_gr);
2019 ptr->r.record.p.gr = gr;
2020 return ptr;
2021}
2022
2023static unw_rec_list *
2024output_priunat_psprel (offset)
2025 unsigned int offset;
2026{
2027 unw_rec_list *ptr = alloc_record (priunat_psprel);
542d6675 2028 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2029 return ptr;
2030}
2031
2032static unw_rec_list *
2033output_priunat_sprel (offset)
2034 unsigned int offset;
2035{
2036 unw_rec_list *ptr = alloc_record (priunat_sprel);
542d6675 2037 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2038 return ptr;
2039}
2040
2041static unw_rec_list *
2042output_bsp_when ()
2043{
2044 unw_rec_list *ptr = alloc_record (bsp_when);
2045 return ptr;
2046}
2047
2048static unw_rec_list *
2049output_bsp_gr (gr)
2050 unsigned int gr;
2051{
2052 unw_rec_list *ptr = alloc_record (bsp_gr);
2053 ptr->r.record.p.gr = gr;
2054 return ptr;
2055}
2056
2057static unw_rec_list *
2058output_bsp_psprel (offset)
2059 unsigned int offset;
2060{
2061 unw_rec_list *ptr = alloc_record (bsp_psprel);
542d6675 2062 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2063 return ptr;
2064}
2065
2066static unw_rec_list *
2067output_bsp_sprel (offset)
2068 unsigned int offset;
2069{
2070 unw_rec_list *ptr = alloc_record (bsp_sprel);
542d6675 2071 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2072 return ptr;
2073}
2074
2075static unw_rec_list *
2076output_bspstore_when ()
2077{
2078 unw_rec_list *ptr = alloc_record (bspstore_when);
2079 return ptr;
2080}
2081
2082static unw_rec_list *
2083output_bspstore_gr (gr)
2084 unsigned int gr;
2085{
2086 unw_rec_list *ptr = alloc_record (bspstore_gr);
2087 ptr->r.record.p.gr = gr;
2088 return ptr;
2089}
2090
2091static unw_rec_list *
2092output_bspstore_psprel (offset)
2093 unsigned int offset;
2094{
2095 unw_rec_list *ptr = alloc_record (bspstore_psprel);
542d6675 2096 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2097 return ptr;
2098}
2099
2100static unw_rec_list *
2101output_bspstore_sprel (offset)
2102 unsigned int offset;
2103{
2104 unw_rec_list *ptr = alloc_record (bspstore_sprel);
542d6675 2105 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2106 return ptr;
2107}
2108
2109static unw_rec_list *
2110output_rnat_when ()
2111{
2112 unw_rec_list *ptr = alloc_record (rnat_when);
2113 return ptr;
2114}
2115
2116static unw_rec_list *
2117output_rnat_gr (gr)
2118 unsigned int gr;
2119{
2120 unw_rec_list *ptr = alloc_record (rnat_gr);
2121 ptr->r.record.p.gr = gr;
2122 return ptr;
2123}
2124
2125static unw_rec_list *
2126output_rnat_psprel (offset)
2127 unsigned int offset;
2128{
2129 unw_rec_list *ptr = alloc_record (rnat_psprel);
542d6675 2130 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2131 return ptr;
2132}
2133
2134static unw_rec_list *
2135output_rnat_sprel (offset)
2136 unsigned int offset;
2137{
2138 unw_rec_list *ptr = alloc_record (rnat_sprel);
542d6675 2139 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2140 return ptr;
2141}
2142
2143static unw_rec_list *
e0c9811a
JW		 2144output_unwabi (abi, context)
2145 unsigned long abi;
2146 unsigned long context;
800eeca4 2147{
e0c9811a
JW		 2148 unw_rec_list *ptr = alloc_record (unwabi);
2149 ptr->r.record.p.abi = abi;
2150 ptr->r.record.p.context = context;
800eeca4
JW		 2151 return ptr;
2152}
2153
2154static unw_rec_list *
e0c9811a 2155output_epilogue (unsigned long ecount)
800eeca4 2156{
e0c9811a
JW		 2157 unw_rec_list *ptr = alloc_record (epilogue);
2158 ptr->r.record.b.ecount = ecount;
800eeca4
JW		 2159 return ptr;
2160}
2161
2162static unw_rec_list *
e0c9811a 2163output_label_state (unsigned long label)
800eeca4 2164{
e0c9811a
JW		 2165 unw_rec_list *ptr = alloc_record (label_state);
2166 ptr->r.record.b.label = label;
800eeca4
JW		 2167 return ptr;
2168}
2169
2170static unw_rec_list *
e0c9811a
JW		 2171output_copy_state (unsigned long label)
2172{
2173 unw_rec_list *ptr = alloc_record (copy_state);
2174 ptr->r.record.b.label = label;
2175 return ptr;
2176}
2177
2178static unw_rec_list *
2179output_spill_psprel (ab, reg, offset)
2180 unsigned int ab;
800eeca4
JW		 2181 unsigned int reg;
2182 unsigned int offset;
2183{
2184 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 2185 ptr->r.record.x.ab = ab;
800eeca4 2186 ptr->r.record.x.reg = reg;
542d6675 2187 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2188 return ptr;
2189}
2190
2191static unw_rec_list *
e0c9811a
JW		 2192output_spill_sprel (ab, reg, offset)
2193 unsigned int ab;
800eeca4
JW		 2194 unsigned int reg;
2195 unsigned int offset;
2196{
2197 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 2198 ptr->r.record.x.ab = ab;
800eeca4 2199 ptr->r.record.x.reg = reg;
542d6675 2200 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2201 return ptr;
2202}
2203
2204static unw_rec_list *
e0c9811a
JW		 2205output_spill_psprel_p (ab, reg, offset, predicate)
2206 unsigned int ab;
800eeca4
JW		 2207 unsigned int reg;
2208 unsigned int offset;
2209 unsigned int predicate;
2210{
2211 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 2212 ptr->r.record.x.ab = ab;
800eeca4 2213 ptr->r.record.x.reg = reg;
542d6675 2214 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2215 ptr->r.record.x.qp = predicate;
2216 return ptr;
2217}
2218
2219static unw_rec_list *
e0c9811a
JW		 2220output_spill_sprel_p (ab, reg, offset, predicate)
2221 unsigned int ab;
800eeca4
JW		 2222 unsigned int reg;
2223 unsigned int offset;
2224 unsigned int predicate;
2225{
2226 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 2227 ptr->r.record.x.ab = ab;
800eeca4 2228 ptr->r.record.x.reg = reg;
542d6675 2229 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2230 ptr->r.record.x.qp = predicate;
2231 return ptr;
2232}
2233
2234static unw_rec_list *
e0c9811a
JW		 2235output_spill_reg (ab, reg, targ_reg, xy)
2236 unsigned int ab;
800eeca4
JW		 2237 unsigned int reg;
2238 unsigned int targ_reg;
2239 unsigned int xy;
2240{
2241 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 2242 ptr->r.record.x.ab = ab;
800eeca4
JW		 2243 ptr->r.record.x.reg = reg;
2244 ptr->r.record.x.treg = targ_reg;
2245 ptr->r.record.x.xy = xy;
2246 return ptr;
2247}
2248
2249static unw_rec_list *
e0c9811a
JW		 2250output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2251 unsigned int ab;
800eeca4
JW		 2252 unsigned int reg;
2253 unsigned int targ_reg;
2254 unsigned int xy;
2255 unsigned int predicate;
2256{
2257 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 2258 ptr->r.record.x.ab = ab;
800eeca4
JW		 2259 ptr->r.record.x.reg = reg;
2260 ptr->r.record.x.treg = targ_reg;
2261 ptr->r.record.x.xy = xy;
2262 ptr->r.record.x.qp = predicate;
2263 return ptr;
2264}
2265
197865e8 2266/* Given a unw_rec_list process the correct format with the
800eeca4 2267 specified function. */
542d6675 2268
800eeca4
JW		 2269static void
2270process_one_record (ptr, f)
2271 unw_rec_list *ptr;
2272 vbyte_func f;
2273{
e0c9811a
JW		 2274 unsigned long fr_mask, gr_mask;
2275
197865e8 2276 switch (ptr->r.type)
800eeca4 2277 {
542d6675
KH		 2278 case gr_mem:
2279 case fr_mem:
2280 case br_mem:
2281 case frgr_mem:
2282 /* These are taken care of by prologue/prologue_gr. */
2283 break;
e0c9811a 2284
542d6675
KH		 2285 case prologue_gr:
2286 case prologue:
2287 if (ptr->r.type == prologue_gr)
2288 output_R2_format (f, ptr->r.record.r.grmask,
2289 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2290 else
800eeca4 2291 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
542d6675
KH		 2292
2293 /* Output descriptor(s) for union of register spills (if any). */
2294 gr_mask = ptr->r.record.r.mask.gr_mem;
2295 fr_mask = ptr->r.record.r.mask.fr_mem;
2296 if (fr_mask)
2297 {
2298 if ((fr_mask & ~0xfUL) == 0)
2299 output_P6_format (f, fr_mem, fr_mask);
2300 else
2301 {
2302 output_P5_format (f, gr_mask, fr_mask);
2303 gr_mask = 0;
2304 }
2305 }
2306 if (gr_mask)
2307 output_P6_format (f, gr_mem, gr_mask);
2308 if (ptr->r.record.r.mask.br_mem)
2309 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2310
2311 /* output imask descriptor if necessary: */
2312 if (ptr->r.record.r.mask.i)
2313 output_P4_format (f, ptr->r.record.r.mask.i,
2314 ptr->r.record.r.imask_size);
2315 break;
2316
2317 case body:
2318 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2319 break;
2320 case mem_stack_f:
2321 case mem_stack_v:
2322 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2323 ptr->r.record.p.size);
2324 break;
2325 case psp_gr:
2326 case rp_gr:
2327 case pfs_gr:
2328 case preds_gr:
2329 case unat_gr:
2330 case lc_gr:
2331 case fpsr_gr:
2332 case priunat_gr:
2333 case bsp_gr:
2334 case bspstore_gr:
2335 case rnat_gr:
2336 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2337 break;
2338 case rp_br:
2339 output_P3_format (f, rp_br, ptr->r.record.p.br);
2340 break;
2341 case psp_sprel:
2342 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2343 break;
2344 case rp_when:
2345 case pfs_when:
2346 case preds_when:
2347 case unat_when:
2348 case lc_when:
2349 case fpsr_when:
2350 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2351 break;
2352 case rp_psprel:
2353 case pfs_psprel:
2354 case preds_psprel:
2355 case unat_psprel:
2356 case lc_psprel:
2357 case fpsr_psprel:
2358 case spill_base:
2359 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2360 break;
2361 case rp_sprel:
2362 case pfs_sprel:
2363 case preds_sprel:
2364 case unat_sprel:
2365 case lc_sprel:
2366 case fpsr_sprel:
2367 case priunat_sprel:
2368 case bsp_sprel:
2369 case bspstore_sprel:
2370 case rnat_sprel:
2371 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2372 break;
2373 case gr_gr:
2374 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2375 break;
2376 case br_gr:
2377 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2378 break;
2379 case spill_mask:
2380 as_bad ("spill_mask record unimplemented.");
2381 break;
2382 case priunat_when_gr:
2383 case priunat_when_mem:
2384 case bsp_when:
2385 case bspstore_when:
2386 case rnat_when:
2387 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2388 break;
2389 case priunat_psprel:
2390 case bsp_psprel:
2391 case bspstore_psprel:
2392 case rnat_psprel:
2393 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2394 break;
2395 case unwabi:
2396 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2397 break;
2398 case epilogue:
2399 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2400 break;
2401 case label_state:
2402 case copy_state:
2403 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2404 break;
2405 case spill_psprel:
2406 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2407 ptr->r.record.x.reg, ptr->r.record.x.t,
2408 ptr->r.record.x.pspoff);
2409 break;
2410 case spill_sprel:
2411 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2412 ptr->r.record.x.reg, ptr->r.record.x.t,
2413 ptr->r.record.x.spoff);
2414 break;
2415 case spill_reg:
2416 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2417 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2418 ptr->r.record.x.treg, ptr->r.record.x.t);
2419 break;
2420 case spill_psprel_p:
2421 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2422 ptr->r.record.x.ab, ptr->r.record.x.reg,
2423 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2424 break;
2425 case spill_sprel_p:
2426 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2427 ptr->r.record.x.ab, ptr->r.record.x.reg,
2428 ptr->r.record.x.t, ptr->r.record.x.spoff);
2429 break;
2430 case spill_reg_p:
2431 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2432 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2433 ptr->r.record.x.xy, ptr->r.record.x.treg,
2434 ptr->r.record.x.t);
2435 break;
2436 default:
2437 as_bad ("record_type_not_valid");
2438 break;
800eeca4
JW		 2439 }
2440}
2441
197865e8 2442/* Given a unw_rec_list list, process all the records with
800eeca4
JW		 2443 the specified function. */
2444static void
2445process_unw_records (list, f)
2446 unw_rec_list *list;
2447 vbyte_func f;
2448{
2449 unw_rec_list *ptr;
2450 for (ptr = list; ptr; ptr = ptr->next)
2451 process_one_record (ptr, f);
2452}
2453
2454/* Determine the size of a record list in bytes. */
2455static int
2456calc_record_size (list)
2457 unw_rec_list *list;
2458{
2459 vbyte_count = 0;
2460 process_unw_records (list, count_output);
2461 return vbyte_count;
2462}
2463
e0c9811a
JW		 2464/* Update IMASK bitmask to reflect the fact that one or more registers
2465 of type TYPE are saved starting at instruction with index T. If N
2466 bits are set in REGMASK, it is assumed that instructions T through
2467 T+N-1 save these registers.
2468
2469 TYPE values:
2470 0: no save
2471 1: instruction saves next fp reg
2472 2: instruction saves next general reg
2473 3: instruction saves next branch reg */
2474static void
2475set_imask (region, regmask, t, type)
2476 unw_rec_list *region;
2477 unsigned long regmask;
2478 unsigned long t;
2479 unsigned int type;
2480{
2481 unsigned char *imask;
2482 unsigned long imask_size;
2483 unsigned int i;
2484 int pos;
2485
2486 imask = region->r.record.r.mask.i;
2487 imask_size = region->r.record.r.imask_size;
2488 if (!imask)
2489 {
542d6675 2490 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
e0c9811a
JW		 2491 imask = xmalloc (imask_size);
2492 memset (imask, 0, imask_size);
2493
2494 region->r.record.r.imask_size = imask_size;
2495 region->r.record.r.mask.i = imask;
2496 }
2497
542d6675
KH		 2498 i = (t / 4) + 1;
2499 pos = 2 * (3 - t % 4);
e0c9811a
JW		 2500 while (regmask)
2501 {
2502 if (i >= imask_size)
2503 {
2504 as_bad ("Ignoring attempt to spill beyond end of region");
2505 return;
2506 }
2507
2508 imask[i] |= (type & 0x3) << pos;
197865e8 2509
e0c9811a
JW		 2510 regmask &= (regmask - 1);
2511 pos -= 2;
2512 if (pos < 0)
2513 {
2514 pos = 0;
2515 ++i;
2516 }
2517 }
2518}
2519
2520static int
2521count_bits (unsigned long mask)
2522{
2523 int n = 0;
2524
2525 while (mask)
2526 {
2527 mask &= mask - 1;
2528 ++n;
2529 }
2530 return n;
2531}
2532
f5a30c2e
JW		 2533/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2534 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2535 containing FIRST_ADDR. */
2536
e0c9811a 2537unsigned long
f5a30c2e
JW		 2538slot_index (slot_addr, slot_frag, first_addr, first_frag)
2539 unsigned long slot_addr;
2540 fragS *slot_frag;
2541 unsigned long first_addr;
2542 fragS *first_frag;
e0c9811a 2543{
f5a30c2e
JW		 2544 unsigned long index = 0;
2545
2546 /* First time we are called, the initial address and frag are invalid. */
2547 if (first_addr == 0)
2548 return 0;
2549
2550 /* If the two addresses are in different frags, then we need to add in
2551 the remaining size of this frag, and then the entire size of intermediate
2552 frags. */
2553 while (slot_frag != first_frag)
2554 {
2555 unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
2556
2557 /* Add in the full size of the frag converted to instruction slots. */
2558 index += 3 * (first_frag->fr_fix >> 4);
2559 /* Subtract away the initial part before first_addr. */
2560 index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
2561 + ((first_addr & 0x3) - (start_addr & 0x3)));
e0c9811a 2562
f5a30c2e
JW		 2563 /* Move to the beginning of the next frag. */
2564 first_frag = first_frag->fr_next;
2565 first_addr = (unsigned long) &first_frag->fr_literal;
2566 }
2567
2568 /* Add in the used part of the last frag. */
2569 index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
2570 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2571 return index;
2572}
4a1805b1 2573
91a2ae2a
RH		 2574/* Optimize unwind record directives. */
2575
2576static unw_rec_list *
2577optimize_unw_records (list)
2578 unw_rec_list *list;
2579{
2580 if (!list)
2581 return NULL;
2582
2583 /* If the only unwind record is ".prologue" or ".prologue" followed
2584 by ".body", then we can optimize the unwind directives away. */
2585 if (list->r.type == prologue
2586 && (list->next == NULL
2587 || (list->next->r.type == body && list->next->next == NULL)))
2588 return NULL;
2589
2590 return list;
2591}
2592
800eeca4
JW		 2593/* Given a complete record list, process any records which have
2594 unresolved fields, (ie length counts for a prologue). After
197865e8 2595 this has been run, all neccessary information should be available
800eeca4 2596 within each record to generate an image. */
542d6675 2597
800eeca4
JW		 2598static void
2599fixup_unw_records (list)
2600 unw_rec_list *list;
2601{
e0c9811a
JW		 2602 unw_rec_list *ptr, *region = 0;
2603 unsigned long first_addr = 0, rlen = 0, t;
f5a30c2e 2604 fragS *first_frag = 0;
e0c9811a 2605
800eeca4
JW		 2606 for (ptr = list; ptr; ptr = ptr->next)
2607 {
2608 if (ptr->slot_number == SLOT_NUM_NOT_SET)
542d6675 2609 as_bad (" Insn slot not set in unwind record.");
f5a30c2e
JW		 2610 t = slot_index (ptr->slot_number, ptr->slot_frag,
2611 first_addr, first_frag);
800eeca4
JW		 2612 switch (ptr->r.type)
2613 {
542d6675
KH		 2614 case prologue:
2615 case prologue_gr:
2616 case body:
2617 {
2618 unw_rec_list *last;
2619 int size, dir_len = 0;
2620 unsigned long last_addr;
f5a30c2e 2621 fragS *last_frag;
542d6675
KH		 2622
2623 first_addr = ptr->slot_number;
f5a30c2e 2624 first_frag = ptr->slot_frag;
542d6675
KH		 2625 ptr->slot_number = 0;
2626 /* Find either the next body/prologue start, or the end of
2627 the list, and determine the size of the region. */
2628 last_addr = unwind.next_slot_number;
f5a30c2e 2629 last_frag = unwind.next_slot_frag;
542d6675
KH		 2630 for (last = ptr->next; last != NULL; last = last->next)
2631 if (last->r.type == prologue || last->r.type == prologue_gr
2632 || last->r.type == body)
2633 {
2634 last_addr = last->slot_number;
f5a30c2e 2635 last_frag = last->slot_frag;
542d6675
KH		 2636 break;
2637 }
2638 else if (!last->next)
2639 {
2640 /* In the absence of an explicit .body directive,
2641 the prologue ends after the last instruction
2642 covered by an unwind directive. */
2643 if (ptr->r.type != body)
2644 {
2645 last_addr = last->slot_number;
f5a30c2e 2646 last_frag = last->slot_frag;
542d6675
KH		 2647 switch (last->r.type)
2648 {
2649 case frgr_mem:
2650 dir_len = (count_bits (last->r.record.p.frmask)
2651 + count_bits (last->r.record.p.grmask));
2652 break;
2653 case fr_mem:
2654 case gr_mem:
2655 dir_len += count_bits (last->r.record.p.rmask);
2656 break;
2657 case br_mem:
2658 case br_gr:
2659 dir_len += count_bits (last->r.record.p.brmask);
2660 break;
2661 case gr_gr:
2662 dir_len += count_bits (last->r.record.p.grmask);
2663 break;
2664 default:
2665 dir_len = 1;
2666 break;
2667 }
2668 }
2669 break;
2670 }
f5a30c2e
JW		 2671 size = (slot_index (last_addr, last_frag, first_addr, first_frag)
2672 + dir_len);
542d6675
KH		 2673 rlen = ptr->r.record.r.rlen = size;
2674 region = ptr;
e0c9811a 2675 break;
542d6675
KH		 2676 }
2677 case epilogue:
2678 ptr->r.record.b.t = rlen - 1 - t;
2679 break;
e0c9811a 2680
542d6675
KH		 2681 case mem_stack_f:
2682 case mem_stack_v:
2683 case rp_when:
2684 case pfs_when:
2685 case preds_when:
2686 case unat_when:
2687 case lc_when:
2688 case fpsr_when:
2689 case priunat_when_gr:
2690 case priunat_when_mem:
2691 case bsp_when:
2692 case bspstore_when:
2693 case rnat_when:
2694 ptr->r.record.p.t = t;
2695 break;
e0c9811a 2696
542d6675
KH		 2697 case spill_reg:
2698 case spill_sprel:
2699 case spill_psprel:
2700 case spill_reg_p:
2701 case spill_sprel_p:
2702 case spill_psprel_p:
2703 ptr->r.record.x.t = t;
2704 break;
e0c9811a 2705
542d6675
KH		 2706 case frgr_mem:
2707 if (!region)
2708 {
2709 as_bad ("frgr_mem record before region record!\n");
2710 return;
2711 }
2712 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2713 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2714 set_imask (region, ptr->r.record.p.frmask, t, 1);
2715 set_imask (region, ptr->r.record.p.grmask, t, 2);
2716 break;
2717 case fr_mem:
2718 if (!region)
2719 {
2720 as_bad ("fr_mem record before region record!\n");
2721 return;
2722 }
2723 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2724 set_imask (region, ptr->r.record.p.rmask, t, 1);
2725 break;
2726 case gr_mem:
2727 if (!region)
2728 {
2729 as_bad ("gr_mem record before region record!\n");
2730 return;
2731 }
2732 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2733 set_imask (region, ptr->r.record.p.rmask, t, 2);
2734 break;
2735 case br_mem:
2736 if (!region)
2737 {
2738 as_bad ("br_mem record before region record!\n");
2739 return;
2740 }
2741 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2742 set_imask (region, ptr->r.record.p.brmask, t, 3);
2743 break;
e0c9811a 2744
542d6675
KH		 2745 case gr_gr:
2746 if (!region)
2747 {
2748 as_bad ("gr_gr record before region record!\n");
2749 return;
2750 }
2751 set_imask (region, ptr->r.record.p.grmask, t, 2);
2752 break;
2753 case br_gr:
2754 if (!region)
2755 {
2756 as_bad ("br_gr record before region record!\n");
2757 return;
2758 }
2759 set_imask (region, ptr->r.record.p.brmask, t, 3);
2760 break;
e0c9811a 2761
542d6675
KH		 2762 default:
2763 break;
800eeca4
JW		 2764 }
2765 }
2766}
2767
557debba
JW		 2768/* Helper routine for output_unw_records. Emits the header for the unwind
2769 info. */
2770
2771static int
2772setup_unwind_header(int size, unsigned char **mem)
2773{
2774 int x, extra = 0;
2775
2776 /* pad to pointer-size boundry. */
2777 x = size % md.pointer_size;
2778 if (x != 0)
2779 extra = md.pointer_size - x;
2780
2781 /* Add 8 for the header + a pointer for the
2782 personality offset. */
2783 *mem = xmalloc (size + extra + 8 + md.pointer_size);
2784
2785 /* Clear the padding area and personality. */
2786 memset (*mem + 8 + size, 0 , extra + md.pointer_size);
2787 /* Initialize the header area. */
2788
2789 md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* version */
2790 | (unwind.personality_routine
2791 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2792 : 0)
2793 | ((size + extra) / md.pointer_size)), /* length */
2794 8);
2795
2796 return extra;
2797}
2798
800eeca4
JW		 2799/* Generate an unwind image from a record list. Returns the number of
2800 bytes in the resulting image. The memory image itselof is returned
2801 in the 'ptr' parameter. */
2802static int
2803output_unw_records (list, ptr)
2804 unw_rec_list *list;
2805 void **ptr;
2806{
557debba 2807 int size, extra;
800eeca4
JW		 2808 unsigned char *mem;
2809
91a2ae2a
RH		 2810 *ptr = NULL;
2811
2812 list = optimize_unw_records (list);
800eeca4
JW		 2813 fixup_unw_records (list);
2814 size = calc_record_size (list);
2815
91a2ae2a
RH		 2816 if (size > 0 || unwind.force_unwind_entry)
2817 {
2818 unwind.force_unwind_entry = 0;
557debba 2819 extra = setup_unwind_header(size, &mem);
800eeca4 2820
91a2ae2a 2821 vbyte_mem_ptr = mem + 8;
91a2ae2a
RH		 2822 process_unw_records (list, output_vbyte_mem);
2823
2824 *ptr = mem;
2825
557debba 2826 size += extra + 8 + md.pointer_size;
91a2ae2a
RH		 2827 }
2828 return size;
800eeca4
JW		 2829}
2830
e0c9811a
JW		 2831static int
2832convert_expr_to_ab_reg (e, ab, regp)
2833 expressionS *e;
2834 unsigned int *ab;
2835 unsigned int *regp;
2836{
2837 unsigned int reg;
2838
2839 if (e->X_op != O_register)
2840 return 0;
2841
2842 reg = e->X_add_number;
2434f565 2843 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7))
e0c9811a
JW		 2844 {
2845 *ab = 0;
2846 *regp = reg - REG_GR;
2847 }
2434f565
JW		 2848 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5))
2849 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31)))
e0c9811a
JW		 2850 {
2851 *ab = 1;
2852 *regp = reg - REG_FR;
2853 }
2434f565 2854 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5))
e0c9811a
JW		 2855 {
2856 *ab = 2;
2857 *regp = reg - REG_BR;
2858 }
2859 else
2860 {
2861 *ab = 3;
2862 switch (reg)
2863 {
2864 case REG_PR: *regp = 0; break;
2865 case REG_PSP: *regp = 1; break;
2866 case REG_PRIUNAT: *regp = 2; break;
2867 case REG_BR + 0: *regp = 3; break;
2868 case REG_AR + AR_BSP: *regp = 4; break;
2869 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2870 case REG_AR + AR_RNAT: *regp = 6; break;
2871 case REG_AR + AR_UNAT: *regp = 7; break;
2872 case REG_AR + AR_FPSR: *regp = 8; break;
2873 case REG_AR + AR_PFS: *regp = 9; break;
2874 case REG_AR + AR_LC: *regp = 10; break;
2875
2876 default:
2877 return 0;
2878 }
2879 }
2880 return 1;
197865e8 2881}
e0c9811a
JW		 2882
2883static int
2884convert_expr_to_xy_reg (e, xy, regp)
2885 expressionS *e;
2886 unsigned int *xy;
2887 unsigned int *regp;
2888{
2889 unsigned int reg;
2890
2891 if (e->X_op != O_register)
2892 return 0;
2893
2894 reg = e->X_add_number;
2895
2434f565 2896 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127))
e0c9811a
JW		 2897 {
2898 *xy = 0;
2899 *regp = reg - REG_GR;
2900 }
2434f565 2901 else if (reg >= REG_FR && reg <= (REG_FR + 127))
e0c9811a
JW		 2902 {
2903 *xy = 1;
2904 *regp = reg - REG_FR;
2905 }
2434f565 2906 else if (reg >= REG_BR && reg <= (REG_BR + 7))
e0c9811a
JW		 2907 {
2908 *xy = 2;
2909 *regp = reg - REG_BR;
2910 }
2911 else
2912 return -1;
2913 return 1;
197865e8 2914}
e0c9811a 2915
800eeca4
JW		 2916static void
2917dot_radix (dummy)
2434f565 2918 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 2919{
2920 int radix;
2921
2922 SKIP_WHITESPACE ();
2923 radix = *input_line_pointer++;
2924
2925 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2926 {
2927 as_bad ("Radix `%c' unsupported", *input_line_pointer);
542d6675 2928 ignore_rest_of_line ();
800eeca4
JW		 2929 return;
2930 }
2931}
2932
2933/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2934static void
2935dot_special_section (which)
2936 int which;
2937{
2938 set_section ((char *) special_section_name[which]);
2939}
2940
2941static void
2942add_unwind_entry (ptr)
2943 unw_rec_list *ptr;
2944{
e0c9811a
JW		 2945 if (unwind.tail)
2946 unwind.tail->next = ptr;
800eeca4 2947 else
e0c9811a
JW		 2948 unwind.list = ptr;
2949 unwind.tail = ptr;
800eeca4
JW		 2950
2951 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW		 2952 if (unwind.current_entry == NULL)
2953 unwind.current_entry = ptr;
800eeca4
JW		 2954}
2955
197865e8 2956static void
800eeca4 2957dot_fframe (dummy)
2434f565 2958 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 2959{
2960 expressionS e;
e0c9811a 2961
800eeca4 2962 parse_operand (&e);
197865e8 2963
800eeca4
JW		 2964 if (e.X_op != O_constant)
2965 as_bad ("Operand to .fframe must be a constant");
2966 else
e0c9811a
JW		 2967 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2968}
2969
197865e8 2970static void
e0c9811a 2971dot_vframe (dummy)
2434f565 2972 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 2973{
2974 expressionS e;
2975 unsigned reg;
2976
2977 parse_operand (&e);
2978 reg = e.X_add_number - REG_GR;
2979 if (e.X_op == O_register && reg < 128)
800eeca4 2980 {
e0c9811a 2981 add_unwind_entry (output_mem_stack_v ());
30d25259
RH		 2982 if (! (unwind.prologue_mask & 2))
2983 add_unwind_entry (output_psp_gr (reg));
800eeca4 2984 }
e0c9811a
JW		 2985 else
2986 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW		 2987}
2988
197865e8 2989static void
e0c9811a 2990dot_vframesp (dummy)
2434f565 2991 int dummy ATTRIBUTE_UNUSED;
800eeca4 2992{
e0c9811a
JW		 2993 expressionS e;
2994
2995 parse_operand (&e);
2996 if (e.X_op == O_constant)
2997 {
2998 add_unwind_entry (output_mem_stack_v ());
2999 add_unwind_entry (output_psp_sprel (e.X_add_number));
3000 }
3001 else
3002 as_bad ("First operand to .vframesp must be a general register");
3003}
3004
197865e8 3005static void
e0c9811a 3006dot_vframepsp (dummy)
2434f565 3007 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3008{
3009 expressionS e;
3010
3011 parse_operand (&e);
3012 if (e.X_op == O_constant)
3013 {
3014 add_unwind_entry (output_mem_stack_v ());
3015 add_unwind_entry (output_psp_sprel (e.X_add_number));
3016 }
3017 else
3018 as_bad ("First operand to .vframepsp must be a general register");
800eeca4
JW		 3019}
3020
197865e8 3021static void
800eeca4 3022dot_save (dummy)
2434f565 3023 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3024{
3025 expressionS e1, e2;
3026 int sep;
3027 int reg1, reg2;
3028
3029 sep = parse_operand (&e1);
3030 if (sep != ',')
3031 as_bad ("No second operand to .save");
3032 sep = parse_operand (&e2);
3033
e0c9811a 3034 reg1 = e1.X_add_number;
800eeca4 3035 reg2 = e2.X_add_number - REG_GR;
197865e8 3036
800eeca4 3037 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3038 if (e1.X_op == O_register)
800eeca4 3039 {
542d6675 3040 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
800eeca4
JW		 3041 {
3042 switch (reg1)
3043 {
542d6675
KH		 3044 case REG_AR + AR_BSP:
3045 add_unwind_entry (output_bsp_when ());
3046 add_unwind_entry (output_bsp_gr (reg2));
3047 break;
3048 case REG_AR + AR_BSPSTORE:
3049 add_unwind_entry (output_bspstore_when ());
3050 add_unwind_entry (output_bspstore_gr (reg2));
3051 break;
3052 case REG_AR + AR_RNAT:
3053 add_unwind_entry (output_rnat_when ());
3054 add_unwind_entry (output_rnat_gr (reg2));
3055 break;
3056 case REG_AR + AR_UNAT:
3057 add_unwind_entry (output_unat_when ());
3058 add_unwind_entry (output_unat_gr (reg2));
3059 break;
3060 case REG_AR + AR_FPSR:
3061 add_unwind_entry (output_fpsr_when ());
3062 add_unwind_entry (output_fpsr_gr (reg2));
3063 break;
3064 case REG_AR + AR_PFS:
3065 add_unwind_entry (output_pfs_when ());
3066 if (! (unwind.prologue_mask & 4))
3067 add_unwind_entry (output_pfs_gr (reg2));
3068 break;
3069 case REG_AR + AR_LC:
3070 add_unwind_entry (output_lc_when ());
3071 add_unwind_entry (output_lc_gr (reg2));
3072 break;
3073 case REG_BR:
3074 add_unwind_entry (output_rp_when ());
3075 if (! (unwind.prologue_mask & 8))
3076 add_unwind_entry (output_rp_gr (reg2));
3077 break;
3078 case REG_PR:
3079 add_unwind_entry (output_preds_when ());
3080 if (! (unwind.prologue_mask & 1))
3081 add_unwind_entry (output_preds_gr (reg2));
3082 break;
3083 case REG_PRIUNAT:
3084 add_unwind_entry (output_priunat_when_gr ());
3085 add_unwind_entry (output_priunat_gr (reg2));
3086 break;
3087 default:
3088 as_bad ("First operand not a valid register");
800eeca4
JW		 3089 }
3090 }
3091 else
3092 as_bad (" Second operand not a valid register");
3093 }
3094 else
e0c9811a 3095 as_bad ("First operand not a register");
800eeca4
JW		 3096}
3097
197865e8 3098static void
800eeca4 3099dot_restore (dummy)
2434f565 3100 int dummy ATTRIBUTE_UNUSED;
800eeca4 3101{
e0c9811a 3102 expressionS e1, e2;
33d01f33 3103 unsigned long ecount; /* # of _additional_ regions to pop */
e0c9811a
JW		 3104 int sep;
3105
3106 sep = parse_operand (&e1);
3107 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
3108 {
3109 as_bad ("First operand to .restore must be stack pointer (sp)");
3110 return;
3111 }
3112
3113 if (sep == ',')
3114 {
3115 parse_operand (&e2);
33d01f33 3116 if (e2.X_op != O_constant || e2.X_add_number < 0)
e0c9811a 3117 {
33d01f33 3118 as_bad ("Second operand to .restore must be a constant >= 0");
e0c9811a
JW		 3119 return;
3120 }
33d01f33 3121 ecount = e2.X_add_number;
e0c9811a 3122 }
33d01f33
JW		 3123 else
3124 ecount = unwind.prologue_count - 1;
e0c9811a 3125 add_unwind_entry (output_epilogue (ecount));
33d01f33
JW		 3126
3127 if (ecount < unwind.prologue_count)
3128 unwind.prologue_count -= ecount + 1;
3129 else
3130 unwind.prologue_count = 0;
e0c9811a
JW		 3131}
3132
197865e8 3133static void
e0c9811a 3134dot_restorereg (dummy)
2434f565 3135 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3136{
3137 unsigned int ab, reg;
3138 expressionS e;
3139
3140 parse_operand (&e);
3141
3142 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
3143 {
3144 as_bad ("First operand to .restorereg must be a preserved register");
3145 return;
3146 }
3147 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
3148}
3149
197865e8 3150static void
e0c9811a 3151dot_restorereg_p (dummy)
2434f565 3152 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3153{
3154 unsigned int qp, ab, reg;
3155 expressionS e1, e2;
3156 int sep;
3157
3158 sep = parse_operand (&e1);
3159 if (sep != ',')
3160 {
3161 as_bad ("No second operand to .restorereg.p");
3162 return;
3163 }
3164
3165 parse_operand (&e2);
3166
3167 qp = e1.X_add_number - REG_P;
3168 if (e1.X_op != O_register || qp > 63)
3169 {
3170 as_bad ("First operand to .restorereg.p must be a predicate");
3171 return;
3172 }
3173
3174 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3175 {
3176 as_bad ("Second operand to .restorereg.p must be a preserved register");
3177 return;
3178 }
3179 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW		 3180}
3181
3182static int
91a2ae2a
RH		 3183generate_unwind_image (text_name)
3184 const char *text_name;
800eeca4
JW		 3185{
3186 int size;
3187 unsigned char *unw_rec;
800eeca4 3188
10850f29
JW		 3189 /* Force out pending instructions, to make sure all unwind records have
3190 a valid slot_number field. */
3191 ia64_flush_insns ();
3192
800eeca4 3193 /* Generate the unwind record. */
150f24a2 3194 size = output_unw_records (unwind.list, (void **) &unw_rec);
557debba
JW		 3195 if (size % md.pointer_size != 0)
3196 as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size);
3197
800eeca4
JW		 3198 /* If there are unwind records, switch sections, and output the info. */
3199 if (size != 0)
3200 {
800eeca4 3201 unsigned char *where;
91a2ae2a 3202 char *sec_name;
800eeca4 3203 expressionS exp;
91a2ae2a
RH		 3204
3205 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name);
3206 set_section (sec_name);
3207 bfd_set_section_flags (stdoutput, now_seg,
3208 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
800eeca4 3209
557debba
JW		 3210 /* Make sure the section has 4 byte alignment for ILP32 and
3211 8 byte alignment for LP64. */
3212 frag_align (md.pointer_size_shift, 0, 0);
3213 record_alignment (now_seg, md.pointer_size_shift);
5e7474a7 3214
800eeca4 3215 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 3216 unwind.info = expr_build_dot ();
800eeca4 3217
542d6675 3218 where = (unsigned char *) frag_more (size);
800eeca4
JW		 3219
3220 /* Issue a label for this address, and keep track of it to put it
3221 in the unwind section. */
3222
3223 /* Copy the information from the unwind record into this section. The
3224 data is already in the correct byte order. */
3225 memcpy (where, unw_rec, size);
91a2ae2a 3226
800eeca4 3227 /* Add the personality address to the image. */
e0c9811a 3228 if (unwind.personality_routine != 0)
542d6675 3229 {
800eeca4 3230 exp.X_op = O_symbol;
e0c9811a 3231 exp.X_add_symbol = unwind.personality_routine;
800eeca4
JW		 3232 exp.X_add_number = 0;
3233 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
3234 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
e0c9811a 3235 unwind.personality_routine = 0;
542d6675 3236 }
800eeca4
JW		 3237 }
3238
e0c9811a
JW		 3239 free_list_records (unwind.list);
3240 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW		 3241
3242 return size;
3243}
3244
197865e8 3245static void
542d6675 3246dot_handlerdata (dummy)
2434f565 3247 int dummy ATTRIBUTE_UNUSED;
800eeca4 3248{
91a2ae2a
RH		 3249 const char *text_name = segment_name (now_seg);
3250
3251 /* If text section name starts with ".text" (which it should),
3252 strip this prefix off. */
3253 if (strcmp (text_name, ".text") == 0)
3254 text_name = "";
3255
3256 unwind.force_unwind_entry = 1;
3257
3258 /* Remember which segment we're in so we can switch back after .endp */
3259 unwind.saved_text_seg = now_seg;
3260 unwind.saved_text_subseg = now_subseg;
3261
3262 /* Generate unwind info into unwind-info section and then leave that
3263 section as the currently active one so dataXX directives go into
3264 the language specific data area of the unwind info block. */
3265 generate_unwind_image (text_name);
e0c9811a 3266 demand_empty_rest_of_line ();
800eeca4
JW		 3267}
3268
197865e8 3269static void
800eeca4 3270dot_unwentry (dummy)
2434f565 3271 int dummy ATTRIBUTE_UNUSED;
800eeca4 3272{
91a2ae2a 3273 unwind.force_unwind_entry = 1;
e0c9811a 3274 demand_empty_rest_of_line ();
800eeca4
JW		 3275}
3276
197865e8 3277static void
800eeca4 3278dot_altrp (dummy)
2434f565 3279 int dummy ATTRIBUTE_UNUSED;
800eeca4 3280{
e0c9811a
JW		 3281 expressionS e;
3282 unsigned reg;
3283
3284 parse_operand (&e);
3285 reg = e.X_add_number - REG_BR;
3286 if (e.X_op == O_register && reg < 8)
3287 add_unwind_entry (output_rp_br (reg));
3288 else
3289 as_bad ("First operand not a valid branch register");
800eeca4
JW		 3290}
3291
197865e8 3292static void
e0c9811a
JW		 3293dot_savemem (psprel)
3294 int psprel;
800eeca4
JW		 3295{
3296 expressionS e1, e2;
3297 int sep;
3298 int reg1, val;
3299
3300 sep = parse_operand (&e1);
3301 if (sep != ',')
e0c9811a 3302 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW		 3303 sep = parse_operand (&e2);
3304
e0c9811a 3305 reg1 = e1.X_add_number;
800eeca4 3306 val = e2.X_add_number;
197865e8 3307
800eeca4 3308 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3309 if (e1.X_op == O_register)
800eeca4
JW		 3310 {
3311 if (e2.X_op == O_constant)
3312 {
3313 switch (reg1)
3314 {
542d6675
KH		 3315 case REG_AR + AR_BSP:
3316 add_unwind_entry (output_bsp_when ());
3317 add_unwind_entry ((psprel
3318 ? output_bsp_psprel
3319 : output_bsp_sprel) (val));
3320 break;
3321 case REG_AR + AR_BSPSTORE:
3322 add_unwind_entry (output_bspstore_when ());
3323 add_unwind_entry ((psprel
3324 ? output_bspstore_psprel
3325 : output_bspstore_sprel) (val));
3326 break;
3327 case REG_AR + AR_RNAT:
3328 add_unwind_entry (output_rnat_when ());
3329 add_unwind_entry ((psprel
3330 ? output_rnat_psprel
3331 : output_rnat_sprel) (val));
3332 break;
3333 case REG_AR + AR_UNAT:
3334 add_unwind_entry (output_unat_when ());
3335 add_unwind_entry ((psprel
3336 ? output_unat_psprel
3337 : output_unat_sprel) (val));
3338 break;
3339 case REG_AR + AR_FPSR:
3340 add_unwind_entry (output_fpsr_when ());
3341 add_unwind_entry ((psprel
3342 ? output_fpsr_psprel
3343 : output_fpsr_sprel) (val));
3344 break;
3345 case REG_AR + AR_PFS:
3346 add_unwind_entry (output_pfs_when ());
3347 add_unwind_entry ((psprel
3348 ? output_pfs_psprel
3349 : output_pfs_sprel) (val));
3350 break;
3351 case REG_AR + AR_LC:
3352 add_unwind_entry (output_lc_when ());
3353 add_unwind_entry ((psprel
3354 ? output_lc_psprel
3355 : output_lc_sprel) (val));
3356 break;
3357 case REG_BR:
3358 add_unwind_entry (output_rp_when ());
3359 add_unwind_entry ((psprel
3360 ? output_rp_psprel
3361 : output_rp_sprel) (val));
3362 break;
3363 case REG_PR:
3364 add_unwind_entry (output_preds_when ());
3365 add_unwind_entry ((psprel
3366 ? output_preds_psprel
3367 : output_preds_sprel) (val));
3368 break;
3369 case REG_PRIUNAT:
3370 add_unwind_entry (output_priunat_when_mem ());
3371 add_unwind_entry ((psprel
3372 ? output_priunat_psprel
3373 : output_priunat_sprel) (val));
3374 break;
3375 default:
3376 as_bad ("First operand not a valid register");
800eeca4
JW		 3377 }
3378 }
3379 else
3380 as_bad (" Second operand not a valid constant");
3381 }
3382 else
e0c9811a 3383 as_bad ("First operand not a register");
800eeca4
JW		 3384}
3385
197865e8 3386static void
800eeca4 3387dot_saveg (dummy)
2434f565 3388 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3389{
3390 expressionS e1, e2;
3391 int sep;
3392 sep = parse_operand (&e1);
3393 if (sep == ',')
3394 parse_operand (&e2);
197865e8 3395
800eeca4
JW		 3396 if (e1.X_op != O_constant)
3397 as_bad ("First operand to .save.g must be a constant.");
3398 else
3399 {
3400 int grmask = e1.X_add_number;
3401 if (sep != ',')
3402 add_unwind_entry (output_gr_mem (grmask));
3403 else
542d6675 3404 {
800eeca4 3405 int reg = e2.X_add_number - REG_GR;
542d6675 3406 if (e2.X_op == O_register && reg >= 0 && reg < 128)
800eeca4
JW		 3407 add_unwind_entry (output_gr_gr (grmask, reg));
3408 else
3409 as_bad ("Second operand is an invalid register.");
3410 }
3411 }
3412}
3413
197865e8 3414static void
800eeca4 3415dot_savef (dummy)
2434f565 3416 int dummy ATTRIBUTE_UNUSED;
800eeca4 3417{
e0c9811a 3418 expressionS e1;
800eeca4
JW		 3419 int sep;
3420 sep = parse_operand (&e1);
197865e8 3421
800eeca4
JW		 3422 if (e1.X_op != O_constant)
3423 as_bad ("Operand to .save.f must be a constant.");
3424 else
e0c9811a 3425 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW		 3426}
3427
197865e8 3428static void
800eeca4 3429dot_saveb (dummy)
2434f565 3430 int dummy ATTRIBUTE_UNUSED;
800eeca4 3431{
e0c9811a
JW		 3432 expressionS e1, e2;
3433 unsigned int reg;
3434 unsigned char sep;
3435 int brmask;
3436
800eeca4 3437 sep = parse_operand (&e1);
800eeca4 3438 if (e1.X_op != O_constant)
800eeca4 3439 {
e0c9811a
JW		 3440 as_bad ("First operand to .save.b must be a constant.");
3441 return;
800eeca4 3442 }
e0c9811a
JW		 3443 brmask = e1.X_add_number;
3444
3445 if (sep == ',')
3446 {
3447 sep = parse_operand (&e2);
3448 reg = e2.X_add_number - REG_GR;
3449 if (e2.X_op != O_register || reg > 127)
3450 {
3451 as_bad ("Second operand to .save.b must be a general register.");
3452 return;
3453 }
3454 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3455 }
3456 else
3457 add_unwind_entry (output_br_mem (brmask));
3458
3459 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3460 ignore_rest_of_line ();
800eeca4
JW		 3461}
3462
197865e8 3463static void
800eeca4 3464dot_savegf (dummy)
2434f565 3465 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3466{
3467 expressionS e1, e2;
3468 int sep;
3469 sep = parse_operand (&e1);
3470 if (sep == ',')
3471 parse_operand (&e2);
197865e8 3472
800eeca4
JW		 3473 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3474 as_bad ("Both operands of .save.gf must be constants.");
3475 else
3476 {
3477 int grmask = e1.X_add_number;
3478 int frmask = e2.X_add_number;
3479 add_unwind_entry (output_frgr_mem (grmask, frmask));
3480 }
3481}
3482
197865e8 3483static void
800eeca4 3484dot_spill (dummy)
2434f565 3485 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3486{
3487 expressionS e;
e0c9811a
JW		 3488 unsigned char sep;
3489
3490 sep = parse_operand (&e);
3491 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3492 ignore_rest_of_line ();
197865e8 3493
800eeca4
JW		 3494 if (e.X_op != O_constant)
3495 as_bad ("Operand to .spill must be a constant");
3496 else
e0c9811a
JW		 3497 add_unwind_entry (output_spill_base (e.X_add_number));
3498}
3499
3500static void
3501dot_spillreg (dummy)
2434f565 3502 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3503{
3504 int sep, ab, xy, reg, treg;
3505 expressionS e1, e2;
3506
3507 sep = parse_operand (&e1);
3508 if (sep != ',')
3509 {
3510 as_bad ("No second operand to .spillreg");
3511 return;
3512 }
3513
3514 parse_operand (&e2);
3515
3516 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3517 {
e0c9811a
JW		 3518 as_bad ("First operand to .spillreg must be a preserved register");
3519 return;
800eeca4 3520 }
e0c9811a
JW		 3521
3522 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3523 {
3524 as_bad ("Second operand to .spillreg must be a register");
3525 return;
3526 }
3527
3528 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3529}
3530
3531static void
3532dot_spillmem (psprel)
3533 int psprel;
3534{
3535 expressionS e1, e2;
3536 int sep, ab, reg;
3537
3538 sep = parse_operand (&e1);
3539 if (sep != ',')
3540 {
3541 as_bad ("Second operand missing");
3542 return;
3543 }
3544
3545 parse_operand (&e2);
3546
3547 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3548 {
3549 as_bad ("First operand to .spill%s must be a preserved register",
3550 psprel ? "psp" : "sp");
3551 return;
3552 }
3553
3554 if (e2.X_op != O_constant)
3555 {
3556 as_bad ("Second operand to .spill%s must be a constant",
3557 psprel ? "psp" : "sp");
3558 return;
3559 }
3560
3561 if (psprel)
3562 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3563 else
3564 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3565}
3566
3567static void
3568dot_spillreg_p (dummy)
2434f565 3569 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3570{
3571 int sep, ab, xy, reg, treg;
3572 expressionS e1, e2, e3;
3573 unsigned int qp;
3574
3575 sep = parse_operand (&e1);
3576 if (sep != ',')
3577 {
3578 as_bad ("No second and third operand to .spillreg.p");
3579 return;
3580 }
3581
3582 sep = parse_operand (&e2);
3583 if (sep != ',')
3584 {
3585 as_bad ("No third operand to .spillreg.p");
3586 return;
3587 }
3588
3589 parse_operand (&e3);
3590
3591 qp = e1.X_add_number - REG_P;
3592
3593 if (e1.X_op != O_register || qp > 63)
3594 {
3595 as_bad ("First operand to .spillreg.p must be a predicate");
3596 return;
3597 }
3598
3599 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3600 {
3601 as_bad ("Second operand to .spillreg.p must be a preserved register");
3602 return;
3603 }
3604
3605 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3606 {
3607 as_bad ("Third operand to .spillreg.p must be a register");
3608 return;
3609 }
3610
3611 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3612}
3613
3614static void
3615dot_spillmem_p (psprel)
3616 int psprel;
3617{
3618 expressionS e1, e2, e3;
3619 int sep, ab, reg;
3620 unsigned int qp;
3621
3622 sep = parse_operand (&e1);
3623 if (sep != ',')
3624 {
3625 as_bad ("Second operand missing");
3626 return;
3627 }
3628
3629 parse_operand (&e2);
3630 if (sep != ',')
3631 {
3632 as_bad ("Second operand missing");
3633 return;
3634 }
3635
3636 parse_operand (&e3);
3637
3638 qp = e1.X_add_number - REG_P;
3639 if (e1.X_op != O_register || qp > 63)
3640 {
3641 as_bad ("First operand to .spill%s_p must be a predicate",
3642 psprel ? "psp" : "sp");
3643 return;
3644 }
3645
3646 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3647 {
3648 as_bad ("Second operand to .spill%s_p must be a preserved register",
3649 psprel ? "psp" : "sp");
3650 return;
3651 }
3652
3653 if (e3.X_op != O_constant)
3654 {
3655 as_bad ("Third operand to .spill%s_p must be a constant",
3656 psprel ? "psp" : "sp");
3657 return;
3658 }
3659
3660 if (psprel)
fa7fda74 3661 add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp));
e0c9811a 3662 else
fa7fda74 3663 add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp));
e0c9811a
JW		 3664}
3665
3666static void
3667dot_label_state (dummy)
2434f565 3668 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3669{
3670 expressionS e;
3671
3672 parse_operand (&e);
3673 if (e.X_op != O_constant)
3674 {
3675 as_bad ("Operand to .label_state must be a constant");
3676 return;
3677 }
3678 add_unwind_entry (output_label_state (e.X_add_number));
3679}
3680
3681static void
3682dot_copy_state (dummy)
2434f565 3683 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3684{
3685 expressionS e;
3686
3687 parse_operand (&e);
3688 if (e.X_op != O_constant)
3689 {
3690 as_bad ("Operand to .copy_state must be a constant");
3691 return;
3692 }
3693 add_unwind_entry (output_copy_state (e.X_add_number));
800eeca4
JW		 3694}
3695
197865e8 3696static void
800eeca4 3697dot_unwabi (dummy)
2434f565 3698 int dummy ATTRIBUTE_UNUSED;
800eeca4 3699{
e0c9811a
JW		 3700 expressionS e1, e2;
3701 unsigned char sep;
3702
3703 sep = parse_operand (&e1);
3704 if (sep != ',')
3705 {
3706 as_bad ("Second operand to .unwabi missing");
3707 return;
3708 }
3709 sep = parse_operand (&e2);
3710 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3711 ignore_rest_of_line ();
3712
3713 if (e1.X_op != O_constant)
3714 {
3715 as_bad ("First operand to .unwabi must be a constant");
3716 return;
3717 }
3718
3719 if (e2.X_op != O_constant)
3720 {
3721 as_bad ("Second operand to .unwabi must be a constant");
3722 return;
3723 }
3724
3725 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW		 3726}
3727
197865e8 3728static void
800eeca4 3729dot_personality (dummy)
2434f565 3730 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3731{
3732 char *name, *p, c;
3733 SKIP_WHITESPACE ();
3734 name = input_line_pointer;
3735 c = get_symbol_end ();
3736 p = input_line_pointer;
e0c9811a 3737 unwind.personality_routine = symbol_find_or_make (name);
91a2ae2a 3738 unwind.force_unwind_entry = 1;
800eeca4
JW		 3739 *p = c;
3740 SKIP_WHITESPACE ();
3741 demand_empty_rest_of_line ();
3742}
3743
3744static void
3745dot_proc (dummy)
2434f565 3746 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3747{
3748 char *name, *p, c;
3749 symbolS *sym;
3750
e0c9811a
JW		 3751 unwind.proc_start = expr_build_dot ();
3752 /* Parse names of main and alternate entry points and mark them as
542d6675 3753 function symbols: */
800eeca4
JW		 3754 while (1)
3755 {
3756 SKIP_WHITESPACE ();
3757 name = input_line_pointer;
3758 c = get_symbol_end ();
3759 p = input_line_pointer;
3760 sym = symbol_find_or_make (name);
e0c9811a 3761 if (unwind.proc_start == 0)
542d6675 3762 {
e0c9811a 3763 unwind.proc_start = sym;
800eeca4
JW		 3764 }
3765 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3766 *p = c;
3767 SKIP_WHITESPACE ();
3768 if (*input_line_pointer != ',')
3769 break;
3770 ++input_line_pointer;
3771 }
3772 demand_empty_rest_of_line ();
3773 ia64_do_align (16);
3774
33d01f33 3775 unwind.prologue_count = 0;
e0c9811a
JW		 3776 unwind.list = unwind.tail = unwind.current_entry = NULL;
3777 unwind.personality_routine = 0;
800eeca4
JW		 3778}
3779
3780static void
3781dot_body (dummy)
2434f565 3782 int dummy ATTRIBUTE_UNUSED;
800eeca4 3783{
e0c9811a 3784 unwind.prologue = 0;
30d25259
RH		 3785 unwind.prologue_mask = 0;
3786
800eeca4 3787 add_unwind_entry (output_body ());
e0c9811a 3788 demand_empty_rest_of_line ();
800eeca4
JW		 3789}
3790
3791static void
3792dot_prologue (dummy)
2434f565 3793 int dummy ATTRIBUTE_UNUSED;
800eeca4 3794{
e0c9811a 3795 unsigned char sep;
2434f565 3796 int mask = 0, grsave = 0;
e0c9811a 3797
e0c9811a 3798 if (!is_it_end_of_statement ())
800eeca4
JW		 3799 {
3800 expressionS e1, e2;
800eeca4
JW		 3801 sep = parse_operand (&e1);
3802 if (sep != ',')
3803 as_bad ("No second operand to .prologue");
3804 sep = parse_operand (&e2);
e0c9811a 3805 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
542d6675 3806 ignore_rest_of_line ();
800eeca4
JW		 3807
3808 if (e1.X_op == O_constant)
542d6675 3809 {
30d25259
RH		 3810 mask = e1.X_add_number;
3811
800eeca4 3812 if (e2.X_op == O_constant)
30d25259
RH		 3813 grsave = e2.X_add_number;
3814 else if (e2.X_op == O_register
3815 && (grsave = e2.X_add_number - REG_GR) < 128)
3816 ;
800eeca4 3817 else
30d25259
RH		 3818 as_bad ("Second operand not a constant or general register");
3819
3820 add_unwind_entry (output_prologue_gr (mask, grsave));
800eeca4
JW		 3821 }
3822 else
3823 as_bad ("First operand not a constant");
3824 }
3825 else
3826 add_unwind_entry (output_prologue ());
30d25259
RH		 3827
3828 unwind.prologue = 1;
3829 unwind.prologue_mask = mask;
33d01f33 3830 ++unwind.prologue_count;
800eeca4
JW		 3831}
3832
3833static void
3834dot_endp (dummy)
2434f565 3835 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3836{
3837 expressionS e;
3838 unsigned char *ptr;
44f5c83a 3839 int bytes_per_address;
800eeca4
JW		 3840 long where;
3841 segT saved_seg;
3842 subsegT saved_subseg;
91a2ae2a 3843 const char *sec_name, *text_name;
800eeca4 3844
91a2ae2a
RH		 3845 if (unwind.saved_text_seg)
3846 {
3847 saved_seg = unwind.saved_text_seg;
3848 saved_subseg = unwind.saved_text_subseg;
3849 unwind.saved_text_seg = NULL;
3850 }
3851 else
3852 {
3853 saved_seg = now_seg;
3854 saved_subseg = now_subseg;
3855 }
3856
3857 /*
3858 Use a slightly ugly scheme to derive the unwind section names from
3859 the text section name:
3860
3861 text sect. unwind table sect.
3862 name: name: comments:
3863 ---------- ----------------- --------------------------------
3864 .text .IA_64.unwind
3865 .text.foo .IA_64.unwind.text.foo
3866 .foo .IA_64.unwind.foo
579f31ac
JJ		 3867 .gnu.linkonce.t.foo
3868 .gnu.linkonce.ia64unw.foo
91a2ae2a
RH		 3869 _info .IA_64.unwind_info gas issues error message (ditto)
3870 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3871
3872 This mapping is done so that:
3873
3874 (a) An object file with unwind info only in .text will use
3875 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3876 This follows the letter of the ABI and also ensures backwards
3877 compatibility with older toolchains.
3878
3879 (b) An object file with unwind info in multiple text sections
3880 will use separate unwind sections for each text section.
3881 This allows us to properly set the "sh_info" and "sh_link"
3882 fields in SHT_IA_64_UNWIND as required by the ABI and also
3883 lets GNU ld support programs with multiple segments
3884 containing unwind info (as might be the case for certain
3885 embedded applications).
3886
3887 (c) An error is issued if there would be a name clash.
3888 */
3889 text_name = segment_name (saved_seg);
3890 if (strncmp (text_name, "_info", 5) == 0)
3891 {
3892 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3893 text_name);
3894 ignore_rest_of_line ();
3895 return;
3896 }
3897 if (strcmp (text_name, ".text") == 0)
3898 text_name = "";
800eeca4
JW		 3899
3900 expression (&e);
3901 demand_empty_rest_of_line ();
3902
3903 insn_group_break (1, 0, 0);
800eeca4 3904
91a2ae2a
RH		 3905 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3906 if (!unwind.info)
3907 generate_unwind_image (text_name);
800eeca4 3908
91a2ae2a
RH		 3909 if (unwind.info || unwind.force_unwind_entry)
3910 {
3911 subseg_set (md.last_text_seg, 0);
3912 unwind.proc_end = expr_build_dot ();
5e7474a7 3913
91a2ae2a
RH		 3914 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name);
3915 set_section ((char *) sec_name);
3916 bfd_set_section_flags (stdoutput, now_seg,
3917 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
5e7474a7 3918
557debba
JW		 3919 /* Make sure that section has 4 byte alignment for ILP32 and
3920 8 byte alignment for LP64. */
3921 record_alignment (now_seg, md.pointer_size_shift);
800eeca4 3922
557debba
JW		 3923 /* Need space for 3 pointers for procedure start, procedure end,
3924 and unwind info. */
3925 ptr = frag_more (3 * md.pointer_size);
3926 where = frag_now_fix () - (3 * md.pointer_size);
91a2ae2a 3927 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
800eeca4 3928
91a2ae2a
RH		 3929 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3930 e.X_op = O_pseudo_fixup;
3931 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3932 e.X_add_number = 0;
3933 e.X_add_symbol = unwind.proc_start;
3934 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
800eeca4 3935
800eeca4
JW		 3936 e.X_op = O_pseudo_fixup;
3937 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3938 e.X_add_number = 0;
91a2ae2a
RH		 3939 e.X_add_symbol = unwind.proc_end;
3940 ia64_cons_fix_new (frag_now, where + bytes_per_address,
3941 bytes_per_address, &e);
3942
3943 if (unwind.info)
3944 {
3945 e.X_op = O_pseudo_fixup;
3946 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3947 e.X_add_number = 0;
3948 e.X_add_symbol = unwind.info;
3949 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2),
3950 bytes_per_address, &e);
3951 }
3952 else
3953 md_number_to_chars (ptr + (bytes_per_address * 2), 0,
3954 bytes_per_address);
800eeca4 3955
91a2ae2a 3956 }
800eeca4 3957 subseg_set (saved_seg, saved_subseg);
e0c9811a 3958 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW		 3959}
3960
3961static void
3962dot_template (template)
3963 int template;
3964{
3965 CURR_SLOT.user_template = template;
3966}
3967
3968static void
3969dot_regstk (dummy)
2434f565 3970 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3971{
3972 int ins, locs, outs, rots;
3973
3974 if (is_it_end_of_statement ())
3975 ins = locs = outs = rots = 0;
3976 else
3977 {
3978 ins = get_absolute_expression ();
3979 if (*input_line_pointer++ != ',')
3980 goto err;
3981 locs = get_absolute_expression ();
3982 if (*input_line_pointer++ != ',')
3983 goto err;
3984 outs = get_absolute_expression ();
3985 if (*input_line_pointer++ != ',')
3986 goto err;
3987 rots = get_absolute_expression ();
3988 }
3989 set_regstack (ins, locs, outs, rots);
3990 return;
3991
3992 err:
3993 as_bad ("Comma expected");
3994 ignore_rest_of_line ();
3995}
3996
3997static void
3998dot_rot (type)
3999 int type;
4000{
4001 unsigned num_regs, num_alloced = 0;
4002 struct dynreg **drpp, *dr;
4003 int ch, base_reg = 0;
4004 char *name, *start;
4005 size_t len;
4006
4007 switch (type)
4008 {
4009 case DYNREG_GR: base_reg = REG_GR + 32; break;
4010 case DYNREG_FR: base_reg = REG_FR + 32; break;
4011 case DYNREG_PR: base_reg = REG_P + 16; break;
4012 default: break;
4013 }
4014
542d6675 4015 /* First, remove existing names from hash table. */
800eeca4
JW		 4016 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
4017 {
4018 hash_delete (md.dynreg_hash, dr->name);
4019 dr->num_regs = 0;
4020 }
4021
4022 drpp = &md.dynreg[type];
4023 while (1)
4024 {
4025 start = input_line_pointer;
4026 ch = get_symbol_end ();
4027 *input_line_pointer = ch;
4028 len = (input_line_pointer - start);
4029
4030 SKIP_WHITESPACE ();
4031 if (*input_line_pointer != '[')
4032 {
4033 as_bad ("Expected '['");
4034 goto err;
4035 }
4036 ++input_line_pointer; /* skip '[' */
4037
4038 num_regs = get_absolute_expression ();
4039
4040 if (*input_line_pointer++ != ']')
4041 {
4042 as_bad ("Expected ']'");
4043 goto err;
4044 }
4045 SKIP_WHITESPACE ();
4046
4047 num_alloced += num_regs;
4048 switch (type)
4049 {
4050 case DYNREG_GR:
4051 if (num_alloced > md.rot.num_regs)
4052 {
4053 as_bad ("Used more than the declared %d rotating registers",
4054 md.rot.num_regs);
4055 goto err;
4056 }
4057 break;
4058 case DYNREG_FR:
4059 if (num_alloced > 96)
4060 {
4061 as_bad ("Used more than the available 96 rotating registers");
4062 goto err;
4063 }
4064 break;
4065 case DYNREG_PR:
4066 if (num_alloced > 48)
4067 {
4068 as_bad ("Used more than the available 48 rotating registers");
4069 goto err;
4070 }
4071 break;
4072
4073 default:
4074 break;
4075 }
4076
4077 name = obstack_alloc (&notes, len + 1);
4078 memcpy (name, start, len);
4079 name[len] = '\0';
4080
4081 if (!*drpp)
4082 {
4083 *drpp = obstack_alloc (&notes, sizeof (*dr));
4084 memset (*drpp, 0, sizeof (*dr));
4085 }
4086
4087 dr = *drpp;
4088 dr->name = name;
4089 dr->num_regs = num_regs;
4090 dr->base = base_reg;
4091 drpp = &dr->next;
4092 base_reg += num_regs;
4093
4094 if (hash_insert (md.dynreg_hash, name, dr))
4095 {
4096 as_bad ("Attempt to redefine register set `%s'", name);
4097 goto err;
4098 }
4099
4100 if (*input_line_pointer != ',')
4101 break;
4102 ++input_line_pointer; /* skip comma */
4103 SKIP_WHITESPACE ();
4104 }
4105 demand_empty_rest_of_line ();
4106 return;
4107
4108 err:
4109 ignore_rest_of_line ();
4110}
4111
4112static void
4113dot_byteorder (byteorder)
4114 int byteorder;
4115{
4116 target_big_endian = byteorder;
4117}
4118
4119static void
4120dot_psr (dummy)
2434f565 4121 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4122{
4123 char *option;
4124 int ch;
4125
4126 while (1)
4127 {
4128 option = input_line_pointer;
4129 ch = get_symbol_end ();
4130 if (strcmp (option, "lsb") == 0)
4131 md.flags &= ~EF_IA_64_BE;
4132 else if (strcmp (option, "msb") == 0)
4133 md.flags |= EF_IA_64_BE;
4134 else if (strcmp (option, "abi32") == 0)
4135 md.flags &= ~EF_IA_64_ABI64;
4136 else if (strcmp (option, "abi64") == 0)
4137 md.flags |= EF_IA_64_ABI64;
4138 else
4139 as_bad ("Unknown psr option `%s'", option);
4140 *input_line_pointer = ch;
4141
4142 SKIP_WHITESPACE ();
4143 if (*input_line_pointer != ',')
4144 break;
4145
4146 ++input_line_pointer;
4147 SKIP_WHITESPACE ();
4148 }
4149 demand_empty_rest_of_line ();
4150}
4151
4152static void
4153dot_alias (dummy)
2434f565 4154 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4155{
4156 as_bad (".alias not implemented yet");
4157}
4158
4159static void
4160dot_ln (dummy)
2434f565 4161 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4162{
4163 new_logical_line (0, get_absolute_expression ());
4164 demand_empty_rest_of_line ();
4165}
4166
542d6675 4167static char *
800eeca4
JW		 4168parse_section_name ()
4169{
4170 char *name;
4171 int len;
4172
4173 SKIP_WHITESPACE ();
4174 if (*input_line_pointer != '"')
4175 {
4176 as_bad ("Missing section name");
4177 ignore_rest_of_line ();
4178 return 0;
4179 }
4180 name = demand_copy_C_string (&len);
4181 if (!name)
4182 {
4183 ignore_rest_of_line ();
4184 return 0;
4185 }
4186 SKIP_WHITESPACE ();
4187 if (*input_line_pointer != ',')
4188 {
4189 as_bad ("Comma expected after section name");
4190 ignore_rest_of_line ();
4191 return 0;
4192 }
4193 ++input_line_pointer; /* skip comma */
4194 return name;
4195}
4196
4197static void
4198dot_xdata (size)
4199 int size;
4200{
4201 char *name = parse_section_name ();
4202 if (!name)
4203 return;
4204
4d5a53ff 4205 md.keep_pending_output = 1;
800eeca4
JW		 4206 set_section (name);
4207 cons (size);
4208 obj_elf_previous (0);
4d5a53ff 4209 md.keep_pending_output = 0;
800eeca4
JW		 4210}
4211
4212/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
542d6675 4213
800eeca4
JW		 4214static void
4215stmt_float_cons (kind)
4216 int kind;
4217{
4218 size_t size;
4219
4220 switch (kind)
4221 {
4222 case 'd': size = 8; break;
4223 case 'x': size = 10; break;
4224
4225 case 'f':
4226 default:
4227 size = 4;
4228 break;
4229 }
4230 ia64_do_align (size);
4231 float_cons (kind);
4232}
4233
4234static void
4235stmt_cons_ua (size)
4236 int size;
4237{
4238 int saved_auto_align = md.auto_align;
4239
4240 md.auto_align = 0;
4241 cons (size);
4242 md.auto_align = saved_auto_align;
4243}
4244
4245static void
4246dot_xfloat_cons (kind)
4247 int kind;
4248{
4249 char *name = parse_section_name ();
4250 if (!name)
4251 return;
4252
4d5a53ff 4253 md.keep_pending_output = 1;
800eeca4
JW		 4254 set_section (name);
4255 stmt_float_cons (kind);
4256 obj_elf_previous (0);
4d5a53ff 4257 md.keep_pending_output = 0;
800eeca4
JW		 4258}
4259
4260static void
4261dot_xstringer (zero)
4262 int zero;
4263{
4264 char *name = parse_section_name ();
4265 if (!name)
4266 return;
4267
4d5a53ff 4268 md.keep_pending_output = 1;
800eeca4
JW		 4269 set_section (name);
4270 stringer (zero);
4271 obj_elf_previous (0);
4d5a53ff 4272 md.keep_pending_output = 0;
800eeca4
JW		 4273}
4274
4275static void
4276dot_xdata_ua (size)
4277 int size;
4278{
4279 int saved_auto_align = md.auto_align;
4280 char *name = parse_section_name ();
4281 if (!name)
4282 return;
4283
4d5a53ff 4284 md.keep_pending_output = 1;
800eeca4
JW		 4285 set_section (name);
4286 md.auto_align = 0;
4287 cons (size);
4288 md.auto_align = saved_auto_align;
4289 obj_elf_previous (0);
4d5a53ff 4290 md.keep_pending_output = 0;
800eeca4
JW		 4291}
4292
4293static void
4294dot_xfloat_cons_ua (kind)
4295 int kind;
4296{
4297 int saved_auto_align = md.auto_align;
4298 char *name = parse_section_name ();
4299 if (!name)
4300 return;
4301
4d5a53ff 4302 md.keep_pending_output = 1;
800eeca4
JW		 4303 set_section (name);
4304 md.auto_align = 0;
4305 stmt_float_cons (kind);
4306 md.auto_align = saved_auto_align;
4307 obj_elf_previous (0);
4d5a53ff 4308 md.keep_pending_output = 0;
800eeca4
JW		 4309}
4310
4311/* .reg.val <regname>,value */
542d6675 4312
800eeca4
JW		 4313static void
4314dot_reg_val (dummy)
2434f565 4315 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4316{
4317 expressionS reg;
4318
4319 expression (&reg);
4320 if (reg.X_op != O_register)
4321 {
4322 as_bad (_("Register name expected"));
4323 ignore_rest_of_line ();
4324 }
4325 else if (*input_line_pointer++ != ',')
4326 {
4327 as_bad (_("Comma expected"));
4328 ignore_rest_of_line ();
4329 }
197865e8 4330 else
800eeca4
JW		 4331 {
4332 valueT value = get_absolute_expression ();
4333 int regno = reg.X_add_number;
542d6675
KH		 4334 if (regno < REG_GR || regno > REG_GR + 128)
4335 as_warn (_("Register value annotation ignored"));
800eeca4 4336 else
542d6675
KH		 4337 {
4338 gr_values[regno - REG_GR].known = 1;
4339 gr_values[regno - REG_GR].value = value;
4340 gr_values[regno - REG_GR].path = md.path;
4341 }
800eeca4
JW		 4342 }
4343 demand_empty_rest_of_line ();
4344}
4345
197865e8 4346/* select dv checking mode
800eeca4
JW		 4347 .auto
4348 .explicit
4349 .default
4350
197865e8 4351 A stop is inserted when changing modes
800eeca4 4352 */
542d6675 4353
800eeca4
JW		 4354static void
4355dot_dv_mode (type)
542d6675 4356 int type;
800eeca4
JW		 4357{
4358 if (md.manual_bundling)
4359 as_warn (_("Directive invalid within a bundle"));
4360
4361 if (type == 'E' || type == 'A')
4362 md.mode_explicitly_set = 0;
4363 else
4364 md.mode_explicitly_set = 1;
4365
4366 md.detect_dv = 1;
4367 switch (type)
4368 {
4369 case 'A':
4370 case 'a':
4371 if (md.explicit_mode)
542d6675 4372 insn_group_break (1, 0, 0);
800eeca4
JW		 4373 md.explicit_mode = 0;
4374 break;
4375 case 'E':
4376 case 'e':
4377 if (!md.explicit_mode)
542d6675 4378 insn_group_break (1, 0, 0);
800eeca4
JW		 4379 md.explicit_mode = 1;
4380 break;
4381 default:
4382 case 'd':
4383 if (md.explicit_mode != md.default_explicit_mode)
542d6675 4384 insn_group_break (1, 0, 0);
800eeca4
JW		 4385 md.explicit_mode = md.default_explicit_mode;
4386 md.mode_explicitly_set = 0;
4387 break;
4388 }
4389}
4390
4391static void
4392print_prmask (mask)
542d6675 4393 valueT mask;
800eeca4
JW		 4394{
4395 int regno;
4396 char *comma = "";
542d6675 4397 for (regno = 0; regno < 64; regno++)
800eeca4 4398 {
542d6675
KH		 4399 if (mask & ((valueT) 1 << regno))
4400 {
4401 fprintf (stderr, "%s p%d", comma, regno);
4402 comma = ",";
4403 }
800eeca4
JW		 4404 }
4405}
4406
4407/*
4408 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4409 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4410 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4411 .pred.safe_across_calls p1 [, p2 [,...]]
4412 */
542d6675 4413
800eeca4
JW		 4414static void
4415dot_pred_rel (type)
542d6675 4416 int type;
800eeca4
JW		 4417{
4418 valueT mask = 0;
4419 int count = 0;
4420 int p1 = -1, p2 = -1;
4421
4422 if (type == 0)
4423 {
4424 if (*input_line_pointer != '"')
542d6675
KH		 4425 {
4426 as_bad (_("Missing predicate relation type"));
4427 ignore_rest_of_line ();
4428 return;
4429 }
197865e8 4430 else
542d6675
KH		 4431 {
4432 int len;
4433 char *form = demand_copy_C_string (&len);
4434 if (strcmp (form, "mutex") == 0)
4435 type = 'm';
4436 else if (strcmp (form, "clear") == 0)
4437 type = 'c';
4438 else if (strcmp (form, "imply") == 0)
4439 type = 'i';
4440 else
4441 {
4442 as_bad (_("Unrecognized predicate relation type"));
4443 ignore_rest_of_line ();
4444 return;
4445 }
4446 }
800eeca4 4447 if (*input_line_pointer == ',')
542d6675 4448 ++input_line_pointer;
800eeca4
JW		 4449 SKIP_WHITESPACE ();
4450 }
4451
4452 SKIP_WHITESPACE ();
4453 while (1)
4454 {
4455 valueT bit = 1;
4456 int regno;
197865e8 4457
800eeca4 4458 if (toupper (*input_line_pointer) != 'P'
542d6675
KH		 4459 || (regno = atoi (++input_line_pointer)) < 0
4460 || regno > 63)
4461 {
4462 as_bad (_("Predicate register expected"));
4463 ignore_rest_of_line ();
4464 return;
4465 }
800eeca4 4466 while (isdigit (*input_line_pointer))
542d6675 4467 ++input_line_pointer;
800eeca4 4468 if (p1 == -1)
542d6675 4469 p1 = regno;
800eeca4 4470 else if (p2 == -1)
542d6675 4471 p2 = regno;
800eeca4
JW		 4472 bit <<= regno;
4473 if (mask & bit)
542d6675
KH		 4474 as_warn (_("Duplicate predicate register ignored"));
4475 mask |= bit;
4476 count++;
4477 /* See if it's a range. */
800eeca4 4478 if (*input_line_pointer == '-')
542d6675
KH		 4479 {
4480 valueT stop = 1;
4481 ++input_line_pointer;
4482
4483 if (toupper (*input_line_pointer) != 'P'
4484 || (regno = atoi (++input_line_pointer)) < 0
4485 || regno > 63)
4486 {
4487 as_bad (_("Predicate register expected"));
4488 ignore_rest_of_line ();
4489 return;
4490 }
4491 while (isdigit (*input_line_pointer))
4492 ++input_line_pointer;
4493 stop <<= regno;
4494 if (bit >= stop)
4495 {
4496 as_bad (_("Bad register range"));
4497 ignore_rest_of_line ();
4498 return;
4499 }
4500 while (bit < stop)
4501 {
4502 bit <<= 1;
4503 mask |= bit;
4504 count++;
4505 }
4506 SKIP_WHITESPACE ();
4507 }
800eeca4 4508 if (*input_line_pointer != ',')
542d6675 4509 break;
800eeca4
JW		 4510 ++input_line_pointer;
4511 SKIP_WHITESPACE ();
4512 }
4513
4514 switch (type)
4515 {
4516 case 'c':
4517 if (count == 0)
542d6675 4518 mask = ~(valueT) 0;
800eeca4 4519 clear_qp_mutex (mask);
197865e8 4520 clear_qp_implies (mask, (valueT) 0);
800eeca4
JW		 4521 break;
4522 case 'i':
4523 if (count != 2 || p1 == -1 || p2 == -1)
542d6675 4524 as_bad (_("Predicate source and target required"));
800eeca4 4525 else if (p1 == 0 || p2 == 0)
542d6675 4526 as_bad (_("Use of p0 is not valid in this context"));
800eeca4 4527 else
542d6675 4528 add_qp_imply (p1, p2);
800eeca4
JW		 4529 break;
4530 case 'm':
4531 if (count < 2)
542d6675
KH		 4532 {
4533 as_bad (_("At least two PR arguments expected"));
4534 break;
4535 }
800eeca4 4536 else if (mask & 1)
542d6675
KH		 4537 {
4538 as_bad (_("Use of p0 is not valid in this context"));
4539 break;
4540 }
800eeca4
JW		 4541 add_qp_mutex (mask);
4542 break;
4543 case 's':
4544 /* note that we don't override any existing relations */
4545 if (count == 0)
542d6675
KH		 4546 {
4547 as_bad (_("At least one PR argument expected"));
4548 break;
4549 }
800eeca4 4550 if (md.debug_dv)
542d6675
KH		 4551 {
4552 fprintf (stderr, "Safe across calls: ");
4553 print_prmask (mask);
4554 fprintf (stderr, "\n");
4555 }
800eeca4
JW		 4556 qp_safe_across_calls = mask;
4557 break;
4558 }
4559 demand_empty_rest_of_line ();
4560}
4561
4562/* .entry label [, label [, ...]]
4563 Hint to DV code that the given labels are to be considered entry points.
542d6675
KH		 4564 Otherwise, only global labels are considered entry points. */
4565
800eeca4
JW		 4566static void
4567dot_entry (dummy)
2434f565 4568 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4569{
4570 const char *err;
4571 char *name;
4572 int c;
4573 symbolS *symbolP;
4574
4575 do
4576 {
4577 name = input_line_pointer;
4578 c = get_symbol_end ();
4579 symbolP = symbol_find_or_make (name);
4580
4581 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4582 if (err)
542d6675
KH		 4583 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4584 name, err);
800eeca4
JW		 4585
4586 *input_line_pointer = c;
4587 SKIP_WHITESPACE ();
4588 c = *input_line_pointer;
4589 if (c == ',')
4590 {
4591 input_line_pointer++;
4592 SKIP_WHITESPACE ();
4593 if (*input_line_pointer == '\n')
4594 c = '\n';
4595 }
4596 }
4597 while (c == ',');
4598
4599 demand_empty_rest_of_line ();
4600}
4601
197865e8 4602/* .mem.offset offset, base
542d6675
KH		 4603 "base" is used to distinguish between offsets from a different base. */
4604
800eeca4
JW		 4605static void
4606dot_mem_offset (dummy)
2434f565 4607 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4608{
4609 md.mem_offset.hint = 1;
4610 md.mem_offset.offset = get_absolute_expression ();
4611 if (*input_line_pointer != ',')
4612 {
4613 as_bad (_("Comma expected"));
4614 ignore_rest_of_line ();
4615 return;
4616 }
4617 ++input_line_pointer;
4618 md.mem_offset.base = get_absolute_expression ();
4619 demand_empty_rest_of_line ();
4620}
4621
542d6675 4622/* ia64-specific pseudo-ops: */
800eeca4
JW		 4623const pseudo_typeS md_pseudo_table[] =
4624 {
4625 { "radix", dot_radix, 0 },
4626 { "lcomm", s_lcomm_bytes, 1 },
4627 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4628 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4629 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4630 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4631 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4632 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4633 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
557debba
JW		 4634 { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY },
4635 { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY },
800eeca4
JW		 4636 { "proc", dot_proc, 0 },
4637 { "body", dot_body, 0 },
4638 { "prologue", dot_prologue, 0 },
2434f565
JW		 4639 { "endp", dot_endp, 0 },
4640 { "file", dwarf2_directive_file, 0 },
4641 { "loc", dwarf2_directive_loc, 0 },
4642
4643 { "fframe", dot_fframe, 0 },
4644 { "vframe", dot_vframe, 0 },
4645 { "vframesp", dot_vframesp, 0 },
4646 { "vframepsp", dot_vframepsp, 0 },
4647 { "save", dot_save, 0 },
4648 { "restore", dot_restore, 0 },
4649 { "restorereg", dot_restorereg, 0 },
4650 { "restorereg.p", dot_restorereg_p, 0 },
4651 { "handlerdata", dot_handlerdata, 0 },
4652 { "unwentry", dot_unwentry, 0 },
4653 { "altrp", dot_altrp, 0 },
e0c9811a
JW		 4654 { "savesp", dot_savemem, 0 },
4655 { "savepsp", dot_savemem, 1 },
2434f565
JW		 4656 { "save.g", dot_saveg, 0 },
4657 { "save.f", dot_savef, 0 },
4658 { "save.b", dot_saveb, 0 },
4659 { "save.gf", dot_savegf, 0 },
4660 { "spill", dot_spill, 0 },
4661 { "spillreg", dot_spillreg, 0 },
e0c9811a
JW		 4662 { "spillsp", dot_spillmem, 0 },
4663 { "spillpsp", dot_spillmem, 1 },
2434f565 4664 { "spillreg.p", dot_spillreg_p, 0 },
e0c9811a
JW		 4665 { "spillsp.p", dot_spillmem_p, 0 },
4666 { "spillpsp.p", dot_spillmem_p, 1 },
2434f565
JW		 4667 { "label_state", dot_label_state, 0 },
4668 { "copy_state", dot_copy_state, 0 },
4669 { "unwabi", dot_unwabi, 0 },
4670 { "personality", dot_personality, 0 },
800eeca4 4671#if 0
2434f565 4672 { "estate", dot_estate, 0 },
800eeca4
JW		 4673#endif
4674 { "mii", dot_template, 0x0 },
4675 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4676 { "mlx", dot_template, 0x2 },
4677 { "mmi", dot_template, 0x4 },
4678 { "mfi", dot_template, 0x6 },
4679 { "mmf", dot_template, 0x7 },
4680 { "mib", dot_template, 0x8 },
4681 { "mbb", dot_template, 0x9 },
4682 { "bbb", dot_template, 0xb },
4683 { "mmb", dot_template, 0xc },
4684 { "mfb", dot_template, 0xe },
4685#if 0
4686 { "lb", dot_scope, 0 },
4687 { "le", dot_scope, 1 },
4688#endif
4689 { "align", s_align_bytes, 0 },
4690 { "regstk", dot_regstk, 0 },
4691 { "rotr", dot_rot, DYNREG_GR },
4692 { "rotf", dot_rot, DYNREG_FR },
4693 { "rotp", dot_rot, DYNREG_PR },
4694 { "lsb", dot_byteorder, 0 },
4695 { "msb", dot_byteorder, 1 },
4696 { "psr", dot_psr, 0 },
4697 { "alias", dot_alias, 0 },
4698 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4699
4700 { "xdata1", dot_xdata, 1 },
4701 { "xdata2", dot_xdata, 2 },
4702 { "xdata4", dot_xdata, 4 },
4703 { "xdata8", dot_xdata, 8 },
4704 { "xreal4", dot_xfloat_cons, 'f' },
4705 { "xreal8", dot_xfloat_cons, 'd' },
4706 { "xreal10", dot_xfloat_cons, 'x' },
4707 { "xstring", dot_xstringer, 0 },
4708 { "xstringz", dot_xstringer, 1 },
4709
542d6675 4710 /* unaligned versions: */
800eeca4
JW		 4711 { "xdata2.ua", dot_xdata_ua, 2 },
4712 { "xdata4.ua", dot_xdata_ua, 4 },
4713 { "xdata8.ua", dot_xdata_ua, 8 },
4714 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4715 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4716 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4717
4718 /* annotations/DV checking support */
4719 { "entry", dot_entry, 0 },
2434f565 4720 { "mem.offset", dot_mem_offset, 0 },
800eeca4
JW		 4721 { "pred.rel", dot_pred_rel, 0 },
4722 { "pred.rel.clear", dot_pred_rel, 'c' },
4723 { "pred.rel.imply", dot_pred_rel, 'i' },
4724 { "pred.rel.mutex", dot_pred_rel, 'm' },
4725 { "pred.safe_across_calls", dot_pred_rel, 's' },
2434f565 4726 { "reg.val", dot_reg_val, 0 },
800eeca4
JW		 4727 { "auto", dot_dv_mode, 'a' },
4728 { "explicit", dot_dv_mode, 'e' },
4729 { "default", dot_dv_mode, 'd' },
4730
87885043
JW		 4731 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4732 IA-64 aligns data allocation pseudo-ops by default, so we have to
4733 tell it that these ones are supposed to be unaligned. Long term,
4734 should rewrite so that only IA-64 specific data allocation pseudo-ops
4735 are aligned by default. */
4736 {"2byte", stmt_cons_ua, 2},
4737 {"4byte", stmt_cons_ua, 4},
4738 {"8byte", stmt_cons_ua, 8},
4739
800eeca4
JW		 4740 { NULL, 0, 0 }
4741 };
4742
4743static const struct pseudo_opcode
4744 {
4745 const char *name;
4746 void (*handler) (int);
4747 int arg;
4748 }
4749pseudo_opcode[] =
4750 {
4751 /* these are more like pseudo-ops, but don't start with a dot */
4752 { "data1", cons, 1 },
4753 { "data2", cons, 2 },
4754 { "data4", cons, 4 },
4755 { "data8", cons, 8 },
4756 { "real4", stmt_float_cons, 'f' },
4757 { "real8", stmt_float_cons, 'd' },
4758 { "real10", stmt_float_cons, 'x' },
4759 { "string", stringer, 0 },
4760 { "stringz", stringer, 1 },
4761
542d6675 4762 /* unaligned versions: */
800eeca4
JW		 4763 { "data2.ua", stmt_cons_ua, 2 },
4764 { "data4.ua", stmt_cons_ua, 4 },
4765 { "data8.ua", stmt_cons_ua, 8 },
4766 { "real4.ua", float_cons, 'f' },
4767 { "real8.ua", float_cons, 'd' },
4768 { "real10.ua", float_cons, 'x' },
4769 };
4770
4771/* Declare a register by creating a symbol for it and entering it in
4772 the symbol table. */
542d6675
KH		 4773
4774static symbolS *
800eeca4
JW		 4775declare_register (name, regnum)
4776 const char *name;
4777 int regnum;
4778{
4779 const char *err;
4780 symbolS *sym;
4781
4782 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4783
4784 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4785 if (err)
4786 as_fatal ("Inserting \"%s\" into register table failed: %s",
4787 name, err);
4788
4789 return sym;
4790}
4791
4792static void
4793declare_register_set (prefix, num_regs, base_regnum)
4794 const char *prefix;
4795 int num_regs;
4796 int base_regnum;
4797{
4798 char name[8];
4799 int i;
4800
4801 for (i = 0; i < num_regs; ++i)
4802 {
4803 sprintf (name, "%s%u", prefix, i);
4804 declare_register (name, base_regnum + i);
4805 }
4806}
4807
4808static unsigned int
4809operand_width (opnd)
4810 enum ia64_opnd opnd;
4811{
4812 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4813 unsigned int bits = 0;
4814 int i;
4815
4816 bits = 0;
4817 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4818 bits += odesc->field[i].bits;
4819
4820 return bits;
4821}
4822
87f8eb97 4823static enum operand_match_result
800eeca4
JW		 4824operand_match (idesc, index, e)
4825 const struct ia64_opcode *idesc;
4826 int index;
4827 expressionS *e;
4828{
4829 enum ia64_opnd opnd = idesc->operands[index];
4830 int bits, relocatable = 0;
4831 struct insn_fix *fix;
4832 bfd_signed_vma val;
4833
4834 switch (opnd)
4835 {
542d6675 4836 /* constants: */
800eeca4
JW		 4837
4838 case IA64_OPND_AR_CCV:
4839 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
87f8eb97 4840 return OPERAND_MATCH;
800eeca4
JW		 4841 break;
4842
4843 case IA64_OPND_AR_PFS:
4844 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
87f8eb97 4845 return OPERAND_MATCH;
800eeca4
JW		 4846 break;
4847
4848 case IA64_OPND_GR0:
4849 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
87f8eb97 4850 return OPERAND_MATCH;
800eeca4
JW		 4851 break;
4852
4853 case IA64_OPND_IP:
4854 if (e->X_op == O_register && e->X_add_number == REG_IP)
87f8eb97 4855 return OPERAND_MATCH;
800eeca4
JW		 4856 break;
4857
4858 case IA64_OPND_PR:
4859 if (e->X_op == O_register && e->X_add_number == REG_PR)
87f8eb97 4860 return OPERAND_MATCH;
800eeca4
JW		 4861 break;
4862
4863 case IA64_OPND_PR_ROT:
4864 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
87f8eb97 4865 return OPERAND_MATCH;
800eeca4
JW		 4866 break;
4867
4868 case IA64_OPND_PSR:
4869 if (e->X_op == O_register && e->X_add_number == REG_PSR)
87f8eb97 4870 return OPERAND_MATCH;
800eeca4
JW		 4871 break;
4872
4873 case IA64_OPND_PSR_L:
4874 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
87f8eb97 4875 return OPERAND_MATCH;
800eeca4
JW		 4876 break;
4877
4878 case IA64_OPND_PSR_UM:
4879 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
87f8eb97 4880 return OPERAND_MATCH;
800eeca4
JW		 4881 break;
4882
4883 case IA64_OPND_C1:
87f8eb97
JW		 4884 if (e->X_op == O_constant)
4885 {
4886 if (e->X_add_number == 1)
4887 return OPERAND_MATCH;
4888 else
4889 return OPERAND_OUT_OF_RANGE;
4890 }
800eeca4
JW		 4891 break;
4892
4893 case IA64_OPND_C8:
87f8eb97
JW		 4894 if (e->X_op == O_constant)
4895 {
4896 if (e->X_add_number == 8)
4897 return OPERAND_MATCH;
4898 else
4899 return OPERAND_OUT_OF_RANGE;
4900 }
800eeca4
JW		 4901 break;
4902
4903 case IA64_OPND_C16:
87f8eb97
JW		 4904 if (e->X_op == O_constant)
4905 {
4906 if (e->X_add_number == 16)
4907 return OPERAND_MATCH;
4908 else
4909 return OPERAND_OUT_OF_RANGE;
4910 }
800eeca4
JW		 4911 break;
4912
542d6675 4913 /* register operands: */
800eeca4
JW		 4914
4915 case IA64_OPND_AR3:
4916 if (e->X_op == O_register && e->X_add_number >= REG_AR
4917 && e->X_add_number < REG_AR + 128)
87f8eb97 4918 return OPERAND_MATCH;
800eeca4
JW		 4919 break;
4920
4921 case IA64_OPND_B1:
4922 case IA64_OPND_B2:
4923 if (e->X_op == O_register && e->X_add_number >= REG_BR
4924 && e->X_add_number < REG_BR + 8)
87f8eb97 4925 return OPERAND_MATCH;
800eeca4
JW		 4926 break;
4927
4928 case IA64_OPND_CR3:
4929 if (e->X_op == O_register && e->X_add_number >= REG_CR
4930 && e->X_add_number < REG_CR + 128)
87f8eb97 4931 return OPERAND_MATCH;
800eeca4
JW		 4932 break;
4933
4934 case IA64_OPND_F1:
4935 case IA64_OPND_F2:
4936 case IA64_OPND_F3:
4937 case IA64_OPND_F4:
4938 if (e->X_op == O_register && e->X_add_number >= REG_FR
4939 && e->X_add_number < REG_FR + 128)
87f8eb97 4940 return OPERAND_MATCH;
800eeca4
JW		 4941 break;
4942
4943 case IA64_OPND_P1:
4944 case IA64_OPND_P2:
4945 if (e->X_op == O_register && e->X_add_number >= REG_P
4946 && e->X_add_number < REG_P + 64)
87f8eb97 4947 return OPERAND_MATCH;
800eeca4
JW		 4948 break;
4949
4950 case IA64_OPND_R1:
4951 case IA64_OPND_R2:
4952 case IA64_OPND_R3:
4953 if (e->X_op == O_register && e->X_add_number >= REG_GR
4954 && e->X_add_number < REG_GR + 128)
87f8eb97 4955 return OPERAND_MATCH;
800eeca4
JW		 4956 break;
4957
4958 case IA64_OPND_R3_2:
87f8eb97
JW		 4959 if (e->X_op == O_register && e->X_add_number >= REG_GR)
4960 {
4961 if (e->X_add_number < REG_GR + 4)
4962 return OPERAND_MATCH;
4963 else if (e->X_add_number < REG_GR + 128)
4964 return OPERAND_OUT_OF_RANGE;
4965 }
800eeca4
JW		 4966 break;
4967
542d6675 4968 /* indirect operands: */
800eeca4
JW		 4969 case IA64_OPND_CPUID_R3:
4970 case IA64_OPND_DBR_R3:
4971 case IA64_OPND_DTR_R3:
4972 case IA64_OPND_ITR_R3:
4973 case IA64_OPND_IBR_R3:
4974 case IA64_OPND_MSR_R3:
4975 case IA64_OPND_PKR_R3:
4976 case IA64_OPND_PMC_R3:
4977 case IA64_OPND_PMD_R3:
4978 case IA64_OPND_RR_R3:
4979 if (e->X_op == O_index && e->X_op_symbol
4980 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4981 == opnd - IA64_OPND_CPUID_R3))
87f8eb97 4982 return OPERAND_MATCH;
800eeca4
JW		 4983 break;
4984
4985 case IA64_OPND_MR3:
4986 if (e->X_op == O_index && !e->X_op_symbol)
87f8eb97 4987 return OPERAND_MATCH;
800eeca4
JW		 4988 break;
4989
542d6675 4990 /* immediate operands: */
800eeca4
JW		 4991 case IA64_OPND_CNT2a:
4992 case IA64_OPND_LEN4:
4993 case IA64_OPND_LEN6:
4994 bits = operand_width (idesc->operands[index]);
87f8eb97
JW		 4995 if (e->X_op == O_constant)
4996 {
4997 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4998 return OPERAND_MATCH;
4999 else
5000 return OPERAND_OUT_OF_RANGE;
5001 }
800eeca4
JW		 5002 break;
5003
5004 case IA64_OPND_CNT2b:
87f8eb97
JW		 5005 if (e->X_op == O_constant)
5006 {
5007 if ((bfd_vma) (e->X_add_number - 1) < 3)
5008 return OPERAND_MATCH;
5009 else
5010 return OPERAND_OUT_OF_RANGE;
5011 }
800eeca4
JW		 5012 break;
5013
5014 case IA64_OPND_CNT2c:
5015 val = e->X_add_number;
87f8eb97
JW		 5016 if (e->X_op == O_constant)
5017 {
5018 if ((val == 0 || val == 7 || val == 15 || val == 16))
5019 return OPERAND_MATCH;
5020 else
5021 return OPERAND_OUT_OF_RANGE;
5022 }
800eeca4
JW		 5023 break;
5024
5025 case IA64_OPND_SOR:
5026 /* SOR must be an integer multiple of 8 */
87f8eb97
JW		 5027 if (e->X_op == O_constant && e->X_add_number & 0x7)
5028 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5029 case IA64_OPND_SOF:
5030 case IA64_OPND_SOL:
87f8eb97
JW		 5031 if (e->X_op == O_constant)
5032 {
5033 if ((bfd_vma) e->X_add_number <= 96)
5034 return OPERAND_MATCH;
5035 else
5036 return OPERAND_OUT_OF_RANGE;
5037 }
800eeca4
JW		 5038 break;
5039
5040 case IA64_OPND_IMMU62:
5041 if (e->X_op == O_constant)
542d6675 5042 {
800eeca4 5043 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
87f8eb97
JW		 5044 return OPERAND_MATCH;
5045 else
5046 return OPERAND_OUT_OF_RANGE;
542d6675 5047 }
197865e8 5048 else
542d6675
KH		 5049 {
5050 /* FIXME -- need 62-bit relocation type */
5051 as_bad (_("62-bit relocation not yet implemented"));
5052 }
800eeca4
JW		 5053 break;
5054
5055 case IA64_OPND_IMMU64:
5056 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
5057 || e->X_op == O_subtract)
5058 {
5059 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5060 fix->code = BFD_RELOC_IA64_IMM64;
5061 if (e->X_op != O_subtract)
5062 {
5063 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5064 if (e->X_op == O_pseudo_fixup)
5065 e->X_op = O_symbol;
5066 }
5067
5068 fix->opnd = idesc->operands[index];
5069 fix->expr = *e;
5070 fix->is_pcrel = 0;
5071 ++CURR_SLOT.num_fixups;
87f8eb97 5072 return OPERAND_MATCH;
800eeca4
JW		 5073 }
5074 else if (e->X_op == O_constant)
87f8eb97 5075 return OPERAND_MATCH;
800eeca4
JW		 5076 break;
5077
5078 case IA64_OPND_CCNT5:
5079 case IA64_OPND_CNT5:
5080 case IA64_OPND_CNT6:
5081 case IA64_OPND_CPOS6a:
5082 case IA64_OPND_CPOS6b:
5083 case IA64_OPND_CPOS6c:
5084 case IA64_OPND_IMMU2:
5085 case IA64_OPND_IMMU7a:
5086 case IA64_OPND_IMMU7b:
800eeca4
JW		 5087 case IA64_OPND_IMMU21:
5088 case IA64_OPND_IMMU24:
5089 case IA64_OPND_MBTYPE4:
5090 case IA64_OPND_MHTYPE8:
5091 case IA64_OPND_POS6:
5092 bits = operand_width (idesc->operands[index]);
87f8eb97
JW		 5093 if (e->X_op == O_constant)
5094 {
5095 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5096 return OPERAND_MATCH;
5097 else
5098 return OPERAND_OUT_OF_RANGE;
5099 }
800eeca4
JW		 5100 break;
5101
bf3ca999
TW		 5102 case IA64_OPND_IMMU9:
5103 bits = operand_width (idesc->operands[index]);
87f8eb97 5104 if (e->X_op == O_constant)
542d6675 5105 {
87f8eb97
JW		 5106 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5107 {
5108 int lobits = e->X_add_number & 0x3;
5109 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
5110 e->X_add_number |= (bfd_vma) 0x3;
5111 return OPERAND_MATCH;
5112 }
5113 else
5114 return OPERAND_OUT_OF_RANGE;
542d6675 5115 }
bf3ca999
TW		 5116 break;
5117
800eeca4
JW		 5118 case IA64_OPND_IMM44:
5119 /* least 16 bits must be zero */
5120 if ((e->X_add_number & 0xffff) != 0)
87f8eb97
JW		 5121 /* XXX technically, this is wrong: we should not be issuing warning
5122 messages until we're sure this instruction pattern is going to
5123 be used! */
542d6675 5124 as_warn (_("lower 16 bits of mask ignored"));
800eeca4 5125
87f8eb97 5126 if (e->X_op == O_constant)
542d6675 5127 {
87f8eb97
JW		 5128 if (((e->X_add_number >= 0
5129 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44))
5130 || (e->X_add_number < 0
5131 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44))))
542d6675 5132 {
87f8eb97
JW		 5133 /* sign-extend */
5134 if (e->X_add_number >= 0
5135 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
5136 {
5137 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
5138 }
5139 return OPERAND_MATCH;
542d6675 5140 }
87f8eb97
JW		 5141 else
5142 return OPERAND_OUT_OF_RANGE;
542d6675 5143 }
800eeca4
JW		 5144 break;
5145
5146 case IA64_OPND_IMM17:
5147 /* bit 0 is a don't care (pr0 is hardwired to 1) */
87f8eb97 5148 if (e->X_op == O_constant)
542d6675 5149 {
87f8eb97
JW		 5150 if (((e->X_add_number >= 0
5151 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17))
5152 || (e->X_add_number < 0
5153 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17))))
542d6675 5154 {
87f8eb97
JW		 5155 /* sign-extend */
5156 if (e->X_add_number >= 0
5157 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
5158 {
5159 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
5160 }
5161 return OPERAND_MATCH;
542d6675 5162 }
87f8eb97
JW		 5163 else
5164 return OPERAND_OUT_OF_RANGE;
542d6675 5165 }
800eeca4
JW		 5166 break;
5167
5168 case IA64_OPND_IMM14:
5169 case IA64_OPND_IMM22:
5170 relocatable = 1;
5171 case IA64_OPND_IMM1:
5172 case IA64_OPND_IMM8:
5173 case IA64_OPND_IMM8U4:
5174 case IA64_OPND_IMM8M1:
5175 case IA64_OPND_IMM8M1U4:
5176 case IA64_OPND_IMM8M1U8:
5177 case IA64_OPND_IMM9a:
5178 case IA64_OPND_IMM9b:
5179 bits = operand_width (idesc->operands[index]);
5180 if (relocatable && (e->X_op == O_symbol
5181 || e->X_op == O_subtract
5182 || e->X_op == O_pseudo_fixup))
5183 {
5184 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5185
5186 if (idesc->operands[index] == IA64_OPND_IMM14)
5187 fix->code = BFD_RELOC_IA64_IMM14;
5188 else
5189 fix->code = BFD_RELOC_IA64_IMM22;
5190
5191 if (e->X_op != O_subtract)
5192 {
5193 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5194 if (e->X_op == O_pseudo_fixup)
5195 e->X_op = O_symbol;
5196 }
5197
5198 fix->opnd = idesc->operands[index];
5199 fix->expr = *e;
5200 fix->is_pcrel = 0;
5201 ++CURR_SLOT.num_fixups;
87f8eb97 5202 return OPERAND_MATCH;
800eeca4
JW		 5203 }
5204 else if (e->X_op != O_constant
5205 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
87f8eb97 5206 return OPERAND_MISMATCH;
800eeca4
JW		 5207
5208 if (opnd == IA64_OPND_IMM8M1U4)
5209 {
5210 /* Zero is not valid for unsigned compares that take an adjusted
5211 constant immediate range. */
5212 if (e->X_add_number == 0)
87f8eb97 5213 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5214
5215 /* Sign-extend 32-bit unsigned numbers, so that the following range
5216 checks will work. */
5217 val = e->X_add_number;
197865e8
KH		 5218 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5219 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 5220 val = ((val << 32) >> 32);
5221
5222 /* Check for 0x100000000. This is valid because
5223 0x100000000-1 is the same as ((uint32_t) -1). */
5224 if (val == ((bfd_signed_vma) 1 << 32))
87f8eb97 5225 return OPERAND_MATCH;
800eeca4
JW		 5226
5227 val = val - 1;
5228 }
5229 else if (opnd == IA64_OPND_IMM8M1U8)
5230 {
5231 /* Zero is not valid for unsigned compares that take an adjusted
5232 constant immediate range. */
5233 if (e->X_add_number == 0)
87f8eb97 5234 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5235
5236 /* Check for 0x10000000000000000. */
5237 if (e->X_op == O_big)
5238 {
5239 if (generic_bignum[0] == 0
5240 && generic_bignum[1] == 0
5241 && generic_bignum[2] == 0
5242 && generic_bignum[3] == 0
5243 && generic_bignum[4] == 1)
87f8eb97 5244 return OPERAND_MATCH;
800eeca4 5245 else
87f8eb97 5246 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5247 }
5248 else
5249 val = e->X_add_number - 1;
5250 }
5251 else if (opnd == IA64_OPND_IMM8M1)
5252 val = e->X_add_number - 1;
5253 else if (opnd == IA64_OPND_IMM8U4)
5254 {
5255 /* Sign-extend 32-bit unsigned numbers, so that the following range
5256 checks will work. */
5257 val = e->X_add_number;
197865e8
KH		 5258 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5259 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 5260 val = ((val << 32) >> 32);
5261 }
5262 else
5263 val = e->X_add_number;
5264
2434f565
JW		 5265 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1)))
5266 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1))))
87f8eb97
JW		 5267 return OPERAND_MATCH;
5268 else
5269 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5270
5271 case IA64_OPND_INC3:
5272 /* +/- 1, 4, 8, 16 */
5273 val = e->X_add_number;
5274 if (val < 0)
5275 val = -val;
87f8eb97
JW		 5276 if (e->X_op == O_constant)
5277 {
5278 if ((val == 1 || val == 4 || val == 8 || val == 16))
5279 return OPERAND_MATCH;
5280 else
5281 return OPERAND_OUT_OF_RANGE;
5282 }
800eeca4
JW		 5283 break;
5284
5285 case IA64_OPND_TGT25:
5286 case IA64_OPND_TGT25b:
5287 case IA64_OPND_TGT25c:
5288 case IA64_OPND_TGT64:
5289 if (e->X_op == O_symbol)
5290 {
5291 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5292 if (opnd == IA64_OPND_TGT25)
5293 fix->code = BFD_RELOC_IA64_PCREL21F;
5294 else if (opnd == IA64_OPND_TGT25b)
5295 fix->code = BFD_RELOC_IA64_PCREL21M;
5296 else if (opnd == IA64_OPND_TGT25c)
5297 fix->code = BFD_RELOC_IA64_PCREL21B;
542d6675 5298 else if (opnd == IA64_OPND_TGT64)
c67e42c9
RH		 5299 fix->code = BFD_RELOC_IA64_PCREL60B;
5300 else
5301 abort ();
5302
800eeca4
JW		 5303 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5304 fix->opnd = idesc->operands[index];
5305 fix->expr = *e;
5306 fix->is_pcrel = 1;
5307 ++CURR_SLOT.num_fixups;
87f8eb97 5308 return OPERAND_MATCH;
800eeca4
JW		 5309 }
5310 case IA64_OPND_TAG13:
5311 case IA64_OPND_TAG13b:
5312 switch (e->X_op)
5313 {
5314 case O_constant:
87f8eb97 5315 return OPERAND_MATCH;
800eeca4
JW		 5316
5317 case O_symbol:
5318 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
fa1cb89c
JW		 5319 /* There are no external relocs for TAG13/TAG13b fields, so we
5320 create a dummy reloc. This will not live past md_apply_fix3. */
5321 fix->code = BFD_RELOC_UNUSED;
5322 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
800eeca4
JW		 5323 fix->opnd = idesc->operands[index];
5324 fix->expr = *e;
5325 fix->is_pcrel = 1;
5326 ++CURR_SLOT.num_fixups;
87f8eb97 5327 return OPERAND_MATCH;
800eeca4
JW		 5328
5329 default:
5330 break;
5331 }
5332 break;
5333
5334 default:
5335 break;
5336 }
87f8eb97 5337 return OPERAND_MISMATCH;
800eeca4
JW		 5338}
5339
5340static int
5341parse_operand (e)
5342 expressionS *e;
5343{
5344 int sep = '\0';
5345
5346 memset (e, 0, sizeof (*e));
5347 e->X_op = O_absent;
5348 SKIP_WHITESPACE ();
5349 if (*input_line_pointer != '}')
5350 expression (e);
5351 sep = *input_line_pointer++;
5352
5353 if (sep == '}')
5354 {
5355 if (!md.manual_bundling)
5356 as_warn ("Found '}' when manual bundling is off");
5357 else
5358 CURR_SLOT.manual_bundling_off = 1;
5359 md.manual_bundling = 0;
5360 sep = '\0';
5361 }
5362 return sep;
5363}
5364
5365/* Returns the next entry in the opcode table that matches the one in
5366 IDESC, and frees the entry in IDESC. If no matching entry is
197865e8 5367 found, NULL is returned instead. */
800eeca4
JW		 5368
5369static struct ia64_opcode *
5370get_next_opcode (struct ia64_opcode *idesc)
5371{
5372 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
5373 ia64_free_opcode (idesc);
5374 return next;
5375}
5376
5377/* Parse the operands for the opcode and find the opcode variant that
5378 matches the specified operands, or NULL if no match is possible. */
542d6675
KH		 5379
5380static struct ia64_opcode *
800eeca4
JW		 5381parse_operands (idesc)
5382 struct ia64_opcode *idesc;
5383{
5384 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
87f8eb97 5385 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0;
800eeca4 5386 enum ia64_opnd expected_operand = IA64_OPND_NIL;
87f8eb97 5387 enum operand_match_result result;
800eeca4
JW		 5388 char mnemonic[129];
5389 char *first_arg = 0, *end, *saved_input_pointer;
5390 unsigned int sof;
5391
5392 assert (strlen (idesc->name) <= 128);
5393
5394 strcpy (mnemonic, idesc->name);
5395 if (idesc->operands[2] == IA64_OPND_SOF)
5396 {
5397 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5398 can't parse the first operand until we have parsed the
5399 remaining operands of the "alloc" instruction. */
5400 SKIP_WHITESPACE ();
5401 first_arg = input_line_pointer;
5402 end = strchr (input_line_pointer, '=');
5403 if (!end)
5404 {
5405 as_bad ("Expected separator `='");
5406 return 0;
5407 }
5408 input_line_pointer = end + 1;
5409 ++i;
5410 ++num_outputs;
5411 }
5412
5413 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5414 {
5415 sep = parse_operand (CURR_SLOT.opnd + i);
5416 if (CURR_SLOT.opnd[i].X_op == O_absent)
5417 break;
5418
5419 ++num_operands;
5420
5421 if (sep != '=' && sep != ',')
5422 break;
5423
5424 if (sep == '=')
5425 {
5426 if (num_outputs > 0)
5427 as_bad ("Duplicate equal sign (=) in instruction");
5428 else
5429 num_outputs = i + 1;
5430 }
5431 }
5432 if (sep != '\0')
5433 {
5434 as_bad ("Illegal operand separator `%c'", sep);
5435 return 0;
5436 }
197865e8 5437
800eeca4
JW		 5438 if (idesc->operands[2] == IA64_OPND_SOF)
5439 {
5440 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5441 know (strcmp (idesc->name, "alloc") == 0);
5442 if (num_operands == 5 /* first_arg not included in this count! */
5443 && CURR_SLOT.opnd[2].X_op == O_constant
5444 && CURR_SLOT.opnd[3].X_op == O_constant
5445 && CURR_SLOT.opnd[4].X_op == O_constant
5446 && CURR_SLOT.opnd[5].X_op == O_constant)
5447 {
5448 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5449 CURR_SLOT.opnd[3].X_add_number,
5450 CURR_SLOT.opnd[4].X_add_number,
5451 CURR_SLOT.opnd[5].X_add_number);
5452
542d6675 5453 /* now we can parse the first arg: */
800eeca4
JW		 5454 saved_input_pointer = input_line_pointer;
5455 input_line_pointer = first_arg;
5456 sep = parse_operand (CURR_SLOT.opnd + 0);
5457 if (sep != '=')
5458 --num_outputs; /* force error */
5459 input_line_pointer = saved_input_pointer;
5460
5461 CURR_SLOT.opnd[2].X_add_number = sof;
5462 CURR_SLOT.opnd[3].X_add_number
5463 = sof - CURR_SLOT.opnd[4].X_add_number;
5464 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5465 }
5466 }
5467
5468 highest_unmatched_operand = 0;
87f8eb97
JW		 5469 curr_out_of_range_pos = -1;
5470 error_pos = 0;
800eeca4
JW		 5471 expected_operand = idesc->operands[0];
5472 for (; idesc; idesc = get_next_opcode (idesc))
5473 {
5474 if (num_outputs != idesc->num_outputs)
5475 continue; /* mismatch in # of outputs */
5476
5477 CURR_SLOT.num_fixups = 0;
87f8eb97
JW		 5478
5479 /* Try to match all operands. If we see an out-of-range operand,
5480 then continue trying to match the rest of the operands, since if
5481 the rest match, then this idesc will give the best error message. */
5482
5483 out_of_range_pos = -1;
800eeca4 5484 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
87f8eb97
JW		 5485 {
5486 result = operand_match (idesc, i, CURR_SLOT.opnd + i);
5487 if (result != OPERAND_MATCH)
5488 {
5489 if (result != OPERAND_OUT_OF_RANGE)
5490 break;
5491 if (out_of_range_pos < 0)
5492 /* remember position of the first out-of-range operand: */
5493 out_of_range_pos = i;
5494 }
5495 }
800eeca4 5496
87f8eb97
JW		 5497 /* If we did not match all operands, or if at least one operand was
5498 out-of-range, then this idesc does not match. Keep track of which
5499 idesc matched the most operands before failing. If we have two
5500 idescs that failed at the same position, and one had an out-of-range
5501 operand, then prefer the out-of-range operand. Thus if we have
5502 "add r0=0x1000000,r1" we get an error saying the constant is out
5503 of range instead of an error saying that the constant should have been
5504 a register. */
5505
5506 if (i != num_operands || out_of_range_pos >= 0)
800eeca4 5507 {
87f8eb97
JW		 5508 if (i > highest_unmatched_operand
5509 || (i == highest_unmatched_operand
5510 && out_of_range_pos > curr_out_of_range_pos))
800eeca4
JW		 5511 {
5512 highest_unmatched_operand = i;
87f8eb97
JW		 5513 if (out_of_range_pos >= 0)
5514 {
5515 expected_operand = idesc->operands[out_of_range_pos];
5516 error_pos = out_of_range_pos;
5517 }
5518 else
5519 {
5520 expected_operand = idesc->operands[i];
5521 error_pos = i;
5522 }
5523 curr_out_of_range_pos = out_of_range_pos;
800eeca4
JW		 5524 }
5525 continue;
5526 }
5527
5528 if (num_operands < NELEMS (idesc->operands)
5529 && idesc->operands[num_operands])
5530 continue; /* mismatch in number of arguments */
5531
5532 break;
5533 }
5534 if (!idesc)
5535 {
5536 if (expected_operand)
5537 as_bad ("Operand %u of `%s' should be %s",
87f8eb97 5538 error_pos + 1, mnemonic,
800eeca4
JW		 5539 elf64_ia64_operands[expected_operand].desc);
5540 else
5541 as_bad ("Operand mismatch");
5542 return 0;
5543 }
5544 return idesc;
5545}
5546
88be23ec
BS		 5547/* Keep track of state necessary to determine whether a NOP is necessary
5548 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5549 detect a case where additional NOPs may be necessary. */
5550static int
5551errata_nop_necessary_p (slot, insn_unit)
5552 struct slot *slot;
5553 enum ia64_unit insn_unit;
5554{
5555 int i;
5556 struct group *this_group = md.last_groups + md.group_idx;
5557 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
5558 struct ia64_opcode *idesc = slot->idesc;
5559
5560 /* Test whether this could be the first insn in a problematic sequence. */
5561 if (insn_unit == IA64_UNIT_F)
5562 {
5563 for (i = 0; i < idesc->num_outputs; i++)
5564 if (idesc->operands[i] == IA64_OPND_P1
5565 || idesc->operands[i] == IA64_OPND_P2)
5566 {
5567 int regno = slot->opnd[i].X_add_number - REG_P;
3557da92 5568 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5569 if (regno >= 64)
3557da92 5570 return 0;
88be23ec
BS		 5571 this_group->p_reg_set[regno] = 1;
5572 }
5573 }
5574
5575 /* Test whether this could be the second insn in a problematic sequence. */
5576 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
5577 && prev_group->p_reg_set[slot->qp_regno])
5578 {
5579 for (i = 0; i < idesc->num_outputs; i++)
5580 if (idesc->operands[i] == IA64_OPND_R1
5581 || idesc->operands[i] == IA64_OPND_R2
5582 || idesc->operands[i] == IA64_OPND_R3)
5583 {
5584 int regno = slot->opnd[i].X_add_number - REG_GR;
3557da92 5585 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5586 if (regno >= 128)
3557da92 5587 return 0;
88be23ec
BS		 5588 if (strncmp (idesc->name, "add", 3) != 0
5589 && strncmp (idesc->name, "sub", 3) != 0
5590 && strncmp (idesc->name, "shladd", 6) != 0
5591 && (idesc->flags & IA64_OPCODE_POSTINC) == 0)
5592 this_group->g_reg_set_conditionally[regno] = 1;
5593 }
5594 }
5595
5596 /* Test whether this could be the third insn in a problematic sequence. */
5597 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
5598 {
5599 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5600 idesc->operands[i] == IA64_OPND_R3
5601 /* For mov indirect. */
5602 || idesc->operands[i] == IA64_OPND_RR_R3
5603 || idesc->operands[i] == IA64_OPND_DBR_R3
5604 || idesc->operands[i] == IA64_OPND_IBR_R3
5605 || idesc->operands[i] == IA64_OPND_PKR_R3
5606 || idesc->operands[i] == IA64_OPND_PMC_R3
5607 || idesc->operands[i] == IA64_OPND_PMD_R3
5608 || idesc->operands[i] == IA64_OPND_MSR_R3
5609 || idesc->operands[i] == IA64_OPND_CPUID_R3
5610 /* For itr. */
5611 || idesc->operands[i] == IA64_OPND_ITR_R3
5612 || idesc->operands[i] == IA64_OPND_DTR_R3
5613 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5614 || idesc->operands[i] == IA64_OPND_MR3)
5615 {
5616 int regno = slot->opnd[i].X_add_number - REG_GR;
3557da92 5617 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5618 if (regno >= 128)
3557da92 5619 return 0;
88be23ec
BS		 5620 if (idesc->operands[i] == IA64_OPND_R3)
5621 {
5622 if (strcmp (idesc->name, "fc") != 0
5623 && strcmp (idesc->name, "tak") != 0
5624 && strcmp (idesc->name, "thash") != 0
5625 && strcmp (idesc->name, "tpa") != 0
5626 && strcmp (idesc->name, "ttag") != 0
5627 && strncmp (idesc->name, "ptr", 3) != 0
5628 && strncmp (idesc->name, "ptc", 3) != 0
5629 && strncmp (idesc->name, "probe", 5) != 0)
5630 return 0;
5631 }
bc805888 5632 if (prev_group->g_reg_set_conditionally[regno])
88be23ec
BS		 5633 return 1;
5634 }
5635 }
5636 return 0;
5637}
5638
800eeca4
JW		 5639static void
5640build_insn (slot, insnp)
5641 struct slot *slot;
5642 bfd_vma *insnp;
5643{
5644 const struct ia64_operand *odesc, *o2desc;
5645 struct ia64_opcode *idesc = slot->idesc;
5646 bfd_signed_vma insn, val;
5647 const char *err;
5648 int i;
5649
5650 insn = idesc->opcode | slot->qp_regno;
5651
5652 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5653 {
c67e42c9
RH		 5654 if (slot->opnd[i].X_op == O_register
5655 || slot->opnd[i].X_op == O_constant
5656 || slot->opnd[i].X_op == O_index)
5657 val = slot->opnd[i].X_add_number;
5658 else if (slot->opnd[i].X_op == O_big)
800eeca4 5659 {
c67e42c9
RH		 5660 /* This must be the value 0x10000000000000000. */
5661 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5662 val = 0;
5663 }
5664 else
5665 val = 0;
5666
5667 switch (idesc->operands[i])
5668 {
5669 case IA64_OPND_IMMU64:
800eeca4
JW		 5670 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5671 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5672 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5673 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH		 5674 continue;
5675
5676 case IA64_OPND_IMMU62:
542d6675
KH		 5677 val &= 0x3fffffffffffffffULL;
5678 if (val != slot->opnd[i].X_add_number)
5679 as_warn (_("Value truncated to 62 bits"));
5680 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5681 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 5682 continue;
800eeca4 5683
c67e42c9
RH		 5684 case IA64_OPND_TGT64:
5685 val >>= 4;
5686 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5687 insn |= ((((val >> 59) & 0x1) << 36)
5688 | (((val >> 0) & 0xfffff) << 13));
5689 continue;
800eeca4 5690
c67e42c9
RH		 5691 case IA64_OPND_AR3:
5692 val -= REG_AR;
5693 break;
5694
5695 case IA64_OPND_B1:
5696 case IA64_OPND_B2:
5697 val -= REG_BR;
5698 break;
5699
5700 case IA64_OPND_CR3:
5701 val -= REG_CR;
5702 break;
5703
5704 case IA64_OPND_F1:
5705 case IA64_OPND_F2:
5706 case IA64_OPND_F3:
5707 case IA64_OPND_F4:
5708 val -= REG_FR;
5709 break;
5710
5711 case IA64_OPND_P1:
5712 case IA64_OPND_P2:
5713 val -= REG_P;
5714 break;
5715
5716 case IA64_OPND_R1:
5717 case IA64_OPND_R2:
5718 case IA64_OPND_R3:
5719 case IA64_OPND_R3_2:
5720 case IA64_OPND_CPUID_R3:
5721 case IA64_OPND_DBR_R3:
5722 case IA64_OPND_DTR_R3:
5723 case IA64_OPND_ITR_R3:
5724 case IA64_OPND_IBR_R3:
5725 case IA64_OPND_MR3:
5726 case IA64_OPND_MSR_R3:
5727 case IA64_OPND_PKR_R3:
5728 case IA64_OPND_PMC_R3:
5729 case IA64_OPND_PMD_R3:
197865e8 5730 case IA64_OPND_RR_R3:
c67e42c9
RH		 5731 val -= REG_GR;
5732 break;
5733
5734 default:
5735 break;
5736 }
5737
5738 odesc = elf64_ia64_operands + idesc->operands[i];
5739 err = (*odesc->insert) (odesc, val, &insn);
5740 if (err)
5741 as_bad_where (slot->src_file, slot->src_line,
5742 "Bad operand value: %s", err);
5743 if (idesc->flags & IA64_OPCODE_PSEUDO)
5744 {
5745 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5746 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5747 {
5748 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5749 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5750 }
c67e42c9
RH		 5751 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5752 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5753 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5754 {
c67e42c9
RH		 5755 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5756 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW		 5757 }
5758 }
5759 }
5760 *insnp = insn;
5761}
5762
5763static void
5764emit_one_bundle ()
5765{
5766 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5767 unsigned int manual_bundling = 0;
5768 enum ia64_unit required_unit, insn_unit = 0;
5769 enum ia64_insn_type type[3], insn_type;
5770 unsigned int template, orig_template;
542d6675 5771 bfd_vma insn[3] = { -1, -1, -1 };
800eeca4
JW		 5772 struct ia64_opcode *idesc;
5773 int end_of_insn_group = 0, user_template = -1;
5774 int n, i, j, first, curr;
2434f565 5775 unw_rec_list *ptr;
800eeca4
JW		 5776 bfd_vma t0 = 0, t1 = 0;
5777 struct label_fix *lfix;
5778 struct insn_fix *ifix;
5779 char mnemonic[16];
5780 fixS *fix;
5781 char *f;
5782
5783 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5784 know (first >= 0 & first < NUM_SLOTS);
5785 n = MIN (3, md.num_slots_in_use);
5786
5787 /* Determine template: user user_template if specified, best match
542d6675 5788 otherwise: */
800eeca4
JW		 5789
5790 if (md.slot[first].user_template >= 0)
5791 user_template = template = md.slot[first].user_template;
5792 else
5793 {
032efc85 5794 /* Auto select appropriate template. */
800eeca4
JW		 5795 memset (type, 0, sizeof (type));
5796 curr = first;
5797 for (i = 0; i < n; ++i)
5798 {
032efc85
RH		 5799 if (md.slot[curr].label_fixups && i != 0)
5800 break;
800eeca4
JW		 5801 type[i] = md.slot[curr].idesc->type;
5802 curr = (curr + 1) % NUM_SLOTS;
5803 }
5804 template = best_template[type[0]][type[1]][type[2]];
5805 }
5806
542d6675 5807 /* initialize instructions with appropriate nops: */
800eeca4
JW		 5808 for (i = 0; i < 3; ++i)
5809 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5810
5811 f = frag_more (16);
5812
542d6675 5813 /* now fill in slots with as many insns as possible: */
800eeca4
JW		 5814 curr = first;
5815 idesc = md.slot[curr].idesc;
5816 end_of_insn_group = 0;
5817 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5818 {
e0c9811a
JW		 5819 /* Set the slot number for prologue/body records now as those
5820 refer to the current point, not the point after the
542d6675 5821 instruction has been issued: */
10850f29
JW		 5822 /* Don't try to delete prologue/body records here, as that will cause
5823 them to also be deleted from the master list of unwind records. */
e0c9811a 5824 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
10850f29
JW		 5825 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5826 || ptr->r.type == body)
f5a30c2e
JW		 5827 {
5828 ptr->slot_number = (unsigned long) f + i;
5829 ptr->slot_frag = frag_now;
5830 }
e0c9811a 5831
800eeca4
JW		 5832 if (idesc->flags & IA64_OPCODE_SLOT2)
5833 {
5834 if (manual_bundling && i != 2)
5835 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5836 "`%s' must be last in bundle", idesc->name);
5837 else
5838 i = 2;
5839 }
5840 if (idesc->flags & IA64_OPCODE_LAST)
5841 {
2434f565
JW		 5842 int required_slot;
5843 unsigned int required_template;
800eeca4
JW		 5844
5845 /* If we need a stop bit after an M slot, our only choice is
5846 template 5 (M;;MI). If we need a stop bit after a B
5847 slot, our only choice is to place it at the end of the
5848 bundle, because the only available templates are MIB,
5849 MBB, BBB, MMB, and MFB. We don't handle anything other
5850 than M and B slots because these are the only kind of
5851 instructions that can have the IA64_OPCODE_LAST bit set. */
5852 required_template = template;
5853 switch (idesc->type)
5854 {
5855 case IA64_TYPE_M:
5856 required_slot = 0;
5857 required_template = 5;
5858 break;
5859
5860 case IA64_TYPE_B:
5861 required_slot = 2;
5862 break;
5863
5864 default:
5865 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5866 "Internal error: don't know how to force %s to end"
5867 "of instruction group", idesc->name);
5868 required_slot = i;
5869 break;
5870 }
5871 if (manual_bundling && i != required_slot)
5872 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5873 "`%s' must be last in instruction group",
5874 idesc->name);
5875 if (required_slot < i)
5876 /* Can't fit this instruction. */
5877 break;
5878
5879 i = required_slot;
5880 if (required_template != template)
5881 {
5882 /* If we switch the template, we need to reset the NOPs
5883 after slot i. The slot-types of the instructions ahead
5884 of i never change, so we don't need to worry about
5885 changing NOPs in front of this slot. */
5886 for (j = i; j < 3; ++j)
5887 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5888 }
5889 template = required_template;
5890 }
5891 if (curr != first && md.slot[curr].label_fixups)
5892 {
5893 if (manual_bundling_on)
5894 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5895 "Label must be first in a bundle");
5896 /* This insn must go into the first slot of a bundle. */
5897 break;
5898 }
5899
5900 manual_bundling_on = md.slot[curr].manual_bundling_on;
5901 manual_bundling_off = md.slot[curr].manual_bundling_off;
5902
5903 if (manual_bundling_on)
5904 {
5905 if (curr == first)
5906 manual_bundling = 1;
5907 else
5908 break; /* need to start a new bundle */
5909 }
5910
5911 if (end_of_insn_group && md.num_slots_in_use >= 1)
5912 {
5913 /* We need an instruction group boundary in the middle of a
5914 bundle. See if we can switch to an other template with
5915 an appropriate boundary. */
5916
5917 orig_template = template;
5918 if (i == 1 && (user_template == 4
5919 || (user_template < 0
5920 && (ia64_templ_desc[template].exec_unit[0]
5921 == IA64_UNIT_M))))
5922 {
5923 template = 5;
5924 end_of_insn_group = 0;
5925 }
5926 else if (i == 2 && (user_template == 0
5927 || (user_template < 0
5928 && (ia64_templ_desc[template].exec_unit[1]
5929 == IA64_UNIT_I)))
5930 /* This test makes sure we don't switch the template if
5931 the next instruction is one that needs to be first in
5932 an instruction group. Since all those instructions are
5933 in the M group, there is no way such an instruction can
5934 fit in this bundle even if we switch the template. The
5935 reason we have to check for this is that otherwise we
5936 may end up generating "MI;;I M.." which has the deadly
5937 effect that the second M instruction is no longer the
5938 first in the bundle! --davidm 99/12/16 */
5939 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5940 {
5941 template = 1;
5942 end_of_insn_group = 0;
5943 }
5944 else if (curr != first)
5945 /* can't fit this insn */
5946 break;
5947
5948 if (template != orig_template)
5949 /* if we switch the template, we need to reset the NOPs
5950 after slot i. The slot-types of the instructions ahead
5951 of i never change, so we don't need to worry about
5952 changing NOPs in front of this slot. */
5953 for (j = i; j < 3; ++j)
5954 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5955 }
5956 required_unit = ia64_templ_desc[template].exec_unit[i];
5957
542d6675 5958 /* resolve dynamic opcodes such as "break" and "nop": */
800eeca4
JW		 5959 if (idesc->type == IA64_TYPE_DYN)
5960 {
5961 if ((strcmp (idesc->name, "nop") == 0)
5962 || (strcmp (idesc->name, "break") == 0))
5963 insn_unit = required_unit;
5964 else if (strcmp (idesc->name, "chk.s") == 0)
5965 {
5966 insn_unit = IA64_UNIT_M;
5967 if (required_unit == IA64_UNIT_I)
5968 insn_unit = IA64_UNIT_I;
5969 }
5970 else
5971 as_fatal ("emit_one_bundle: unexpected dynamic op");
5972
5973 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
3d56ab85 5974 ia64_free_opcode (idesc);
800eeca4
JW		 5975 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5976#if 0
5977 know (!idesc->next); /* no resolved dynamic ops have collisions */
5978#endif
5979 }
5980 else
5981 {
5982 insn_type = idesc->type;
5983 insn_unit = IA64_UNIT_NIL;
5984 switch (insn_type)
5985 {
5986 case IA64_TYPE_A:
5987 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5988 insn_unit = required_unit;
5989 break;
542d6675 5990 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
800eeca4
JW		 5991 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5992 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5993 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5994 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5995 default: break;
5996 }
5997 }
5998
5999 if (insn_unit != required_unit)
6000 {
6001 if (required_unit == IA64_UNIT_L
542d6675 6002 && insn_unit == IA64_UNIT_I
800eeca4
JW		 6003 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
6004 {
6005 /* we got ourselves an MLX template but the current
197865e8 6006 instruction isn't an X-unit, or an I-unit instruction
800eeca4
JW		 6007 that can go into the X slot of an MLX template. Duh. */
6008 if (md.num_slots_in_use >= NUM_SLOTS)
6009 {
6010 as_bad_where (md.slot[curr].src_file,
6011 md.slot[curr].src_line,
6012 "`%s' can't go in X slot of "
6013 "MLX template", idesc->name);
542d6675 6014 /* drop this insn so we don't livelock: */
800eeca4
JW		 6015 --md.num_slots_in_use;
6016 }
6017 break;
6018 }
6019 continue; /* try next slot */
6020 }
6021
800eeca4
JW		 6022 {
6023 bfd_vma addr;
6024
f1bcba5b 6025 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
800eeca4
JW		 6026 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
6027 }
6028
88be23ec
BS		 6029 if (errata_nop_necessary_p (md.slot + curr, insn_unit))
6030 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6031
800eeca4
JW		 6032 build_insn (md.slot + curr, insn + i);
6033
10850f29
JW		 6034 /* Set slot counts for non prologue/body unwind records. */
6035 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
6036 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
6037 && ptr->r.type != body)
f5a30c2e
JW		 6038 {
6039 ptr->slot_number = (unsigned long) f + i;
6040 ptr->slot_frag = frag_now;
6041 }
10850f29 6042 md.slot[curr].unwind_record = NULL;
10850f29 6043
800eeca4
JW		 6044 if (required_unit == IA64_UNIT_L)
6045 {
6046 know (i == 1);
6047 /* skip one slot for long/X-unit instructions */
6048 ++i;
6049 }
6050 --md.num_slots_in_use;
6051
542d6675 6052 /* now is a good time to fix up the labels for this insn: */
800eeca4
JW		 6053 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
6054 {
6055 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
6056 symbol_set_frag (lfix->sym, frag_now);
6057 }
f1bcba5b
JW		 6058 /* and fix up the tags also. */
6059 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
6060 {
6061 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
6062 symbol_set_frag (lfix->sym, frag_now);
6063 }
800eeca4
JW		 6064
6065 for (j = 0; j < md.slot[curr].num_fixups; ++j)
6066 {
6067 ifix = md.slot[curr].fixup + j;
5a080f89 6068 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
800eeca4
JW		 6069 &ifix->expr, ifix->is_pcrel, ifix->code);
6070 fix->tc_fix_data.opnd = ifix->opnd;
6071 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
6072 fix->fx_file = md.slot[curr].src_file;
6073 fix->fx_line = md.slot[curr].src_line;
6074 }
6075
6076 end_of_insn_group = md.slot[curr].end_of_insn_group;
6077
88be23ec
BS		 6078 if (end_of_insn_group)
6079 {
6080 md.group_idx = (md.group_idx + 1) % 3;
6081 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
6082 }
6083
542d6675 6084 /* clear slot: */
800eeca4
JW		 6085 ia64_free_opcode (md.slot[curr].idesc);
6086 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
6087 md.slot[curr].user_template = -1;
6088
6089 if (manual_bundling_off)
6090 {
6091 manual_bundling = 0;
6092 break;
6093 }
6094 curr = (curr + 1) % NUM_SLOTS;
6095 idesc = md.slot[curr].idesc;
6096 }
6097 if (manual_bundling)
6098 {
6099 if (md.num_slots_in_use > 0)
6100 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6101 "`%s' does not fit into %s template",
6102 idesc->name, ia64_templ_desc[template].name);
6103 else
6104 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6105 "Missing '}' at end of file");
6106 }
6107 know (md.num_slots_in_use < NUM_SLOTS);
6108
6109 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
6110 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
6111
44f5c83a
JW		 6112 number_to_chars_littleendian (f + 0, t0, 8);
6113 number_to_chars_littleendian (f + 8, t1, 8);
f5a30c2e
JW		 6114
6115 unwind.next_slot_number = (unsigned long) f + 16;
6116 unwind.next_slot_frag = frag_now;
800eeca4
JW		 6117}
6118
6119int
6120md_parse_option (c, arg)
6121 int c;
6122 char *arg;
6123{
7463c317 6124
800eeca4
JW		 6125 switch (c)
6126 {
c43c2cc5 6127 /* Switches from the Intel assembler. */
44f5c83a 6128 case 'm':
800eeca4
JW		 6129 if (strcmp (arg, "ilp64") == 0
6130 || strcmp (arg, "lp64") == 0
6131 || strcmp (arg, "p64") == 0)
6132 {
6133 md.flags |= EF_IA_64_ABI64;
6134 }
6135 else if (strcmp (arg, "ilp32") == 0)
6136 {
6137 md.flags &= ~EF_IA_64_ABI64;
6138 }
6139 else if (strcmp (arg, "le") == 0)
6140 {
6141 md.flags &= ~EF_IA_64_BE;
6142 }
6143 else if (strcmp (arg, "be") == 0)
6144 {
6145 md.flags |= EF_IA_64_BE;
6146 }
6147 else
6148 return 0;
6149 break;
6150
6151 case 'N':
6152 if (strcmp (arg, "so") == 0)
6153 {
542d6675 6154 /* Suppress signon message. */
800eeca4
JW		 6155 }
6156 else if (strcmp (arg, "pi") == 0)
6157 {
6158 /* Reject privileged instructions. FIXME */
6159 }
6160 else if (strcmp (arg, "us") == 0)
6161 {
6162 /* Allow union of signed and unsigned range. FIXME */
6163 }
6164 else if (strcmp (arg, "close_fcalls") == 0)
6165 {
6166 /* Do not resolve global function calls. */
6167 }
6168 else
6169 return 0;
6170 break;
6171
6172 case 'C':
6173 /* temp[="prefix"] Insert temporary labels into the object file
6174 symbol table prefixed by "prefix".
6175 Default prefix is ":temp:".
6176 */
6177 break;
6178
6179 case 'a':
800eeca4
JW		 6180 /* indirect=<tgt> Assume unannotated indirect branches behavior
6181 according to <tgt> --
6182 exit: branch out from the current context (default)
6183 labels: all labels in context may be branch targets
6184 */
85b40035
L		 6185 if (strncmp (arg, "indirect=", 9) != 0)
6186 return 0;
800eeca4
JW		 6187 break;
6188
6189 case 'x':
6190 /* -X conflicts with an ignored option, use -x instead */
6191 md.detect_dv = 1;
6192 if (!arg || strcmp (arg, "explicit") == 0)
542d6675
KH		 6193 {
6194 /* set default mode to explicit */
6195 md.default_explicit_mode = 1;
6196 break;
6197 }
800eeca4 6198 else if (strcmp (arg, "auto") == 0)
542d6675
KH		 6199 {
6200 md.default_explicit_mode = 0;
6201 }
800eeca4 6202 else if (strcmp (arg, "debug") == 0)
542d6675
KH		 6203 {
6204 md.debug_dv = 1;
6205 }
800eeca4 6206 else if (strcmp (arg, "debugx") == 0)
542d6675
KH		 6207 {
6208 md.default_explicit_mode = 1;
6209 md.debug_dv = 1;
6210 }
800eeca4 6211 else
542d6675
KH		 6212 {
6213 as_bad (_("Unrecognized option '-x%s'"), arg);
6214 }
800eeca4
JW		 6215 break;
6216
6217 case 'S':
6218 /* nops Print nops statistics. */
6219 break;
6220
c43c2cc5
JW		 6221 /* GNU specific switches for gcc. */
6222 case OPTION_MCONSTANT_GP:
6223 md.flags |= EF_IA_64_CONS_GP;
6224 break;
6225
6226 case OPTION_MAUTO_PIC:
6227 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
6228 break;
6229
800eeca4
JW		 6230 default:
6231 return 0;
6232 }
6233
6234 return 1;
6235}
6236
6237void
6238md_show_usage (stream)
6239 FILE *stream;
6240{
542d6675 6241 fputs (_("\
800eeca4 6242IA-64 options:\n\
44f5c83a
JW		 6243 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6244 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
800eeca4
JW		 6245 -x | -xexplicit turn on dependency violation checking (default)\n\
6246 -xauto automagically remove dependency violations\n\
6247 -xdebug debug dependency violation checker\n"),
6248 stream);
6249}
6250
44576e1f
RH		 6251/* Return true if TYPE fits in TEMPL at SLOT. */
6252
6253static int
800eeca4
JW		 6254match (int templ, int type, int slot)
6255{
6256 enum ia64_unit unit;
6257 int result;
6258
6259 unit = ia64_templ_desc[templ].exec_unit[slot];
6260 switch (type)
6261 {
6262 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
6263 case IA64_TYPE_A:
6264 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
6265 break;
6266 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
6267 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
6268 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
6269 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
6270 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
6271 default: result = 0; break;
6272 }
6273 return result;
6274}
6275
44576e1f
RH		 6276/* Add a bit of extra goodness if a nop of type F or B would fit
6277 in TEMPL at SLOT. */
6278
6279static inline int
6280extra_goodness (int templ, int slot)
6281{
ebeeafe6 6282 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
44576e1f 6283 return 2;
ebeeafe6 6284 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
44576e1f
RH		 6285 return 1;
6286 return 0;
6287}
6288
800eeca4
JW		 6289/* This function is called once, at assembler startup time. It sets
6290 up all the tables, etc. that the MD part of the assembler will need
6291 that can be determined before arguments are parsed. */
6292void
6293md_begin ()
6294{
44f5c83a 6295 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
800eeca4
JW		 6296 const char *err;
6297 char name[8];
6298
6299 md.auto_align = 1;
6300 md.explicit_mode = md.default_explicit_mode;
6301
6302 bfd_set_section_alignment (stdoutput, text_section, 4);
6303
44f5c83a 6304 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
800eeca4 6305 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
542d6675
KH		 6306 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
6307 &zero_address_frag);
800eeca4
JW		 6308
6309 pseudo_func[FUNC_GP_RELATIVE].u.sym =
542d6675
KH		 6310 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
6311 &zero_address_frag);
800eeca4
JW		 6312
6313 pseudo_func[FUNC_LT_RELATIVE].u.sym =
542d6675
KH		 6314 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
6315 &zero_address_frag);
800eeca4 6316
c67e42c9 6317 pseudo_func[FUNC_PC_RELATIVE].u.sym =
542d6675
KH		 6318 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
6319 &zero_address_frag);
c67e42c9 6320
800eeca4 6321 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
542d6675
KH		 6322 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
6323 &zero_address_frag);
800eeca4
JW		 6324
6325 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
542d6675
KH		 6326 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
6327 &zero_address_frag);
800eeca4
JW		 6328
6329 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
542d6675
KH		 6330 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
6331 &zero_address_frag);
800eeca4
JW		 6332
6333 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
542d6675
KH		 6334 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
6335 &zero_address_frag);
800eeca4
JW		 6336
6337 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
542d6675
KH		 6338 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
6339 &zero_address_frag);
800eeca4 6340
197865e8 6341 /* Compute the table of best templates. We compute goodness as a
44576e1f
RH		 6342 base 4 value, in which each match counts for 3, each F counts
6343 for 2, each B counts for 1. This should maximize the number of
6344 F and B nops in the chosen bundles, which is good because these
6345 pipelines are least likely to be overcommitted. */
800eeca4
JW		 6346 for (i = 0; i < IA64_NUM_TYPES; ++i)
6347 for (j = 0; j < IA64_NUM_TYPES; ++j)
6348 for (k = 0; k < IA64_NUM_TYPES; ++k)
6349 {
6350 best = 0;
6351 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
6352 {
6353 goodness = 0;
6354 if (match (t, i, 0))
6355 {
6356 if (match (t, j, 1))
6357 {
6358 if (match (t, k, 2))
44576e1f 6359 goodness = 3 + 3 + 3;
800eeca4 6360 else
44576e1f 6361 goodness = 3 + 3 + extra_goodness (t, 2);
800eeca4
JW		 6362 }
6363 else if (match (t, j, 2))
44576e1f 6364 goodness = 3 + 3 + extra_goodness (t, 1);
800eeca4 6365 else
44576e1f
RH		 6366 {
6367 goodness = 3;
6368 goodness += extra_goodness (t, 1);
6369 goodness += extra_goodness (t, 2);
6370 }
800eeca4
JW		 6371 }
6372 else if (match (t, i, 1))
6373 {
6374 if (match (t, j, 2))
44576e1f 6375 goodness = 3 + 3;
800eeca4 6376 else
44576e1f 6377 goodness = 3 + extra_goodness (t, 2);
800eeca4
JW		 6378 }
6379 else if (match (t, i, 2))
44576e1f 6380 goodness = 3 + extra_goodness (t, 1);
800eeca4
JW		 6381
6382 if (goodness > best)
6383 {
6384 best = goodness;
6385 best_template[i][j][k] = t;
6386 }
6387 }
6388 }
6389
6390 for (i = 0; i < NUM_SLOTS; ++i)
6391 md.slot[i].user_template = -1;
6392
6393 md.pseudo_hash = hash_new ();
6394 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
6395 {
6396 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
6397 (void *) (pseudo_opcode + i));
6398 if (err)
6399 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6400 pseudo_opcode[i].name, err);
6401 }
6402
6403 md.reg_hash = hash_new ();
6404 md.dynreg_hash = hash_new ();
6405 md.const_hash = hash_new ();
6406 md.entry_hash = hash_new ();
6407
542d6675 6408 /* general registers: */
800eeca4
JW		 6409
6410 total = 128;
6411 for (i = 0; i < total; ++i)
6412 {
6413 sprintf (name, "r%d", i - REG_GR);
6414 md.regsym[i] = declare_register (name, i);
6415 }
6416
542d6675 6417 /* floating point registers: */
800eeca4
JW		 6418 total += 128;
6419 for (; i < total; ++i)
6420 {
6421 sprintf (name, "f%d", i - REG_FR);
6422 md.regsym[i] = declare_register (name, i);
6423 }
6424
542d6675 6425 /* application registers: */
800eeca4
JW		 6426 total += 128;
6427 ar_base = i;
6428 for (; i < total; ++i)
6429 {
6430 sprintf (name, "ar%d", i - REG_AR);
6431 md.regsym[i] = declare_register (name, i);
6432 }
6433
542d6675 6434 /* control registers: */
800eeca4
JW		 6435 total += 128;
6436 cr_base = i;
6437 for (; i < total; ++i)
6438 {
6439 sprintf (name, "cr%d", i - REG_CR);
6440 md.regsym[i] = declare_register (name, i);
6441 }
6442
542d6675 6443 /* predicate registers: */
800eeca4
JW		 6444 total += 64;
6445 for (; i < total; ++i)
6446 {
6447 sprintf (name, "p%d", i - REG_P);
6448 md.regsym[i] = declare_register (name, i);
6449 }
6450
542d6675 6451 /* branch registers: */
800eeca4
JW		 6452 total += 8;
6453 for (; i < total; ++i)
6454 {
6455 sprintf (name, "b%d", i - REG_BR);
6456 md.regsym[i] = declare_register (name, i);
6457 }
6458
6459 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
6460 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
6461 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
6462 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
6463 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
6464 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
6465 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
6466
6467 for (i = 0; i < NELEMS (indirect_reg); ++i)
6468 {
6469 regnum = indirect_reg[i].regnum;
6470 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
6471 }
6472
542d6675 6473 /* define synonyms for application registers: */
800eeca4
JW		 6474 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
6475 md.regsym[i] = declare_register (ar[i - REG_AR].name,
6476 REG_AR + ar[i - REG_AR].regnum);
6477
542d6675 6478 /* define synonyms for control registers: */
800eeca4
JW		 6479 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
6480 md.regsym[i] = declare_register (cr[i - REG_CR].name,
6481 REG_CR + cr[i - REG_CR].regnum);
6482
6483 declare_register ("gp", REG_GR + 1);
6484 declare_register ("sp", REG_GR + 12);
6485 declare_register ("rp", REG_BR + 0);
6486
542d6675 6487 /* pseudo-registers used to specify unwind info: */
e0c9811a
JW		 6488 declare_register ("psp", REG_PSP);
6489
800eeca4
JW		 6490 declare_register_set ("ret", 4, REG_GR + 8);
6491 declare_register_set ("farg", 8, REG_FR + 8);
6492 declare_register_set ("fret", 8, REG_FR + 8);
6493
6494 for (i = 0; i < NELEMS (const_bits); ++i)
6495 {
6496 err = hash_insert (md.const_hash, const_bits[i].name,
6497 (PTR) (const_bits + i));
6498 if (err)
6499 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6500 name, err);
6501 }
6502
44f5c83a
JW		 6503 /* Set the architecture and machine depending on defaults and command line
6504 options. */
6505 if (md.flags & EF_IA_64_ABI64)
6506 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
6507 else
6508 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
6509
6510 if (! ok)
6511 as_warn (_("Could not set architecture and machine"));
800eeca4 6512
557debba
JW		 6513 /* Set the pointer size and pointer shift size depending on md.flags */
6514
6515 if (md.flags & EF_IA_64_ABI64)
6516 {
6517 md.pointer_size = 8; /* pointers are 8 bytes */
6518 md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */
6519 }
6520 else
6521 {
6522 md.pointer_size = 4; /* pointers are 4 bytes */
6523 md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */
6524 }
6525
800eeca4
JW		 6526 md.mem_offset.hint = 0;
6527 md.path = 0;
6528 md.maxpaths = 0;
6529 md.entry_labels = NULL;
6530}
6531
44f5c83a
JW		 6532/* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6533 because that is called after md_parse_option which is where we do the
6534 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6535 default endianness. */
6536
6537void
6538ia64_init (argc, argv)
2434f565
JW		 6539 int argc ATTRIBUTE_UNUSED;
6540 char **argv ATTRIBUTE_UNUSED;
44f5c83a
JW		 6541{
6542 md.flags = EF_IA_64_ABI64;
6543 if (TARGET_BYTES_BIG_ENDIAN)
6544 md.flags |= EF_IA_64_BE;
6545}
6546
6547/* Return a string for the target object file format. */
6548
6549const char *
6550ia64_target_format ()
6551{
6552 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6553 {
72a76794
JW		 6554 if (md.flags & EF_IA_64_BE)
6555 {
6556 if (md.flags & EF_IA_64_ABI64)
7463c317
TW		 6557#ifdef TE_AIX50
6558 return "elf64-ia64-aix-big";
6559#else
72a76794 6560 return "elf64-ia64-big";
7463c317 6561#endif
72a76794 6562 else
7463c317
TW		 6563#ifdef TE_AIX50
6564 return "elf32-ia64-aix-big";
6565#else
72a76794 6566 return "elf32-ia64-big";
7463c317 6567#endif
72a76794 6568 }
44f5c83a 6569 else
72a76794
JW		 6570 {
6571 if (md.flags & EF_IA_64_ABI64)
7463c317
TW		 6572#ifdef TE_AIX50
6573 return "elf64-ia64-aix-little";
6574#else
72a76794 6575 return "elf64-ia64-little";
7463c317 6576#endif
72a76794 6577 else
7463c317
TW		 6578#ifdef TE_AIX50
6579 return "elf32-ia64-aix-little";
6580#else
72a76794 6581 return "elf32-ia64-little";
7463c317 6582#endif
72a76794 6583 }
44f5c83a
JW		 6584 }
6585 else
6586 return "unknown-format";
6587}
6588
800eeca4
JW		 6589void
6590ia64_end_of_source ()
6591{
542d6675 6592 /* terminate insn group upon reaching end of file: */
800eeca4
JW		 6593 insn_group_break (1, 0, 0);
6594
542d6675 6595 /* emits slots we haven't written yet: */
800eeca4
JW		 6596 ia64_flush_insns ();
6597
6598 bfd_set_private_flags (stdoutput, md.flags);
6599
800eeca4
JW		 6600 md.mem_offset.hint = 0;
6601}
6602
6603void
6604ia64_start_line ()
6605{
f1bcba5b
JW		 6606 if (md.qp.X_op == O_register)
6607 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW		 6608 md.qp.X_op = O_absent;
6609
6610 if (ignore_input ())
6611 return;
6612
6613 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6614 {
6615 if (md.detect_dv && !md.explicit_mode)
542d6675 6616 as_warn (_("Explicit stops are ignored in auto mode"));
800eeca4 6617 else
542d6675 6618 insn_group_break (1, 0, 0);
800eeca4
JW		 6619 }
6620}
6621
f1bcba5b
JW		 6622/* This is a hook for ia64_frob_label, so that it can distinguish tags from
6623 labels. */
6624static int defining_tag = 0;
6625
800eeca4
JW		 6626int
6627ia64_unrecognized_line (ch)
6628 int ch;
6629{
6630 switch (ch)
6631 {
6632 case '(':
6633 expression (&md.qp);
6634 if (*input_line_pointer++ != ')')
6635 {
6636 as_bad ("Expected ')'");
6637 return 0;
6638 }
6639 if (md.qp.X_op != O_register)
6640 {
6641 as_bad ("Qualifying predicate expected");
6642 return 0;
6643 }
6644 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6645 {
6646 as_bad ("Predicate register expected");
6647 return 0;
6648 }
6649 return 1;
6650
6651 case '{':
6652 if (md.manual_bundling)
6653 as_warn ("Found '{' when manual bundling is already turned on");
6654 else
6655 CURR_SLOT.manual_bundling_on = 1;
6656 md.manual_bundling = 1;
6657
542d6675
KH		 6658 /* Bundling is only acceptable in explicit mode
6659 or when in default automatic mode. */
800eeca4 6660 if (md.detect_dv && !md.explicit_mode)
542d6675
KH		 6661 {
6662 if (!md.mode_explicitly_set
6663 && !md.default_explicit_mode)
6664 dot_dv_mode ('E');
6665 else
6666 as_warn (_("Found '{' after explicit switch to automatic mode"));
6667 }
800eeca4
JW		 6668 return 1;
6669
6670 case '}':
6671 if (!md.manual_bundling)
6672 as_warn ("Found '}' when manual bundling is off");
6673 else
6674 PREV_SLOT.manual_bundling_off = 1;
6675 md.manual_bundling = 0;
6676
6677 /* switch back to automatic mode, if applicable */
197865e8 6678 if (md.detect_dv
542d6675
KH		 6679 && md.explicit_mode
6680 && !md.mode_explicitly_set
6681 && !md.default_explicit_mode)
6682 dot_dv_mode ('A');
800eeca4
JW		 6683
6684 /* Allow '{' to follow on the same line. We also allow ";;", but that
6685 happens automatically because ';' is an end of line marker. */
6686 SKIP_WHITESPACE ();
6687 if (input_line_pointer[0] == '{')
6688 {
6689 input_line_pointer++;
6690 return ia64_unrecognized_line ('{');
6691 }
6692
6693 demand_empty_rest_of_line ();
6694 return 1;
6695
f1bcba5b
JW		 6696 case '[':
6697 {
6698 char *s;
6699 char c;
6700 symbolS *tag;
4d5a53ff 6701 int temp;
f1bcba5b
JW		 6702
6703 if (md.qp.X_op == O_register)
6704 {
6705 as_bad ("Tag must come before qualifying predicate.");
6706 return 0;
6707 }
4d5a53ff
JW		 6708
6709 /* This implements just enough of read_a_source_file in read.c to
6710 recognize labels. */
6711 if (is_name_beginner (*input_line_pointer))
6712 {
6713 s = input_line_pointer;
6714 c = get_symbol_end ();
6715 }
6716 else if (LOCAL_LABELS_FB
6717 && isdigit ((unsigned char) *input_line_pointer))
6718 {
6719 temp = 0;
6720 while (isdigit ((unsigned char) *input_line_pointer))
6721 temp = (temp * 10) + *input_line_pointer++ - '0';
6722 fb_label_instance_inc (temp);
6723 s = fb_label_name (temp, 0);
6724 c = *input_line_pointer;
6725 }
6726 else
6727 {
6728 s = NULL;
6729 c = '\0';
6730 }
f1bcba5b
JW		 6731 if (c != ':')
6732 {
6733 /* Put ':' back for error messages' sake. */
6734 *input_line_pointer++ = ':';
6735 as_bad ("Expected ':'");
6736 return 0;
6737 }
4d5a53ff 6738
f1bcba5b
JW		 6739 defining_tag = 1;
6740 tag = colon (s);
6741 defining_tag = 0;
6742 /* Put ':' back for error messages' sake. */
6743 *input_line_pointer++ = ':';
6744 if (*input_line_pointer++ != ']')
6745 {
6746 as_bad ("Expected ']'");
6747 return 0;
6748 }
6749 if (! tag)
6750 {
6751 as_bad ("Tag name expected");
6752 return 0;
6753 }
6754 return 1;
6755 }
6756
800eeca4
JW		 6757 default:
6758 break;
6759 }
542d6675
KH		 6760
6761 /* Not a valid line. */
6762 return 0;
800eeca4
JW		 6763}
6764
6765void
6766ia64_frob_label (sym)
6767 struct symbol *sym;
6768{
6769 struct label_fix *fix;
6770
f1bcba5b
JW		 6771 /* Tags need special handling since they are not bundle breaks like
6772 labels. */
6773 if (defining_tag)
6774 {
6775 fix = obstack_alloc (&notes, sizeof (*fix));
6776 fix->sym = sym;
6777 fix->next = CURR_SLOT.tag_fixups;
6778 CURR_SLOT.tag_fixups = fix;
6779
6780 return;
6781 }
6782
800eeca4
JW		 6783 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6784 {
6785 md.last_text_seg = now_seg;
6786 fix = obstack_alloc (&notes, sizeof (*fix));
6787 fix->sym = sym;
6788 fix->next = CURR_SLOT.label_fixups;
6789 CURR_SLOT.label_fixups = fix;
6790
542d6675 6791 /* Keep track of how many code entry points we've seen. */
800eeca4 6792 if (md.path == md.maxpaths)
542d6675
KH		 6793 {
6794 md.maxpaths += 20;
6795 md.entry_labels = (const char **)
6796 xrealloc ((void *) md.entry_labels,
6797 md.maxpaths * sizeof (char *));
6798 }
800eeca4
JW		 6799 md.entry_labels[md.path++] = S_GET_NAME (sym);
6800 }
6801}
6802
6803void
6804ia64_flush_pending_output ()
6805{
4d5a53ff
JW		 6806 if (!md.keep_pending_output
6807 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
800eeca4
JW		 6808 {
6809 /* ??? This causes many unnecessary stop bits to be emitted.
6810 Unfortunately, it isn't clear if it is safe to remove this. */
6811 insn_group_break (1, 0, 0);
6812 ia64_flush_insns ();
6813 }
6814}
6815
6816/* Do ia64-specific expression optimization. All that's done here is
6817 to transform index expressions that are either due to the indexing
6818 of rotating registers or due to the indexing of indirect register
6819 sets. */
6820int
6821ia64_optimize_expr (l, op, r)
6822 expressionS *l;
6823 operatorT op;
6824 expressionS *r;
6825{
6826 unsigned num_regs;
6827
6828 if (op == O_index)
6829 {
6830 if (l->X_op == O_register && r->X_op == O_constant)
6831 {
6832 num_regs = (l->X_add_number >> 16);
6833 if ((unsigned) r->X_add_number >= num_regs)
6834 {
6835 if (!num_regs)
6836 as_bad ("No current frame");
6837 else
6838 as_bad ("Index out of range 0..%u", num_regs - 1);
6839 r->X_add_number = 0;
6840 }
6841 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6842 return 1;
6843 }
6844 else if (l->X_op == O_register && r->X_op == O_register)
6845 {
6846 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6847 || l->X_add_number == IND_MEM)
6848 {
6849 as_bad ("Indirect register set name expected");
6850 l->X_add_number = IND_CPUID;
6851 }
6852 l->X_op = O_index;
6853 l->X_op_symbol = md.regsym[l->X_add_number];
6854 l->X_add_number = r->X_add_number;
6855 return 1;
6856 }
6857 }
6858 return 0;
6859}
6860
6861int
6862ia64_parse_name (name, e)
6863 char *name;
6864 expressionS *e;
6865{
6866 struct const_desc *cdesc;
6867 struct dynreg *dr = 0;
6868 unsigned int regnum;
6869 struct symbol *sym;
6870 char *end;
6871
542d6675 6872 /* first see if NAME is a known register name: */
800eeca4
JW		 6873 sym = hash_find (md.reg_hash, name);
6874 if (sym)
6875 {
6876 e->X_op = O_register;
6877 e->X_add_number = S_GET_VALUE (sym);
6878 return 1;
6879 }
6880
6881 cdesc = hash_find (md.const_hash, name);
6882 if (cdesc)
6883 {
6884 e->X_op = O_constant;
6885 e->X_add_number = cdesc->value;
6886 return 1;
6887 }
6888
542d6675 6889 /* check for inN, locN, or outN: */
800eeca4
JW		 6890 switch (name[0])
6891 {
6892 case 'i':
6893 if (name[1] == 'n' && isdigit (name[2]))
6894 {
6895 dr = &md.in;
6896 name += 2;
6897 }
6898 break;
6899
6900 case 'l':
6901 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6902 {
6903 dr = &md.loc;
6904 name += 3;
6905 }
6906 break;
6907
6908 case 'o':
6909 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6910 {
6911 dr = &md.out;
6912 name += 3;
6913 }
6914 break;
6915
6916 default:
6917 break;
6918 }
6919
6920 if (dr)
6921 {
542d6675 6922 /* The name is inN, locN, or outN; parse the register number. */
800eeca4
JW		 6923 regnum = strtoul (name, &end, 10);
6924 if (end > name && *end == '\0')
6925 {
6926 if ((unsigned) regnum >= dr->num_regs)
6927 {
6928 if (!dr->num_regs)
6929 as_bad ("No current frame");
6930 else
542d6675
KH		 6931 as_bad ("Register number out of range 0..%u",
6932 dr->num_regs - 1);
800eeca4
JW		 6933 regnum = 0;
6934 }
6935 e->X_op = O_register;
6936 e->X_add_number = dr->base + regnum;
6937 return 1;
6938 }
6939 }
6940
6941 if ((dr = hash_find (md.dynreg_hash, name)))
6942 {
6943 /* We've got ourselves the name of a rotating register set.
542d6675
KH		 6944 Store the base register number in the low 16 bits of
6945 X_add_number and the size of the register set in the top 16
6946 bits. */
800eeca4
JW		 6947 e->X_op = O_register;
6948 e->X_add_number = dr->base | (dr->num_regs << 16);
6949 return 1;
6950 }
6951 return 0;
6952}
6953
6954/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6955
6956char *
6957ia64_canonicalize_symbol_name (name)
6958 char *name;
6959{
542d6675
KH		 6960 size_t len = strlen (name);
6961 if (len > 1 && name[len - 1] == '#')
6962 name[len - 1] = '\0';
800eeca4
JW		 6963 return name;
6964}
6965
3e37788f
JW		 6966/* Return true if idesc is a conditional branch instruction. This excludes
6967 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
6968 because they always read/write resources regardless of the value of the
6969 qualifying predicate. br.ia must always use p0, and hence is always
6970 taken. Thus this function returns true for branches which can fall
6971 through, and which use no resources if they do fall through. */
1deb8127 6972
800eeca4
JW		 6973static int
6974is_conditional_branch (idesc)
542d6675 6975 struct ia64_opcode *idesc;
800eeca4 6976{
1deb8127 6977 /* br is a conditional branch. Everything that starts with br. except
3e37788f
JW		 6978 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
6979 Everything that starts with brl is a conditional branch. */
1deb8127
JW		 6980 return (idesc->name[0] == 'b' && idesc->name[1] == 'r'
6981 && (idesc->name[2] == '\0'
3e37788f
JW		 6982 || (idesc->name[2] == '.' && idesc->name[3] != 'i'
6983 && idesc->name[3] != 'c' && idesc->name[3] != 'w')
6984 || idesc->name[2] == 'l'
6985 /* br.cond, br.call, br.clr */
6986 || (idesc->name[2] == '.' && idesc->name[3] == 'c'
6987 && (idesc->name[4] == 'a' || idesc->name[4] == 'o'
6988 || (idesc->name[4] == 'l' && idesc->name[5] == 'r')))));
800eeca4
JW		 6989}
6990
6991/* Return whether the given opcode is a taken branch. If there's any doubt,
542d6675
KH		 6992 returns zero. */
6993
800eeca4
JW		 6994static int
6995is_taken_branch (idesc)
542d6675 6996 struct ia64_opcode *idesc;
800eeca4
JW		 6997{
6998 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
542d6675 6999 || strncmp (idesc->name, "br.ia", 5) == 0);
800eeca4
JW		 7000}
7001
7002/* Return whether the given opcode is an interruption or rfi. If there's any
542d6675
KH		 7003 doubt, returns zero. */
7004
800eeca4
JW		 7005static int
7006is_interruption_or_rfi (idesc)
542d6675 7007 struct ia64_opcode *idesc;
800eeca4
JW		 7008{
7009 if (strcmp (idesc->name, "rfi") == 0)
7010 return 1;
7011 return 0;
7012}
7013
7014/* Returns the index of the given dependency in the opcode's list of chks, or
7015 -1 if there is no dependency. */
542d6675 7016
800eeca4
JW		 7017static int
7018depends_on (depind, idesc)
542d6675
KH		 7019 int depind;
7020 struct ia64_opcode *idesc;
800eeca4
JW		 7021{
7022 int i;
7023 const struct ia64_opcode_dependency *dep = idesc->dependencies;
542d6675 7024 for (i = 0; i < dep->nchks; i++)
800eeca4 7025 {
542d6675
KH		 7026 if (depind == DEP (dep->chks[i]))
7027 return i;
800eeca4
JW		 7028 }
7029 return -1;
7030}
7031
7032/* Determine a set of specific resources used for a particular resource
7033 class. Returns the number of specific resources identified For those
7034 cases which are not determinable statically, the resource returned is
197865e8 7035 marked nonspecific.
800eeca4
JW		 7036
7037 Meanings of value in 'NOTE':
7038 1) only read/write when the register number is explicitly encoded in the
7039 insn.
7040 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
197865e8 7041 accesses CFM when qualifying predicate is in the rotating region.
800eeca4
JW		 7042 3) general register value is used to specify an indirect register; not
7043 determinable statically.
7044 4) only read the given resource when bits 7:0 of the indirect index
7045 register value does not match the register number of the resource; not
7046 determinable statically.
7047 5) all rules are implementation specific.
7048 6) only when both the index specified by the reader and the index specified
7049 by the writer have the same value in bits 63:61; not determinable
197865e8 7050 statically.
800eeca4 7051 7) only access the specified resource when the corresponding mask bit is
197865e8 7052 set
800eeca4
JW		 7053 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7054 only read when these insns reference FR2-31
7055 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7056 written when these insns write FR32-127
7057 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7058 instruction
7059 11) The target predicates are written independently of PR[qp], but source
7060 registers are only read if PR[qp] is true. Since the state of PR[qp]
7061 cannot statically be determined, all source registers are marked used.
7062 12) This insn only reads the specified predicate register when that
7063 register is the PR[qp].
7064 13) This reference to ld-c only applies to teh GR whose value is loaded
197865e8 7065 with data returned from memory, not the post-incremented address register.
800eeca4
JW		 7066 14) The RSE resource includes the implementation-specific RSE internal
7067 state resources. At least one (and possibly more) of these resources are
7068 read by each instruction listed in IC:rse-readers. At least one (and
7069 possibly more) of these resources are written by each insn listed in
197865e8 7070 IC:rse-writers.
800eeca4 7071 15+16) Represents reserved instructions, which the assembler does not
197865e8 7072 generate.
800eeca4
JW		 7073
7074 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7075 this code; there are no dependency violations based on memory access.
800eeca4
JW		 7076*/
7077
7078#define MAX_SPECS 256
7079#define DV_CHK 1
7080#define DV_REG 0
7081
7082static int
7083specify_resource (dep, idesc, type, specs, note, path)
542d6675
KH		 7084 const struct ia64_dependency *dep;
7085 struct ia64_opcode *idesc;
7086 int type; /* is this a DV chk or a DV reg? */
7087 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
7088 int note; /* resource note for this insn's usage */
7089 int path; /* which execution path to examine */
800eeca4
JW		 7090{
7091 int count = 0;
7092 int i;
7093 int rsrc_write = 0;
7094 struct rsrc tmpl;
197865e8 7095
800eeca4
JW		 7096 if (dep->mode == IA64_DV_WAW
7097 || (dep->mode == IA64_DV_RAW && type == DV_REG)
7098 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
7099 rsrc_write = 1;
7100
7101 /* template for any resources we identify */
7102 tmpl.dependency = dep;
7103 tmpl.note = note;
7104 tmpl.insn_srlz = tmpl.data_srlz = 0;
7105 tmpl.qp_regno = CURR_SLOT.qp_regno;
7106 tmpl.link_to_qp_branch = 1;
7107 tmpl.mem_offset.hint = 0;
7108 tmpl.specific = 1;
7109 tmpl.index = 0;
7484b8e6 7110 tmpl.cmp_type = CMP_NONE;
800eeca4
JW		 7111
7112#define UNHANDLED \
7113as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7114dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7115#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7116
7117 /* we don't need to track these */
7118 if (dep->semantics == IA64_DVS_NONE)
7119 return 0;
7120
7121 switch (dep->specifier)
7122 {
7123 case IA64_RS_AR_K:
7124 if (note == 1)
542d6675
KH		 7125 {
7126 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7127 {
7128 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7129 if (regno >= 0 && regno <= 7)
7130 {
7131 specs[count] = tmpl;
7132 specs[count++].index = regno;
7133 }
7134 }
7135 }
800eeca4 7136 else if (note == 0)
542d6675
KH		 7137 {
7138 for (i = 0; i < 8; i++)
7139 {
7140 specs[count] = tmpl;
7141 specs[count++].index = i;
7142 }
7143 }
800eeca4 7144 else
542d6675
KH		 7145 {
7146 UNHANDLED;
7147 }
800eeca4
JW		 7148 break;
7149
7150 case IA64_RS_AR_UNAT:
7151 /* This is a mov =AR or mov AR= instruction. */
7152 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7153 {
7154 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7155 if (regno == AR_UNAT)
7156 {
7157 specs[count++] = tmpl;
7158 }
7159 }
7160 else
7161 {
7162 /* This is a spill/fill, or other instruction that modifies the
7163 unat register. */
7164
7165 /* Unless we can determine the specific bits used, mark the whole
7166 thing; bits 8:3 of the memory address indicate the bit used in
7167 UNAT. The .mem.offset hint may be used to eliminate a small
7168 subset of conflicts. */
7169 specs[count] = tmpl;
7170 if (md.mem_offset.hint)
7171 {
542d6675
KH		 7172 if (md.debug_dv)
7173 fprintf (stderr, " Using hint for spill/fill\n");
7174 /* The index isn't actually used, just set it to something
7175 approximating the bit index. */
800eeca4
JW		 7176 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
7177 specs[count].mem_offset.hint = 1;
7178 specs[count].mem_offset.offset = md.mem_offset.offset;
7179 specs[count++].mem_offset.base = md.mem_offset.base;
7180 }
7181 else
7182 {
7183 specs[count++].specific = 0;
7184 }
7185 }
7186 break;
7187
7188 case IA64_RS_AR:
7189 if (note == 1)
542d6675
KH		 7190 {
7191 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7192 {
7193 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7194 if ((regno >= 8 && regno <= 15)
7195 || (regno >= 20 && regno <= 23)
7196 || (regno >= 31 && regno <= 39)
7197 || (regno >= 41 && regno <= 47)
7198 || (regno >= 67 && regno <= 111))
7199 {
7200 specs[count] = tmpl;
7201 specs[count++].index = regno;
7202 }
7203 }
7204 }
800eeca4 7205 else
542d6675
KH		 7206 {
7207 UNHANDLED;
7208 }
800eeca4
JW		 7209 break;
7210
7211 case IA64_RS_ARb:
7212 if (note == 1)
542d6675
KH		 7213 {
7214 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7215 {
7216 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7217 if ((regno >= 48 && regno <= 63)
7218 || (regno >= 112 && regno <= 127))
7219 {
7220 specs[count] = tmpl;
7221 specs[count++].index = regno;
7222 }
7223 }
7224 }
800eeca4 7225 else if (note == 0)
542d6675
KH		 7226 {
7227 for (i = 48; i < 64; i++)
7228 {
7229 specs[count] = tmpl;
7230 specs[count++].index = i;
7231 }
7232 for (i = 112; i < 128; i++)
7233 {
7234 specs[count] = tmpl;
7235 specs[count++].index = i;
7236 }
7237 }
197865e8 7238 else
542d6675
KH		 7239 {
7240 UNHANDLED;
7241 }
800eeca4
JW		 7242 break;
7243
7244 case IA64_RS_BR:
7245 if (note != 1)
542d6675
KH		 7246 {
7247 UNHANDLED;
7248 }
800eeca4 7249 else
542d6675
KH		 7250 {
7251 if (rsrc_write)
7252 {
7253 for (i = 0; i < idesc->num_outputs; i++)
7254 if (idesc->operands[i] == IA64_OPND_B1
7255 || idesc->operands[i] == IA64_OPND_B2)
7256 {
7257 specs[count] = tmpl;
7258 specs[count++].index =
7259 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7260 }
7261 }
7262 else
7263 {
7264 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
7265 if (idesc->operands[i] == IA64_OPND_B1
7266 || idesc->operands[i] == IA64_OPND_B2)
7267 {
7268 specs[count] = tmpl;
7269 specs[count++].index =
7270 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7271 }
7272 }
7273 }
800eeca4
JW		 7274 break;
7275
7276 case IA64_RS_CPUID: /* four or more registers */
7277 if (note == 3)
542d6675
KH		 7278 {
7279 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
7280 {
7281 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7282 if (regno >= 0 && regno < NELEMS (gr_values)
7283 && KNOWN (regno))
7284 {
7285 specs[count] = tmpl;
7286 specs[count++].index = gr_values[regno].value & 0xFF;
7287 }
7288 else
7289 {
7290 specs[count] = tmpl;
7291 specs[count++].specific = 0;
7292 }
7293 }
7294 }
800eeca4 7295 else
542d6675
KH		 7296 {
7297 UNHANDLED;
7298 }
800eeca4
JW		 7299 break;
7300
7301 case IA64_RS_DBR: /* four or more registers */
7302 if (note == 3)
542d6675
KH		 7303 {
7304 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
7305 {
7306 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7307 if (regno >= 0 && regno < NELEMS (gr_values)
7308 && KNOWN (regno))
7309 {
7310 specs[count] = tmpl;
7311 specs[count++].index = gr_values[regno].value & 0xFF;
7312 }
7313 else
7314 {
7315 specs[count] = tmpl;
7316 specs[count++].specific = 0;
7317 }
7318 }
7319 }
800eeca4 7320 else if (note == 0 && !rsrc_write)
542d6675
KH		 7321 {
7322 specs[count] = tmpl;
7323 specs[count++].specific = 0;
7324 }
800eeca4 7325 else
542d6675
KH		 7326 {
7327 UNHANDLED;
7328 }
800eeca4
JW		 7329 break;
7330
7331 case IA64_RS_IBR: /* four or more registers */
7332 if (note == 3)
542d6675
KH		 7333 {
7334 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
7335 {
7336 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7337 if (regno >= 0 && regno < NELEMS (gr_values)
7338 && KNOWN (regno))
7339 {
7340 specs[count] = tmpl;
7341 specs[count++].index = gr_values[regno].value & 0xFF;
7342 }
7343 else
7344 {
7345 specs[count] = tmpl;
7346 specs[count++].specific = 0;
7347 }
7348 }
7349 }
800eeca4 7350 else
542d6675
KH		 7351 {
7352 UNHANDLED;
7353 }
800eeca4
JW		 7354 break;
7355
7356 case IA64_RS_MSR:
7357 if (note == 5)
7358 {
7359 /* These are implementation specific. Force all references to
7360 conflict with all other references. */
7361 specs[count] = tmpl;
7362 specs[count++].specific = 0;
7363 }
7364 else
7365 {
7366 UNHANDLED;
7367 }
7368 break;
7369
7370 case IA64_RS_PKR: /* 16 or more registers */
7371 if (note == 3 || note == 4)
542d6675
KH		 7372 {
7373 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
7374 {
7375 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7376 if (regno >= 0 && regno < NELEMS (gr_values)
7377 && KNOWN (regno))
7378 {
7379 if (note == 3)
7380 {
7381 specs[count] = tmpl;
7382 specs[count++].index = gr_values[regno].value & 0xFF;
7383 }
7384 else
7385 for (i = 0; i < NELEMS (gr_values); i++)
7386 {
7387 /* Uses all registers *except* the one in R3. */
2434f565 7388 if ((unsigned)i != (gr_values[regno].value & 0xFF))
542d6675
KH		 7389 {
7390 specs[count] = tmpl;
7391 specs[count++].index = i;
7392 }
7393 }
7394 }
7395 else
7396 {
7397 specs[count] = tmpl;
7398 specs[count++].specific = 0;
7399 }
7400 }
7401 }
7402 else if (note == 0)
7403 {
7404 /* probe et al. */
7405 specs[count] = tmpl;
7406 specs[count++].specific = 0;
7407 }
7408 break;
7409
7410 case IA64_RS_PMC: /* four or more registers */
7411 if (note == 3)
7412 {
7413 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
7414 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
7415
7416 {
7417 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
7418 ? 1 : !rsrc_write);
7419 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
7420 if (regno >= 0 && regno < NELEMS (gr_values)
7421 && KNOWN (regno))
7422 {
7423 specs[count] = tmpl;
7424 specs[count++].index = gr_values[regno].value & 0xFF;
7425 }
7426 else
7427 {
7428 specs[count] = tmpl;
7429 specs[count++].specific = 0;
7430 }
7431 }
7432 }
7433 else
7434 {
7435 UNHANDLED;
7436 }
800eeca4
JW		 7437 break;
7438
7439 case IA64_RS_PMD: /* four or more registers */
7440 if (note == 3)
542d6675
KH		 7441 {
7442 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
7443 {
7444 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7445 if (regno >= 0 && regno < NELEMS (gr_values)
7446 && KNOWN (regno))
7447 {
7448 specs[count] = tmpl;
7449 specs[count++].index = gr_values[regno].value & 0xFF;
7450 }
7451 else
7452 {
7453 specs[count] = tmpl;
7454 specs[count++].specific = 0;
7455 }
7456 }
7457 }
800eeca4 7458 else
542d6675
KH		 7459 {
7460 UNHANDLED;
7461 }
800eeca4
JW		 7462 break;
7463
7464 case IA64_RS_RR: /* eight registers */
7465 if (note == 6)
542d6675
KH		 7466 {
7467 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
7468 {
7469 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7470 if (regno >= 0 && regno < NELEMS (gr_values)
7471 && KNOWN (regno))
7472 {
7473 specs[count] = tmpl;
7474 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
7475 }
7476 else
7477 {
7478 specs[count] = tmpl;
7479 specs[count++].specific = 0;
7480 }
7481 }
7482 }
800eeca4 7483 else if (note == 0 && !rsrc_write)
542d6675
KH		 7484 {
7485 specs[count] = tmpl;
7486 specs[count++].specific = 0;
7487 }
197865e8 7488 else
542d6675
KH		 7489 {
7490 UNHANDLED;
7491 }
800eeca4
JW		 7492 break;
7493
7494 case IA64_RS_CR_IRR:
197865e8 7495 if (note == 0)
542d6675
KH		 7496 {
7497 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7498 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
7499 if (rsrc_write
7500 && idesc->operands[1] == IA64_OPND_CR3
7501 && regno == CR_IVR)
7502 {
7503 for (i = 0; i < 4; i++)
7504 {
7505 specs[count] = tmpl;
7506 specs[count++].index = CR_IRR0 + i;
7507 }
7508 }
7509 }
800eeca4 7510 else if (note == 1)
542d6675
KH		 7511 {
7512 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7513 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7514 && regno >= CR_IRR0
7515 && regno <= CR_IRR3)
7516 {
7517 specs[count] = tmpl;
7518 specs[count++].index = regno;
7519 }
7520 }
800eeca4 7521 else
542d6675
KH		 7522 {
7523 UNHANDLED;
7524 }
800eeca4
JW		 7525 break;
7526
7527 case IA64_RS_CR_LRR:
7528 if (note != 1)
542d6675
KH		 7529 {
7530 UNHANDLED;
7531 }
197865e8 7532 else
542d6675
KH		 7533 {
7534 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7535 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7536 && (regno == CR_LRR0 || regno == CR_LRR1))
7537 {
7538 specs[count] = tmpl;
7539 specs[count++].index = regno;
7540 }
7541 }
800eeca4
JW		 7542 break;
7543
7544 case IA64_RS_CR:
7545 if (note == 1)
542d6675
KH		 7546 {
7547 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7548 {
7549 specs[count] = tmpl;
7550 specs[count++].index =
7551 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7552 }
7553 }
800eeca4 7554 else
542d6675
KH		 7555 {
7556 UNHANDLED;
7557 }
800eeca4
JW		 7558 break;
7559
7560 case IA64_RS_FR:
7561 case IA64_RS_FRb:
7562 if (note != 1)
542d6675
KH		 7563 {
7564 UNHANDLED;
7565 }
800eeca4 7566 else if (rsrc_write)
542d6675
KH		 7567 {
7568 if (dep->specifier == IA64_RS_FRb
7569 && idesc->operands[0] == IA64_OPND_F1)
7570 {
7571 specs[count] = tmpl;
7572 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
7573 }
7574 }
800eeca4 7575 else
542d6675
KH		 7576 {
7577 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7578 {
7579 if (idesc->operands[i] == IA64_OPND_F2
7580 || idesc->operands[i] == IA64_OPND_F3
7581 || idesc->operands[i] == IA64_OPND_F4)
7582 {
7583 specs[count] = tmpl;
7584 specs[count++].index =
7585 CURR_SLOT.opnd[i].X_add_number - REG_FR;
7586 }
7587 }
7588 }
800eeca4
JW		 7589 break;
7590
7591 case IA64_RS_GR:
7592 if (note == 13)
542d6675
KH		 7593 {
7594 /* This reference applies only to the GR whose value is loaded with
7595 data returned from memory. */
7596 specs[count] = tmpl;
7597 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7598 }
800eeca4 7599 else if (note == 1)
542d6675
KH		 7600 {
7601 if (rsrc_write)
7602 {
7603 for (i = 0; i < idesc->num_outputs; i++)
50b81f19
JW		 7604 if (idesc->operands[i] == IA64_OPND_R1
7605 || idesc->operands[i] == IA64_OPND_R2
7606 || idesc->operands[i] == IA64_OPND_R3)
7607 {
7608 specs[count] = tmpl;
197865e8 7609 specs[count++].index =
50b81f19
JW		 7610 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7611 }
7612 if (idesc->flags & IA64_OPCODE_POSTINC)
7613 for (i = 0; i < NELEMS (idesc->operands); i++)
7614 if (idesc->operands[i] == IA64_OPND_MR3)
7615 {
7616 specs[count] = tmpl;
7617 specs[count++].index =
7618 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7619 }
542d6675
KH		 7620 }
7621 else
7622 {
7623 /* Look for anything that reads a GR. */
7624 for (i = 0; i < NELEMS (idesc->operands); i++)
7625 {
7626 if (idesc->operands[i] == IA64_OPND_MR3
7627 || idesc->operands[i] == IA64_OPND_CPUID_R3
7628 || idesc->operands[i] == IA64_OPND_DBR_R3
7629 || idesc->operands[i] == IA64_OPND_IBR_R3
800eeca4 7630 || idesc->operands[i] == IA64_OPND_MSR_R3
542d6675
KH		 7631 || idesc->operands[i] == IA64_OPND_PKR_R3
7632 || idesc->operands[i] == IA64_OPND_PMC_R3
7633 || idesc->operands[i] == IA64_OPND_PMD_R3
7634 || idesc->operands[i] == IA64_OPND_RR_R3
7635 || ((i >= idesc->num_outputs)
7636 && (idesc->operands[i] == IA64_OPND_R1
7637 || idesc->operands[i] == IA64_OPND_R2
7638 || idesc->operands[i] == IA64_OPND_R3
50b81f19
JW		 7639 /* addl source register. */
7640 || idesc->operands[i] == IA64_OPND_R3_2)))
542d6675
KH		 7641 {
7642 specs[count] = tmpl;
7643 specs[count++].index =
7644 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7645 }
7646 }
7647 }
7648 }
197865e8 7649 else
542d6675
KH		 7650 {
7651 UNHANDLED;
7652 }
800eeca4
JW		 7653 break;
7654
139368c9
JW		 7655 /* This is the same as IA64_RS_PRr, except that the register range is
7656 from 1 - 15, and there are no rotating register reads/writes here. */
800eeca4
JW		 7657 case IA64_RS_PR:
7658 if (note == 0)
542d6675 7659 {
139368c9 7660 for (i = 1; i < 16; i++)
542d6675 7661 {
139368c9
JW		 7662 specs[count] = tmpl;
7663 specs[count++].index = i;
7664 }
7665 }
7666 else if (note == 7)
7667 {
7668 valueT mask = 0;
7669 /* Mark only those registers indicated by the mask. */
7670 if (rsrc_write)
7671 {
7672 mask = CURR_SLOT.opnd[2].X_add_number;
7673 for (i = 1; i < 16; i++)
7674 if (mask & ((valueT) 1 << i))
7675 {
7676 specs[count] = tmpl;
7677 specs[count++].index = i;
7678 }
7679 }
7680 else
7681 {
7682 UNHANDLED;
7683 }
7684 }
7685 else if (note == 11) /* note 11 implies note 1 as well */
7686 {
7687 if (rsrc_write)
7688 {
7689 for (i = 0; i < idesc->num_outputs; i++)
7690 {
7691 if (idesc->operands[i] == IA64_OPND_P1
7692 || idesc->operands[i] == IA64_OPND_P2)
7693 {
7694 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7695 if (regno >= 1 && regno < 16)
7696 {
7697 specs[count] = tmpl;
7698 specs[count++].index = regno;
7699 }
7700 }
7701 }
7702 }
7703 else
7704 {
7705 UNHANDLED;
7706 }
7707 }
7708 else if (note == 12)
7709 {
7710 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7711 {
7712 specs[count] = tmpl;
7713 specs[count++].index = CURR_SLOT.qp_regno;
7714 }
7715 }
7716 else if (note == 1)
7717 {
7718 if (rsrc_write)
7719 {
7720 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7721 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7722 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7723 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7724
7725 if ((idesc->operands[0] == IA64_OPND_P1
7726 || idesc->operands[0] == IA64_OPND_P2)
7727 && p1 >= 1 && p1 < 16)
542d6675
KH		 7728 {
7729 specs[count] = tmpl;
139368c9
JW		 7730 specs[count].cmp_type =
7731 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7732 specs[count++].index = p1;
7733 }
7734 if ((idesc->operands[1] == IA64_OPND_P1
7735 || idesc->operands[1] == IA64_OPND_P2)
7736 && p2 >= 1 && p2 < 16)
7737 {
7738 specs[count] = tmpl;
7739 specs[count].cmp_type =
7740 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7741 specs[count++].index = p2;
542d6675
KH		 7742 }
7743 }
7744 else
7745 {
139368c9 7746 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
542d6675
KH		 7747 {
7748 specs[count] = tmpl;
139368c9
JW		 7749 specs[count++].index = CURR_SLOT.qp_regno;
7750 }
7751 if (idesc->operands[1] == IA64_OPND_PR)
7752 {
7753 for (i = 1; i < 16; i++)
7754 {
7755 specs[count] = tmpl;
7756 specs[count++].index = i;
7757 }
542d6675
KH		 7758 }
7759 }
7760 }
139368c9
JW		 7761 else
7762 {
7763 UNHANDLED;
7764 }
7765 break;
7766
7767 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7768 simplified cases of this. */
7769 case IA64_RS_PRr:
7770 if (note == 0)
7771 {
7772 for (i = 16; i < 63; i++)
7773 {
7774 specs[count] = tmpl;
7775 specs[count++].index = i;
7776 }
7777 }
800eeca4 7778 else if (note == 7)
542d6675
KH		 7779 {
7780 valueT mask = 0;
7781 /* Mark only those registers indicated by the mask. */
7782 if (rsrc_write
7783 && idesc->operands[0] == IA64_OPND_PR)
7784 {
7785 mask = CURR_SLOT.opnd[2].X_add_number;
139368c9
JW		 7786 if (mask & ((valueT) 1<<16))
7787 for (i = 16; i < 63; i++)
7788 {
7789 specs[count] = tmpl;
7790 specs[count++].index = i;
7791 }
542d6675
KH		 7792 }
7793 else if (rsrc_write
7794 && idesc->operands[0] == IA64_OPND_PR_ROT)
7795 {
7796 for (i = 16; i < 63; i++)
7797 {
7798 specs[count] = tmpl;
7799 specs[count++].index = i;
7800 }
7801 }
7802 else
7803 {
7804 UNHANDLED;
7805 }
7806 }
800eeca4 7807 else if (note == 11) /* note 11 implies note 1 as well */
542d6675
KH		 7808 {
7809 if (rsrc_write)
7810 {
7811 for (i = 0; i < idesc->num_outputs; i++)
7812 {
7813 if (idesc->operands[i] == IA64_OPND_P1
7814 || idesc->operands[i] == IA64_OPND_P2)
7815 {
7816 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
139368c9 7817 if (regno >= 16 && regno < 63)
542d6675
KH		 7818 {
7819 specs[count] = tmpl;
7820 specs[count++].index = regno;
7821 }
7822 }
7823 }
7824 }
7825 else
7826 {
7827 UNHANDLED;
7828 }
7829 }
800eeca4 7830 else if (note == 12)
542d6675 7831 {
139368c9 7832 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH		 7833 {
7834 specs[count] = tmpl;
7835 specs[count++].index = CURR_SLOT.qp_regno;
7836 }
7837 }
800eeca4 7838 else if (note == 1)
542d6675
KH		 7839 {
7840 if (rsrc_write)
7841 {
7842 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7843 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7484b8e6
TW		 7844 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7845 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7846
542d6675
KH		 7847 if ((idesc->operands[0] == IA64_OPND_P1
7848 || idesc->operands[0] == IA64_OPND_P2)
139368c9 7849 && p1 >= 16 && p1 < 63)
542d6675
KH		 7850 {
7851 specs[count] = tmpl;
4a4f25cf 7852 specs[count].cmp_type =
7484b8e6 7853 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
542d6675
KH		 7854 specs[count++].index = p1;
7855 }
7856 if ((idesc->operands[1] == IA64_OPND_P1
7857 || idesc->operands[1] == IA64_OPND_P2)
139368c9 7858 && p2 >= 16 && p2 < 63)
542d6675
KH		 7859 {
7860 specs[count] = tmpl;
4a4f25cf 7861 specs[count].cmp_type =
7484b8e6 7862 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
542d6675
KH		 7863 specs[count++].index = p2;
7864 }
7865 }
7866 else
7867 {
139368c9 7868 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH		 7869 {
7870 specs[count] = tmpl;
7871 specs[count++].index = CURR_SLOT.qp_regno;
7872 }
7873 if (idesc->operands[1] == IA64_OPND_PR)
7874 {
139368c9 7875 for (i = 16; i < 63; i++)
542d6675
KH		 7876 {
7877 specs[count] = tmpl;
7878 specs[count++].index = i;
7879 }
7880 }
7881 }
7882 }
197865e8 7883 else
542d6675
KH		 7884 {
7885 UNHANDLED;
7886 }
800eeca4
JW		 7887 break;
7888
7889 case IA64_RS_PSR:
197865e8 7890 /* Verify that the instruction is using the PSR bit indicated in
542d6675 7891 dep->regindex. */
800eeca4 7892 if (note == 0)
542d6675
KH		 7893 {
7894 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7895 {
7896 if (dep->regindex < 6)
7897 {
7898 specs[count++] = tmpl;
7899 }
7900 }
7901 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7902 {
7903 if (dep->regindex < 32
7904 || dep->regindex == 35
7905 || dep->regindex == 36
7906 || (!rsrc_write && dep->regindex == PSR_CPL))
7907 {
7908 specs[count++] = tmpl;
7909 }
7910 }
7911 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7912 {
7913 if (dep->regindex < 32
7914 || dep->regindex == 35
7915 || dep->regindex == 36
7916 || (rsrc_write && dep->regindex == PSR_CPL))
7917 {
7918 specs[count++] = tmpl;
7919 }
7920 }
7921 else
7922 {
7923 /* Several PSR bits have very specific dependencies. */
7924 switch (dep->regindex)
7925 {
7926 default:
7927 specs[count++] = tmpl;
7928 break;
7929 case PSR_IC:
7930 if (rsrc_write)
7931 {
7932 specs[count++] = tmpl;
7933 }
7934 else
7935 {
7936 /* Only certain CR accesses use PSR.ic */
7937 if (idesc->operands[0] == IA64_OPND_CR3
7938 || idesc->operands[1] == IA64_OPND_CR3)
7939 {
7940 int index =
7941 ((idesc->operands[0] == IA64_OPND_CR3)
7942 ? 0 : 1);
7943 int regno =
7944 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7945
7946 switch (regno)
7947 {
7948 default:
7949 break;
7950 case CR_ITIR:
7951 case CR_IFS:
7952 case CR_IIM:
7953 case CR_IIP:
7954 case CR_IPSR:
7955 case CR_ISR:
7956 case CR_IFA:
7957 case CR_IHA:
7958 case CR_IIPA:
7959 specs[count++] = tmpl;
7960 break;
7961 }
7962 }
7963 }
7964 break;
7965 case PSR_CPL:
7966 if (rsrc_write)
7967 {
7968 specs[count++] = tmpl;
7969 }
7970 else
7971 {
7972 /* Only some AR accesses use cpl */
7973 if (idesc->operands[0] == IA64_OPND_AR3
7974 || idesc->operands[1] == IA64_OPND_AR3)
7975 {
7976 int index =
7977 ((idesc->operands[0] == IA64_OPND_AR3)
7978 ? 0 : 1);
7979 int regno =
7980 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7981
7982 if (regno == AR_ITC
7983 || (index == 0
7984 && (regno == AR_ITC
7985 || regno == AR_RSC
7986 || (regno >= AR_K0
7987 && regno <= AR_K7))))
7988 {
7989 specs[count++] = tmpl;
7990 }
7991 }
7992 else
7993 {
7994 specs[count++] = tmpl;
7995 }
7996 break;
7997 }
7998 }
7999 }
8000 }
800eeca4 8001 else if (note == 7)
542d6675
KH		 8002 {
8003 valueT mask = 0;
8004 if (idesc->operands[0] == IA64_OPND_IMMU24)
8005 {
8006 mask = CURR_SLOT.opnd[0].X_add_number;
8007 }
8008 else
8009 {
8010 UNHANDLED;
8011 }
8012 if (mask & ((valueT) 1 << dep->regindex))
8013 {
8014 specs[count++] = tmpl;
8015 }
8016 }
800eeca4 8017 else if (note == 8)
542d6675
KH		 8018 {
8019 int min = dep->regindex == PSR_DFL ? 2 : 32;
8020 int max = dep->regindex == PSR_DFL ? 31 : 127;
8021 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8022 for (i = 0; i < NELEMS (idesc->operands); i++)
8023 {
8024 if (idesc->operands[i] == IA64_OPND_F1
8025 || idesc->operands[i] == IA64_OPND_F2
8026 || idesc->operands[i] == IA64_OPND_F3
8027 || idesc->operands[i] == IA64_OPND_F4)
8028 {
8029 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8030 if (reg >= min && reg <= max)
8031 {
8032 specs[count++] = tmpl;
8033 }
8034 }
8035 }
8036 }
800eeca4 8037 else if (note == 9)
542d6675
KH		 8038 {
8039 int min = dep->regindex == PSR_MFL ? 2 : 32;
8040 int max = dep->regindex == PSR_MFL ? 31 : 127;
8041 /* mfh is read on writes to FR32-127; mfl is read on writes to
8042 FR2-31 */
8043 for (i = 0; i < idesc->num_outputs; i++)
8044 {
8045 if (idesc->operands[i] == IA64_OPND_F1)
8046 {
8047 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8048 if (reg >= min && reg <= max)
8049 {
8050 specs[count++] = tmpl;
8051 }
8052 }
8053 }
8054 }
800eeca4 8055 else if (note == 10)
542d6675
KH		 8056 {
8057 for (i = 0; i < NELEMS (idesc->operands); i++)
8058 {
8059 if (idesc->operands[i] == IA64_OPND_R1
8060 || idesc->operands[i] == IA64_OPND_R2
8061 || idesc->operands[i] == IA64_OPND_R3)
8062 {
8063 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8064 if (regno >= 16 && regno <= 31)
8065 {
8066 specs[count++] = tmpl;
8067 }
8068 }
8069 }
8070 }
800eeca4 8071 else
542d6675
KH		 8072 {
8073 UNHANDLED;
8074 }
800eeca4
JW		 8075 break;
8076
8077 case IA64_RS_AR_FPSR:
8078 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
542d6675
KH		 8079 {
8080 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8081 if (regno == AR_FPSR)
8082 {
8083 specs[count++] = tmpl;
8084 }
8085 }
800eeca4 8086 else
542d6675
KH		 8087 {
8088 specs[count++] = tmpl;
8089 }
800eeca4
JW		 8090 break;
8091
197865e8 8092 case IA64_RS_ARX:
800eeca4
JW		 8093 /* Handle all AR[REG] resources */
8094 if (note == 0 || note == 1)
542d6675
KH		 8095 {
8096 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8097 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
8098 && regno == dep->regindex)
8099 {
8100 specs[count++] = tmpl;
8101 }
8102 /* other AR[REG] resources may be affected by AR accesses */
8103 else if (idesc->operands[0] == IA64_OPND_AR3)
8104 {
8105 /* AR[] writes */
8106 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
8107 switch (dep->regindex)
8108 {
8109 default:
8110 break;
8111 case AR_BSP:
8112 case AR_RNAT:
8113 if (regno == AR_BSPSTORE)
8114 {
8115 specs[count++] = tmpl;
8116 }
8117 case AR_RSC:
8118 if (!rsrc_write &&
8119 (regno == AR_BSPSTORE
8120 || regno == AR_RNAT))
8121 {
8122 specs[count++] = tmpl;
8123 }
8124 break;
8125 }
8126 }
8127 else if (idesc->operands[1] == IA64_OPND_AR3)
8128 {
8129 /* AR[] reads */
8130 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
8131 switch (dep->regindex)
8132 {
8133 default:
8134 break;
8135 case AR_RSC:
8136 if (regno == AR_BSPSTORE || regno == AR_RNAT)
8137 {
8138 specs[count++] = tmpl;
8139 }
8140 break;
8141 }
8142 }
8143 else
8144 {
8145 specs[count++] = tmpl;
8146 }
8147 }
800eeca4 8148 else
542d6675
KH		 8149 {
8150 UNHANDLED;
8151 }
800eeca4
JW		 8152 break;
8153
8154 case IA64_RS_CRX:
8155 /* Handle all CR[REG] resources */
8156 if (note == 0 || note == 1)
542d6675
KH		 8157 {
8158 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
8159 {
8160 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
8161 if (regno == dep->regindex)
8162 {
8163 specs[count++] = tmpl;
8164 }
8165 else if (!rsrc_write)
8166 {
8167 /* Reads from CR[IVR] affect other resources. */
8168 if (regno == CR_IVR)
8169 {
8170 if ((dep->regindex >= CR_IRR0
8171 && dep->regindex <= CR_IRR3)
8172 || dep->regindex == CR_TPR)
8173 {
8174 specs[count++] = tmpl;
8175 }
8176 }
8177 }
8178 }
8179 else
8180 {
8181 specs[count++] = tmpl;
8182 }
8183 }
800eeca4 8184 else
542d6675
KH		 8185 {
8186 UNHANDLED;
8187 }
800eeca4
JW		 8188 break;
8189
8190 case IA64_RS_INSERVICE:
8191 /* look for write of EOI (67) or read of IVR (65) */
8192 if ((idesc->operands[0] == IA64_OPND_CR3
542d6675
KH		 8193 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
8194 || (idesc->operands[1] == IA64_OPND_CR3
8195 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
8196 {
8197 specs[count++] = tmpl;
8198 }
800eeca4
JW		 8199 break;
8200
8201 case IA64_RS_GR0:
8202 if (note == 1)
542d6675
KH		 8203 {
8204 specs[count++] = tmpl;
8205 }
800eeca4 8206 else
542d6675
KH		 8207 {
8208 UNHANDLED;
8209 }
800eeca4
JW		 8210 break;
8211
8212 case IA64_RS_CFM:
8213 if (note != 2)
542d6675
KH		 8214 {
8215 specs[count++] = tmpl;
8216 }
800eeca4 8217 else
542d6675
KH		 8218 {
8219 /* Check if any of the registers accessed are in the rotating region.
8220 mov to/from pr accesses CFM only when qp_regno is in the rotating
8221 region */
8222 for (i = 0; i < NELEMS (idesc->operands); i++)
8223 {
8224 if (idesc->operands[i] == IA64_OPND_R1
8225 || idesc->operands[i] == IA64_OPND_R2
8226 || idesc->operands[i] == IA64_OPND_R3)
8227 {
8228 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8229 /* Assumes that md.rot.num_regs is always valid */
8230 if (md.rot.num_regs > 0
8231 && num > 31
8232 && num < 31 + md.rot.num_regs)
8233 {
8234 specs[count] = tmpl;
8235 specs[count++].specific = 0;
8236 }
8237 }
8238 else if (idesc->operands[i] == IA64_OPND_F1
8239 || idesc->operands[i] == IA64_OPND_F2
8240 || idesc->operands[i] == IA64_OPND_F3
8241 || idesc->operands[i] == IA64_OPND_F4)
8242 {
8243 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8244 if (num > 31)
8245 {
8246 specs[count] = tmpl;
8247 specs[count++].specific = 0;
8248 }
8249 }
8250 else if (idesc->operands[i] == IA64_OPND_P1
8251 || idesc->operands[i] == IA64_OPND_P2)
8252 {
8253 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
8254 if (num > 15)
8255 {
8256 specs[count] = tmpl;
8257 specs[count++].specific = 0;
8258 }
8259 }
8260 }
8261 if (CURR_SLOT.qp_regno > 15)
8262 {
8263 specs[count] = tmpl;
8264 specs[count++].specific = 0;
8265 }
8266 }
800eeca4
JW		 8267 break;
8268
139368c9
JW		 8269 /* This is the same as IA64_RS_PRr, except simplified to account for
8270 the fact that there is only one register. */
800eeca4
JW		 8271 case IA64_RS_PR63:
8272 if (note == 0)
542d6675
KH		 8273 {
8274 specs[count++] = tmpl;
8275 }
139368c9
JW		 8276 else if (note == 7)
8277 {
8278 valueT mask = 0;
8279 if (idesc->operands[2] == IA64_OPND_IMM17)
8280 mask = CURR_SLOT.opnd[2].X_add_number;
8281 if (mask & ((valueT) 1 << 63))
8282 specs[count++] = tmpl;
8283 }
800eeca4 8284 else if (note == 11)
542d6675
KH		 8285 {
8286 if ((idesc->operands[0] == IA64_OPND_P1
8287 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
8288 || (idesc->operands[1] == IA64_OPND_P2
8289 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
8290 {
8291 specs[count++] = tmpl;
8292 }
8293 }
800eeca4 8294 else if (note == 12)
542d6675
KH		 8295 {
8296 if (CURR_SLOT.qp_regno == 63)
8297 {
8298 specs[count++] = tmpl;
8299 }
8300 }
800eeca4 8301 else if (note == 1)
542d6675
KH		 8302 {
8303 if (rsrc_write)
8304 {
7484b8e6
TW		 8305 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8306 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8307 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
8308 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
8309
4a4f25cf 8310 if (p1 == 63
7484b8e6
TW		 8311 && (idesc->operands[0] == IA64_OPND_P1
8312 || idesc->operands[0] == IA64_OPND_P2))
8313 {
8314 specs[count] = tmpl;
4a4f25cf 8315 specs[count++].cmp_type =
7484b8e6
TW		 8316 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8317 }
8318 if (p2 == 63
8319 && (idesc->operands[1] == IA64_OPND_P1
8320 || idesc->operands[1] == IA64_OPND_P2))
8321 {
8322 specs[count] = tmpl;
4a4f25cf 8323 specs[count++].cmp_type =
7484b8e6
TW		 8324 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8325 }
542d6675
KH		 8326 }
8327 else
8328 {
8329 if (CURR_SLOT.qp_regno == 63)
8330 {
8331 specs[count++] = tmpl;
8332 }
8333 }
8334 }
800eeca4 8335 else
542d6675
KH		 8336 {
8337 UNHANDLED;
8338 }
800eeca4
JW		 8339 break;
8340
8341 case IA64_RS_RSE:
8342 /* FIXME we can identify some individual RSE written resources, but RSE
542d6675
KH		 8343 read resources have not yet been completely identified, so for now
8344 treat RSE as a single resource */
800eeca4 8345 if (strncmp (idesc->name, "mov", 3) == 0)
542d6675
KH		 8346 {
8347 if (rsrc_write)
8348 {
8349 if (idesc->operands[0] == IA64_OPND_AR3
8350 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
8351 {
8352 specs[count] = tmpl;
8353 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8354 }
8355 }
8356 else
8357 {
8358 if (idesc->operands[0] == IA64_OPND_AR3)
8359 {
8360 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
8361 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
8362 {
8363 specs[count++] = tmpl;
8364 }
8365 }
8366 else if (idesc->operands[1] == IA64_OPND_AR3)
8367 {
8368 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
8369 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
8370 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
8371 {
8372 specs[count++] = tmpl;
8373 }
8374 }
8375 }
8376 }
197865e8 8377 else
542d6675
KH		 8378 {
8379 specs[count++] = tmpl;
8380 }
800eeca4
JW		 8381 break;
8382
8383 case IA64_RS_ANY:
8384 /* FIXME -- do any of these need to be non-specific? */
8385 specs[count++] = tmpl;
8386 break;
8387
8388 default:
8389 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
8390 break;
8391 }
8392
8393 return count;
8394}
8395
8396/* Clear branch flags on marked resources. This breaks the link between the
542d6675
KH		 8397 QP of the marking instruction and a subsequent branch on the same QP. */
8398
800eeca4
JW		 8399static void
8400clear_qp_branch_flag (mask)
542d6675 8401 valueT mask;
800eeca4
JW		 8402{
8403 int i;
542d6675 8404 for (i = 0; i < regdepslen; i++)
800eeca4 8405 {
197865e8 8406 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
800eeca4 8407 if ((bit & mask) != 0)
542d6675
KH		 8408 {
8409 regdeps[i].link_to_qp_branch = 0;
8410 }
800eeca4
JW		 8411 }
8412}
8413
197865e8 8414/* Remove any mutexes which contain any of the PRs indicated in the mask.
800eeca4 8415
542d6675
KH		 8416 Any changes to a PR clears the mutex relations which include that PR. */
8417
800eeca4
JW		 8418static void
8419clear_qp_mutex (mask)
542d6675 8420 valueT mask;
800eeca4
JW		 8421{
8422 int i;
8423
8424 i = 0;
8425 while (i < qp_mutexeslen)
8426 {
8427 if ((qp_mutexes[i].prmask & mask) != 0)
542d6675
KH		 8428 {
8429 if (md.debug_dv)
8430 {
8431 fprintf (stderr, " Clearing mutex relation");
8432 print_prmask (qp_mutexes[i].prmask);
8433 fprintf (stderr, "\n");
8434 }
8435 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
8436 }
800eeca4 8437 else
542d6675 8438 ++i;
800eeca4
JW		 8439 }
8440}
8441
8442/* Clear implies relations which contain PRs in the given masks.
8443 P1_MASK indicates the source of the implies relation, while P2_MASK
542d6675
KH		 8444 indicates the implied PR. */
8445
800eeca4
JW		 8446static void
8447clear_qp_implies (p1_mask, p2_mask)
542d6675
KH		 8448 valueT p1_mask;
8449 valueT p2_mask;
800eeca4
JW		 8450{
8451 int i;
8452
8453 i = 0;
8454 while (i < qp_implieslen)
8455 {
197865e8 8456 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
542d6675
KH		 8457 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
8458 {
8459 if (md.debug_dv)
8460 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
8461 qp_implies[i].p1, qp_implies[i].p2);
8462 qp_implies[i] = qp_implies[--qp_implieslen];
8463 }
197865e8 8464 else
542d6675 8465 ++i;
800eeca4
JW		 8466 }
8467}
8468
542d6675
KH		 8469/* Add the PRs specified to the list of implied relations. */
8470
800eeca4
JW		 8471static void
8472add_qp_imply (p1, p2)
542d6675 8473 int p1, p2;
800eeca4
JW		 8474{
8475 valueT mask;
8476 valueT bit;
8477 int i;
8478
542d6675 8479 /* p0 is not meaningful here. */
800eeca4
JW		 8480 if (p1 == 0 || p2 == 0)
8481 abort ();
8482
8483 if (p1 == p2)
8484 return;
8485
542d6675
KH		 8486 /* If it exists already, ignore it. */
8487 for (i = 0; i < qp_implieslen; i++)
800eeca4 8488 {
197865e8 8489 if (qp_implies[i].p1 == p1
542d6675
KH		 8490 && qp_implies[i].p2 == p2
8491 && qp_implies[i].path == md.path
8492 && !qp_implies[i].p2_branched)
8493 return;
800eeca4
JW		 8494 }
8495
8496 if (qp_implieslen == qp_impliestotlen)
8497 {
8498 qp_impliestotlen += 20;
8499 qp_implies = (struct qp_imply *)
542d6675
KH		 8500 xrealloc ((void *) qp_implies,
8501 qp_impliestotlen * sizeof (struct qp_imply));
800eeca4
JW		 8502 }
8503 if (md.debug_dv)
8504 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
8505 qp_implies[qp_implieslen].p1 = p1;
8506 qp_implies[qp_implieslen].p2 = p2;
8507 qp_implies[qp_implieslen].path = md.path;
8508 qp_implies[qp_implieslen++].p2_branched = 0;
8509
8510 /* Add in the implied transitive relations; for everything that p2 implies,
8511 make p1 imply that, too; for everything that implies p1, make it imply p2
197865e8 8512 as well. */
542d6675 8513 for (i = 0; i < qp_implieslen; i++)
800eeca4
JW		 8514 {
8515 if (qp_implies[i].p1 == p2)
542d6675 8516 add_qp_imply (p1, qp_implies[i].p2);
800eeca4 8517 if (qp_implies[i].p2 == p1)
542d6675 8518 add_qp_imply (qp_implies[i].p1, p2);
800eeca4
JW		 8519 }
8520 /* Add in mutex relations implied by this implies relation; for each mutex
197865e8
KH		 8521 relation containing p2, duplicate it and replace p2 with p1. */
8522 bit = (valueT) 1 << p1;
8523 mask = (valueT) 1 << p2;
542d6675 8524 for (i = 0; i < qp_mutexeslen; i++)
800eeca4
JW		 8525 {
8526 if (qp_mutexes[i].prmask & mask)
542d6675 8527 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
800eeca4
JW		 8528 }
8529}
8530
800eeca4
JW		 8531/* Add the PRs specified in the mask to the mutex list; this means that only
8532 one of the PRs can be true at any time. PR0 should never be included in
8533 the mask. */
542d6675 8534
800eeca4
JW		 8535static void
8536add_qp_mutex (mask)
542d6675 8537 valueT mask;
800eeca4
JW		 8538{
8539 if (mask & 0x1)
8540 abort ();
8541
8542 if (qp_mutexeslen == qp_mutexestotlen)
8543 {
8544 qp_mutexestotlen += 20;
8545 qp_mutexes = (struct qpmutex *)
542d6675
KH		 8546 xrealloc ((void *) qp_mutexes,
8547 qp_mutexestotlen * sizeof (struct qpmutex));
800eeca4
JW		 8548 }
8549 if (md.debug_dv)
8550 {
8551 fprintf (stderr, " Registering mutex on");
8552 print_prmask (mask);
8553 fprintf (stderr, "\n");
8554 }
8555 qp_mutexes[qp_mutexeslen].path = md.path;
8556 qp_mutexes[qp_mutexeslen++].prmask = mask;
8557}
8558
8559static void
8560clear_register_values ()
8561{
8562 int i;
8563 if (md.debug_dv)
8564 fprintf (stderr, " Clearing register values\n");
542d6675 8565 for (i = 1; i < NELEMS (gr_values); i++)
800eeca4
JW		 8566 gr_values[i].known = 0;
8567}
8568
8569/* Keep track of register values/changes which affect DV tracking.
8570
8571 optimization note: should add a flag to classes of insns where otherwise we
542d6675 8572 have to examine a group of strings to identify them. */
800eeca4 8573
800eeca4
JW		 8574static void
8575note_register_values (idesc)
542d6675 8576 struct ia64_opcode *idesc;
800eeca4
JW		 8577{
8578 valueT qp_changemask = 0;
8579 int i;
8580
542d6675
KH		 8581 /* Invalidate values for registers being written to. */
8582 for (i = 0; i < idesc->num_outputs; i++)
800eeca4 8583 {
197865e8 8584 if (idesc->operands[i] == IA64_OPND_R1
542d6675
KH		 8585 || idesc->operands[i] == IA64_OPND_R2
8586 || idesc->operands[i] == IA64_OPND_R3)
8587 {
8588 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8589 if (regno > 0 && regno < NELEMS (gr_values))
8590 gr_values[regno].known = 0;
8591 }
50b81f19
JW		 8592 else if (idesc->operands[i] == IA64_OPND_R3_2)
8593 {
8594 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8595 if (regno > 0 && regno < 4)
8596 gr_values[regno].known = 0;
8597 }
197865e8 8598 else if (idesc->operands[i] == IA64_OPND_P1
542d6675
KH		 8599 || idesc->operands[i] == IA64_OPND_P2)
8600 {
8601 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8602 qp_changemask |= (valueT) 1 << regno;
8603 }
800eeca4 8604 else if (idesc->operands[i] == IA64_OPND_PR)
542d6675
KH		 8605 {
8606 if (idesc->operands[2] & (valueT) 0x10000)
8607 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
8608 else
8609 qp_changemask = idesc->operands[2];
8610 break;
8611 }
800eeca4 8612 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
542d6675
KH		 8613 {
8614 if (idesc->operands[1] & ((valueT) 1 << 43))
8615 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
8616 else
8617 qp_changemask = idesc->operands[1];
8618 qp_changemask &= ~(valueT) 0xFFFF;
8619 break;
8620 }
8621 }
8622
8623 /* Always clear qp branch flags on any PR change. */
8624 /* FIXME there may be exceptions for certain compares. */
800eeca4
JW		 8625 clear_qp_branch_flag (qp_changemask);
8626
542d6675 8627 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
800eeca4
JW		 8628 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8629 {
197865e8 8630 qp_changemask |= ~(valueT) 0xFFFF;
800eeca4 8631 if (strcmp (idesc->name, "clrrrb.pr") != 0)
542d6675
KH		 8632 {
8633 for (i = 32; i < 32 + md.rot.num_regs; i++)
8634 gr_values[i].known = 0;
8635 }
800eeca4
JW		 8636 clear_qp_mutex (qp_changemask);
8637 clear_qp_implies (qp_changemask, qp_changemask);
8638 }
542d6675
KH		 8639 /* After a call, all register values are undefined, except those marked
8640 as "safe". */
800eeca4 8641 else if (strncmp (idesc->name, "br.call", 6) == 0
542d6675 8642 || strncmp (idesc->name, "brl.call", 7) == 0)
800eeca4 8643 {
56d27c17 8644 /* FIXME keep GR values which are marked as "safe_across_calls" */
800eeca4
JW		 8645 clear_register_values ();
8646 clear_qp_mutex (~qp_safe_across_calls);
8647 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8648 clear_qp_branch_flag (~qp_safe_across_calls);
8649 }
e9718fe1 8650 else if (is_interruption_or_rfi (idesc)
542d6675 8651 || is_taken_branch (idesc))
e9718fe1
TW		 8652 {
8653 clear_register_values ();
197865e8
KH		 8654 clear_qp_mutex (~(valueT) 0);
8655 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
e9718fe1 8656 }
542d6675 8657 /* Look for mutex and implies relations. */
197865e8 8658 else if ((idesc->operands[0] == IA64_OPND_P1
542d6675
KH		 8659 || idesc->operands[0] == IA64_OPND_P2)
8660 && (idesc->operands[1] == IA64_OPND_P1
8661 || idesc->operands[1] == IA64_OPND_P2))
800eeca4
JW		 8662 {
8663 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
197865e8
KH		 8664 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8665 valueT p1mask = (valueT) 1 << p1;
8666 valueT p2mask = (valueT) 1 << p2;
800eeca4 8667
542d6675 8668 /* If one of the PRs is PR0, we can't really do anything. */
800eeca4 8669 if (p1 == 0 || p2 == 0)
542d6675
KH		 8670 {
8671 if (md.debug_dv)
8672 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8673 }
800eeca4 8674 /* In general, clear mutexes and implies which include P1 or P2,
542d6675 8675 with the following exceptions. */
800eeca4 8676 else if (strstr (idesc->name, ".or.andcm") != NULL)
542d6675
KH		 8677 {
8678 add_qp_mutex (p1mask | p2mask);
8679 clear_qp_implies (p2mask, p1mask);
8680 }
800eeca4 8681 else if (strstr (idesc->name, ".and.orcm") != NULL)
542d6675
KH		 8682 {
8683 add_qp_mutex (p1mask | p2mask);
8684 clear_qp_implies (p1mask, p2mask);
8685 }
800eeca4 8686 else if (strstr (idesc->name, ".and") != NULL)
542d6675
KH		 8687 {
8688 clear_qp_implies (0, p1mask | p2mask);
8689 }
800eeca4 8690 else if (strstr (idesc->name, ".or") != NULL)
542d6675
KH		 8691 {
8692 clear_qp_mutex (p1mask | p2mask);
8693 clear_qp_implies (p1mask | p2mask, 0);
8694 }
800eeca4 8695 else
542d6675
KH		 8696 {
8697 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
8698 if (strstr (idesc->name, ".unc") != NULL)
8699 {
8700 add_qp_mutex (p1mask | p2mask);
8701 if (CURR_SLOT.qp_regno != 0)
8702 {
8703 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8704 CURR_SLOT.qp_regno);
8705 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8706 CURR_SLOT.qp_regno);
8707 }
8708 }
8709 else if (CURR_SLOT.qp_regno == 0)
8710 {
8711 add_qp_mutex (p1mask | p2mask);
8712 }
8713 else
8714 {
8715 clear_qp_mutex (p1mask | p2mask);
8716 }
8717 }
8718 }
8719 /* Look for mov imm insns into GRs. */
800eeca4 8720 else if (idesc->operands[0] == IA64_OPND_R1
542d6675
KH		 8721 && (idesc->operands[1] == IA64_OPND_IMM22
8722 || idesc->operands[1] == IA64_OPND_IMMU64)
8723 && (strcmp (idesc->name, "mov") == 0
8724 || strcmp (idesc->name, "movl") == 0))
800eeca4
JW		 8725 {
8726 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
542d6675
KH		 8727 if (regno > 0 && regno < NELEMS (gr_values))
8728 {
8729 gr_values[regno].known = 1;
8730 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
8731 gr_values[regno].path = md.path;
8732 if (md.debug_dv)
2434f565
JW		 8733 {
8734 fprintf (stderr, " Know gr%d = ", regno);
8735 fprintf_vma (stderr, gr_values[regno].value);
8736 fputs ("\n", stderr);
8737 }
542d6675 8738 }
800eeca4 8739 }
197865e8 8740 else
800eeca4
JW		 8741 {
8742 clear_qp_mutex (qp_changemask);
8743 clear_qp_implies (qp_changemask, qp_changemask);
8744 }
8745}
8746
542d6675
KH		 8747/* Return whether the given predicate registers are currently mutex. */
8748
800eeca4
JW		 8749static int
8750qp_mutex (p1, p2, path)
542d6675
KH		 8751 int p1;
8752 int p2;
8753 int path;
800eeca4
JW		 8754{
8755 int i;
8756 valueT mask;
8757
8758 if (p1 != p2)
8759 {
542d6675
KH		 8760 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
8761 for (i = 0; i < qp_mutexeslen; i++)
8762 {
8763 if (qp_mutexes[i].path >= path
8764 && (qp_mutexes[i].prmask & mask) == mask)
8765 return 1;
8766 }
800eeca4
JW		 8767 }
8768 return 0;
8769}
8770
8771/* Return whether the given resource is in the given insn's list of chks
8772 Return 1 if the conflict is absolutely determined, 2 if it's a potential
542d6675
KH		 8773 conflict. */
8774
800eeca4
JW		 8775static int
8776resources_match (rs, idesc, note, qp_regno, path)
542d6675
KH		 8777 struct rsrc *rs;
8778 struct ia64_opcode *idesc;
8779 int note;
8780 int qp_regno;
8781 int path;
800eeca4
JW		 8782{
8783 struct rsrc specs[MAX_SPECS];
8784 int count;
8785
8786 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8787 we don't need to check. One exception is note 11, which indicates that
8788 target predicates are written regardless of PR[qp]. */
197865e8 8789 if (qp_mutex (rs->qp_regno, qp_regno, path)
800eeca4
JW		 8790 && note != 11)
8791 return 0;
8792
8793 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
8794 while (count-- > 0)
8795 {
8796 /* UNAT checking is a bit more specific than other resources */
8797 if (rs->dependency->specifier == IA64_RS_AR_UNAT
542d6675
KH		 8798 && specs[count].mem_offset.hint
8799 && rs->mem_offset.hint)
8800 {
8801 if (rs->mem_offset.base == specs[count].mem_offset.base)
8802 {
8803 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
8804 ((specs[count].mem_offset.offset >> 3) & 0x3F))
8805 return 1;
8806 else
8807 continue;
8808 }
8809 }
800eeca4 8810
7484b8e6 8811 /* Skip apparent PR write conflicts where both writes are an AND or both
4a4f25cf 8812 writes are an OR. */
7484b8e6 8813 if (rs->dependency->specifier == IA64_RS_PR
afa680f8 8814 || rs->dependency->specifier == IA64_RS_PRr
7484b8e6
TW		 8815 || rs->dependency->specifier == IA64_RS_PR63)
8816 {
8817 if (specs[count].cmp_type != CMP_NONE
8818 && specs[count].cmp_type == rs->cmp_type)
8819 {
8820 if (md.debug_dv)
8821 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
8822 dv_mode[rs->dependency->mode],
afa680f8 8823 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6
TW		 8824 specs[count].index : 63);
8825 continue;
8826 }
8827 if (md.debug_dv)
4a4f25cf 8828 fprintf (stderr,
7484b8e6
TW		 8829 " %s on parallel compare conflict %s vs %s on PR%d\n",
8830 dv_mode[rs->dependency->mode],
4a4f25cf 8831 dv_cmp_type[rs->cmp_type],
7484b8e6 8832 dv_cmp_type[specs[count].cmp_type],
afa680f8 8833 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6 8834 specs[count].index : 63);
4a4f25cf 8835
7484b8e6
TW		 8836 }
8837
800eeca4 8838 /* If either resource is not specific, conservatively assume a conflict
197865e8 8839 */
800eeca4 8840 if (!specs[count].specific || !rs->specific)
542d6675 8841 return 2;
800eeca4 8842 else if (specs[count].index == rs->index)
542d6675 8843 return 1;
800eeca4
JW		 8844 }
8845#if 0
8846 if (md.debug_dv)
8847 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
8848#endif
8849
8850 return 0;
8851}
8852
8853/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8854 insert a stop to create the break. Update all resource dependencies
8855 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8856 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8857 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
542d6675 8858 instruction. */
800eeca4
JW		 8859
8860static void
8861insn_group_break (insert_stop, qp_regno, save_current)
542d6675
KH		 8862 int insert_stop;
8863 int qp_regno;
8864 int save_current;
800eeca4
JW		 8865{
8866 int i;
8867
8868 if (insert_stop && md.num_slots_in_use > 0)
8869 PREV_SLOT.end_of_insn_group = 1;
8870
8871 if (md.debug_dv)
8872 {
197865e8 8873 fprintf (stderr, " Insn group break%s",
542d6675 8874 (insert_stop ? " (w/stop)" : ""));
800eeca4 8875 if (qp_regno != 0)
542d6675 8876 fprintf (stderr, " effective for QP=%d", qp_regno);
800eeca4
JW		 8877 fprintf (stderr, "\n");
8878 }
8879
8880 i = 0;
8881 while (i < regdepslen)
8882 {
8883 const struct ia64_dependency *dep = regdeps[i].dependency;
8884
8885 if (qp_regno != 0
542d6675
KH		 8886 && regdeps[i].qp_regno != qp_regno)
8887 {
8888 ++i;
8889 continue;
8890 }
800eeca4
JW		 8891
8892 if (save_current
542d6675
KH		 8893 && CURR_SLOT.src_file == regdeps[i].file
8894 && CURR_SLOT.src_line == regdeps[i].line)
8895 {
8896 ++i;
8897 continue;
8898 }
800eeca4
JW		 8899
8900 /* clear dependencies which are automatically cleared by a stop, or
542d6675 8901 those that have reached the appropriate state of insn serialization */
800eeca4 8902 if (dep->semantics == IA64_DVS_IMPLIED
542d6675
KH		 8903 || dep->semantics == IA64_DVS_IMPLIEDF
8904 || regdeps[i].insn_srlz == STATE_SRLZ)
8905 {
8906 print_dependency ("Removing", i);
8907 regdeps[i] = regdeps[--regdepslen];
8908 }
800eeca4 8909 else
542d6675
KH		 8910 {
8911 if (dep->semantics == IA64_DVS_DATA
8912 || dep->semantics == IA64_DVS_INSTR
800eeca4 8913 || dep->semantics == IA64_DVS_SPECIFIC)
542d6675
KH		 8914 {
8915 if (regdeps[i].insn_srlz == STATE_NONE)
8916 regdeps[i].insn_srlz = STATE_STOP;
8917 if (regdeps[i].data_srlz == STATE_NONE)
8918 regdeps[i].data_srlz = STATE_STOP;
8919 }
8920 ++i;
8921 }
800eeca4
JW		 8922 }
8923}
8924
542d6675
KH		 8925/* Add the given resource usage spec to the list of active dependencies. */
8926
197865e8 8927static void
800eeca4 8928mark_resource (idesc, dep, spec, depind, path)
2434f565
JW		 8929 struct ia64_opcode *idesc ATTRIBUTE_UNUSED;
8930 const struct ia64_dependency *dep ATTRIBUTE_UNUSED;
542d6675
KH		 8931 struct rsrc *spec;
8932 int depind;
8933 int path;
800eeca4
JW		 8934{
8935 if (regdepslen == regdepstotlen)
8936 {
8937 regdepstotlen += 20;
8938 regdeps = (struct rsrc *)
542d6675 8939 xrealloc ((void *) regdeps,
bc805888 8940 regdepstotlen * sizeof (struct rsrc));
800eeca4
JW		 8941 }
8942
8943 regdeps[regdepslen] = *spec;
8944 regdeps[regdepslen].depind = depind;
8945 regdeps[regdepslen].path = path;
8946 regdeps[regdepslen].file = CURR_SLOT.src_file;
8947 regdeps[regdepslen].line = CURR_SLOT.src_line;
8948
8949 print_dependency ("Adding", regdepslen);
8950
8951 ++regdepslen;
8952}
8953
8954static void
8955print_dependency (action, depind)
542d6675
KH		 8956 const char *action;
8957 int depind;
800eeca4
JW		 8958{
8959 if (md.debug_dv)
8960 {
197865e8 8961 fprintf (stderr, " %s %s '%s'",
542d6675
KH		 8962 action, dv_mode[(regdeps[depind].dependency)->mode],
8963 (regdeps[depind].dependency)->name);
800eeca4 8964 if (regdeps[depind].specific && regdeps[depind].index != 0)
542d6675 8965 fprintf (stderr, " (%d)", regdeps[depind].index);
800eeca4 8966 if (regdeps[depind].mem_offset.hint)
2434f565
JW		 8967 {
8968 fputs (" ", stderr);
8969 fprintf_vma (stderr, regdeps[depind].mem_offset.base);
8970 fputs ("+", stderr);
8971 fprintf_vma (stderr, regdeps[depind].mem_offset.offset);
8972 }
800eeca4
JW		 8973 fprintf (stderr, "\n");
8974 }
8975}
8976
8977static void
8978instruction_serialization ()
8979{
8980 int i;
8981 if (md.debug_dv)
8982 fprintf (stderr, " Instruction serialization\n");
542d6675 8983 for (i = 0; i < regdepslen; i++)
800eeca4
JW		 8984 if (regdeps[i].insn_srlz == STATE_STOP)
8985 regdeps[i].insn_srlz = STATE_SRLZ;
8986}
8987
8988static void
8989data_serialization ()
8990{
8991 int i = 0;
8992 if (md.debug_dv)
8993 fprintf (stderr, " Data serialization\n");
8994 while (i < regdepslen)
8995 {
8996 if (regdeps[i].data_srlz == STATE_STOP
542d6675
KH		 8997 /* Note: as of 991210, all "other" dependencies are cleared by a
8998 data serialization. This might change with new tables */
8999 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
9000 {
9001 print_dependency ("Removing", i);
9002 regdeps[i] = regdeps[--regdepslen];
9003 }
800eeca4 9004 else
542d6675 9005 ++i;
800eeca4
JW		 9006 }
9007}
9008
542d6675
KH		 9009/* Insert stops and serializations as needed to avoid DVs. */
9010
800eeca4
JW		 9011static void
9012remove_marked_resource (rs)
542d6675 9013 struct rsrc *rs;
800eeca4
JW		 9014{
9015 switch (rs->dependency->semantics)
9016 {
9017 case IA64_DVS_SPECIFIC:
9018 if (md.debug_dv)
9019 fprintf (stderr, "Implementation-specific, assume worst case...\n");
197865e8 9020 /* ...fall through... */
800eeca4
JW		 9021 case IA64_DVS_INSTR:
9022 if (md.debug_dv)
542d6675 9023 fprintf (stderr, "Inserting instr serialization\n");
800eeca4 9024 if (rs->insn_srlz < STATE_STOP)
542d6675 9025 insn_group_break (1, 0, 0);
800eeca4 9026 if (rs->insn_srlz < STATE_SRLZ)
542d6675
KH		 9027 {
9028 int oldqp = CURR_SLOT.qp_regno;
9029 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9030 /* Manually jam a srlz.i insn into the stream */
9031 CURR_SLOT.qp_regno = 0;
9032 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
9033 instruction_serialization ();
9034 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9035 if (++md.num_slots_in_use >= NUM_SLOTS)
9036 emit_one_bundle ();
9037 CURR_SLOT.qp_regno = oldqp;
9038 CURR_SLOT.idesc = oldidesc;
9039 }
800eeca4
JW		 9040 insn_group_break (1, 0, 0);
9041 break;
9042 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
542d6675
KH		 9043 "other" types of DV are eliminated
9044 by a data serialization */
800eeca4
JW		 9045 case IA64_DVS_DATA:
9046 if (md.debug_dv)
542d6675 9047 fprintf (stderr, "Inserting data serialization\n");
800eeca4 9048 if (rs->data_srlz < STATE_STOP)
542d6675 9049 insn_group_break (1, 0, 0);
800eeca4 9050 {
542d6675
KH		 9051 int oldqp = CURR_SLOT.qp_regno;
9052 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9053 /* Manually jam a srlz.d insn into the stream */
9054 CURR_SLOT.qp_regno = 0;
9055 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
9056 data_serialization ();
9057 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9058 if (++md.num_slots_in_use >= NUM_SLOTS)
9059 emit_one_bundle ();
9060 CURR_SLOT.qp_regno = oldqp;
9061 CURR_SLOT.idesc = oldidesc;
800eeca4
JW		 9062 }
9063 break;
9064 case IA64_DVS_IMPLIED:
9065 case IA64_DVS_IMPLIEDF:
9066 if (md.debug_dv)
542d6675 9067 fprintf (stderr, "Inserting stop\n");
800eeca4
JW		 9068 insn_group_break (1, 0, 0);
9069 break;
9070 default:
9071 break;
9072 }
9073}
9074
9075/* Check the resources used by the given opcode against the current dependency
197865e8 9076 list.
800eeca4
JW		 9077
9078 The check is run once for each execution path encountered. In this case,
9079 a unique execution path is the sequence of instructions following a code
9080 entry point, e.g. the following has three execution paths, one starting
9081 at L0, one at L1, and one at L2.
197865e8 9082
800eeca4
JW		 9083 L0: nop
9084 L1: add
9085 L2: add
197865e8 9086 br.ret
800eeca4 9087*/
542d6675 9088
800eeca4
JW		 9089static void
9090check_dependencies (idesc)
542d6675 9091 struct ia64_opcode *idesc;
800eeca4
JW		 9092{
9093 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9094 int path;
9095 int i;
9096
9097 /* Note that the number of marked resources may change within the
197865e8 9098 loop if in auto mode. */
800eeca4
JW		 9099 i = 0;
9100 while (i < regdepslen)
9101 {
9102 struct rsrc *rs = &regdeps[i];
9103 const struct ia64_dependency *dep = rs->dependency;
9104 int chkind;
9105 int note;
9106 int start_over = 0;
9107
9108 if (dep->semantics == IA64_DVS_NONE
542d6675
KH		 9109 || (chkind = depends_on (rs->depind, idesc)) == -1)
9110 {
9111 ++i;
9112 continue;
9113 }
9114
9115 note = NOTE (opdeps->chks[chkind]);
9116
9117 /* Check this resource against each execution path seen thus far. */
9118 for (path = 0; path <= md.path; path++)
9119 {
9120 int matchtype;
9121
9122 /* If the dependency wasn't on the path being checked, ignore it. */
9123 if (rs->path < path)
9124 continue;
9125
9126 /* If the QP for this insn implies a QP which has branched, don't
9127 bother checking. Ed. NOTE: I don't think this check is terribly
9128 useful; what's the point of generating code which will only be
9129 reached if its QP is zero?
9130 This code was specifically inserted to handle the following code,
9131 based on notes from Intel's DV checking code, where p1 implies p2.
9132
9133 mov r4 = 2
9134 (p2) br.cond L
9135 (p1) mov r4 = 7
9136 */
9137 if (CURR_SLOT.qp_regno != 0)
9138 {
9139 int skip = 0;
9140 int implies;
9141 for (implies = 0; implies < qp_implieslen; implies++)
9142 {
9143 if (qp_implies[implies].path >= path
9144 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
9145 && qp_implies[implies].p2_branched)
9146 {
9147 skip = 1;
9148 break;
9149 }
9150 }
9151 if (skip)
9152 continue;
9153 }
9154
9155 if ((matchtype = resources_match (rs, idesc, note,
9156 CURR_SLOT.qp_regno, path)) != 0)
9157 {
9158 char msg[1024];
9159 char pathmsg[256] = "";
9160 char indexmsg[256] = "";
9161 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
9162
9163 if (path != 0)
9164 sprintf (pathmsg, " when entry is at label '%s'",
9165 md.entry_labels[path - 1]);
9166 if (rs->specific && rs->index != 0)
9167 sprintf (indexmsg, ", specific resource number is %d",
9168 rs->index);
9169 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9170 idesc->name,
9171 (certain ? "violates" : "may violate"),
9172 dv_mode[dep->mode], dep->name,
9173 dv_sem[dep->semantics],
9174 pathmsg, indexmsg);
9175
9176 if (md.explicit_mode)
9177 {
9178 as_warn ("%s", msg);
9179 if (path < md.path)
9180 as_warn (_("Only the first path encountering the conflict "
9181 "is reported"));
9182 as_warn_where (rs->file, rs->line,
9183 _("This is the location of the "
9184 "conflicting usage"));
9185 /* Don't bother checking other paths, to avoid duplicating
9186 the same warning */
9187 break;
9188 }
9189 else
9190 {
9191 if (md.debug_dv)
9192 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
9193
9194 remove_marked_resource (rs);
9195
9196 /* since the set of dependencies has changed, start over */
9197 /* FIXME -- since we're removing dvs as we go, we
9198 probably don't really need to start over... */
9199 start_over = 1;
9200 break;
9201 }
9202 }
9203 }
800eeca4 9204 if (start_over)
542d6675 9205 i = 0;
800eeca4 9206 else
542d6675 9207 ++i;
800eeca4
JW		 9208 }
9209}
9210
542d6675
KH		 9211/* Register new dependencies based on the given opcode. */
9212
800eeca4
JW		 9213static void
9214mark_resources (idesc)
542d6675 9215 struct ia64_opcode *idesc;
800eeca4
JW		 9216{
9217 int i;
9218 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9219 int add_only_qp_reads = 0;
9220
9221 /* A conditional branch only uses its resources if it is taken; if it is
9222 taken, we stop following that path. The other branch types effectively
9223 *always* write their resources. If it's not taken, register only QP
197865e8 9224 reads. */
800eeca4
JW		 9225 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
9226 {
9227 add_only_qp_reads = 1;
9228 }
9229
9230 if (md.debug_dv)
9231 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
9232
542d6675 9233 for (i = 0; i < opdeps->nregs; i++)
800eeca4
JW		 9234 {
9235 const struct ia64_dependency *dep;
9236 struct rsrc specs[MAX_SPECS];
9237 int note;
9238 int path;
9239 int count;
197865e8 9240
800eeca4 9241 dep = ia64_find_dependency (opdeps->regs[i]);
542d6675 9242 note = NOTE (opdeps->regs[i]);
800eeca4
JW		 9243
9244 if (add_only_qp_reads
542d6675
KH		 9245 && !(dep->mode == IA64_DV_WAR
9246 && (dep->specifier == IA64_RS_PR
139368c9 9247 || dep->specifier == IA64_RS_PRr
542d6675
KH		 9248 || dep->specifier == IA64_RS_PR63)))
9249 continue;
800eeca4
JW		 9250
9251 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
9252
9253#if 0
9254 if (md.debug_dv && !count)
542d6675
KH		 9255 fprintf (stderr, " No %s %s usage found (path %d)\n",
9256 dv_mode[dep->mode], dep->name, md.path);
800eeca4 9257#endif
197865e8 9258
800eeca4 9259 while (count-- > 0)
542d6675
KH		 9260 {
9261 mark_resource (idesc, dep, &specs[count],
9262 DEP (opdeps->regs[i]), md.path);
9263 }
800eeca4
JW		 9264
9265 /* The execution path may affect register values, which may in turn
542d6675 9266 affect which indirect-access resources are accessed. */
800eeca4 9267 switch (dep->specifier)
542d6675
KH		 9268 {
9269 default:
9270 break;
9271 case IA64_RS_CPUID:
9272 case IA64_RS_DBR:
9273 case IA64_RS_IBR:
800eeca4 9274 case IA64_RS_MSR:
542d6675
KH		 9275 case IA64_RS_PKR:
9276 case IA64_RS_PMC:
9277 case IA64_RS_PMD:
9278 case IA64_RS_RR:
9279 for (path = 0; path < md.path; path++)
9280 {
9281 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
9282 while (count-- > 0)
9283 mark_resource (idesc, dep, &specs[count],
9284 DEP (opdeps->regs[i]), path);
9285 }
9286 break;
9287 }
9288 }
9289}
9290
9291/* Remove dependencies when they no longer apply. */
9292
800eeca4
JW		 9293static void
9294update_dependencies (idesc)
542d6675 9295 struct ia64_opcode *idesc;
800eeca4
JW		 9296{
9297 int i;
9298
9299 if (strcmp (idesc->name, "srlz.i") == 0)
9300 {
9301 instruction_serialization ();
9302 }
9303 else if (strcmp (idesc->name, "srlz.d") == 0)
9304 {
9305 data_serialization ();
9306 }
9307 else if (is_interruption_or_rfi (idesc)
542d6675 9308 || is_taken_branch (idesc))
800eeca4 9309 {
542d6675
KH		 9310 /* Although technically the taken branch doesn't clear dependencies
9311 which require a srlz.[id], we don't follow the branch; the next
9312 instruction is assumed to start with a clean slate. */
800eeca4 9313 regdepslen = 0;
800eeca4
JW		 9314 md.path = 0;
9315 }
9316 else if (is_conditional_branch (idesc)
542d6675 9317 && CURR_SLOT.qp_regno != 0)
800eeca4
JW		 9318 {
9319 int is_call = strstr (idesc->name, ".call") != NULL;
9320
542d6675
KH		 9321 for (i = 0; i < qp_implieslen; i++)
9322 {
9323 /* If the conditional branch's predicate is implied by the predicate
9324 in an existing dependency, remove that dependency. */
9325 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
9326 {
9327 int depind = 0;
9328 /* Note that this implied predicate takes a branch so that if
9329 a later insn generates a DV but its predicate implies this
9330 one, we can avoid the false DV warning. */
9331 qp_implies[i].p2_branched = 1;
9332 while (depind < regdepslen)
9333 {
9334 if (regdeps[depind].qp_regno == qp_implies[i].p1)
9335 {
9336 print_dependency ("Removing", depind);
9337 regdeps[depind] = regdeps[--regdepslen];
9338 }
9339 else
9340 ++depind;
9341 }
9342 }
9343 }
800eeca4 9344 /* Any marked resources which have this same predicate should be
542d6675
KH		 9345 cleared, provided that the QP hasn't been modified between the
9346 marking instruction and the branch. */
800eeca4 9347 if (is_call)
542d6675
KH		 9348 {
9349 insn_group_break (0, CURR_SLOT.qp_regno, 1);
9350 }
800eeca4 9351 else
542d6675
KH		 9352 {
9353 i = 0;
9354 while (i < regdepslen)
9355 {
9356 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
9357 && regdeps[i].link_to_qp_branch
9358 && (regdeps[i].file != CURR_SLOT.src_file
9359 || regdeps[i].line != CURR_SLOT.src_line))
9360 {
9361 /* Treat like a taken branch */
9362 print_dependency ("Removing", i);
9363 regdeps[i] = regdeps[--regdepslen];
9364 }
9365 else
9366 ++i;
9367 }
9368 }
800eeca4
JW		 9369 }
9370}
9371
9372/* Examine the current instruction for dependency violations. */
542d6675 9373
800eeca4
JW		 9374static int
9375check_dv (idesc)
542d6675 9376 struct ia64_opcode *idesc;
800eeca4
JW		 9377{
9378 if (md.debug_dv)
9379 {
197865e8 9380 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
542d6675
KH		 9381 idesc->name, CURR_SLOT.src_line,
9382 idesc->dependencies->nchks,
9383 idesc->dependencies->nregs);
800eeca4
JW		 9384 }
9385
197865e8 9386 /* Look through the list of currently marked resources; if the current
800eeca4 9387 instruction has the dependency in its chks list which uses that resource,
542d6675 9388 check against the specific resources used. */
800eeca4
JW		 9389 check_dependencies (idesc);
9390
542d6675
KH		 9391 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9392 then add them to the list of marked resources. */
800eeca4
JW		 9393 mark_resources (idesc);
9394
9395 /* There are several types of dependency semantics, and each has its own
197865e8
KH		 9396 requirements for being cleared
9397
800eeca4
JW		 9398 Instruction serialization (insns separated by interruption, rfi, or
9399 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9400
9401 Data serialization (instruction serialization, or writer + srlz.d +
9402 reader, where writer and srlz.d are in separate groups) clears
9403 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9404 always be the case).
9405
9406 Instruction group break (groups separated by stop, taken branch,
9407 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9408 */
9409 update_dependencies (idesc);
9410
9411 /* Sometimes, knowing a register value allows us to avoid giving a false DV
197865e8 9412 warning. Keep track of as many as possible that are useful. */
800eeca4
JW		 9413 note_register_values (idesc);
9414
197865e8 9415 /* We don't need or want this anymore. */
800eeca4
JW		 9416 md.mem_offset.hint = 0;
9417
9418 return 0;
9419}
9420
9421/* Translate one line of assembly. Pseudo ops and labels do not show
9422 here. */
9423void
9424md_assemble (str)
9425 char *str;
9426{
9427 char *saved_input_line_pointer, *mnemonic;
9428 const struct pseudo_opcode *pdesc;
9429 struct ia64_opcode *idesc;
9430 unsigned char qp_regno;
9431 unsigned int flags;
9432 int ch;
9433
9434 saved_input_line_pointer = input_line_pointer;
9435 input_line_pointer = str;
9436
542d6675 9437 /* extract the opcode (mnemonic): */
800eeca4
JW		 9438
9439 mnemonic = input_line_pointer;
9440 ch = get_symbol_end ();
9441 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
9442 if (pdesc)
9443 {
9444 *input_line_pointer = ch;
9445 (*pdesc->handler) (pdesc->arg);
9446 goto done;
9447 }
9448
542d6675 9449 /* Find the instruction descriptor matching the arguments. */
800eeca4
JW		 9450
9451 idesc = ia64_find_opcode (mnemonic);
9452 *input_line_pointer = ch;
9453 if (!idesc)
9454 {
9455 as_bad ("Unknown opcode `%s'", mnemonic);
9456 goto done;
9457 }
9458
9459 idesc = parse_operands (idesc);
9460 if (!idesc)
9461 goto done;
9462
542d6675 9463 /* Handle the dynamic ops we can handle now: */
800eeca4
JW		 9464 if (idesc->type == IA64_TYPE_DYN)
9465 {
9466 if (strcmp (idesc->name, "add") == 0)
9467 {
9468 if (CURR_SLOT.opnd[2].X_op == O_register
9469 && CURR_SLOT.opnd[2].X_add_number < 4)
9470 mnemonic = "addl";
9471 else
9472 mnemonic = "adds";
3d56ab85 9473 ia64_free_opcode (idesc);
800eeca4
JW		 9474 idesc = ia64_find_opcode (mnemonic);
9475#if 0
9476 know (!idesc->next);
9477#endif
9478 }
9479 else if (strcmp (idesc->name, "mov") == 0)
9480 {
9481 enum ia64_opnd opnd1, opnd2;
9482 int rop;
9483
9484 opnd1 = idesc->operands[0];
9485 opnd2 = idesc->operands[1];
9486 if (opnd1 == IA64_OPND_AR3)
9487 rop = 0;
9488 else if (opnd2 == IA64_OPND_AR3)
9489 rop = 1;
9490 else
9491 abort ();
9492 if (CURR_SLOT.opnd[rop].X_op == O_register
9493 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
9494 mnemonic = "mov.i";
9495 else
9496 mnemonic = "mov.m";
3d56ab85 9497 ia64_free_opcode (idesc);
800eeca4
JW		 9498 idesc = ia64_find_opcode (mnemonic);
9499 while (idesc != NULL
9500 && (idesc->operands[0] != opnd1
9501 || idesc->operands[1] != opnd2))
9502 idesc = get_next_opcode (idesc);
9503 }
9504 }
9505
9506 qp_regno = 0;
9507 if (md.qp.X_op == O_register)
f1bcba5b
JW		 9508 {
9509 qp_regno = md.qp.X_add_number - REG_P;
9510 md.qp.X_op = O_absent;
9511 }
800eeca4
JW		 9512
9513 flags = idesc->flags;
9514
9515 if ((flags & IA64_OPCODE_FIRST) != 0)
9516 insn_group_break (1, 0, 0);
9517
9518 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
9519 {
9520 as_bad ("`%s' cannot be predicated", idesc->name);
9521 goto done;
9522 }
9523
542d6675 9524 /* Build the instruction. */
800eeca4
JW		 9525 CURR_SLOT.qp_regno = qp_regno;
9526 CURR_SLOT.idesc = idesc;
9527 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
4dc7ead9 9528 dwarf2_where (&CURR_SLOT.debug_line);
800eeca4
JW		 9529
9530 /* Add unwind entry, if there is one. */
e0c9811a 9531 if (unwind.current_entry)
800eeca4 9532 {
e0c9811a
JW		 9533 CURR_SLOT.unwind_record = unwind.current_entry;
9534 unwind.current_entry = NULL;
800eeca4
JW		 9535 }
9536
542d6675 9537 /* Check for dependency violations. */
800eeca4 9538 if (md.detect_dv)
542d6675 9539 check_dv (idesc);
800eeca4
JW		 9540
9541 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9542 if (++md.num_slots_in_use >= NUM_SLOTS)
9543 emit_one_bundle ();
9544
9545 if ((flags & IA64_OPCODE_LAST) != 0)
9546 insn_group_break (1, 0, 0);
9547
9548 md.last_text_seg = now_seg;
9549
9550 done:
9551 input_line_pointer = saved_input_line_pointer;
9552}
9553
9554/* Called when symbol NAME cannot be found in the symbol table.
9555 Should be used for dynamic valued symbols only. */
542d6675
KH		 9556
9557symbolS *
800eeca4 9558md_undefined_symbol (name)
2434f565 9559 char *name ATTRIBUTE_UNUSED;
800eeca4
JW		 9560{
9561 return 0;
9562}
9563
9564/* Called for any expression that can not be recognized. When the
9565 function is called, `input_line_pointer' will point to the start of
9566 the expression. */
542d6675 9567
800eeca4
JW		 9568void
9569md_operand (e)
9570 expressionS *e;
9571{
9572 enum pseudo_type pseudo_type;
e0c9811a 9573 const char *name;
800eeca4
JW		 9574 size_t len;
9575 int ch, i;
9576
9577 switch (*input_line_pointer)
9578 {
9579 case '@':
542d6675 9580 /* Find what relocation pseudo-function we're dealing with. */
800eeca4
JW		 9581 pseudo_type = 0;
9582 ch = *++input_line_pointer;
9583 for (i = 0; i < NELEMS (pseudo_func); ++i)
9584 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
9585 {
9586 len = strlen (pseudo_func[i].name);
9587 if (strncmp (pseudo_func[i].name + 1,
9588 input_line_pointer + 1, len - 1) == 0
9589 && !is_part_of_name (input_line_pointer[len]))
9590 {
9591 input_line_pointer += len;
9592 pseudo_type = pseudo_func[i].type;
9593 break;
9594 }
9595 }
9596 switch (pseudo_type)
9597 {
9598 case PSEUDO_FUNC_RELOC:
9599 SKIP_WHITESPACE ();
9600 if (*input_line_pointer != '(')
9601 {
9602 as_bad ("Expected '('");
9603 goto err;
9604 }
542d6675
KH		 9605 /* Skip '('. */
9606 ++input_line_pointer;
800eeca4
JW		 9607 expression (e);
9608 if (*input_line_pointer++ != ')')
9609 {
9610 as_bad ("Missing ')'");
9611 goto err;
9612 }
9613 if (e->X_op != O_symbol)
9614 {
9615 if (e->X_op != O_pseudo_fixup)
9616 {
9617 as_bad ("Not a symbolic expression");
9618 goto err;
9619 }
9620 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
9621 && i == FUNC_LT_RELATIVE)
9622 i = FUNC_LT_FPTR_RELATIVE;
9623 else
9624 {
9625 as_bad ("Illegal combination of relocation functions");
9626 goto err;
9627 }
9628 }
542d6675
KH		 9629 /* Make sure gas doesn't get rid of local symbols that are used
9630 in relocs. */
800eeca4
JW		 9631 e->X_op = O_pseudo_fixup;
9632 e->X_op_symbol = pseudo_func[i].u.sym;
9633 break;
9634
9635 case PSEUDO_FUNC_CONST:
9636 e->X_op = O_constant;
9637 e->X_add_number = pseudo_func[i].u.ival;
9638 break;
9639
e0c9811a
JW		 9640 case PSEUDO_FUNC_REG:
9641 e->X_op = O_register;
9642 e->X_add_number = pseudo_func[i].u.ival;
9643 break;
9644
800eeca4 9645 default:
e0c9811a
JW		 9646 name = input_line_pointer - 1;
9647 get_symbol_end ();
9648 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW		 9649 goto err;
9650 }
9651 break;
9652
9653 case '[':
9654 ++input_line_pointer;
9655 expression (e);
9656 if (*input_line_pointer != ']')
9657 {
9658 as_bad ("Closing bracket misssing");
9659 goto err;
9660 }
9661 else
9662 {
9663 if (e->X_op != O_register)
9664 as_bad ("Register expected as index");
9665
9666 ++input_line_pointer;
9667 e->X_op = O_index;
9668 }
9669 break;
9670
9671 default:
9672 break;
9673 }
9674 return;
9675
9676 err:
9677 ignore_rest_of_line ();
9678}
9679
9680/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9681 a section symbol plus some offset. For relocs involving @fptr(),
9682 directives we don't want such adjustments since we need to have the
9683 original symbol's name in the reloc. */
9684int
9685ia64_fix_adjustable (fix)
9686 fixS *fix;
9687{
9688 /* Prevent all adjustments to global symbols */
9689 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9690 return 0;
9691
9692 switch (fix->fx_r_type)
9693 {
9694 case BFD_RELOC_IA64_FPTR64I:
9695 case BFD_RELOC_IA64_FPTR32MSB:
9696 case BFD_RELOC_IA64_FPTR32LSB:
9697 case BFD_RELOC_IA64_FPTR64MSB:
9698 case BFD_RELOC_IA64_FPTR64LSB:
9699 case BFD_RELOC_IA64_LTOFF_FPTR22:
9700 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9701 return 0;
9702 default:
9703 break;
9704 }
9705
9706 return 1;
9707}
9708
9709int
9710ia64_force_relocation (fix)
9711 fixS *fix;
9712{
9713 switch (fix->fx_r_type)
9714 {
9715 case BFD_RELOC_IA64_FPTR64I:
9716 case BFD_RELOC_IA64_FPTR32MSB:
9717 case BFD_RELOC_IA64_FPTR32LSB:
9718 case BFD_RELOC_IA64_FPTR64MSB:
9719 case BFD_RELOC_IA64_FPTR64LSB:
9720
9721 case BFD_RELOC_IA64_LTOFF22:
9722 case BFD_RELOC_IA64_LTOFF64I:
9723 case BFD_RELOC_IA64_LTOFF_FPTR22:
9724 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9725 case BFD_RELOC_IA64_PLTOFF22:
9726 case BFD_RELOC_IA64_PLTOFF64I:
9727 case BFD_RELOC_IA64_PLTOFF64MSB:
9728 case BFD_RELOC_IA64_PLTOFF64LSB:
9729 return 1;
9730
9731 default:
9732 return 0;
9733 }
9734 return 0;
9735}
9736
9737/* Decide from what point a pc-relative relocation is relative to,
9738 relative to the pc-relative fixup. Er, relatively speaking. */
9739long
9740ia64_pcrel_from_section (fix, sec)
9741 fixS *fix;
9742 segT sec;
9743{
9744 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
197865e8 9745
800eeca4
JW		 9746 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
9747 off &= ~0xfUL;
9748
9749 return off;
9750}
9751
9752/* This is called whenever some data item (not an instruction) needs a
9753 fixup. We pick the right reloc code depending on the byteorder
9754 currently in effect. */
9755void
9756ia64_cons_fix_new (f, where, nbytes, exp)
9757 fragS *f;
9758 int where;
9759 int nbytes;
9760 expressionS *exp;
9761{
9762 bfd_reloc_code_real_type code;
9763 fixS *fix;
9764
9765 switch (nbytes)
9766 {
9767 /* There are no reloc for 8 and 16 bit quantities, but we allow
9768 them here since they will work fine as long as the expression
9769 is fully defined at the end of the pass over the source file. */
9770 case 1: code = BFD_RELOC_8; break;
9771 case 2: code = BFD_RELOC_16; break;
9772 case 4:
9773 if (target_big_endian)
9774 code = BFD_RELOC_IA64_DIR32MSB;
9775 else
9776 code = BFD_RELOC_IA64_DIR32LSB;
9777 break;
9778
9779 case 8:
9780 if (target_big_endian)
9781 code = BFD_RELOC_IA64_DIR64MSB;
9782 else
9783 code = BFD_RELOC_IA64_DIR64LSB;
9784 break;
9785
9786 default:
9787 as_bad ("Unsupported fixup size %d", nbytes);
9788 ignore_rest_of_line ();
9789 return;
9790 }
9791 if (exp->X_op == O_pseudo_fixup)
9792 {
9793 /* ??? */
9794 exp->X_op = O_symbol;
9795 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
9796 }
9797 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
9798 /* We need to store the byte order in effect in case we're going
9799 to fix an 8 or 16 bit relocation (for which there no real
9800 relocs available). See md_apply_fix(). */
9801 fix->tc_fix_data.bigendian = target_big_endian;
9802}
9803
9804/* Return the actual relocation we wish to associate with the pseudo
9805 reloc described by SYM and R_TYPE. SYM should be one of the
197865e8 9806 symbols in the pseudo_func array, or NULL. */
800eeca4
JW		 9807
9808static bfd_reloc_code_real_type
9809ia64_gen_real_reloc_type (sym, r_type)
9810 struct symbol *sym;
9811 bfd_reloc_code_real_type r_type;
9812{
9813 bfd_reloc_code_real_type new = 0;
9814
9815 if (sym == NULL)
9816 {
9817 return r_type;
9818 }
9819
9820 switch (S_GET_VALUE (sym))
9821 {
9822 case FUNC_FPTR_RELATIVE:
9823 switch (r_type)
9824 {
9825 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
9826 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
9827 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
9828 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
9829 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
9830 default: break;
9831 }
9832 break;
9833
9834 case FUNC_GP_RELATIVE:
9835 switch (r_type)
9836 {
9837 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
9838 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
9839 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
9840 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
9841 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
9842 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
9843 default: break;
9844 }
9845 break;
9846
9847 case FUNC_LT_RELATIVE:
9848 switch (r_type)
9849 {
9850 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
9851 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
9852 default: break;
9853 }
9854 break;
9855
c67e42c9
RH		 9856 case FUNC_PC_RELATIVE:
9857 switch (r_type)
9858 {
9859 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
9860 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
9861 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
9862 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
9863 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
9864 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
9865 default: break;
9866 }
9867 break;
9868
800eeca4
JW		 9869 case FUNC_PLT_RELATIVE:
9870 switch (r_type)
9871 {
9872 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
9873 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
9874 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
9875 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
9876 default: break;
9877 }
9878 break;
9879
9880 case FUNC_SEC_RELATIVE:
9881 switch (r_type)
9882 {
9883 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
9884 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
9885 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
9886 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
9887 default: break;
9888 }
9889 break;
9890
9891 case FUNC_SEG_RELATIVE:
9892 switch (r_type)
9893 {
9894 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
9895 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
9896 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
9897 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
9898 default: break;
9899 }
9900 break;
9901
9902 case FUNC_LTV_RELATIVE:
9903 switch (r_type)
9904 {
9905 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
9906 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
9907 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
9908 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
9909 default: break;
9910 }
9911 break;
9912
9913 case FUNC_LT_FPTR_RELATIVE:
9914 switch (r_type)
9915 {
9916 case BFD_RELOC_IA64_IMM22:
9917 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9918 case BFD_RELOC_IA64_IMM64:
9919 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9920 default:
9921 break;
9922 }
9923 break;
9924 default:
9925 abort ();
9926 }
9927 /* Hmmmm. Should this ever occur? */
9928 if (new)
9929 return new;
9930 else
9931 return r_type;
9932}
9933
9934/* Here is where generate the appropriate reloc for pseudo relocation
9935 functions. */
9936void
9937ia64_validate_fix (fix)
9938 fixS *fix;
9939{
9940 switch (fix->fx_r_type)
9941 {
9942 case BFD_RELOC_IA64_FPTR64I:
9943 case BFD_RELOC_IA64_FPTR32MSB:
9944 case BFD_RELOC_IA64_FPTR64LSB:
9945 case BFD_RELOC_IA64_LTOFF_FPTR22:
9946 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9947 if (fix->fx_offset != 0)
9948 as_bad_where (fix->fx_file, fix->fx_line,
9949 "No addend allowed in @fptr() relocation");
9950 break;
9951 default:
9952 break;
9953 }
9954
9955 return;
9956}
9957
9958static void
9959fix_insn (fix, odesc, value)
9960 fixS *fix;
9961 const struct ia64_operand *odesc;
9962 valueT value;
9963{
9964 bfd_vma insn[3], t0, t1, control_bits;
9965 const char *err;
9966 char *fixpos;
9967 long slot;
9968
9969 slot = fix->fx_where & 0x3;
9970 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9971
c67e42c9 9972 /* Bundles are always in little-endian byte order */
800eeca4
JW		 9973 t0 = bfd_getl64 (fixpos);
9974 t1 = bfd_getl64 (fixpos + 8);
9975 control_bits = t0 & 0x1f;
9976 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9977 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9978 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9979
c67e42c9
RH		 9980 err = NULL;
9981 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 9982 {
c67e42c9
RH		 9983 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9984 insn[2] |= (((value & 0x7f) << 13)
9985 | (((value >> 7) & 0x1ff) << 27)
9986 | (((value >> 16) & 0x1f) << 22)
9987 | (((value >> 21) & 0x1) << 21)
9988 | (((value >> 63) & 0x1) << 36));
800eeca4 9989 }
c67e42c9
RH		 9990 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9991 {
9992 if (value & ~0x3fffffffffffffffULL)
9993 err = "integer operand out of range";
9994 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9995 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9996 }
9997 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9998 {
9999 value >>= 4;
10000 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
10001 insn[2] |= ((((value >> 59) & 0x1) << 36)
10002 | (((value >> 0) & 0xfffff) << 13));
10003 }
10004 else
10005 err = (*odesc->insert) (odesc, value, insn + slot);
10006
10007 if (err)
10008 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW		 10009
10010 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
10011 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
44f5c83a
JW		 10012 number_to_chars_littleendian (fixpos + 0, t0, 8);
10013 number_to_chars_littleendian (fixpos + 8, t1, 8);
800eeca4
JW		 10014}
10015
10016/* Attempt to simplify or even eliminate a fixup. The return value is
10017 ignored; perhaps it was once meaningful, but now it is historical.
10018 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10019
10020 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
197865e8 10021 (if possible). */
800eeca4
JW		 10022int
10023md_apply_fix3 (fix, valuep, seg)
10024 fixS *fix;
10025 valueT *valuep;
2434f565 10026 segT seg ATTRIBUTE_UNUSED;
800eeca4
JW		 10027{
10028 char *fixpos;
10029 valueT value = *valuep;
10030 int adjust = 0;
10031
10032 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
10033
10034 if (fix->fx_pcrel)
10035 {
10036 switch (fix->fx_r_type)
10037 {
10038 case BFD_RELOC_IA64_DIR32MSB:
10039 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
10040 adjust = 1;
10041 break;
10042
10043 case BFD_RELOC_IA64_DIR32LSB:
10044 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
10045 adjust = 1;
10046 break;
10047
10048 case BFD_RELOC_IA64_DIR64MSB:
10049 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
10050 adjust = 1;
10051 break;
10052
10053 case BFD_RELOC_IA64_DIR64LSB:
10054 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
10055 adjust = 1;
10056 break;
10057
10058 default:
10059 break;
10060 }
10061 }
10062 if (fix->fx_addsy)
10063 {
fa1cb89c 10064 if (fix->fx_r_type == (int) BFD_RELOC_UNUSED)
800eeca4 10065 {
fa1cb89c
JW		 10066 /* This must be a TAG13 or TAG13b operand. There are no external
10067 relocs defined for them, so we must give an error. */
800eeca4
JW		 10068 as_bad_where (fix->fx_file, fix->fx_line,
10069 "%s must have a constant value",
10070 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
fa1cb89c
JW		 10071 fix->fx_done = 1;
10072 return 1;
800eeca4
JW		 10073 }
10074
10075 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
542d6675 10076 work. There should be a better way to handle this. */
800eeca4
JW		 10077 if (adjust)
10078 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
10079 }
10080 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
10081 {
10082 if (fix->tc_fix_data.bigendian)
10083 number_to_chars_bigendian (fixpos, value, fix->fx_size);
10084 else
10085 number_to_chars_littleendian (fixpos, value, fix->fx_size);
10086 fix->fx_done = 1;
10087 return 1;
10088 }
10089 else
10090 {
10091 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
10092 fix->fx_done = 1;
10093 return 1;
10094 }
10095 return 1;
10096}
10097
10098/* Generate the BFD reloc to be stuck in the object file from the
10099 fixup used internally in the assembler. */
542d6675
KH		 10100
10101arelent *
800eeca4 10102tc_gen_reloc (sec, fixp)
2434f565 10103 asection *sec ATTRIBUTE_UNUSED;
800eeca4
JW		 10104 fixS *fixp;
10105{
10106 arelent *reloc;
10107
10108 reloc = xmalloc (sizeof (*reloc));
10109 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10110 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10111 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
10112 reloc->addend = fixp->fx_offset;
10113 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
10114
10115 if (!reloc->howto)
10116 {
10117 as_bad_where (fixp->fx_file, fixp->fx_line,
10118 "Cannot represent %s relocation in object file",
10119 bfd_get_reloc_code_name (fixp->fx_r_type));
10120 }
10121 return reloc;
10122}
10123
10124/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 10125 of type TYPE, and store the appropriate bytes in *LIT. The number
10126 of LITTLENUMS emitted is stored in *SIZE. An error message is
800eeca4
JW		 10127 returned, or NULL on OK. */
10128
10129#define MAX_LITTLENUMS 5
10130
542d6675 10131char *
800eeca4
JW		 10132md_atof (type, lit, size)
10133 int type;
10134 char *lit;
10135 int *size;
10136{
10137 LITTLENUM_TYPE words[MAX_LITTLENUMS];
10138 LITTLENUM_TYPE *word;
10139 char *t;
10140 int prec;
10141
10142 switch (type)
10143 {
10144 /* IEEE floats */
10145 case 'f':
10146 case 'F':
10147 case 's':
10148 case 'S':
10149 prec = 2;
10150 break;
10151
10152 case 'd':
10153 case 'D':
10154 case 'r':
10155 case 'R':
10156 prec = 4;
10157 break;
10158
10159 case 'x':
10160 case 'X':
10161 case 'p':
10162 case 'P':
10163 prec = 5;
10164 break;
10165
10166 default:
10167 *size = 0;
10168 return "Bad call to MD_ATOF()";
10169 }
10170 t = atof_ieee (input_line_pointer, type, words);
10171 if (t)
10172 input_line_pointer = t;
10173 *size = prec * sizeof (LITTLENUM_TYPE);
10174
10175 for (word = words + prec - 1; prec--;)
10176 {
10177 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
10178 lit += sizeof (LITTLENUM_TYPE);
10179 }
10180 return 0;
10181}
10182
10183/* Round up a section's size to the appropriate boundary. */
10184valueT
10185md_section_align (seg, size)
10186 segT seg;
10187 valueT size;
10188{
10189 int align = bfd_get_section_alignment (stdoutput, seg);
197865e8 10190 valueT mask = ((valueT) 1 << align) - 1;
800eeca4
JW		 10191
10192 return (size + mask) & ~mask;
10193}
10194
10195/* Handle ia64 specific semantics of the align directive. */
10196
0a9ef439 10197void
800eeca4 10198ia64_md_do_align (n, fill, len, max)
91a2ae2a
RH		 10199 int n ATTRIBUTE_UNUSED;
10200 const char *fill ATTRIBUTE_UNUSED;
2434f565 10201 int len ATTRIBUTE_UNUSED;
91a2ae2a 10202 int max ATTRIBUTE_UNUSED;
800eeca4 10203{
0a9ef439 10204 if (subseg_text_p (now_seg))
800eeca4 10205 ia64_flush_insns ();
0a9ef439 10206}
800eeca4 10207
0a9ef439
RH		 10208/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10209 of an rs_align_code fragment. */
800eeca4 10210
0a9ef439
RH		 10211void
10212ia64_handle_align (fragp)
10213 fragS *fragp;
10214{
10215 /* Use mfi bundle of nops with no stop bits. */
10216 static const unsigned char be_nop[]
10217 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10218 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10219 static const unsigned char le_nop[]
10220 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10221 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10222
10223 int bytes;
10224 char *p;
10225
10226 if (fragp->fr_type != rs_align_code)
10227 return;
10228
10229 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
10230 p = fragp->fr_literal + fragp->fr_fix;
10231
10232 /* Make sure we are on a 16-byte boundary, in case someone has been
10233 putting data into a text section. */
10234 if (bytes & 15)
10235 {
10236 int fix = bytes & 15;
10237 memset (p, 0, fix);
10238 p += fix;
10239 bytes -= fix;
10240 fragp->fr_fix += fix;
800eeca4
JW		 10241 }
10242
0a9ef439
RH		 10243 memcpy (p, (target_big_endian ? be_nop : le_nop), 16);
10244 fragp->fr_var = 16;
800eeca4 10245}
GDB Binutils - Deliverables
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