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[deliverable/binutils-gdb.git] / gas / config / tc-ia64.c
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800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
b3dfd7fe 2 Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
800eeca4
JW		 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
800eeca4
JW		 35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
542d6675
KH		 38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
800eeca4
JW		 42
43 */
44
45#include "as.h"
3882b010 46#include "safe-ctype.h"
800eeca4
JW		 47#include "dwarf2dbg.h"
48#include "subsegs.h"
49
50#include "opcode/ia64.h"
51
52#include "elf/ia64.h"
53
54#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
55#define MIN(a,b) ((a) < (b) ? (a) : (b))
56
57#define NUM_SLOTS 4
58#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
59#define CURR_SLOT md.slot[md.curr_slot]
60
61#define O_pseudo_fixup (O_max + 1)
62
63enum special_section
64 {
557debba 65 /* IA-64 ABI section pseudo-ops. */
800eeca4
JW		 66 SPECIAL_SECTION_BSS = 0,
67 SPECIAL_SECTION_SBSS,
68 SPECIAL_SECTION_SDATA,
69 SPECIAL_SECTION_RODATA,
70 SPECIAL_SECTION_COMMENT,
71 SPECIAL_SECTION_UNWIND,
557debba
JW		 72 SPECIAL_SECTION_UNWIND_INFO,
73 /* HPUX specific section pseudo-ops. */
74 SPECIAL_SECTION_INIT_ARRAY,
75 SPECIAL_SECTION_FINI_ARRAY,
800eeca4
JW		 76 };
77
78enum reloc_func
79 {
13ae64f3
JJ		 80 FUNC_DTP_MODULE,
81 FUNC_DTP_RELATIVE,
800eeca4
JW		 82 FUNC_FPTR_RELATIVE,
83 FUNC_GP_RELATIVE,
84 FUNC_LT_RELATIVE,
fa2c7eff 85 FUNC_LT_RELATIVE_X,
c67e42c9 86 FUNC_PC_RELATIVE,
800eeca4
JW		 87 FUNC_PLT_RELATIVE,
88 FUNC_SEC_RELATIVE,
89 FUNC_SEG_RELATIVE,
13ae64f3 90 FUNC_TP_RELATIVE,
800eeca4
JW		 91 FUNC_LTV_RELATIVE,
92 FUNC_LT_FPTR_RELATIVE,
13ae64f3
JJ		 93 FUNC_LT_DTP_MODULE,
94 FUNC_LT_DTP_RELATIVE,
95 FUNC_LT_TP_RELATIVE,
3969b680 96 FUNC_IPLT_RELOC,
800eeca4
JW		 97 };
98
99enum reg_symbol
100 {
101 REG_GR = 0,
102 REG_FR = (REG_GR + 128),
103 REG_AR = (REG_FR + 128),
104 REG_CR = (REG_AR + 128),
105 REG_P = (REG_CR + 128),
106 REG_BR = (REG_P + 64),
107 REG_IP = (REG_BR + 8),
108 REG_CFM,
109 REG_PR,
110 REG_PR_ROT,
111 REG_PSR,
112 REG_PSR_L,
113 REG_PSR_UM,
114 /* The following are pseudo-registers for use by gas only. */
115 IND_CPUID,
116 IND_DBR,
117 IND_DTR,
118 IND_ITR,
119 IND_IBR,
120 IND_MEM,
121 IND_MSR,
122 IND_PKR,
123 IND_PMC,
124 IND_PMD,
125 IND_RR,
542d6675 126 /* The following pseudo-registers are used for unwind directives only: */
e0c9811a
JW		 127 REG_PSP,
128 REG_PRIUNAT,
800eeca4
JW		 129 REG_NUM
130 };
131
132enum dynreg_type
133 {
134 DYNREG_GR = 0, /* dynamic general purpose register */
135 DYNREG_FR, /* dynamic floating point register */
136 DYNREG_PR, /* dynamic predicate register */
137 DYNREG_NUM_TYPES
138 };
139
87f8eb97
JW		 140enum operand_match_result
141 {
142 OPERAND_MATCH,
143 OPERAND_OUT_OF_RANGE,
144 OPERAND_MISMATCH
145 };
146
800eeca4
JW		 147/* On the ia64, we can't know the address of a text label until the
148 instructions are packed into a bundle. To handle this, we keep
149 track of the list of labels that appear in front of each
150 instruction. */
151struct label_fix
542d6675
KH		 152{
153 struct label_fix *next;
154 struct symbol *sym;
155};
800eeca4
JW		 156
157extern int target_big_endian;
158
159/* Characters which always start a comment. */
160const char comment_chars[] = "";
161
162/* Characters which start a comment at the beginning of a line. */
163const char line_comment_chars[] = "#";
164
165/* Characters which may be used to separate multiple commands on a
166 single line. */
167const char line_separator_chars[] = ";";
168
169/* Characters which are used to indicate an exponent in a floating
170 point number. */
171const char EXP_CHARS[] = "eE";
172
173/* Characters which mean that a number is a floating point constant,
174 as in 0d1.0. */
175const char FLT_CHARS[] = "rRsSfFdDxXpP";
176
542d6675 177/* ia64-specific option processing: */
800eeca4 178
44f5c83a 179const char *md_shortopts = "m:N:x::";
800eeca4
JW		 180
181struct option md_longopts[] =
182 {
c43c2cc5
JW		 183#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
184 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
185#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
186 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
800eeca4
JW		 187 };
188
189size_t md_longopts_size = sizeof (md_longopts);
190
191static struct
192 {
193 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
194 struct hash_control *reg_hash; /* register name hash table */
195 struct hash_control *dynreg_hash; /* dynamic register hash table */
196 struct hash_control *const_hash; /* constant hash table */
197 struct hash_control *entry_hash; /* code entry hint hash table */
198
199 symbolS *regsym[REG_NUM];
200
201 /* If X_op is != O_absent, the registername for the instruction's
202 qualifying predicate. If NULL, p0 is assumed for instructions
203 that are predicatable. */
204 expressionS qp;
205
206 unsigned int
197865e8 207 manual_bundling : 1,
800eeca4
JW		 208 debug_dv: 1,
209 detect_dv: 1,
210 explicit_mode : 1, /* which mode we're in */
211 default_explicit_mode : 1, /* which mode is the default */
212 mode_explicitly_set : 1, /* was the current mode explicitly set? */
4d5a53ff
JW		 213 auto_align : 1,
214 keep_pending_output : 1;
800eeca4
JW		 215
216 /* Each bundle consists of up to three instructions. We keep
217 track of four most recent instructions so we can correctly set
197865e8 218 the end_of_insn_group for the last instruction in a bundle. */
800eeca4
JW		 219 int curr_slot;
220 int num_slots_in_use;
221 struct slot
222 {
223 unsigned int
224 end_of_insn_group : 1,
225 manual_bundling_on : 1,
226 manual_bundling_off : 1;
227 signed char user_template; /* user-selected template, if any */
228 unsigned char qp_regno; /* qualifying predicate */
229 /* This duplicates a good fraction of "struct fix" but we
230 can't use a "struct fix" instead since we can't call
231 fix_new_exp() until we know the address of the instruction. */
232 int num_fixups;
233 struct insn_fix
234 {
235 bfd_reloc_code_real_type code;
236 enum ia64_opnd opnd; /* type of operand in need of fix */
237 unsigned int is_pcrel : 1; /* is operand pc-relative? */
238 expressionS expr; /* the value to be inserted */
239 }
240 fixup[2]; /* at most two fixups per insn */
241 struct ia64_opcode *idesc;
242 struct label_fix *label_fixups;
f1bcba5b 243 struct label_fix *tag_fixups;
800eeca4
JW		 244 struct unw_rec_list *unwind_record; /* Unwind directive. */
245 expressionS opnd[6];
246 char *src_file;
247 unsigned int src_line;
248 struct dwarf2_line_info debug_line;
249 }
250 slot[NUM_SLOTS];
251
252 segT last_text_seg;
253
254 struct dynreg
255 {
256 struct dynreg *next; /* next dynamic register */
257 const char *name;
258 unsigned short base; /* the base register number */
259 unsigned short num_regs; /* # of registers in this set */
260 }
261 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
262
263 flagword flags; /* ELF-header flags */
264
265 struct mem_offset {
266 unsigned hint:1; /* is this hint currently valid? */
267 bfd_vma offset; /* mem.offset offset */
268 bfd_vma base; /* mem.offset base */
269 } mem_offset;
270
271 int path; /* number of alt. entry points seen */
272 const char **entry_labels; /* labels of all alternate paths in
542d6675 273 the current DV-checking block. */
800eeca4 274 int maxpaths; /* size currently allocated for
542d6675 275 entry_labels */
88be23ec
BS		 276 /* Support for hardware errata workarounds. */
277
278 /* Record data about the last three insn groups. */
279 struct group
280 {
281 /* B-step workaround.
282 For each predicate register, this is set if the corresponding insn
283 group conditionally sets this register with one of the affected
284 instructions. */
285 int p_reg_set[64];
286 /* B-step workaround.
287 For each general register, this is set if the corresponding insn
288 a) is conditional one one of the predicate registers for which
289 P_REG_SET is 1 in the corresponding entry of the previous group,
290 b) sets this general register with one of the affected
291 instructions. */
292 int g_reg_set_conditionally[128];
293 } last_groups[3];
294 int group_idx;
557debba
JW		 295
296 int pointer_size; /* size in bytes of a pointer */
297 int pointer_size_shift; /* shift size of a pointer for alignment */
800eeca4
JW		 298 }
299md;
300
542d6675 301/* application registers: */
800eeca4 302
e0c9811a
JW		 303#define AR_K0 0
304#define AR_K7 7
305#define AR_RSC 16
306#define AR_BSP 17
307#define AR_BSPSTORE 18
308#define AR_RNAT 19
309#define AR_UNAT 36
310#define AR_FPSR 40
311#define AR_ITC 44
312#define AR_PFS 64
313#define AR_LC 65
800eeca4
JW		 314
315static const struct
316 {
317 const char *name;
318 int regnum;
319 }
320ar[] =
321 {
322 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
323 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
324 {"ar.rsc", 16}, {"ar.bsp", 17},
325 {"ar.bspstore", 18}, {"ar.rnat", 19},
326 {"ar.fcr", 21}, {"ar.eflag", 24},
327 {"ar.csd", 25}, {"ar.ssd", 26},
328 {"ar.cflg", 27}, {"ar.fsr", 28},
329 {"ar.fir", 29}, {"ar.fdr", 30},
330 {"ar.ccv", 32}, {"ar.unat", 36},
331 {"ar.fpsr", 40}, {"ar.itc", 44},
332 {"ar.pfs", 64}, {"ar.lc", 65},
197865e8 333 {"ar.ec", 66},
800eeca4
JW		 334 };
335
336#define CR_IPSR 16
337#define CR_ISR 17
338#define CR_IIP 19
339#define CR_IFA 20
340#define CR_ITIR 21
341#define CR_IIPA 22
342#define CR_IFS 23
343#define CR_IIM 24
344#define CR_IHA 25
345#define CR_IVR 65
346#define CR_TPR 66
347#define CR_EOI 67
348#define CR_IRR0 68
349#define CR_IRR3 71
350#define CR_LRR0 80
351#define CR_LRR1 81
352
542d6675 353/* control registers: */
800eeca4
JW		 354static const struct
355 {
356 const char *name;
357 int regnum;
358 }
359cr[] =
360 {
361 {"cr.dcr", 0},
362 {"cr.itm", 1},
363 {"cr.iva", 2},
364 {"cr.pta", 8},
365 {"cr.gpta", 9},
366 {"cr.ipsr", 16},
367 {"cr.isr", 17},
368 {"cr.iip", 19},
369 {"cr.ifa", 20},
370 {"cr.itir", 21},
371 {"cr.iipa", 22},
372 {"cr.ifs", 23},
373 {"cr.iim", 24},
374 {"cr.iha", 25},
375 {"cr.lid", 64},
376 {"cr.ivr", 65},
377 {"cr.tpr", 66},
378 {"cr.eoi", 67},
379 {"cr.irr0", 68},
380 {"cr.irr1", 69},
381 {"cr.irr2", 70},
382 {"cr.irr3", 71},
383 {"cr.itv", 72},
384 {"cr.pmv", 73},
385 {"cr.cmcv", 74},
386 {"cr.lrr0", 80},
387 {"cr.lrr1", 81}
388 };
389
390#define PSR_MFL 4
391#define PSR_IC 13
392#define PSR_DFL 18
393#define PSR_CPL 32
394
395static const struct const_desc
396 {
397 const char *name;
398 valueT value;
399 }
400const_bits[] =
401 {
542d6675 402 /* PSR constant masks: */
800eeca4
JW		 403
404 /* 0: reserved */
405 {"psr.be", ((valueT) 1) << 1},
406 {"psr.up", ((valueT) 1) << 2},
407 {"psr.ac", ((valueT) 1) << 3},
408 {"psr.mfl", ((valueT) 1) << 4},
409 {"psr.mfh", ((valueT) 1) << 5},
410 /* 6-12: reserved */
411 {"psr.ic", ((valueT) 1) << 13},
412 {"psr.i", ((valueT) 1) << 14},
413 {"psr.pk", ((valueT) 1) << 15},
414 /* 16: reserved */
415 {"psr.dt", ((valueT) 1) << 17},
416 {"psr.dfl", ((valueT) 1) << 18},
417 {"psr.dfh", ((valueT) 1) << 19},
418 {"psr.sp", ((valueT) 1) << 20},
419 {"psr.pp", ((valueT) 1) << 21},
420 {"psr.di", ((valueT) 1) << 22},
421 {"psr.si", ((valueT) 1) << 23},
422 {"psr.db", ((valueT) 1) << 24},
423 {"psr.lp", ((valueT) 1) << 25},
424 {"psr.tb", ((valueT) 1) << 26},
425 {"psr.rt", ((valueT) 1) << 27},
426 /* 28-31: reserved */
427 /* 32-33: cpl (current privilege level) */
428 {"psr.is", ((valueT) 1) << 34},
429 {"psr.mc", ((valueT) 1) << 35},
430 {"psr.it", ((valueT) 1) << 36},
431 {"psr.id", ((valueT) 1) << 37},
432 {"psr.da", ((valueT) 1) << 38},
433 {"psr.dd", ((valueT) 1) << 39},
434 {"psr.ss", ((valueT) 1) << 40},
435 /* 41-42: ri (restart instruction) */
436 {"psr.ed", ((valueT) 1) << 43},
437 {"psr.bn", ((valueT) 1) << 44},
438 };
439
542d6675 440/* indirect register-sets/memory: */
800eeca4
JW		 441
442static const struct
443 {
444 const char *name;
445 int regnum;
446 }
447indirect_reg[] =
448 {
449 { "CPUID", IND_CPUID },
450 { "cpuid", IND_CPUID },
451 { "dbr", IND_DBR },
452 { "dtr", IND_DTR },
453 { "itr", IND_ITR },
454 { "ibr", IND_IBR },
455 { "msr", IND_MSR },
456 { "pkr", IND_PKR },
457 { "pmc", IND_PMC },
458 { "pmd", IND_PMD },
459 { "rr", IND_RR },
460 };
461
462/* Pseudo functions used to indicate relocation types (these functions
463 start with an at sign (@). */
464static struct
465 {
466 const char *name;
467 enum pseudo_type
468 {
469 PSEUDO_FUNC_NONE,
470 PSEUDO_FUNC_RELOC,
471 PSEUDO_FUNC_CONST,
e0c9811a 472 PSEUDO_FUNC_REG,
800eeca4
JW		 473 PSEUDO_FUNC_FLOAT
474 }
475 type;
476 union
477 {
478 unsigned long ival;
479 symbolS *sym;
480 }
481 u;
482 }
483pseudo_func[] =
484 {
542d6675 485 /* reloc pseudo functions (these must come first!): */
13ae64f3
JJ		 486 { "dtpmod", PSEUDO_FUNC_RELOC, { 0 } },
487 { "dtprel", PSEUDO_FUNC_RELOC, { 0 } },
2434f565
JW		 488 { "fptr", PSEUDO_FUNC_RELOC, { 0 } },
489 { "gprel", PSEUDO_FUNC_RELOC, { 0 } },
490 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } },
fa2c7eff 491 { "ltoffx", PSEUDO_FUNC_RELOC, { 0 } },
2434f565
JW		 492 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } },
493 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } },
494 { "secrel", PSEUDO_FUNC_RELOC, { 0 } },
495 { "segrel", PSEUDO_FUNC_RELOC, { 0 } },
13ae64f3 496 { "tprel", PSEUDO_FUNC_RELOC, { 0 } },
2434f565
JW		 497 { "ltv", PSEUDO_FUNC_RELOC, { 0 } },
498 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
13ae64f3
JJ		 499 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */
500 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */
501 { "", 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */
3969b680 502 { "iplt", PSEUDO_FUNC_RELOC, { 0 } },
800eeca4 503
542d6675 504 /* mbtype4 constants: */
800eeca4
JW		 505 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
506 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
507 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
508 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
509 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
510
542d6675 511 /* fclass constants: */
bf3ca999 512 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
800eeca4
JW		 513 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
514 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
515 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
516 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
517 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
518 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
519 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
520 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
TW		 521
522 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a 523
c10d9d8f
JW		 524 /* hint constants: */
525 { "pause", PSEUDO_FUNC_CONST, { 0x0 } },
526
542d6675 527 /* unwind-related constants: */
e0c9811a
JW		 528 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
529 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
530 { "nt", PSEUDO_FUNC_CONST, { 2 } },
531
542d6675 532 /* unwind-related registers: */
e0c9811a 533 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
800eeca4
JW		 534 };
535
542d6675 536/* 41-bit nop opcodes (one per unit): */
800eeca4
JW		 537static const bfd_vma nop[IA64_NUM_UNITS] =
538 {
539 0x0000000000LL, /* NIL => break 0 */
540 0x0008000000LL, /* I-unit nop */
541 0x0008000000LL, /* M-unit nop */
542 0x4000000000LL, /* B-unit nop */
543 0x0008000000LL, /* F-unit nop */
544 0x0008000000LL, /* L-"unit" nop */
545 0x0008000000LL, /* X-unit nop */
546 };
547
548/* Can't be `const' as it's passed to input routines (which have the
549 habit of setting temporary sentinels. */
550static char special_section_name[][20] =
551 {
552 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
557debba
JW		 553 {".IA_64.unwind"}, {".IA_64.unwind_info"},
554 {".init_array"}, {".fini_array"}
800eeca4
JW		 555 };
556
579f31ac
JJ		 557static char *special_linkonce_name[] =
558 {
559 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
560 };
561
800eeca4
JW		 562/* The best template for a particular sequence of up to three
563 instructions: */
564#define N IA64_NUM_TYPES
565static unsigned char best_template[N][N][N];
566#undef N
567
568/* Resource dependencies currently in effect */
569static struct rsrc {
570 int depind; /* dependency index */
571 const struct ia64_dependency *dependency; /* actual dependency */
572 unsigned specific:1, /* is this a specific bit/regno? */
573 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
574 int index; /* specific regno/bit within dependency */
575 int note; /* optional qualifying note (0 if none) */
576#define STATE_NONE 0
577#define STATE_STOP 1
578#define STATE_SRLZ 2
579 int insn_srlz; /* current insn serialization state */
580 int data_srlz; /* current data serialization state */
581 int qp_regno; /* qualifying predicate for this usage */
582 char *file; /* what file marked this dependency */
2434f565 583 unsigned int line; /* what line marked this dependency */
800eeca4 584 struct mem_offset mem_offset; /* optional memory offset hint */
7484b8e6 585 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
800eeca4
JW		 586 int path; /* corresponding code entry index */
587} *regdeps = NULL;
588static int regdepslen = 0;
589static int regdepstotlen = 0;
590static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
591static const char *dv_sem[] = { "none", "implied", "impliedf",
139368c9 592 "data", "instr", "specific", "stop", "other" };
7484b8e6 593static const char *dv_cmp_type[] = { "none", "OR", "AND" };
800eeca4
JW		 594
595/* Current state of PR mutexation */
596static struct qpmutex {
597 valueT prmask;
598 int path;
599} *qp_mutexes = NULL; /* QP mutex bitmasks */
600static int qp_mutexeslen = 0;
601static int qp_mutexestotlen = 0;
197865e8 602static valueT qp_safe_across_calls = 0;
800eeca4
JW		 603
604/* Current state of PR implications */
605static struct qp_imply {
606 unsigned p1:6;
607 unsigned p2:6;
608 unsigned p2_branched:1;
609 int path;
610} *qp_implies = NULL;
611static int qp_implieslen = 0;
612static int qp_impliestotlen = 0;
613
197865e8
KH		 614/* Keep track of static GR values so that indirect register usage can
615 sometimes be tracked. */
800eeca4
JW		 616static struct gr {
617 unsigned known:1;
618 int path;
619 valueT value;
2434f565 620} gr_values[128] = {{ 1, 0, 0 }};
800eeca4
JW		 621
622/* These are the routines required to output the various types of
623 unwind records. */
624
f5a30c2e
JW		 625/* A slot_number is a frag address plus the slot index (0-2). We use the
626 frag address here so that if there is a section switch in the middle of
627 a function, then instructions emitted to a different section are not
628 counted. Since there may be more than one frag for a function, this
629 means we also need to keep track of which frag this address belongs to
630 so we can compute inter-frag distances. This also nicely solves the
631 problem with nops emitted for align directives, which can't easily be
632 counted, but can easily be derived from frag sizes. */
633
800eeca4
JW		 634typedef struct unw_rec_list {
635 unwind_record r;
e0c9811a 636 unsigned long slot_number;
f5a30c2e 637 fragS *slot_frag;
800eeca4
JW		 638 struct unw_rec_list *next;
639} unw_rec_list;
640
2434f565 641#define SLOT_NUM_NOT_SET (unsigned)-1
800eeca4 642
6290819d
NC		 643/* Linked list of saved prologue counts. A very poor
644 implementation of a map from label numbers to prologue counts. */
645typedef struct label_prologue_count
646{
647 struct label_prologue_count *next;
648 unsigned long label_number;
649 unsigned int prologue_count;
650} label_prologue_count;
651
e0c9811a
JW		 652static struct
653{
654 unsigned long next_slot_number;
f5a30c2e 655 fragS *next_slot_frag;
e0c9811a
JW		 656
657 /* Maintain a list of unwind entries for the current function. */
658 unw_rec_list *list;
659 unw_rec_list *tail;
800eeca4 660
e0c9811a
JW		 661 /* Any unwind entires that should be attached to the current slot
662 that an insn is being constructed for. */
663 unw_rec_list *current_entry;
800eeca4 664
e0c9811a
JW		 665 /* These are used to create the unwind table entry for this function. */
666 symbolS *proc_start;
667 symbolS *proc_end;
668 symbolS *info; /* pointer to unwind info */
669 symbolS *personality_routine;
91a2ae2a
RH		 670 segT saved_text_seg;
671 subsegT saved_text_subseg;
672 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */
800eeca4 673
e0c9811a
JW		 674 /* TRUE if processing unwind directives in a prologue region. */
675 int prologue;
30d25259 676 int prologue_mask;
33d01f33 677 unsigned int prologue_count; /* number of .prologues seen so far */
6290819d
NC		 678 /* Prologue counts at previous .label_state directives. */
679 struct label_prologue_count * saved_prologue_counts;
e0c9811a 680} unwind;
800eeca4
JW		 681
682typedef void (*vbyte_func) PARAMS ((int, char *, char *));
683
542d6675 684/* Forward delarations: */
800eeca4
JW		 685static int ar_is_in_integer_unit PARAMS ((int regnum));
686static void set_section PARAMS ((char *name));
687static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
688 unsigned int, unsigned int));
689static void dot_radix PARAMS ((int));
690static void dot_special_section PARAMS ((int));
691static void dot_proc PARAMS ((int));
692static void dot_fframe PARAMS ((int));
693static void dot_vframe PARAMS ((int));
150f24a2
JW		 694static void dot_vframesp PARAMS ((int));
695static void dot_vframepsp PARAMS ((int));
800eeca4
JW		 696static void dot_save PARAMS ((int));
697static void dot_restore PARAMS ((int));
150f24a2
JW		 698static void dot_restorereg PARAMS ((int));
699static void dot_restorereg_p PARAMS ((int));
800eeca4
JW		 700static void dot_handlerdata PARAMS ((int));
701static void dot_unwentry PARAMS ((int));
702static void dot_altrp PARAMS ((int));
e0c9811a 703static void dot_savemem PARAMS ((int));
800eeca4
JW		 704static void dot_saveg PARAMS ((int));
705static void dot_savef PARAMS ((int));
706static void dot_saveb PARAMS ((int));
707static void dot_savegf PARAMS ((int));
708static void dot_spill PARAMS ((int));
150f24a2
JW		 709static void dot_spillreg PARAMS ((int));
710static void dot_spillmem PARAMS ((int));
711static void dot_spillreg_p PARAMS ((int));
712static void dot_spillmem_p PARAMS ((int));
713static void dot_label_state PARAMS ((int));
714static void dot_copy_state PARAMS ((int));
800eeca4
JW		 715static void dot_unwabi PARAMS ((int));
716static void dot_personality PARAMS ((int));
717static void dot_body PARAMS ((int));
718static void dot_prologue PARAMS ((int));
719static void dot_endp PARAMS ((int));
720static void dot_template PARAMS ((int));
721static void dot_regstk PARAMS ((int));
722static void dot_rot PARAMS ((int));
723static void dot_byteorder PARAMS ((int));
724static void dot_psr PARAMS ((int));
725static void dot_alias PARAMS ((int));
726static void dot_ln PARAMS ((int));
727static char *parse_section_name PARAMS ((void));
728static void dot_xdata PARAMS ((int));
729static void stmt_float_cons PARAMS ((int));
730static void stmt_cons_ua PARAMS ((int));
731static void dot_xfloat_cons PARAMS ((int));
732static void dot_xstringer PARAMS ((int));
733static void dot_xdata_ua PARAMS ((int));
734static void dot_xfloat_cons_ua PARAMS ((int));
150f24a2 735static void print_prmask PARAMS ((valueT mask));
800eeca4
JW		 736static void dot_pred_rel PARAMS ((int));
737static void dot_reg_val PARAMS ((int));
738static void dot_dv_mode PARAMS ((int));
739static void dot_entry PARAMS ((int));
740static void dot_mem_offset PARAMS ((int));
e0c9811a 741static void add_unwind_entry PARAMS((unw_rec_list *ptr));
542d6675 742static symbolS *declare_register PARAMS ((const char *name, int regnum));
800eeca4
JW		 743static void declare_register_set PARAMS ((const char *, int, int));
744static unsigned int operand_width PARAMS ((enum ia64_opnd));
87f8eb97
JW		 745static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc,
746 int index,
747 expressionS *e));
800eeca4
JW		 748static int parse_operand PARAMS ((expressionS *e));
749static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
86cf98f3 750static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit));
800eeca4
JW		 751static void build_insn PARAMS ((struct slot *, bfd_vma *));
752static void emit_one_bundle PARAMS ((void));
753static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
197865e8 754static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
800eeca4
JW		 755 bfd_reloc_code_real_type r_type));
756static void insn_group_break PARAMS ((int, int, int));
150f24a2
JW		 757static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
758 struct rsrc *, int depind, int path));
800eeca4
JW		 759static void add_qp_mutex PARAMS((valueT mask));
760static void add_qp_imply PARAMS((int p1, int p2));
761static void clear_qp_branch_flag PARAMS((valueT mask));
762static void clear_qp_mutex PARAMS((valueT mask));
763static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
cb5301b6 764static int has_suffix_p PARAMS((const char *, const char *));
800eeca4
JW		 765static void clear_register_values PARAMS ((void));
766static void print_dependency PARAMS ((const char *action, int depind));
150f24a2
JW		 767static void instruction_serialization PARAMS ((void));
768static void data_serialization PARAMS ((void));
769static void remove_marked_resource PARAMS ((struct rsrc *));
800eeca4 770static int is_conditional_branch PARAMS ((struct ia64_opcode *));
150f24a2 771static int is_taken_branch PARAMS ((struct ia64_opcode *));
800eeca4 772static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
150f24a2
JW		 773static int depends_on PARAMS ((int, struct ia64_opcode *));
774static int specify_resource PARAMS ((const struct ia64_dependency *,
775 struct ia64_opcode *, int, struct rsrc [], int, int));
800eeca4
JW		 776static int check_dv PARAMS((struct ia64_opcode *idesc));
777static void check_dependencies PARAMS((struct ia64_opcode *));
778static void mark_resources PARAMS((struct ia64_opcode *));
779static void update_dependencies PARAMS((struct ia64_opcode *));
780static void note_register_values PARAMS((struct ia64_opcode *));
150f24a2
JW		 781static int qp_mutex PARAMS ((int, int, int));
782static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
783static void output_vbyte_mem PARAMS ((int, char *, char *));
784static void count_output PARAMS ((int, char *, char *));
785static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
786static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
800eeca4 787static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 788static void output_P1_format PARAMS ((vbyte_func, int));
789static void output_P2_format PARAMS ((vbyte_func, int, int));
790static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
791static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
792static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
793static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
794static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
795static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
796static void output_P9_format PARAMS ((vbyte_func, int, int));
797static void output_P10_format PARAMS ((vbyte_func, int, int));
798static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
799static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800eeca4
JW		 800static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
801static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 802static char format_ab_reg PARAMS ((int, int));
803static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
804 unsigned long));
805static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
806static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
807 unsigned long));
808static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
809static void free_list_records PARAMS ((unw_rec_list *));
810static unw_rec_list *output_prologue PARAMS ((void));
811static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
812static unw_rec_list *output_body PARAMS ((void));
813static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
814static unw_rec_list *output_mem_stack_v PARAMS ((void));
815static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
816static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
817static unw_rec_list *output_rp_when PARAMS ((void));
818static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
819static unw_rec_list *output_rp_br PARAMS ((unsigned int));
820static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
821static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
822static unw_rec_list *output_pfs_when PARAMS ((void));
823static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
824static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
825static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
826static unw_rec_list *output_preds_when PARAMS ((void));
827static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
828static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
829static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
830static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
831static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
832static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
833static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
834static unw_rec_list *output_br_mem PARAMS ((unsigned int));
835static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
836static unw_rec_list *output_spill_base PARAMS ((unsigned int));
837static unw_rec_list *output_unat_when PARAMS ((void));
838static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
839static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
840static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
841static unw_rec_list *output_lc_when PARAMS ((void));
842static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
843static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
844static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
845static unw_rec_list *output_fpsr_when PARAMS ((void));
846static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
847static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
848static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
849static unw_rec_list *output_priunat_when_gr PARAMS ((void));
850static unw_rec_list *output_priunat_when_mem PARAMS ((void));
851static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
852static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
853static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
854static unw_rec_list *output_bsp_when PARAMS ((void));
855static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
856static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
857static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
858static unw_rec_list *output_bspstore_when PARAMS ((void));
859static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
860static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
861static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
862static unw_rec_list *output_rnat_when PARAMS ((void));
863static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
864static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
865static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
866static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
867static unw_rec_list *output_epilogue PARAMS ((unsigned long));
868static unw_rec_list *output_label_state PARAMS ((unsigned long));
869static unw_rec_list *output_copy_state PARAMS ((unsigned long));
870static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
871static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
872static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
873 unsigned int));
874static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
875 unsigned int));
876static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
877 unsigned int));
878static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
879 unsigned int, unsigned int));
880static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
881static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
882static int calc_record_size PARAMS ((unw_rec_list *));
883static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
884static int count_bits PARAMS ((unsigned long));
f5a30c2e
JW		 885static unsigned long slot_index PARAMS ((unsigned long, fragS *,
886 unsigned long, fragS *));
91a2ae2a 887static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *));
150f24a2
JW		 888static void fixup_unw_records PARAMS ((unw_rec_list *));
889static int output_unw_records PARAMS ((unw_rec_list *, void **));
890static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
891static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
91a2ae2a 892static int generate_unwind_image PARAMS ((const char *));
6290819d
NC		 893static unsigned int get_saved_prologue_count PARAMS ((unsigned long));
894static void save_prologue_count PARAMS ((unsigned long, unsigned int));
895static void free_saved_prologue_counts PARAMS ((void));
91a2ae2a
RH		 896
897/* Build the unwind section name by appending the (possibly stripped)
898 text section NAME to the unwind PREFIX. The resulting string
899 pointer is assigned to RESULT. The string is allocated on the
40449e9f 900 stack, so this must be a macro... */
91a2ae2a
RH		 901#define make_unw_section_name(special, text_name, result) \
902 { \
86cf98f3
RH		 903 const char *_prefix = special_section_name[special]; \
904 const char *_suffix = text_name; \
579f31ac
JJ		 905 size_t _prefix_len, _suffix_len; \
906 char *_result; \
907 if (strncmp (text_name, ".gnu.linkonce.t.", \
908 sizeof (".gnu.linkonce.t.") - 1) == 0) \
909 { \
910 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
911 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
912 } \
913 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
914 _result = alloca (_prefix_len + _suffix_len + 1); \
07726851
KH		 915 memcpy (_result, _prefix, _prefix_len); \
916 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
579f31ac 917 _result[_prefix_len + _suffix_len] = '\0'; \
91a2ae2a
RH		 918 result = _result; \
919 } \
920while (0)
800eeca4
JW		 921
922/* Determine if application register REGNUM resides in the integer
923 unit (as opposed to the memory unit). */
924static int
925ar_is_in_integer_unit (reg)
926 int reg;
927{
928 reg -= REG_AR;
929
930 return (reg == 64 /* pfs */
931 || reg == 65 /* lc */
932 || reg == 66 /* ec */
933 /* ??? ias accepts and puts these in the integer unit. */
934 || (reg >= 112 && reg <= 127));
935}
936
937/* Switch to section NAME and create section if necessary. It's
938 rather ugly that we have to manipulate input_line_pointer but I
939 don't see any other way to accomplish the same thing without
940 changing obj-elf.c (which may be the Right Thing, in the end). */
941static void
942set_section (name)
943 char *name;
944{
945 char *saved_input_line_pointer;
946
947 saved_input_line_pointer = input_line_pointer;
948 input_line_pointer = name;
949 obj_elf_section (0);
950 input_line_pointer = saved_input_line_pointer;
951}
952
d61a78a7
RH		 953/* Map 's' to SHF_IA_64_SHORT. */
954
955int
956ia64_elf_section_letter (letter, ptr_msg)
957 int letter;
958 char **ptr_msg;
959{
960 if (letter == 's')
961 return SHF_IA_64_SHORT;
962
13ae64f3 963 *ptr_msg = _("Bad .section directive: want a,s,w,x,M,S,G,T in string");
d61a78a7
RH		 964 return 0;
965}
966
800eeca4
JW		 967/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
968
969flagword
970ia64_elf_section_flags (flags, attr, type)
971 flagword flags;
2434f565 972 int attr, type ATTRIBUTE_UNUSED;
800eeca4
JW		 973{
974 if (attr & SHF_IA_64_SHORT)
975 flags |= SEC_SMALL_DATA;
976 return flags;
977}
978
91a2ae2a
RH		 979int
980ia64_elf_section_type (str, len)
40449e9f
KH		 981 const char *str;
982 size_t len;
91a2ae2a 983{
1cd8ff38 984#define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0))
40449e9f 985
1cd8ff38 986 if (STREQ (ELF_STRING_ia64_unwind_info))
91a2ae2a
RH		 987 return SHT_PROGBITS;
988
1cd8ff38 989 if (STREQ (ELF_STRING_ia64_unwind_info_once))
579f31ac
JJ		 990 return SHT_PROGBITS;
991
1cd8ff38 992 if (STREQ (ELF_STRING_ia64_unwind))
91a2ae2a
RH		 993 return SHT_IA_64_UNWIND;
994
1cd8ff38 995 if (STREQ (ELF_STRING_ia64_unwind_once))
579f31ac
JJ		 996 return SHT_IA_64_UNWIND;
997
1cd8ff38
NC		 998 if (STREQ ("init_array"))
999 return SHT_INIT_ARRAY;
40449e9f 1000
1cd8ff38
NC		 1001 if (STREQ ("fini_array"))
1002 return SHT_FINI_ARRAY;
40449e9f 1003
91a2ae2a 1004 return -1;
1cd8ff38 1005#undef STREQ
91a2ae2a
RH		 1006}
1007
800eeca4
JW		 1008static unsigned int
1009set_regstack (ins, locs, outs, rots)
1010 unsigned int ins, locs, outs, rots;
1011{
542d6675
KH		 1012 /* Size of frame. */
1013 unsigned int sof;
800eeca4
JW		 1014
1015 sof = ins + locs + outs;
1016 if (sof > 96)
1017 {
1018 as_bad ("Size of frame exceeds maximum of 96 registers");
1019 return 0;
1020 }
1021 if (rots > sof)
1022 {
1023 as_warn ("Size of rotating registers exceeds frame size");
1024 return 0;
1025 }
1026 md.in.base = REG_GR + 32;
1027 md.loc.base = md.in.base + ins;
1028 md.out.base = md.loc.base + locs;
1029
1030 md.in.num_regs = ins;
1031 md.loc.num_regs = locs;
1032 md.out.num_regs = outs;
1033 md.rot.num_regs = rots;
1034 return sof;
1035}
1036
1037void
1038ia64_flush_insns ()
1039{
1040 struct label_fix *lfix;
1041 segT saved_seg;
1042 subsegT saved_subseg;
b44b1b85 1043 unw_rec_list *ptr;
800eeca4
JW		 1044
1045 if (!md.last_text_seg)
1046 return;
1047
1048 saved_seg = now_seg;
1049 saved_subseg = now_subseg;
1050
1051 subseg_set (md.last_text_seg, 0);
1052
1053 while (md.num_slots_in_use > 0)
1054 emit_one_bundle (); /* force out queued instructions */
1055
1056 /* In case there are labels following the last instruction, resolve
542d6675 1057 those now: */
800eeca4
JW		 1058 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
1059 {
1060 S_SET_VALUE (lfix->sym, frag_now_fix ());
1061 symbol_set_frag (lfix->sym, frag_now);
1062 }
1063 CURR_SLOT.label_fixups = 0;
f1bcba5b
JW		 1064 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
1065 {
1066 S_SET_VALUE (lfix->sym, frag_now_fix ());
1067 symbol_set_frag (lfix->sym, frag_now);
1068 }
1069 CURR_SLOT.tag_fixups = 0;
800eeca4 1070
b44b1b85
JW		 1071 /* In case there are unwind directives following the last instruction,
1072 resolve those now. We only handle body and prologue directives here.
1073 Give an error for others. */
1074 for (ptr = unwind.current_entry; ptr; ptr = ptr->next)
1075 {
1076 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
1077 || ptr->r.type == body)
1078 {
1079 ptr->slot_number = (unsigned long) frag_more (0);
1080 ptr->slot_frag = frag_now;
1081 }
1082 else
1083 as_bad (_("Unwind directive not followed by an instruction."));
1084 }
1085 unwind.current_entry = NULL;
1086
800eeca4 1087 subseg_set (saved_seg, saved_subseg);
f1bcba5b
JW		 1088
1089 if (md.qp.X_op == O_register)
1090 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW		 1091}
1092
1093void
1094ia64_do_align (nbytes)
1095 int nbytes;
1096{
1097 char *saved_input_line_pointer = input_line_pointer;
1098
1099 input_line_pointer = "";
1100 s_align_bytes (nbytes);
1101 input_line_pointer = saved_input_line_pointer;
1102}
1103
1104void
1105ia64_cons_align (nbytes)
1106 int nbytes;
1107{
1108 if (md.auto_align)
1109 {
1110 char *saved_input_line_pointer = input_line_pointer;
1111 input_line_pointer = "";
1112 s_align_bytes (nbytes);
1113 input_line_pointer = saved_input_line_pointer;
1114 }
1115}
1116
1117/* Output COUNT bytes to a memory location. */
1118static unsigned char *vbyte_mem_ptr = NULL;
1119
197865e8 1120void
800eeca4
JW		 1121output_vbyte_mem (count, ptr, comment)
1122 int count;
1123 char *ptr;
2434f565 1124 char *comment ATTRIBUTE_UNUSED;
800eeca4
JW		 1125{
1126 int x;
1127 if (vbyte_mem_ptr == NULL)
1128 abort ();
1129
1130 if (count == 0)
1131 return;
1132 for (x = 0; x < count; x++)
1133 *(vbyte_mem_ptr++) = ptr[x];
1134}
1135
1136/* Count the number of bytes required for records. */
1137static int vbyte_count = 0;
197865e8 1138void
800eeca4
JW		 1139count_output (count, ptr, comment)
1140 int count;
2434f565
JW		 1141 char *ptr ATTRIBUTE_UNUSED;
1142 char *comment ATTRIBUTE_UNUSED;
800eeca4
JW		 1143{
1144 vbyte_count += count;
1145}
1146
1147static void
1148output_R1_format (f, rtype, rlen)
1149 vbyte_func f;
1150 unw_record_type rtype;
1151 int rlen;
1152{
e0c9811a 1153 int r = 0;
800eeca4
JW		 1154 char byte;
1155 if (rlen > 0x1f)
1156 {
1157 output_R3_format (f, rtype, rlen);
1158 return;
1159 }
197865e8 1160
e0c9811a
JW		 1161 if (rtype == body)
1162 r = 1;
1163 else if (rtype != prologue)
1164 as_bad ("record type is not valid");
1165
800eeca4
JW		 1166 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
1167 (*f) (1, &byte, NULL);
1168}
1169
1170static void
1171output_R2_format (f, mask, grsave, rlen)
1172 vbyte_func f;
1173 int mask, grsave;
1174 unsigned long rlen;
1175{
1176 char bytes[20];
1177 int count = 2;
1178 mask = (mask & 0x0f);
1179 grsave = (grsave & 0x7f);
1180
1181 bytes[0] = (UNW_R2 | (mask >> 1));
1182 bytes[1] = (((mask & 0x01) << 7) | grsave);
1183 count += output_leb128 (bytes + 2, rlen, 0);
1184 (*f) (count, bytes, NULL);
1185}
1186
1187static void
1188output_R3_format (f, rtype, rlen)
1189 vbyte_func f;
1190 unw_record_type rtype;
1191 unsigned long rlen;
1192{
e0c9811a 1193 int r = 0, count;
800eeca4
JW		 1194 char bytes[20];
1195 if (rlen <= 0x1f)
1196 {
1197 output_R1_format (f, rtype, rlen);
1198 return;
1199 }
197865e8 1200
e0c9811a
JW		 1201 if (rtype == body)
1202 r = 1;
1203 else if (rtype != prologue)
1204 as_bad ("record type is not valid");
800eeca4
JW		 1205 bytes[0] = (UNW_R3 | r);
1206 count = output_leb128 (bytes + 1, rlen, 0);
1207 (*f) (count + 1, bytes, NULL);
1208}
1209
1210static void
1211output_P1_format (f, brmask)
1212 vbyte_func f;
1213 int brmask;
1214{
1215 char byte;
1216 byte = UNW_P1 | (brmask & 0x1f);
1217 (*f) (1, &byte, NULL);
1218}
1219
1220static void
1221output_P2_format (f, brmask, gr)
1222 vbyte_func f;
1223 int brmask;
1224 int gr;
1225{
1226 char bytes[2];
1227 brmask = (brmask & 0x1f);
1228 bytes[0] = UNW_P2 | (brmask >> 1);
1229 bytes[1] = (((brmask & 1) << 7) | gr);
1230 (*f) (2, bytes, NULL);
1231}
1232
1233static void
1234output_P3_format (f, rtype, reg)
1235 vbyte_func f;
1236 unw_record_type rtype;
1237 int reg;
1238{
1239 char bytes[2];
e0c9811a 1240 int r = 0;
800eeca4
JW		 1241 reg = (reg & 0x7f);
1242 switch (rtype)
542d6675 1243 {
800eeca4
JW		 1244 case psp_gr:
1245 r = 0;
1246 break;
1247 case rp_gr:
1248 r = 1;
1249 break;
1250 case pfs_gr:
1251 r = 2;
1252 break;
1253 case preds_gr:
1254 r = 3;
1255 break;
1256 case unat_gr:
1257 r = 4;
1258 break;
1259 case lc_gr:
1260 r = 5;
1261 break;
1262 case rp_br:
1263 r = 6;
1264 break;
1265 case rnat_gr:
1266 r = 7;
1267 break;
1268 case bsp_gr:
1269 r = 8;
1270 break;
1271 case bspstore_gr:
1272 r = 9;
1273 break;
1274 case fpsr_gr:
1275 r = 10;
1276 break;
1277 case priunat_gr:
1278 r = 11;
1279 break;
1280 default:
1281 as_bad ("Invalid record type for P3 format.");
542d6675 1282 }
800eeca4
JW		 1283 bytes[0] = (UNW_P3 | (r >> 1));
1284 bytes[1] = (((r & 1) << 7) | reg);
1285 (*f) (2, bytes, NULL);
1286}
1287
800eeca4 1288static void
e0c9811a 1289output_P4_format (f, imask, imask_size)
800eeca4 1290 vbyte_func f;
e0c9811a
JW		 1291 unsigned char *imask;
1292 unsigned long imask_size;
800eeca4 1293{
e0c9811a
JW		 1294 imask[0] = UNW_P4;
1295 (*f) (imask_size, imask, NULL);
800eeca4
JW		 1296}
1297
1298static void
1299output_P5_format (f, grmask, frmask)
1300 vbyte_func f;
1301 int grmask;
1302 unsigned long frmask;
1303{
1304 char bytes[4];
1305 grmask = (grmask & 0x0f);
1306
1307 bytes[0] = UNW_P5;
1308 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1309 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1310 bytes[3] = (frmask & 0x000000ff);
1311 (*f) (4, bytes, NULL);
1312}
1313
1314static void
1315output_P6_format (f, rtype, rmask)
1316 vbyte_func f;
1317 unw_record_type rtype;
1318 int rmask;
1319{
1320 char byte;
e0c9811a 1321 int r = 0;
197865e8 1322
e0c9811a
JW		 1323 if (rtype == gr_mem)
1324 r = 1;
1325 else if (rtype != fr_mem)
1326 as_bad ("Invalid record type for format P6");
800eeca4
JW		 1327 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1328 (*f) (1, &byte, NULL);
1329}
1330
1331static void
1332output_P7_format (f, rtype, w1, w2)
1333 vbyte_func f;
1334 unw_record_type rtype;
1335 unsigned long w1;
1336 unsigned long w2;
1337{
1338 char bytes[20];
1339 int count = 1;
e0c9811a 1340 int r = 0;
800eeca4
JW		 1341 count += output_leb128 (bytes + 1, w1, 0);
1342 switch (rtype)
1343 {
542d6675
KH		 1344 case mem_stack_f:
1345 r = 0;
1346 count += output_leb128 (bytes + count, w2 >> 4, 0);
1347 break;
1348 case mem_stack_v:
1349 r = 1;
1350 break;
1351 case spill_base:
1352 r = 2;
1353 break;
1354 case psp_sprel:
1355 r = 3;
1356 break;
1357 case rp_when:
1358 r = 4;
1359 break;
1360 case rp_psprel:
1361 r = 5;
1362 break;
1363 case pfs_when:
1364 r = 6;
1365 break;
1366 case pfs_psprel:
1367 r = 7;
1368 break;
1369 case preds_when:
1370 r = 8;
1371 break;
1372 case preds_psprel:
1373 r = 9;
1374 break;
1375 case lc_when:
1376 r = 10;
1377 break;
1378 case lc_psprel:
1379 r = 11;
1380 break;
1381 case unat_when:
1382 r = 12;
1383 break;
1384 case unat_psprel:
1385 r = 13;
1386 break;
1387 case fpsr_when:
1388 r = 14;
1389 break;
1390 case fpsr_psprel:
1391 r = 15;
1392 break;
1393 default:
1394 break;
800eeca4
JW		 1395 }
1396 bytes[0] = (UNW_P7 | r);
1397 (*f) (count, bytes, NULL);
1398}
1399
1400static void
1401output_P8_format (f, rtype, t)
1402 vbyte_func f;
1403 unw_record_type rtype;
1404 unsigned long t;
1405{
1406 char bytes[20];
e0c9811a 1407 int r = 0;
800eeca4
JW		 1408 int count = 2;
1409 bytes[0] = UNW_P8;
1410 switch (rtype)
1411 {
542d6675
KH		 1412 case rp_sprel:
1413 r = 1;
1414 break;
1415 case pfs_sprel:
1416 r = 2;
1417 break;
1418 case preds_sprel:
1419 r = 3;
1420 break;
1421 case lc_sprel:
1422 r = 4;
1423 break;
1424 case unat_sprel:
1425 r = 5;
1426 break;
1427 case fpsr_sprel:
1428 r = 6;
1429 break;
1430 case bsp_when:
1431 r = 7;
1432 break;
1433 case bsp_psprel:
1434 r = 8;
1435 break;
1436 case bsp_sprel:
1437 r = 9;
1438 break;
1439 case bspstore_when:
1440 r = 10;
1441 break;
1442 case bspstore_psprel:
1443 r = 11;
1444 break;
1445 case bspstore_sprel:
1446 r = 12;
1447 break;
1448 case rnat_when:
1449 r = 13;
1450 break;
1451 case rnat_psprel:
1452 r = 14;
1453 break;
1454 case rnat_sprel:
1455 r = 15;
1456 break;
1457 case priunat_when_gr:
1458 r = 16;
1459 break;
1460 case priunat_psprel:
1461 r = 17;
1462 break;
1463 case priunat_sprel:
1464 r = 18;
1465 break;
1466 case priunat_when_mem:
1467 r = 19;
1468 break;
1469 default:
1470 break;
800eeca4
JW		 1471 }
1472 bytes[1] = r;
1473 count += output_leb128 (bytes + 2, t, 0);
1474 (*f) (count, bytes, NULL);
1475}
1476
1477static void
1478output_P9_format (f, grmask, gr)
1479 vbyte_func f;
1480 int grmask;
1481 int gr;
1482{
1483 char bytes[3];
1484 bytes[0] = UNW_P9;
1485 bytes[1] = (grmask & 0x0f);
1486 bytes[2] = (gr & 0x7f);
1487 (*f) (3, bytes, NULL);
1488}
1489
1490static void
1491output_P10_format (f, abi, context)
1492 vbyte_func f;
1493 int abi;
1494 int context;
1495{
1496 char bytes[3];
1497 bytes[0] = UNW_P10;
1498 bytes[1] = (abi & 0xff);
1499 bytes[2] = (context & 0xff);
1500 (*f) (3, bytes, NULL);
1501}
1502
1503static void
1504output_B1_format (f, rtype, label)
1505 vbyte_func f;
1506 unw_record_type rtype;
1507 unsigned long label;
1508{
1509 char byte;
e0c9811a 1510 int r = 0;
197865e8 1511 if (label > 0x1f)
800eeca4
JW		 1512 {
1513 output_B4_format (f, rtype, label);
1514 return;
1515 }
e0c9811a
JW		 1516 if (rtype == copy_state)
1517 r = 1;
1518 else if (rtype != label_state)
1519 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1520
1521 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1522 (*f) (1, &byte, NULL);
1523}
1524
1525static void
1526output_B2_format (f, ecount, t)
1527 vbyte_func f;
1528 unsigned long ecount;
1529 unsigned long t;
1530{
1531 char bytes[20];
1532 int count = 1;
1533 if (ecount > 0x1f)
1534 {
1535 output_B3_format (f, ecount, t);
1536 return;
1537 }
1538 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1539 count += output_leb128 (bytes + 1, t, 0);
1540 (*f) (count, bytes, NULL);
1541}
1542
1543static void
1544output_B3_format (f, ecount, t)
1545 vbyte_func f;
1546 unsigned long ecount;
1547 unsigned long t;
1548{
1549 char bytes[20];
1550 int count = 1;
1551 if (ecount <= 0x1f)
1552 {
1553 output_B2_format (f, ecount, t);
1554 return;
1555 }
1556 bytes[0] = UNW_B3;
1557 count += output_leb128 (bytes + 1, t, 0);
1558 count += output_leb128 (bytes + count, ecount, 0);
1559 (*f) (count, bytes, NULL);
1560}
1561
1562static void
1563output_B4_format (f, rtype, label)
1564 vbyte_func f;
1565 unw_record_type rtype;
1566 unsigned long label;
1567{
1568 char bytes[20];
e0c9811a 1569 int r = 0;
800eeca4 1570 int count = 1;
197865e8 1571 if (label <= 0x1f)
800eeca4
JW		 1572 {
1573 output_B1_format (f, rtype, label);
1574 return;
1575 }
197865e8 1576
e0c9811a
JW		 1577 if (rtype == copy_state)
1578 r = 1;
1579 else if (rtype != label_state)
1580 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1581
1582 bytes[0] = (UNW_B4 | (r << 3));
1583 count += output_leb128 (bytes + 1, label, 0);
1584 (*f) (count, bytes, NULL);
1585}
1586
1587static char
e0c9811a 1588format_ab_reg (ab, reg)
542d6675
KH		 1589 int ab;
1590 int reg;
800eeca4
JW		 1591{
1592 int ret;
e0c9811a 1593 ab = (ab & 3);
800eeca4 1594 reg = (reg & 0x1f);
e0c9811a 1595 ret = (ab << 5) | reg;
800eeca4
JW		 1596 return ret;
1597}
1598
1599static void
e0c9811a 1600output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW		 1601 vbyte_func f;
1602 unw_record_type rtype;
e0c9811a 1603 int ab, reg;
800eeca4
JW		 1604 unsigned long t;
1605 unsigned long w1;
1606{
1607 char bytes[20];
e0c9811a 1608 int r = 0;
800eeca4
JW		 1609 int count = 2;
1610 bytes[0] = UNW_X1;
197865e8 1611
e0c9811a
JW		 1612 if (rtype == spill_sprel)
1613 r = 1;
1614 else if (rtype != spill_psprel)
1615 as_bad ("Invalid record type for format X1");
1616 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1617 count += output_leb128 (bytes + 2, t, 0);
1618 count += output_leb128 (bytes + count, w1, 0);
1619 (*f) (count, bytes, NULL);
1620}
1621
1622static void
e0c9811a 1623output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1624 vbyte_func f;
e0c9811a 1625 int ab, reg;
800eeca4
JW		 1626 int x, y, treg;
1627 unsigned long t;
1628{
1629 char bytes[20];
800eeca4
JW		 1630 int count = 3;
1631 bytes[0] = UNW_X2;
e0c9811a 1632 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1633 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1634 count += output_leb128 (bytes + 3, t, 0);
1635 (*f) (count, bytes, NULL);
1636}
1637
1638static void
e0c9811a 1639output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW		 1640 vbyte_func f;
1641 unw_record_type rtype;
1642 int qp;
e0c9811a 1643 int ab, reg;
800eeca4
JW		 1644 unsigned long t;
1645 unsigned long w1;
1646{
1647 char bytes[20];
e0c9811a 1648 int r = 0;
800eeca4 1649 int count = 3;
e0c9811a
JW		 1650 bytes[0] = UNW_X3;
1651
1652 if (rtype == spill_sprel_p)
1653 r = 1;
1654 else if (rtype != spill_psprel_p)
1655 as_bad ("Invalid record type for format X3");
800eeca4 1656 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1657 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW		 1658 count += output_leb128 (bytes + 3, t, 0);
1659 count += output_leb128 (bytes + count, w1, 0);
1660 (*f) (count, bytes, NULL);
1661}
1662
1663static void
e0c9811a 1664output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW		 1665 vbyte_func f;
1666 int qp;
e0c9811a 1667 int ab, reg;
800eeca4
JW		 1668 int x, y, treg;
1669 unsigned long t;
1670{
1671 char bytes[20];
800eeca4 1672 int count = 4;
e0c9811a 1673 bytes[0] = UNW_X4;
800eeca4 1674 bytes[1] = (qp & 0x3f);
e0c9811a 1675 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1676 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1677 count += output_leb128 (bytes + 4, t, 0);
1678 (*f) (count, bytes, NULL);
1679}
1680
1681/* This function allocates a record list structure, and initializes fields. */
542d6675 1682
800eeca4 1683static unw_rec_list *
197865e8 1684alloc_record (unw_record_type t)
800eeca4
JW		 1685{
1686 unw_rec_list *ptr;
1687 ptr = xmalloc (sizeof (*ptr));
1688 ptr->next = NULL;
1689 ptr->slot_number = SLOT_NUM_NOT_SET;
1690 ptr->r.type = t;
1691 return ptr;
1692}
1693
800eeca4 1694/* This function frees an entire list of record structures. */
542d6675 1695
800eeca4
JW		 1696void
1697free_list_records (unw_rec_list *first)
1698{
1699 unw_rec_list *ptr;
542d6675 1700 for (ptr = first; ptr != NULL;)
800eeca4
JW		 1701 {
1702 unw_rec_list *tmp = ptr;
e0c9811a
JW		 1703
1704 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1705 && tmp->r.record.r.mask.i)
1706 free (tmp->r.record.r.mask.i);
1707
800eeca4
JW		 1708 ptr = ptr->next;
1709 free (tmp);
1710 }
1711}
1712
1713static unw_rec_list *
1714output_prologue ()
1715{
1716 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1717 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW		 1718 return ptr;
1719}
1720
1721static unw_rec_list *
1722output_prologue_gr (saved_mask, reg)
1723 unsigned int saved_mask;
1724 unsigned int reg;
1725{
1726 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW		 1727 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1728 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW		 1729 ptr->r.record.r.grsave = reg;
1730 return ptr;
1731}
1732
1733static unw_rec_list *
1734output_body ()
1735{
1736 unw_rec_list *ptr = alloc_record (body);
1737 return ptr;
1738}
1739
1740static unw_rec_list *
1741output_mem_stack_f (size)
1742 unsigned int size;
1743{
1744 unw_rec_list *ptr = alloc_record (mem_stack_f);
1745 ptr->r.record.p.size = size;
1746 return ptr;
1747}
1748
1749static unw_rec_list *
1750output_mem_stack_v ()
1751{
1752 unw_rec_list *ptr = alloc_record (mem_stack_v);
1753 return ptr;
1754}
1755
1756static unw_rec_list *
1757output_psp_gr (gr)
1758 unsigned int gr;
1759{
1760 unw_rec_list *ptr = alloc_record (psp_gr);
1761 ptr->r.record.p.gr = gr;
1762 return ptr;
1763}
1764
1765static unw_rec_list *
1766output_psp_sprel (offset)
1767 unsigned int offset;
1768{
1769 unw_rec_list *ptr = alloc_record (psp_sprel);
542d6675 1770 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1771 return ptr;
1772}
1773
1774static unw_rec_list *
1775output_rp_when ()
1776{
1777 unw_rec_list *ptr = alloc_record (rp_when);
1778 return ptr;
1779}
1780
1781static unw_rec_list *
1782output_rp_gr (gr)
1783 unsigned int gr;
1784{
1785 unw_rec_list *ptr = alloc_record (rp_gr);
1786 ptr->r.record.p.gr = gr;
1787 return ptr;
1788}
1789
1790static unw_rec_list *
1791output_rp_br (br)
1792 unsigned int br;
1793{
1794 unw_rec_list *ptr = alloc_record (rp_br);
1795 ptr->r.record.p.br = br;
1796 return ptr;
1797}
1798
1799static unw_rec_list *
1800output_rp_psprel (offset)
1801 unsigned int offset;
1802{
1803 unw_rec_list *ptr = alloc_record (rp_psprel);
542d6675 1804 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1805 return ptr;
1806}
1807
1808static unw_rec_list *
1809output_rp_sprel (offset)
1810 unsigned int offset;
1811{
1812 unw_rec_list *ptr = alloc_record (rp_sprel);
542d6675 1813 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1814 return ptr;
1815}
1816
1817static unw_rec_list *
1818output_pfs_when ()
1819{
1820 unw_rec_list *ptr = alloc_record (pfs_when);
1821 return ptr;
1822}
1823
1824static unw_rec_list *
1825output_pfs_gr (gr)
1826 unsigned int gr;
1827{
1828 unw_rec_list *ptr = alloc_record (pfs_gr);
1829 ptr->r.record.p.gr = gr;
1830 return ptr;
1831}
1832
1833static unw_rec_list *
1834output_pfs_psprel (offset)
1835 unsigned int offset;
1836{
1837 unw_rec_list *ptr = alloc_record (pfs_psprel);
542d6675 1838 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1839 return ptr;
1840}
1841
1842static unw_rec_list *
1843output_pfs_sprel (offset)
1844 unsigned int offset;
1845{
1846 unw_rec_list *ptr = alloc_record (pfs_sprel);
542d6675 1847 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1848 return ptr;
1849}
1850
1851static unw_rec_list *
1852output_preds_when ()
1853{
1854 unw_rec_list *ptr = alloc_record (preds_when);
1855 return ptr;
1856}
1857
1858static unw_rec_list *
1859output_preds_gr (gr)
1860 unsigned int gr;
1861{
1862 unw_rec_list *ptr = alloc_record (preds_gr);
1863 ptr->r.record.p.gr = gr;
1864 return ptr;
1865}
1866
1867static unw_rec_list *
1868output_preds_psprel (offset)
1869 unsigned int offset;
1870{
1871 unw_rec_list *ptr = alloc_record (preds_psprel);
542d6675 1872 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1873 return ptr;
1874}
1875
1876static unw_rec_list *
1877output_preds_sprel (offset)
1878 unsigned int offset;
1879{
1880 unw_rec_list *ptr = alloc_record (preds_sprel);
542d6675 1881 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1882 return ptr;
1883}
1884
1885static unw_rec_list *
1886output_fr_mem (mask)
1887 unsigned int mask;
1888{
1889 unw_rec_list *ptr = alloc_record (fr_mem);
1890 ptr->r.record.p.rmask = mask;
1891 return ptr;
1892}
1893
1894static unw_rec_list *
1895output_frgr_mem (gr_mask, fr_mask)
1896 unsigned int gr_mask;
1897 unsigned int fr_mask;
1898{
1899 unw_rec_list *ptr = alloc_record (frgr_mem);
1900 ptr->r.record.p.grmask = gr_mask;
1901 ptr->r.record.p.frmask = fr_mask;
1902 return ptr;
1903}
1904
1905static unw_rec_list *
1906output_gr_gr (mask, reg)
1907 unsigned int mask;
1908 unsigned int reg;
1909{
1910 unw_rec_list *ptr = alloc_record (gr_gr);
1911 ptr->r.record.p.grmask = mask;
1912 ptr->r.record.p.gr = reg;
1913 return ptr;
1914}
1915
1916static unw_rec_list *
1917output_gr_mem (mask)
1918 unsigned int mask;
1919{
1920 unw_rec_list *ptr = alloc_record (gr_mem);
1921 ptr->r.record.p.rmask = mask;
1922 return ptr;
1923}
1924
1925static unw_rec_list *
1926output_br_mem (unsigned int mask)
1927{
1928 unw_rec_list *ptr = alloc_record (br_mem);
1929 ptr->r.record.p.brmask = mask;
1930 return ptr;
1931}
1932
1933static unw_rec_list *
1934output_br_gr (save_mask, reg)
1935 unsigned int save_mask;
1936 unsigned int reg;
1937{
1938 unw_rec_list *ptr = alloc_record (br_gr);
1939 ptr->r.record.p.brmask = save_mask;
1940 ptr->r.record.p.gr = reg;
1941 return ptr;
1942}
1943
1944static unw_rec_list *
1945output_spill_base (offset)
1946 unsigned int offset;
1947{
1948 unw_rec_list *ptr = alloc_record (spill_base);
542d6675 1949 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1950 return ptr;
1951}
1952
1953static unw_rec_list *
1954output_unat_when ()
1955{
1956 unw_rec_list *ptr = alloc_record (unat_when);
1957 return ptr;
1958}
1959
1960static unw_rec_list *
1961output_unat_gr (gr)
1962 unsigned int gr;
1963{
1964 unw_rec_list *ptr = alloc_record (unat_gr);
1965 ptr->r.record.p.gr = gr;
1966 return ptr;
1967}
1968
1969static unw_rec_list *
1970output_unat_psprel (offset)
1971 unsigned int offset;
1972{
1973 unw_rec_list *ptr = alloc_record (unat_psprel);
542d6675 1974 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1975 return ptr;
1976}
1977
1978static unw_rec_list *
1979output_unat_sprel (offset)
1980 unsigned int offset;
1981{
1982 unw_rec_list *ptr = alloc_record (unat_sprel);
542d6675 1983 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1984 return ptr;
1985}
1986
1987static unw_rec_list *
1988output_lc_when ()
1989{
1990 unw_rec_list *ptr = alloc_record (lc_when);
1991 return ptr;
1992}
1993
1994static unw_rec_list *
1995output_lc_gr (gr)
1996 unsigned int gr;
1997{
1998 unw_rec_list *ptr = alloc_record (lc_gr);
1999 ptr->r.record.p.gr = gr;
2000 return ptr;
2001}
2002
2003static unw_rec_list *
2004output_lc_psprel (offset)
2005 unsigned int offset;
2006{
2007 unw_rec_list *ptr = alloc_record (lc_psprel);
542d6675 2008 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2009 return ptr;
2010}
2011
2012static unw_rec_list *
2013output_lc_sprel (offset)
2014 unsigned int offset;
2015{
2016 unw_rec_list *ptr = alloc_record (lc_sprel);
542d6675 2017 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2018 return ptr;
2019}
2020
2021static unw_rec_list *
2022output_fpsr_when ()
2023{
2024 unw_rec_list *ptr = alloc_record (fpsr_when);
2025 return ptr;
2026}
2027
2028static unw_rec_list *
2029output_fpsr_gr (gr)
2030 unsigned int gr;
2031{
2032 unw_rec_list *ptr = alloc_record (fpsr_gr);
2033 ptr->r.record.p.gr = gr;
2034 return ptr;
2035}
2036
2037static unw_rec_list *
2038output_fpsr_psprel (offset)
2039 unsigned int offset;
2040{
2041 unw_rec_list *ptr = alloc_record (fpsr_psprel);
542d6675 2042 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2043 return ptr;
2044}
2045
2046static unw_rec_list *
2047output_fpsr_sprel (offset)
2048 unsigned int offset;
2049{
2050 unw_rec_list *ptr = alloc_record (fpsr_sprel);
542d6675 2051 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2052 return ptr;
2053}
2054
2055static unw_rec_list *
2056output_priunat_when_gr ()
2057{
2058 unw_rec_list *ptr = alloc_record (priunat_when_gr);
2059 return ptr;
2060}
2061
2062static unw_rec_list *
2063output_priunat_when_mem ()
2064{
2065 unw_rec_list *ptr = alloc_record (priunat_when_mem);
2066 return ptr;
2067}
2068
2069static unw_rec_list *
2070output_priunat_gr (gr)
2071 unsigned int gr;
2072{
2073 unw_rec_list *ptr = alloc_record (priunat_gr);
2074 ptr->r.record.p.gr = gr;
2075 return ptr;
2076}
2077
2078static unw_rec_list *
2079output_priunat_psprel (offset)
2080 unsigned int offset;
2081{
2082 unw_rec_list *ptr = alloc_record (priunat_psprel);
542d6675 2083 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2084 return ptr;
2085}
2086
2087static unw_rec_list *
2088output_priunat_sprel (offset)
2089 unsigned int offset;
2090{
2091 unw_rec_list *ptr = alloc_record (priunat_sprel);
542d6675 2092 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2093 return ptr;
2094}
2095
2096static unw_rec_list *
2097output_bsp_when ()
2098{
2099 unw_rec_list *ptr = alloc_record (bsp_when);
2100 return ptr;
2101}
2102
2103static unw_rec_list *
2104output_bsp_gr (gr)
2105 unsigned int gr;
2106{
2107 unw_rec_list *ptr = alloc_record (bsp_gr);
2108 ptr->r.record.p.gr = gr;
2109 return ptr;
2110}
2111
2112static unw_rec_list *
2113output_bsp_psprel (offset)
2114 unsigned int offset;
2115{
2116 unw_rec_list *ptr = alloc_record (bsp_psprel);
542d6675 2117 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2118 return ptr;
2119}
2120
2121static unw_rec_list *
2122output_bsp_sprel (offset)
2123 unsigned int offset;
2124{
2125 unw_rec_list *ptr = alloc_record (bsp_sprel);
542d6675 2126 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2127 return ptr;
2128}
2129
2130static unw_rec_list *
2131output_bspstore_when ()
2132{
2133 unw_rec_list *ptr = alloc_record (bspstore_when);
2134 return ptr;
2135}
2136
2137static unw_rec_list *
2138output_bspstore_gr (gr)
2139 unsigned int gr;
2140{
2141 unw_rec_list *ptr = alloc_record (bspstore_gr);
2142 ptr->r.record.p.gr = gr;
2143 return ptr;
2144}
2145
2146static unw_rec_list *
2147output_bspstore_psprel (offset)
2148 unsigned int offset;
2149{
2150 unw_rec_list *ptr = alloc_record (bspstore_psprel);
542d6675 2151 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2152 return ptr;
2153}
2154
2155static unw_rec_list *
2156output_bspstore_sprel (offset)
2157 unsigned int offset;
2158{
2159 unw_rec_list *ptr = alloc_record (bspstore_sprel);
542d6675 2160 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2161 return ptr;
2162}
2163
2164static unw_rec_list *
2165output_rnat_when ()
2166{
2167 unw_rec_list *ptr = alloc_record (rnat_when);
2168 return ptr;
2169}
2170
2171static unw_rec_list *
2172output_rnat_gr (gr)
2173 unsigned int gr;
2174{
2175 unw_rec_list *ptr = alloc_record (rnat_gr);
2176 ptr->r.record.p.gr = gr;
2177 return ptr;
2178}
2179
2180static unw_rec_list *
2181output_rnat_psprel (offset)
2182 unsigned int offset;
2183{
2184 unw_rec_list *ptr = alloc_record (rnat_psprel);
542d6675 2185 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2186 return ptr;
2187}
2188
2189static unw_rec_list *
2190output_rnat_sprel (offset)
2191 unsigned int offset;
2192{
2193 unw_rec_list *ptr = alloc_record (rnat_sprel);
542d6675 2194 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2195 return ptr;
2196}
2197
2198static unw_rec_list *
e0c9811a
JW		 2199output_unwabi (abi, context)
2200 unsigned long abi;
2201 unsigned long context;
800eeca4 2202{
e0c9811a
JW		 2203 unw_rec_list *ptr = alloc_record (unwabi);
2204 ptr->r.record.p.abi = abi;
2205 ptr->r.record.p.context = context;
800eeca4
JW		 2206 return ptr;
2207}
2208
2209static unw_rec_list *
e0c9811a 2210output_epilogue (unsigned long ecount)
800eeca4 2211{
e0c9811a
JW		 2212 unw_rec_list *ptr = alloc_record (epilogue);
2213 ptr->r.record.b.ecount = ecount;
800eeca4
JW		 2214 return ptr;
2215}
2216
2217static unw_rec_list *
e0c9811a 2218output_label_state (unsigned long label)
800eeca4 2219{
e0c9811a
JW		 2220 unw_rec_list *ptr = alloc_record (label_state);
2221 ptr->r.record.b.label = label;
800eeca4
JW		 2222 return ptr;
2223}
2224
2225static unw_rec_list *
e0c9811a
JW		 2226output_copy_state (unsigned long label)
2227{
2228 unw_rec_list *ptr = alloc_record (copy_state);
2229 ptr->r.record.b.label = label;
2230 return ptr;
2231}
2232
2233static unw_rec_list *
2234output_spill_psprel (ab, reg, offset)
2235 unsigned int ab;
800eeca4
JW		 2236 unsigned int reg;
2237 unsigned int offset;
2238{
2239 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 2240 ptr->r.record.x.ab = ab;
800eeca4 2241 ptr->r.record.x.reg = reg;
542d6675 2242 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2243 return ptr;
2244}
2245
2246static unw_rec_list *
e0c9811a
JW		 2247output_spill_sprel (ab, reg, offset)
2248 unsigned int ab;
800eeca4
JW		 2249 unsigned int reg;
2250 unsigned int offset;
2251{
2252 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 2253 ptr->r.record.x.ab = ab;
800eeca4 2254 ptr->r.record.x.reg = reg;
542d6675 2255 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2256 return ptr;
2257}
2258
2259static unw_rec_list *
e0c9811a
JW		 2260output_spill_psprel_p (ab, reg, offset, predicate)
2261 unsigned int ab;
800eeca4
JW		 2262 unsigned int reg;
2263 unsigned int offset;
2264 unsigned int predicate;
2265{
2266 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 2267 ptr->r.record.x.ab = ab;
800eeca4 2268 ptr->r.record.x.reg = reg;
542d6675 2269 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2270 ptr->r.record.x.qp = predicate;
2271 return ptr;
2272}
2273
2274static unw_rec_list *
e0c9811a
JW		 2275output_spill_sprel_p (ab, reg, offset, predicate)
2276 unsigned int ab;
800eeca4
JW		 2277 unsigned int reg;
2278 unsigned int offset;
2279 unsigned int predicate;
2280{
2281 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 2282 ptr->r.record.x.ab = ab;
800eeca4 2283 ptr->r.record.x.reg = reg;
542d6675 2284 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2285 ptr->r.record.x.qp = predicate;
2286 return ptr;
2287}
2288
2289static unw_rec_list *
e0c9811a
JW		 2290output_spill_reg (ab, reg, targ_reg, xy)
2291 unsigned int ab;
800eeca4
JW		 2292 unsigned int reg;
2293 unsigned int targ_reg;
2294 unsigned int xy;
2295{
2296 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 2297 ptr->r.record.x.ab = ab;
800eeca4
JW		 2298 ptr->r.record.x.reg = reg;
2299 ptr->r.record.x.treg = targ_reg;
2300 ptr->r.record.x.xy = xy;
2301 return ptr;
2302}
2303
2304static unw_rec_list *
e0c9811a
JW		 2305output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2306 unsigned int ab;
800eeca4
JW		 2307 unsigned int reg;
2308 unsigned int targ_reg;
2309 unsigned int xy;
2310 unsigned int predicate;
2311{
2312 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 2313 ptr->r.record.x.ab = ab;
800eeca4
JW		 2314 ptr->r.record.x.reg = reg;
2315 ptr->r.record.x.treg = targ_reg;
2316 ptr->r.record.x.xy = xy;
2317 ptr->r.record.x.qp = predicate;
2318 return ptr;
2319}
2320
197865e8 2321/* Given a unw_rec_list process the correct format with the
800eeca4 2322 specified function. */
542d6675 2323
800eeca4
JW		 2324static void
2325process_one_record (ptr, f)
2326 unw_rec_list *ptr;
2327 vbyte_func f;
2328{
e0c9811a
JW		 2329 unsigned long fr_mask, gr_mask;
2330
197865e8 2331 switch (ptr->r.type)
800eeca4 2332 {
542d6675
KH		 2333 case gr_mem:
2334 case fr_mem:
2335 case br_mem:
2336 case frgr_mem:
2337 /* These are taken care of by prologue/prologue_gr. */
2338 break;
e0c9811a 2339
542d6675
KH		 2340 case prologue_gr:
2341 case prologue:
2342 if (ptr->r.type == prologue_gr)
2343 output_R2_format (f, ptr->r.record.r.grmask,
2344 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2345 else
800eeca4 2346 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
542d6675
KH		 2347
2348 /* Output descriptor(s) for union of register spills (if any). */
2349 gr_mask = ptr->r.record.r.mask.gr_mem;
2350 fr_mask = ptr->r.record.r.mask.fr_mem;
2351 if (fr_mask)
2352 {
2353 if ((fr_mask & ~0xfUL) == 0)
2354 output_P6_format (f, fr_mem, fr_mask);
2355 else
2356 {
2357 output_P5_format (f, gr_mask, fr_mask);
2358 gr_mask = 0;
2359 }
2360 }
2361 if (gr_mask)
2362 output_P6_format (f, gr_mem, gr_mask);
2363 if (ptr->r.record.r.mask.br_mem)
2364 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2365
2366 /* output imask descriptor if necessary: */
2367 if (ptr->r.record.r.mask.i)
2368 output_P4_format (f, ptr->r.record.r.mask.i,
2369 ptr->r.record.r.imask_size);
2370 break;
2371
2372 case body:
2373 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2374 break;
2375 case mem_stack_f:
2376 case mem_stack_v:
2377 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2378 ptr->r.record.p.size);
2379 break;
2380 case psp_gr:
2381 case rp_gr:
2382 case pfs_gr:
2383 case preds_gr:
2384 case unat_gr:
2385 case lc_gr:
2386 case fpsr_gr:
2387 case priunat_gr:
2388 case bsp_gr:
2389 case bspstore_gr:
2390 case rnat_gr:
2391 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2392 break;
2393 case rp_br:
2394 output_P3_format (f, rp_br, ptr->r.record.p.br);
2395 break;
2396 case psp_sprel:
2397 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2398 break;
2399 case rp_when:
2400 case pfs_when:
2401 case preds_when:
2402 case unat_when:
2403 case lc_when:
2404 case fpsr_when:
2405 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2406 break;
2407 case rp_psprel:
2408 case pfs_psprel:
2409 case preds_psprel:
2410 case unat_psprel:
2411 case lc_psprel:
2412 case fpsr_psprel:
2413 case spill_base:
2414 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2415 break;
2416 case rp_sprel:
2417 case pfs_sprel:
2418 case preds_sprel:
2419 case unat_sprel:
2420 case lc_sprel:
2421 case fpsr_sprel:
2422 case priunat_sprel:
2423 case bsp_sprel:
2424 case bspstore_sprel:
2425 case rnat_sprel:
2426 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2427 break;
2428 case gr_gr:
2429 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2430 break;
2431 case br_gr:
2432 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2433 break;
2434 case spill_mask:
2435 as_bad ("spill_mask record unimplemented.");
2436 break;
2437 case priunat_when_gr:
2438 case priunat_when_mem:
2439 case bsp_when:
2440 case bspstore_when:
2441 case rnat_when:
2442 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2443 break;
2444 case priunat_psprel:
2445 case bsp_psprel:
2446 case bspstore_psprel:
2447 case rnat_psprel:
2448 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2449 break;
2450 case unwabi:
2451 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2452 break;
2453 case epilogue:
2454 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2455 break;
2456 case label_state:
2457 case copy_state:
2458 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2459 break;
2460 case spill_psprel:
2461 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2462 ptr->r.record.x.reg, ptr->r.record.x.t,
2463 ptr->r.record.x.pspoff);
2464 break;
2465 case spill_sprel:
2466 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2467 ptr->r.record.x.reg, ptr->r.record.x.t,
2468 ptr->r.record.x.spoff);
2469 break;
2470 case spill_reg:
2471 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2472 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2473 ptr->r.record.x.treg, ptr->r.record.x.t);
2474 break;
2475 case spill_psprel_p:
2476 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2477 ptr->r.record.x.ab, ptr->r.record.x.reg,
2478 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2479 break;
2480 case spill_sprel_p:
2481 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2482 ptr->r.record.x.ab, ptr->r.record.x.reg,
2483 ptr->r.record.x.t, ptr->r.record.x.spoff);
2484 break;
2485 case spill_reg_p:
2486 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2487 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2488 ptr->r.record.x.xy, ptr->r.record.x.treg,
2489 ptr->r.record.x.t);
2490 break;
2491 default:
2492 as_bad ("record_type_not_valid");
2493 break;
800eeca4
JW		 2494 }
2495}
2496
197865e8 2497/* Given a unw_rec_list list, process all the records with
800eeca4
JW		 2498 the specified function. */
2499static void
2500process_unw_records (list, f)
2501 unw_rec_list *list;
2502 vbyte_func f;
2503{
2504 unw_rec_list *ptr;
2505 for (ptr = list; ptr; ptr = ptr->next)
2506 process_one_record (ptr, f);
2507}
2508
2509/* Determine the size of a record list in bytes. */
2510static int
2511calc_record_size (list)
2512 unw_rec_list *list;
2513{
2514 vbyte_count = 0;
2515 process_unw_records (list, count_output);
2516 return vbyte_count;
2517}
2518
e0c9811a
JW		 2519/* Update IMASK bitmask to reflect the fact that one or more registers
2520 of type TYPE are saved starting at instruction with index T. If N
2521 bits are set in REGMASK, it is assumed that instructions T through
2522 T+N-1 save these registers.
2523
2524 TYPE values:
2525 0: no save
2526 1: instruction saves next fp reg
2527 2: instruction saves next general reg
2528 3: instruction saves next branch reg */
2529static void
2530set_imask (region, regmask, t, type)
2531 unw_rec_list *region;
2532 unsigned long regmask;
2533 unsigned long t;
2534 unsigned int type;
2535{
2536 unsigned char *imask;
2537 unsigned long imask_size;
2538 unsigned int i;
2539 int pos;
2540
2541 imask = region->r.record.r.mask.i;
2542 imask_size = region->r.record.r.imask_size;
2543 if (!imask)
2544 {
542d6675 2545 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
e0c9811a
JW		 2546 imask = xmalloc (imask_size);
2547 memset (imask, 0, imask_size);
2548
2549 region->r.record.r.imask_size = imask_size;
2550 region->r.record.r.mask.i = imask;
2551 }
2552
542d6675
KH		 2553 i = (t / 4) + 1;
2554 pos = 2 * (3 - t % 4);
e0c9811a
JW		 2555 while (regmask)
2556 {
2557 if (i >= imask_size)
2558 {
2559 as_bad ("Ignoring attempt to spill beyond end of region");
2560 return;
2561 }
2562
2563 imask[i] |= (type & 0x3) << pos;
197865e8 2564
e0c9811a
JW		 2565 regmask &= (regmask - 1);
2566 pos -= 2;
2567 if (pos < 0)
2568 {
2569 pos = 0;
2570 ++i;
2571 }
2572 }
2573}
2574
2575static int
2576count_bits (unsigned long mask)
2577{
2578 int n = 0;
2579
2580 while (mask)
2581 {
2582 mask &= mask - 1;
2583 ++n;
2584 }
2585 return n;
2586}
2587
f5a30c2e
JW		 2588/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2589 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2590 containing FIRST_ADDR. */
2591
e0c9811a 2592unsigned long
f5a30c2e
JW		 2593slot_index (slot_addr, slot_frag, first_addr, first_frag)
2594 unsigned long slot_addr;
2595 fragS *slot_frag;
2596 unsigned long first_addr;
2597 fragS *first_frag;
e0c9811a 2598{
f5a30c2e
JW		 2599 unsigned long index = 0;
2600
2601 /* First time we are called, the initial address and frag are invalid. */
2602 if (first_addr == 0)
2603 return 0;
2604
2605 /* If the two addresses are in different frags, then we need to add in
2606 the remaining size of this frag, and then the entire size of intermediate
2607 frags. */
2608 while (slot_frag != first_frag)
2609 {
2610 unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
2611
2612 /* Add in the full size of the frag converted to instruction slots. */
2613 index += 3 * (first_frag->fr_fix >> 4);
2614 /* Subtract away the initial part before first_addr. */
2615 index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
2616 + ((first_addr & 0x3) - (start_addr & 0x3)));
e0c9811a 2617
f5a30c2e
JW		 2618 /* Move to the beginning of the next frag. */
2619 first_frag = first_frag->fr_next;
2620 first_addr = (unsigned long) &first_frag->fr_literal;
2621 }
2622
2623 /* Add in the used part of the last frag. */
2624 index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
2625 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2626 return index;
2627}
4a1805b1 2628
91a2ae2a
RH		 2629/* Optimize unwind record directives. */
2630
2631static unw_rec_list *
2632optimize_unw_records (list)
2633 unw_rec_list *list;
2634{
2635 if (!list)
2636 return NULL;
2637
2638 /* If the only unwind record is ".prologue" or ".prologue" followed
2639 by ".body", then we can optimize the unwind directives away. */
2640 if (list->r.type == prologue
2641 && (list->next == NULL
2642 || (list->next->r.type == body && list->next->next == NULL)))
2643 return NULL;
2644
2645 return list;
2646}
2647
800eeca4
JW		 2648/* Given a complete record list, process any records which have
2649 unresolved fields, (ie length counts for a prologue). After
197865e8 2650 this has been run, all neccessary information should be available
800eeca4 2651 within each record to generate an image. */
542d6675 2652
800eeca4
JW		 2653static void
2654fixup_unw_records (list)
2655 unw_rec_list *list;
2656{
e0c9811a
JW		 2657 unw_rec_list *ptr, *region = 0;
2658 unsigned long first_addr = 0, rlen = 0, t;
f5a30c2e 2659 fragS *first_frag = 0;
e0c9811a 2660
800eeca4
JW		 2661 for (ptr = list; ptr; ptr = ptr->next)
2662 {
2663 if (ptr->slot_number == SLOT_NUM_NOT_SET)
542d6675 2664 as_bad (" Insn slot not set in unwind record.");
f5a30c2e
JW		 2665 t = slot_index (ptr->slot_number, ptr->slot_frag,
2666 first_addr, first_frag);
800eeca4
JW		 2667 switch (ptr->r.type)
2668 {
542d6675
KH		 2669 case prologue:
2670 case prologue_gr:
2671 case body:
2672 {
2673 unw_rec_list *last;
2674 int size, dir_len = 0;
2675 unsigned long last_addr;
f5a30c2e 2676 fragS *last_frag;
542d6675
KH		 2677
2678 first_addr = ptr->slot_number;
f5a30c2e 2679 first_frag = ptr->slot_frag;
542d6675
KH		 2680 ptr->slot_number = 0;
2681 /* Find either the next body/prologue start, or the end of
2682 the list, and determine the size of the region. */
2683 last_addr = unwind.next_slot_number;
f5a30c2e 2684 last_frag = unwind.next_slot_frag;
542d6675
KH		 2685 for (last = ptr->next; last != NULL; last = last->next)
2686 if (last->r.type == prologue || last->r.type == prologue_gr
2687 || last->r.type == body)
2688 {
2689 last_addr = last->slot_number;
f5a30c2e 2690 last_frag = last->slot_frag;
542d6675
KH		 2691 break;
2692 }
2693 else if (!last->next)
2694 {
2695 /* In the absence of an explicit .body directive,
2696 the prologue ends after the last instruction
2697 covered by an unwind directive. */
2698 if (ptr->r.type != body)
2699 {
2700 last_addr = last->slot_number;
f5a30c2e 2701 last_frag = last->slot_frag;
542d6675
KH		 2702 switch (last->r.type)
2703 {
2704 case frgr_mem:
2705 dir_len = (count_bits (last->r.record.p.frmask)
2706 + count_bits (last->r.record.p.grmask));
2707 break;
2708 case fr_mem:
2709 case gr_mem:
2710 dir_len += count_bits (last->r.record.p.rmask);
2711 break;
2712 case br_mem:
2713 case br_gr:
2714 dir_len += count_bits (last->r.record.p.brmask);
2715 break;
2716 case gr_gr:
2717 dir_len += count_bits (last->r.record.p.grmask);
2718 break;
2719 default:
2720 dir_len = 1;
2721 break;
2722 }
2723 }
2724 break;
2725 }
f5a30c2e
JW		 2726 size = (slot_index (last_addr, last_frag, first_addr, first_frag)
2727 + dir_len);
542d6675 2728 rlen = ptr->r.record.r.rlen = size;
1e16b528
AS		 2729 if (ptr->r.type == body)
2730 /* End of region. */
2731 region = 0;
2732 else
2733 region = ptr;
e0c9811a 2734 break;
542d6675
KH		 2735 }
2736 case epilogue:
2737 ptr->r.record.b.t = rlen - 1 - t;
2738 break;
e0c9811a 2739
542d6675
KH		 2740 case mem_stack_f:
2741 case mem_stack_v:
2742 case rp_when:
2743 case pfs_when:
2744 case preds_when:
2745 case unat_when:
2746 case lc_when:
2747 case fpsr_when:
2748 case priunat_when_gr:
2749 case priunat_when_mem:
2750 case bsp_when:
2751 case bspstore_when:
2752 case rnat_when:
2753 ptr->r.record.p.t = t;
2754 break;
e0c9811a 2755
542d6675
KH		 2756 case spill_reg:
2757 case spill_sprel:
2758 case spill_psprel:
2759 case spill_reg_p:
2760 case spill_sprel_p:
2761 case spill_psprel_p:
2762 ptr->r.record.x.t = t;
2763 break;
e0c9811a 2764
542d6675
KH		 2765 case frgr_mem:
2766 if (!region)
2767 {
2768 as_bad ("frgr_mem record before region record!\n");
2769 return;
2770 }
2771 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2772 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2773 set_imask (region, ptr->r.record.p.frmask, t, 1);
2774 set_imask (region, ptr->r.record.p.grmask, t, 2);
2775 break;
2776 case fr_mem:
2777 if (!region)
2778 {
2779 as_bad ("fr_mem record before region record!\n");
2780 return;
2781 }
2782 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2783 set_imask (region, ptr->r.record.p.rmask, t, 1);
2784 break;
2785 case gr_mem:
2786 if (!region)
2787 {
2788 as_bad ("gr_mem record before region record!\n");
2789 return;
2790 }
2791 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2792 set_imask (region, ptr->r.record.p.rmask, t, 2);
2793 break;
2794 case br_mem:
2795 if (!region)
2796 {
2797 as_bad ("br_mem record before region record!\n");
2798 return;
2799 }
2800 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2801 set_imask (region, ptr->r.record.p.brmask, t, 3);
2802 break;
e0c9811a 2803
542d6675
KH		 2804 case gr_gr:
2805 if (!region)
2806 {
2807 as_bad ("gr_gr record before region record!\n");
2808 return;
2809 }
2810 set_imask (region, ptr->r.record.p.grmask, t, 2);
2811 break;
2812 case br_gr:
2813 if (!region)
2814 {
2815 as_bad ("br_gr record before region record!\n");
2816 return;
2817 }
2818 set_imask (region, ptr->r.record.p.brmask, t, 3);
2819 break;
e0c9811a 2820
542d6675
KH		 2821 default:
2822 break;
800eeca4
JW		 2823 }
2824 }
2825}
2826
557debba
JW		 2827/* Helper routine for output_unw_records. Emits the header for the unwind
2828 info. */
2829
2830static int
07726851 2831setup_unwind_header (int size, unsigned char **mem)
557debba
JW		 2832{
2833 int x, extra = 0;
1cd8ff38 2834 valueT flag_value;
557debba
JW		 2835
2836 /* pad to pointer-size boundry. */
2837 x = size % md.pointer_size;
2838 if (x != 0)
2839 extra = md.pointer_size - x;
2840
40449e9f 2841 /* Add 8 for the header + a pointer for the
557debba
JW		 2842 personality offset. */
2843 *mem = xmalloc (size + extra + 8 + md.pointer_size);
2844
2845 /* Clear the padding area and personality. */
40449e9f 2846 memset (*mem + 8 + size, 0, extra + md.pointer_size);
1cd8ff38 2847
557debba 2848 /* Initialize the header area. */
1cd8ff38
NC		 2849 if (unwind.personality_routine)
2850 {
2851 if (md.flags & EF_IA_64_ABI64)
2852 flag_value = (bfd_vma) 3 << 32;
2853 else
2854 /* 32-bit unwind info block. */
2855 flag_value = (bfd_vma) 0x1003 << 32;
2856 }
2857 else
2858 flag_value = 0;
557debba 2859
1cd8ff38
NC		 2860 md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */
2861 | flag_value /* U & E handler flags. */
2862 | ((size + extra) / md.pointer_size)), /* Length. */
557debba
JW		 2863 8);
2864
2865 return extra;
2866}
2867
800eeca4
JW		 2868/* Generate an unwind image from a record list. Returns the number of
2869 bytes in the resulting image. The memory image itselof is returned
2870 in the 'ptr' parameter. */
2871static int
2872output_unw_records (list, ptr)
2873 unw_rec_list *list;
2874 void **ptr;
2875{
557debba 2876 int size, extra;
800eeca4
JW		 2877 unsigned char *mem;
2878
91a2ae2a
RH		 2879 *ptr = NULL;
2880
2881 list = optimize_unw_records (list);
800eeca4
JW		 2882 fixup_unw_records (list);
2883 size = calc_record_size (list);
2884
91a2ae2a
RH		 2885 if (size > 0 || unwind.force_unwind_entry)
2886 {
2887 unwind.force_unwind_entry = 0;
07726851 2888 extra = setup_unwind_header (size, &mem);
800eeca4 2889
91a2ae2a 2890 vbyte_mem_ptr = mem + 8;
91a2ae2a
RH		 2891 process_unw_records (list, output_vbyte_mem);
2892
2893 *ptr = mem;
2894
557debba 2895 size += extra + 8 + md.pointer_size;
91a2ae2a
RH		 2896 }
2897 return size;
800eeca4
JW		 2898}
2899
e0c9811a
JW		 2900static int
2901convert_expr_to_ab_reg (e, ab, regp)
2902 expressionS *e;
2903 unsigned int *ab;
2904 unsigned int *regp;
2905{
2906 unsigned int reg;
2907
2908 if (e->X_op != O_register)
2909 return 0;
2910
2911 reg = e->X_add_number;
2434f565 2912 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7))
e0c9811a
JW		 2913 {
2914 *ab = 0;
2915 *regp = reg - REG_GR;
2916 }
2434f565
JW		 2917 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5))
2918 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31)))
e0c9811a
JW		 2919 {
2920 *ab = 1;
2921 *regp = reg - REG_FR;
2922 }
2434f565 2923 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5))
e0c9811a
JW		 2924 {
2925 *ab = 2;
2926 *regp = reg - REG_BR;
2927 }
2928 else
2929 {
2930 *ab = 3;
2931 switch (reg)
2932 {
2933 case REG_PR: *regp = 0; break;
2934 case REG_PSP: *regp = 1; break;
2935 case REG_PRIUNAT: *regp = 2; break;
2936 case REG_BR + 0: *regp = 3; break;
2937 case REG_AR + AR_BSP: *regp = 4; break;
2938 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2939 case REG_AR + AR_RNAT: *regp = 6; break;
2940 case REG_AR + AR_UNAT: *regp = 7; break;
2941 case REG_AR + AR_FPSR: *regp = 8; break;
2942 case REG_AR + AR_PFS: *regp = 9; break;
2943 case REG_AR + AR_LC: *regp = 10; break;
2944
2945 default:
2946 return 0;
2947 }
2948 }
2949 return 1;
197865e8 2950}
e0c9811a
JW		 2951
2952static int
2953convert_expr_to_xy_reg (e, xy, regp)
2954 expressionS *e;
2955 unsigned int *xy;
2956 unsigned int *regp;
2957{
2958 unsigned int reg;
2959
2960 if (e->X_op != O_register)
2961 return 0;
2962
2963 reg = e->X_add_number;
2964
2434f565 2965 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127))
e0c9811a
JW		 2966 {
2967 *xy = 0;
2968 *regp = reg - REG_GR;
2969 }
2434f565 2970 else if (reg >= REG_FR && reg <= (REG_FR + 127))
e0c9811a
JW		 2971 {
2972 *xy = 1;
2973 *regp = reg - REG_FR;
2974 }
2434f565 2975 else if (reg >= REG_BR && reg <= (REG_BR + 7))
e0c9811a
JW		 2976 {
2977 *xy = 2;
2978 *regp = reg - REG_BR;
2979 }
2980 else
2981 return -1;
2982 return 1;
197865e8 2983}
e0c9811a 2984
800eeca4
JW		 2985static void
2986dot_radix (dummy)
2434f565 2987 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 2988{
2989 int radix;
2990
2991 SKIP_WHITESPACE ();
2992 radix = *input_line_pointer++;
2993
2994 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2995 {
2996 as_bad ("Radix `%c' unsupported", *input_line_pointer);
542d6675 2997 ignore_rest_of_line ();
800eeca4
JW		 2998 return;
2999 }
3000}
3001
3002/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
3003static void
3004dot_special_section (which)
3005 int which;
3006{
3007 set_section ((char *) special_section_name[which]);
3008}
3009
3010static void
3011add_unwind_entry (ptr)
3012 unw_rec_list *ptr;
3013{
e0c9811a
JW		 3014 if (unwind.tail)
3015 unwind.tail->next = ptr;
800eeca4 3016 else
e0c9811a
JW		 3017 unwind.list = ptr;
3018 unwind.tail = ptr;
800eeca4
JW		 3019
3020 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW		 3021 if (unwind.current_entry == NULL)
3022 unwind.current_entry = ptr;
800eeca4
JW		 3023}
3024
197865e8 3025static void
800eeca4 3026dot_fframe (dummy)
2434f565 3027 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3028{
3029 expressionS e;
e0c9811a 3030
800eeca4 3031 parse_operand (&e);
197865e8 3032
800eeca4
JW		 3033 if (e.X_op != O_constant)
3034 as_bad ("Operand to .fframe must be a constant");
3035 else
e0c9811a
JW		 3036 add_unwind_entry (output_mem_stack_f (e.X_add_number));
3037}
3038
197865e8 3039static void
e0c9811a 3040dot_vframe (dummy)
2434f565 3041 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3042{
3043 expressionS e;
3044 unsigned reg;
3045
3046 parse_operand (&e);
3047 reg = e.X_add_number - REG_GR;
3048 if (e.X_op == O_register && reg < 128)
800eeca4 3049 {
e0c9811a 3050 add_unwind_entry (output_mem_stack_v ());
30d25259
RH		 3051 if (! (unwind.prologue_mask & 2))
3052 add_unwind_entry (output_psp_gr (reg));
800eeca4 3053 }
e0c9811a
JW		 3054 else
3055 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW		 3056}
3057
197865e8 3058static void
e0c9811a 3059dot_vframesp (dummy)
2434f565 3060 int dummy ATTRIBUTE_UNUSED;
800eeca4 3061{
e0c9811a
JW		 3062 expressionS e;
3063
3064 parse_operand (&e);
3065 if (e.X_op == O_constant)
3066 {
3067 add_unwind_entry (output_mem_stack_v ());
3068 add_unwind_entry (output_psp_sprel (e.X_add_number));
3069 }
3070 else
69906a9b 3071 as_bad ("Operand to .vframesp must be a constant (sp-relative offset)");
e0c9811a
JW		 3072}
3073
197865e8 3074static void
e0c9811a 3075dot_vframepsp (dummy)
2434f565 3076 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3077{
3078 expressionS e;
3079
3080 parse_operand (&e);
3081 if (e.X_op == O_constant)
3082 {
3083 add_unwind_entry (output_mem_stack_v ());
3084 add_unwind_entry (output_psp_sprel (e.X_add_number));
3085 }
3086 else
69906a9b 3087 as_bad ("Operand to .vframepsp must be a constant (psp-relative offset)");
800eeca4
JW		 3088}
3089
197865e8 3090static void
800eeca4 3091dot_save (dummy)
2434f565 3092 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3093{
3094 expressionS e1, e2;
3095 int sep;
3096 int reg1, reg2;
3097
3098 sep = parse_operand (&e1);
3099 if (sep != ',')
3100 as_bad ("No second operand to .save");
3101 sep = parse_operand (&e2);
3102
e0c9811a 3103 reg1 = e1.X_add_number;
800eeca4 3104 reg2 = e2.X_add_number - REG_GR;
197865e8 3105
800eeca4 3106 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3107 if (e1.X_op == O_register)
800eeca4 3108 {
542d6675 3109 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
800eeca4
JW		 3110 {
3111 switch (reg1)
3112 {
542d6675
KH		 3113 case REG_AR + AR_BSP:
3114 add_unwind_entry (output_bsp_when ());
3115 add_unwind_entry (output_bsp_gr (reg2));
3116 break;
3117 case REG_AR + AR_BSPSTORE:
3118 add_unwind_entry (output_bspstore_when ());
3119 add_unwind_entry (output_bspstore_gr (reg2));
3120 break;
3121 case REG_AR + AR_RNAT:
3122 add_unwind_entry (output_rnat_when ());
3123 add_unwind_entry (output_rnat_gr (reg2));
3124 break;
3125 case REG_AR + AR_UNAT:
3126 add_unwind_entry (output_unat_when ());
3127 add_unwind_entry (output_unat_gr (reg2));
3128 break;
3129 case REG_AR + AR_FPSR:
3130 add_unwind_entry (output_fpsr_when ());
3131 add_unwind_entry (output_fpsr_gr (reg2));
3132 break;
3133 case REG_AR + AR_PFS:
3134 add_unwind_entry (output_pfs_when ());
3135 if (! (unwind.prologue_mask & 4))
3136 add_unwind_entry (output_pfs_gr (reg2));
3137 break;
3138 case REG_AR + AR_LC:
3139 add_unwind_entry (output_lc_when ());
3140 add_unwind_entry (output_lc_gr (reg2));
3141 break;
3142 case REG_BR:
3143 add_unwind_entry (output_rp_when ());
3144 if (! (unwind.prologue_mask & 8))
3145 add_unwind_entry (output_rp_gr (reg2));
3146 break;
3147 case REG_PR:
3148 add_unwind_entry (output_preds_when ());
3149 if (! (unwind.prologue_mask & 1))
3150 add_unwind_entry (output_preds_gr (reg2));
3151 break;
3152 case REG_PRIUNAT:
3153 add_unwind_entry (output_priunat_when_gr ());
3154 add_unwind_entry (output_priunat_gr (reg2));
3155 break;
3156 default:
3157 as_bad ("First operand not a valid register");
800eeca4
JW		 3158 }
3159 }
3160 else
3161 as_bad (" Second operand not a valid register");
3162 }
3163 else
e0c9811a 3164 as_bad ("First operand not a register");
800eeca4
JW		 3165}
3166
197865e8 3167static void
800eeca4 3168dot_restore (dummy)
2434f565 3169 int dummy ATTRIBUTE_UNUSED;
800eeca4 3170{
e0c9811a 3171 expressionS e1, e2;
33d01f33 3172 unsigned long ecount; /* # of _additional_ regions to pop */
e0c9811a
JW		 3173 int sep;
3174
3175 sep = parse_operand (&e1);
3176 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
3177 {
3178 as_bad ("First operand to .restore must be stack pointer (sp)");
3179 return;
3180 }
3181
3182 if (sep == ',')
3183 {
3184 parse_operand (&e2);
33d01f33 3185 if (e2.X_op != O_constant || e2.X_add_number < 0)
e0c9811a 3186 {
33d01f33 3187 as_bad ("Second operand to .restore must be a constant >= 0");
e0c9811a
JW		 3188 return;
3189 }
33d01f33 3190 ecount = e2.X_add_number;
e0c9811a 3191 }
33d01f33
JW		 3192 else
3193 ecount = unwind.prologue_count - 1;
6290819d
NC		 3194
3195 if (ecount >= unwind.prologue_count)
3196 {
3197 as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)",
3198 ecount + 1, unwind.prologue_count);
3199 return;
3200 }
3201
e0c9811a 3202 add_unwind_entry (output_epilogue (ecount));
33d01f33
JW		 3203
3204 if (ecount < unwind.prologue_count)
3205 unwind.prologue_count -= ecount + 1;
3206 else
3207 unwind.prologue_count = 0;
e0c9811a
JW		 3208}
3209
197865e8 3210static void
e0c9811a 3211dot_restorereg (dummy)
2434f565 3212 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3213{
3214 unsigned int ab, reg;
3215 expressionS e;
3216
3217 parse_operand (&e);
3218
3219 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
3220 {
3221 as_bad ("First operand to .restorereg must be a preserved register");
3222 return;
3223 }
3224 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
3225}
3226
197865e8 3227static void
e0c9811a 3228dot_restorereg_p (dummy)
2434f565 3229 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3230{
3231 unsigned int qp, ab, reg;
3232 expressionS e1, e2;
3233 int sep;
3234
3235 sep = parse_operand (&e1);
3236 if (sep != ',')
3237 {
3238 as_bad ("No second operand to .restorereg.p");
3239 return;
3240 }
3241
3242 parse_operand (&e2);
3243
3244 qp = e1.X_add_number - REG_P;
3245 if (e1.X_op != O_register || qp > 63)
3246 {
3247 as_bad ("First operand to .restorereg.p must be a predicate");
3248 return;
3249 }
3250
3251 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3252 {
3253 as_bad ("Second operand to .restorereg.p must be a preserved register");
3254 return;
3255 }
3256 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW		 3257}
3258
3259static int
91a2ae2a
RH		 3260generate_unwind_image (text_name)
3261 const char *text_name;
800eeca4
JW		 3262{
3263 int size;
e39edc66 3264 void *unw_rec;
800eeca4 3265
10850f29
JW		 3266 /* Force out pending instructions, to make sure all unwind records have
3267 a valid slot_number field. */
3268 ia64_flush_insns ();
3269
800eeca4 3270 /* Generate the unwind record. */
e39edc66 3271 size = output_unw_records (unwind.list, &unw_rec);
557debba
JW		 3272 if (size % md.pointer_size != 0)
3273 as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size);
6290819d 3274
800eeca4
JW		 3275 /* If there are unwind records, switch sections, and output the info. */
3276 if (size != 0)
3277 {
800eeca4 3278 unsigned char *where;
91a2ae2a 3279 char *sec_name;
800eeca4 3280 expressionS exp;
1cd8ff38 3281 bfd_reloc_code_real_type reloc;
91a2ae2a
RH		 3282
3283 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name);
3284 set_section (sec_name);
3285 bfd_set_section_flags (stdoutput, now_seg,
3286 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
800eeca4 3287
557debba
JW		 3288 /* Make sure the section has 4 byte alignment for ILP32 and
3289 8 byte alignment for LP64. */
3290 frag_align (md.pointer_size_shift, 0, 0);
3291 record_alignment (now_seg, md.pointer_size_shift);
5e7474a7 3292
800eeca4 3293 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 3294 unwind.info = expr_build_dot ();
800eeca4 3295
542d6675 3296 where = (unsigned char *) frag_more (size);
800eeca4
JW		 3297
3298 /* Issue a label for this address, and keep track of it to put it
3299 in the unwind section. */
3300
3301 /* Copy the information from the unwind record into this section. The
3302 data is already in the correct byte order. */
3303 memcpy (where, unw_rec, size);
91a2ae2a 3304
800eeca4 3305 /* Add the personality address to the image. */
e0c9811a 3306 if (unwind.personality_routine != 0)
542d6675 3307 {
40449e9f 3308 exp.X_op = O_symbol;
e0c9811a 3309 exp.X_add_symbol = unwind.personality_routine;
800eeca4 3310 exp.X_add_number = 0;
1cd8ff38
NC		 3311
3312 if (md.flags & EF_IA_64_BE)
3313 {
3314 if (md.flags & EF_IA_64_ABI64)
3315 reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB;
3316 else
3317 reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB;
3318 }
40449e9f 3319 else
1cd8ff38
NC		 3320 {
3321 if (md.flags & EF_IA_64_ABI64)
3322 reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB;
3323 else
3324 reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB;
3325 }
3326
3327 fix_new_exp (frag_now, frag_now_fix () - md.pointer_size,
40449e9f 3328 md.pointer_size, &exp, 0, reloc);
e0c9811a 3329 unwind.personality_routine = 0;
542d6675 3330 }
800eeca4
JW		 3331 }
3332
e0c9811a 3333 free_list_records (unwind.list);
6290819d 3334 free_saved_prologue_counts ();
e0c9811a 3335 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW		 3336
3337 return size;
3338}
3339
197865e8 3340static void
542d6675 3341dot_handlerdata (dummy)
2434f565 3342 int dummy ATTRIBUTE_UNUSED;
800eeca4 3343{
91a2ae2a
RH		 3344 const char *text_name = segment_name (now_seg);
3345
3346 /* If text section name starts with ".text" (which it should),
3347 strip this prefix off. */
3348 if (strcmp (text_name, ".text") == 0)
3349 text_name = "";
3350
3351 unwind.force_unwind_entry = 1;
3352
3353 /* Remember which segment we're in so we can switch back after .endp */
3354 unwind.saved_text_seg = now_seg;
3355 unwind.saved_text_subseg = now_subseg;
3356
3357 /* Generate unwind info into unwind-info section and then leave that
3358 section as the currently active one so dataXX directives go into
3359 the language specific data area of the unwind info block. */
3360 generate_unwind_image (text_name);
e0c9811a 3361 demand_empty_rest_of_line ();
800eeca4
JW		 3362}
3363
197865e8 3364static void
800eeca4 3365dot_unwentry (dummy)
2434f565 3366 int dummy ATTRIBUTE_UNUSED;
800eeca4 3367{
91a2ae2a 3368 unwind.force_unwind_entry = 1;
e0c9811a 3369 demand_empty_rest_of_line ();
800eeca4
JW		 3370}
3371
197865e8 3372static void
800eeca4 3373dot_altrp (dummy)
2434f565 3374 int dummy ATTRIBUTE_UNUSED;
800eeca4 3375{
e0c9811a
JW		 3376 expressionS e;
3377 unsigned reg;
3378
3379 parse_operand (&e);
3380 reg = e.X_add_number - REG_BR;
3381 if (e.X_op == O_register && reg < 8)
3382 add_unwind_entry (output_rp_br (reg));
3383 else
3384 as_bad ("First operand not a valid branch register");
800eeca4
JW		 3385}
3386
197865e8 3387static void
e0c9811a
JW		 3388dot_savemem (psprel)
3389 int psprel;
800eeca4
JW		 3390{
3391 expressionS e1, e2;
3392 int sep;
3393 int reg1, val;
3394
3395 sep = parse_operand (&e1);
3396 if (sep != ',')
e0c9811a 3397 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW		 3398 sep = parse_operand (&e2);
3399
e0c9811a 3400 reg1 = e1.X_add_number;
800eeca4 3401 val = e2.X_add_number;
197865e8 3402
800eeca4 3403 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3404 if (e1.X_op == O_register)
800eeca4
JW		 3405 {
3406 if (e2.X_op == O_constant)
3407 {
3408 switch (reg1)
3409 {
542d6675
KH		 3410 case REG_AR + AR_BSP:
3411 add_unwind_entry (output_bsp_when ());
3412 add_unwind_entry ((psprel
3413 ? output_bsp_psprel
3414 : output_bsp_sprel) (val));
3415 break;
3416 case REG_AR + AR_BSPSTORE:
3417 add_unwind_entry (output_bspstore_when ());
3418 add_unwind_entry ((psprel
3419 ? output_bspstore_psprel
3420 : output_bspstore_sprel) (val));
3421 break;
3422 case REG_AR + AR_RNAT:
3423 add_unwind_entry (output_rnat_when ());
3424 add_unwind_entry ((psprel
3425 ? output_rnat_psprel
3426 : output_rnat_sprel) (val));
3427 break;
3428 case REG_AR + AR_UNAT:
3429 add_unwind_entry (output_unat_when ());
3430 add_unwind_entry ((psprel
3431 ? output_unat_psprel
3432 : output_unat_sprel) (val));
3433 break;
3434 case REG_AR + AR_FPSR:
3435 add_unwind_entry (output_fpsr_when ());
3436 add_unwind_entry ((psprel
3437 ? output_fpsr_psprel
3438 : output_fpsr_sprel) (val));
3439 break;
3440 case REG_AR + AR_PFS:
3441 add_unwind_entry (output_pfs_when ());
3442 add_unwind_entry ((psprel
3443 ? output_pfs_psprel
3444 : output_pfs_sprel) (val));
3445 break;
3446 case REG_AR + AR_LC:
3447 add_unwind_entry (output_lc_when ());
3448 add_unwind_entry ((psprel
3449 ? output_lc_psprel
3450 : output_lc_sprel) (val));
3451 break;
3452 case REG_BR:
3453 add_unwind_entry (output_rp_when ());
3454 add_unwind_entry ((psprel
3455 ? output_rp_psprel
3456 : output_rp_sprel) (val));
3457 break;
3458 case REG_PR:
3459 add_unwind_entry (output_preds_when ());
3460 add_unwind_entry ((psprel
3461 ? output_preds_psprel
3462 : output_preds_sprel) (val));
3463 break;
3464 case REG_PRIUNAT:
3465 add_unwind_entry (output_priunat_when_mem ());
3466 add_unwind_entry ((psprel
3467 ? output_priunat_psprel
3468 : output_priunat_sprel) (val));
3469 break;
3470 default:
3471 as_bad ("First operand not a valid register");
800eeca4
JW		 3472 }
3473 }
3474 else
3475 as_bad (" Second operand not a valid constant");
3476 }
3477 else
e0c9811a 3478 as_bad ("First operand not a register");
800eeca4
JW		 3479}
3480
197865e8 3481static void
800eeca4 3482dot_saveg (dummy)
2434f565 3483 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3484{
3485 expressionS e1, e2;
3486 int sep;
3487 sep = parse_operand (&e1);
3488 if (sep == ',')
3489 parse_operand (&e2);
197865e8 3490
800eeca4
JW		 3491 if (e1.X_op != O_constant)
3492 as_bad ("First operand to .save.g must be a constant.");
3493 else
3494 {
3495 int grmask = e1.X_add_number;
3496 if (sep != ',')
3497 add_unwind_entry (output_gr_mem (grmask));
3498 else
542d6675 3499 {
800eeca4 3500 int reg = e2.X_add_number - REG_GR;
542d6675 3501 if (e2.X_op == O_register && reg >= 0 && reg < 128)
800eeca4
JW		 3502 add_unwind_entry (output_gr_gr (grmask, reg));
3503 else
3504 as_bad ("Second operand is an invalid register.");
3505 }
3506 }
3507}
3508
197865e8 3509static void
800eeca4 3510dot_savef (dummy)
2434f565 3511 int dummy ATTRIBUTE_UNUSED;
800eeca4 3512{
e0c9811a 3513 expressionS e1;
800eeca4
JW		 3514 int sep;
3515 sep = parse_operand (&e1);
197865e8 3516
800eeca4
JW		 3517 if (e1.X_op != O_constant)
3518 as_bad ("Operand to .save.f must be a constant.");
3519 else
e0c9811a 3520 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW		 3521}
3522
197865e8 3523static void
800eeca4 3524dot_saveb (dummy)
2434f565 3525 int dummy ATTRIBUTE_UNUSED;
800eeca4 3526{
e0c9811a
JW		 3527 expressionS e1, e2;
3528 unsigned int reg;
3529 unsigned char sep;
3530 int brmask;
3531
800eeca4 3532 sep = parse_operand (&e1);
800eeca4 3533 if (e1.X_op != O_constant)
800eeca4 3534 {
e0c9811a
JW		 3535 as_bad ("First operand to .save.b must be a constant.");
3536 return;
800eeca4 3537 }
e0c9811a
JW		 3538 brmask = e1.X_add_number;
3539
3540 if (sep == ',')
3541 {
3542 sep = parse_operand (&e2);
3543 reg = e2.X_add_number - REG_GR;
3544 if (e2.X_op != O_register || reg > 127)
3545 {
3546 as_bad ("Second operand to .save.b must be a general register.");
3547 return;
3548 }
3549 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3550 }
3551 else
3552 add_unwind_entry (output_br_mem (brmask));
3553
3554 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3555 ignore_rest_of_line ();
800eeca4
JW		 3556}
3557
197865e8 3558static void
800eeca4 3559dot_savegf (dummy)
2434f565 3560 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3561{
3562 expressionS e1, e2;
3563 int sep;
3564 sep = parse_operand (&e1);
3565 if (sep == ',')
3566 parse_operand (&e2);
197865e8 3567
800eeca4
JW		 3568 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3569 as_bad ("Both operands of .save.gf must be constants.");
3570 else
3571 {
3572 int grmask = e1.X_add_number;
3573 int frmask = e2.X_add_number;
3574 add_unwind_entry (output_frgr_mem (grmask, frmask));
3575 }
3576}
3577
197865e8 3578static void
800eeca4 3579dot_spill (dummy)
2434f565 3580 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3581{
3582 expressionS e;
e0c9811a
JW		 3583 unsigned char sep;
3584
3585 sep = parse_operand (&e);
3586 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3587 ignore_rest_of_line ();
197865e8 3588
800eeca4
JW		 3589 if (e.X_op != O_constant)
3590 as_bad ("Operand to .spill must be a constant");
3591 else
e0c9811a
JW		 3592 add_unwind_entry (output_spill_base (e.X_add_number));
3593}
3594
3595static void
3596dot_spillreg (dummy)
2434f565 3597 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3598{
3599 int sep, ab, xy, reg, treg;
3600 expressionS e1, e2;
3601
3602 sep = parse_operand (&e1);
3603 if (sep != ',')
3604 {
3605 as_bad ("No second operand to .spillreg");
3606 return;
3607 }
3608
3609 parse_operand (&e2);
3610
3611 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3612 {
e0c9811a
JW		 3613 as_bad ("First operand to .spillreg must be a preserved register");
3614 return;
800eeca4 3615 }
e0c9811a
JW		 3616
3617 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3618 {
3619 as_bad ("Second operand to .spillreg must be a register");
3620 return;
3621 }
3622
3623 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3624}
3625
3626static void
3627dot_spillmem (psprel)
3628 int psprel;
3629{
3630 expressionS e1, e2;
3631 int sep, ab, reg;
3632
3633 sep = parse_operand (&e1);
3634 if (sep != ',')
3635 {
3636 as_bad ("Second operand missing");
3637 return;
3638 }
3639
3640 parse_operand (&e2);
3641
3642 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3643 {
3644 as_bad ("First operand to .spill%s must be a preserved register",
3645 psprel ? "psp" : "sp");
3646 return;
3647 }
3648
3649 if (e2.X_op != O_constant)
3650 {
3651 as_bad ("Second operand to .spill%s must be a constant",
3652 psprel ? "psp" : "sp");
3653 return;
3654 }
3655
3656 if (psprel)
3657 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3658 else
3659 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3660}
3661
3662static void
3663dot_spillreg_p (dummy)
2434f565 3664 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3665{
3666 int sep, ab, xy, reg, treg;
3667 expressionS e1, e2, e3;
3668 unsigned int qp;
3669
3670 sep = parse_operand (&e1);
3671 if (sep != ',')
3672 {
3673 as_bad ("No second and third operand to .spillreg.p");
3674 return;
3675 }
3676
3677 sep = parse_operand (&e2);
3678 if (sep != ',')
3679 {
3680 as_bad ("No third operand to .spillreg.p");
3681 return;
3682 }
3683
3684 parse_operand (&e3);
3685
3686 qp = e1.X_add_number - REG_P;
3687
3688 if (e1.X_op != O_register || qp > 63)
3689 {
3690 as_bad ("First operand to .spillreg.p must be a predicate");
3691 return;
3692 }
3693
3694 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3695 {
3696 as_bad ("Second operand to .spillreg.p must be a preserved register");
3697 return;
3698 }
3699
3700 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3701 {
3702 as_bad ("Third operand to .spillreg.p must be a register");
3703 return;
3704 }
3705
3706 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3707}
3708
3709static void
3710dot_spillmem_p (psprel)
3711 int psprel;
3712{
3713 expressionS e1, e2, e3;
3714 int sep, ab, reg;
3715 unsigned int qp;
3716
3717 sep = parse_operand (&e1);
3718 if (sep != ',')
3719 {
3720 as_bad ("Second operand missing");
3721 return;
3722 }
3723
3724 parse_operand (&e2);
3725 if (sep != ',')
3726 {
3727 as_bad ("Second operand missing");
3728 return;
3729 }
3730
3731 parse_operand (&e3);
3732
3733 qp = e1.X_add_number - REG_P;
3734 if (e1.X_op != O_register || qp > 63)
3735 {
3736 as_bad ("First operand to .spill%s_p must be a predicate",
3737 psprel ? "psp" : "sp");
3738 return;
3739 }
3740
3741 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3742 {
3743 as_bad ("Second operand to .spill%s_p must be a preserved register",
3744 psprel ? "psp" : "sp");
3745 return;
3746 }
3747
3748 if (e3.X_op != O_constant)
3749 {
3750 as_bad ("Third operand to .spill%s_p must be a constant",
3751 psprel ? "psp" : "sp");
3752 return;
3753 }
3754
3755 if (psprel)
fa7fda74 3756 add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp));
e0c9811a 3757 else
fa7fda74 3758 add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp));
e0c9811a
JW		 3759}
3760
6290819d
NC		 3761static unsigned int
3762get_saved_prologue_count (lbl)
3763 unsigned long lbl;
3764{
3765 label_prologue_count *lpc = unwind.saved_prologue_counts;
3766
3767 while (lpc != NULL && lpc->label_number != lbl)
3768 lpc = lpc->next;
3769
3770 if (lpc != NULL)
3771 return lpc->prologue_count;
3772
3773 as_bad ("Missing .label_state %ld", lbl);
3774 return 1;
3775}
3776
3777static void
3778save_prologue_count (lbl, count)
3779 unsigned long lbl;
3780 unsigned int count;
3781{
3782 label_prologue_count *lpc = unwind.saved_prologue_counts;
3783
3784 while (lpc != NULL && lpc->label_number != lbl)
3785 lpc = lpc->next;
3786
3787 if (lpc != NULL)
3788 lpc->prologue_count = count;
3789 else
3790 {
40449e9f 3791 label_prologue_count *new_lpc = xmalloc (sizeof (* new_lpc));
6290819d
NC		 3792
3793 new_lpc->next = unwind.saved_prologue_counts;
3794 new_lpc->label_number = lbl;
3795 new_lpc->prologue_count = count;
3796 unwind.saved_prologue_counts = new_lpc;
3797 }
3798}
3799
3800static void
3801free_saved_prologue_counts ()
3802{
40449e9f
KH		 3803 label_prologue_count *lpc = unwind.saved_prologue_counts;
3804 label_prologue_count *next;
6290819d
NC		 3805
3806 while (lpc != NULL)
3807 {
3808 next = lpc->next;
3809 free (lpc);
3810 lpc = next;
3811 }
3812
3813 unwind.saved_prologue_counts = NULL;
3814}
3815
e0c9811a
JW		 3816static void
3817dot_label_state (dummy)
2434f565 3818 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3819{
3820 expressionS e;
3821
3822 parse_operand (&e);
3823 if (e.X_op != O_constant)
3824 {
3825 as_bad ("Operand to .label_state must be a constant");
3826 return;
3827 }
3828 add_unwind_entry (output_label_state (e.X_add_number));
6290819d 3829 save_prologue_count (e.X_add_number, unwind.prologue_count);
e0c9811a
JW		 3830}
3831
3832static void
3833dot_copy_state (dummy)
2434f565 3834 int dummy ATTRIBUTE_UNUSED;
e0c9811a
JW		 3835{
3836 expressionS e;
3837
3838 parse_operand (&e);
3839 if (e.X_op != O_constant)
3840 {
3841 as_bad ("Operand to .copy_state must be a constant");
3842 return;
3843 }
3844 add_unwind_entry (output_copy_state (e.X_add_number));
6290819d 3845 unwind.prologue_count = get_saved_prologue_count (e.X_add_number);
800eeca4
JW		 3846}
3847
197865e8 3848static void
800eeca4 3849dot_unwabi (dummy)
2434f565 3850 int dummy ATTRIBUTE_UNUSED;
800eeca4 3851{
e0c9811a
JW		 3852 expressionS e1, e2;
3853 unsigned char sep;
3854
3855 sep = parse_operand (&e1);
3856 if (sep != ',')
3857 {
3858 as_bad ("Second operand to .unwabi missing");
3859 return;
3860 }
3861 sep = parse_operand (&e2);
3862 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3863 ignore_rest_of_line ();
3864
3865 if (e1.X_op != O_constant)
3866 {
3867 as_bad ("First operand to .unwabi must be a constant");
3868 return;
3869 }
3870
3871 if (e2.X_op != O_constant)
3872 {
3873 as_bad ("Second operand to .unwabi must be a constant");
3874 return;
3875 }
3876
3877 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW		 3878}
3879
197865e8 3880static void
800eeca4 3881dot_personality (dummy)
2434f565 3882 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3883{
3884 char *name, *p, c;
3885 SKIP_WHITESPACE ();
3886 name = input_line_pointer;
3887 c = get_symbol_end ();
3888 p = input_line_pointer;
e0c9811a 3889 unwind.personality_routine = symbol_find_or_make (name);
91a2ae2a 3890 unwind.force_unwind_entry = 1;
800eeca4
JW		 3891 *p = c;
3892 SKIP_WHITESPACE ();
3893 demand_empty_rest_of_line ();
3894}
3895
3896static void
3897dot_proc (dummy)
2434f565 3898 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3899{
3900 char *name, *p, c;
3901 symbolS *sym;
3902
e0c9811a
JW		 3903 unwind.proc_start = expr_build_dot ();
3904 /* Parse names of main and alternate entry points and mark them as
542d6675 3905 function symbols: */
800eeca4
JW		 3906 while (1)
3907 {
3908 SKIP_WHITESPACE ();
3909 name = input_line_pointer;
3910 c = get_symbol_end ();
3911 p = input_line_pointer;
3912 sym = symbol_find_or_make (name);
e0c9811a 3913 if (unwind.proc_start == 0)
542d6675 3914 {
e0c9811a 3915 unwind.proc_start = sym;
800eeca4
JW		 3916 }
3917 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3918 *p = c;
3919 SKIP_WHITESPACE ();
3920 if (*input_line_pointer != ',')
3921 break;
3922 ++input_line_pointer;
3923 }
3924 demand_empty_rest_of_line ();
3925 ia64_do_align (16);
3926
33d01f33 3927 unwind.prologue_count = 0;
e0c9811a
JW		 3928 unwind.list = unwind.tail = unwind.current_entry = NULL;
3929 unwind.personality_routine = 0;
800eeca4
JW		 3930}
3931
3932static void
3933dot_body (dummy)
2434f565 3934 int dummy ATTRIBUTE_UNUSED;
800eeca4 3935{
e0c9811a 3936 unwind.prologue = 0;
30d25259
RH		 3937 unwind.prologue_mask = 0;
3938
800eeca4 3939 add_unwind_entry (output_body ());
e0c9811a 3940 demand_empty_rest_of_line ();
800eeca4
JW		 3941}
3942
3943static void
3944dot_prologue (dummy)
2434f565 3945 int dummy ATTRIBUTE_UNUSED;
800eeca4 3946{
e0c9811a 3947 unsigned char sep;
2434f565 3948 int mask = 0, grsave = 0;
e0c9811a 3949
e0c9811a 3950 if (!is_it_end_of_statement ())
800eeca4
JW		 3951 {
3952 expressionS e1, e2;
800eeca4
JW		 3953 sep = parse_operand (&e1);
3954 if (sep != ',')
3955 as_bad ("No second operand to .prologue");
3956 sep = parse_operand (&e2);
e0c9811a 3957 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
542d6675 3958 ignore_rest_of_line ();
800eeca4
JW		 3959
3960 if (e1.X_op == O_constant)
542d6675 3961 {
30d25259
RH		 3962 mask = e1.X_add_number;
3963
800eeca4 3964 if (e2.X_op == O_constant)
30d25259
RH		 3965 grsave = e2.X_add_number;
3966 else if (e2.X_op == O_register
3967 && (grsave = e2.X_add_number - REG_GR) < 128)
3968 ;
800eeca4 3969 else
30d25259
RH		 3970 as_bad ("Second operand not a constant or general register");
3971
3972 add_unwind_entry (output_prologue_gr (mask, grsave));
800eeca4
JW		 3973 }
3974 else
3975 as_bad ("First operand not a constant");
3976 }
3977 else
3978 add_unwind_entry (output_prologue ());
30d25259
RH		 3979
3980 unwind.prologue = 1;
3981 unwind.prologue_mask = mask;
33d01f33 3982 ++unwind.prologue_count;
800eeca4
JW		 3983}
3984
3985static void
3986dot_endp (dummy)
2434f565 3987 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 3988{
3989 expressionS e;
3990 unsigned char *ptr;
44f5c83a 3991 int bytes_per_address;
800eeca4
JW		 3992 long where;
3993 segT saved_seg;
3994 subsegT saved_subseg;
91a2ae2a 3995 const char *sec_name, *text_name;
c538998c
JJ		 3996 char *name, *p, c;
3997 symbolS *sym;
800eeca4 3998
91a2ae2a
RH		 3999 if (unwind.saved_text_seg)
4000 {
4001 saved_seg = unwind.saved_text_seg;
4002 saved_subseg = unwind.saved_text_subseg;
4003 unwind.saved_text_seg = NULL;
4004 }
4005 else
4006 {
4007 saved_seg = now_seg;
4008 saved_subseg = now_subseg;
4009 }
4010
4011 /*
4012 Use a slightly ugly scheme to derive the unwind section names from
4013 the text section name:
4014
4015 text sect. unwind table sect.
4016 name: name: comments:
4017 ---------- ----------------- --------------------------------
4018 .text .IA_64.unwind
4019 .text.foo .IA_64.unwind.text.foo
4020 .foo .IA_64.unwind.foo
579f31ac
JJ		 4021 .gnu.linkonce.t.foo
4022 .gnu.linkonce.ia64unw.foo
91a2ae2a
RH		 4023 _info .IA_64.unwind_info gas issues error message (ditto)
4024 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
4025
4026 This mapping is done so that:
4027
4028 (a) An object file with unwind info only in .text will use
4029 unwind section names .IA_64.unwind and .IA_64.unwind_info.
4030 This follows the letter of the ABI and also ensures backwards
4031 compatibility with older toolchains.
4032
4033 (b) An object file with unwind info in multiple text sections
4034 will use separate unwind sections for each text section.
4035 This allows us to properly set the "sh_info" and "sh_link"
4036 fields in SHT_IA_64_UNWIND as required by the ABI and also
4037 lets GNU ld support programs with multiple segments
4038 containing unwind info (as might be the case for certain
4039 embedded applications).
40449e9f 4040
91a2ae2a
RH		 4041 (c) An error is issued if there would be a name clash.
4042 */
4043 text_name = segment_name (saved_seg);
4044 if (strncmp (text_name, "_info", 5) == 0)
4045 {
4046 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
4047 text_name);
4048 ignore_rest_of_line ();
4049 return;
4050 }
4051 if (strcmp (text_name, ".text") == 0)
4052 text_name = "";
800eeca4 4053
800eeca4 4054 insn_group_break (1, 0, 0);
800eeca4 4055
91a2ae2a
RH		 4056 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
4057 if (!unwind.info)
4058 generate_unwind_image (text_name);
800eeca4 4059
91a2ae2a
RH		 4060 if (unwind.info || unwind.force_unwind_entry)
4061 {
4062 subseg_set (md.last_text_seg, 0);
4063 unwind.proc_end = expr_build_dot ();
5e7474a7 4064
91a2ae2a
RH		 4065 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name);
4066 set_section ((char *) sec_name);
4067 bfd_set_section_flags (stdoutput, now_seg,
4068 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
5e7474a7 4069
557debba
JW		 4070 /* Make sure that section has 4 byte alignment for ILP32 and
4071 8 byte alignment for LP64. */
4072 record_alignment (now_seg, md.pointer_size_shift);
800eeca4 4073
557debba
JW		 4074 /* Need space for 3 pointers for procedure start, procedure end,
4075 and unwind info. */
4076 ptr = frag_more (3 * md.pointer_size);
4077 where = frag_now_fix () - (3 * md.pointer_size);
91a2ae2a 4078 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
800eeca4 4079
40449e9f 4080 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
91a2ae2a
RH		 4081 e.X_op = O_pseudo_fixup;
4082 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4083 e.X_add_number = 0;
4084 e.X_add_symbol = unwind.proc_start;
4085 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
800eeca4 4086
800eeca4
JW		 4087 e.X_op = O_pseudo_fixup;
4088 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4089 e.X_add_number = 0;
91a2ae2a
RH		 4090 e.X_add_symbol = unwind.proc_end;
4091 ia64_cons_fix_new (frag_now, where + bytes_per_address,
4092 bytes_per_address, &e);
4093
4094 if (unwind.info)
4095 {
4096 e.X_op = O_pseudo_fixup;
4097 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4098 e.X_add_number = 0;
4099 e.X_add_symbol = unwind.info;
4100 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2),
4101 bytes_per_address, &e);
4102 }
4103 else
4104 md_number_to_chars (ptr + (bytes_per_address * 2), 0,
4105 bytes_per_address);
800eeca4 4106
91a2ae2a 4107 }
800eeca4 4108 subseg_set (saved_seg, saved_subseg);
c538998c
JJ		 4109
4110 /* Parse names of main and alternate entry points and set symbol sizes. */
4111 while (1)
4112 {
4113 SKIP_WHITESPACE ();
4114 name = input_line_pointer;
4115 c = get_symbol_end ();
4116 p = input_line_pointer;
4117 sym = symbol_find (name);
4118 if (sym && unwind.proc_start
4119 && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION)
4120 && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL)
4121 {
4122 fragS *fr = symbol_get_frag (unwind.proc_start);
4123 fragS *frag = symbol_get_frag (sym);
4124
4125 /* Check whether the function label is at or beyond last
4126 .proc directive. */
4127 while (fr && fr != frag)
4128 fr = fr->fr_next;
4129 if (fr)
4130 {
4131 if (frag == frag_now && SEG_NORMAL (now_seg))
4132 S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym));
4133 else
4134 {
4135 symbol_get_obj (sym)->size =
4136 (expressionS *) xmalloc (sizeof (expressionS));
4137 symbol_get_obj (sym)->size->X_op = O_subtract;
4138 symbol_get_obj (sym)->size->X_add_symbol
4139 = symbol_new (FAKE_LABEL_NAME, now_seg,
4140 frag_now_fix (), frag_now);
4141 symbol_get_obj (sym)->size->X_op_symbol = sym;
4142 symbol_get_obj (sym)->size->X_add_number = 0;
4143 }
4144 }
4145 }
4146 *p = c;
4147 SKIP_WHITESPACE ();
4148 if (*input_line_pointer != ',')
4149 break;
4150 ++input_line_pointer;
4151 }
4152 demand_empty_rest_of_line ();
e0c9811a 4153 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW		 4154}
4155
4156static void
4157dot_template (template)
4158 int template;
4159{
4160 CURR_SLOT.user_template = template;
4161}
4162
4163static void
4164dot_regstk (dummy)
2434f565 4165 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4166{
4167 int ins, locs, outs, rots;
4168
4169 if (is_it_end_of_statement ())
4170 ins = locs = outs = rots = 0;
4171 else
4172 {
4173 ins = get_absolute_expression ();
4174 if (*input_line_pointer++ != ',')
4175 goto err;
4176 locs = get_absolute_expression ();
4177 if (*input_line_pointer++ != ',')
4178 goto err;
4179 outs = get_absolute_expression ();
4180 if (*input_line_pointer++ != ',')
4181 goto err;
4182 rots = get_absolute_expression ();
4183 }
4184 set_regstack (ins, locs, outs, rots);
4185 return;
4186
4187 err:
4188 as_bad ("Comma expected");
4189 ignore_rest_of_line ();
4190}
4191
4192static void
4193dot_rot (type)
4194 int type;
4195{
4196 unsigned num_regs, num_alloced = 0;
4197 struct dynreg **drpp, *dr;
4198 int ch, base_reg = 0;
4199 char *name, *start;
4200 size_t len;
4201
4202 switch (type)
4203 {
4204 case DYNREG_GR: base_reg = REG_GR + 32; break;
4205 case DYNREG_FR: base_reg = REG_FR + 32; break;
4206 case DYNREG_PR: base_reg = REG_P + 16; break;
4207 default: break;
4208 }
4209
542d6675 4210 /* First, remove existing names from hash table. */
800eeca4
JW		 4211 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
4212 {
4213 hash_delete (md.dynreg_hash, dr->name);
4214 dr->num_regs = 0;
4215 }
4216
4217 drpp = &md.dynreg[type];
4218 while (1)
4219 {
4220 start = input_line_pointer;
4221 ch = get_symbol_end ();
4222 *input_line_pointer = ch;
4223 len = (input_line_pointer - start);
4224
4225 SKIP_WHITESPACE ();
4226 if (*input_line_pointer != '[')
4227 {
4228 as_bad ("Expected '['");
4229 goto err;
4230 }
4231 ++input_line_pointer; /* skip '[' */
4232
4233 num_regs = get_absolute_expression ();
4234
4235 if (*input_line_pointer++ != ']')
4236 {
4237 as_bad ("Expected ']'");
4238 goto err;
4239 }
4240 SKIP_WHITESPACE ();
4241
4242 num_alloced += num_regs;
4243 switch (type)
4244 {
4245 case DYNREG_GR:
4246 if (num_alloced > md.rot.num_regs)
4247 {
4248 as_bad ("Used more than the declared %d rotating registers",
4249 md.rot.num_regs);
4250 goto err;
4251 }
4252 break;
4253 case DYNREG_FR:
4254 if (num_alloced > 96)
4255 {
4256 as_bad ("Used more than the available 96 rotating registers");
4257 goto err;
4258 }
4259 break;
4260 case DYNREG_PR:
4261 if (num_alloced > 48)
4262 {
4263 as_bad ("Used more than the available 48 rotating registers");
4264 goto err;
4265 }
4266 break;
4267
4268 default:
4269 break;
4270 }
4271
4272 name = obstack_alloc (&notes, len + 1);
4273 memcpy (name, start, len);
4274 name[len] = '\0';
4275
4276 if (!*drpp)
4277 {
4278 *drpp = obstack_alloc (&notes, sizeof (*dr));
4279 memset (*drpp, 0, sizeof (*dr));
4280 }
4281
4282 dr = *drpp;
4283 dr->name = name;
4284 dr->num_regs = num_regs;
4285 dr->base = base_reg;
4286 drpp = &dr->next;
4287 base_reg += num_regs;
4288
4289 if (hash_insert (md.dynreg_hash, name, dr))
4290 {
4291 as_bad ("Attempt to redefine register set `%s'", name);
4292 goto err;
4293 }
4294
4295 if (*input_line_pointer != ',')
4296 break;
4297 ++input_line_pointer; /* skip comma */
4298 SKIP_WHITESPACE ();
4299 }
4300 demand_empty_rest_of_line ();
4301 return;
4302
4303 err:
4304 ignore_rest_of_line ();
4305}
4306
4307static void
4308dot_byteorder (byteorder)
4309 int byteorder;
4310{
4311 target_big_endian = byteorder;
4312}
4313
4314static void
4315dot_psr (dummy)
2434f565 4316 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4317{
4318 char *option;
4319 int ch;
4320
4321 while (1)
4322 {
4323 option = input_line_pointer;
4324 ch = get_symbol_end ();
4325 if (strcmp (option, "lsb") == 0)
4326 md.flags &= ~EF_IA_64_BE;
4327 else if (strcmp (option, "msb") == 0)
4328 md.flags |= EF_IA_64_BE;
4329 else if (strcmp (option, "abi32") == 0)
4330 md.flags &= ~EF_IA_64_ABI64;
4331 else if (strcmp (option, "abi64") == 0)
4332 md.flags |= EF_IA_64_ABI64;
4333 else
4334 as_bad ("Unknown psr option `%s'", option);
4335 *input_line_pointer = ch;
4336
4337 SKIP_WHITESPACE ();
4338 if (*input_line_pointer != ',')
4339 break;
4340
4341 ++input_line_pointer;
4342 SKIP_WHITESPACE ();
4343 }
4344 demand_empty_rest_of_line ();
4345}
4346
4347static void
4348dot_alias (dummy)
2434f565 4349 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4350{
4351 as_bad (".alias not implemented yet");
4352}
4353
4354static void
4355dot_ln (dummy)
2434f565 4356 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4357{
4358 new_logical_line (0, get_absolute_expression ());
4359 demand_empty_rest_of_line ();
4360}
4361
542d6675 4362static char *
800eeca4
JW		 4363parse_section_name ()
4364{
4365 char *name;
4366 int len;
4367
4368 SKIP_WHITESPACE ();
4369 if (*input_line_pointer != '"')
4370 {
4371 as_bad ("Missing section name");
4372 ignore_rest_of_line ();
4373 return 0;
4374 }
4375 name = demand_copy_C_string (&len);
4376 if (!name)
4377 {
4378 ignore_rest_of_line ();
4379 return 0;
4380 }
4381 SKIP_WHITESPACE ();
4382 if (*input_line_pointer != ',')
4383 {
4384 as_bad ("Comma expected after section name");
4385 ignore_rest_of_line ();
4386 return 0;
4387 }
4388 ++input_line_pointer; /* skip comma */
4389 return name;
4390}
4391
4392static void
4393dot_xdata (size)
4394 int size;
4395{
4396 char *name = parse_section_name ();
4397 if (!name)
4398 return;
4399
4d5a53ff 4400 md.keep_pending_output = 1;
800eeca4
JW		 4401 set_section (name);
4402 cons (size);
4403 obj_elf_previous (0);
4d5a53ff 4404 md.keep_pending_output = 0;
800eeca4
JW		 4405}
4406
4407/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
542d6675 4408
800eeca4
JW		 4409static void
4410stmt_float_cons (kind)
4411 int kind;
4412{
165a7f90 4413 size_t alignment;
800eeca4
JW		 4414
4415 switch (kind)
4416 {
165a7f90
L		 4417 case 'd':
4418 alignment = 8;
4419 break;
4420
4421 case 'x':
4422 case 'X':
4423 alignment = 16;
4424 break;
800eeca4
JW		 4425
4426 case 'f':
4427 default:
165a7f90 4428 alignment = 4;
800eeca4
JW		 4429 break;
4430 }
165a7f90 4431 ia64_do_align (alignment);
800eeca4
JW		 4432 float_cons (kind);
4433}
4434
4435static void
4436stmt_cons_ua (size)
4437 int size;
4438{
4439 int saved_auto_align = md.auto_align;
4440
4441 md.auto_align = 0;
4442 cons (size);
4443 md.auto_align = saved_auto_align;
4444}
4445
4446static void
4447dot_xfloat_cons (kind)
4448 int kind;
4449{
4450 char *name = parse_section_name ();
4451 if (!name)
4452 return;
4453
4d5a53ff 4454 md.keep_pending_output = 1;
800eeca4
JW		 4455 set_section (name);
4456 stmt_float_cons (kind);
4457 obj_elf_previous (0);
4d5a53ff 4458 md.keep_pending_output = 0;
800eeca4
JW		 4459}
4460
4461static void
4462dot_xstringer (zero)
4463 int zero;
4464{
4465 char *name = parse_section_name ();
4466 if (!name)
4467 return;
4468
4d5a53ff 4469 md.keep_pending_output = 1;
800eeca4
JW		 4470 set_section (name);
4471 stringer (zero);
4472 obj_elf_previous (0);
4d5a53ff 4473 md.keep_pending_output = 0;
800eeca4
JW		 4474}
4475
4476static void
4477dot_xdata_ua (size)
4478 int size;
4479{
4480 int saved_auto_align = md.auto_align;
4481 char *name = parse_section_name ();
4482 if (!name)
4483 return;
4484
4d5a53ff 4485 md.keep_pending_output = 1;
800eeca4
JW		 4486 set_section (name);
4487 md.auto_align = 0;
4488 cons (size);
4489 md.auto_align = saved_auto_align;
4490 obj_elf_previous (0);
4d5a53ff 4491 md.keep_pending_output = 0;
800eeca4
JW		 4492}
4493
4494static void
4495dot_xfloat_cons_ua (kind)
4496 int kind;
4497{
4498 int saved_auto_align = md.auto_align;
4499 char *name = parse_section_name ();
4500 if (!name)
4501 return;
4502
4d5a53ff 4503 md.keep_pending_output = 1;
800eeca4
JW		 4504 set_section (name);
4505 md.auto_align = 0;
4506 stmt_float_cons (kind);
4507 md.auto_align = saved_auto_align;
4508 obj_elf_previous (0);
4d5a53ff 4509 md.keep_pending_output = 0;
800eeca4
JW		 4510}
4511
4512/* .reg.val <regname>,value */
542d6675 4513
800eeca4
JW		 4514static void
4515dot_reg_val (dummy)
2434f565 4516 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4517{
4518 expressionS reg;
4519
4520 expression (&reg);
4521 if (reg.X_op != O_register)
4522 {
4523 as_bad (_("Register name expected"));
4524 ignore_rest_of_line ();
4525 }
4526 else if (*input_line_pointer++ != ',')
4527 {
4528 as_bad (_("Comma expected"));
4529 ignore_rest_of_line ();
4530 }
197865e8 4531 else
800eeca4
JW		 4532 {
4533 valueT value = get_absolute_expression ();
4534 int regno = reg.X_add_number;
542d6675
KH		 4535 if (regno < REG_GR || regno > REG_GR + 128)
4536 as_warn (_("Register value annotation ignored"));
800eeca4 4537 else
542d6675
KH		 4538 {
4539 gr_values[regno - REG_GR].known = 1;
4540 gr_values[regno - REG_GR].value = value;
4541 gr_values[regno - REG_GR].path = md.path;
4542 }
800eeca4
JW		 4543 }
4544 demand_empty_rest_of_line ();
4545}
4546
197865e8 4547/* select dv checking mode
800eeca4
JW		 4548 .auto
4549 .explicit
4550 .default
4551
197865e8 4552 A stop is inserted when changing modes
800eeca4 4553 */
542d6675 4554
800eeca4
JW		 4555static void
4556dot_dv_mode (type)
542d6675 4557 int type;
800eeca4
JW		 4558{
4559 if (md.manual_bundling)
4560 as_warn (_("Directive invalid within a bundle"));
4561
4562 if (type == 'E' || type == 'A')
4563 md.mode_explicitly_set = 0;
4564 else
4565 md.mode_explicitly_set = 1;
4566
4567 md.detect_dv = 1;
4568 switch (type)
4569 {
4570 case 'A':
4571 case 'a':
4572 if (md.explicit_mode)
542d6675 4573 insn_group_break (1, 0, 0);
800eeca4
JW		 4574 md.explicit_mode = 0;
4575 break;
4576 case 'E':
4577 case 'e':
4578 if (!md.explicit_mode)
542d6675 4579 insn_group_break (1, 0, 0);
800eeca4
JW		 4580 md.explicit_mode = 1;
4581 break;
4582 default:
4583 case 'd':
4584 if (md.explicit_mode != md.default_explicit_mode)
542d6675 4585 insn_group_break (1, 0, 0);
800eeca4
JW		 4586 md.explicit_mode = md.default_explicit_mode;
4587 md.mode_explicitly_set = 0;
4588 break;
4589 }
4590}
4591
4592static void
4593print_prmask (mask)
542d6675 4594 valueT mask;
800eeca4
JW		 4595{
4596 int regno;
4597 char *comma = "";
542d6675 4598 for (regno = 0; regno < 64; regno++)
800eeca4 4599 {
542d6675
KH		 4600 if (mask & ((valueT) 1 << regno))
4601 {
4602 fprintf (stderr, "%s p%d", comma, regno);
4603 comma = ",";
4604 }
800eeca4
JW		 4605 }
4606}
4607
4608/*
4609 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4610 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4611 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4612 .pred.safe_across_calls p1 [, p2 [,...]]
4613 */
542d6675 4614
800eeca4
JW		 4615static void
4616dot_pred_rel (type)
542d6675 4617 int type;
800eeca4
JW		 4618{
4619 valueT mask = 0;
4620 int count = 0;
4621 int p1 = -1, p2 = -1;
4622
4623 if (type == 0)
4624 {
4625 if (*input_line_pointer != '"')
542d6675
KH		 4626 {
4627 as_bad (_("Missing predicate relation type"));
4628 ignore_rest_of_line ();
4629 return;
4630 }
197865e8 4631 else
542d6675
KH		 4632 {
4633 int len;
4634 char *form = demand_copy_C_string (&len);
4635 if (strcmp (form, "mutex") == 0)
4636 type = 'm';
4637 else if (strcmp (form, "clear") == 0)
4638 type = 'c';
4639 else if (strcmp (form, "imply") == 0)
4640 type = 'i';
4641 else
4642 {
4643 as_bad (_("Unrecognized predicate relation type"));
4644 ignore_rest_of_line ();
4645 return;
4646 }
4647 }
800eeca4 4648 if (*input_line_pointer == ',')
542d6675 4649 ++input_line_pointer;
800eeca4
JW		 4650 SKIP_WHITESPACE ();
4651 }
4652
4653 SKIP_WHITESPACE ();
4654 while (1)
4655 {
4656 valueT bit = 1;
4657 int regno;
197865e8 4658
3882b010 4659 if (TOUPPER (*input_line_pointer) != 'P'
542d6675
KH		 4660 || (regno = atoi (++input_line_pointer)) < 0
4661 || regno > 63)
4662 {
4663 as_bad (_("Predicate register expected"));
4664 ignore_rest_of_line ();
4665 return;
4666 }
3882b010 4667 while (ISDIGIT (*input_line_pointer))
542d6675 4668 ++input_line_pointer;
800eeca4 4669 if (p1 == -1)
542d6675 4670 p1 = regno;
800eeca4 4671 else if (p2 == -1)
542d6675 4672 p2 = regno;
800eeca4
JW		 4673 bit <<= regno;
4674 if (mask & bit)
542d6675
KH		 4675 as_warn (_("Duplicate predicate register ignored"));
4676 mask |= bit;
4677 count++;
4678 /* See if it's a range. */
800eeca4 4679 if (*input_line_pointer == '-')
542d6675
KH		 4680 {
4681 valueT stop = 1;
4682 ++input_line_pointer;
4683
3882b010 4684 if (TOUPPER (*input_line_pointer) != 'P'
542d6675
KH		 4685 || (regno = atoi (++input_line_pointer)) < 0
4686 || regno > 63)
4687 {
4688 as_bad (_("Predicate register expected"));
4689 ignore_rest_of_line ();
4690 return;
4691 }
3882b010 4692 while (ISDIGIT (*input_line_pointer))
542d6675
KH		 4693 ++input_line_pointer;
4694 stop <<= regno;
4695 if (bit >= stop)
4696 {
4697 as_bad (_("Bad register range"));
4698 ignore_rest_of_line ();
4699 return;
4700 }
4701 while (bit < stop)
4702 {
4703 bit <<= 1;
4704 mask |= bit;
4705 count++;
4706 }
4707 SKIP_WHITESPACE ();
4708 }
800eeca4 4709 if (*input_line_pointer != ',')
542d6675 4710 break;
800eeca4
JW		 4711 ++input_line_pointer;
4712 SKIP_WHITESPACE ();
4713 }
4714
4715 switch (type)
4716 {
4717 case 'c':
4718 if (count == 0)
542d6675 4719 mask = ~(valueT) 0;
800eeca4 4720 clear_qp_mutex (mask);
197865e8 4721 clear_qp_implies (mask, (valueT) 0);
800eeca4
JW		 4722 break;
4723 case 'i':
4724 if (count != 2 || p1 == -1 || p2 == -1)
542d6675 4725 as_bad (_("Predicate source and target required"));
800eeca4 4726 else if (p1 == 0 || p2 == 0)
542d6675 4727 as_bad (_("Use of p0 is not valid in this context"));
800eeca4 4728 else
542d6675 4729 add_qp_imply (p1, p2);
800eeca4
JW		 4730 break;
4731 case 'm':
4732 if (count < 2)
542d6675
KH		 4733 {
4734 as_bad (_("At least two PR arguments expected"));
4735 break;
4736 }
800eeca4 4737 else if (mask & 1)
542d6675
KH		 4738 {
4739 as_bad (_("Use of p0 is not valid in this context"));
4740 break;
4741 }
800eeca4
JW		 4742 add_qp_mutex (mask);
4743 break;
4744 case 's':
4745 /* note that we don't override any existing relations */
4746 if (count == 0)
542d6675
KH		 4747 {
4748 as_bad (_("At least one PR argument expected"));
4749 break;
4750 }
800eeca4 4751 if (md.debug_dv)
542d6675
KH		 4752 {
4753 fprintf (stderr, "Safe across calls: ");
4754 print_prmask (mask);
4755 fprintf (stderr, "\n");
4756 }
800eeca4
JW		 4757 qp_safe_across_calls = mask;
4758 break;
4759 }
4760 demand_empty_rest_of_line ();
4761}
4762
4763/* .entry label [, label [, ...]]
4764 Hint to DV code that the given labels are to be considered entry points.
542d6675
KH		 4765 Otherwise, only global labels are considered entry points. */
4766
800eeca4
JW		 4767static void
4768dot_entry (dummy)
2434f565 4769 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4770{
4771 const char *err;
4772 char *name;
4773 int c;
4774 symbolS *symbolP;
4775
4776 do
4777 {
4778 name = input_line_pointer;
4779 c = get_symbol_end ();
4780 symbolP = symbol_find_or_make (name);
4781
4782 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4783 if (err)
542d6675
KH		 4784 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4785 name, err);
800eeca4
JW		 4786
4787 *input_line_pointer = c;
4788 SKIP_WHITESPACE ();
4789 c = *input_line_pointer;
4790 if (c == ',')
4791 {
4792 input_line_pointer++;
4793 SKIP_WHITESPACE ();
4794 if (*input_line_pointer == '\n')
4795 c = '\n';
4796 }
4797 }
4798 while (c == ',');
4799
4800 demand_empty_rest_of_line ();
4801}
4802
197865e8 4803/* .mem.offset offset, base
542d6675
KH		 4804 "base" is used to distinguish between offsets from a different base. */
4805
800eeca4
JW		 4806static void
4807dot_mem_offset (dummy)
2434f565 4808 int dummy ATTRIBUTE_UNUSED;
800eeca4
JW		 4809{
4810 md.mem_offset.hint = 1;
4811 md.mem_offset.offset = get_absolute_expression ();
4812 if (*input_line_pointer != ',')
4813 {
4814 as_bad (_("Comma expected"));
4815 ignore_rest_of_line ();
4816 return;
4817 }
4818 ++input_line_pointer;
4819 md.mem_offset.base = get_absolute_expression ();
4820 demand_empty_rest_of_line ();
4821}
4822
542d6675 4823/* ia64-specific pseudo-ops: */
800eeca4
JW		 4824const pseudo_typeS md_pseudo_table[] =
4825 {
4826 { "radix", dot_radix, 0 },
4827 { "lcomm", s_lcomm_bytes, 1 },
4828 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4829 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4830 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4831 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4832 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4833 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4834 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
557debba
JW		 4835 { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY },
4836 { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY },
800eeca4
JW		 4837 { "proc", dot_proc, 0 },
4838 { "body", dot_body, 0 },
4839 { "prologue", dot_prologue, 0 },
2434f565 4840 { "endp", dot_endp, 0 },
9f1838ed 4841 { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
2434f565
JW		 4842 { "loc", dwarf2_directive_loc, 0 },
4843
4844 { "fframe", dot_fframe, 0 },
4845 { "vframe", dot_vframe, 0 },
4846 { "vframesp", dot_vframesp, 0 },
4847 { "vframepsp", dot_vframepsp, 0 },
4848 { "save", dot_save, 0 },
4849 { "restore", dot_restore, 0 },
4850 { "restorereg", dot_restorereg, 0 },
4851 { "restorereg.p", dot_restorereg_p, 0 },
4852 { "handlerdata", dot_handlerdata, 0 },
4853 { "unwentry", dot_unwentry, 0 },
4854 { "altrp", dot_altrp, 0 },
e0c9811a
JW		 4855 { "savesp", dot_savemem, 0 },
4856 { "savepsp", dot_savemem, 1 },
2434f565
JW		 4857 { "save.g", dot_saveg, 0 },
4858 { "save.f", dot_savef, 0 },
4859 { "save.b", dot_saveb, 0 },
4860 { "save.gf", dot_savegf, 0 },
4861 { "spill", dot_spill, 0 },
4862 { "spillreg", dot_spillreg, 0 },
e0c9811a
JW		 4863 { "spillsp", dot_spillmem, 0 },
4864 { "spillpsp", dot_spillmem, 1 },
2434f565 4865 { "spillreg.p", dot_spillreg_p, 0 },
e0c9811a
JW		 4866 { "spillsp.p", dot_spillmem_p, 0 },
4867 { "spillpsp.p", dot_spillmem_p, 1 },
2434f565
JW		 4868 { "label_state", dot_label_state, 0 },
4869 { "copy_state", dot_copy_state, 0 },
4870 { "unwabi", dot_unwabi, 0 },
4871 { "personality", dot_personality, 0 },
800eeca4 4872#if 0
2434f565 4873 { "estate", dot_estate, 0 },
800eeca4
JW		 4874#endif
4875 { "mii", dot_template, 0x0 },
4876 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4877 { "mlx", dot_template, 0x2 },
4878 { "mmi", dot_template, 0x4 },
4879 { "mfi", dot_template, 0x6 },
4880 { "mmf", dot_template, 0x7 },
4881 { "mib", dot_template, 0x8 },
4882 { "mbb", dot_template, 0x9 },
4883 { "bbb", dot_template, 0xb },
4884 { "mmb", dot_template, 0xc },
4885 { "mfb", dot_template, 0xe },
4886#if 0
4887 { "lb", dot_scope, 0 },
4888 { "le", dot_scope, 1 },
4889#endif
4890 { "align", s_align_bytes, 0 },
4891 { "regstk", dot_regstk, 0 },
4892 { "rotr", dot_rot, DYNREG_GR },
4893 { "rotf", dot_rot, DYNREG_FR },
4894 { "rotp", dot_rot, DYNREG_PR },
4895 { "lsb", dot_byteorder, 0 },
4896 { "msb", dot_byteorder, 1 },
4897 { "psr", dot_psr, 0 },
4898 { "alias", dot_alias, 0 },
4899 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4900
4901 { "xdata1", dot_xdata, 1 },
4902 { "xdata2", dot_xdata, 2 },
4903 { "xdata4", dot_xdata, 4 },
4904 { "xdata8", dot_xdata, 8 },
4905 { "xreal4", dot_xfloat_cons, 'f' },
4906 { "xreal8", dot_xfloat_cons, 'd' },
4907 { "xreal10", dot_xfloat_cons, 'x' },
165a7f90 4908 { "xreal16", dot_xfloat_cons, 'X' },
800eeca4
JW		 4909 { "xstring", dot_xstringer, 0 },
4910 { "xstringz", dot_xstringer, 1 },
4911
542d6675 4912 /* unaligned versions: */
800eeca4
JW		 4913 { "xdata2.ua", dot_xdata_ua, 2 },
4914 { "xdata4.ua", dot_xdata_ua, 4 },
4915 { "xdata8.ua", dot_xdata_ua, 8 },
4916 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4917 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4918 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
165a7f90 4919 { "xreal16.ua", dot_xfloat_cons_ua, 'X' },
800eeca4
JW		 4920
4921 /* annotations/DV checking support */
4922 { "entry", dot_entry, 0 },
2434f565 4923 { "mem.offset", dot_mem_offset, 0 },
800eeca4
JW		 4924 { "pred.rel", dot_pred_rel, 0 },
4925 { "pred.rel.clear", dot_pred_rel, 'c' },
4926 { "pred.rel.imply", dot_pred_rel, 'i' },
4927 { "pred.rel.mutex", dot_pred_rel, 'm' },
4928 { "pred.safe_across_calls", dot_pred_rel, 's' },
2434f565 4929 { "reg.val", dot_reg_val, 0 },
800eeca4
JW		 4930 { "auto", dot_dv_mode, 'a' },
4931 { "explicit", dot_dv_mode, 'e' },
4932 { "default", dot_dv_mode, 'd' },
4933
87885043
JW		 4934 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4935 IA-64 aligns data allocation pseudo-ops by default, so we have to
4936 tell it that these ones are supposed to be unaligned. Long term,
4937 should rewrite so that only IA-64 specific data allocation pseudo-ops
4938 are aligned by default. */
4939 {"2byte", stmt_cons_ua, 2},
4940 {"4byte", stmt_cons_ua, 4},
4941 {"8byte", stmt_cons_ua, 8},
4942
800eeca4
JW		 4943 { NULL, 0, 0 }
4944 };
4945
4946static const struct pseudo_opcode
4947 {
4948 const char *name;
4949 void (*handler) (int);
4950 int arg;
4951 }
4952pseudo_opcode[] =
4953 {
4954 /* these are more like pseudo-ops, but don't start with a dot */
4955 { "data1", cons, 1 },
4956 { "data2", cons, 2 },
4957 { "data4", cons, 4 },
4958 { "data8", cons, 8 },
3969b680 4959 { "data16", cons, 16 },
800eeca4
JW		 4960 { "real4", stmt_float_cons, 'f' },
4961 { "real8", stmt_float_cons, 'd' },
4962 { "real10", stmt_float_cons, 'x' },
165a7f90 4963 { "real16", stmt_float_cons, 'X' },
800eeca4
JW		 4964 { "string", stringer, 0 },
4965 { "stringz", stringer, 1 },
4966
542d6675 4967 /* unaligned versions: */
800eeca4
JW		 4968 { "data2.ua", stmt_cons_ua, 2 },
4969 { "data4.ua", stmt_cons_ua, 4 },
4970 { "data8.ua", stmt_cons_ua, 8 },
3969b680 4971 { "data16.ua", stmt_cons_ua, 16 },
800eeca4
JW		 4972 { "real4.ua", float_cons, 'f' },
4973 { "real8.ua", float_cons, 'd' },
4974 { "real10.ua", float_cons, 'x' },
165a7f90 4975 { "real16.ua", float_cons, 'X' },
800eeca4
JW		 4976 };
4977
4978/* Declare a register by creating a symbol for it and entering it in
4979 the symbol table. */
542d6675
KH		 4980
4981static symbolS *
800eeca4
JW		 4982declare_register (name, regnum)
4983 const char *name;
4984 int regnum;
4985{
4986 const char *err;
4987 symbolS *sym;
4988
4989 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4990
4991 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4992 if (err)
4993 as_fatal ("Inserting \"%s\" into register table failed: %s",
4994 name, err);
4995
4996 return sym;
4997}
4998
4999static void
5000declare_register_set (prefix, num_regs, base_regnum)
5001 const char *prefix;
5002 int num_regs;
5003 int base_regnum;
5004{
5005 char name[8];
5006 int i;
5007
5008 for (i = 0; i < num_regs; ++i)
5009 {
5010 sprintf (name, "%s%u", prefix, i);
5011 declare_register (name, base_regnum + i);
5012 }
5013}
5014
5015static unsigned int
5016operand_width (opnd)
5017 enum ia64_opnd opnd;
5018{
5019 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
5020 unsigned int bits = 0;
5021 int i;
5022
5023 bits = 0;
5024 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
5025 bits += odesc->field[i].bits;
5026
5027 return bits;
5028}
5029
87f8eb97 5030static enum operand_match_result
800eeca4
JW		 5031operand_match (idesc, index, e)
5032 const struct ia64_opcode *idesc;
5033 int index;
5034 expressionS *e;
5035{
5036 enum ia64_opnd opnd = idesc->operands[index];
5037 int bits, relocatable = 0;
5038 struct insn_fix *fix;
5039 bfd_signed_vma val;
5040
5041 switch (opnd)
5042 {
542d6675 5043 /* constants: */
800eeca4
JW		 5044
5045 case IA64_OPND_AR_CCV:
5046 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
87f8eb97 5047 return OPERAND_MATCH;
800eeca4
JW		 5048 break;
5049
c10d9d8f
JW		 5050 case IA64_OPND_AR_CSD:
5051 if (e->X_op == O_register && e->X_add_number == REG_AR + 25)
5052 return OPERAND_MATCH;
5053 break;
5054
800eeca4
JW		 5055 case IA64_OPND_AR_PFS:
5056 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
87f8eb97 5057 return OPERAND_MATCH;
800eeca4
JW		 5058 break;
5059
5060 case IA64_OPND_GR0:
5061 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
87f8eb97 5062 return OPERAND_MATCH;
800eeca4
JW		 5063 break;
5064
5065 case IA64_OPND_IP:
5066 if (e->X_op == O_register && e->X_add_number == REG_IP)
87f8eb97 5067 return OPERAND_MATCH;
800eeca4
JW		 5068 break;
5069
5070 case IA64_OPND_PR:
5071 if (e->X_op == O_register && e->X_add_number == REG_PR)
87f8eb97 5072 return OPERAND_MATCH;
800eeca4
JW		 5073 break;
5074
5075 case IA64_OPND_PR_ROT:
5076 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
87f8eb97 5077 return OPERAND_MATCH;
800eeca4
JW		 5078 break;
5079
5080 case IA64_OPND_PSR:
5081 if (e->X_op == O_register && e->X_add_number == REG_PSR)
87f8eb97 5082 return OPERAND_MATCH;
800eeca4
JW		 5083 break;
5084
5085 case IA64_OPND_PSR_L:
5086 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
87f8eb97 5087 return OPERAND_MATCH;
800eeca4
JW		 5088 break;
5089
5090 case IA64_OPND_PSR_UM:
5091 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
87f8eb97 5092 return OPERAND_MATCH;
800eeca4
JW		 5093 break;
5094
5095 case IA64_OPND_C1:
87f8eb97
JW		 5096 if (e->X_op == O_constant)
5097 {
5098 if (e->X_add_number == 1)
5099 return OPERAND_MATCH;
5100 else
5101 return OPERAND_OUT_OF_RANGE;
5102 }
800eeca4
JW		 5103 break;
5104
5105 case IA64_OPND_C8:
87f8eb97
JW		 5106 if (e->X_op == O_constant)
5107 {
5108 if (e->X_add_number == 8)
5109 return OPERAND_MATCH;
5110 else
5111 return OPERAND_OUT_OF_RANGE;
5112 }
800eeca4
JW		 5113 break;
5114
5115 case IA64_OPND_C16:
87f8eb97
JW		 5116 if (e->X_op == O_constant)
5117 {
5118 if (e->X_add_number == 16)
5119 return OPERAND_MATCH;
5120 else
5121 return OPERAND_OUT_OF_RANGE;
5122 }
800eeca4
JW		 5123 break;
5124
542d6675 5125 /* register operands: */
800eeca4
JW		 5126
5127 case IA64_OPND_AR3:
5128 if (e->X_op == O_register && e->X_add_number >= REG_AR
5129 && e->X_add_number < REG_AR + 128)
87f8eb97 5130 return OPERAND_MATCH;
800eeca4
JW		 5131 break;
5132
5133 case IA64_OPND_B1:
5134 case IA64_OPND_B2:
5135 if (e->X_op == O_register && e->X_add_number >= REG_BR
5136 && e->X_add_number < REG_BR + 8)
87f8eb97 5137 return OPERAND_MATCH;
800eeca4
JW		 5138 break;
5139
5140 case IA64_OPND_CR3:
5141 if (e->X_op == O_register && e->X_add_number >= REG_CR
5142 && e->X_add_number < REG_CR + 128)
87f8eb97 5143 return OPERAND_MATCH;
800eeca4
JW		 5144 break;
5145
5146 case IA64_OPND_F1:
5147 case IA64_OPND_F2:
5148 case IA64_OPND_F3:
5149 case IA64_OPND_F4:
5150 if (e->X_op == O_register && e->X_add_number >= REG_FR
5151 && e->X_add_number < REG_FR + 128)
87f8eb97 5152 return OPERAND_MATCH;
800eeca4
JW		 5153 break;
5154
5155 case IA64_OPND_P1:
5156 case IA64_OPND_P2:
5157 if (e->X_op == O_register && e->X_add_number >= REG_P
5158 && e->X_add_number < REG_P + 64)
87f8eb97 5159 return OPERAND_MATCH;
800eeca4
JW		 5160 break;
5161
5162 case IA64_OPND_R1:
5163 case IA64_OPND_R2:
5164 case IA64_OPND_R3:
5165 if (e->X_op == O_register && e->X_add_number >= REG_GR
5166 && e->X_add_number < REG_GR + 128)
87f8eb97 5167 return OPERAND_MATCH;
800eeca4
JW		 5168 break;
5169
5170 case IA64_OPND_R3_2:
87f8eb97 5171 if (e->X_op == O_register && e->X_add_number >= REG_GR)
40449e9f 5172 {
87f8eb97
JW		 5173 if (e->X_add_number < REG_GR + 4)
5174 return OPERAND_MATCH;
5175 else if (e->X_add_number < REG_GR + 128)
5176 return OPERAND_OUT_OF_RANGE;
5177 }
800eeca4
JW		 5178 break;
5179
542d6675 5180 /* indirect operands: */
800eeca4
JW		 5181 case IA64_OPND_CPUID_R3:
5182 case IA64_OPND_DBR_R3:
5183 case IA64_OPND_DTR_R3:
5184 case IA64_OPND_ITR_R3:
5185 case IA64_OPND_IBR_R3:
5186 case IA64_OPND_MSR_R3:
5187 case IA64_OPND_PKR_R3:
5188 case IA64_OPND_PMC_R3:
5189 case IA64_OPND_PMD_R3:
5190 case IA64_OPND_RR_R3:
5191 if (e->X_op == O_index && e->X_op_symbol
5192 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
5193 == opnd - IA64_OPND_CPUID_R3))
87f8eb97 5194 return OPERAND_MATCH;
800eeca4
JW		 5195 break;
5196
5197 case IA64_OPND_MR3:
5198 if (e->X_op == O_index && !e->X_op_symbol)
87f8eb97 5199 return OPERAND_MATCH;
800eeca4
JW		 5200 break;
5201
542d6675 5202 /* immediate operands: */
800eeca4
JW		 5203 case IA64_OPND_CNT2a:
5204 case IA64_OPND_LEN4:
5205 case IA64_OPND_LEN6:
5206 bits = operand_width (idesc->operands[index]);
87f8eb97
JW		 5207 if (e->X_op == O_constant)
5208 {
5209 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
5210 return OPERAND_MATCH;
5211 else
5212 return OPERAND_OUT_OF_RANGE;
5213 }
800eeca4
JW		 5214 break;
5215
5216 case IA64_OPND_CNT2b:
87f8eb97
JW		 5217 if (e->X_op == O_constant)
5218 {
5219 if ((bfd_vma) (e->X_add_number - 1) < 3)
5220 return OPERAND_MATCH;
5221 else
5222 return OPERAND_OUT_OF_RANGE;
5223 }
800eeca4
JW		 5224 break;
5225
5226 case IA64_OPND_CNT2c:
5227 val = e->X_add_number;
87f8eb97
JW		 5228 if (e->X_op == O_constant)
5229 {
5230 if ((val == 0 || val == 7 || val == 15 || val == 16))
5231 return OPERAND_MATCH;
5232 else
5233 return OPERAND_OUT_OF_RANGE;
5234 }
800eeca4
JW		 5235 break;
5236
5237 case IA64_OPND_SOR:
5238 /* SOR must be an integer multiple of 8 */
87f8eb97
JW		 5239 if (e->X_op == O_constant && e->X_add_number & 0x7)
5240 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5241 case IA64_OPND_SOF:
5242 case IA64_OPND_SOL:
87f8eb97
JW		 5243 if (e->X_op == O_constant)
5244 {
5245 if ((bfd_vma) e->X_add_number <= 96)
5246 return OPERAND_MATCH;
5247 else
5248 return OPERAND_OUT_OF_RANGE;
5249 }
800eeca4
JW		 5250 break;
5251
5252 case IA64_OPND_IMMU62:
5253 if (e->X_op == O_constant)
542d6675 5254 {
800eeca4 5255 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
87f8eb97
JW		 5256 return OPERAND_MATCH;
5257 else
5258 return OPERAND_OUT_OF_RANGE;
542d6675 5259 }
197865e8 5260 else
542d6675
KH		 5261 {
5262 /* FIXME -- need 62-bit relocation type */
5263 as_bad (_("62-bit relocation not yet implemented"));
5264 }
800eeca4
JW		 5265 break;
5266
5267 case IA64_OPND_IMMU64:
5268 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
5269 || e->X_op == O_subtract)
5270 {
5271 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5272 fix->code = BFD_RELOC_IA64_IMM64;
5273 if (e->X_op != O_subtract)
5274 {
5275 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5276 if (e->X_op == O_pseudo_fixup)
5277 e->X_op = O_symbol;
5278 }
5279
5280 fix->opnd = idesc->operands[index];
5281 fix->expr = *e;
5282 fix->is_pcrel = 0;
5283 ++CURR_SLOT.num_fixups;
87f8eb97 5284 return OPERAND_MATCH;
800eeca4
JW		 5285 }
5286 else if (e->X_op == O_constant)
87f8eb97 5287 return OPERAND_MATCH;
800eeca4
JW		 5288 break;
5289
5290 case IA64_OPND_CCNT5:
5291 case IA64_OPND_CNT5:
5292 case IA64_OPND_CNT6:
5293 case IA64_OPND_CPOS6a:
5294 case IA64_OPND_CPOS6b:
5295 case IA64_OPND_CPOS6c:
5296 case IA64_OPND_IMMU2:
5297 case IA64_OPND_IMMU7a:
5298 case IA64_OPND_IMMU7b:
800eeca4
JW		 5299 case IA64_OPND_IMMU21:
5300 case IA64_OPND_IMMU24:
5301 case IA64_OPND_MBTYPE4:
5302 case IA64_OPND_MHTYPE8:
5303 case IA64_OPND_POS6:
5304 bits = operand_width (idesc->operands[index]);
87f8eb97
JW		 5305 if (e->X_op == O_constant)
5306 {
5307 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5308 return OPERAND_MATCH;
5309 else
5310 return OPERAND_OUT_OF_RANGE;
5311 }
800eeca4
JW		 5312 break;
5313
bf3ca999
TW		 5314 case IA64_OPND_IMMU9:
5315 bits = operand_width (idesc->operands[index]);
87f8eb97 5316 if (e->X_op == O_constant)
542d6675 5317 {
87f8eb97
JW		 5318 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5319 {
5320 int lobits = e->X_add_number & 0x3;
5321 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
5322 e->X_add_number |= (bfd_vma) 0x3;
5323 return OPERAND_MATCH;
5324 }
5325 else
5326 return OPERAND_OUT_OF_RANGE;
542d6675 5327 }
bf3ca999
TW		 5328 break;
5329
800eeca4
JW		 5330 case IA64_OPND_IMM44:
5331 /* least 16 bits must be zero */
5332 if ((e->X_add_number & 0xffff) != 0)
87f8eb97
JW		 5333 /* XXX technically, this is wrong: we should not be issuing warning
5334 messages until we're sure this instruction pattern is going to
5335 be used! */
542d6675 5336 as_warn (_("lower 16 bits of mask ignored"));
800eeca4 5337
87f8eb97 5338 if (e->X_op == O_constant)
542d6675 5339 {
87f8eb97
JW		 5340 if (((e->X_add_number >= 0
5341 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44))
5342 || (e->X_add_number < 0
5343 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44))))
542d6675 5344 {
87f8eb97
JW		 5345 /* sign-extend */
5346 if (e->X_add_number >= 0
5347 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
5348 {
5349 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
5350 }
5351 return OPERAND_MATCH;
542d6675 5352 }
87f8eb97
JW		 5353 else
5354 return OPERAND_OUT_OF_RANGE;
542d6675 5355 }
800eeca4
JW		 5356 break;
5357
5358 case IA64_OPND_IMM17:
5359 /* bit 0 is a don't care (pr0 is hardwired to 1) */
87f8eb97 5360 if (e->X_op == O_constant)
542d6675 5361 {
87f8eb97
JW		 5362 if (((e->X_add_number >= 0
5363 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17))
5364 || (e->X_add_number < 0
5365 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17))))
542d6675 5366 {
87f8eb97
JW		 5367 /* sign-extend */
5368 if (e->X_add_number >= 0
5369 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
5370 {
5371 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
5372 }
5373 return OPERAND_MATCH;
542d6675 5374 }
87f8eb97
JW		 5375 else
5376 return OPERAND_OUT_OF_RANGE;
542d6675 5377 }
800eeca4
JW		 5378 break;
5379
5380 case IA64_OPND_IMM14:
5381 case IA64_OPND_IMM22:
5382 relocatable = 1;
5383 case IA64_OPND_IMM1:
5384 case IA64_OPND_IMM8:
5385 case IA64_OPND_IMM8U4:
5386 case IA64_OPND_IMM8M1:
5387 case IA64_OPND_IMM8M1U4:
5388 case IA64_OPND_IMM8M1U8:
5389 case IA64_OPND_IMM9a:
5390 case IA64_OPND_IMM9b:
5391 bits = operand_width (idesc->operands[index]);
5392 if (relocatable && (e->X_op == O_symbol
5393 || e->X_op == O_subtract
5394 || e->X_op == O_pseudo_fixup))
5395 {
5396 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5397
5398 if (idesc->operands[index] == IA64_OPND_IMM14)
5399 fix->code = BFD_RELOC_IA64_IMM14;
5400 else
5401 fix->code = BFD_RELOC_IA64_IMM22;
5402
5403 if (e->X_op != O_subtract)
5404 {
5405 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5406 if (e->X_op == O_pseudo_fixup)
5407 e->X_op = O_symbol;
5408 }
5409
5410 fix->opnd = idesc->operands[index];
5411 fix->expr = *e;
5412 fix->is_pcrel = 0;
5413 ++CURR_SLOT.num_fixups;
87f8eb97 5414 return OPERAND_MATCH;
800eeca4
JW		 5415 }
5416 else if (e->X_op != O_constant
5417 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
87f8eb97 5418 return OPERAND_MISMATCH;
800eeca4
JW		 5419
5420 if (opnd == IA64_OPND_IMM8M1U4)
5421 {
5422 /* Zero is not valid for unsigned compares that take an adjusted
5423 constant immediate range. */
5424 if (e->X_add_number == 0)
87f8eb97 5425 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5426
5427 /* Sign-extend 32-bit unsigned numbers, so that the following range
5428 checks will work. */
5429 val = e->X_add_number;
197865e8
KH		 5430 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5431 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 5432 val = ((val << 32) >> 32);
5433
5434 /* Check for 0x100000000. This is valid because
5435 0x100000000-1 is the same as ((uint32_t) -1). */
5436 if (val == ((bfd_signed_vma) 1 << 32))
87f8eb97 5437 return OPERAND_MATCH;
800eeca4
JW		 5438
5439 val = val - 1;
5440 }
5441 else if (opnd == IA64_OPND_IMM8M1U8)
5442 {
5443 /* Zero is not valid for unsigned compares that take an adjusted
5444 constant immediate range. */
5445 if (e->X_add_number == 0)
87f8eb97 5446 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5447
5448 /* Check for 0x10000000000000000. */
5449 if (e->X_op == O_big)
5450 {
5451 if (generic_bignum[0] == 0
5452 && generic_bignum[1] == 0
5453 && generic_bignum[2] == 0
5454 && generic_bignum[3] == 0
5455 && generic_bignum[4] == 1)
87f8eb97 5456 return OPERAND_MATCH;
800eeca4 5457 else
87f8eb97 5458 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5459 }
5460 else
5461 val = e->X_add_number - 1;
5462 }
5463 else if (opnd == IA64_OPND_IMM8M1)
5464 val = e->X_add_number - 1;
5465 else if (opnd == IA64_OPND_IMM8U4)
5466 {
5467 /* Sign-extend 32-bit unsigned numbers, so that the following range
5468 checks will work. */
5469 val = e->X_add_number;
197865e8
KH		 5470 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5471 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 5472 val = ((val << 32) >> 32);
5473 }
5474 else
5475 val = e->X_add_number;
5476
2434f565
JW		 5477 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1)))
5478 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1))))
87f8eb97
JW		 5479 return OPERAND_MATCH;
5480 else
5481 return OPERAND_OUT_OF_RANGE;
800eeca4
JW		 5482
5483 case IA64_OPND_INC3:
5484 /* +/- 1, 4, 8, 16 */
5485 val = e->X_add_number;
5486 if (val < 0)
5487 val = -val;
87f8eb97
JW		 5488 if (e->X_op == O_constant)
5489 {
5490 if ((val == 1 || val == 4 || val == 8 || val == 16))
5491 return OPERAND_MATCH;
5492 else
5493 return OPERAND_OUT_OF_RANGE;
5494 }
800eeca4
JW		 5495 break;
5496
5497 case IA64_OPND_TGT25:
5498 case IA64_OPND_TGT25b:
5499 case IA64_OPND_TGT25c:
5500 case IA64_OPND_TGT64:
5501 if (e->X_op == O_symbol)
5502 {
5503 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5504 if (opnd == IA64_OPND_TGT25)
5505 fix->code = BFD_RELOC_IA64_PCREL21F;
5506 else if (opnd == IA64_OPND_TGT25b)
5507 fix->code = BFD_RELOC_IA64_PCREL21M;
5508 else if (opnd == IA64_OPND_TGT25c)
5509 fix->code = BFD_RELOC_IA64_PCREL21B;
542d6675 5510 else if (opnd == IA64_OPND_TGT64)
c67e42c9
RH		 5511 fix->code = BFD_RELOC_IA64_PCREL60B;
5512 else
5513 abort ();
5514
800eeca4
JW		 5515 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5516 fix->opnd = idesc->operands[index];
5517 fix->expr = *e;
5518 fix->is_pcrel = 1;
5519 ++CURR_SLOT.num_fixups;
87f8eb97 5520 return OPERAND_MATCH;
800eeca4
JW		 5521 }
5522 case IA64_OPND_TAG13:
5523 case IA64_OPND_TAG13b:
5524 switch (e->X_op)
5525 {
5526 case O_constant:
87f8eb97 5527 return OPERAND_MATCH;
800eeca4
JW		 5528
5529 case O_symbol:
5530 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
fa1cb89c
JW		 5531 /* There are no external relocs for TAG13/TAG13b fields, so we
5532 create a dummy reloc. This will not live past md_apply_fix3. */
5533 fix->code = BFD_RELOC_UNUSED;
5534 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
800eeca4
JW		 5535 fix->opnd = idesc->operands[index];
5536 fix->expr = *e;
5537 fix->is_pcrel = 1;
5538 ++CURR_SLOT.num_fixups;
87f8eb97 5539 return OPERAND_MATCH;
800eeca4
JW		 5540
5541 default:
5542 break;
5543 }
5544 break;
5545
a823923b
RH		 5546 case IA64_OPND_LDXMOV:
5547 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5548 fix->code = BFD_RELOC_IA64_LDXMOV;
5549 fix->opnd = idesc->operands[index];
5550 fix->expr = *e;
5551 fix->is_pcrel = 0;
5552 ++CURR_SLOT.num_fixups;
5553 return OPERAND_MATCH;
5554
800eeca4
JW		 5555 default:
5556 break;
5557 }
87f8eb97 5558 return OPERAND_MISMATCH;
800eeca4
JW		 5559}
5560
5561static int
5562parse_operand (e)
5563 expressionS *e;
5564{
5565 int sep = '\0';
5566
5567 memset (e, 0, sizeof (*e));
5568 e->X_op = O_absent;
5569 SKIP_WHITESPACE ();
5570 if (*input_line_pointer != '}')
5571 expression (e);
5572 sep = *input_line_pointer++;
5573
5574 if (sep == '}')
5575 {
5576 if (!md.manual_bundling)
5577 as_warn ("Found '}' when manual bundling is off");
5578 else
5579 CURR_SLOT.manual_bundling_off = 1;
5580 md.manual_bundling = 0;
5581 sep = '\0';
5582 }
5583 return sep;
5584}
5585
5586/* Returns the next entry in the opcode table that matches the one in
5587 IDESC, and frees the entry in IDESC. If no matching entry is
197865e8 5588 found, NULL is returned instead. */
800eeca4
JW		 5589
5590static struct ia64_opcode *
5591get_next_opcode (struct ia64_opcode *idesc)
5592{
5593 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
5594 ia64_free_opcode (idesc);
5595 return next;
5596}
5597
5598/* Parse the operands for the opcode and find the opcode variant that
5599 matches the specified operands, or NULL if no match is possible. */
542d6675
KH		 5600
5601static struct ia64_opcode *
800eeca4
JW		 5602parse_operands (idesc)
5603 struct ia64_opcode *idesc;
5604{
5605 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
87f8eb97 5606 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0;
800eeca4 5607 enum ia64_opnd expected_operand = IA64_OPND_NIL;
87f8eb97 5608 enum operand_match_result result;
800eeca4
JW		 5609 char mnemonic[129];
5610 char *first_arg = 0, *end, *saved_input_pointer;
5611 unsigned int sof;
5612
5613 assert (strlen (idesc->name) <= 128);
5614
5615 strcpy (mnemonic, idesc->name);
5616 if (idesc->operands[2] == IA64_OPND_SOF)
5617 {
5618 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5619 can't parse the first operand until we have parsed the
5620 remaining operands of the "alloc" instruction. */
5621 SKIP_WHITESPACE ();
5622 first_arg = input_line_pointer;
5623 end = strchr (input_line_pointer, '=');
5624 if (!end)
5625 {
5626 as_bad ("Expected separator `='");
5627 return 0;
5628 }
5629 input_line_pointer = end + 1;
5630 ++i;
5631 ++num_outputs;
5632 }
5633
5634 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5635 {
5636 sep = parse_operand (CURR_SLOT.opnd + i);
5637 if (CURR_SLOT.opnd[i].X_op == O_absent)
5638 break;
5639
5640 ++num_operands;
5641
5642 if (sep != '=' && sep != ',')
5643 break;
5644
5645 if (sep == '=')
5646 {
5647 if (num_outputs > 0)
5648 as_bad ("Duplicate equal sign (=) in instruction");
5649 else
5650 num_outputs = i + 1;
5651 }
5652 }
5653 if (sep != '\0')
5654 {
5655 as_bad ("Illegal operand separator `%c'", sep);
5656 return 0;
5657 }
197865e8 5658
800eeca4
JW		 5659 if (idesc->operands[2] == IA64_OPND_SOF)
5660 {
5661 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5662 know (strcmp (idesc->name, "alloc") == 0);
5663 if (num_operands == 5 /* first_arg not included in this count! */
5664 && CURR_SLOT.opnd[2].X_op == O_constant
5665 && CURR_SLOT.opnd[3].X_op == O_constant
5666 && CURR_SLOT.opnd[4].X_op == O_constant
5667 && CURR_SLOT.opnd[5].X_op == O_constant)
5668 {
5669 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5670 CURR_SLOT.opnd[3].X_add_number,
5671 CURR_SLOT.opnd[4].X_add_number,
5672 CURR_SLOT.opnd[5].X_add_number);
5673
542d6675 5674 /* now we can parse the first arg: */
800eeca4
JW		 5675 saved_input_pointer = input_line_pointer;
5676 input_line_pointer = first_arg;
5677 sep = parse_operand (CURR_SLOT.opnd + 0);
5678 if (sep != '=')
5679 --num_outputs; /* force error */
5680 input_line_pointer = saved_input_pointer;
5681
5682 CURR_SLOT.opnd[2].X_add_number = sof;
5683 CURR_SLOT.opnd[3].X_add_number
5684 = sof - CURR_SLOT.opnd[4].X_add_number;
5685 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5686 }
5687 }
5688
5689 highest_unmatched_operand = 0;
87f8eb97
JW		 5690 curr_out_of_range_pos = -1;
5691 error_pos = 0;
800eeca4
JW		 5692 expected_operand = idesc->operands[0];
5693 for (; idesc; idesc = get_next_opcode (idesc))
5694 {
5695 if (num_outputs != idesc->num_outputs)
5696 continue; /* mismatch in # of outputs */
5697
5698 CURR_SLOT.num_fixups = 0;
87f8eb97
JW		 5699
5700 /* Try to match all operands. If we see an out-of-range operand,
5701 then continue trying to match the rest of the operands, since if
5702 the rest match, then this idesc will give the best error message. */
5703
5704 out_of_range_pos = -1;
800eeca4 5705 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
87f8eb97
JW		 5706 {
5707 result = operand_match (idesc, i, CURR_SLOT.opnd + i);
5708 if (result != OPERAND_MATCH)
5709 {
5710 if (result != OPERAND_OUT_OF_RANGE)
5711 break;
5712 if (out_of_range_pos < 0)
5713 /* remember position of the first out-of-range operand: */
5714 out_of_range_pos = i;
5715 }
5716 }
800eeca4 5717
87f8eb97
JW		 5718 /* If we did not match all operands, or if at least one operand was
5719 out-of-range, then this idesc does not match. Keep track of which
5720 idesc matched the most operands before failing. If we have two
5721 idescs that failed at the same position, and one had an out-of-range
5722 operand, then prefer the out-of-range operand. Thus if we have
5723 "add r0=0x1000000,r1" we get an error saying the constant is out
5724 of range instead of an error saying that the constant should have been
5725 a register. */
5726
5727 if (i != num_operands || out_of_range_pos >= 0)
800eeca4 5728 {
87f8eb97
JW		 5729 if (i > highest_unmatched_operand
5730 || (i == highest_unmatched_operand
5731 && out_of_range_pos > curr_out_of_range_pos))
800eeca4
JW		 5732 {
5733 highest_unmatched_operand = i;
87f8eb97
JW		 5734 if (out_of_range_pos >= 0)
5735 {
5736 expected_operand = idesc->operands[out_of_range_pos];
5737 error_pos = out_of_range_pos;
5738 }
5739 else
5740 {
5741 expected_operand = idesc->operands[i];
5742 error_pos = i;
5743 }
5744 curr_out_of_range_pos = out_of_range_pos;
800eeca4
JW		 5745 }
5746 continue;
5747 }
5748
5749 if (num_operands < NELEMS (idesc->operands)
5750 && idesc->operands[num_operands])
5751 continue; /* mismatch in number of arguments */
5752
5753 break;
5754 }
5755 if (!idesc)
5756 {
5757 if (expected_operand)
5758 as_bad ("Operand %u of `%s' should be %s",
87f8eb97 5759 error_pos + 1, mnemonic,
800eeca4
JW		 5760 elf64_ia64_operands[expected_operand].desc);
5761 else
5762 as_bad ("Operand mismatch");
5763 return 0;
5764 }
5765 return idesc;
5766}
5767
88be23ec
BS		 5768/* Keep track of state necessary to determine whether a NOP is necessary
5769 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5770 detect a case where additional NOPs may be necessary. */
5771static int
5772errata_nop_necessary_p (slot, insn_unit)
5773 struct slot *slot;
5774 enum ia64_unit insn_unit;
5775{
5776 int i;
5777 struct group *this_group = md.last_groups + md.group_idx;
5778 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
5779 struct ia64_opcode *idesc = slot->idesc;
5780
5781 /* Test whether this could be the first insn in a problematic sequence. */
5782 if (insn_unit == IA64_UNIT_F)
5783 {
5784 for (i = 0; i < idesc->num_outputs; i++)
5785 if (idesc->operands[i] == IA64_OPND_P1
5786 || idesc->operands[i] == IA64_OPND_P2)
5787 {
5788 int regno = slot->opnd[i].X_add_number - REG_P;
3557da92 5789 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5790 if (regno >= 64)
3557da92 5791 return 0;
88be23ec
BS		 5792 this_group->p_reg_set[regno] = 1;
5793 }
5794 }
5795
5796 /* Test whether this could be the second insn in a problematic sequence. */
5797 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
5798 && prev_group->p_reg_set[slot->qp_regno])
5799 {
5800 for (i = 0; i < idesc->num_outputs; i++)
5801 if (idesc->operands[i] == IA64_OPND_R1
5802 || idesc->operands[i] == IA64_OPND_R2
5803 || idesc->operands[i] == IA64_OPND_R3)
5804 {
5805 int regno = slot->opnd[i].X_add_number - REG_GR;
3557da92 5806 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5807 if (regno >= 128)
3557da92 5808 return 0;
88be23ec
BS		 5809 if (strncmp (idesc->name, "add", 3) != 0
5810 && strncmp (idesc->name, "sub", 3) != 0
5811 && strncmp (idesc->name, "shladd", 6) != 0
5812 && (idesc->flags & IA64_OPCODE_POSTINC) == 0)
5813 this_group->g_reg_set_conditionally[regno] = 1;
5814 }
5815 }
5816
5817 /* Test whether this could be the third insn in a problematic sequence. */
5818 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
5819 {
5820 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5821 idesc->operands[i] == IA64_OPND_R3
5822 /* For mov indirect. */
5823 || idesc->operands[i] == IA64_OPND_RR_R3
5824 || idesc->operands[i] == IA64_OPND_DBR_R3
5825 || idesc->operands[i] == IA64_OPND_IBR_R3
5826 || idesc->operands[i] == IA64_OPND_PKR_R3
5827 || idesc->operands[i] == IA64_OPND_PMC_R3
5828 || idesc->operands[i] == IA64_OPND_PMD_R3
5829 || idesc->operands[i] == IA64_OPND_MSR_R3
5830 || idesc->operands[i] == IA64_OPND_CPUID_R3
5831 /* For itr. */
5832 || idesc->operands[i] == IA64_OPND_ITR_R3
5833 || idesc->operands[i] == IA64_OPND_DTR_R3
5834 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5835 || idesc->operands[i] == IA64_OPND_MR3)
5836 {
5837 int regno = slot->opnd[i].X_add_number - REG_GR;
3557da92 5838 /* Ignore invalid operands; they generate errors elsewhere. */
ca683b78 5839 if (regno >= 128)
3557da92 5840 return 0;
88be23ec
BS		 5841 if (idesc->operands[i] == IA64_OPND_R3)
5842 {
5843 if (strcmp (idesc->name, "fc") != 0
5844 && strcmp (idesc->name, "tak") != 0
5845 && strcmp (idesc->name, "thash") != 0
5846 && strcmp (idesc->name, "tpa") != 0
5847 && strcmp (idesc->name, "ttag") != 0
5848 && strncmp (idesc->name, "ptr", 3) != 0
5849 && strncmp (idesc->name, "ptc", 3) != 0
5850 && strncmp (idesc->name, "probe", 5) != 0)
40449e9f 5851 return 0;
88be23ec 5852 }
bc805888 5853 if (prev_group->g_reg_set_conditionally[regno])
88be23ec
BS		 5854 return 1;
5855 }
5856 }
5857 return 0;
5858}
5859
800eeca4
JW		 5860static void
5861build_insn (slot, insnp)
5862 struct slot *slot;
5863 bfd_vma *insnp;
5864{
5865 const struct ia64_operand *odesc, *o2desc;
5866 struct ia64_opcode *idesc = slot->idesc;
5867 bfd_signed_vma insn, val;
5868 const char *err;
5869 int i;
5870
5871 insn = idesc->opcode | slot->qp_regno;
5872
5873 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5874 {
c67e42c9
RH		 5875 if (slot->opnd[i].X_op == O_register
5876 || slot->opnd[i].X_op == O_constant
5877 || slot->opnd[i].X_op == O_index)
5878 val = slot->opnd[i].X_add_number;
5879 else if (slot->opnd[i].X_op == O_big)
800eeca4 5880 {
c67e42c9
RH		 5881 /* This must be the value 0x10000000000000000. */
5882 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5883 val = 0;
5884 }
5885 else
5886 val = 0;
5887
5888 switch (idesc->operands[i])
5889 {
5890 case IA64_OPND_IMMU64:
800eeca4
JW		 5891 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5892 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5893 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5894 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH		 5895 continue;
5896
5897 case IA64_OPND_IMMU62:
542d6675
KH		 5898 val &= 0x3fffffffffffffffULL;
5899 if (val != slot->opnd[i].X_add_number)
5900 as_warn (_("Value truncated to 62 bits"));
5901 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5902 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 5903 continue;
800eeca4 5904
c67e42c9
RH		 5905 case IA64_OPND_TGT64:
5906 val >>= 4;
5907 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5908 insn |= ((((val >> 59) & 0x1) << 36)
5909 | (((val >> 0) & 0xfffff) << 13));
5910 continue;
800eeca4 5911
c67e42c9
RH		 5912 case IA64_OPND_AR3:
5913 val -= REG_AR;
5914 break;
5915
5916 case IA64_OPND_B1:
5917 case IA64_OPND_B2:
5918 val -= REG_BR;
5919 break;
5920
5921 case IA64_OPND_CR3:
5922 val -= REG_CR;
5923 break;
5924
5925 case IA64_OPND_F1:
5926 case IA64_OPND_F2:
5927 case IA64_OPND_F3:
5928 case IA64_OPND_F4:
5929 val -= REG_FR;
5930 break;
5931
5932 case IA64_OPND_P1:
5933 case IA64_OPND_P2:
5934 val -= REG_P;
5935 break;
5936
5937 case IA64_OPND_R1:
5938 case IA64_OPND_R2:
5939 case IA64_OPND_R3:
5940 case IA64_OPND_R3_2:
5941 case IA64_OPND_CPUID_R3:
5942 case IA64_OPND_DBR_R3:
5943 case IA64_OPND_DTR_R3:
5944 case IA64_OPND_ITR_R3:
5945 case IA64_OPND_IBR_R3:
5946 case IA64_OPND_MR3:
5947 case IA64_OPND_MSR_R3:
5948 case IA64_OPND_PKR_R3:
5949 case IA64_OPND_PMC_R3:
5950 case IA64_OPND_PMD_R3:
197865e8 5951 case IA64_OPND_RR_R3:
c67e42c9
RH		 5952 val -= REG_GR;
5953 break;
5954
5955 default:
5956 break;
5957 }
5958
5959 odesc = elf64_ia64_operands + idesc->operands[i];
5960 err = (*odesc->insert) (odesc, val, &insn);
5961 if (err)
5962 as_bad_where (slot->src_file, slot->src_line,
5963 "Bad operand value: %s", err);
5964 if (idesc->flags & IA64_OPCODE_PSEUDO)
5965 {
5966 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5967 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5968 {
5969 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5970 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5971 }
c67e42c9
RH		 5972 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5973 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5974 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5975 {
c67e42c9
RH		 5976 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5977 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW		 5978 }
5979 }
5980 }
5981 *insnp = insn;
5982}
5983
5984static void
5985emit_one_bundle ()
5986{
5987 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5988 unsigned int manual_bundling = 0;
5989 enum ia64_unit required_unit, insn_unit = 0;
5990 enum ia64_insn_type type[3], insn_type;
5991 unsigned int template, orig_template;
542d6675 5992 bfd_vma insn[3] = { -1, -1, -1 };
800eeca4
JW		 5993 struct ia64_opcode *idesc;
5994 int end_of_insn_group = 0, user_template = -1;
5995 int n, i, j, first, curr;
2434f565 5996 unw_rec_list *ptr;
800eeca4
JW		 5997 bfd_vma t0 = 0, t1 = 0;
5998 struct label_fix *lfix;
5999 struct insn_fix *ifix;
6000 char mnemonic[16];
6001 fixS *fix;
6002 char *f;
6003
6004 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
6005 know (first >= 0 & first < NUM_SLOTS);
6006 n = MIN (3, md.num_slots_in_use);
6007
6008 /* Determine template: user user_template if specified, best match
542d6675 6009 otherwise: */
800eeca4
JW		 6010
6011 if (md.slot[first].user_template >= 0)
6012 user_template = template = md.slot[first].user_template;
6013 else
6014 {
032efc85 6015 /* Auto select appropriate template. */
800eeca4
JW		 6016 memset (type, 0, sizeof (type));
6017 curr = first;
6018 for (i = 0; i < n; ++i)
6019 {
032efc85
RH		 6020 if (md.slot[curr].label_fixups && i != 0)
6021 break;
800eeca4
JW		 6022 type[i] = md.slot[curr].idesc->type;
6023 curr = (curr + 1) % NUM_SLOTS;
6024 }
6025 template = best_template[type[0]][type[1]][type[2]];
6026 }
6027
542d6675 6028 /* initialize instructions with appropriate nops: */
800eeca4
JW		 6029 for (i = 0; i < 3; ++i)
6030 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
6031
6032 f = frag_more (16);
6033
542d6675 6034 /* now fill in slots with as many insns as possible: */
800eeca4
JW		 6035 curr = first;
6036 idesc = md.slot[curr].idesc;
6037 end_of_insn_group = 0;
6038 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
6039 {
e0c9811a
JW		 6040 /* Set the slot number for prologue/body records now as those
6041 refer to the current point, not the point after the
542d6675 6042 instruction has been issued: */
10850f29
JW		 6043 /* Don't try to delete prologue/body records here, as that will cause
6044 them to also be deleted from the master list of unwind records. */
e0c9811a 6045 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
10850f29
JW		 6046 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
6047 || ptr->r.type == body)
f5a30c2e
JW		 6048 {
6049 ptr->slot_number = (unsigned long) f + i;
6050 ptr->slot_frag = frag_now;
6051 }
e0c9811a 6052
800eeca4
JW		 6053 if (idesc->flags & IA64_OPCODE_SLOT2)
6054 {
6055 if (manual_bundling && i != 2)
6056 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6057 "`%s' must be last in bundle", idesc->name);
6058 else
6059 i = 2;
6060 }
6061 if (idesc->flags & IA64_OPCODE_LAST)
6062 {
2434f565
JW		 6063 int required_slot;
6064 unsigned int required_template;
800eeca4
JW		 6065
6066 /* If we need a stop bit after an M slot, our only choice is
6067 template 5 (M;;MI). If we need a stop bit after a B
6068 slot, our only choice is to place it at the end of the
6069 bundle, because the only available templates are MIB,
6070 MBB, BBB, MMB, and MFB. We don't handle anything other
6071 than M and B slots because these are the only kind of
6072 instructions that can have the IA64_OPCODE_LAST bit set. */
6073 required_template = template;
6074 switch (idesc->type)
6075 {
6076 case IA64_TYPE_M:
6077 required_slot = 0;
6078 required_template = 5;
6079 break;
6080
6081 case IA64_TYPE_B:
6082 required_slot = 2;
6083 break;
6084
6085 default:
6086 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6087 "Internal error: don't know how to force %s to end"
6088 "of instruction group", idesc->name);
6089 required_slot = i;
6090 break;
6091 }
6092 if (manual_bundling && i != required_slot)
6093 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6094 "`%s' must be last in instruction group",
6095 idesc->name);
6096 if (required_slot < i)
6097 /* Can't fit this instruction. */
6098 break;
6099
6100 i = required_slot;
6101 if (required_template != template)
6102 {
6103 /* If we switch the template, we need to reset the NOPs
6104 after slot i. The slot-types of the instructions ahead
6105 of i never change, so we don't need to worry about
6106 changing NOPs in front of this slot. */
6107 for (j = i; j < 3; ++j)
6108 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
6109 }
6110 template = required_template;
6111 }
6112 if (curr != first && md.slot[curr].label_fixups)
6113 {
6114 if (manual_bundling_on)
6115 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6116 "Label must be first in a bundle");
6117 /* This insn must go into the first slot of a bundle. */
6118 break;
6119 }
6120
6121 manual_bundling_on = md.slot[curr].manual_bundling_on;
6122 manual_bundling_off = md.slot[curr].manual_bundling_off;
6123
6124 if (manual_bundling_on)
6125 {
6126 if (curr == first)
6127 manual_bundling = 1;
6128 else
6129 break; /* need to start a new bundle */
6130 }
6131
6132 if (end_of_insn_group && md.num_slots_in_use >= 1)
6133 {
6134 /* We need an instruction group boundary in the middle of a
6135 bundle. See if we can switch to an other template with
6136 an appropriate boundary. */
6137
6138 orig_template = template;
6139 if (i == 1 && (user_template == 4
6140 || (user_template < 0
6141 && (ia64_templ_desc[template].exec_unit[0]
6142 == IA64_UNIT_M))))
6143 {
6144 template = 5;
6145 end_of_insn_group = 0;
6146 }
6147 else if (i == 2 && (user_template == 0
6148 || (user_template < 0
6149 && (ia64_templ_desc[template].exec_unit[1]
6150 == IA64_UNIT_I)))
6151 /* This test makes sure we don't switch the template if
6152 the next instruction is one that needs to be first in
6153 an instruction group. Since all those instructions are
6154 in the M group, there is no way such an instruction can
6155 fit in this bundle even if we switch the template. The
6156 reason we have to check for this is that otherwise we
6157 may end up generating "MI;;I M.." which has the deadly
6158 effect that the second M instruction is no longer the
6159 first in the bundle! --davidm 99/12/16 */
6160 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
6161 {
6162 template = 1;
6163 end_of_insn_group = 0;
6164 }
6165 else if (curr != first)
6166 /* can't fit this insn */
6167 break;
6168
6169 if (template != orig_template)
6170 /* if we switch the template, we need to reset the NOPs
6171 after slot i. The slot-types of the instructions ahead
6172 of i never change, so we don't need to worry about
6173 changing NOPs in front of this slot. */
6174 for (j = i; j < 3; ++j)
6175 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
6176 }
6177 required_unit = ia64_templ_desc[template].exec_unit[i];
6178
c10d9d8f 6179 /* resolve dynamic opcodes such as "break", "hint", and "nop": */
800eeca4
JW		 6180 if (idesc->type == IA64_TYPE_DYN)
6181 {
6182 if ((strcmp (idesc->name, "nop") == 0)
c10d9d8f 6183 || (strcmp (idesc->name, "hint") == 0)
800eeca4
JW		 6184 || (strcmp (idesc->name, "break") == 0))
6185 insn_unit = required_unit;
6186 else if (strcmp (idesc->name, "chk.s") == 0)
6187 {
6188 insn_unit = IA64_UNIT_M;
6189 if (required_unit == IA64_UNIT_I)
6190 insn_unit = IA64_UNIT_I;
6191 }
6192 else
6193 as_fatal ("emit_one_bundle: unexpected dynamic op");
6194
6195 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
3d56ab85 6196 ia64_free_opcode (idesc);
800eeca4
JW		 6197 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
6198#if 0
6199 know (!idesc->next); /* no resolved dynamic ops have collisions */
6200#endif
6201 }
6202 else
6203 {
6204 insn_type = idesc->type;
6205 insn_unit = IA64_UNIT_NIL;
6206 switch (insn_type)
6207 {
6208 case IA64_TYPE_A:
6209 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
6210 insn_unit = required_unit;
6211 break;
542d6675 6212 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
800eeca4
JW		 6213 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
6214 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
6215 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
6216 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
6217 default: break;
6218 }
6219 }
6220
6221 if (insn_unit != required_unit)
6222 {
6223 if (required_unit == IA64_UNIT_L
542d6675 6224 && insn_unit == IA64_UNIT_I
800eeca4
JW		 6225 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
6226 {
6227 /* we got ourselves an MLX template but the current
197865e8 6228 instruction isn't an X-unit, or an I-unit instruction
800eeca4
JW		 6229 that can go into the X slot of an MLX template. Duh. */
6230 if (md.num_slots_in_use >= NUM_SLOTS)
6231 {
6232 as_bad_where (md.slot[curr].src_file,
6233 md.slot[curr].src_line,
6234 "`%s' can't go in X slot of "
6235 "MLX template", idesc->name);
542d6675 6236 /* drop this insn so we don't livelock: */
800eeca4
JW		 6237 --md.num_slots_in_use;
6238 }
6239 break;
6240 }
6241 continue; /* try next slot */
6242 }
6243
40449e9f
KH		 6244 {
6245 bfd_vma addr;
800eeca4 6246
40449e9f
KH		 6247 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
6248 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
6249 }
800eeca4 6250
88be23ec
BS		 6251 if (errata_nop_necessary_p (md.slot + curr, insn_unit))
6252 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6253
800eeca4
JW		 6254 build_insn (md.slot + curr, insn + i);
6255
10850f29
JW		 6256 /* Set slot counts for non prologue/body unwind records. */
6257 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
6258 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
6259 && ptr->r.type != body)
f5a30c2e
JW		 6260 {
6261 ptr->slot_number = (unsigned long) f + i;
6262 ptr->slot_frag = frag_now;
6263 }
10850f29 6264 md.slot[curr].unwind_record = NULL;
10850f29 6265
800eeca4
JW		 6266 if (required_unit == IA64_UNIT_L)
6267 {
6268 know (i == 1);
6269 /* skip one slot for long/X-unit instructions */
6270 ++i;
6271 }
6272 --md.num_slots_in_use;
6273
542d6675 6274 /* now is a good time to fix up the labels for this insn: */
800eeca4
JW		 6275 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
6276 {
6277 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
6278 symbol_set_frag (lfix->sym, frag_now);
6279 }
f1bcba5b
JW		 6280 /* and fix up the tags also. */
6281 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
6282 {
6283 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
6284 symbol_set_frag (lfix->sym, frag_now);
6285 }
800eeca4
JW		 6286
6287 for (j = 0; j < md.slot[curr].num_fixups; ++j)
6288 {
6289 ifix = md.slot[curr].fixup + j;
5a080f89 6290 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
800eeca4
JW		 6291 &ifix->expr, ifix->is_pcrel, ifix->code);
6292 fix->tc_fix_data.opnd = ifix->opnd;
6293 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
6294 fix->fx_file = md.slot[curr].src_file;
6295 fix->fx_line = md.slot[curr].src_line;
6296 }
6297
6298 end_of_insn_group = md.slot[curr].end_of_insn_group;
6299
88be23ec
BS		 6300 if (end_of_insn_group)
6301 {
6302 md.group_idx = (md.group_idx + 1) % 3;
6303 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
6304 }
6305
542d6675 6306 /* clear slot: */
800eeca4
JW		 6307 ia64_free_opcode (md.slot[curr].idesc);
6308 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
6309 md.slot[curr].user_template = -1;
6310
6311 if (manual_bundling_off)
6312 {
6313 manual_bundling = 0;
6314 break;
6315 }
6316 curr = (curr + 1) % NUM_SLOTS;
6317 idesc = md.slot[curr].idesc;
6318 }
6319 if (manual_bundling)
6320 {
6321 if (md.num_slots_in_use > 0)
6322 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6323 "`%s' does not fit into %s template",
6324 idesc->name, ia64_templ_desc[template].name);
6325 else
6326 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6327 "Missing '}' at end of file");
6328 }
6329 know (md.num_slots_in_use < NUM_SLOTS);
6330
6331 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
6332 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
6333
44f5c83a
JW		 6334 number_to_chars_littleendian (f + 0, t0, 8);
6335 number_to_chars_littleendian (f + 8, t1, 8);
f5a30c2e
JW		 6336
6337 unwind.next_slot_number = (unsigned long) f + 16;
6338 unwind.next_slot_frag = frag_now;
800eeca4
JW		 6339}
6340
6341int
6342md_parse_option (c, arg)
6343 int c;
6344 char *arg;
6345{
7463c317 6346
800eeca4
JW		 6347 switch (c)
6348 {
c43c2cc5 6349 /* Switches from the Intel assembler. */
44f5c83a 6350 case 'm':
800eeca4
JW		 6351 if (strcmp (arg, "ilp64") == 0
6352 || strcmp (arg, "lp64") == 0
6353 || strcmp (arg, "p64") == 0)
6354 {
6355 md.flags |= EF_IA_64_ABI64;
6356 }
6357 else if (strcmp (arg, "ilp32") == 0)
6358 {
6359 md.flags &= ~EF_IA_64_ABI64;
6360 }
6361 else if (strcmp (arg, "le") == 0)
6362 {
6363 md.flags &= ~EF_IA_64_BE;
6364 }
6365 else if (strcmp (arg, "be") == 0)
6366 {
6367 md.flags |= EF_IA_64_BE;
6368 }
6369 else
6370 return 0;
6371 break;
6372
6373 case 'N':
6374 if (strcmp (arg, "so") == 0)
6375 {
542d6675 6376 /* Suppress signon message. */
800eeca4
JW		 6377 }
6378 else if (strcmp (arg, "pi") == 0)
6379 {
6380 /* Reject privileged instructions. FIXME */
6381 }
6382 else if (strcmp (arg, "us") == 0)
6383 {
6384 /* Allow union of signed and unsigned range. FIXME */
6385 }
6386 else if (strcmp (arg, "close_fcalls") == 0)
6387 {
6388 /* Do not resolve global function calls. */
6389 }
6390 else
6391 return 0;
6392 break;
6393
6394 case 'C':
6395 /* temp[="prefix"] Insert temporary labels into the object file
6396 symbol table prefixed by "prefix".
6397 Default prefix is ":temp:".
6398 */
6399 break;
6400
6401 case 'a':
800eeca4
JW		 6402 /* indirect=<tgt> Assume unannotated indirect branches behavior
6403 according to <tgt> --
6404 exit: branch out from the current context (default)
6405 labels: all labels in context may be branch targets
6406 */
85b40035
L		 6407 if (strncmp (arg, "indirect=", 9) != 0)
6408 return 0;
800eeca4
JW		 6409 break;
6410
6411 case 'x':
6412 /* -X conflicts with an ignored option, use -x instead */
6413 md.detect_dv = 1;
6414 if (!arg || strcmp (arg, "explicit") == 0)
542d6675
KH		 6415 {
6416 /* set default mode to explicit */
6417 md.default_explicit_mode = 1;
6418 break;
6419 }
800eeca4 6420 else if (strcmp (arg, "auto") == 0)
542d6675
KH		 6421 {
6422 md.default_explicit_mode = 0;
6423 }
800eeca4 6424 else if (strcmp (arg, "debug") == 0)
542d6675
KH		 6425 {
6426 md.debug_dv = 1;
6427 }
800eeca4 6428 else if (strcmp (arg, "debugx") == 0)
542d6675
KH		 6429 {
6430 md.default_explicit_mode = 1;
6431 md.debug_dv = 1;
6432 }
800eeca4 6433 else
542d6675
KH		 6434 {
6435 as_bad (_("Unrecognized option '-x%s'"), arg);
6436 }
800eeca4
JW		 6437 break;
6438
6439 case 'S':
6440 /* nops Print nops statistics. */
6441 break;
6442
c43c2cc5
JW		 6443 /* GNU specific switches for gcc. */
6444 case OPTION_MCONSTANT_GP:
6445 md.flags |= EF_IA_64_CONS_GP;
6446 break;
6447
6448 case OPTION_MAUTO_PIC:
6449 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
6450 break;
6451
800eeca4
JW		 6452 default:
6453 return 0;
6454 }
6455
6456 return 1;
6457}
6458
6459void
6460md_show_usage (stream)
6461 FILE *stream;
6462{
542d6675 6463 fputs (_("\
800eeca4 6464IA-64 options:\n\
6290819d
NC		 6465 --mconstant-gp mark output file as using the constant-GP model\n\
6466 (sets ELF header flag EF_IA_64_CONS_GP)\n\
6467 --mauto-pic mark output file as using the constant-GP model\n\
6468 without function descriptors (sets ELF header flag\n\
6469 EF_IA_64_NOFUNCDESC_CONS_GP)\n\
44f5c83a
JW		 6470 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6471 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
800eeca4
JW		 6472 -x | -xexplicit turn on dependency violation checking (default)\n\
6473 -xauto automagically remove dependency violations\n\
6474 -xdebug debug dependency violation checker\n"),
6475 stream);
6476}
6477
acebd4ce
AS		 6478void
6479ia64_after_parse_args ()
6480{
6481 if (debug_type == DEBUG_STABS)
6482 as_fatal (_("--gstabs is not supported for ia64"));
6483}
6484
44576e1f
RH		 6485/* Return true if TYPE fits in TEMPL at SLOT. */
6486
6487static int
800eeca4
JW		 6488match (int templ, int type, int slot)
6489{
6490 enum ia64_unit unit;
6491 int result;
6492
6493 unit = ia64_templ_desc[templ].exec_unit[slot];
6494 switch (type)
6495 {
6496 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
6497 case IA64_TYPE_A:
6498 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
6499 break;
6500 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
6501 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
6502 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
6503 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
6504 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
6505 default: result = 0; break;
6506 }
6507 return result;
6508}
6509
44576e1f
RH		 6510/* Add a bit of extra goodness if a nop of type F or B would fit
6511 in TEMPL at SLOT. */
6512
6513static inline int
6514extra_goodness (int templ, int slot)
6515{
ebeeafe6 6516 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
44576e1f 6517 return 2;
ebeeafe6 6518 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
44576e1f
RH		 6519 return 1;
6520 return 0;
6521}
6522
800eeca4
JW		 6523/* This function is called once, at assembler startup time. It sets
6524 up all the tables, etc. that the MD part of the assembler will need
6525 that can be determined before arguments are parsed. */
6526void
6527md_begin ()
6528{
44f5c83a 6529 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
800eeca4
JW		 6530 const char *err;
6531 char name[8];
6532
6533 md.auto_align = 1;
6534 md.explicit_mode = md.default_explicit_mode;
6535
6536 bfd_set_section_alignment (stdoutput, text_section, 4);
6537
44f5c83a 6538 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
13ae64f3
JJ		 6539 pseudo_func[FUNC_DTP_MODULE].u.sym =
6540 symbol_new (".<dtpmod>", undefined_section, FUNC_DTP_MODULE,
6541 &zero_address_frag);
6542
6543 pseudo_func[FUNC_DTP_RELATIVE].u.sym =
6544 symbol_new (".<dtprel>", undefined_section, FUNC_DTP_RELATIVE,
6545 &zero_address_frag);
6546
800eeca4 6547 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
542d6675
KH		 6548 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
6549 &zero_address_frag);
800eeca4
JW		 6550
6551 pseudo_func[FUNC_GP_RELATIVE].u.sym =
542d6675
KH		 6552 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
6553 &zero_address_frag);
800eeca4
JW		 6554
6555 pseudo_func[FUNC_LT_RELATIVE].u.sym =
542d6675
KH		 6556 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
6557 &zero_address_frag);
800eeca4 6558
fa2c7eff
RH		 6559 pseudo_func[FUNC_LT_RELATIVE_X].u.sym =
6560 symbol_new (".<ltoffx>", undefined_section, FUNC_LT_RELATIVE_X,
6561 &zero_address_frag);
6562
c67e42c9 6563 pseudo_func[FUNC_PC_RELATIVE].u.sym =
542d6675
KH		 6564 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
6565 &zero_address_frag);
c67e42c9 6566
800eeca4 6567 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
542d6675
KH		 6568 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
6569 &zero_address_frag);
800eeca4
JW		 6570
6571 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
542d6675
KH		 6572 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
6573 &zero_address_frag);
800eeca4
JW		 6574
6575 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
542d6675
KH		 6576 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
6577 &zero_address_frag);
800eeca4 6578
13ae64f3
JJ		 6579 pseudo_func[FUNC_TP_RELATIVE].u.sym =
6580 symbol_new (".<tprel>", undefined_section, FUNC_TP_RELATIVE,
6581 &zero_address_frag);
6582
800eeca4 6583 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
542d6675
KH		 6584 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
6585 &zero_address_frag);
800eeca4
JW		 6586
6587 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
542d6675
KH		 6588 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
6589 &zero_address_frag);
800eeca4 6590
13ae64f3
JJ		 6591 pseudo_func[FUNC_LT_DTP_MODULE].u.sym =
6592 symbol_new (".<ltoff.dtpmod>", undefined_section, FUNC_LT_DTP_MODULE,
6593 &zero_address_frag);
6594
6595 pseudo_func[FUNC_LT_DTP_RELATIVE].u.sym =
6596 symbol_new (".<ltoff.dptrel>", undefined_section, FUNC_LT_DTP_RELATIVE,
6597 &zero_address_frag);
6598
6599 pseudo_func[FUNC_LT_TP_RELATIVE].u.sym =
6600 symbol_new (".<ltoff.tprel>", undefined_section, FUNC_LT_TP_RELATIVE,
6601 &zero_address_frag);
6602
3969b680
RH		 6603 pseudo_func[FUNC_IPLT_RELOC].u.sym =
6604 symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC,
6605 &zero_address_frag);
6606
197865e8 6607 /* Compute the table of best templates. We compute goodness as a
44576e1f
RH		 6608 base 4 value, in which each match counts for 3, each F counts
6609 for 2, each B counts for 1. This should maximize the number of
6610 F and B nops in the chosen bundles, which is good because these
6611 pipelines are least likely to be overcommitted. */
800eeca4
JW		 6612 for (i = 0; i < IA64_NUM_TYPES; ++i)
6613 for (j = 0; j < IA64_NUM_TYPES; ++j)
6614 for (k = 0; k < IA64_NUM_TYPES; ++k)
6615 {
6616 best = 0;
6617 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
6618 {
6619 goodness = 0;
6620 if (match (t, i, 0))
6621 {
6622 if (match (t, j, 1))
6623 {
6624 if (match (t, k, 2))
44576e1f 6625 goodness = 3 + 3 + 3;
800eeca4 6626 else
44576e1f 6627 goodness = 3 + 3 + extra_goodness (t, 2);
800eeca4
JW		 6628 }
6629 else if (match (t, j, 2))
44576e1f 6630 goodness = 3 + 3 + extra_goodness (t, 1);
800eeca4 6631 else
44576e1f
RH		 6632 {
6633 goodness = 3;
6634 goodness += extra_goodness (t, 1);
6635 goodness += extra_goodness (t, 2);
6636 }
800eeca4
JW		 6637 }
6638 else if (match (t, i, 1))
6639 {
6640 if (match (t, j, 2))
44576e1f 6641 goodness = 3 + 3;
800eeca4 6642 else
44576e1f 6643 goodness = 3 + extra_goodness (t, 2);
800eeca4
JW		 6644 }
6645 else if (match (t, i, 2))
44576e1f 6646 goodness = 3 + extra_goodness (t, 1);
800eeca4
JW		 6647
6648 if (goodness > best)
6649 {
6650 best = goodness;
6651 best_template[i][j][k] = t;
6652 }
6653 }
6654 }
6655
6656 for (i = 0; i < NUM_SLOTS; ++i)
6657 md.slot[i].user_template = -1;
6658
6659 md.pseudo_hash = hash_new ();
6660 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
6661 {
6662 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
6663 (void *) (pseudo_opcode + i));
6664 if (err)
6665 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6666 pseudo_opcode[i].name, err);
6667 }
6668
6669 md.reg_hash = hash_new ();
6670 md.dynreg_hash = hash_new ();
6671 md.const_hash = hash_new ();
6672 md.entry_hash = hash_new ();
6673
542d6675 6674 /* general registers: */
800eeca4
JW		 6675
6676 total = 128;
6677 for (i = 0; i < total; ++i)
6678 {
6679 sprintf (name, "r%d", i - REG_GR);
6680 md.regsym[i] = declare_register (name, i);
6681 }
6682
542d6675 6683 /* floating point registers: */
800eeca4
JW		 6684 total += 128;
6685 for (; i < total; ++i)
6686 {
6687 sprintf (name, "f%d", i - REG_FR);
6688 md.regsym[i] = declare_register (name, i);
6689 }
6690
542d6675 6691 /* application registers: */
800eeca4
JW		 6692 total += 128;
6693 ar_base = i;
6694 for (; i < total; ++i)
6695 {
6696 sprintf (name, "ar%d", i - REG_AR);
6697 md.regsym[i] = declare_register (name, i);
6698 }
6699
542d6675 6700 /* control registers: */
800eeca4
JW		 6701 total += 128;
6702 cr_base = i;
6703 for (; i < total; ++i)
6704 {
6705 sprintf (name, "cr%d", i - REG_CR);
6706 md.regsym[i] = declare_register (name, i);
6707 }
6708
542d6675 6709 /* predicate registers: */
800eeca4
JW		 6710 total += 64;
6711 for (; i < total; ++i)
6712 {
6713 sprintf (name, "p%d", i - REG_P);
6714 md.regsym[i] = declare_register (name, i);
6715 }
6716
542d6675 6717 /* branch registers: */
800eeca4
JW		 6718 total += 8;
6719 for (; i < total; ++i)
6720 {
6721 sprintf (name, "b%d", i - REG_BR);
6722 md.regsym[i] = declare_register (name, i);
6723 }
6724
6725 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
6726 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
6727 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
6728 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
6729 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
6730 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
6731 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
6732
6733 for (i = 0; i < NELEMS (indirect_reg); ++i)
6734 {
6735 regnum = indirect_reg[i].regnum;
6736 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
6737 }
6738
542d6675 6739 /* define synonyms for application registers: */
800eeca4
JW		 6740 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
6741 md.regsym[i] = declare_register (ar[i - REG_AR].name,
6742 REG_AR + ar[i - REG_AR].regnum);
6743
542d6675 6744 /* define synonyms for control registers: */
800eeca4
JW		 6745 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
6746 md.regsym[i] = declare_register (cr[i - REG_CR].name,
6747 REG_CR + cr[i - REG_CR].regnum);
6748
6749 declare_register ("gp", REG_GR + 1);
6750 declare_register ("sp", REG_GR + 12);
6751 declare_register ("rp", REG_BR + 0);
6752
542d6675 6753 /* pseudo-registers used to specify unwind info: */
e0c9811a
JW		 6754 declare_register ("psp", REG_PSP);
6755
800eeca4
JW		 6756 declare_register_set ("ret", 4, REG_GR + 8);
6757 declare_register_set ("farg", 8, REG_FR + 8);
6758 declare_register_set ("fret", 8, REG_FR + 8);
6759
6760 for (i = 0; i < NELEMS (const_bits); ++i)
6761 {
6762 err = hash_insert (md.const_hash, const_bits[i].name,
6763 (PTR) (const_bits + i));
6764 if (err)
6765 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6766 name, err);
6767 }
6768
44f5c83a
JW		 6769 /* Set the architecture and machine depending on defaults and command line
6770 options. */
6771 if (md.flags & EF_IA_64_ABI64)
6772 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
6773 else
6774 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
6775
6776 if (! ok)
6777 as_warn (_("Could not set architecture and machine"));
800eeca4 6778
557debba
JW		 6779 /* Set the pointer size and pointer shift size depending on md.flags */
6780
6781 if (md.flags & EF_IA_64_ABI64)
6782 {
6783 md.pointer_size = 8; /* pointers are 8 bytes */
6784 md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */
6785 }
6786 else
6787 {
6788 md.pointer_size = 4; /* pointers are 4 bytes */
6789 md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */
6790 }
6791
800eeca4
JW		 6792 md.mem_offset.hint = 0;
6793 md.path = 0;
6794 md.maxpaths = 0;
6795 md.entry_labels = NULL;
6796}
6797
44f5c83a
JW		 6798/* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6799 because that is called after md_parse_option which is where we do the
6800 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6801 default endianness. */
6802
6803void
6804ia64_init (argc, argv)
2434f565
JW		 6805 int argc ATTRIBUTE_UNUSED;
6806 char **argv ATTRIBUTE_UNUSED;
44f5c83a 6807{
1cd8ff38 6808 md.flags = MD_FLAGS_DEFAULT;
44f5c83a
JW		 6809}
6810
6811/* Return a string for the target object file format. */
6812
6813const char *
6814ia64_target_format ()
6815{
6816 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6817 {
72a76794
JW		 6818 if (md.flags & EF_IA_64_BE)
6819 {
6820 if (md.flags & EF_IA_64_ABI64)
1cd8ff38 6821#if defined(TE_AIX50)
7463c317 6822 return "elf64-ia64-aix-big";
1cd8ff38
NC		 6823#elif defined(TE_HPUX)
6824 return "elf64-ia64-hpux-big";
7463c317 6825#else
72a76794 6826 return "elf64-ia64-big";
7463c317 6827#endif
72a76794 6828 else
1cd8ff38 6829#if defined(TE_AIX50)
7463c317 6830 return "elf32-ia64-aix-big";
1cd8ff38
NC		 6831#elif defined(TE_HPUX)
6832 return "elf32-ia64-hpux-big";
7463c317 6833#else
72a76794 6834 return "elf32-ia64-big";
7463c317 6835#endif
72a76794 6836 }
44f5c83a 6837 else
72a76794
JW		 6838 {
6839 if (md.flags & EF_IA_64_ABI64)
7463c317
TW		 6840#ifdef TE_AIX50
6841 return "elf64-ia64-aix-little";
6842#else
72a76794 6843 return "elf64-ia64-little";
7463c317 6844#endif
72a76794 6845 else
7463c317
TW		 6846#ifdef TE_AIX50
6847 return "elf32-ia64-aix-little";
6848#else
72a76794 6849 return "elf32-ia64-little";
7463c317 6850#endif
72a76794 6851 }
44f5c83a
JW		 6852 }
6853 else
6854 return "unknown-format";
6855}
6856
800eeca4
JW		 6857void
6858ia64_end_of_source ()
6859{
542d6675 6860 /* terminate insn group upon reaching end of file: */
800eeca4
JW		 6861 insn_group_break (1, 0, 0);
6862
542d6675 6863 /* emits slots we haven't written yet: */
800eeca4
JW		 6864 ia64_flush_insns ();
6865
6866 bfd_set_private_flags (stdoutput, md.flags);
6867
800eeca4
JW		 6868 md.mem_offset.hint = 0;
6869}
6870
6871void
6872ia64_start_line ()
6873{
f1bcba5b
JW		 6874 if (md.qp.X_op == O_register)
6875 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW		 6876 md.qp.X_op = O_absent;
6877
6878 if (ignore_input ())
6879 return;
6880
6881 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6882 {
6883 if (md.detect_dv && !md.explicit_mode)
542d6675 6884 as_warn (_("Explicit stops are ignored in auto mode"));
800eeca4 6885 else
542d6675 6886 insn_group_break (1, 0, 0);
800eeca4
JW		 6887 }
6888}
6889
f1bcba5b
JW		 6890/* This is a hook for ia64_frob_label, so that it can distinguish tags from
6891 labels. */
6892static int defining_tag = 0;
6893
800eeca4
JW		 6894int
6895ia64_unrecognized_line (ch)
6896 int ch;
6897{
6898 switch (ch)
6899 {
6900 case '(':
6901 expression (&md.qp);
6902 if (*input_line_pointer++ != ')')
6903 {
6904 as_bad ("Expected ')'");
6905 return 0;
6906 }
6907 if (md.qp.X_op != O_register)
6908 {
6909 as_bad ("Qualifying predicate expected");
6910 return 0;
6911 }
6912 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6913 {
6914 as_bad ("Predicate register expected");
6915 return 0;
6916 }
6917 return 1;
6918
6919 case '{':
6920 if (md.manual_bundling)
6921 as_warn ("Found '{' when manual bundling is already turned on");
6922 else
6923 CURR_SLOT.manual_bundling_on = 1;
6924 md.manual_bundling = 1;
6925
542d6675
KH		 6926 /* Bundling is only acceptable in explicit mode
6927 or when in default automatic mode. */
800eeca4 6928 if (md.detect_dv && !md.explicit_mode)
542d6675
KH		 6929 {
6930 if (!md.mode_explicitly_set
6931 && !md.default_explicit_mode)
6932 dot_dv_mode ('E');
6933 else
6934 as_warn (_("Found '{' after explicit switch to automatic mode"));
6935 }
800eeca4
JW		 6936 return 1;
6937
6938 case '}':
6939 if (!md.manual_bundling)
6940 as_warn ("Found '}' when manual bundling is off");
6941 else
6942 PREV_SLOT.manual_bundling_off = 1;
6943 md.manual_bundling = 0;
6944
6945 /* switch back to automatic mode, if applicable */
197865e8 6946 if (md.detect_dv
542d6675
KH		 6947 && md.explicit_mode
6948 && !md.mode_explicitly_set
6949 && !md.default_explicit_mode)
6950 dot_dv_mode ('A');
800eeca4
JW		 6951
6952 /* Allow '{' to follow on the same line. We also allow ";;", but that
6953 happens automatically because ';' is an end of line marker. */
6954 SKIP_WHITESPACE ();
6955 if (input_line_pointer[0] == '{')
6956 {
6957 input_line_pointer++;
6958 return ia64_unrecognized_line ('{');
6959 }
6960
6961 demand_empty_rest_of_line ();
6962 return 1;
6963
f1bcba5b
JW		 6964 case '[':
6965 {
6966 char *s;
6967 char c;
6968 symbolS *tag;
4d5a53ff 6969 int temp;
f1bcba5b
JW		 6970
6971 if (md.qp.X_op == O_register)
6972 {
6973 as_bad ("Tag must come before qualifying predicate.");
6974 return 0;
6975 }
4d5a53ff
JW		 6976
6977 /* This implements just enough of read_a_source_file in read.c to
6978 recognize labels. */
6979 if (is_name_beginner (*input_line_pointer))
6980 {
6981 s = input_line_pointer;
6982 c = get_symbol_end ();
6983 }
6984 else if (LOCAL_LABELS_FB
3882b010 6985 && ISDIGIT (*input_line_pointer))
4d5a53ff
JW		 6986 {
6987 temp = 0;
3882b010 6988 while (ISDIGIT (*input_line_pointer))
4d5a53ff
JW		 6989 temp = (temp * 10) + *input_line_pointer++ - '0';
6990 fb_label_instance_inc (temp);
6991 s = fb_label_name (temp, 0);
6992 c = *input_line_pointer;
6993 }
6994 else
6995 {
6996 s = NULL;
6997 c = '\0';
6998 }
f1bcba5b
JW		 6999 if (c != ':')
7000 {
7001 /* Put ':' back for error messages' sake. */
7002 *input_line_pointer++ = ':';
7003 as_bad ("Expected ':'");
7004 return 0;
7005 }
4d5a53ff 7006
f1bcba5b
JW		 7007 defining_tag = 1;
7008 tag = colon (s);
7009 defining_tag = 0;
7010 /* Put ':' back for error messages' sake. */
7011 *input_line_pointer++ = ':';
7012 if (*input_line_pointer++ != ']')
7013 {
7014 as_bad ("Expected ']'");
7015 return 0;
7016 }
7017 if (! tag)
7018 {
7019 as_bad ("Tag name expected");
7020 return 0;
7021 }
7022 return 1;
7023 }
7024
800eeca4
JW		 7025 default:
7026 break;
7027 }
542d6675
KH		 7028
7029 /* Not a valid line. */
7030 return 0;
800eeca4
JW		 7031}
7032
7033void
7034ia64_frob_label (sym)
7035 struct symbol *sym;
7036{
7037 struct label_fix *fix;
7038
f1bcba5b
JW		 7039 /* Tags need special handling since they are not bundle breaks like
7040 labels. */
7041 if (defining_tag)
7042 {
7043 fix = obstack_alloc (&notes, sizeof (*fix));
7044 fix->sym = sym;
7045 fix->next = CURR_SLOT.tag_fixups;
7046 CURR_SLOT.tag_fixups = fix;
7047
7048 return;
7049 }
7050
800eeca4
JW		 7051 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
7052 {
7053 md.last_text_seg = now_seg;
7054 fix = obstack_alloc (&notes, sizeof (*fix));
7055 fix->sym = sym;
7056 fix->next = CURR_SLOT.label_fixups;
7057 CURR_SLOT.label_fixups = fix;
7058
542d6675 7059 /* Keep track of how many code entry points we've seen. */
800eeca4 7060 if (md.path == md.maxpaths)
542d6675
KH		 7061 {
7062 md.maxpaths += 20;
7063 md.entry_labels = (const char **)
7064 xrealloc ((void *) md.entry_labels,
7065 md.maxpaths * sizeof (char *));
7066 }
800eeca4
JW		 7067 md.entry_labels[md.path++] = S_GET_NAME (sym);
7068 }
7069}
7070
7071void
7072ia64_flush_pending_output ()
7073{
4d5a53ff
JW		 7074 if (!md.keep_pending_output
7075 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
800eeca4
JW		 7076 {
7077 /* ??? This causes many unnecessary stop bits to be emitted.
7078 Unfortunately, it isn't clear if it is safe to remove this. */
7079 insn_group_break (1, 0, 0);
7080 ia64_flush_insns ();
7081 }
7082}
7083
7084/* Do ia64-specific expression optimization. All that's done here is
7085 to transform index expressions that are either due to the indexing
7086 of rotating registers or due to the indexing of indirect register
7087 sets. */
7088int
7089ia64_optimize_expr (l, op, r)
7090 expressionS *l;
7091 operatorT op;
7092 expressionS *r;
7093{
7094 unsigned num_regs;
7095
7096 if (op == O_index)
7097 {
7098 if (l->X_op == O_register && r->X_op == O_constant)
7099 {
7100 num_regs = (l->X_add_number >> 16);
7101 if ((unsigned) r->X_add_number >= num_regs)
7102 {
7103 if (!num_regs)
7104 as_bad ("No current frame");
7105 else
7106 as_bad ("Index out of range 0..%u", num_regs - 1);
7107 r->X_add_number = 0;
7108 }
7109 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
7110 return 1;
7111 }
7112 else if (l->X_op == O_register && r->X_op == O_register)
7113 {
7114 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
7115 || l->X_add_number == IND_MEM)
7116 {
7117 as_bad ("Indirect register set name expected");
7118 l->X_add_number = IND_CPUID;
7119 }
7120 l->X_op = O_index;
7121 l->X_op_symbol = md.regsym[l->X_add_number];
7122 l->X_add_number = r->X_add_number;
7123 return 1;
7124 }
7125 }
7126 return 0;
7127}
7128
7129int
7130ia64_parse_name (name, e)
7131 char *name;
7132 expressionS *e;
7133{
7134 struct const_desc *cdesc;
7135 struct dynreg *dr = 0;
7136 unsigned int regnum;
7137 struct symbol *sym;
7138 char *end;
7139
542d6675 7140 /* first see if NAME is a known register name: */
800eeca4
JW		 7141 sym = hash_find (md.reg_hash, name);
7142 if (sym)
7143 {
7144 e->X_op = O_register;
7145 e->X_add_number = S_GET_VALUE (sym);
7146 return 1;
7147 }
7148
7149 cdesc = hash_find (md.const_hash, name);
7150 if (cdesc)
7151 {
7152 e->X_op = O_constant;
7153 e->X_add_number = cdesc->value;
7154 return 1;
7155 }
7156
542d6675 7157 /* check for inN, locN, or outN: */
800eeca4
JW		 7158 switch (name[0])
7159 {
7160 case 'i':
3882b010 7161 if (name[1] == 'n' && ISDIGIT (name[2]))
800eeca4
JW		 7162 {
7163 dr = &md.in;
7164 name += 2;
7165 }
7166 break;
7167
7168 case 'l':
3882b010 7169 if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3]))
800eeca4
JW		 7170 {
7171 dr = &md.loc;
7172 name += 3;
7173 }
7174 break;
7175
7176 case 'o':
3882b010 7177 if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3]))
800eeca4
JW		 7178 {
7179 dr = &md.out;
7180 name += 3;
7181 }
7182 break;
7183
7184 default:
7185 break;
7186 }
7187
7188 if (dr)
7189 {
542d6675 7190 /* The name is inN, locN, or outN; parse the register number. */
800eeca4
JW		 7191 regnum = strtoul (name, &end, 10);
7192 if (end > name && *end == '\0')
7193 {
7194 if ((unsigned) regnum >= dr->num_regs)
7195 {
7196 if (!dr->num_regs)
7197 as_bad ("No current frame");
7198 else
542d6675
KH		 7199 as_bad ("Register number out of range 0..%u",
7200 dr->num_regs - 1);
800eeca4
JW		 7201 regnum = 0;
7202 }
7203 e->X_op = O_register;
7204 e->X_add_number = dr->base + regnum;
7205 return 1;
7206 }
7207 }
7208
7209 if ((dr = hash_find (md.dynreg_hash, name)))
7210 {
7211 /* We've got ourselves the name of a rotating register set.
542d6675
KH		 7212 Store the base register number in the low 16 bits of
7213 X_add_number and the size of the register set in the top 16
7214 bits. */
800eeca4
JW		 7215 e->X_op = O_register;
7216 e->X_add_number = dr->base | (dr->num_regs << 16);
7217 return 1;
7218 }
7219 return 0;
7220}
7221
7222/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7223
7224char *
7225ia64_canonicalize_symbol_name (name)
7226 char *name;
7227{
542d6675
KH		 7228 size_t len = strlen (name);
7229 if (len > 1 && name[len - 1] == '#')
7230 name[len - 1] = '\0';
800eeca4
JW		 7231 return name;
7232}
7233
3e37788f
JW		 7234/* Return true if idesc is a conditional branch instruction. This excludes
7235 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7236 because they always read/write resources regardless of the value of the
7237 qualifying predicate. br.ia must always use p0, and hence is always
7238 taken. Thus this function returns true for branches which can fall
7239 through, and which use no resources if they do fall through. */
1deb8127 7240
800eeca4
JW		 7241static int
7242is_conditional_branch (idesc)
542d6675 7243 struct ia64_opcode *idesc;
800eeca4 7244{
1deb8127 7245 /* br is a conditional branch. Everything that starts with br. except
3e37788f
JW		 7246 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7247 Everything that starts with brl is a conditional branch. */
1deb8127
JW		 7248 return (idesc->name[0] == 'b' && idesc->name[1] == 'r'
7249 && (idesc->name[2] == '\0'
3e37788f
JW		 7250 || (idesc->name[2] == '.' && idesc->name[3] != 'i'
7251 && idesc->name[3] != 'c' && idesc->name[3] != 'w')
7252 || idesc->name[2] == 'l'
7253 /* br.cond, br.call, br.clr */
7254 || (idesc->name[2] == '.' && idesc->name[3] == 'c'
7255 && (idesc->name[4] == 'a' || idesc->name[4] == 'o'
7256 || (idesc->name[4] == 'l' && idesc->name[5] == 'r')))));
800eeca4
JW		 7257}
7258
7259/* Return whether the given opcode is a taken branch. If there's any doubt,
542d6675
KH		 7260 returns zero. */
7261
800eeca4
JW		 7262static int
7263is_taken_branch (idesc)
542d6675 7264 struct ia64_opcode *idesc;
800eeca4
JW		 7265{
7266 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
542d6675 7267 || strncmp (idesc->name, "br.ia", 5) == 0);
800eeca4
JW		 7268}
7269
7270/* Return whether the given opcode is an interruption or rfi. If there's any
542d6675
KH		 7271 doubt, returns zero. */
7272
800eeca4
JW		 7273static int
7274is_interruption_or_rfi (idesc)
542d6675 7275 struct ia64_opcode *idesc;
800eeca4
JW		 7276{
7277 if (strcmp (idesc->name, "rfi") == 0)
7278 return 1;
7279 return 0;
7280}
7281
7282/* Returns the index of the given dependency in the opcode's list of chks, or
7283 -1 if there is no dependency. */
542d6675 7284
800eeca4
JW		 7285static int
7286depends_on (depind, idesc)
542d6675
KH		 7287 int depind;
7288 struct ia64_opcode *idesc;
800eeca4
JW		 7289{
7290 int i;
7291 const struct ia64_opcode_dependency *dep = idesc->dependencies;
542d6675 7292 for (i = 0; i < dep->nchks; i++)
800eeca4 7293 {
542d6675
KH		 7294 if (depind == DEP (dep->chks[i]))
7295 return i;
800eeca4
JW		 7296 }
7297 return -1;
7298}
7299
7300/* Determine a set of specific resources used for a particular resource
7301 class. Returns the number of specific resources identified For those
7302 cases which are not determinable statically, the resource returned is
197865e8 7303 marked nonspecific.
800eeca4
JW		 7304
7305 Meanings of value in 'NOTE':
7306 1) only read/write when the register number is explicitly encoded in the
7307 insn.
7308 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
197865e8 7309 accesses CFM when qualifying predicate is in the rotating region.
800eeca4
JW		 7310 3) general register value is used to specify an indirect register; not
7311 determinable statically.
7312 4) only read the given resource when bits 7:0 of the indirect index
7313 register value does not match the register number of the resource; not
7314 determinable statically.
7315 5) all rules are implementation specific.
7316 6) only when both the index specified by the reader and the index specified
7317 by the writer have the same value in bits 63:61; not determinable
197865e8 7318 statically.
800eeca4 7319 7) only access the specified resource when the corresponding mask bit is
197865e8 7320 set
800eeca4
JW		 7321 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7322 only read when these insns reference FR2-31
7323 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7324 written when these insns write FR32-127
7325 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7326 instruction
7327 11) The target predicates are written independently of PR[qp], but source
7328 registers are only read if PR[qp] is true. Since the state of PR[qp]
7329 cannot statically be determined, all source registers are marked used.
7330 12) This insn only reads the specified predicate register when that
7331 register is the PR[qp].
7332 13) This reference to ld-c only applies to teh GR whose value is loaded
197865e8 7333 with data returned from memory, not the post-incremented address register.
800eeca4
JW		 7334 14) The RSE resource includes the implementation-specific RSE internal
7335 state resources. At least one (and possibly more) of these resources are
7336 read by each instruction listed in IC:rse-readers. At least one (and
7337 possibly more) of these resources are written by each insn listed in
197865e8 7338 IC:rse-writers.
800eeca4 7339 15+16) Represents reserved instructions, which the assembler does not
197865e8 7340 generate.
800eeca4
JW		 7341
7342 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7343 this code; there are no dependency violations based on memory access.
800eeca4
JW		 7344*/
7345
7346#define MAX_SPECS 256
7347#define DV_CHK 1
7348#define DV_REG 0
7349
7350static int
7351specify_resource (dep, idesc, type, specs, note, path)
542d6675
KH		 7352 const struct ia64_dependency *dep;
7353 struct ia64_opcode *idesc;
7354 int type; /* is this a DV chk or a DV reg? */
7355 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
7356 int note; /* resource note for this insn's usage */
7357 int path; /* which execution path to examine */
800eeca4
JW		 7358{
7359 int count = 0;
7360 int i;
7361 int rsrc_write = 0;
7362 struct rsrc tmpl;
197865e8 7363
800eeca4
JW		 7364 if (dep->mode == IA64_DV_WAW
7365 || (dep->mode == IA64_DV_RAW && type == DV_REG)
7366 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
7367 rsrc_write = 1;
7368
7369 /* template for any resources we identify */
7370 tmpl.dependency = dep;
7371 tmpl.note = note;
7372 tmpl.insn_srlz = tmpl.data_srlz = 0;
7373 tmpl.qp_regno = CURR_SLOT.qp_regno;
7374 tmpl.link_to_qp_branch = 1;
7375 tmpl.mem_offset.hint = 0;
7376 tmpl.specific = 1;
7377 tmpl.index = 0;
7484b8e6 7378 tmpl.cmp_type = CMP_NONE;
800eeca4
JW		 7379
7380#define UNHANDLED \
7381as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7382dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7383#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7384
7385 /* we don't need to track these */
7386 if (dep->semantics == IA64_DVS_NONE)
7387 return 0;
7388
7389 switch (dep->specifier)
7390 {
7391 case IA64_RS_AR_K:
7392 if (note == 1)
542d6675
KH		 7393 {
7394 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7395 {
7396 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7397 if (regno >= 0 && regno <= 7)
7398 {
7399 specs[count] = tmpl;
7400 specs[count++].index = regno;
7401 }
7402 }
7403 }
800eeca4 7404 else if (note == 0)
542d6675
KH		 7405 {
7406 for (i = 0; i < 8; i++)
7407 {
7408 specs[count] = tmpl;
7409 specs[count++].index = i;
7410 }
7411 }
800eeca4 7412 else
542d6675
KH		 7413 {
7414 UNHANDLED;
7415 }
800eeca4
JW		 7416 break;
7417
7418 case IA64_RS_AR_UNAT:
7419 /* This is a mov =AR or mov AR= instruction. */
7420 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7421 {
7422 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7423 if (regno == AR_UNAT)
7424 {
7425 specs[count++] = tmpl;
7426 }
7427 }
7428 else
7429 {
7430 /* This is a spill/fill, or other instruction that modifies the
7431 unat register. */
7432
7433 /* Unless we can determine the specific bits used, mark the whole
7434 thing; bits 8:3 of the memory address indicate the bit used in
7435 UNAT. The .mem.offset hint may be used to eliminate a small
7436 subset of conflicts. */
7437 specs[count] = tmpl;
7438 if (md.mem_offset.hint)
7439 {
542d6675
KH		 7440 if (md.debug_dv)
7441 fprintf (stderr, " Using hint for spill/fill\n");
7442 /* The index isn't actually used, just set it to something
7443 approximating the bit index. */
800eeca4
JW		 7444 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
7445 specs[count].mem_offset.hint = 1;
7446 specs[count].mem_offset.offset = md.mem_offset.offset;
7447 specs[count++].mem_offset.base = md.mem_offset.base;
7448 }
7449 else
7450 {
7451 specs[count++].specific = 0;
7452 }
7453 }
7454 break;
7455
7456 case IA64_RS_AR:
7457 if (note == 1)
542d6675
KH		 7458 {
7459 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7460 {
7461 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7462 if ((regno >= 8 && regno <= 15)
7463 || (regno >= 20 && regno <= 23)
7464 || (regno >= 31 && regno <= 39)
7465 || (regno >= 41 && regno <= 47)
7466 || (regno >= 67 && regno <= 111))
7467 {
7468 specs[count] = tmpl;
7469 specs[count++].index = regno;
7470 }
7471 }
7472 }
800eeca4 7473 else
542d6675
KH		 7474 {
7475 UNHANDLED;
7476 }
800eeca4
JW		 7477 break;
7478
7479 case IA64_RS_ARb:
7480 if (note == 1)
542d6675
KH		 7481 {
7482 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7483 {
7484 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7485 if ((regno >= 48 && regno <= 63)
7486 || (regno >= 112 && regno <= 127))
7487 {
7488 specs[count] = tmpl;
7489 specs[count++].index = regno;
7490 }
7491 }
7492 }
800eeca4 7493 else if (note == 0)
542d6675
KH		 7494 {
7495 for (i = 48; i < 64; i++)
7496 {
7497 specs[count] = tmpl;
7498 specs[count++].index = i;
7499 }
7500 for (i = 112; i < 128; i++)
7501 {
7502 specs[count] = tmpl;
7503 specs[count++].index = i;
7504 }
7505 }
197865e8 7506 else
542d6675
KH		 7507 {
7508 UNHANDLED;
7509 }
800eeca4
JW		 7510 break;
7511
7512 case IA64_RS_BR:
7513 if (note != 1)
542d6675
KH		 7514 {
7515 UNHANDLED;
7516 }
800eeca4 7517 else
542d6675
KH		 7518 {
7519 if (rsrc_write)
7520 {
7521 for (i = 0; i < idesc->num_outputs; i++)
7522 if (idesc->operands[i] == IA64_OPND_B1
7523 || idesc->operands[i] == IA64_OPND_B2)
7524 {
7525 specs[count] = tmpl;
7526 specs[count++].index =
7527 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7528 }
7529 }
7530 else
7531 {
40449e9f 7532 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
542d6675
KH		 7533 if (idesc->operands[i] == IA64_OPND_B1
7534 || idesc->operands[i] == IA64_OPND_B2)
7535 {
7536 specs[count] = tmpl;
7537 specs[count++].index =
7538 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7539 }
7540 }
7541 }
800eeca4
JW		 7542 break;
7543
7544 case IA64_RS_CPUID: /* four or more registers */
7545 if (note == 3)
542d6675
KH		 7546 {
7547 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
7548 {
7549 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7550 if (regno >= 0 && regno < NELEMS (gr_values)
7551 && KNOWN (regno))
7552 {
7553 specs[count] = tmpl;
7554 specs[count++].index = gr_values[regno].value & 0xFF;
7555 }
7556 else
7557 {
7558 specs[count] = tmpl;
7559 specs[count++].specific = 0;
7560 }
7561 }
7562 }
800eeca4 7563 else
542d6675
KH		 7564 {
7565 UNHANDLED;
7566 }
800eeca4
JW		 7567 break;
7568
7569 case IA64_RS_DBR: /* four or more registers */
7570 if (note == 3)
542d6675
KH		 7571 {
7572 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
7573 {
7574 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7575 if (regno >= 0 && regno < NELEMS (gr_values)
7576 && KNOWN (regno))
7577 {
7578 specs[count] = tmpl;
7579 specs[count++].index = gr_values[regno].value & 0xFF;
7580 }
7581 else
7582 {
7583 specs[count] = tmpl;
7584 specs[count++].specific = 0;
7585 }
7586 }
7587 }
800eeca4 7588 else if (note == 0 && !rsrc_write)
542d6675
KH		 7589 {
7590 specs[count] = tmpl;
7591 specs[count++].specific = 0;
7592 }
800eeca4 7593 else
542d6675
KH		 7594 {
7595 UNHANDLED;
7596 }
800eeca4
JW		 7597 break;
7598
7599 case IA64_RS_IBR: /* four or more registers */
7600 if (note == 3)
542d6675
KH		 7601 {
7602 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
7603 {
7604 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7605 if (regno >= 0 && regno < NELEMS (gr_values)
7606 && KNOWN (regno))
7607 {
7608 specs[count] = tmpl;
7609 specs[count++].index = gr_values[regno].value & 0xFF;
7610 }
7611 else
7612 {
7613 specs[count] = tmpl;
7614 specs[count++].specific = 0;
7615 }
7616 }
7617 }
800eeca4 7618 else
542d6675
KH		 7619 {
7620 UNHANDLED;
7621 }
800eeca4
JW		 7622 break;
7623
7624 case IA64_RS_MSR:
7625 if (note == 5)
7626 {
7627 /* These are implementation specific. Force all references to
7628 conflict with all other references. */
7629 specs[count] = tmpl;
7630 specs[count++].specific = 0;
7631 }
7632 else
7633 {
7634 UNHANDLED;
7635 }
7636 break;
7637
7638 case IA64_RS_PKR: /* 16 or more registers */
7639 if (note == 3 || note == 4)
542d6675
KH		 7640 {
7641 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
7642 {
7643 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7644 if (regno >= 0 && regno < NELEMS (gr_values)
7645 && KNOWN (regno))
7646 {
7647 if (note == 3)
7648 {
7649 specs[count] = tmpl;
7650 specs[count++].index = gr_values[regno].value & 0xFF;
7651 }
7652 else
7653 for (i = 0; i < NELEMS (gr_values); i++)
7654 {
7655 /* Uses all registers *except* the one in R3. */
2434f565 7656 if ((unsigned)i != (gr_values[regno].value & 0xFF))
542d6675
KH		 7657 {
7658 specs[count] = tmpl;
7659 specs[count++].index = i;
7660 }
7661 }
7662 }
7663 else
7664 {
7665 specs[count] = tmpl;
7666 specs[count++].specific = 0;
7667 }
7668 }
7669 }
7670 else if (note == 0)
7671 {
7672 /* probe et al. */
7673 specs[count] = tmpl;
7674 specs[count++].specific = 0;
7675 }
7676 break;
7677
7678 case IA64_RS_PMC: /* four or more registers */
7679 if (note == 3)
7680 {
7681 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
7682 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
7683
7684 {
7685 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
7686 ? 1 : !rsrc_write);
7687 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
7688 if (regno >= 0 && regno < NELEMS (gr_values)
7689 && KNOWN (regno))
7690 {
7691 specs[count] = tmpl;
7692 specs[count++].index = gr_values[regno].value & 0xFF;
7693 }
7694 else
7695 {
7696 specs[count] = tmpl;
7697 specs[count++].specific = 0;
7698 }
7699 }
7700 }
7701 else
7702 {
7703 UNHANDLED;
7704 }
800eeca4
JW		 7705 break;
7706
7707 case IA64_RS_PMD: /* four or more registers */
7708 if (note == 3)
542d6675
KH		 7709 {
7710 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
7711 {
7712 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7713 if (regno >= 0 && regno < NELEMS (gr_values)
7714 && KNOWN (regno))
7715 {
7716 specs[count] = tmpl;
7717 specs[count++].index = gr_values[regno].value & 0xFF;
7718 }
7719 else
7720 {
7721 specs[count] = tmpl;
7722 specs[count++].specific = 0;
7723 }
7724 }
7725 }
800eeca4 7726 else
542d6675
KH		 7727 {
7728 UNHANDLED;
7729 }
800eeca4
JW		 7730 break;
7731
7732 case IA64_RS_RR: /* eight registers */
7733 if (note == 6)
542d6675
KH		 7734 {
7735 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
7736 {
7737 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7738 if (regno >= 0 && regno < NELEMS (gr_values)
7739 && KNOWN (regno))
7740 {
7741 specs[count] = tmpl;
7742 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
7743 }
7744 else
7745 {
7746 specs[count] = tmpl;
7747 specs[count++].specific = 0;
7748 }
7749 }
7750 }
800eeca4 7751 else if (note == 0 && !rsrc_write)
542d6675
KH		 7752 {
7753 specs[count] = tmpl;
7754 specs[count++].specific = 0;
7755 }
197865e8 7756 else
542d6675
KH		 7757 {
7758 UNHANDLED;
7759 }
800eeca4
JW		 7760 break;
7761
7762 case IA64_RS_CR_IRR:
197865e8 7763 if (note == 0)
542d6675
KH		 7764 {
7765 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7766 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
7767 if (rsrc_write
7768 && idesc->operands[1] == IA64_OPND_CR3
7769 && regno == CR_IVR)
7770 {
7771 for (i = 0; i < 4; i++)
7772 {
7773 specs[count] = tmpl;
7774 specs[count++].index = CR_IRR0 + i;
7775 }
7776 }
7777 }
800eeca4 7778 else if (note == 1)
542d6675
KH		 7779 {
7780 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7781 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7782 && regno >= CR_IRR0
7783 && regno <= CR_IRR3)
7784 {
7785 specs[count] = tmpl;
7786 specs[count++].index = regno;
7787 }
7788 }
800eeca4 7789 else
542d6675
KH		 7790 {
7791 UNHANDLED;
7792 }
800eeca4
JW		 7793 break;
7794
7795 case IA64_RS_CR_LRR:
7796 if (note != 1)
542d6675
KH		 7797 {
7798 UNHANDLED;
7799 }
197865e8 7800 else
542d6675
KH		 7801 {
7802 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7803 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7804 && (regno == CR_LRR0 || regno == CR_LRR1))
7805 {
7806 specs[count] = tmpl;
7807 specs[count++].index = regno;
7808 }
7809 }
800eeca4
JW		 7810 break;
7811
7812 case IA64_RS_CR:
7813 if (note == 1)
542d6675
KH		 7814 {
7815 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7816 {
7817 specs[count] = tmpl;
7818 specs[count++].index =
7819 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7820 }
7821 }
800eeca4 7822 else
542d6675
KH		 7823 {
7824 UNHANDLED;
7825 }
800eeca4
JW		 7826 break;
7827
7828 case IA64_RS_FR:
7829 case IA64_RS_FRb:
7830 if (note != 1)
542d6675
KH		 7831 {
7832 UNHANDLED;
7833 }
800eeca4 7834 else if (rsrc_write)
542d6675
KH		 7835 {
7836 if (dep->specifier == IA64_RS_FRb
7837 && idesc->operands[0] == IA64_OPND_F1)
7838 {
7839 specs[count] = tmpl;
7840 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
7841 }
7842 }
800eeca4 7843 else
542d6675
KH		 7844 {
7845 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7846 {
7847 if (idesc->operands[i] == IA64_OPND_F2
7848 || idesc->operands[i] == IA64_OPND_F3
7849 || idesc->operands[i] == IA64_OPND_F4)
7850 {
7851 specs[count] = tmpl;
7852 specs[count++].index =
7853 CURR_SLOT.opnd[i].X_add_number - REG_FR;
7854 }
7855 }
7856 }
800eeca4
JW		 7857 break;
7858
7859 case IA64_RS_GR:
7860 if (note == 13)
542d6675
KH		 7861 {
7862 /* This reference applies only to the GR whose value is loaded with
7863 data returned from memory. */
7864 specs[count] = tmpl;
7865 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7866 }
800eeca4 7867 else if (note == 1)
542d6675
KH		 7868 {
7869 if (rsrc_write)
7870 {
7871 for (i = 0; i < idesc->num_outputs; i++)
50b81f19
JW		 7872 if (idesc->operands[i] == IA64_OPND_R1
7873 || idesc->operands[i] == IA64_OPND_R2
7874 || idesc->operands[i] == IA64_OPND_R3)
7875 {
7876 specs[count] = tmpl;
197865e8 7877 specs[count++].index =
50b81f19
JW		 7878 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7879 }
7880 if (idesc->flags & IA64_OPCODE_POSTINC)
7881 for (i = 0; i < NELEMS (idesc->operands); i++)
7882 if (idesc->operands[i] == IA64_OPND_MR3)
7883 {
7884 specs[count] = tmpl;
7885 specs[count++].index =
7886 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7887 }
542d6675
KH		 7888 }
7889 else
7890 {
7891 /* Look for anything that reads a GR. */
7892 for (i = 0; i < NELEMS (idesc->operands); i++)
7893 {
7894 if (idesc->operands[i] == IA64_OPND_MR3
7895 || idesc->operands[i] == IA64_OPND_CPUID_R3
7896 || idesc->operands[i] == IA64_OPND_DBR_R3
7897 || idesc->operands[i] == IA64_OPND_IBR_R3
800eeca4 7898 || idesc->operands[i] == IA64_OPND_MSR_R3
542d6675
KH		 7899 || idesc->operands[i] == IA64_OPND_PKR_R3
7900 || idesc->operands[i] == IA64_OPND_PMC_R3
7901 || idesc->operands[i] == IA64_OPND_PMD_R3
7902 || idesc->operands[i] == IA64_OPND_RR_R3
7903 || ((i >= idesc->num_outputs)
7904 && (idesc->operands[i] == IA64_OPND_R1
7905 || idesc->operands[i] == IA64_OPND_R2
7906 || idesc->operands[i] == IA64_OPND_R3
50b81f19
JW		 7907 /* addl source register. */
7908 || idesc->operands[i] == IA64_OPND_R3_2)))
542d6675
KH		 7909 {
7910 specs[count] = tmpl;
7911 specs[count++].index =
7912 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7913 }
7914 }
7915 }
7916 }
197865e8 7917 else
542d6675
KH		 7918 {
7919 UNHANDLED;
7920 }
800eeca4
JW		 7921 break;
7922
139368c9
JW		 7923 /* This is the same as IA64_RS_PRr, except that the register range is
7924 from 1 - 15, and there are no rotating register reads/writes here. */
800eeca4
JW		 7925 case IA64_RS_PR:
7926 if (note == 0)
542d6675 7927 {
139368c9 7928 for (i = 1; i < 16; i++)
542d6675 7929 {
139368c9
JW		 7930 specs[count] = tmpl;
7931 specs[count++].index = i;
7932 }
7933 }
7934 else if (note == 7)
7935 {
7936 valueT mask = 0;
7937 /* Mark only those registers indicated by the mask. */
7938 if (rsrc_write)
7939 {
7940 mask = CURR_SLOT.opnd[2].X_add_number;
7941 for (i = 1; i < 16; i++)
7942 if (mask & ((valueT) 1 << i))
7943 {
7944 specs[count] = tmpl;
7945 specs[count++].index = i;
7946 }
7947 }
7948 else
7949 {
7950 UNHANDLED;
7951 }
7952 }
7953 else if (note == 11) /* note 11 implies note 1 as well */
7954 {
7955 if (rsrc_write)
7956 {
7957 for (i = 0; i < idesc->num_outputs; i++)
7958 {
7959 if (idesc->operands[i] == IA64_OPND_P1
7960 || idesc->operands[i] == IA64_OPND_P2)
7961 {
7962 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7963 if (regno >= 1 && regno < 16)
7964 {
7965 specs[count] = tmpl;
7966 specs[count++].index = regno;
7967 }
7968 }
7969 }
7970 }
7971 else
7972 {
7973 UNHANDLED;
7974 }
7975 }
7976 else if (note == 12)
7977 {
7978 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7979 {
7980 specs[count] = tmpl;
7981 specs[count++].index = CURR_SLOT.qp_regno;
7982 }
7983 }
7984 else if (note == 1)
7985 {
7986 if (rsrc_write)
7987 {
7988 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7989 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
07726851
KH		 7990 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
7991 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
139368c9
JW		 7992
7993 if ((idesc->operands[0] == IA64_OPND_P1
7994 || idesc->operands[0] == IA64_OPND_P2)
7995 && p1 >= 1 && p1 < 16)
542d6675
KH		 7996 {
7997 specs[count] = tmpl;
139368c9
JW		 7998 specs[count].cmp_type =
7999 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8000 specs[count++].index = p1;
8001 }
8002 if ((idesc->operands[1] == IA64_OPND_P1
8003 || idesc->operands[1] == IA64_OPND_P2)
8004 && p2 >= 1 && p2 < 16)
8005 {
8006 specs[count] = tmpl;
8007 specs[count].cmp_type =
8008 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8009 specs[count++].index = p2;
542d6675
KH		 8010 }
8011 }
8012 else
8013 {
139368c9 8014 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
542d6675
KH		 8015 {
8016 specs[count] = tmpl;
139368c9
JW		 8017 specs[count++].index = CURR_SLOT.qp_regno;
8018 }
8019 if (idesc->operands[1] == IA64_OPND_PR)
8020 {
8021 for (i = 1; i < 16; i++)
8022 {
8023 specs[count] = tmpl;
8024 specs[count++].index = i;
8025 }
542d6675
KH		 8026 }
8027 }
8028 }
139368c9
JW		 8029 else
8030 {
8031 UNHANDLED;
8032 }
8033 break;
8034
8035 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
8036 simplified cases of this. */
8037 case IA64_RS_PRr:
8038 if (note == 0)
8039 {
8040 for (i = 16; i < 63; i++)
8041 {
8042 specs[count] = tmpl;
8043 specs[count++].index = i;
8044 }
8045 }
800eeca4 8046 else if (note == 7)
542d6675
KH		 8047 {
8048 valueT mask = 0;
8049 /* Mark only those registers indicated by the mask. */
8050 if (rsrc_write
8051 && idesc->operands[0] == IA64_OPND_PR)
8052 {
8053 mask = CURR_SLOT.opnd[2].X_add_number;
40449e9f 8054 if (mask & ((valueT) 1 << 16))
139368c9
JW		 8055 for (i = 16; i < 63; i++)
8056 {
8057 specs[count] = tmpl;
8058 specs[count++].index = i;
8059 }
542d6675
KH		 8060 }
8061 else if (rsrc_write
8062 && idesc->operands[0] == IA64_OPND_PR_ROT)
8063 {
8064 for (i = 16; i < 63; i++)
8065 {
8066 specs[count] = tmpl;
8067 specs[count++].index = i;
8068 }
8069 }
8070 else
8071 {
8072 UNHANDLED;
8073 }
8074 }
800eeca4 8075 else if (note == 11) /* note 11 implies note 1 as well */
542d6675
KH		 8076 {
8077 if (rsrc_write)
8078 {
8079 for (i = 0; i < idesc->num_outputs; i++)
8080 {
8081 if (idesc->operands[i] == IA64_OPND_P1
8082 || idesc->operands[i] == IA64_OPND_P2)
8083 {
8084 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
139368c9 8085 if (regno >= 16 && regno < 63)
542d6675
KH		 8086 {
8087 specs[count] = tmpl;
8088 specs[count++].index = regno;
8089 }
8090 }
8091 }
8092 }
8093 else
8094 {
8095 UNHANDLED;
8096 }
8097 }
800eeca4 8098 else if (note == 12)
542d6675 8099 {
139368c9 8100 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH		 8101 {
8102 specs[count] = tmpl;
8103 specs[count++].index = CURR_SLOT.qp_regno;
8104 }
8105 }
800eeca4 8106 else if (note == 1)
542d6675
KH		 8107 {
8108 if (rsrc_write)
8109 {
8110 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8111 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
07726851
KH		 8112 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
8113 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
7484b8e6 8114
542d6675
KH		 8115 if ((idesc->operands[0] == IA64_OPND_P1
8116 || idesc->operands[0] == IA64_OPND_P2)
139368c9 8117 && p1 >= 16 && p1 < 63)
542d6675
KH		 8118 {
8119 specs[count] = tmpl;
4a4f25cf 8120 specs[count].cmp_type =
7484b8e6 8121 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
542d6675
KH		 8122 specs[count++].index = p1;
8123 }
8124 if ((idesc->operands[1] == IA64_OPND_P1
8125 || idesc->operands[1] == IA64_OPND_P2)
139368c9 8126 && p2 >= 16 && p2 < 63)
542d6675
KH		 8127 {
8128 specs[count] = tmpl;
4a4f25cf 8129 specs[count].cmp_type =
7484b8e6 8130 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
542d6675
KH		 8131 specs[count++].index = p2;
8132 }
8133 }
8134 else
8135 {
139368c9 8136 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH		 8137 {
8138 specs[count] = tmpl;
8139 specs[count++].index = CURR_SLOT.qp_regno;
8140 }
8141 if (idesc->operands[1] == IA64_OPND_PR)
8142 {
139368c9 8143 for (i = 16; i < 63; i++)
542d6675
KH		 8144 {
8145 specs[count] = tmpl;
8146 specs[count++].index = i;
8147 }
8148 }
8149 }
8150 }
197865e8 8151 else
542d6675
KH		 8152 {
8153 UNHANDLED;
8154 }
800eeca4
JW		 8155 break;
8156
8157 case IA64_RS_PSR:
197865e8 8158 /* Verify that the instruction is using the PSR bit indicated in
542d6675 8159 dep->regindex. */
800eeca4 8160 if (note == 0)
542d6675
KH		 8161 {
8162 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
8163 {
8164 if (dep->regindex < 6)
8165 {
8166 specs[count++] = tmpl;
8167 }
8168 }
8169 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
8170 {
8171 if (dep->regindex < 32
8172 || dep->regindex == 35
8173 || dep->regindex == 36
8174 || (!rsrc_write && dep->regindex == PSR_CPL))
8175 {
8176 specs[count++] = tmpl;
8177 }
8178 }
8179 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
8180 {
8181 if (dep->regindex < 32
8182 || dep->regindex == 35
8183 || dep->regindex == 36
8184 || (rsrc_write && dep->regindex == PSR_CPL))
8185 {
8186 specs[count++] = tmpl;
8187 }
8188 }
8189 else
8190 {
8191 /* Several PSR bits have very specific dependencies. */
8192 switch (dep->regindex)
8193 {
8194 default:
8195 specs[count++] = tmpl;
8196 break;
8197 case PSR_IC:
8198 if (rsrc_write)
8199 {
8200 specs[count++] = tmpl;
8201 }
8202 else
8203 {
8204 /* Only certain CR accesses use PSR.ic */
8205 if (idesc->operands[0] == IA64_OPND_CR3
8206 || idesc->operands[1] == IA64_OPND_CR3)
8207 {
8208 int index =
8209 ((idesc->operands[0] == IA64_OPND_CR3)
8210 ? 0 : 1);
8211 int regno =
8212 CURR_SLOT.opnd[index].X_add_number - REG_CR;
8213
8214 switch (regno)
8215 {
8216 default:
8217 break;
8218 case CR_ITIR:
8219 case CR_IFS:
8220 case CR_IIM:
8221 case CR_IIP:
8222 case CR_IPSR:
8223 case CR_ISR:
8224 case CR_IFA:
8225 case CR_IHA:
8226 case CR_IIPA:
8227 specs[count++] = tmpl;
8228 break;
8229 }
8230 }
8231 }
8232 break;
8233 case PSR_CPL:
8234 if (rsrc_write)
8235 {
8236 specs[count++] = tmpl;
8237 }
8238 else
8239 {
8240 /* Only some AR accesses use cpl */
8241 if (idesc->operands[0] == IA64_OPND_AR3
8242 || idesc->operands[1] == IA64_OPND_AR3)
8243 {
8244 int index =
8245 ((idesc->operands[0] == IA64_OPND_AR3)
8246 ? 0 : 1);
8247 int regno =
8248 CURR_SLOT.opnd[index].X_add_number - REG_AR;
8249
8250 if (regno == AR_ITC
8251 || (index == 0
8252 && (regno == AR_ITC
8253 || regno == AR_RSC
8254 || (regno >= AR_K0
8255 && regno <= AR_K7))))
8256 {
8257 specs[count++] = tmpl;
8258 }
8259 }
8260 else
8261 {
8262 specs[count++] = tmpl;
8263 }
8264 break;
8265 }
8266 }
8267 }
8268 }
800eeca4 8269 else if (note == 7)
542d6675
KH		 8270 {
8271 valueT mask = 0;
8272 if (idesc->operands[0] == IA64_OPND_IMMU24)
8273 {
8274 mask = CURR_SLOT.opnd[0].X_add_number;
8275 }
8276 else
8277 {
8278 UNHANDLED;
8279 }
8280 if (mask & ((valueT) 1 << dep->regindex))
8281 {
8282 specs[count++] = tmpl;
8283 }
8284 }
800eeca4 8285 else if (note == 8)
542d6675
KH		 8286 {
8287 int min = dep->regindex == PSR_DFL ? 2 : 32;
8288 int max = dep->regindex == PSR_DFL ? 31 : 127;
8289 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8290 for (i = 0; i < NELEMS (idesc->operands); i++)
8291 {
8292 if (idesc->operands[i] == IA64_OPND_F1
8293 || idesc->operands[i] == IA64_OPND_F2
8294 || idesc->operands[i] == IA64_OPND_F3
8295 || idesc->operands[i] == IA64_OPND_F4)
8296 {
8297 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8298 if (reg >= min && reg <= max)
8299 {
8300 specs[count++] = tmpl;
8301 }
8302 }
8303 }
8304 }
800eeca4 8305 else if (note == 9)
542d6675
KH		 8306 {
8307 int min = dep->regindex == PSR_MFL ? 2 : 32;
8308 int max = dep->regindex == PSR_MFL ? 31 : 127;
8309 /* mfh is read on writes to FR32-127; mfl is read on writes to
8310 FR2-31 */
8311 for (i = 0; i < idesc->num_outputs; i++)
8312 {
8313 if (idesc->operands[i] == IA64_OPND_F1)
8314 {
8315 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8316 if (reg >= min && reg <= max)
8317 {
8318 specs[count++] = tmpl;
8319 }
8320 }
8321 }
8322 }
800eeca4 8323 else if (note == 10)
542d6675
KH		 8324 {
8325 for (i = 0; i < NELEMS (idesc->operands); i++)
8326 {
8327 if (idesc->operands[i] == IA64_OPND_R1
8328 || idesc->operands[i] == IA64_OPND_R2
8329 || idesc->operands[i] == IA64_OPND_R3)
8330 {
8331 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8332 if (regno >= 16 && regno <= 31)
8333 {
8334 specs[count++] = tmpl;
8335 }
8336 }
8337 }
8338 }
800eeca4 8339 else
542d6675
KH		 8340 {
8341 UNHANDLED;
8342 }
800eeca4
JW		 8343 break;
8344
8345 case IA64_RS_AR_FPSR:
8346 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
542d6675
KH		 8347 {
8348 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8349 if (regno == AR_FPSR)
8350 {
8351 specs[count++] = tmpl;
8352 }
8353 }
800eeca4 8354 else
542d6675
KH		 8355 {
8356 specs[count++] = tmpl;
8357 }
800eeca4
JW		 8358 break;
8359
197865e8 8360 case IA64_RS_ARX:
800eeca4
JW		 8361 /* Handle all AR[REG] resources */
8362 if (note == 0 || note == 1)
542d6675
KH		 8363 {
8364 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8365 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
8366 && regno == dep->regindex)
8367 {
8368 specs[count++] = tmpl;
8369 }
8370 /* other AR[REG] resources may be affected by AR accesses */
8371 else if (idesc->operands[0] == IA64_OPND_AR3)
8372 {
8373 /* AR[] writes */
8374 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
8375 switch (dep->regindex)
8376 {
8377 default:
8378 break;
8379 case AR_BSP:
8380 case AR_RNAT:
8381 if (regno == AR_BSPSTORE)
8382 {
8383 specs[count++] = tmpl;
8384 }
8385 case AR_RSC:
8386 if (!rsrc_write &&
8387 (regno == AR_BSPSTORE
8388 || regno == AR_RNAT))
8389 {
8390 specs[count++] = tmpl;
8391 }
8392 break;
8393 }
8394 }
8395 else if (idesc->operands[1] == IA64_OPND_AR3)
8396 {
8397 /* AR[] reads */
8398 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
8399 switch (dep->regindex)
8400 {
8401 default:
8402 break;
8403 case AR_RSC:
8404 if (regno == AR_BSPSTORE || regno == AR_RNAT)
8405 {
8406 specs[count++] = tmpl;
8407 }
8408 break;
8409 }
8410 }
8411 else
8412 {
8413 specs[count++] = tmpl;
8414 }
8415 }
800eeca4 8416 else
542d6675
KH		 8417 {
8418 UNHANDLED;
8419 }
800eeca4
JW		 8420 break;
8421
8422 case IA64_RS_CRX:
8423 /* Handle all CR[REG] resources */
8424 if (note == 0 || note == 1)
542d6675
KH		 8425 {
8426 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
8427 {
8428 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
8429 if (regno == dep->regindex)
8430 {
8431 specs[count++] = tmpl;
8432 }
8433 else if (!rsrc_write)
8434 {
8435 /* Reads from CR[IVR] affect other resources. */
8436 if (regno == CR_IVR)
8437 {
8438 if ((dep->regindex >= CR_IRR0
8439 && dep->regindex <= CR_IRR3)
8440 || dep->regindex == CR_TPR)
8441 {
8442 specs[count++] = tmpl;
8443 }
8444 }
8445 }
8446 }
8447 else
8448 {
8449 specs[count++] = tmpl;
8450 }
8451 }
800eeca4 8452 else
542d6675
KH		 8453 {
8454 UNHANDLED;
8455 }
800eeca4
JW		 8456 break;
8457
8458 case IA64_RS_INSERVICE:
8459 /* look for write of EOI (67) or read of IVR (65) */
8460 if ((idesc->operands[0] == IA64_OPND_CR3
542d6675
KH		 8461 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
8462 || (idesc->operands[1] == IA64_OPND_CR3
8463 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
8464 {
8465 specs[count++] = tmpl;
8466 }
800eeca4
JW		 8467 break;
8468
8469 case IA64_RS_GR0:
8470 if (note == 1)
542d6675
KH		 8471 {
8472 specs[count++] = tmpl;
8473 }
800eeca4 8474 else
542d6675
KH		 8475 {
8476 UNHANDLED;
8477 }
800eeca4
JW		 8478 break;
8479
8480 case IA64_RS_CFM:
8481 if (note != 2)
542d6675
KH		 8482 {
8483 specs[count++] = tmpl;
8484 }
800eeca4 8485 else
542d6675
KH		 8486 {
8487 /* Check if any of the registers accessed are in the rotating region.
8488 mov to/from pr accesses CFM only when qp_regno is in the rotating
8489 region */
8490 for (i = 0; i < NELEMS (idesc->operands); i++)
8491 {
8492 if (idesc->operands[i] == IA64_OPND_R1
8493 || idesc->operands[i] == IA64_OPND_R2
8494 || idesc->operands[i] == IA64_OPND_R3)
8495 {
8496 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8497 /* Assumes that md.rot.num_regs is always valid */
8498 if (md.rot.num_regs > 0
8499 && num > 31
8500 && num < 31 + md.rot.num_regs)
8501 {
8502 specs[count] = tmpl;
8503 specs[count++].specific = 0;
8504 }
8505 }
8506 else if (idesc->operands[i] == IA64_OPND_F1
8507 || idesc->operands[i] == IA64_OPND_F2
8508 || idesc->operands[i] == IA64_OPND_F3
8509 || idesc->operands[i] == IA64_OPND_F4)
8510 {
8511 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8512 if (num > 31)
8513 {
8514 specs[count] = tmpl;
8515 specs[count++].specific = 0;
8516 }
8517 }
8518 else if (idesc->operands[i] == IA64_OPND_P1
8519 || idesc->operands[i] == IA64_OPND_P2)
8520 {
8521 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
8522 if (num > 15)
8523 {
8524 specs[count] = tmpl;
8525 specs[count++].specific = 0;
8526 }
8527 }
8528 }
8529 if (CURR_SLOT.qp_regno > 15)
8530 {
8531 specs[count] = tmpl;
8532 specs[count++].specific = 0;
8533 }
8534 }
800eeca4
JW		 8535 break;
8536
139368c9
JW		 8537 /* This is the same as IA64_RS_PRr, except simplified to account for
8538 the fact that there is only one register. */
800eeca4
JW		 8539 case IA64_RS_PR63:
8540 if (note == 0)
542d6675
KH		 8541 {
8542 specs[count++] = tmpl;
8543 }
139368c9 8544 else if (note == 7)
40449e9f
KH		 8545 {
8546 valueT mask = 0;
8547 if (idesc->operands[2] == IA64_OPND_IMM17)
8548 mask = CURR_SLOT.opnd[2].X_add_number;
8549 if (mask & ((valueT) 1 << 63))
139368c9 8550 specs[count++] = tmpl;
40449e9f 8551 }
800eeca4 8552 else if (note == 11)
542d6675
KH		 8553 {
8554 if ((idesc->operands[0] == IA64_OPND_P1
8555 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
8556 || (idesc->operands[1] == IA64_OPND_P2
8557 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
8558 {
8559 specs[count++] = tmpl;
8560 }
8561 }
800eeca4 8562 else if (note == 12)
542d6675
KH		 8563 {
8564 if (CURR_SLOT.qp_regno == 63)
8565 {
8566 specs[count++] = tmpl;
8567 }
8568 }
800eeca4 8569 else if (note == 1)
542d6675
KH		 8570 {
8571 if (rsrc_write)
8572 {
40449e9f
KH		 8573 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8574 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
07726851
KH		 8575 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
8576 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
7484b8e6 8577
4a4f25cf 8578 if (p1 == 63
7484b8e6
TW		 8579 && (idesc->operands[0] == IA64_OPND_P1
8580 || idesc->operands[0] == IA64_OPND_P2))
8581 {
40449e9f 8582 specs[count] = tmpl;
4a4f25cf 8583 specs[count++].cmp_type =
7484b8e6
TW		 8584 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8585 }
8586 if (p2 == 63
8587 && (idesc->operands[1] == IA64_OPND_P1
8588 || idesc->operands[1] == IA64_OPND_P2))
8589 {
40449e9f 8590 specs[count] = tmpl;
4a4f25cf 8591 specs[count++].cmp_type =
7484b8e6
TW		 8592 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8593 }
542d6675
KH		 8594 }
8595 else
8596 {
8597 if (CURR_SLOT.qp_regno == 63)
8598 {
8599 specs[count++] = tmpl;
8600 }
8601 }
8602 }
800eeca4 8603 else
542d6675
KH		 8604 {
8605 UNHANDLED;
8606 }
800eeca4
JW		 8607 break;
8608
8609 case IA64_RS_RSE:
8610 /* FIXME we can identify some individual RSE written resources, but RSE
542d6675
KH		 8611 read resources have not yet been completely identified, so for now
8612 treat RSE as a single resource */
800eeca4 8613 if (strncmp (idesc->name, "mov", 3) == 0)
542d6675
KH		 8614 {
8615 if (rsrc_write)
8616 {
8617 if (idesc->operands[0] == IA64_OPND_AR3
8618 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
8619 {
8620 specs[count] = tmpl;
8621 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8622 }
8623 }
8624 else
8625 {
8626 if (idesc->operands[0] == IA64_OPND_AR3)
8627 {
8628 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
8629 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
8630 {
8631 specs[count++] = tmpl;
8632 }
8633 }
8634 else if (idesc->operands[1] == IA64_OPND_AR3)
8635 {
8636 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
8637 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
8638 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
8639 {
8640 specs[count++] = tmpl;
8641 }
8642 }
8643 }
8644 }
197865e8 8645 else
542d6675
KH		 8646 {
8647 specs[count++] = tmpl;
8648 }
800eeca4
JW		 8649 break;
8650
8651 case IA64_RS_ANY:
8652 /* FIXME -- do any of these need to be non-specific? */
8653 specs[count++] = tmpl;
8654 break;
8655
8656 default:
8657 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
8658 break;
8659 }
8660
8661 return count;
8662}
8663
8664/* Clear branch flags on marked resources. This breaks the link between the
542d6675
KH		 8665 QP of the marking instruction and a subsequent branch on the same QP. */
8666
800eeca4
JW		 8667static void
8668clear_qp_branch_flag (mask)
542d6675 8669 valueT mask;
800eeca4
JW		 8670{
8671 int i;
542d6675 8672 for (i = 0; i < regdepslen; i++)
800eeca4 8673 {
197865e8 8674 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
800eeca4 8675 if ((bit & mask) != 0)
542d6675
KH		 8676 {
8677 regdeps[i].link_to_qp_branch = 0;
8678 }
800eeca4
JW		 8679 }
8680}
8681
197865e8 8682/* Remove any mutexes which contain any of the PRs indicated in the mask.
800eeca4 8683
542d6675
KH		 8684 Any changes to a PR clears the mutex relations which include that PR. */
8685
800eeca4
JW		 8686static void
8687clear_qp_mutex (mask)
542d6675 8688 valueT mask;
800eeca4
JW		 8689{
8690 int i;
8691
8692 i = 0;
8693 while (i < qp_mutexeslen)
8694 {
8695 if ((qp_mutexes[i].prmask & mask) != 0)
542d6675
KH		 8696 {
8697 if (md.debug_dv)
8698 {
8699 fprintf (stderr, " Clearing mutex relation");
8700 print_prmask (qp_mutexes[i].prmask);
8701 fprintf (stderr, "\n");
8702 }
8703 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
8704 }
800eeca4 8705 else
542d6675 8706 ++i;
800eeca4
JW		 8707 }
8708}
8709
8710/* Clear implies relations which contain PRs in the given masks.
8711 P1_MASK indicates the source of the implies relation, while P2_MASK
542d6675
KH		 8712 indicates the implied PR. */
8713
800eeca4
JW		 8714static void
8715clear_qp_implies (p1_mask, p2_mask)
542d6675
KH		 8716 valueT p1_mask;
8717 valueT p2_mask;
800eeca4
JW		 8718{
8719 int i;
8720
8721 i = 0;
8722 while (i < qp_implieslen)
8723 {
197865e8 8724 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
542d6675
KH		 8725 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
8726 {
8727 if (md.debug_dv)
8728 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
8729 qp_implies[i].p1, qp_implies[i].p2);
8730 qp_implies[i] = qp_implies[--qp_implieslen];
8731 }
197865e8 8732 else
542d6675 8733 ++i;
800eeca4
JW		 8734 }
8735}
8736
542d6675
KH		 8737/* Add the PRs specified to the list of implied relations. */
8738
800eeca4
JW		 8739static void
8740add_qp_imply (p1, p2)
542d6675 8741 int p1, p2;
800eeca4
JW		 8742{
8743 valueT mask;
8744 valueT bit;
8745 int i;
8746
542d6675 8747 /* p0 is not meaningful here. */
800eeca4
JW		 8748 if (p1 == 0 || p2 == 0)
8749 abort ();
8750
8751 if (p1 == p2)
8752 return;
8753
542d6675
KH		 8754 /* If it exists already, ignore it. */
8755 for (i = 0; i < qp_implieslen; i++)
800eeca4 8756 {
197865e8 8757 if (qp_implies[i].p1 == p1
542d6675
KH		 8758 && qp_implies[i].p2 == p2
8759 && qp_implies[i].path == md.path
8760 && !qp_implies[i].p2_branched)
8761 return;
800eeca4
JW		 8762 }
8763
8764 if (qp_implieslen == qp_impliestotlen)
8765 {
8766 qp_impliestotlen += 20;
8767 qp_implies = (struct qp_imply *)
542d6675
KH		 8768 xrealloc ((void *) qp_implies,
8769 qp_impliestotlen * sizeof (struct qp_imply));
800eeca4
JW		 8770 }
8771 if (md.debug_dv)
8772 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
8773 qp_implies[qp_implieslen].p1 = p1;
8774 qp_implies[qp_implieslen].p2 = p2;
8775 qp_implies[qp_implieslen].path = md.path;
8776 qp_implies[qp_implieslen++].p2_branched = 0;
8777
8778 /* Add in the implied transitive relations; for everything that p2 implies,
8779 make p1 imply that, too; for everything that implies p1, make it imply p2
197865e8 8780 as well. */
542d6675 8781 for (i = 0; i < qp_implieslen; i++)
800eeca4
JW		 8782 {
8783 if (qp_implies[i].p1 == p2)
542d6675 8784 add_qp_imply (p1, qp_implies[i].p2);
800eeca4 8785 if (qp_implies[i].p2 == p1)
542d6675 8786 add_qp_imply (qp_implies[i].p1, p2);
800eeca4
JW		 8787 }
8788 /* Add in mutex relations implied by this implies relation; for each mutex
197865e8
KH		 8789 relation containing p2, duplicate it and replace p2 with p1. */
8790 bit = (valueT) 1 << p1;
8791 mask = (valueT) 1 << p2;
542d6675 8792 for (i = 0; i < qp_mutexeslen; i++)
800eeca4
JW		 8793 {
8794 if (qp_mutexes[i].prmask & mask)
542d6675 8795 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
800eeca4
JW		 8796 }
8797}
8798
800eeca4
JW		 8799/* Add the PRs specified in the mask to the mutex list; this means that only
8800 one of the PRs can be true at any time. PR0 should never be included in
8801 the mask. */
542d6675 8802
800eeca4
JW		 8803static void
8804add_qp_mutex (mask)
542d6675 8805 valueT mask;
800eeca4
JW		 8806{
8807 if (mask & 0x1)
8808 abort ();
8809
8810 if (qp_mutexeslen == qp_mutexestotlen)
8811 {
8812 qp_mutexestotlen += 20;
8813 qp_mutexes = (struct qpmutex *)
542d6675
KH		 8814 xrealloc ((void *) qp_mutexes,
8815 qp_mutexestotlen * sizeof (struct qpmutex));
800eeca4
JW		 8816 }
8817 if (md.debug_dv)
8818 {
8819 fprintf (stderr, " Registering mutex on");
8820 print_prmask (mask);
8821 fprintf (stderr, "\n");
8822 }
8823 qp_mutexes[qp_mutexeslen].path = md.path;
8824 qp_mutexes[qp_mutexeslen++].prmask = mask;
8825}
8826
cb5301b6
RH		 8827static int
8828has_suffix_p (name, suffix)
40449e9f
KH		 8829 const char *name;
8830 const char *suffix;
cb5301b6
RH		 8831{
8832 size_t namelen = strlen (name);
8833 size_t sufflen = strlen (suffix);
8834
8835 if (namelen <= sufflen)
8836 return 0;
8837 return strcmp (name + namelen - sufflen, suffix) == 0;
8838}
8839
800eeca4
JW		 8840static void
8841clear_register_values ()
8842{
8843 int i;
8844 if (md.debug_dv)
8845 fprintf (stderr, " Clearing register values\n");
542d6675 8846 for (i = 1; i < NELEMS (gr_values); i++)
800eeca4
JW		 8847 gr_values[i].known = 0;
8848}
8849
8850/* Keep track of register values/changes which affect DV tracking.
8851
8852 optimization note: should add a flag to classes of insns where otherwise we
542d6675 8853 have to examine a group of strings to identify them. */
800eeca4 8854
800eeca4
JW		 8855static void
8856note_register_values (idesc)
542d6675 8857 struct ia64_opcode *idesc;
800eeca4
JW		 8858{
8859 valueT qp_changemask = 0;
8860 int i;
8861
542d6675
KH		 8862 /* Invalidate values for registers being written to. */
8863 for (i = 0; i < idesc->num_outputs; i++)
800eeca4 8864 {
197865e8 8865 if (idesc->operands[i] == IA64_OPND_R1
542d6675
KH		 8866 || idesc->operands[i] == IA64_OPND_R2
8867 || idesc->operands[i] == IA64_OPND_R3)
8868 {
8869 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8870 if (regno > 0 && regno < NELEMS (gr_values))
8871 gr_values[regno].known = 0;
8872 }
50b81f19
JW		 8873 else if (idesc->operands[i] == IA64_OPND_R3_2)
8874 {
8875 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8876 if (regno > 0 && regno < 4)
8877 gr_values[regno].known = 0;
8878 }
197865e8 8879 else if (idesc->operands[i] == IA64_OPND_P1
542d6675
KH		 8880 || idesc->operands[i] == IA64_OPND_P2)
8881 {
8882 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8883 qp_changemask |= (valueT) 1 << regno;
8884 }
800eeca4 8885 else if (idesc->operands[i] == IA64_OPND_PR)
542d6675
KH		 8886 {
8887 if (idesc->operands[2] & (valueT) 0x10000)
8888 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
8889 else
8890 qp_changemask = idesc->operands[2];
8891 break;
8892 }
800eeca4 8893 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
542d6675
KH		 8894 {
8895 if (idesc->operands[1] & ((valueT) 1 << 43))
8896 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
8897 else
8898 qp_changemask = idesc->operands[1];
8899 qp_changemask &= ~(valueT) 0xFFFF;
8900 break;
8901 }
8902 }
8903
8904 /* Always clear qp branch flags on any PR change. */
8905 /* FIXME there may be exceptions for certain compares. */
800eeca4
JW		 8906 clear_qp_branch_flag (qp_changemask);
8907
542d6675 8908 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
800eeca4
JW		 8909 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8910 {
197865e8 8911 qp_changemask |= ~(valueT) 0xFFFF;
800eeca4 8912 if (strcmp (idesc->name, "clrrrb.pr") != 0)
542d6675
KH		 8913 {
8914 for (i = 32; i < 32 + md.rot.num_regs; i++)
8915 gr_values[i].known = 0;
8916 }
800eeca4
JW		 8917 clear_qp_mutex (qp_changemask);
8918 clear_qp_implies (qp_changemask, qp_changemask);
8919 }
542d6675
KH		 8920 /* After a call, all register values are undefined, except those marked
8921 as "safe". */
800eeca4 8922 else if (strncmp (idesc->name, "br.call", 6) == 0
542d6675 8923 || strncmp (idesc->name, "brl.call", 7) == 0)
800eeca4 8924 {
56d27c17 8925 /* FIXME keep GR values which are marked as "safe_across_calls" */
800eeca4
JW		 8926 clear_register_values ();
8927 clear_qp_mutex (~qp_safe_across_calls);
8928 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8929 clear_qp_branch_flag (~qp_safe_across_calls);
8930 }
e9718fe1 8931 else if (is_interruption_or_rfi (idesc)
542d6675 8932 || is_taken_branch (idesc))
e9718fe1
TW		 8933 {
8934 clear_register_values ();
197865e8
KH		 8935 clear_qp_mutex (~(valueT) 0);
8936 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
e9718fe1 8937 }
542d6675 8938 /* Look for mutex and implies relations. */
197865e8 8939 else if ((idesc->operands[0] == IA64_OPND_P1
542d6675
KH		 8940 || idesc->operands[0] == IA64_OPND_P2)
8941 && (idesc->operands[1] == IA64_OPND_P1
8942 || idesc->operands[1] == IA64_OPND_P2))
800eeca4
JW		 8943 {
8944 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
197865e8
KH		 8945 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8946 valueT p1mask = (valueT) 1 << p1;
8947 valueT p2mask = (valueT) 1 << p2;
800eeca4 8948
542d6675 8949 /* If one of the PRs is PR0, we can't really do anything. */
800eeca4 8950 if (p1 == 0 || p2 == 0)
542d6675
KH		 8951 {
8952 if (md.debug_dv)
8953 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8954 }
800eeca4 8955 /* In general, clear mutexes and implies which include P1 or P2,
542d6675 8956 with the following exceptions. */
cb5301b6
RH		 8957 else if (has_suffix_p (idesc->name, ".or.andcm")
8958 || has_suffix_p (idesc->name, ".and.orcm"))
542d6675
KH		 8959 {
8960 add_qp_mutex (p1mask | p2mask);
8961 clear_qp_implies (p2mask, p1mask);
8962 }
cb5301b6
RH		 8963 else if (has_suffix_p (idesc->name, ".andcm")
8964 || has_suffix_p (idesc->name, ".and"))
542d6675
KH		 8965 {
8966 clear_qp_implies (0, p1mask | p2mask);
8967 }
cb5301b6
RH		 8968 else if (has_suffix_p (idesc->name, ".orcm")
8969 || has_suffix_p (idesc->name, ".or"))
542d6675
KH		 8970 {
8971 clear_qp_mutex (p1mask | p2mask);
8972 clear_qp_implies (p1mask | p2mask, 0);
8973 }
800eeca4 8974 else
542d6675
KH		 8975 {
8976 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
cb5301b6 8977 if (has_suffix_p (idesc->name, ".unc"))
542d6675
KH		 8978 {
8979 add_qp_mutex (p1mask | p2mask);
8980 if (CURR_SLOT.qp_regno != 0)
8981 {
8982 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8983 CURR_SLOT.qp_regno);
8984 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8985 CURR_SLOT.qp_regno);
8986 }
8987 }
8988 else if (CURR_SLOT.qp_regno == 0)
8989 {
8990 add_qp_mutex (p1mask | p2mask);
8991 }
8992 else
8993 {
8994 clear_qp_mutex (p1mask | p2mask);
8995 }
8996 }
8997 }
8998 /* Look for mov imm insns into GRs. */
800eeca4 8999 else if (idesc->operands[0] == IA64_OPND_R1
542d6675
KH		 9000 && (idesc->operands[1] == IA64_OPND_IMM22
9001 || idesc->operands[1] == IA64_OPND_IMMU64)
9002 && (strcmp (idesc->name, "mov") == 0
9003 || strcmp (idesc->name, "movl") == 0))
800eeca4
JW		 9004 {
9005 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
542d6675
KH		 9006 if (regno > 0 && regno < NELEMS (gr_values))
9007 {
9008 gr_values[regno].known = 1;
9009 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
9010 gr_values[regno].path = md.path;
9011 if (md.debug_dv)
2434f565
JW		 9012 {
9013 fprintf (stderr, " Know gr%d = ", regno);
9014 fprintf_vma (stderr, gr_values[regno].value);
9015 fputs ("\n", stderr);
9016 }
542d6675 9017 }
800eeca4 9018 }
197865e8 9019 else
800eeca4
JW		 9020 {
9021 clear_qp_mutex (qp_changemask);
9022 clear_qp_implies (qp_changemask, qp_changemask);
9023 }
9024}
9025
542d6675
KH		 9026/* Return whether the given predicate registers are currently mutex. */
9027
800eeca4
JW		 9028static int
9029qp_mutex (p1, p2, path)
542d6675
KH		 9030 int p1;
9031 int p2;
9032 int path;
800eeca4
JW		 9033{
9034 int i;
9035 valueT mask;
9036
9037 if (p1 != p2)
9038 {
542d6675
KH		 9039 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
9040 for (i = 0; i < qp_mutexeslen; i++)
9041 {
9042 if (qp_mutexes[i].path >= path
9043 && (qp_mutexes[i].prmask & mask) == mask)
9044 return 1;
9045 }
800eeca4
JW		 9046 }
9047 return 0;
9048}
9049
9050/* Return whether the given resource is in the given insn's list of chks
9051 Return 1 if the conflict is absolutely determined, 2 if it's a potential
542d6675
KH		 9052 conflict. */
9053
800eeca4
JW		 9054static int
9055resources_match (rs, idesc, note, qp_regno, path)
542d6675
KH		 9056 struct rsrc *rs;
9057 struct ia64_opcode *idesc;
9058 int note;
9059 int qp_regno;
9060 int path;
800eeca4
JW		 9061{
9062 struct rsrc specs[MAX_SPECS];
9063 int count;
9064
9065 /* If the marked resource's qp_regno and the given qp_regno are mutex,
9066 we don't need to check. One exception is note 11, which indicates that
9067 target predicates are written regardless of PR[qp]. */
197865e8 9068 if (qp_mutex (rs->qp_regno, qp_regno, path)
800eeca4
JW		 9069 && note != 11)
9070 return 0;
9071
9072 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
9073 while (count-- > 0)
9074 {
9075 /* UNAT checking is a bit more specific than other resources */
9076 if (rs->dependency->specifier == IA64_RS_AR_UNAT
542d6675
KH		 9077 && specs[count].mem_offset.hint
9078 && rs->mem_offset.hint)
9079 {
9080 if (rs->mem_offset.base == specs[count].mem_offset.base)
9081 {
9082 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
9083 ((specs[count].mem_offset.offset >> 3) & 0x3F))
9084 return 1;
9085 else
9086 continue;
9087 }
9088 }
800eeca4 9089
7484b8e6 9090 /* Skip apparent PR write conflicts where both writes are an AND or both
4a4f25cf 9091 writes are an OR. */
7484b8e6 9092 if (rs->dependency->specifier == IA64_RS_PR
afa680f8 9093 || rs->dependency->specifier == IA64_RS_PRr
7484b8e6
TW		 9094 || rs->dependency->specifier == IA64_RS_PR63)
9095 {
9096 if (specs[count].cmp_type != CMP_NONE
9097 && specs[count].cmp_type == rs->cmp_type)
9098 {
9099 if (md.debug_dv)
9100 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
9101 dv_mode[rs->dependency->mode],
afa680f8 9102 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6
TW		 9103 specs[count].index : 63);
9104 continue;
9105 }
9106 if (md.debug_dv)
4a4f25cf 9107 fprintf (stderr,
7484b8e6
TW		 9108 " %s on parallel compare conflict %s vs %s on PR%d\n",
9109 dv_mode[rs->dependency->mode],
4a4f25cf 9110 dv_cmp_type[rs->cmp_type],
7484b8e6 9111 dv_cmp_type[specs[count].cmp_type],
afa680f8 9112 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6 9113 specs[count].index : 63);
4a4f25cf 9114
7484b8e6
TW		 9115 }
9116
800eeca4 9117 /* If either resource is not specific, conservatively assume a conflict
197865e8 9118 */
800eeca4 9119 if (!specs[count].specific || !rs->specific)
542d6675 9120 return 2;
800eeca4 9121 else if (specs[count].index == rs->index)
542d6675 9122 return 1;
800eeca4
JW		 9123 }
9124#if 0
9125 if (md.debug_dv)
9126 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
9127#endif
9128
9129 return 0;
9130}
9131
9132/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
9133 insert a stop to create the break. Update all resource dependencies
9134 appropriately. If QP_REGNO is non-zero, only apply the break to resources
9135 which use the same QP_REGNO and have the link_to_qp_branch flag set.
9136 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
542d6675 9137 instruction. */
800eeca4
JW		 9138
9139static void
9140insn_group_break (insert_stop, qp_regno, save_current)
542d6675
KH		 9141 int insert_stop;
9142 int qp_regno;
9143 int save_current;
800eeca4
JW		 9144{
9145 int i;
9146
9147 if (insert_stop && md.num_slots_in_use > 0)
9148 PREV_SLOT.end_of_insn_group = 1;
9149
9150 if (md.debug_dv)
9151 {
197865e8 9152 fprintf (stderr, " Insn group break%s",
542d6675 9153 (insert_stop ? " (w/stop)" : ""));
800eeca4 9154 if (qp_regno != 0)
542d6675 9155 fprintf (stderr, " effective for QP=%d", qp_regno);
800eeca4
JW		 9156 fprintf (stderr, "\n");
9157 }
9158
9159 i = 0;
9160 while (i < regdepslen)
9161 {
9162 const struct ia64_dependency *dep = regdeps[i].dependency;
9163
9164 if (qp_regno != 0
542d6675
KH		 9165 && regdeps[i].qp_regno != qp_regno)
9166 {
9167 ++i;
9168 continue;
9169 }
800eeca4
JW		 9170
9171 if (save_current
542d6675
KH		 9172 && CURR_SLOT.src_file == regdeps[i].file
9173 && CURR_SLOT.src_line == regdeps[i].line)
9174 {
9175 ++i;
9176 continue;
9177 }
800eeca4
JW		 9178
9179 /* clear dependencies which are automatically cleared by a stop, or
542d6675 9180 those that have reached the appropriate state of insn serialization */
800eeca4 9181 if (dep->semantics == IA64_DVS_IMPLIED
542d6675
KH		 9182 || dep->semantics == IA64_DVS_IMPLIEDF
9183 || regdeps[i].insn_srlz == STATE_SRLZ)
9184 {
9185 print_dependency ("Removing", i);
9186 regdeps[i] = regdeps[--regdepslen];
9187 }
800eeca4 9188 else
542d6675
KH		 9189 {
9190 if (dep->semantics == IA64_DVS_DATA
9191 || dep->semantics == IA64_DVS_INSTR
800eeca4 9192 || dep->semantics == IA64_DVS_SPECIFIC)
542d6675
KH		 9193 {
9194 if (regdeps[i].insn_srlz == STATE_NONE)
9195 regdeps[i].insn_srlz = STATE_STOP;
9196 if (regdeps[i].data_srlz == STATE_NONE)
9197 regdeps[i].data_srlz = STATE_STOP;
9198 }
9199 ++i;
9200 }
800eeca4
JW		 9201 }
9202}
9203
542d6675
KH		 9204/* Add the given resource usage spec to the list of active dependencies. */
9205
197865e8 9206static void
800eeca4 9207mark_resource (idesc, dep, spec, depind, path)
2434f565
JW		 9208 struct ia64_opcode *idesc ATTRIBUTE_UNUSED;
9209 const struct ia64_dependency *dep ATTRIBUTE_UNUSED;
542d6675
KH		 9210 struct rsrc *spec;
9211 int depind;
9212 int path;
800eeca4
JW		 9213{
9214 if (regdepslen == regdepstotlen)
9215 {
9216 regdepstotlen += 20;
9217 regdeps = (struct rsrc *)
542d6675 9218 xrealloc ((void *) regdeps,
bc805888 9219 regdepstotlen * sizeof (struct rsrc));
800eeca4
JW		 9220 }
9221
9222 regdeps[regdepslen] = *spec;
9223 regdeps[regdepslen].depind = depind;
9224 regdeps[regdepslen].path = path;
9225 regdeps[regdepslen].file = CURR_SLOT.src_file;
9226 regdeps[regdepslen].line = CURR_SLOT.src_line;
9227
9228 print_dependency ("Adding", regdepslen);
9229
9230 ++regdepslen;
9231}
9232
9233static void
9234print_dependency (action, depind)
542d6675
KH		 9235 const char *action;
9236 int depind;
800eeca4
JW		 9237{
9238 if (md.debug_dv)
9239 {
197865e8 9240 fprintf (stderr, " %s %s '%s'",
542d6675
KH		 9241 action, dv_mode[(regdeps[depind].dependency)->mode],
9242 (regdeps[depind].dependency)->name);
800eeca4 9243 if (regdeps[depind].specific && regdeps[depind].index != 0)
542d6675 9244 fprintf (stderr, " (%d)", regdeps[depind].index);
800eeca4 9245 if (regdeps[depind].mem_offset.hint)
2434f565
JW		 9246 {
9247 fputs (" ", stderr);
9248 fprintf_vma (stderr, regdeps[depind].mem_offset.base);
9249 fputs ("+", stderr);
9250 fprintf_vma (stderr, regdeps[depind].mem_offset.offset);
9251 }
800eeca4
JW		 9252 fprintf (stderr, "\n");
9253 }
9254}
9255
9256static void
9257instruction_serialization ()
9258{
9259 int i;
9260 if (md.debug_dv)
9261 fprintf (stderr, " Instruction serialization\n");
542d6675 9262 for (i = 0; i < regdepslen; i++)
800eeca4
JW		 9263 if (regdeps[i].insn_srlz == STATE_STOP)
9264 regdeps[i].insn_srlz = STATE_SRLZ;
9265}
9266
9267static void
9268data_serialization ()
9269{
9270 int i = 0;
9271 if (md.debug_dv)
9272 fprintf (stderr, " Data serialization\n");
9273 while (i < regdepslen)
9274 {
9275 if (regdeps[i].data_srlz == STATE_STOP
542d6675
KH		 9276 /* Note: as of 991210, all "other" dependencies are cleared by a
9277 data serialization. This might change with new tables */
9278 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
9279 {
9280 print_dependency ("Removing", i);
9281 regdeps[i] = regdeps[--regdepslen];
9282 }
800eeca4 9283 else
542d6675 9284 ++i;
800eeca4
JW		 9285 }
9286}
9287
542d6675
KH		 9288/* Insert stops and serializations as needed to avoid DVs. */
9289
800eeca4
JW		 9290static void
9291remove_marked_resource (rs)
542d6675 9292 struct rsrc *rs;
800eeca4
JW		 9293{
9294 switch (rs->dependency->semantics)
9295 {
9296 case IA64_DVS_SPECIFIC:
9297 if (md.debug_dv)
9298 fprintf (stderr, "Implementation-specific, assume worst case...\n");
197865e8 9299 /* ...fall through... */
800eeca4
JW		 9300 case IA64_DVS_INSTR:
9301 if (md.debug_dv)
542d6675 9302 fprintf (stderr, "Inserting instr serialization\n");
800eeca4 9303 if (rs->insn_srlz < STATE_STOP)
542d6675 9304 insn_group_break (1, 0, 0);
800eeca4 9305 if (rs->insn_srlz < STATE_SRLZ)
542d6675
KH		 9306 {
9307 int oldqp = CURR_SLOT.qp_regno;
9308 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9309 /* Manually jam a srlz.i insn into the stream */
9310 CURR_SLOT.qp_regno = 0;
9311 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
9312 instruction_serialization ();
9313 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9314 if (++md.num_slots_in_use >= NUM_SLOTS)
9315 emit_one_bundle ();
9316 CURR_SLOT.qp_regno = oldqp;
9317 CURR_SLOT.idesc = oldidesc;
9318 }
800eeca4
JW		 9319 insn_group_break (1, 0, 0);
9320 break;
9321 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
542d6675
KH		 9322 "other" types of DV are eliminated
9323 by a data serialization */
800eeca4
JW		 9324 case IA64_DVS_DATA:
9325 if (md.debug_dv)
542d6675 9326 fprintf (stderr, "Inserting data serialization\n");
800eeca4 9327 if (rs->data_srlz < STATE_STOP)
542d6675 9328 insn_group_break (1, 0, 0);
800eeca4 9329 {
542d6675
KH		 9330 int oldqp = CURR_SLOT.qp_regno;
9331 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9332 /* Manually jam a srlz.d insn into the stream */
9333 CURR_SLOT.qp_regno = 0;
9334 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
9335 data_serialization ();
9336 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9337 if (++md.num_slots_in_use >= NUM_SLOTS)
9338 emit_one_bundle ();
9339 CURR_SLOT.qp_regno = oldqp;
9340 CURR_SLOT.idesc = oldidesc;
800eeca4
JW		 9341 }
9342 break;
9343 case IA64_DVS_IMPLIED:
9344 case IA64_DVS_IMPLIEDF:
9345 if (md.debug_dv)
542d6675 9346 fprintf (stderr, "Inserting stop\n");
800eeca4
JW		 9347 insn_group_break (1, 0, 0);
9348 break;
9349 default:
9350 break;
9351 }
9352}
9353
9354/* Check the resources used by the given opcode against the current dependency
197865e8 9355 list.
800eeca4
JW		 9356
9357 The check is run once for each execution path encountered. In this case,
9358 a unique execution path is the sequence of instructions following a code
9359 entry point, e.g. the following has three execution paths, one starting
9360 at L0, one at L1, and one at L2.
197865e8 9361
800eeca4
JW		 9362 L0: nop
9363 L1: add
9364 L2: add
197865e8 9365 br.ret
800eeca4 9366*/
542d6675 9367
800eeca4
JW		 9368static void
9369check_dependencies (idesc)
542d6675 9370 struct ia64_opcode *idesc;
800eeca4
JW		 9371{
9372 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9373 int path;
9374 int i;
9375
9376 /* Note that the number of marked resources may change within the
197865e8 9377 loop if in auto mode. */
800eeca4
JW		 9378 i = 0;
9379 while (i < regdepslen)
9380 {
9381 struct rsrc *rs = &regdeps[i];
9382 const struct ia64_dependency *dep = rs->dependency;
9383 int chkind;
9384 int note;
9385 int start_over = 0;
9386
9387 if (dep->semantics == IA64_DVS_NONE
542d6675
KH		 9388 || (chkind = depends_on (rs->depind, idesc)) == -1)
9389 {
9390 ++i;
9391 continue;
9392 }
9393
9394 note = NOTE (opdeps->chks[chkind]);
9395
9396 /* Check this resource against each execution path seen thus far. */
9397 for (path = 0; path <= md.path; path++)
9398 {
9399 int matchtype;
9400
9401 /* If the dependency wasn't on the path being checked, ignore it. */
9402 if (rs->path < path)
9403 continue;
9404
9405 /* If the QP for this insn implies a QP which has branched, don't
9406 bother checking. Ed. NOTE: I don't think this check is terribly
9407 useful; what's the point of generating code which will only be
9408 reached if its QP is zero?
9409 This code was specifically inserted to handle the following code,
9410 based on notes from Intel's DV checking code, where p1 implies p2.
9411
9412 mov r4 = 2
9413 (p2) br.cond L
9414 (p1) mov r4 = 7
9415 */
9416 if (CURR_SLOT.qp_regno != 0)
9417 {
9418 int skip = 0;
9419 int implies;
9420 for (implies = 0; implies < qp_implieslen; implies++)
9421 {
9422 if (qp_implies[implies].path >= path
9423 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
9424 && qp_implies[implies].p2_branched)
9425 {
9426 skip = 1;
9427 break;
9428 }
9429 }
9430 if (skip)
9431 continue;
9432 }
9433
9434 if ((matchtype = resources_match (rs, idesc, note,
9435 CURR_SLOT.qp_regno, path)) != 0)
9436 {
9437 char msg[1024];
9438 char pathmsg[256] = "";
9439 char indexmsg[256] = "";
9440 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
9441
9442 if (path != 0)
9443 sprintf (pathmsg, " when entry is at label '%s'",
9444 md.entry_labels[path - 1]);
9445 if (rs->specific && rs->index != 0)
9446 sprintf (indexmsg, ", specific resource number is %d",
9447 rs->index);
9448 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9449 idesc->name,
9450 (certain ? "violates" : "may violate"),
9451 dv_mode[dep->mode], dep->name,
9452 dv_sem[dep->semantics],
9453 pathmsg, indexmsg);
9454
9455 if (md.explicit_mode)
9456 {
9457 as_warn ("%s", msg);
9458 if (path < md.path)
9459 as_warn (_("Only the first path encountering the conflict "
9460 "is reported"));
9461 as_warn_where (rs->file, rs->line,
9462 _("This is the location of the "
9463 "conflicting usage"));
9464 /* Don't bother checking other paths, to avoid duplicating
9465 the same warning */
9466 break;
9467 }
9468 else
9469 {
9470 if (md.debug_dv)
9471 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
9472
9473 remove_marked_resource (rs);
9474
9475 /* since the set of dependencies has changed, start over */
9476 /* FIXME -- since we're removing dvs as we go, we
9477 probably don't really need to start over... */
9478 start_over = 1;
9479 break;
9480 }
9481 }
9482 }
800eeca4 9483 if (start_over)
542d6675 9484 i = 0;
800eeca4 9485 else
542d6675 9486 ++i;
800eeca4
JW		 9487 }
9488}
9489
542d6675
KH		 9490/* Register new dependencies based on the given opcode. */
9491
800eeca4
JW		 9492static void
9493mark_resources (idesc)
542d6675 9494 struct ia64_opcode *idesc;
800eeca4
JW		 9495{
9496 int i;
9497 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9498 int add_only_qp_reads = 0;
9499
9500 /* A conditional branch only uses its resources if it is taken; if it is
9501 taken, we stop following that path. The other branch types effectively
9502 *always* write their resources. If it's not taken, register only QP
197865e8 9503 reads. */
800eeca4
JW		 9504 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
9505 {
9506 add_only_qp_reads = 1;
9507 }
9508
9509 if (md.debug_dv)
9510 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
9511
542d6675 9512 for (i = 0; i < opdeps->nregs; i++)
800eeca4
JW		 9513 {
9514 const struct ia64_dependency *dep;
9515 struct rsrc specs[MAX_SPECS];
9516 int note;
9517 int path;
9518 int count;
197865e8 9519
800eeca4 9520 dep = ia64_find_dependency (opdeps->regs[i]);
542d6675 9521 note = NOTE (opdeps->regs[i]);
800eeca4
JW		 9522
9523 if (add_only_qp_reads
542d6675
KH		 9524 && !(dep->mode == IA64_DV_WAR
9525 && (dep->specifier == IA64_RS_PR
139368c9 9526 || dep->specifier == IA64_RS_PRr
542d6675
KH		 9527 || dep->specifier == IA64_RS_PR63)))
9528 continue;
800eeca4
JW		 9529
9530 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
9531
9532#if 0
9533 if (md.debug_dv && !count)
542d6675
KH		 9534 fprintf (stderr, " No %s %s usage found (path %d)\n",
9535 dv_mode[dep->mode], dep->name, md.path);
800eeca4 9536#endif
197865e8 9537
800eeca4 9538 while (count-- > 0)
542d6675
KH		 9539 {
9540 mark_resource (idesc, dep, &specs[count],
9541 DEP (opdeps->regs[i]), md.path);
9542 }
800eeca4
JW		 9543
9544 /* The execution path may affect register values, which may in turn
542d6675 9545 affect which indirect-access resources are accessed. */
800eeca4 9546 switch (dep->specifier)
542d6675
KH		 9547 {
9548 default:
9549 break;
9550 case IA64_RS_CPUID:
9551 case IA64_RS_DBR:
9552 case IA64_RS_IBR:
800eeca4 9553 case IA64_RS_MSR:
542d6675
KH		 9554 case IA64_RS_PKR:
9555 case IA64_RS_PMC:
9556 case IA64_RS_PMD:
9557 case IA64_RS_RR:
9558 for (path = 0; path < md.path; path++)
9559 {
9560 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
9561 while (count-- > 0)
9562 mark_resource (idesc, dep, &specs[count],
9563 DEP (opdeps->regs[i]), path);
9564 }
9565 break;
9566 }
9567 }
9568}
9569
9570/* Remove dependencies when they no longer apply. */
9571
800eeca4
JW		 9572static void
9573update_dependencies (idesc)
542d6675 9574 struct ia64_opcode *idesc;
800eeca4
JW		 9575{
9576 int i;
9577
9578 if (strcmp (idesc->name, "srlz.i") == 0)
9579 {
9580 instruction_serialization ();
9581 }
9582 else if (strcmp (idesc->name, "srlz.d") == 0)
9583 {
9584 data_serialization ();
9585 }
9586 else if (is_interruption_or_rfi (idesc)
542d6675 9587 || is_taken_branch (idesc))
800eeca4 9588 {
542d6675
KH		 9589 /* Although technically the taken branch doesn't clear dependencies
9590 which require a srlz.[id], we don't follow the branch; the next
9591 instruction is assumed to start with a clean slate. */
800eeca4 9592 regdepslen = 0;
800eeca4
JW		 9593 md.path = 0;
9594 }
9595 else if (is_conditional_branch (idesc)
542d6675 9596 && CURR_SLOT.qp_regno != 0)
800eeca4
JW		 9597 {
9598 int is_call = strstr (idesc->name, ".call") != NULL;
9599
542d6675
KH		 9600 for (i = 0; i < qp_implieslen; i++)
9601 {
9602 /* If the conditional branch's predicate is implied by the predicate
9603 in an existing dependency, remove that dependency. */
9604 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
9605 {
9606 int depind = 0;
9607 /* Note that this implied predicate takes a branch so that if
9608 a later insn generates a DV but its predicate implies this
9609 one, we can avoid the false DV warning. */
9610 qp_implies[i].p2_branched = 1;
9611 while (depind < regdepslen)
9612 {
9613 if (regdeps[depind].qp_regno == qp_implies[i].p1)
9614 {
9615 print_dependency ("Removing", depind);
9616 regdeps[depind] = regdeps[--regdepslen];
9617 }
9618 else
9619 ++depind;
9620 }
9621 }
9622 }
800eeca4 9623 /* Any marked resources which have this same predicate should be
542d6675
KH		 9624 cleared, provided that the QP hasn't been modified between the
9625 marking instruction and the branch. */
800eeca4 9626 if (is_call)
542d6675
KH		 9627 {
9628 insn_group_break (0, CURR_SLOT.qp_regno, 1);
9629 }
800eeca4 9630 else
542d6675
KH		 9631 {
9632 i = 0;
9633 while (i < regdepslen)
9634 {
9635 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
9636 && regdeps[i].link_to_qp_branch
9637 && (regdeps[i].file != CURR_SLOT.src_file
9638 || regdeps[i].line != CURR_SLOT.src_line))
9639 {
9640 /* Treat like a taken branch */
9641 print_dependency ("Removing", i);
9642 regdeps[i] = regdeps[--regdepslen];
9643 }
9644 else
9645 ++i;
9646 }
9647 }
800eeca4
JW		 9648 }
9649}
9650
9651/* Examine the current instruction for dependency violations. */
542d6675 9652
800eeca4
JW		 9653static int
9654check_dv (idesc)
542d6675 9655 struct ia64_opcode *idesc;
800eeca4
JW		 9656{
9657 if (md.debug_dv)
9658 {
197865e8 9659 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
542d6675
KH		 9660 idesc->name, CURR_SLOT.src_line,
9661 idesc->dependencies->nchks,
9662 idesc->dependencies->nregs);
800eeca4
JW		 9663 }
9664
197865e8 9665 /* Look through the list of currently marked resources; if the current
800eeca4 9666 instruction has the dependency in its chks list which uses that resource,
542d6675 9667 check against the specific resources used. */
800eeca4
JW		 9668 check_dependencies (idesc);
9669
542d6675
KH		 9670 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9671 then add them to the list of marked resources. */
800eeca4
JW		 9672 mark_resources (idesc);
9673
9674 /* There are several types of dependency semantics, and each has its own
197865e8
KH		 9675 requirements for being cleared
9676
800eeca4
JW		 9677 Instruction serialization (insns separated by interruption, rfi, or
9678 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9679
9680 Data serialization (instruction serialization, or writer + srlz.d +
9681 reader, where writer and srlz.d are in separate groups) clears
9682 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9683 always be the case).
9684
9685 Instruction group break (groups separated by stop, taken branch,
9686 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9687 */
9688 update_dependencies (idesc);
9689
9690 /* Sometimes, knowing a register value allows us to avoid giving a false DV
197865e8 9691 warning. Keep track of as many as possible that are useful. */
800eeca4
JW		 9692 note_register_values (idesc);
9693
197865e8 9694 /* We don't need or want this anymore. */
800eeca4
JW		 9695 md.mem_offset.hint = 0;
9696
9697 return 0;
9698}
9699
9700/* Translate one line of assembly. Pseudo ops and labels do not show
9701 here. */
9702void
9703md_assemble (str)
9704 char *str;
9705{
9706 char *saved_input_line_pointer, *mnemonic;
9707 const struct pseudo_opcode *pdesc;
9708 struct ia64_opcode *idesc;
9709 unsigned char qp_regno;
9710 unsigned int flags;
9711 int ch;
9712
9713 saved_input_line_pointer = input_line_pointer;
9714 input_line_pointer = str;
9715
542d6675 9716 /* extract the opcode (mnemonic): */
800eeca4
JW		 9717
9718 mnemonic = input_line_pointer;
9719 ch = get_symbol_end ();
9720 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
9721 if (pdesc)
9722 {
9723 *input_line_pointer = ch;
9724 (*pdesc->handler) (pdesc->arg);
9725 goto done;
9726 }
9727
542d6675 9728 /* Find the instruction descriptor matching the arguments. */
800eeca4
JW		 9729
9730 idesc = ia64_find_opcode (mnemonic);
9731 *input_line_pointer = ch;
9732 if (!idesc)
9733 {
9734 as_bad ("Unknown opcode `%s'", mnemonic);
9735 goto done;
9736 }
9737
9738 idesc = parse_operands (idesc);
9739 if (!idesc)
9740 goto done;
9741
542d6675 9742 /* Handle the dynamic ops we can handle now: */
800eeca4
JW		 9743 if (idesc->type == IA64_TYPE_DYN)
9744 {
9745 if (strcmp (idesc->name, "add") == 0)
9746 {
9747 if (CURR_SLOT.opnd[2].X_op == O_register
9748 && CURR_SLOT.opnd[2].X_add_number < 4)
9749 mnemonic = "addl";
9750 else
9751 mnemonic = "adds";
3d56ab85 9752 ia64_free_opcode (idesc);
800eeca4
JW		 9753 idesc = ia64_find_opcode (mnemonic);
9754#if 0
9755 know (!idesc->next);
9756#endif
9757 }
9758 else if (strcmp (idesc->name, "mov") == 0)
9759 {
9760 enum ia64_opnd opnd1, opnd2;
9761 int rop;
9762
9763 opnd1 = idesc->operands[0];
9764 opnd2 = idesc->operands[1];
9765 if (opnd1 == IA64_OPND_AR3)
9766 rop = 0;
9767 else if (opnd2 == IA64_OPND_AR3)
9768 rop = 1;
9769 else
9770 abort ();
9771 if (CURR_SLOT.opnd[rop].X_op == O_register
9772 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
9773 mnemonic = "mov.i";
9774 else
9775 mnemonic = "mov.m";
3d56ab85 9776 ia64_free_opcode (idesc);
800eeca4
JW		 9777 idesc = ia64_find_opcode (mnemonic);
9778 while (idesc != NULL
9779 && (idesc->operands[0] != opnd1
9780 || idesc->operands[1] != opnd2))
9781 idesc = get_next_opcode (idesc);
9782 }
9783 }
9784
9785 qp_regno = 0;
9786 if (md.qp.X_op == O_register)
f1bcba5b
JW		 9787 {
9788 qp_regno = md.qp.X_add_number - REG_P;
9789 md.qp.X_op = O_absent;
9790 }
800eeca4
JW		 9791
9792 flags = idesc->flags;
9793
9794 if ((flags & IA64_OPCODE_FIRST) != 0)
9795 insn_group_break (1, 0, 0);
9796
9797 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
9798 {
9799 as_bad ("`%s' cannot be predicated", idesc->name);
9800 goto done;
9801 }
9802
542d6675 9803 /* Build the instruction. */
800eeca4
JW		 9804 CURR_SLOT.qp_regno = qp_regno;
9805 CURR_SLOT.idesc = idesc;
9806 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
4dc7ead9 9807 dwarf2_where (&CURR_SLOT.debug_line);
800eeca4
JW		 9808
9809 /* Add unwind entry, if there is one. */
e0c9811a 9810 if (unwind.current_entry)
800eeca4 9811 {
e0c9811a
JW		 9812 CURR_SLOT.unwind_record = unwind.current_entry;
9813 unwind.current_entry = NULL;
800eeca4
JW		 9814 }
9815
542d6675 9816 /* Check for dependency violations. */
800eeca4 9817 if (md.detect_dv)
542d6675 9818 check_dv (idesc);
800eeca4
JW		 9819
9820 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9821 if (++md.num_slots_in_use >= NUM_SLOTS)
9822 emit_one_bundle ();
9823
9824 if ((flags & IA64_OPCODE_LAST) != 0)
9825 insn_group_break (1, 0, 0);
9826
9827 md.last_text_seg = now_seg;
9828
9829 done:
9830 input_line_pointer = saved_input_line_pointer;
9831}
9832
9833/* Called when symbol NAME cannot be found in the symbol table.
9834 Should be used for dynamic valued symbols only. */
542d6675
KH		 9835
9836symbolS *
800eeca4 9837md_undefined_symbol (name)
2434f565 9838 char *name ATTRIBUTE_UNUSED;
800eeca4
JW		 9839{
9840 return 0;
9841}
9842
9843/* Called for any expression that can not be recognized. When the
9844 function is called, `input_line_pointer' will point to the start of
9845 the expression. */
542d6675 9846
800eeca4
JW		 9847void
9848md_operand (e)
9849 expressionS *e;
9850{
9851 enum pseudo_type pseudo_type;
e0c9811a 9852 const char *name;
800eeca4
JW		 9853 size_t len;
9854 int ch, i;
9855
9856 switch (*input_line_pointer)
9857 {
9858 case '@':
542d6675 9859 /* Find what relocation pseudo-function we're dealing with. */
800eeca4
JW		 9860 pseudo_type = 0;
9861 ch = *++input_line_pointer;
9862 for (i = 0; i < NELEMS (pseudo_func); ++i)
9863 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
9864 {
9865 len = strlen (pseudo_func[i].name);
9866 if (strncmp (pseudo_func[i].name + 1,
9867 input_line_pointer + 1, len - 1) == 0
9868 && !is_part_of_name (input_line_pointer[len]))
9869 {
9870 input_line_pointer += len;
9871 pseudo_type = pseudo_func[i].type;
9872 break;
9873 }
9874 }
9875 switch (pseudo_type)
9876 {
9877 case PSEUDO_FUNC_RELOC:
9878 SKIP_WHITESPACE ();
9879 if (*input_line_pointer != '(')
9880 {
9881 as_bad ("Expected '('");
9882 goto err;
9883 }
542d6675
KH		 9884 /* Skip '('. */
9885 ++input_line_pointer;
800eeca4
JW		 9886 expression (e);
9887 if (*input_line_pointer++ != ')')
9888 {
9889 as_bad ("Missing ')'");
9890 goto err;
9891 }
9892 if (e->X_op != O_symbol)
9893 {
9894 if (e->X_op != O_pseudo_fixup)
9895 {
9896 as_bad ("Not a symbolic expression");
9897 goto err;
9898 }
13ae64f3
JJ		 9899 if (i != FUNC_LT_RELATIVE)
9900 {
9901 as_bad ("Illegal combination of relocation functions");
9902 goto err;
9903 }
9904 switch (S_GET_VALUE (e->X_op_symbol))
800eeca4 9905 {
13ae64f3
JJ		 9906 case FUNC_FPTR_RELATIVE:
9907 i = FUNC_LT_FPTR_RELATIVE; break;
9908 case FUNC_DTP_MODULE:
9909 i = FUNC_LT_DTP_MODULE; break;
9910 case FUNC_DTP_RELATIVE:
9911 i = FUNC_LT_DTP_RELATIVE; break;
9912 case FUNC_TP_RELATIVE:
9913 i = FUNC_LT_TP_RELATIVE; break;
9914 default:
800eeca4
JW		 9915 as_bad ("Illegal combination of relocation functions");
9916 goto err;
9917 }
9918 }
542d6675
KH		 9919 /* Make sure gas doesn't get rid of local symbols that are used
9920 in relocs. */
800eeca4
JW		 9921 e->X_op = O_pseudo_fixup;
9922 e->X_op_symbol = pseudo_func[i].u.sym;
9923 break;
9924
9925 case PSEUDO_FUNC_CONST:
9926 e->X_op = O_constant;
9927 e->X_add_number = pseudo_func[i].u.ival;
9928 break;
9929
e0c9811a
JW		 9930 case PSEUDO_FUNC_REG:
9931 e->X_op = O_register;
9932 e->X_add_number = pseudo_func[i].u.ival;
9933 break;
9934
800eeca4 9935 default:
e0c9811a
JW		 9936 name = input_line_pointer - 1;
9937 get_symbol_end ();
9938 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW		 9939 goto err;
9940 }
9941 break;
9942
9943 case '[':
9944 ++input_line_pointer;
9945 expression (e);
9946 if (*input_line_pointer != ']')
9947 {
9948 as_bad ("Closing bracket misssing");
9949 goto err;
9950 }
9951 else
9952 {
9953 if (e->X_op != O_register)
9954 as_bad ("Register expected as index");
9955
9956 ++input_line_pointer;
9957 e->X_op = O_index;
9958 }
9959 break;
9960
9961 default:
9962 break;
9963 }
9964 return;
9965
9966 err:
9967 ignore_rest_of_line ();
9968}
9969
9970/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9971 a section symbol plus some offset. For relocs involving @fptr(),
9972 directives we don't want such adjustments since we need to have the
9973 original symbol's name in the reloc. */
9974int
9975ia64_fix_adjustable (fix)
9976 fixS *fix;
9977{
9978 /* Prevent all adjustments to global symbols */
9979 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9980 return 0;
9981
9982 switch (fix->fx_r_type)
9983 {
9984 case BFD_RELOC_IA64_FPTR64I:
9985 case BFD_RELOC_IA64_FPTR32MSB:
9986 case BFD_RELOC_IA64_FPTR32LSB:
9987 case BFD_RELOC_IA64_FPTR64MSB:
9988 case BFD_RELOC_IA64_FPTR64LSB:
9989 case BFD_RELOC_IA64_LTOFF_FPTR22:
9990 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9991 return 0;
9992 default:
9993 break;
9994 }
9995
9996 return 1;
9997}
9998
9999int
10000ia64_force_relocation (fix)
10001 fixS *fix;
10002{
10003 switch (fix->fx_r_type)
10004 {
10005 case BFD_RELOC_IA64_FPTR64I:
10006 case BFD_RELOC_IA64_FPTR32MSB:
10007 case BFD_RELOC_IA64_FPTR32LSB:
10008 case BFD_RELOC_IA64_FPTR64MSB:
10009 case BFD_RELOC_IA64_FPTR64LSB:
10010
10011 case BFD_RELOC_IA64_LTOFF22:
10012 case BFD_RELOC_IA64_LTOFF64I:
10013 case BFD_RELOC_IA64_LTOFF_FPTR22:
10014 case BFD_RELOC_IA64_LTOFF_FPTR64I:
10015 case BFD_RELOC_IA64_PLTOFF22:
10016 case BFD_RELOC_IA64_PLTOFF64I:
10017 case BFD_RELOC_IA64_PLTOFF64MSB:
10018 case BFD_RELOC_IA64_PLTOFF64LSB:
fa2c7eff
RH		 10019
10020 case BFD_RELOC_IA64_LTOFF22X:
10021 case BFD_RELOC_IA64_LDXMOV:
800eeca4
JW		 10022 return 1;
10023
10024 default:
a161fe53 10025 break;
800eeca4 10026 }
a161fe53 10027
ae6063d4 10028 return generic_force_reloc (fix);
800eeca4
JW		 10029}
10030
10031/* Decide from what point a pc-relative relocation is relative to,
10032 relative to the pc-relative fixup. Er, relatively speaking. */
10033long
10034ia64_pcrel_from_section (fix, sec)
10035 fixS *fix;
10036 segT sec;
10037{
10038 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
197865e8 10039
800eeca4
JW		 10040 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
10041 off &= ~0xfUL;
10042
10043 return off;
10044}
10045
6174d9c8
RH		 10046
10047/* Used to emit section-relative relocs for the dwarf2 debug data. */
10048void
10049ia64_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10050{
10051 expressionS expr;
10052
10053 expr.X_op = O_pseudo_fixup;
10054 expr.X_op_symbol = pseudo_func[FUNC_SEC_RELATIVE].u.sym;
10055 expr.X_add_number = 0;
10056 expr.X_add_symbol = symbol;
10057 emit_expr (&expr, size);
10058}
10059
800eeca4
JW		 10060/* This is called whenever some data item (not an instruction) needs a
10061 fixup. We pick the right reloc code depending on the byteorder
10062 currently in effect. */
10063void
10064ia64_cons_fix_new (f, where, nbytes, exp)
10065 fragS *f;
10066 int where;
10067 int nbytes;
10068 expressionS *exp;
10069{
10070 bfd_reloc_code_real_type code;
10071 fixS *fix;
10072
10073 switch (nbytes)
10074 {
10075 /* There are no reloc for 8 and 16 bit quantities, but we allow
10076 them here since they will work fine as long as the expression
10077 is fully defined at the end of the pass over the source file. */
10078 case 1: code = BFD_RELOC_8; break;
10079 case 2: code = BFD_RELOC_16; break;
10080 case 4:
10081 if (target_big_endian)
10082 code = BFD_RELOC_IA64_DIR32MSB;
10083 else
10084 code = BFD_RELOC_IA64_DIR32LSB;
10085 break;
10086
10087 case 8:
40449e9f 10088 /* In 32-bit mode, data8 could mean function descriptors too. */
5f44c186 10089 if (exp->X_op == O_pseudo_fixup
40449e9f
KH		 10090 && exp->X_op_symbol
10091 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC
10092 && !(md.flags & EF_IA_64_ABI64))
10093 {
10094 if (target_big_endian)
10095 code = BFD_RELOC_IA64_IPLTMSB;
10096 else
10097 code = BFD_RELOC_IA64_IPLTLSB;
10098 exp->X_op = O_symbol;
10099 break;
10100 }
10101 else
10102 {
10103 if (target_big_endian)
10104 code = BFD_RELOC_IA64_DIR64MSB;
10105 else
10106 code = BFD_RELOC_IA64_DIR64LSB;
10107 break;
10108 }
800eeca4 10109
3969b680
RH		 10110 case 16:
10111 if (exp->X_op == O_pseudo_fixup
10112 && exp->X_op_symbol
10113 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC)
10114 {
10115 if (target_big_endian)
10116 code = BFD_RELOC_IA64_IPLTMSB;
10117 else
10118 code = BFD_RELOC_IA64_IPLTLSB;
3969b680
RH		 10119 exp->X_op = O_symbol;
10120 break;
10121 }
10122 /* FALLTHRU */
10123
800eeca4
JW		 10124 default:
10125 as_bad ("Unsupported fixup size %d", nbytes);
10126 ignore_rest_of_line ();
10127 return;
10128 }
6174d9c8 10129
800eeca4
JW		 10130 if (exp->X_op == O_pseudo_fixup)
10131 {
800eeca4
JW		 10132 exp->X_op = O_symbol;
10133 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
6174d9c8 10134 /* ??? If code unchanged, unsupported. */
800eeca4 10135 }
3969b680 10136
800eeca4
JW		 10137 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
10138 /* We need to store the byte order in effect in case we're going
10139 to fix an 8 or 16 bit relocation (for which there no real
94f592af 10140 relocs available). See md_apply_fix3(). */
800eeca4
JW		 10141 fix->tc_fix_data.bigendian = target_big_endian;
10142}
10143
10144/* Return the actual relocation we wish to associate with the pseudo
10145 reloc described by SYM and R_TYPE. SYM should be one of the
197865e8 10146 symbols in the pseudo_func array, or NULL. */
800eeca4
JW		 10147
10148static bfd_reloc_code_real_type
10149ia64_gen_real_reloc_type (sym, r_type)
10150 struct symbol *sym;
10151 bfd_reloc_code_real_type r_type;
10152{
10153 bfd_reloc_code_real_type new = 0;
10154
10155 if (sym == NULL)
10156 {
10157 return r_type;
10158 }
10159
10160 switch (S_GET_VALUE (sym))
10161 {
10162 case FUNC_FPTR_RELATIVE:
10163 switch (r_type)
10164 {
10165 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
10166 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
10167 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
10168 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
10169 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
10170 default: break;
10171 }
10172 break;
10173
10174 case FUNC_GP_RELATIVE:
10175 switch (r_type)
10176 {
10177 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
10178 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
10179 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
10180 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
10181 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
10182 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
10183 default: break;
10184 }
10185 break;
10186
10187 case FUNC_LT_RELATIVE:
10188 switch (r_type)
10189 {
10190 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
10191 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
10192 default: break;
10193 }
10194 break;
10195
fa2c7eff
RH		 10196 case FUNC_LT_RELATIVE_X:
10197 switch (r_type)
10198 {
10199 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22X; break;
10200 default: break;
10201 }
10202 break;
10203
c67e42c9
RH		 10204 case FUNC_PC_RELATIVE:
10205 switch (r_type)
10206 {
10207 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
10208 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
10209 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
10210 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
10211 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
10212 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
10213 default: break;
10214 }
10215 break;
10216
800eeca4
JW		 10217 case FUNC_PLT_RELATIVE:
10218 switch (r_type)
10219 {
10220 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
10221 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
10222 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
10223 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
10224 default: break;
10225 }
10226 break;
10227
10228 case FUNC_SEC_RELATIVE:
10229 switch (r_type)
10230 {
10231 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
10232 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
10233 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
10234 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
10235 default: break;
10236 }
10237 break;
10238
10239 case FUNC_SEG_RELATIVE:
10240 switch (r_type)
10241 {
10242 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
10243 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
10244 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
10245 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
10246 default: break;
10247 }
10248 break;
10249
10250 case FUNC_LTV_RELATIVE:
10251 switch (r_type)
10252 {
10253 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
10254 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
10255 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
10256 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
10257 default: break;
10258 }
10259 break;
10260
10261 case FUNC_LT_FPTR_RELATIVE:
10262 switch (r_type)
10263 {
10264 case BFD_RELOC_IA64_IMM22:
10265 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
10266 case BFD_RELOC_IA64_IMM64:
10267 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
10268 default:
10269 break;
10270 }
10271 break;
3969b680 10272
13ae64f3
JJ		 10273 case FUNC_TP_RELATIVE:
10274 switch (r_type)
10275 {
10276 case BFD_RELOC_IA64_IMM14:
10277 new = BFD_RELOC_IA64_TPREL14; break;
10278 case BFD_RELOC_IA64_IMM22:
10279 new = BFD_RELOC_IA64_TPREL22; break;
10280 case BFD_RELOC_IA64_IMM64:
10281 new = BFD_RELOC_IA64_TPREL64I; break;
10282 default:
10283 break;
10284 }
10285 break;
10286
10287 case FUNC_LT_TP_RELATIVE:
10288 switch (r_type)
10289 {
10290 case BFD_RELOC_IA64_IMM22:
10291 new = BFD_RELOC_IA64_LTOFF_TPREL22; break;
10292 default:
10293 break;
10294 }
10295 break;
10296
10297 case FUNC_LT_DTP_MODULE:
10298 switch (r_type)
10299 {
10300 case BFD_RELOC_IA64_IMM22:
10301 new = BFD_RELOC_IA64_LTOFF_DTPMOD22; break;
10302 default:
10303 break;
10304 }
10305 break;
10306
10307 case FUNC_DTP_RELATIVE:
10308 switch (r_type)
10309 {
6174d9c8
RH		 10310 case BFD_RELOC_IA64_DIR64MSB:
10311 new = BFD_RELOC_IA64_DTPREL64MSB; break;
10312 case BFD_RELOC_IA64_DIR64LSB:
10313 new = BFD_RELOC_IA64_DTPREL64LSB; break;
13ae64f3
JJ		 10314 case BFD_RELOC_IA64_IMM14:
10315 new = BFD_RELOC_IA64_DTPREL14; break;
10316 case BFD_RELOC_IA64_IMM22:
10317 new = BFD_RELOC_IA64_DTPREL22; break;
10318 case BFD_RELOC_IA64_IMM64:
10319 new = BFD_RELOC_IA64_DTPREL64I; break;
10320 default:
10321 break;
10322 }
10323 break;
10324
10325 case FUNC_LT_DTP_RELATIVE:
10326 switch (r_type)
10327 {
10328 case BFD_RELOC_IA64_IMM22:
10329 new = BFD_RELOC_IA64_LTOFF_DTPREL22; break;
10330 default:
10331 break;
10332 }
10333 break;
10334
40449e9f
KH		 10335 case FUNC_IPLT_RELOC:
10336 break;
1cd8ff38 10337
800eeca4
JW		 10338 default:
10339 abort ();
10340 }
6174d9c8 10341
800eeca4
JW		 10342 /* Hmmmm. Should this ever occur? */
10343 if (new)
10344 return new;
10345 else
10346 return r_type;
10347}
10348
10349/* Here is where generate the appropriate reloc for pseudo relocation
10350 functions. */
10351void
10352ia64_validate_fix (fix)
10353 fixS *fix;
10354{
10355 switch (fix->fx_r_type)
10356 {
10357 case BFD_RELOC_IA64_FPTR64I:
10358 case BFD_RELOC_IA64_FPTR32MSB:
10359 case BFD_RELOC_IA64_FPTR64LSB:
10360 case BFD_RELOC_IA64_LTOFF_FPTR22:
10361 case BFD_RELOC_IA64_LTOFF_FPTR64I:
10362 if (fix->fx_offset != 0)
10363 as_bad_where (fix->fx_file, fix->fx_line,
10364 "No addend allowed in @fptr() relocation");
10365 break;
10366 default:
10367 break;
10368 }
10369
10370 return;
10371}
10372
10373static void
10374fix_insn (fix, odesc, value)
10375 fixS *fix;
10376 const struct ia64_operand *odesc;
10377 valueT value;
10378{
10379 bfd_vma insn[3], t0, t1, control_bits;
10380 const char *err;
10381 char *fixpos;
10382 long slot;
10383
10384 slot = fix->fx_where & 0x3;
10385 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
10386
c67e42c9 10387 /* Bundles are always in little-endian byte order */
800eeca4
JW		 10388 t0 = bfd_getl64 (fixpos);
10389 t1 = bfd_getl64 (fixpos + 8);
10390 control_bits = t0 & 0x1f;
10391 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
10392 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
10393 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
10394
c67e42c9
RH		 10395 err = NULL;
10396 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 10397 {
c67e42c9
RH		 10398 insn[1] = (value >> 22) & 0x1ffffffffffLL;
10399 insn[2] |= (((value & 0x7f) << 13)
10400 | (((value >> 7) & 0x1ff) << 27)
10401 | (((value >> 16) & 0x1f) << 22)
10402 | (((value >> 21) & 0x1) << 21)
10403 | (((value >> 63) & 0x1) << 36));
800eeca4 10404 }
c67e42c9
RH		 10405 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
10406 {
10407 if (value & ~0x3fffffffffffffffULL)
10408 err = "integer operand out of range";
10409 insn[1] = (value >> 21) & 0x1ffffffffffLL;
10410 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
10411 }
10412 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
10413 {
10414 value >>= 4;
10415 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
10416 insn[2] |= ((((value >> 59) & 0x1) << 36)
10417 | (((value >> 0) & 0xfffff) << 13));
10418 }
10419 else
10420 err = (*odesc->insert) (odesc, value, insn + slot);
10421
10422 if (err)
10423 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW		 10424
10425 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
10426 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
44f5c83a
JW		 10427 number_to_chars_littleendian (fixpos + 0, t0, 8);
10428 number_to_chars_littleendian (fixpos + 8, t1, 8);
800eeca4
JW		 10429}
10430
10431/* Attempt to simplify or even eliminate a fixup. The return value is
10432 ignored; perhaps it was once meaningful, but now it is historical.
10433 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10434
10435 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
197865e8 10436 (if possible). */
94f592af
NC		 10437
10438void
10439md_apply_fix3 (fix, valP, seg)
800eeca4 10440 fixS *fix;
40449e9f 10441 valueT *valP;
2434f565 10442 segT seg ATTRIBUTE_UNUSED;
800eeca4
JW		 10443{
10444 char *fixpos;
40449e9f 10445 valueT value = *valP;
800eeca4
JW		 10446
10447 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
10448
10449 if (fix->fx_pcrel)
10450 {
10451 switch (fix->fx_r_type)
10452 {
10453 case BFD_RELOC_IA64_DIR32MSB:
10454 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
800eeca4
JW		 10455 break;
10456
10457 case BFD_RELOC_IA64_DIR32LSB:
10458 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
800eeca4
JW		 10459 break;
10460
10461 case BFD_RELOC_IA64_DIR64MSB:
10462 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
800eeca4
JW		 10463 break;
10464
10465 case BFD_RELOC_IA64_DIR64LSB:
10466 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
800eeca4
JW		 10467 break;
10468
10469 default:
10470 break;
10471 }
10472 }
10473 if (fix->fx_addsy)
10474 {
00f7efb6 10475 switch (fix->fx_r_type)
800eeca4 10476 {
00f7efb6 10477 case BFD_RELOC_UNUSED:
fa1cb89c
JW		 10478 /* This must be a TAG13 or TAG13b operand. There are no external
10479 relocs defined for them, so we must give an error. */
800eeca4
JW		 10480 as_bad_where (fix->fx_file, fix->fx_line,
10481 "%s must have a constant value",
10482 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
fa1cb89c 10483 fix->fx_done = 1;
94f592af 10484 return;
00f7efb6
JJ		 10485
10486 case BFD_RELOC_IA64_TPREL14:
10487 case BFD_RELOC_IA64_TPREL22:
10488 case BFD_RELOC_IA64_TPREL64I:
10489 case BFD_RELOC_IA64_LTOFF_TPREL22:
10490 case BFD_RELOC_IA64_LTOFF_DTPMOD22:
10491 case BFD_RELOC_IA64_DTPREL14:
10492 case BFD_RELOC_IA64_DTPREL22:
10493 case BFD_RELOC_IA64_DTPREL64I:
10494 case BFD_RELOC_IA64_LTOFF_DTPREL22:
10495 S_SET_THREAD_LOCAL (fix->fx_addsy);
10496 break;
7925dd68
JJ		 10497
10498 default:
10499 break;
800eeca4 10500 }
800eeca4
JW		 10501 }
10502 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
10503 {
10504 if (fix->tc_fix_data.bigendian)
10505 number_to_chars_bigendian (fixpos, value, fix->fx_size);
10506 else
10507 number_to_chars_littleendian (fixpos, value, fix->fx_size);
10508 fix->fx_done = 1;
800eeca4
JW		 10509 }
10510 else
10511 {
10512 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
10513 fix->fx_done = 1;
800eeca4 10514 }
800eeca4
JW		 10515}
10516
10517/* Generate the BFD reloc to be stuck in the object file from the
10518 fixup used internally in the assembler. */
542d6675
KH		 10519
10520arelent *
800eeca4 10521tc_gen_reloc (sec, fixp)
2434f565 10522 asection *sec ATTRIBUTE_UNUSED;
800eeca4
JW		 10523 fixS *fixp;
10524{
10525 arelent *reloc;
10526
10527 reloc = xmalloc (sizeof (*reloc));
10528 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10529 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10530 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
10531 reloc->addend = fixp->fx_offset;
10532 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
10533
10534 if (!reloc->howto)
10535 {
10536 as_bad_where (fixp->fx_file, fixp->fx_line,
10537 "Cannot represent %s relocation in object file",
10538 bfd_get_reloc_code_name (fixp->fx_r_type));
10539 }
10540 return reloc;
10541}
10542
10543/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 10544 of type TYPE, and store the appropriate bytes in *LIT. The number
10545 of LITTLENUMS emitted is stored in *SIZE. An error message is
800eeca4
JW		 10546 returned, or NULL on OK. */
10547
10548#define MAX_LITTLENUMS 5
10549
542d6675 10550char *
800eeca4
JW		 10551md_atof (type, lit, size)
10552 int type;
10553 char *lit;
10554 int *size;
10555{
10556 LITTLENUM_TYPE words[MAX_LITTLENUMS];
10557 LITTLENUM_TYPE *word;
10558 char *t;
10559 int prec;
10560
10561 switch (type)
10562 {
10563 /* IEEE floats */
10564 case 'f':
10565 case 'F':
10566 case 's':
10567 case 'S':
10568 prec = 2;
10569 break;
10570
10571 case 'd':
10572 case 'D':
10573 case 'r':
10574 case 'R':
10575 prec = 4;
10576 break;
10577
10578 case 'x':
10579 case 'X':
10580 case 'p':
10581 case 'P':
10582 prec = 5;
10583 break;
10584
10585 default:
10586 *size = 0;
10587 return "Bad call to MD_ATOF()";
10588 }
10589 t = atof_ieee (input_line_pointer, type, words);
10590 if (t)
10591 input_line_pointer = t;
10592 *size = prec * sizeof (LITTLENUM_TYPE);
10593
10594 for (word = words + prec - 1; prec--;)
10595 {
10596 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
10597 lit += sizeof (LITTLENUM_TYPE);
10598 }
165a7f90
L		 10599 if (type == 'X')
10600 {
10601 /* It is 10 byte floating point with 6 byte padding. */
10602 memset (lit, 0, 6);
10603 *size = 8 * sizeof (LITTLENUM_TYPE);
10604 }
800eeca4
JW		 10605 return 0;
10606}
10607
800eeca4
JW		 10608/* Handle ia64 specific semantics of the align directive. */
10609
0a9ef439 10610void
800eeca4 10611ia64_md_do_align (n, fill, len, max)
91a2ae2a
RH		 10612 int n ATTRIBUTE_UNUSED;
10613 const char *fill ATTRIBUTE_UNUSED;
2434f565 10614 int len ATTRIBUTE_UNUSED;
91a2ae2a 10615 int max ATTRIBUTE_UNUSED;
800eeca4 10616{
0a9ef439 10617 if (subseg_text_p (now_seg))
800eeca4 10618 ia64_flush_insns ();
0a9ef439 10619}
800eeca4 10620
0a9ef439
RH		 10621/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10622 of an rs_align_code fragment. */
800eeca4 10623
0a9ef439
RH		 10624void
10625ia64_handle_align (fragp)
10626 fragS *fragp;
10627{
10628 /* Use mfi bundle of nops with no stop bits. */
10629 static const unsigned char be_nop[]
10630 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10631 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10632 static const unsigned char le_nop[]
10633 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10634 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10635
10636 int bytes;
10637 char *p;
10638
10639 if (fragp->fr_type != rs_align_code)
10640 return;
10641
10642 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
10643 p = fragp->fr_literal + fragp->fr_fix;
10644
10645 /* Make sure we are on a 16-byte boundary, in case someone has been
10646 putting data into a text section. */
10647 if (bytes & 15)
10648 {
10649 int fix = bytes & 15;
10650 memset (p, 0, fix);
10651 p += fix;
10652 bytes -= fix;
10653 fragp->fr_fix += fix;
800eeca4
JW		 10654 }
10655
0a9ef439
RH		 10656 memcpy (p, (target_big_endian ? be_nop : le_nop), 16);
10657 fragp->fr_var = 16;
800eeca4 10658}
GDB Binutils - Deliverables
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