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2000-11-06 Kazu Hirata <kazu@hxi.com>
[deliverable/binutils-gdb.git] / gas / config / tc-ia64.c
CommitLineData
800eeca4 1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
e0c9811a 2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
800eeca4
JW		 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 TODO:
24
25 - optional operands
26 - directives:
27 .alias
28 .eb
29 .estate
30 .lb
31 .popsection
32 .previous
33 .psr
34 .pushsection
800eeca4
JW		 35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
37 - DV-related stuff:
542d6675
KH		 38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
41 notes)
800eeca4
JW		 42
43 */
44
45#include "as.h"
46#include "dwarf2dbg.h"
47#include "subsegs.h"
48
49#include "opcode/ia64.h"
50
51#include "elf/ia64.h"
52
53#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54#define MIN(a,b) ((a) < (b) ? (a) : (b))
55
56#define NUM_SLOTS 4
57#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58#define CURR_SLOT md.slot[md.curr_slot]
59
60#define O_pseudo_fixup (O_max + 1)
61
62enum special_section
63 {
64 SPECIAL_SECTION_BSS = 0,
65 SPECIAL_SECTION_SBSS,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
71 };
72
73enum reloc_func
74 {
75 FUNC_FPTR_RELATIVE,
76 FUNC_GP_RELATIVE,
77 FUNC_LT_RELATIVE,
c67e42c9 78 FUNC_PC_RELATIVE,
800eeca4
JW		 79 FUNC_PLT_RELATIVE,
80 FUNC_SEC_RELATIVE,
81 FUNC_SEG_RELATIVE,
82 FUNC_LTV_RELATIVE,
83 FUNC_LT_FPTR_RELATIVE,
84 };
85
86enum reg_symbol
87 {
88 REG_GR = 0,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
95 REG_CFM,
96 REG_PR,
97 REG_PR_ROT,
98 REG_PSR,
99 REG_PSR_L,
100 REG_PSR_UM,
101 /* The following are pseudo-registers for use by gas only. */
102 IND_CPUID,
103 IND_DBR,
104 IND_DTR,
105 IND_ITR,
106 IND_IBR,
107 IND_MEM,
108 IND_MSR,
109 IND_PKR,
110 IND_PMC,
111 IND_PMD,
112 IND_RR,
542d6675 113 /* The following pseudo-registers are used for unwind directives only: */
e0c9811a
JW		 114 REG_PSP,
115 REG_PRIUNAT,
800eeca4
JW		 116 REG_NUM
117 };
118
119enum dynreg_type
120 {
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
124 DYNREG_NUM_TYPES
125 };
126
127/* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
130 instruction. */
131struct label_fix
542d6675
KH		 132{
133 struct label_fix *next;
134 struct symbol *sym;
135};
800eeca4
JW		 136
137extern int target_big_endian;
138
139/* Characters which always start a comment. */
140const char comment_chars[] = "";
141
142/* Characters which start a comment at the beginning of a line. */
143const char line_comment_chars[] = "#";
144
145/* Characters which may be used to separate multiple commands on a
146 single line. */
147const char line_separator_chars[] = ";";
148
149/* Characters which are used to indicate an exponent in a floating
150 point number. */
151const char EXP_CHARS[] = "eE";
152
153/* Characters which mean that a number is a floating point constant,
154 as in 0d1.0. */
155const char FLT_CHARS[] = "rRsSfFdDxXpP";
156
542d6675 157/* ia64-specific option processing: */
800eeca4
JW		 158
159const char *md_shortopts = "M:N:x::";
160
161struct option md_longopts[] =
162 {
c43c2cc5
JW		 163#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
165#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
800eeca4
JW		 167 };
168
169size_t md_longopts_size = sizeof (md_longopts);
170
171static struct
172 {
173 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
174 struct hash_control *reg_hash; /* register name hash table */
175 struct hash_control *dynreg_hash; /* dynamic register hash table */
176 struct hash_control *const_hash; /* constant hash table */
177 struct hash_control *entry_hash; /* code entry hint hash table */
178
179 symbolS *regsym[REG_NUM];
180
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
184 expressionS qp;
185
186 unsigned int
197865e8 187 manual_bundling : 1,
800eeca4
JW		 188 debug_dv: 1,
189 detect_dv: 1,
190 explicit_mode : 1, /* which mode we're in */
191 default_explicit_mode : 1, /* which mode is the default */
192 mode_explicitly_set : 1, /* was the current mode explicitly set? */
193 auto_align : 1;
194
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197865e8 197 the end_of_insn_group for the last instruction in a bundle. */
800eeca4
JW		 198 int curr_slot;
199 int num_slots_in_use;
200 struct slot
201 {
202 unsigned int
203 end_of_insn_group : 1,
204 manual_bundling_on : 1,
205 manual_bundling_off : 1;
206 signed char user_template; /* user-selected template, if any */
207 unsigned char qp_regno; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
211 int num_fixups;
212 struct insn_fix
213 {
214 bfd_reloc_code_real_type code;
215 enum ia64_opnd opnd; /* type of operand in need of fix */
216 unsigned int is_pcrel : 1; /* is operand pc-relative? */
217 expressionS expr; /* the value to be inserted */
218 }
219 fixup[2]; /* at most two fixups per insn */
220 struct ia64_opcode *idesc;
221 struct label_fix *label_fixups;
f1bcba5b 222 struct label_fix *tag_fixups;
800eeca4
JW		 223 struct unw_rec_list *unwind_record; /* Unwind directive. */
224 expressionS opnd[6];
225 char *src_file;
226 unsigned int src_line;
227 struct dwarf2_line_info debug_line;
228 }
229 slot[NUM_SLOTS];
230
231 segT last_text_seg;
232
233 struct dynreg
234 {
235 struct dynreg *next; /* next dynamic register */
236 const char *name;
237 unsigned short base; /* the base register number */
238 unsigned short num_regs; /* # of registers in this set */
239 }
240 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
241
242 flagword flags; /* ELF-header flags */
243
244 struct mem_offset {
245 unsigned hint:1; /* is this hint currently valid? */
246 bfd_vma offset; /* mem.offset offset */
247 bfd_vma base; /* mem.offset base */
248 } mem_offset;
249
250 int path; /* number of alt. entry points seen */
251 const char **entry_labels; /* labels of all alternate paths in
542d6675 252 the current DV-checking block. */
800eeca4 253 int maxpaths; /* size currently allocated for
542d6675 254 entry_labels */
800eeca4
JW		 255 }
256md;
257
542d6675 258/* application registers: */
800eeca4 259
e0c9811a
JW		 260#define AR_K0 0
261#define AR_K7 7
262#define AR_RSC 16
263#define AR_BSP 17
264#define AR_BSPSTORE 18
265#define AR_RNAT 19
266#define AR_UNAT 36
267#define AR_FPSR 40
268#define AR_ITC 44
269#define AR_PFS 64
270#define AR_LC 65
800eeca4
JW		 271
272static const struct
273 {
274 const char *name;
275 int regnum;
276 }
277ar[] =
278 {
279 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
280 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
281 {"ar.rsc", 16}, {"ar.bsp", 17},
282 {"ar.bspstore", 18}, {"ar.rnat", 19},
283 {"ar.fcr", 21}, {"ar.eflag", 24},
284 {"ar.csd", 25}, {"ar.ssd", 26},
285 {"ar.cflg", 27}, {"ar.fsr", 28},
286 {"ar.fir", 29}, {"ar.fdr", 30},
287 {"ar.ccv", 32}, {"ar.unat", 36},
288 {"ar.fpsr", 40}, {"ar.itc", 44},
289 {"ar.pfs", 64}, {"ar.lc", 65},
197865e8 290 {"ar.ec", 66},
800eeca4
JW		 291 };
292
293#define CR_IPSR 16
294#define CR_ISR 17
295#define CR_IIP 19
296#define CR_IFA 20
297#define CR_ITIR 21
298#define CR_IIPA 22
299#define CR_IFS 23
300#define CR_IIM 24
301#define CR_IHA 25
302#define CR_IVR 65
303#define CR_TPR 66
304#define CR_EOI 67
305#define CR_IRR0 68
306#define CR_IRR3 71
307#define CR_LRR0 80
308#define CR_LRR1 81
309
542d6675 310/* control registers: */
800eeca4
JW		 311static const struct
312 {
313 const char *name;
314 int regnum;
315 }
316cr[] =
317 {
318 {"cr.dcr", 0},
319 {"cr.itm", 1},
320 {"cr.iva", 2},
321 {"cr.pta", 8},
322 {"cr.gpta", 9},
323 {"cr.ipsr", 16},
324 {"cr.isr", 17},
325 {"cr.iip", 19},
326 {"cr.ifa", 20},
327 {"cr.itir", 21},
328 {"cr.iipa", 22},
329 {"cr.ifs", 23},
330 {"cr.iim", 24},
331 {"cr.iha", 25},
332 {"cr.lid", 64},
333 {"cr.ivr", 65},
334 {"cr.tpr", 66},
335 {"cr.eoi", 67},
336 {"cr.irr0", 68},
337 {"cr.irr1", 69},
338 {"cr.irr2", 70},
339 {"cr.irr3", 71},
340 {"cr.itv", 72},
341 {"cr.pmv", 73},
342 {"cr.cmcv", 74},
343 {"cr.lrr0", 80},
344 {"cr.lrr1", 81}
345 };
346
347#define PSR_MFL 4
348#define PSR_IC 13
349#define PSR_DFL 18
350#define PSR_CPL 32
351
352static const struct const_desc
353 {
354 const char *name;
355 valueT value;
356 }
357const_bits[] =
358 {
542d6675 359 /* PSR constant masks: */
800eeca4
JW		 360
361 /* 0: reserved */
362 {"psr.be", ((valueT) 1) << 1},
363 {"psr.up", ((valueT) 1) << 2},
364 {"psr.ac", ((valueT) 1) << 3},
365 {"psr.mfl", ((valueT) 1) << 4},
366 {"psr.mfh", ((valueT) 1) << 5},
367 /* 6-12: reserved */
368 {"psr.ic", ((valueT) 1) << 13},
369 {"psr.i", ((valueT) 1) << 14},
370 {"psr.pk", ((valueT) 1) << 15},
371 /* 16: reserved */
372 {"psr.dt", ((valueT) 1) << 17},
373 {"psr.dfl", ((valueT) 1) << 18},
374 {"psr.dfh", ((valueT) 1) << 19},
375 {"psr.sp", ((valueT) 1) << 20},
376 {"psr.pp", ((valueT) 1) << 21},
377 {"psr.di", ((valueT) 1) << 22},
378 {"psr.si", ((valueT) 1) << 23},
379 {"psr.db", ((valueT) 1) << 24},
380 {"psr.lp", ((valueT) 1) << 25},
381 {"psr.tb", ((valueT) 1) << 26},
382 {"psr.rt", ((valueT) 1) << 27},
383 /* 28-31: reserved */
384 /* 32-33: cpl (current privilege level) */
385 {"psr.is", ((valueT) 1) << 34},
386 {"psr.mc", ((valueT) 1) << 35},
387 {"psr.it", ((valueT) 1) << 36},
388 {"psr.id", ((valueT) 1) << 37},
389 {"psr.da", ((valueT) 1) << 38},
390 {"psr.dd", ((valueT) 1) << 39},
391 {"psr.ss", ((valueT) 1) << 40},
392 /* 41-42: ri (restart instruction) */
393 {"psr.ed", ((valueT) 1) << 43},
394 {"psr.bn", ((valueT) 1) << 44},
395 };
396
542d6675 397/* indirect register-sets/memory: */
800eeca4
JW		 398
399static const struct
400 {
401 const char *name;
402 int regnum;
403 }
404indirect_reg[] =
405 {
406 { "CPUID", IND_CPUID },
407 { "cpuid", IND_CPUID },
408 { "dbr", IND_DBR },
409 { "dtr", IND_DTR },
410 { "itr", IND_ITR },
411 { "ibr", IND_IBR },
412 { "msr", IND_MSR },
413 { "pkr", IND_PKR },
414 { "pmc", IND_PMC },
415 { "pmd", IND_PMD },
416 { "rr", IND_RR },
417 };
418
419/* Pseudo functions used to indicate relocation types (these functions
420 start with an at sign (@). */
421static struct
422 {
423 const char *name;
424 enum pseudo_type
425 {
426 PSEUDO_FUNC_NONE,
427 PSEUDO_FUNC_RELOC,
428 PSEUDO_FUNC_CONST,
e0c9811a 429 PSEUDO_FUNC_REG,
800eeca4
JW		 430 PSEUDO_FUNC_FLOAT
431 }
432 type;
433 union
434 {
435 unsigned long ival;
436 symbolS *sym;
437 }
438 u;
439 }
440pseudo_func[] =
441 {
542d6675 442 /* reloc pseudo functions (these must come first!): */
800eeca4
JW		 443 { "fptr", PSEUDO_FUNC_RELOC },
444 { "gprel", PSEUDO_FUNC_RELOC },
445 { "ltoff", PSEUDO_FUNC_RELOC },
c67e42c9 446 { "pcrel", PSEUDO_FUNC_RELOC },
800eeca4
JW		 447 { "pltoff", PSEUDO_FUNC_RELOC },
448 { "secrel", PSEUDO_FUNC_RELOC },
449 { "segrel", PSEUDO_FUNC_RELOC },
450 { "ltv", PSEUDO_FUNC_RELOC },
451 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
452
542d6675 453 /* mbtype4 constants: */
800eeca4
JW		 454 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
455 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
456 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
457 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
458 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
459
542d6675 460 /* fclass constants: */
bf3ca999 461 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
800eeca4
JW		 462 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
463 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
464 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
465 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
466 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
467 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
468 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
469 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
bf3ca999
TW		 470
471 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
e0c9811a 472
542d6675 473 /* unwind-related constants: */
e0c9811a
JW		 474 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
475 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
476 { "nt", PSEUDO_FUNC_CONST, { 2 } },
477
542d6675 478 /* unwind-related registers: */
e0c9811a 479 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
800eeca4
JW		 480 };
481
542d6675 482/* 41-bit nop opcodes (one per unit): */
800eeca4
JW		 483static const bfd_vma nop[IA64_NUM_UNITS] =
484 {
485 0x0000000000LL, /* NIL => break 0 */
486 0x0008000000LL, /* I-unit nop */
487 0x0008000000LL, /* M-unit nop */
488 0x4000000000LL, /* B-unit nop */
489 0x0008000000LL, /* F-unit nop */
490 0x0008000000LL, /* L-"unit" nop */
491 0x0008000000LL, /* X-unit nop */
492 };
493
494/* Can't be `const' as it's passed to input routines (which have the
495 habit of setting temporary sentinels. */
496static char special_section_name[][20] =
497 {
498 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
499 {".IA_64.unwind"}, {".IA_64.unwind_info"}
500 };
501
502/* The best template for a particular sequence of up to three
503 instructions: */
504#define N IA64_NUM_TYPES
505static unsigned char best_template[N][N][N];
506#undef N
507
508/* Resource dependencies currently in effect */
509static struct rsrc {
510 int depind; /* dependency index */
511 const struct ia64_dependency *dependency; /* actual dependency */
512 unsigned specific:1, /* is this a specific bit/regno? */
513 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
514 int index; /* specific regno/bit within dependency */
515 int note; /* optional qualifying note (0 if none) */
516#define STATE_NONE 0
517#define STATE_STOP 1
518#define STATE_SRLZ 2
519 int insn_srlz; /* current insn serialization state */
520 int data_srlz; /* current data serialization state */
521 int qp_regno; /* qualifying predicate for this usage */
522 char *file; /* what file marked this dependency */
523 int line; /* what line marked this dependency */
524 struct mem_offset mem_offset; /* optional memory offset hint */
7484b8e6 525 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
800eeca4
JW		 526 int path; /* corresponding code entry index */
527} *regdeps = NULL;
528static int regdepslen = 0;
529static int regdepstotlen = 0;
530static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
531static const char *dv_sem[] = { "none", "implied", "impliedf",
139368c9 532 "data", "instr", "specific", "stop", "other" };
7484b8e6 533static const char *dv_cmp_type[] = { "none", "OR", "AND" };
800eeca4
JW		 534
535/* Current state of PR mutexation */
536static struct qpmutex {
537 valueT prmask;
538 int path;
539} *qp_mutexes = NULL; /* QP mutex bitmasks */
540static int qp_mutexeslen = 0;
541static int qp_mutexestotlen = 0;
197865e8 542static valueT qp_safe_across_calls = 0;
800eeca4
JW		 543
544/* Current state of PR implications */
545static struct qp_imply {
546 unsigned p1:6;
547 unsigned p2:6;
548 unsigned p2_branched:1;
549 int path;
550} *qp_implies = NULL;
551static int qp_implieslen = 0;
552static int qp_impliestotlen = 0;
553
197865e8
KH		 554/* Keep track of static GR values so that indirect register usage can
555 sometimes be tracked. */
800eeca4
JW		 556static struct gr {
557 unsigned known:1;
558 int path;
559 valueT value;
560} gr_values[128] = {{ 1, 0 }};
561
562/* These are the routines required to output the various types of
563 unwind records. */
564
565typedef struct unw_rec_list {
566 unwind_record r;
e0c9811a 567 unsigned long slot_number;
800eeca4
JW		 568 struct unw_rec_list *next;
569} unw_rec_list;
570
571#define SLOT_NUM_NOT_SET -1
572
e0c9811a
JW		 573static struct
574{
575 unsigned long next_slot_number;
576
577 /* Maintain a list of unwind entries for the current function. */
578 unw_rec_list *list;
579 unw_rec_list *tail;
800eeca4 580
e0c9811a
JW		 581 /* Any unwind entires that should be attached to the current slot
582 that an insn is being constructed for. */
583 unw_rec_list *current_entry;
800eeca4 584
e0c9811a
JW		 585 /* These are used to create the unwind table entry for this function. */
586 symbolS *proc_start;
587 symbolS *proc_end;
588 symbolS *info; /* pointer to unwind info */
589 symbolS *personality_routine;
800eeca4 590
e0c9811a
JW		 591 /* TRUE if processing unwind directives in a prologue region. */
592 int prologue;
30d25259 593 int prologue_mask;
e0c9811a 594} unwind;
800eeca4
JW		 595
596typedef void (*vbyte_func) PARAMS ((int, char *, char *));
597
542d6675 598/* Forward delarations: */
800eeca4
JW		 599static int ar_is_in_integer_unit PARAMS ((int regnum));
600static void set_section PARAMS ((char *name));
601static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
602 unsigned int, unsigned int));
603static void dot_radix PARAMS ((int));
604static void dot_special_section PARAMS ((int));
605static void dot_proc PARAMS ((int));
606static void dot_fframe PARAMS ((int));
607static void dot_vframe PARAMS ((int));
150f24a2
JW		 608static void dot_vframesp PARAMS ((int));
609static void dot_vframepsp PARAMS ((int));
800eeca4
JW		 610static void dot_save PARAMS ((int));
611static void dot_restore PARAMS ((int));
150f24a2
JW		 612static void dot_restorereg PARAMS ((int));
613static void dot_restorereg_p PARAMS ((int));
800eeca4
JW		 614static void dot_handlerdata PARAMS ((int));
615static void dot_unwentry PARAMS ((int));
616static void dot_altrp PARAMS ((int));
e0c9811a 617static void dot_savemem PARAMS ((int));
800eeca4
JW		 618static void dot_saveg PARAMS ((int));
619static void dot_savef PARAMS ((int));
620static void dot_saveb PARAMS ((int));
621static void dot_savegf PARAMS ((int));
622static void dot_spill PARAMS ((int));
150f24a2
JW		 623static void dot_spillreg PARAMS ((int));
624static void dot_spillmem PARAMS ((int));
625static void dot_spillreg_p PARAMS ((int));
626static void dot_spillmem_p PARAMS ((int));
627static void dot_label_state PARAMS ((int));
628static void dot_copy_state PARAMS ((int));
800eeca4
JW		 629static void dot_unwabi PARAMS ((int));
630static void dot_personality PARAMS ((int));
631static void dot_body PARAMS ((int));
632static void dot_prologue PARAMS ((int));
633static void dot_endp PARAMS ((int));
634static void dot_template PARAMS ((int));
635static void dot_regstk PARAMS ((int));
636static void dot_rot PARAMS ((int));
637static void dot_byteorder PARAMS ((int));
638static void dot_psr PARAMS ((int));
639static void dot_alias PARAMS ((int));
640static void dot_ln PARAMS ((int));
641static char *parse_section_name PARAMS ((void));
642static void dot_xdata PARAMS ((int));
643static void stmt_float_cons PARAMS ((int));
644static void stmt_cons_ua PARAMS ((int));
645static void dot_xfloat_cons PARAMS ((int));
646static void dot_xstringer PARAMS ((int));
647static void dot_xdata_ua PARAMS ((int));
648static void dot_xfloat_cons_ua PARAMS ((int));
150f24a2 649static void print_prmask PARAMS ((valueT mask));
800eeca4
JW		 650static void dot_pred_rel PARAMS ((int));
651static void dot_reg_val PARAMS ((int));
652static void dot_dv_mode PARAMS ((int));
653static void dot_entry PARAMS ((int));
654static void dot_mem_offset PARAMS ((int));
e0c9811a 655static void add_unwind_entry PARAMS((unw_rec_list *ptr));
542d6675 656static symbolS *declare_register PARAMS ((const char *name, int regnum));
800eeca4
JW		 657static void declare_register_set PARAMS ((const char *, int, int));
658static unsigned int operand_width PARAMS ((enum ia64_opnd));
659static int operand_match PARAMS ((const struct ia64_opcode *idesc,
660 int index, expressionS *e));
661static int parse_operand PARAMS ((expressionS *e));
662static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
663static void build_insn PARAMS ((struct slot *, bfd_vma *));
664static void emit_one_bundle PARAMS ((void));
665static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
197865e8 666static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
800eeca4
JW		 667 bfd_reloc_code_real_type r_type));
668static void insn_group_break PARAMS ((int, int, int));
150f24a2
JW		 669static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
670 struct rsrc *, int depind, int path));
800eeca4
JW		 671static void add_qp_mutex PARAMS((valueT mask));
672static void add_qp_imply PARAMS((int p1, int p2));
673static void clear_qp_branch_flag PARAMS((valueT mask));
674static void clear_qp_mutex PARAMS((valueT mask));
675static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
676static void clear_register_values PARAMS ((void));
677static void print_dependency PARAMS ((const char *action, int depind));
150f24a2
JW		 678static void instruction_serialization PARAMS ((void));
679static void data_serialization PARAMS ((void));
680static void remove_marked_resource PARAMS ((struct rsrc *));
800eeca4 681static int is_conditional_branch PARAMS ((struct ia64_opcode *));
150f24a2 682static int is_taken_branch PARAMS ((struct ia64_opcode *));
800eeca4 683static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
150f24a2
JW		 684static int depends_on PARAMS ((int, struct ia64_opcode *));
685static int specify_resource PARAMS ((const struct ia64_dependency *,
686 struct ia64_opcode *, int, struct rsrc [], int, int));
800eeca4
JW		 687static int check_dv PARAMS((struct ia64_opcode *idesc));
688static void check_dependencies PARAMS((struct ia64_opcode *));
689static void mark_resources PARAMS((struct ia64_opcode *));
690static void update_dependencies PARAMS((struct ia64_opcode *));
691static void note_register_values PARAMS((struct ia64_opcode *));
150f24a2
JW		 692static int qp_mutex PARAMS ((int, int, int));
693static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
694static void output_vbyte_mem PARAMS ((int, char *, char *));
695static void count_output PARAMS ((int, char *, char *));
696static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
697static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
800eeca4 698static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 699static void output_P1_format PARAMS ((vbyte_func, int));
700static void output_P2_format PARAMS ((vbyte_func, int, int));
701static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
702static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
703static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
704static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
705static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
706static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
707static void output_P9_format PARAMS ((vbyte_func, int, int));
708static void output_P10_format PARAMS ((vbyte_func, int, int));
709static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
710static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800eeca4
JW		 711static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
712static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
150f24a2
JW		 713static char format_ab_reg PARAMS ((int, int));
714static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
715 unsigned long));
716static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
717static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
718 unsigned long));
719static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
720static void free_list_records PARAMS ((unw_rec_list *));
721static unw_rec_list *output_prologue PARAMS ((void));
722static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
723static unw_rec_list *output_body PARAMS ((void));
724static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
725static unw_rec_list *output_mem_stack_v PARAMS ((void));
726static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
727static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
728static unw_rec_list *output_rp_when PARAMS ((void));
729static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
730static unw_rec_list *output_rp_br PARAMS ((unsigned int));
731static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
732static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
733static unw_rec_list *output_pfs_when PARAMS ((void));
734static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
735static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
736static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
737static unw_rec_list *output_preds_when PARAMS ((void));
738static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
739static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
740static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
741static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
742static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
743static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
744static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
745static unw_rec_list *output_br_mem PARAMS ((unsigned int));
746static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
747static unw_rec_list *output_spill_base PARAMS ((unsigned int));
748static unw_rec_list *output_unat_when PARAMS ((void));
749static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
750static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
751static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
752static unw_rec_list *output_lc_when PARAMS ((void));
753static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
754static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
755static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
756static unw_rec_list *output_fpsr_when PARAMS ((void));
757static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
758static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
759static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
760static unw_rec_list *output_priunat_when_gr PARAMS ((void));
761static unw_rec_list *output_priunat_when_mem PARAMS ((void));
762static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
763static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
764static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
765static unw_rec_list *output_bsp_when PARAMS ((void));
766static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
767static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
768static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
769static unw_rec_list *output_bspstore_when PARAMS ((void));
770static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
771static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
772static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
773static unw_rec_list *output_rnat_when PARAMS ((void));
774static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
775static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
776static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
777static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
778static unw_rec_list *output_epilogue PARAMS ((unsigned long));
779static unw_rec_list *output_label_state PARAMS ((unsigned long));
780static unw_rec_list *output_copy_state PARAMS ((unsigned long));
781static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
782static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
783static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
784 unsigned int));
785static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
786 unsigned int));
787static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
788 unsigned int));
789static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
790 unsigned int, unsigned int));
791static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
792static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
793static int calc_record_size PARAMS ((unw_rec_list *));
794static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
795static int count_bits PARAMS ((unsigned long));
796static unsigned long slot_index PARAMS ((unsigned long, unsigned long));
797static void fixup_unw_records PARAMS ((unw_rec_list *));
798static int output_unw_records PARAMS ((unw_rec_list *, void **));
799static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
800static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
801static int generate_unwind_image PARAMS ((void));
800eeca4
JW		 802
803/* Determine if application register REGNUM resides in the integer
804 unit (as opposed to the memory unit). */
805static int
806ar_is_in_integer_unit (reg)
807 int reg;
808{
809 reg -= REG_AR;
810
811 return (reg == 64 /* pfs */
812 || reg == 65 /* lc */
813 || reg == 66 /* ec */
814 /* ??? ias accepts and puts these in the integer unit. */
815 || (reg >= 112 && reg <= 127));
816}
817
818/* Switch to section NAME and create section if necessary. It's
819 rather ugly that we have to manipulate input_line_pointer but I
820 don't see any other way to accomplish the same thing without
821 changing obj-elf.c (which may be the Right Thing, in the end). */
822static void
823set_section (name)
824 char *name;
825{
826 char *saved_input_line_pointer;
827
828 saved_input_line_pointer = input_line_pointer;
829 input_line_pointer = name;
830 obj_elf_section (0);
831 input_line_pointer = saved_input_line_pointer;
832}
833
834/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
835
836flagword
837ia64_elf_section_flags (flags, attr, type)
838 flagword flags;
839 int attr, type;
840{
841 if (attr & SHF_IA_64_SHORT)
842 flags |= SEC_SMALL_DATA;
843 return flags;
844}
845
846static unsigned int
847set_regstack (ins, locs, outs, rots)
848 unsigned int ins, locs, outs, rots;
849{
542d6675
KH		 850 /* Size of frame. */
851 unsigned int sof;
800eeca4
JW		 852
853 sof = ins + locs + outs;
854 if (sof > 96)
855 {
856 as_bad ("Size of frame exceeds maximum of 96 registers");
857 return 0;
858 }
859 if (rots > sof)
860 {
861 as_warn ("Size of rotating registers exceeds frame size");
862 return 0;
863 }
864 md.in.base = REG_GR + 32;
865 md.loc.base = md.in.base + ins;
866 md.out.base = md.loc.base + locs;
867
868 md.in.num_regs = ins;
869 md.loc.num_regs = locs;
870 md.out.num_regs = outs;
871 md.rot.num_regs = rots;
872 return sof;
873}
874
875void
876ia64_flush_insns ()
877{
878 struct label_fix *lfix;
879 segT saved_seg;
880 subsegT saved_subseg;
881
882 if (!md.last_text_seg)
883 return;
884
885 saved_seg = now_seg;
886 saved_subseg = now_subseg;
887
888 subseg_set (md.last_text_seg, 0);
889
890 while (md.num_slots_in_use > 0)
891 emit_one_bundle (); /* force out queued instructions */
892
893 /* In case there are labels following the last instruction, resolve
542d6675 894 those now: */
800eeca4
JW		 895 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
896 {
897 S_SET_VALUE (lfix->sym, frag_now_fix ());
898 symbol_set_frag (lfix->sym, frag_now);
899 }
900 CURR_SLOT.label_fixups = 0;
f1bcba5b
JW		 901 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
902 {
903 S_SET_VALUE (lfix->sym, frag_now_fix ());
904 symbol_set_frag (lfix->sym, frag_now);
905 }
906 CURR_SLOT.tag_fixups = 0;
800eeca4
JW		 907
908 subseg_set (saved_seg, saved_subseg);
f1bcba5b
JW		 909
910 if (md.qp.X_op == O_register)
911 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW		 912}
913
914void
915ia64_do_align (nbytes)
916 int nbytes;
917{
918 char *saved_input_line_pointer = input_line_pointer;
919
920 input_line_pointer = "";
921 s_align_bytes (nbytes);
922 input_line_pointer = saved_input_line_pointer;
923}
924
925void
926ia64_cons_align (nbytes)
927 int nbytes;
928{
929 if (md.auto_align)
930 {
931 char *saved_input_line_pointer = input_line_pointer;
932 input_line_pointer = "";
933 s_align_bytes (nbytes);
934 input_line_pointer = saved_input_line_pointer;
935 }
936}
937
938/* Output COUNT bytes to a memory location. */
939static unsigned char *vbyte_mem_ptr = NULL;
940
197865e8 941void
800eeca4
JW		 942output_vbyte_mem (count, ptr, comment)
943 int count;
944 char *ptr;
945 char *comment;
946{
947 int x;
948 if (vbyte_mem_ptr == NULL)
949 abort ();
950
951 if (count == 0)
952 return;
953 for (x = 0; x < count; x++)
954 *(vbyte_mem_ptr++) = ptr[x];
955}
956
957/* Count the number of bytes required for records. */
958static int vbyte_count = 0;
197865e8 959void
800eeca4
JW		 960count_output (count, ptr, comment)
961 int count;
962 char *ptr;
963 char *comment;
964{
965 vbyte_count += count;
966}
967
968static void
969output_R1_format (f, rtype, rlen)
970 vbyte_func f;
971 unw_record_type rtype;
972 int rlen;
973{
e0c9811a 974 int r = 0;
800eeca4
JW		 975 char byte;
976 if (rlen > 0x1f)
977 {
978 output_R3_format (f, rtype, rlen);
979 return;
980 }
197865e8 981
e0c9811a
JW		 982 if (rtype == body)
983 r = 1;
984 else if (rtype != prologue)
985 as_bad ("record type is not valid");
986
800eeca4
JW		 987 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
988 (*f) (1, &byte, NULL);
989}
990
991static void
992output_R2_format (f, mask, grsave, rlen)
993 vbyte_func f;
994 int mask, grsave;
995 unsigned long rlen;
996{
997 char bytes[20];
998 int count = 2;
999 mask = (mask & 0x0f);
1000 grsave = (grsave & 0x7f);
1001
1002 bytes[0] = (UNW_R2 | (mask >> 1));
1003 bytes[1] = (((mask & 0x01) << 7) | grsave);
1004 count += output_leb128 (bytes + 2, rlen, 0);
1005 (*f) (count, bytes, NULL);
1006}
1007
1008static void
1009output_R3_format (f, rtype, rlen)
1010 vbyte_func f;
1011 unw_record_type rtype;
1012 unsigned long rlen;
1013{
e0c9811a 1014 int r = 0, count;
800eeca4
JW		 1015 char bytes[20];
1016 if (rlen <= 0x1f)
1017 {
1018 output_R1_format (f, rtype, rlen);
1019 return;
1020 }
197865e8 1021
e0c9811a
JW		 1022 if (rtype == body)
1023 r = 1;
1024 else if (rtype != prologue)
1025 as_bad ("record type is not valid");
800eeca4
JW		 1026 bytes[0] = (UNW_R3 | r);
1027 count = output_leb128 (bytes + 1, rlen, 0);
1028 (*f) (count + 1, bytes, NULL);
1029}
1030
1031static void
1032output_P1_format (f, brmask)
1033 vbyte_func f;
1034 int brmask;
1035{
1036 char byte;
1037 byte = UNW_P1 | (brmask & 0x1f);
1038 (*f) (1, &byte, NULL);
1039}
1040
1041static void
1042output_P2_format (f, brmask, gr)
1043 vbyte_func f;
1044 int brmask;
1045 int gr;
1046{
1047 char bytes[2];
1048 brmask = (brmask & 0x1f);
1049 bytes[0] = UNW_P2 | (brmask >> 1);
1050 bytes[1] = (((brmask & 1) << 7) | gr);
1051 (*f) (2, bytes, NULL);
1052}
1053
1054static void
1055output_P3_format (f, rtype, reg)
1056 vbyte_func f;
1057 unw_record_type rtype;
1058 int reg;
1059{
1060 char bytes[2];
e0c9811a 1061 int r = 0;
800eeca4
JW		 1062 reg = (reg & 0x7f);
1063 switch (rtype)
542d6675 1064 {
800eeca4
JW		 1065 case psp_gr:
1066 r = 0;
1067 break;
1068 case rp_gr:
1069 r = 1;
1070 break;
1071 case pfs_gr:
1072 r = 2;
1073 break;
1074 case preds_gr:
1075 r = 3;
1076 break;
1077 case unat_gr:
1078 r = 4;
1079 break;
1080 case lc_gr:
1081 r = 5;
1082 break;
1083 case rp_br:
1084 r = 6;
1085 break;
1086 case rnat_gr:
1087 r = 7;
1088 break;
1089 case bsp_gr:
1090 r = 8;
1091 break;
1092 case bspstore_gr:
1093 r = 9;
1094 break;
1095 case fpsr_gr:
1096 r = 10;
1097 break;
1098 case priunat_gr:
1099 r = 11;
1100 break;
1101 default:
1102 as_bad ("Invalid record type for P3 format.");
542d6675 1103 }
800eeca4
JW		 1104 bytes[0] = (UNW_P3 | (r >> 1));
1105 bytes[1] = (((r & 1) << 7) | reg);
1106 (*f) (2, bytes, NULL);
1107}
1108
800eeca4 1109static void
e0c9811a 1110output_P4_format (f, imask, imask_size)
800eeca4 1111 vbyte_func f;
e0c9811a
JW		 1112 unsigned char *imask;
1113 unsigned long imask_size;
800eeca4 1114{
e0c9811a
JW		 1115 imask[0] = UNW_P4;
1116 (*f) (imask_size, imask, NULL);
800eeca4
JW		 1117}
1118
1119static void
1120output_P5_format (f, grmask, frmask)
1121 vbyte_func f;
1122 int grmask;
1123 unsigned long frmask;
1124{
1125 char bytes[4];
1126 grmask = (grmask & 0x0f);
1127
1128 bytes[0] = UNW_P5;
1129 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1130 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1131 bytes[3] = (frmask & 0x000000ff);
1132 (*f) (4, bytes, NULL);
1133}
1134
1135static void
1136output_P6_format (f, rtype, rmask)
1137 vbyte_func f;
1138 unw_record_type rtype;
1139 int rmask;
1140{
1141 char byte;
e0c9811a 1142 int r = 0;
197865e8 1143
e0c9811a
JW		 1144 if (rtype == gr_mem)
1145 r = 1;
1146 else if (rtype != fr_mem)
1147 as_bad ("Invalid record type for format P6");
800eeca4
JW		 1148 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1149 (*f) (1, &byte, NULL);
1150}
1151
1152static void
1153output_P7_format (f, rtype, w1, w2)
1154 vbyte_func f;
1155 unw_record_type rtype;
1156 unsigned long w1;
1157 unsigned long w2;
1158{
1159 char bytes[20];
1160 int count = 1;
e0c9811a 1161 int r = 0;
800eeca4
JW		 1162 count += output_leb128 (bytes + 1, w1, 0);
1163 switch (rtype)
1164 {
542d6675
KH		 1165 case mem_stack_f:
1166 r = 0;
1167 count += output_leb128 (bytes + count, w2 >> 4, 0);
1168 break;
1169 case mem_stack_v:
1170 r = 1;
1171 break;
1172 case spill_base:
1173 r = 2;
1174 break;
1175 case psp_sprel:
1176 r = 3;
1177 break;
1178 case rp_when:
1179 r = 4;
1180 break;
1181 case rp_psprel:
1182 r = 5;
1183 break;
1184 case pfs_when:
1185 r = 6;
1186 break;
1187 case pfs_psprel:
1188 r = 7;
1189 break;
1190 case preds_when:
1191 r = 8;
1192 break;
1193 case preds_psprel:
1194 r = 9;
1195 break;
1196 case lc_when:
1197 r = 10;
1198 break;
1199 case lc_psprel:
1200 r = 11;
1201 break;
1202 case unat_when:
1203 r = 12;
1204 break;
1205 case unat_psprel:
1206 r = 13;
1207 break;
1208 case fpsr_when:
1209 r = 14;
1210 break;
1211 case fpsr_psprel:
1212 r = 15;
1213 break;
1214 default:
1215 break;
800eeca4
JW		 1216 }
1217 bytes[0] = (UNW_P7 | r);
1218 (*f) (count, bytes, NULL);
1219}
1220
1221static void
1222output_P8_format (f, rtype, t)
1223 vbyte_func f;
1224 unw_record_type rtype;
1225 unsigned long t;
1226{
1227 char bytes[20];
e0c9811a 1228 int r = 0;
800eeca4
JW		 1229 int count = 2;
1230 bytes[0] = UNW_P8;
1231 switch (rtype)
1232 {
542d6675
KH		 1233 case rp_sprel:
1234 r = 1;
1235 break;
1236 case pfs_sprel:
1237 r = 2;
1238 break;
1239 case preds_sprel:
1240 r = 3;
1241 break;
1242 case lc_sprel:
1243 r = 4;
1244 break;
1245 case unat_sprel:
1246 r = 5;
1247 break;
1248 case fpsr_sprel:
1249 r = 6;
1250 break;
1251 case bsp_when:
1252 r = 7;
1253 break;
1254 case bsp_psprel:
1255 r = 8;
1256 break;
1257 case bsp_sprel:
1258 r = 9;
1259 break;
1260 case bspstore_when:
1261 r = 10;
1262 break;
1263 case bspstore_psprel:
1264 r = 11;
1265 break;
1266 case bspstore_sprel:
1267 r = 12;
1268 break;
1269 case rnat_when:
1270 r = 13;
1271 break;
1272 case rnat_psprel:
1273 r = 14;
1274 break;
1275 case rnat_sprel:
1276 r = 15;
1277 break;
1278 case priunat_when_gr:
1279 r = 16;
1280 break;
1281 case priunat_psprel:
1282 r = 17;
1283 break;
1284 case priunat_sprel:
1285 r = 18;
1286 break;
1287 case priunat_when_mem:
1288 r = 19;
1289 break;
1290 default:
1291 break;
800eeca4
JW		 1292 }
1293 bytes[1] = r;
1294 count += output_leb128 (bytes + 2, t, 0);
1295 (*f) (count, bytes, NULL);
1296}
1297
1298static void
1299output_P9_format (f, grmask, gr)
1300 vbyte_func f;
1301 int grmask;
1302 int gr;
1303{
1304 char bytes[3];
1305 bytes[0] = UNW_P9;
1306 bytes[1] = (grmask & 0x0f);
1307 bytes[2] = (gr & 0x7f);
1308 (*f) (3, bytes, NULL);
1309}
1310
1311static void
1312output_P10_format (f, abi, context)
1313 vbyte_func f;
1314 int abi;
1315 int context;
1316{
1317 char bytes[3];
1318 bytes[0] = UNW_P10;
1319 bytes[1] = (abi & 0xff);
1320 bytes[2] = (context & 0xff);
1321 (*f) (3, bytes, NULL);
1322}
1323
1324static void
1325output_B1_format (f, rtype, label)
1326 vbyte_func f;
1327 unw_record_type rtype;
1328 unsigned long label;
1329{
1330 char byte;
e0c9811a 1331 int r = 0;
197865e8 1332 if (label > 0x1f)
800eeca4
JW		 1333 {
1334 output_B4_format (f, rtype, label);
1335 return;
1336 }
e0c9811a
JW		 1337 if (rtype == copy_state)
1338 r = 1;
1339 else if (rtype != label_state)
1340 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1341
1342 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1343 (*f) (1, &byte, NULL);
1344}
1345
1346static void
1347output_B2_format (f, ecount, t)
1348 vbyte_func f;
1349 unsigned long ecount;
1350 unsigned long t;
1351{
1352 char bytes[20];
1353 int count = 1;
1354 if (ecount > 0x1f)
1355 {
1356 output_B3_format (f, ecount, t);
1357 return;
1358 }
1359 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1360 count += output_leb128 (bytes + 1, t, 0);
1361 (*f) (count, bytes, NULL);
1362}
1363
1364static void
1365output_B3_format (f, ecount, t)
1366 vbyte_func f;
1367 unsigned long ecount;
1368 unsigned long t;
1369{
1370 char bytes[20];
1371 int count = 1;
1372 if (ecount <= 0x1f)
1373 {
1374 output_B2_format (f, ecount, t);
1375 return;
1376 }
1377 bytes[0] = UNW_B3;
1378 count += output_leb128 (bytes + 1, t, 0);
1379 count += output_leb128 (bytes + count, ecount, 0);
1380 (*f) (count, bytes, NULL);
1381}
1382
1383static void
1384output_B4_format (f, rtype, label)
1385 vbyte_func f;
1386 unw_record_type rtype;
1387 unsigned long label;
1388{
1389 char bytes[20];
e0c9811a 1390 int r = 0;
800eeca4 1391 int count = 1;
197865e8 1392 if (label <= 0x1f)
800eeca4
JW		 1393 {
1394 output_B1_format (f, rtype, label);
1395 return;
1396 }
197865e8 1397
e0c9811a
JW		 1398 if (rtype == copy_state)
1399 r = 1;
1400 else if (rtype != label_state)
1401 as_bad ("Invalid record type for format B1");
800eeca4
JW		 1402
1403 bytes[0] = (UNW_B4 | (r << 3));
1404 count += output_leb128 (bytes + 1, label, 0);
1405 (*f) (count, bytes, NULL);
1406}
1407
1408static char
e0c9811a 1409format_ab_reg (ab, reg)
542d6675
KH		 1410 int ab;
1411 int reg;
800eeca4
JW		 1412{
1413 int ret;
e0c9811a 1414 ab = (ab & 3);
800eeca4 1415 reg = (reg & 0x1f);
e0c9811a 1416 ret = (ab << 5) | reg;
800eeca4
JW		 1417 return ret;
1418}
1419
1420static void
e0c9811a 1421output_X1_format (f, rtype, ab, reg, t, w1)
800eeca4
JW		 1422 vbyte_func f;
1423 unw_record_type rtype;
e0c9811a 1424 int ab, reg;
800eeca4
JW		 1425 unsigned long t;
1426 unsigned long w1;
1427{
1428 char bytes[20];
e0c9811a 1429 int r = 0;
800eeca4
JW		 1430 int count = 2;
1431 bytes[0] = UNW_X1;
197865e8 1432
e0c9811a
JW		 1433 if (rtype == spill_sprel)
1434 r = 1;
1435 else if (rtype != spill_psprel)
1436 as_bad ("Invalid record type for format X1");
1437 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1438 count += output_leb128 (bytes + 2, t, 0);
1439 count += output_leb128 (bytes + count, w1, 0);
1440 (*f) (count, bytes, NULL);
1441}
1442
1443static void
e0c9811a 1444output_X2_format (f, ab, reg, x, y, treg, t)
800eeca4 1445 vbyte_func f;
e0c9811a 1446 int ab, reg;
800eeca4
JW		 1447 int x, y, treg;
1448 unsigned long t;
1449{
1450 char bytes[20];
800eeca4
JW		 1451 int count = 3;
1452 bytes[0] = UNW_X2;
e0c9811a 1453 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1454 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1455 count += output_leb128 (bytes + 3, t, 0);
1456 (*f) (count, bytes, NULL);
1457}
1458
1459static void
e0c9811a 1460output_X3_format (f, rtype, qp, ab, reg, t, w1)
800eeca4
JW		 1461 vbyte_func f;
1462 unw_record_type rtype;
1463 int qp;
e0c9811a 1464 int ab, reg;
800eeca4
JW		 1465 unsigned long t;
1466 unsigned long w1;
1467{
1468 char bytes[20];
e0c9811a 1469 int r = 0;
800eeca4 1470 int count = 3;
e0c9811a
JW		 1471 bytes[0] = UNW_X3;
1472
1473 if (rtype == spill_sprel_p)
1474 r = 1;
1475 else if (rtype != spill_psprel_p)
1476 as_bad ("Invalid record type for format X3");
800eeca4 1477 bytes[1] = ((r << 7) | (qp & 0x3f));
e0c9811a 1478 bytes[2] = format_ab_reg (ab, reg);
800eeca4
JW		 1479 count += output_leb128 (bytes + 3, t, 0);
1480 count += output_leb128 (bytes + count, w1, 0);
1481 (*f) (count, bytes, NULL);
1482}
1483
1484static void
e0c9811a 1485output_X4_format (f, qp, ab, reg, x, y, treg, t)
800eeca4
JW		 1486 vbyte_func f;
1487 int qp;
e0c9811a 1488 int ab, reg;
800eeca4
JW		 1489 int x, y, treg;
1490 unsigned long t;
1491{
1492 char bytes[20];
800eeca4 1493 int count = 4;
e0c9811a 1494 bytes[0] = UNW_X4;
800eeca4 1495 bytes[1] = (qp & 0x3f);
e0c9811a 1496 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
800eeca4
JW		 1497 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1498 count += output_leb128 (bytes + 4, t, 0);
1499 (*f) (count, bytes, NULL);
1500}
1501
1502/* This function allocates a record list structure, and initializes fields. */
542d6675 1503
800eeca4 1504static unw_rec_list *
197865e8 1505alloc_record (unw_record_type t)
800eeca4
JW		 1506{
1507 unw_rec_list *ptr;
1508 ptr = xmalloc (sizeof (*ptr));
1509 ptr->next = NULL;
1510 ptr->slot_number = SLOT_NUM_NOT_SET;
1511 ptr->r.type = t;
1512 return ptr;
1513}
1514
800eeca4 1515/* This function frees an entire list of record structures. */
542d6675 1516
800eeca4
JW		 1517void
1518free_list_records (unw_rec_list *first)
1519{
1520 unw_rec_list *ptr;
542d6675 1521 for (ptr = first; ptr != NULL;)
800eeca4
JW		 1522 {
1523 unw_rec_list *tmp = ptr;
e0c9811a
JW		 1524
1525 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1526 && tmp->r.record.r.mask.i)
1527 free (tmp->r.record.r.mask.i);
1528
800eeca4
JW		 1529 ptr = ptr->next;
1530 free (tmp);
1531 }
1532}
1533
1534static unw_rec_list *
1535output_prologue ()
1536{
1537 unw_rec_list *ptr = alloc_record (prologue);
e0c9811a 1538 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
800eeca4
JW		 1539 return ptr;
1540}
1541
1542static unw_rec_list *
1543output_prologue_gr (saved_mask, reg)
1544 unsigned int saved_mask;
1545 unsigned int reg;
1546{
1547 unw_rec_list *ptr = alloc_record (prologue_gr);
e0c9811a
JW		 1548 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1549 ptr->r.record.r.grmask = saved_mask;
800eeca4
JW		 1550 ptr->r.record.r.grsave = reg;
1551 return ptr;
1552}
1553
1554static unw_rec_list *
1555output_body ()
1556{
1557 unw_rec_list *ptr = alloc_record (body);
1558 return ptr;
1559}
1560
1561static unw_rec_list *
1562output_mem_stack_f (size)
1563 unsigned int size;
1564{
1565 unw_rec_list *ptr = alloc_record (mem_stack_f);
1566 ptr->r.record.p.size = size;
1567 return ptr;
1568}
1569
1570static unw_rec_list *
1571output_mem_stack_v ()
1572{
1573 unw_rec_list *ptr = alloc_record (mem_stack_v);
1574 return ptr;
1575}
1576
1577static unw_rec_list *
1578output_psp_gr (gr)
1579 unsigned int gr;
1580{
1581 unw_rec_list *ptr = alloc_record (psp_gr);
1582 ptr->r.record.p.gr = gr;
1583 return ptr;
1584}
1585
1586static unw_rec_list *
1587output_psp_sprel (offset)
1588 unsigned int offset;
1589{
1590 unw_rec_list *ptr = alloc_record (psp_sprel);
542d6675 1591 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1592 return ptr;
1593}
1594
1595static unw_rec_list *
1596output_rp_when ()
1597{
1598 unw_rec_list *ptr = alloc_record (rp_when);
1599 return ptr;
1600}
1601
1602static unw_rec_list *
1603output_rp_gr (gr)
1604 unsigned int gr;
1605{
1606 unw_rec_list *ptr = alloc_record (rp_gr);
1607 ptr->r.record.p.gr = gr;
1608 return ptr;
1609}
1610
1611static unw_rec_list *
1612output_rp_br (br)
1613 unsigned int br;
1614{
1615 unw_rec_list *ptr = alloc_record (rp_br);
1616 ptr->r.record.p.br = br;
1617 return ptr;
1618}
1619
1620static unw_rec_list *
1621output_rp_psprel (offset)
1622 unsigned int offset;
1623{
1624 unw_rec_list *ptr = alloc_record (rp_psprel);
542d6675 1625 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1626 return ptr;
1627}
1628
1629static unw_rec_list *
1630output_rp_sprel (offset)
1631 unsigned int offset;
1632{
1633 unw_rec_list *ptr = alloc_record (rp_sprel);
542d6675 1634 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1635 return ptr;
1636}
1637
1638static unw_rec_list *
1639output_pfs_when ()
1640{
1641 unw_rec_list *ptr = alloc_record (pfs_when);
1642 return ptr;
1643}
1644
1645static unw_rec_list *
1646output_pfs_gr (gr)
1647 unsigned int gr;
1648{
1649 unw_rec_list *ptr = alloc_record (pfs_gr);
1650 ptr->r.record.p.gr = gr;
1651 return ptr;
1652}
1653
1654static unw_rec_list *
1655output_pfs_psprel (offset)
1656 unsigned int offset;
1657{
1658 unw_rec_list *ptr = alloc_record (pfs_psprel);
542d6675 1659 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1660 return ptr;
1661}
1662
1663static unw_rec_list *
1664output_pfs_sprel (offset)
1665 unsigned int offset;
1666{
1667 unw_rec_list *ptr = alloc_record (pfs_sprel);
542d6675 1668 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1669 return ptr;
1670}
1671
1672static unw_rec_list *
1673output_preds_when ()
1674{
1675 unw_rec_list *ptr = alloc_record (preds_when);
1676 return ptr;
1677}
1678
1679static unw_rec_list *
1680output_preds_gr (gr)
1681 unsigned int gr;
1682{
1683 unw_rec_list *ptr = alloc_record (preds_gr);
1684 ptr->r.record.p.gr = gr;
1685 return ptr;
1686}
1687
1688static unw_rec_list *
1689output_preds_psprel (offset)
1690 unsigned int offset;
1691{
1692 unw_rec_list *ptr = alloc_record (preds_psprel);
542d6675 1693 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1694 return ptr;
1695}
1696
1697static unw_rec_list *
1698output_preds_sprel (offset)
1699 unsigned int offset;
1700{
1701 unw_rec_list *ptr = alloc_record (preds_sprel);
542d6675 1702 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1703 return ptr;
1704}
1705
1706static unw_rec_list *
1707output_fr_mem (mask)
1708 unsigned int mask;
1709{
1710 unw_rec_list *ptr = alloc_record (fr_mem);
1711 ptr->r.record.p.rmask = mask;
1712 return ptr;
1713}
1714
1715static unw_rec_list *
1716output_frgr_mem (gr_mask, fr_mask)
1717 unsigned int gr_mask;
1718 unsigned int fr_mask;
1719{
1720 unw_rec_list *ptr = alloc_record (frgr_mem);
1721 ptr->r.record.p.grmask = gr_mask;
1722 ptr->r.record.p.frmask = fr_mask;
1723 return ptr;
1724}
1725
1726static unw_rec_list *
1727output_gr_gr (mask, reg)
1728 unsigned int mask;
1729 unsigned int reg;
1730{
1731 unw_rec_list *ptr = alloc_record (gr_gr);
1732 ptr->r.record.p.grmask = mask;
1733 ptr->r.record.p.gr = reg;
1734 return ptr;
1735}
1736
1737static unw_rec_list *
1738output_gr_mem (mask)
1739 unsigned int mask;
1740{
1741 unw_rec_list *ptr = alloc_record (gr_mem);
1742 ptr->r.record.p.rmask = mask;
1743 return ptr;
1744}
1745
1746static unw_rec_list *
1747output_br_mem (unsigned int mask)
1748{
1749 unw_rec_list *ptr = alloc_record (br_mem);
1750 ptr->r.record.p.brmask = mask;
1751 return ptr;
1752}
1753
1754static unw_rec_list *
1755output_br_gr (save_mask, reg)
1756 unsigned int save_mask;
1757 unsigned int reg;
1758{
1759 unw_rec_list *ptr = alloc_record (br_gr);
1760 ptr->r.record.p.brmask = save_mask;
1761 ptr->r.record.p.gr = reg;
1762 return ptr;
1763}
1764
1765static unw_rec_list *
1766output_spill_base (offset)
1767 unsigned int offset;
1768{
1769 unw_rec_list *ptr = alloc_record (spill_base);
542d6675 1770 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1771 return ptr;
1772}
1773
1774static unw_rec_list *
1775output_unat_when ()
1776{
1777 unw_rec_list *ptr = alloc_record (unat_when);
1778 return ptr;
1779}
1780
1781static unw_rec_list *
1782output_unat_gr (gr)
1783 unsigned int gr;
1784{
1785 unw_rec_list *ptr = alloc_record (unat_gr);
1786 ptr->r.record.p.gr = gr;
1787 return ptr;
1788}
1789
1790static unw_rec_list *
1791output_unat_psprel (offset)
1792 unsigned int offset;
1793{
1794 unw_rec_list *ptr = alloc_record (unat_psprel);
542d6675 1795 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1796 return ptr;
1797}
1798
1799static unw_rec_list *
1800output_unat_sprel (offset)
1801 unsigned int offset;
1802{
1803 unw_rec_list *ptr = alloc_record (unat_sprel);
542d6675 1804 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1805 return ptr;
1806}
1807
1808static unw_rec_list *
1809output_lc_when ()
1810{
1811 unw_rec_list *ptr = alloc_record (lc_when);
1812 return ptr;
1813}
1814
1815static unw_rec_list *
1816output_lc_gr (gr)
1817 unsigned int gr;
1818{
1819 unw_rec_list *ptr = alloc_record (lc_gr);
1820 ptr->r.record.p.gr = gr;
1821 return ptr;
1822}
1823
1824static unw_rec_list *
1825output_lc_psprel (offset)
1826 unsigned int offset;
1827{
1828 unw_rec_list *ptr = alloc_record (lc_psprel);
542d6675 1829 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1830 return ptr;
1831}
1832
1833static unw_rec_list *
1834output_lc_sprel (offset)
1835 unsigned int offset;
1836{
1837 unw_rec_list *ptr = alloc_record (lc_sprel);
542d6675 1838 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1839 return ptr;
1840}
1841
1842static unw_rec_list *
1843output_fpsr_when ()
1844{
1845 unw_rec_list *ptr = alloc_record (fpsr_when);
1846 return ptr;
1847}
1848
1849static unw_rec_list *
1850output_fpsr_gr (gr)
1851 unsigned int gr;
1852{
1853 unw_rec_list *ptr = alloc_record (fpsr_gr);
1854 ptr->r.record.p.gr = gr;
1855 return ptr;
1856}
1857
1858static unw_rec_list *
1859output_fpsr_psprel (offset)
1860 unsigned int offset;
1861{
1862 unw_rec_list *ptr = alloc_record (fpsr_psprel);
542d6675 1863 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1864 return ptr;
1865}
1866
1867static unw_rec_list *
1868output_fpsr_sprel (offset)
1869 unsigned int offset;
1870{
1871 unw_rec_list *ptr = alloc_record (fpsr_sprel);
542d6675 1872 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1873 return ptr;
1874}
1875
1876static unw_rec_list *
1877output_priunat_when_gr ()
1878{
1879 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1880 return ptr;
1881}
1882
1883static unw_rec_list *
1884output_priunat_when_mem ()
1885{
1886 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1887 return ptr;
1888}
1889
1890static unw_rec_list *
1891output_priunat_gr (gr)
1892 unsigned int gr;
1893{
1894 unw_rec_list *ptr = alloc_record (priunat_gr);
1895 ptr->r.record.p.gr = gr;
1896 return ptr;
1897}
1898
1899static unw_rec_list *
1900output_priunat_psprel (offset)
1901 unsigned int offset;
1902{
1903 unw_rec_list *ptr = alloc_record (priunat_psprel);
542d6675 1904 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1905 return ptr;
1906}
1907
1908static unw_rec_list *
1909output_priunat_sprel (offset)
1910 unsigned int offset;
1911{
1912 unw_rec_list *ptr = alloc_record (priunat_sprel);
542d6675 1913 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1914 return ptr;
1915}
1916
1917static unw_rec_list *
1918output_bsp_when ()
1919{
1920 unw_rec_list *ptr = alloc_record (bsp_when);
1921 return ptr;
1922}
1923
1924static unw_rec_list *
1925output_bsp_gr (gr)
1926 unsigned int gr;
1927{
1928 unw_rec_list *ptr = alloc_record (bsp_gr);
1929 ptr->r.record.p.gr = gr;
1930 return ptr;
1931}
1932
1933static unw_rec_list *
1934output_bsp_psprel (offset)
1935 unsigned int offset;
1936{
1937 unw_rec_list *ptr = alloc_record (bsp_psprel);
542d6675 1938 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1939 return ptr;
1940}
1941
1942static unw_rec_list *
1943output_bsp_sprel (offset)
1944 unsigned int offset;
1945{
1946 unw_rec_list *ptr = alloc_record (bsp_sprel);
542d6675 1947 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1948 return ptr;
1949}
1950
1951static unw_rec_list *
1952output_bspstore_when ()
1953{
1954 unw_rec_list *ptr = alloc_record (bspstore_when);
1955 return ptr;
1956}
1957
1958static unw_rec_list *
1959output_bspstore_gr (gr)
1960 unsigned int gr;
1961{
1962 unw_rec_list *ptr = alloc_record (bspstore_gr);
1963 ptr->r.record.p.gr = gr;
1964 return ptr;
1965}
1966
1967static unw_rec_list *
1968output_bspstore_psprel (offset)
1969 unsigned int offset;
1970{
1971 unw_rec_list *ptr = alloc_record (bspstore_psprel);
542d6675 1972 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 1973 return ptr;
1974}
1975
1976static unw_rec_list *
1977output_bspstore_sprel (offset)
1978 unsigned int offset;
1979{
1980 unw_rec_list *ptr = alloc_record (bspstore_sprel);
542d6675 1981 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 1982 return ptr;
1983}
1984
1985static unw_rec_list *
1986output_rnat_when ()
1987{
1988 unw_rec_list *ptr = alloc_record (rnat_when);
1989 return ptr;
1990}
1991
1992static unw_rec_list *
1993output_rnat_gr (gr)
1994 unsigned int gr;
1995{
1996 unw_rec_list *ptr = alloc_record (rnat_gr);
1997 ptr->r.record.p.gr = gr;
1998 return ptr;
1999}
2000
2001static unw_rec_list *
2002output_rnat_psprel (offset)
2003 unsigned int offset;
2004{
2005 unw_rec_list *ptr = alloc_record (rnat_psprel);
542d6675 2006 ptr->r.record.p.pspoff = offset / 4;
800eeca4
JW		 2007 return ptr;
2008}
2009
2010static unw_rec_list *
2011output_rnat_sprel (offset)
2012 unsigned int offset;
2013{
2014 unw_rec_list *ptr = alloc_record (rnat_sprel);
542d6675 2015 ptr->r.record.p.spoff = offset / 4;
800eeca4
JW		 2016 return ptr;
2017}
2018
2019static unw_rec_list *
e0c9811a
JW		 2020output_unwabi (abi, context)
2021 unsigned long abi;
2022 unsigned long context;
800eeca4 2023{
e0c9811a
JW		 2024 unw_rec_list *ptr = alloc_record (unwabi);
2025 ptr->r.record.p.abi = abi;
2026 ptr->r.record.p.context = context;
800eeca4
JW		 2027 return ptr;
2028}
2029
2030static unw_rec_list *
e0c9811a 2031output_epilogue (unsigned long ecount)
800eeca4 2032{
e0c9811a
JW		 2033 unw_rec_list *ptr = alloc_record (epilogue);
2034 ptr->r.record.b.ecount = ecount;
800eeca4
JW		 2035 return ptr;
2036}
2037
2038static unw_rec_list *
e0c9811a 2039output_label_state (unsigned long label)
800eeca4 2040{
e0c9811a
JW		 2041 unw_rec_list *ptr = alloc_record (label_state);
2042 ptr->r.record.b.label = label;
800eeca4
JW		 2043 return ptr;
2044}
2045
2046static unw_rec_list *
e0c9811a
JW		 2047output_copy_state (unsigned long label)
2048{
2049 unw_rec_list *ptr = alloc_record (copy_state);
2050 ptr->r.record.b.label = label;
2051 return ptr;
2052}
2053
2054static unw_rec_list *
2055output_spill_psprel (ab, reg, offset)
2056 unsigned int ab;
800eeca4
JW		 2057 unsigned int reg;
2058 unsigned int offset;
2059{
2060 unw_rec_list *ptr = alloc_record (spill_psprel);
e0c9811a 2061 ptr->r.record.x.ab = ab;
800eeca4 2062 ptr->r.record.x.reg = reg;
542d6675 2063 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2064 return ptr;
2065}
2066
2067static unw_rec_list *
e0c9811a
JW		 2068output_spill_sprel (ab, reg, offset)
2069 unsigned int ab;
800eeca4
JW		 2070 unsigned int reg;
2071 unsigned int offset;
2072{
2073 unw_rec_list *ptr = alloc_record (spill_sprel);
e0c9811a 2074 ptr->r.record.x.ab = ab;
800eeca4 2075 ptr->r.record.x.reg = reg;
542d6675 2076 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2077 return ptr;
2078}
2079
2080static unw_rec_list *
e0c9811a
JW		 2081output_spill_psprel_p (ab, reg, offset, predicate)
2082 unsigned int ab;
800eeca4
JW		 2083 unsigned int reg;
2084 unsigned int offset;
2085 unsigned int predicate;
2086{
2087 unw_rec_list *ptr = alloc_record (spill_psprel_p);
e0c9811a 2088 ptr->r.record.x.ab = ab;
800eeca4 2089 ptr->r.record.x.reg = reg;
542d6675 2090 ptr->r.record.x.pspoff = offset / 4;
800eeca4
JW		 2091 ptr->r.record.x.qp = predicate;
2092 return ptr;
2093}
2094
2095static unw_rec_list *
e0c9811a
JW		 2096output_spill_sprel_p (ab, reg, offset, predicate)
2097 unsigned int ab;
800eeca4
JW		 2098 unsigned int reg;
2099 unsigned int offset;
2100 unsigned int predicate;
2101{
2102 unw_rec_list *ptr = alloc_record (spill_sprel_p);
e0c9811a 2103 ptr->r.record.x.ab = ab;
800eeca4 2104 ptr->r.record.x.reg = reg;
542d6675 2105 ptr->r.record.x.spoff = offset / 4;
800eeca4
JW		 2106 ptr->r.record.x.qp = predicate;
2107 return ptr;
2108}
2109
2110static unw_rec_list *
e0c9811a
JW		 2111output_spill_reg (ab, reg, targ_reg, xy)
2112 unsigned int ab;
800eeca4
JW		 2113 unsigned int reg;
2114 unsigned int targ_reg;
2115 unsigned int xy;
2116{
2117 unw_rec_list *ptr = alloc_record (spill_reg);
e0c9811a 2118 ptr->r.record.x.ab = ab;
800eeca4
JW		 2119 ptr->r.record.x.reg = reg;
2120 ptr->r.record.x.treg = targ_reg;
2121 ptr->r.record.x.xy = xy;
2122 return ptr;
2123}
2124
2125static unw_rec_list *
e0c9811a
JW		 2126output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2127 unsigned int ab;
800eeca4
JW		 2128 unsigned int reg;
2129 unsigned int targ_reg;
2130 unsigned int xy;
2131 unsigned int predicate;
2132{
2133 unw_rec_list *ptr = alloc_record (spill_reg_p);
e0c9811a 2134 ptr->r.record.x.ab = ab;
800eeca4
JW		 2135 ptr->r.record.x.reg = reg;
2136 ptr->r.record.x.treg = targ_reg;
2137 ptr->r.record.x.xy = xy;
2138 ptr->r.record.x.qp = predicate;
2139 return ptr;
2140}
2141
197865e8 2142/* Given a unw_rec_list process the correct format with the
800eeca4 2143 specified function. */
542d6675 2144
800eeca4
JW		 2145static void
2146process_one_record (ptr, f)
2147 unw_rec_list *ptr;
2148 vbyte_func f;
2149{
e0c9811a
JW		 2150 unsigned long fr_mask, gr_mask;
2151
197865e8 2152 switch (ptr->r.type)
800eeca4 2153 {
542d6675
KH		 2154 case gr_mem:
2155 case fr_mem:
2156 case br_mem:
2157 case frgr_mem:
2158 /* These are taken care of by prologue/prologue_gr. */
2159 break;
e0c9811a 2160
542d6675
KH		 2161 case prologue_gr:
2162 case prologue:
2163 if (ptr->r.type == prologue_gr)
2164 output_R2_format (f, ptr->r.record.r.grmask,
2165 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2166 else
800eeca4 2167 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
542d6675
KH		 2168
2169 /* Output descriptor(s) for union of register spills (if any). */
2170 gr_mask = ptr->r.record.r.mask.gr_mem;
2171 fr_mask = ptr->r.record.r.mask.fr_mem;
2172 if (fr_mask)
2173 {
2174 if ((fr_mask & ~0xfUL) == 0)
2175 output_P6_format (f, fr_mem, fr_mask);
2176 else
2177 {
2178 output_P5_format (f, gr_mask, fr_mask);
2179 gr_mask = 0;
2180 }
2181 }
2182 if (gr_mask)
2183 output_P6_format (f, gr_mem, gr_mask);
2184 if (ptr->r.record.r.mask.br_mem)
2185 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2186
2187 /* output imask descriptor if necessary: */
2188 if (ptr->r.record.r.mask.i)
2189 output_P4_format (f, ptr->r.record.r.mask.i,
2190 ptr->r.record.r.imask_size);
2191 break;
2192
2193 case body:
2194 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2195 break;
2196 case mem_stack_f:
2197 case mem_stack_v:
2198 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2199 ptr->r.record.p.size);
2200 break;
2201 case psp_gr:
2202 case rp_gr:
2203 case pfs_gr:
2204 case preds_gr:
2205 case unat_gr:
2206 case lc_gr:
2207 case fpsr_gr:
2208 case priunat_gr:
2209 case bsp_gr:
2210 case bspstore_gr:
2211 case rnat_gr:
2212 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2213 break;
2214 case rp_br:
2215 output_P3_format (f, rp_br, ptr->r.record.p.br);
2216 break;
2217 case psp_sprel:
2218 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2219 break;
2220 case rp_when:
2221 case pfs_when:
2222 case preds_when:
2223 case unat_when:
2224 case lc_when:
2225 case fpsr_when:
2226 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2227 break;
2228 case rp_psprel:
2229 case pfs_psprel:
2230 case preds_psprel:
2231 case unat_psprel:
2232 case lc_psprel:
2233 case fpsr_psprel:
2234 case spill_base:
2235 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2236 break;
2237 case rp_sprel:
2238 case pfs_sprel:
2239 case preds_sprel:
2240 case unat_sprel:
2241 case lc_sprel:
2242 case fpsr_sprel:
2243 case priunat_sprel:
2244 case bsp_sprel:
2245 case bspstore_sprel:
2246 case rnat_sprel:
2247 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2248 break;
2249 case gr_gr:
2250 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2251 break;
2252 case br_gr:
2253 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2254 break;
2255 case spill_mask:
2256 as_bad ("spill_mask record unimplemented.");
2257 break;
2258 case priunat_when_gr:
2259 case priunat_when_mem:
2260 case bsp_when:
2261 case bspstore_when:
2262 case rnat_when:
2263 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2264 break;
2265 case priunat_psprel:
2266 case bsp_psprel:
2267 case bspstore_psprel:
2268 case rnat_psprel:
2269 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2270 break;
2271 case unwabi:
2272 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2273 break;
2274 case epilogue:
2275 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2276 break;
2277 case label_state:
2278 case copy_state:
2279 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2280 break;
2281 case spill_psprel:
2282 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2283 ptr->r.record.x.reg, ptr->r.record.x.t,
2284 ptr->r.record.x.pspoff);
2285 break;
2286 case spill_sprel:
2287 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2288 ptr->r.record.x.reg, ptr->r.record.x.t,
2289 ptr->r.record.x.spoff);
2290 break;
2291 case spill_reg:
2292 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2293 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2294 ptr->r.record.x.treg, ptr->r.record.x.t);
2295 break;
2296 case spill_psprel_p:
2297 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2298 ptr->r.record.x.ab, ptr->r.record.x.reg,
2299 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2300 break;
2301 case spill_sprel_p:
2302 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2303 ptr->r.record.x.ab, ptr->r.record.x.reg,
2304 ptr->r.record.x.t, ptr->r.record.x.spoff);
2305 break;
2306 case spill_reg_p:
2307 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2308 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2309 ptr->r.record.x.xy, ptr->r.record.x.treg,
2310 ptr->r.record.x.t);
2311 break;
2312 default:
2313 as_bad ("record_type_not_valid");
2314 break;
800eeca4
JW		 2315 }
2316}
2317
197865e8 2318/* Given a unw_rec_list list, process all the records with
800eeca4
JW		 2319 the specified function. */
2320static void
2321process_unw_records (list, f)
2322 unw_rec_list *list;
2323 vbyte_func f;
2324{
2325 unw_rec_list *ptr;
2326 for (ptr = list; ptr; ptr = ptr->next)
2327 process_one_record (ptr, f);
2328}
2329
2330/* Determine the size of a record list in bytes. */
2331static int
2332calc_record_size (list)
2333 unw_rec_list *list;
2334{
2335 vbyte_count = 0;
2336 process_unw_records (list, count_output);
2337 return vbyte_count;
2338}
2339
e0c9811a
JW		 2340/* Update IMASK bitmask to reflect the fact that one or more registers
2341 of type TYPE are saved starting at instruction with index T. If N
2342 bits are set in REGMASK, it is assumed that instructions T through
2343 T+N-1 save these registers.
2344
2345 TYPE values:
2346 0: no save
2347 1: instruction saves next fp reg
2348 2: instruction saves next general reg
2349 3: instruction saves next branch reg */
2350static void
2351set_imask (region, regmask, t, type)
2352 unw_rec_list *region;
2353 unsigned long regmask;
2354 unsigned long t;
2355 unsigned int type;
2356{
2357 unsigned char *imask;
2358 unsigned long imask_size;
2359 unsigned int i;
2360 int pos;
2361
2362 imask = region->r.record.r.mask.i;
2363 imask_size = region->r.record.r.imask_size;
2364 if (!imask)
2365 {
542d6675 2366 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
e0c9811a
JW		 2367 imask = xmalloc (imask_size);
2368 memset (imask, 0, imask_size);
2369
2370 region->r.record.r.imask_size = imask_size;
2371 region->r.record.r.mask.i = imask;
2372 }
2373
542d6675
KH		 2374 i = (t / 4) + 1;
2375 pos = 2 * (3 - t % 4);
e0c9811a
JW		 2376 while (regmask)
2377 {
2378 if (i >= imask_size)
2379 {
2380 as_bad ("Ignoring attempt to spill beyond end of region");
2381 return;
2382 }
2383
2384 imask[i] |= (type & 0x3) << pos;
197865e8 2385
e0c9811a
JW		 2386 regmask &= (regmask - 1);
2387 pos -= 2;
2388 if (pos < 0)
2389 {
2390 pos = 0;
2391 ++i;
2392 }
2393 }
2394}
2395
2396static int
2397count_bits (unsigned long mask)
2398{
2399 int n = 0;
2400
2401 while (mask)
2402 {
2403 mask &= mask - 1;
2404 ++n;
2405 }
2406 return n;
2407}
2408
2409unsigned long
2410slot_index (unsigned long slot_addr, unsigned long first_addr)
2411{
542d6675 2412 return (3 * ((slot_addr >> 4) - (first_addr >> 4))
e0c9811a
JW		 2413 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2414}
2415
800eeca4
JW		 2416/* Given a complete record list, process any records which have
2417 unresolved fields, (ie length counts for a prologue). After
197865e8 2418 this has been run, all neccessary information should be available
800eeca4 2419 within each record to generate an image. */
542d6675 2420
800eeca4
JW		 2421static void
2422fixup_unw_records (list)
2423 unw_rec_list *list;
2424{
e0c9811a
JW		 2425 unw_rec_list *ptr, *region = 0;
2426 unsigned long first_addr = 0, rlen = 0, t;
2427
800eeca4
JW		 2428 for (ptr = list; ptr; ptr = ptr->next)
2429 {
2430 if (ptr->slot_number == SLOT_NUM_NOT_SET)
542d6675 2431 as_bad (" Insn slot not set in unwind record.");
e0c9811a 2432 t = slot_index (ptr->slot_number, first_addr);
800eeca4
JW		 2433 switch (ptr->r.type)
2434 {
542d6675
KH		 2435 case prologue:
2436 case prologue_gr:
2437 case body:
2438 {
2439 unw_rec_list *last;
2440 int size, dir_len = 0;
2441 unsigned long last_addr;
2442
2443 first_addr = ptr->slot_number;
2444 ptr->slot_number = 0;
2445 /* Find either the next body/prologue start, or the end of
2446 the list, and determine the size of the region. */
2447 last_addr = unwind.next_slot_number;
2448 for (last = ptr->next; last != NULL; last = last->next)
2449 if (last->r.type == prologue || last->r.type == prologue_gr
2450 || last->r.type == body)
2451 {
2452 last_addr = last->slot_number;
2453 break;
2454 }
2455 else if (!last->next)
2456 {
2457 /* In the absence of an explicit .body directive,
2458 the prologue ends after the last instruction
2459 covered by an unwind directive. */
2460 if (ptr->r.type != body)
2461 {
2462 last_addr = last->slot_number;
2463 switch (last->r.type)
2464 {
2465 case frgr_mem:
2466 dir_len = (count_bits (last->r.record.p.frmask)
2467 + count_bits (last->r.record.p.grmask));
2468 break;
2469 case fr_mem:
2470 case gr_mem:
2471 dir_len += count_bits (last->r.record.p.rmask);
2472 break;
2473 case br_mem:
2474 case br_gr:
2475 dir_len += count_bits (last->r.record.p.brmask);
2476 break;
2477 case gr_gr:
2478 dir_len += count_bits (last->r.record.p.grmask);
2479 break;
2480 default:
2481 dir_len = 1;
2482 break;
2483 }
2484 }
2485 break;
2486 }
2487 size = slot_index (last_addr, first_addr) + dir_len;
2488 rlen = ptr->r.record.r.rlen = size;
2489 region = ptr;
e0c9811a 2490 break;
542d6675
KH		 2491 }
2492 case epilogue:
2493 ptr->r.record.b.t = rlen - 1 - t;
2494 break;
e0c9811a 2495
542d6675
KH		 2496 case mem_stack_f:
2497 case mem_stack_v:
2498 case rp_when:
2499 case pfs_when:
2500 case preds_when:
2501 case unat_when:
2502 case lc_when:
2503 case fpsr_when:
2504 case priunat_when_gr:
2505 case priunat_when_mem:
2506 case bsp_when:
2507 case bspstore_when:
2508 case rnat_when:
2509 ptr->r.record.p.t = t;
2510 break;
e0c9811a 2511
542d6675
KH		 2512 case spill_reg:
2513 case spill_sprel:
2514 case spill_psprel:
2515 case spill_reg_p:
2516 case spill_sprel_p:
2517 case spill_psprel_p:
2518 ptr->r.record.x.t = t;
2519 break;
e0c9811a 2520
542d6675
KH		 2521 case frgr_mem:
2522 if (!region)
2523 {
2524 as_bad ("frgr_mem record before region record!\n");
2525 return;
2526 }
2527 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2528 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2529 set_imask (region, ptr->r.record.p.frmask, t, 1);
2530 set_imask (region, ptr->r.record.p.grmask, t, 2);
2531 break;
2532 case fr_mem:
2533 if (!region)
2534 {
2535 as_bad ("fr_mem record before region record!\n");
2536 return;
2537 }
2538 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2539 set_imask (region, ptr->r.record.p.rmask, t, 1);
2540 break;
2541 case gr_mem:
2542 if (!region)
2543 {
2544 as_bad ("gr_mem record before region record!\n");
2545 return;
2546 }
2547 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2548 set_imask (region, ptr->r.record.p.rmask, t, 2);
2549 break;
2550 case br_mem:
2551 if (!region)
2552 {
2553 as_bad ("br_mem record before region record!\n");
2554 return;
2555 }
2556 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2557 set_imask (region, ptr->r.record.p.brmask, t, 3);
2558 break;
e0c9811a 2559
542d6675
KH		 2560 case gr_gr:
2561 if (!region)
2562 {
2563 as_bad ("gr_gr record before region record!\n");
2564 return;
2565 }
2566 set_imask (region, ptr->r.record.p.grmask, t, 2);
2567 break;
2568 case br_gr:
2569 if (!region)
2570 {
2571 as_bad ("br_gr record before region record!\n");
2572 return;
2573 }
2574 set_imask (region, ptr->r.record.p.brmask, t, 3);
2575 break;
e0c9811a 2576
542d6675
KH		 2577 default:
2578 break;
800eeca4
JW		 2579 }
2580 }
2581}
2582
2583/* Generate an unwind image from a record list. Returns the number of
2584 bytes in the resulting image. The memory image itselof is returned
2585 in the 'ptr' parameter. */
2586static int
2587output_unw_records (list, ptr)
2588 unw_rec_list *list;
2589 void **ptr;
2590{
2591 int size, x, extra = 0;
2592 unsigned char *mem;
2593
2594 fixup_unw_records (list);
2595 size = calc_record_size (list);
2596
2597 /* pad to 8 byte boundry. */
2598 x = size % 8;
2599 if (x != 0)
2600 extra = 8 - x;
2601 /* Add 8 for the header + 8 more bytes for the personality offset. */
2602 mem = xmalloc (size + extra + 16);
2603
2604 vbyte_mem_ptr = mem + 8;
2605 /* Clear the padding area and personality. */
2606 memset (mem + 8 + size, 0 , extra + 8);
2607 /* Initialize the header area. */
efcc5914
JW		 2608 md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
2609 | (unwind.personality_routine
2610 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2611 : 0)
e4c58b25
JW		 2612 | ((size + extra) / 8)), /* length (dwords) */
2613 8);
800eeca4
JW		 2614
2615 process_unw_records (list, output_vbyte_mem);
2616
2617 *ptr = mem;
2618 return size + extra + 16;
2619}
2620
e0c9811a
JW		 2621static int
2622convert_expr_to_ab_reg (e, ab, regp)
2623 expressionS *e;
2624 unsigned int *ab;
2625 unsigned int *regp;
2626{
2627 unsigned int reg;
2628
2629 if (e->X_op != O_register)
2630 return 0;
2631
2632 reg = e->X_add_number;
2633 if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
2634 {
2635 *ab = 0;
2636 *regp = reg - REG_GR;
2637 }
2638 else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
2639 || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
2640 {
2641 *ab = 1;
2642 *regp = reg - REG_FR;
2643 }
2644 else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
2645 {
2646 *ab = 2;
2647 *regp = reg - REG_BR;
2648 }
2649 else
2650 {
2651 *ab = 3;
2652 switch (reg)
2653 {
2654 case REG_PR: *regp = 0; break;
2655 case REG_PSP: *regp = 1; break;
2656 case REG_PRIUNAT: *regp = 2; break;
2657 case REG_BR + 0: *regp = 3; break;
2658 case REG_AR + AR_BSP: *regp = 4; break;
2659 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2660 case REG_AR + AR_RNAT: *regp = 6; break;
2661 case REG_AR + AR_UNAT: *regp = 7; break;
2662 case REG_AR + AR_FPSR: *regp = 8; break;
2663 case REG_AR + AR_PFS: *regp = 9; break;
2664 case REG_AR + AR_LC: *regp = 10; break;
2665
2666 default:
2667 return 0;
2668 }
2669 }
2670 return 1;
197865e8 2671}
e0c9811a
JW		 2672
2673static int
2674convert_expr_to_xy_reg (e, xy, regp)
2675 expressionS *e;
2676 unsigned int *xy;
2677 unsigned int *regp;
2678{
2679 unsigned int reg;
2680
2681 if (e->X_op != O_register)
2682 return 0;
2683
2684 reg = e->X_add_number;
2685
2686 if (reg >= REG_GR && reg <= REG_GR + 127)
2687 {
2688 *xy = 0;
2689 *regp = reg - REG_GR;
2690 }
2691 else if (reg >= REG_FR && reg <= REG_FR + 127)
2692 {
2693 *xy = 1;
2694 *regp = reg - REG_FR;
2695 }
2696 else if (reg >= REG_BR && reg <= REG_BR + 7)
2697 {
2698 *xy = 2;
2699 *regp = reg - REG_BR;
2700 }
2701 else
2702 return -1;
2703 return 1;
197865e8 2704}
e0c9811a 2705
800eeca4
JW		 2706static void
2707dot_radix (dummy)
2708 int dummy;
2709{
2710 int radix;
2711
2712 SKIP_WHITESPACE ();
2713 radix = *input_line_pointer++;
2714
2715 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2716 {
2717 as_bad ("Radix `%c' unsupported", *input_line_pointer);
542d6675 2718 ignore_rest_of_line ();
800eeca4
JW		 2719 return;
2720 }
2721}
2722
2723/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2724static void
2725dot_special_section (which)
2726 int which;
2727{
2728 set_section ((char *) special_section_name[which]);
2729}
2730
2731static void
2732add_unwind_entry (ptr)
2733 unw_rec_list *ptr;
2734{
e0c9811a
JW		 2735 if (unwind.tail)
2736 unwind.tail->next = ptr;
800eeca4 2737 else
e0c9811a
JW		 2738 unwind.list = ptr;
2739 unwind.tail = ptr;
800eeca4
JW		 2740
2741 /* The current entry can in fact be a chain of unwind entries. */
e0c9811a
JW		 2742 if (unwind.current_entry == NULL)
2743 unwind.current_entry = ptr;
800eeca4
JW		 2744}
2745
197865e8 2746static void
800eeca4
JW		 2747dot_fframe (dummy)
2748 int dummy;
2749{
2750 expressionS e;
e0c9811a 2751
800eeca4 2752 parse_operand (&e);
197865e8 2753
800eeca4
JW		 2754 if (e.X_op != O_constant)
2755 as_bad ("Operand to .fframe must be a constant");
2756 else
e0c9811a
JW		 2757 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2758}
2759
197865e8 2760static void
e0c9811a
JW		 2761dot_vframe (dummy)
2762 int dummy;
2763{
2764 expressionS e;
2765 unsigned reg;
2766
2767 parse_operand (&e);
2768 reg = e.X_add_number - REG_GR;
2769 if (e.X_op == O_register && reg < 128)
800eeca4 2770 {
e0c9811a 2771 add_unwind_entry (output_mem_stack_v ());
30d25259
RH		 2772 if (! (unwind.prologue_mask & 2))
2773 add_unwind_entry (output_psp_gr (reg));
800eeca4 2774 }
e0c9811a
JW		 2775 else
2776 as_bad ("First operand to .vframe must be a general register");
800eeca4
JW		 2777}
2778
197865e8 2779static void
e0c9811a 2780dot_vframesp (dummy)
800eeca4
JW		 2781 int dummy;
2782{
e0c9811a
JW		 2783 expressionS e;
2784
2785 parse_operand (&e);
2786 if (e.X_op == O_constant)
2787 {
2788 add_unwind_entry (output_mem_stack_v ());
2789 add_unwind_entry (output_psp_sprel (e.X_add_number));
2790 }
2791 else
2792 as_bad ("First operand to .vframesp must be a general register");
2793}
2794
197865e8 2795static void
e0c9811a
JW		 2796dot_vframepsp (dummy)
2797 int dummy;
2798{
2799 expressionS e;
2800
2801 parse_operand (&e);
2802 if (e.X_op == O_constant)
2803 {
2804 add_unwind_entry (output_mem_stack_v ());
2805 add_unwind_entry (output_psp_sprel (e.X_add_number));
2806 }
2807 else
2808 as_bad ("First operand to .vframepsp must be a general register");
800eeca4
JW		 2809}
2810
197865e8 2811static void
800eeca4
JW		 2812dot_save (dummy)
2813 int dummy;
2814{
2815 expressionS e1, e2;
2816 int sep;
2817 int reg1, reg2;
2818
2819 sep = parse_operand (&e1);
2820 if (sep != ',')
2821 as_bad ("No second operand to .save");
2822 sep = parse_operand (&e2);
2823
e0c9811a 2824 reg1 = e1.X_add_number;
800eeca4 2825 reg2 = e2.X_add_number - REG_GR;
197865e8 2826
800eeca4 2827 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 2828 if (e1.X_op == O_register)
800eeca4 2829 {
542d6675 2830 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
800eeca4
JW		 2831 {
2832 switch (reg1)
2833 {
542d6675
KH		 2834 case REG_AR + AR_BSP:
2835 add_unwind_entry (output_bsp_when ());
2836 add_unwind_entry (output_bsp_gr (reg2));
2837 break;
2838 case REG_AR + AR_BSPSTORE:
2839 add_unwind_entry (output_bspstore_when ());
2840 add_unwind_entry (output_bspstore_gr (reg2));
2841 break;
2842 case REG_AR + AR_RNAT:
2843 add_unwind_entry (output_rnat_when ());
2844 add_unwind_entry (output_rnat_gr (reg2));
2845 break;
2846 case REG_AR + AR_UNAT:
2847 add_unwind_entry (output_unat_when ());
2848 add_unwind_entry (output_unat_gr (reg2));
2849 break;
2850 case REG_AR + AR_FPSR:
2851 add_unwind_entry (output_fpsr_when ());
2852 add_unwind_entry (output_fpsr_gr (reg2));
2853 break;
2854 case REG_AR + AR_PFS:
2855 add_unwind_entry (output_pfs_when ());
2856 if (! (unwind.prologue_mask & 4))
2857 add_unwind_entry (output_pfs_gr (reg2));
2858 break;
2859 case REG_AR + AR_LC:
2860 add_unwind_entry (output_lc_when ());
2861 add_unwind_entry (output_lc_gr (reg2));
2862 break;
2863 case REG_BR:
2864 add_unwind_entry (output_rp_when ());
2865 if (! (unwind.prologue_mask & 8))
2866 add_unwind_entry (output_rp_gr (reg2));
2867 break;
2868 case REG_PR:
2869 add_unwind_entry (output_preds_when ());
2870 if (! (unwind.prologue_mask & 1))
2871 add_unwind_entry (output_preds_gr (reg2));
2872 break;
2873 case REG_PRIUNAT:
2874 add_unwind_entry (output_priunat_when_gr ());
2875 add_unwind_entry (output_priunat_gr (reg2));
2876 break;
2877 default:
2878 as_bad ("First operand not a valid register");
800eeca4
JW		 2879 }
2880 }
2881 else
2882 as_bad (" Second operand not a valid register");
2883 }
2884 else
e0c9811a 2885 as_bad ("First operand not a register");
800eeca4
JW		 2886}
2887
197865e8 2888static void
800eeca4
JW		 2889dot_restore (dummy)
2890 int dummy;
2891{
e0c9811a
JW		 2892 expressionS e1, e2;
2893 unsigned long ecount = 0;
2894 int sep;
2895
2896 sep = parse_operand (&e1);
2897 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2898 {
2899 as_bad ("First operand to .restore must be stack pointer (sp)");
2900 return;
2901 }
2902
2903 if (sep == ',')
2904 {
2905 parse_operand (&e2);
2906 if (e1.X_op != O_constant)
2907 {
2908 as_bad ("Second operand to .restore must be constant");
2909 return;
2910 }
2911 ecount = e1.X_op;
2912 }
2913 add_unwind_entry (output_epilogue (ecount));
2914}
2915
197865e8 2916static void
e0c9811a
JW		 2917dot_restorereg (dummy)
2918 int dummy;
2919{
2920 unsigned int ab, reg;
2921 expressionS e;
2922
2923 parse_operand (&e);
2924
2925 if (!convert_expr_to_ab_reg (&e, &ab, &reg))
2926 {
2927 as_bad ("First operand to .restorereg must be a preserved register");
2928 return;
2929 }
2930 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
2931}
2932
197865e8 2933static void
e0c9811a
JW		 2934dot_restorereg_p (dummy)
2935 int dummy;
2936{
2937 unsigned int qp, ab, reg;
2938 expressionS e1, e2;
2939 int sep;
2940
2941 sep = parse_operand (&e1);
2942 if (sep != ',')
2943 {
2944 as_bad ("No second operand to .restorereg.p");
2945 return;
2946 }
2947
2948 parse_operand (&e2);
2949
2950 qp = e1.X_add_number - REG_P;
2951 if (e1.X_op != O_register || qp > 63)
2952 {
2953 as_bad ("First operand to .restorereg.p must be a predicate");
2954 return;
2955 }
2956
2957 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
2958 {
2959 as_bad ("Second operand to .restorereg.p must be a preserved register");
2960 return;
2961 }
2962 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
800eeca4
JW		 2963}
2964
2965static int
2966generate_unwind_image ()
2967{
2968 int size;
2969 unsigned char *unw_rec;
800eeca4 2970
10850f29
JW		 2971 /* Force out pending instructions, to make sure all unwind records have
2972 a valid slot_number field. */
2973 ia64_flush_insns ();
2974
800eeca4 2975 /* Generate the unwind record. */
150f24a2 2976 size = output_unw_records (unwind.list, (void **) &unw_rec);
e0c9811a
JW		 2977 if (size % 8 != 0)
2978 as_bad ("Unwind record is not a multiple of 8 bytes.");
800eeca4
JW		 2979
2980 /* If there are unwind records, switch sections, and output the info. */
2981 if (size != 0)
2982 {
800eeca4 2983 unsigned char *where;
800eeca4 2984 expressionS exp;
800eeca4
JW		 2985 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
2986
2987 /* Set expression which points to start of unwind descriptor area. */
e0c9811a 2988 unwind.info = expr_build_dot ();
800eeca4 2989
542d6675 2990 where = (unsigned char *) frag_more (size);
800eeca4
JW		 2991
2992 /* Issue a label for this address, and keep track of it to put it
2993 in the unwind section. */
2994
2995 /* Copy the information from the unwind record into this section. The
2996 data is already in the correct byte order. */
2997 memcpy (where, unw_rec, size);
2998 /* Add the personality address to the image. */
e0c9811a 2999 if (unwind.personality_routine != 0)
542d6675 3000 {
800eeca4 3001 exp.X_op = O_symbol;
e0c9811a 3002 exp.X_add_symbol = unwind.personality_routine;
800eeca4
JW		 3003 exp.X_add_number = 0;
3004 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
3005 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
e0c9811a 3006 unwind.personality_routine = 0;
542d6675 3007 }
800eeca4
JW		 3008 obj_elf_previous (0);
3009 }
3010
e0c9811a
JW		 3011 free_list_records (unwind.list);
3012 unwind.list = unwind.tail = unwind.current_entry = NULL;
800eeca4
JW		 3013
3014 return size;
3015}
3016
197865e8 3017static void
542d6675 3018dot_handlerdata (dummy)
800eeca4
JW		 3019 int dummy;
3020{
3021 generate_unwind_image ();
e0c9811a 3022 demand_empty_rest_of_line ();
800eeca4
JW		 3023}
3024
197865e8 3025static void
800eeca4
JW		 3026dot_unwentry (dummy)
3027 int dummy;
3028{
e0c9811a 3029 demand_empty_rest_of_line ();
800eeca4
JW		 3030}
3031
197865e8 3032static void
800eeca4
JW		 3033dot_altrp (dummy)
3034 int dummy;
3035{
e0c9811a
JW		 3036 expressionS e;
3037 unsigned reg;
3038
3039 parse_operand (&e);
3040 reg = e.X_add_number - REG_BR;
3041 if (e.X_op == O_register && reg < 8)
3042 add_unwind_entry (output_rp_br (reg));
3043 else
3044 as_bad ("First operand not a valid branch register");
800eeca4
JW		 3045}
3046
197865e8 3047static void
e0c9811a
JW		 3048dot_savemem (psprel)
3049 int psprel;
800eeca4
JW		 3050{
3051 expressionS e1, e2;
3052 int sep;
3053 int reg1, val;
3054
3055 sep = parse_operand (&e1);
3056 if (sep != ',')
e0c9811a 3057 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
800eeca4
JW		 3058 sep = parse_operand (&e2);
3059
e0c9811a 3060 reg1 = e1.X_add_number;
800eeca4 3061 val = e2.X_add_number;
197865e8 3062
800eeca4 3063 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
e0c9811a 3064 if (e1.X_op == O_register)
800eeca4
JW		 3065 {
3066 if (e2.X_op == O_constant)
3067 {
3068 switch (reg1)
3069 {
542d6675
KH		 3070 case REG_AR + AR_BSP:
3071 add_unwind_entry (output_bsp_when ());
3072 add_unwind_entry ((psprel
3073 ? output_bsp_psprel
3074 : output_bsp_sprel) (val));
3075 break;
3076 case REG_AR + AR_BSPSTORE:
3077 add_unwind_entry (output_bspstore_when ());
3078 add_unwind_entry ((psprel
3079 ? output_bspstore_psprel
3080 : output_bspstore_sprel) (val));
3081 break;
3082 case REG_AR + AR_RNAT:
3083 add_unwind_entry (output_rnat_when ());
3084 add_unwind_entry ((psprel
3085 ? output_rnat_psprel
3086 : output_rnat_sprel) (val));
3087 break;
3088 case REG_AR + AR_UNAT:
3089 add_unwind_entry (output_unat_when ());
3090 add_unwind_entry ((psprel
3091 ? output_unat_psprel
3092 : output_unat_sprel) (val));
3093 break;
3094 case REG_AR + AR_FPSR:
3095 add_unwind_entry (output_fpsr_when ());
3096 add_unwind_entry ((psprel
3097 ? output_fpsr_psprel
3098 : output_fpsr_sprel) (val));
3099 break;
3100 case REG_AR + AR_PFS:
3101 add_unwind_entry (output_pfs_when ());
3102 add_unwind_entry ((psprel
3103 ? output_pfs_psprel
3104 : output_pfs_sprel) (val));
3105 break;
3106 case REG_AR + AR_LC:
3107 add_unwind_entry (output_lc_when ());
3108 add_unwind_entry ((psprel
3109 ? output_lc_psprel
3110 : output_lc_sprel) (val));
3111 break;
3112 case REG_BR:
3113 add_unwind_entry (output_rp_when ());
3114 add_unwind_entry ((psprel
3115 ? output_rp_psprel
3116 : output_rp_sprel) (val));
3117 break;
3118 case REG_PR:
3119 add_unwind_entry (output_preds_when ());
3120 add_unwind_entry ((psprel
3121 ? output_preds_psprel
3122 : output_preds_sprel) (val));
3123 break;
3124 case REG_PRIUNAT:
3125 add_unwind_entry (output_priunat_when_mem ());
3126 add_unwind_entry ((psprel
3127 ? output_priunat_psprel
3128 : output_priunat_sprel) (val));
3129 break;
3130 default:
3131 as_bad ("First operand not a valid register");
800eeca4
JW		 3132 }
3133 }
3134 else
3135 as_bad (" Second operand not a valid constant");
3136 }
3137 else
e0c9811a 3138 as_bad ("First operand not a register");
800eeca4
JW		 3139}
3140
197865e8 3141static void
800eeca4
JW		 3142dot_saveg (dummy)
3143 int dummy;
3144{
3145 expressionS e1, e2;
3146 int sep;
3147 sep = parse_operand (&e1);
3148 if (sep == ',')
3149 parse_operand (&e2);
197865e8 3150
800eeca4
JW		 3151 if (e1.X_op != O_constant)
3152 as_bad ("First operand to .save.g must be a constant.");
3153 else
3154 {
3155 int grmask = e1.X_add_number;
3156 if (sep != ',')
3157 add_unwind_entry (output_gr_mem (grmask));
3158 else
542d6675 3159 {
800eeca4 3160 int reg = e2.X_add_number - REG_GR;
542d6675 3161 if (e2.X_op == O_register && reg >= 0 && reg < 128)
800eeca4
JW		 3162 add_unwind_entry (output_gr_gr (grmask, reg));
3163 else
3164 as_bad ("Second operand is an invalid register.");
3165 }
3166 }
3167}
3168
197865e8 3169static void
800eeca4
JW		 3170dot_savef (dummy)
3171 int dummy;
3172{
e0c9811a 3173 expressionS e1;
800eeca4
JW		 3174 int sep;
3175 sep = parse_operand (&e1);
197865e8 3176
800eeca4
JW		 3177 if (e1.X_op != O_constant)
3178 as_bad ("Operand to .save.f must be a constant.");
3179 else
e0c9811a 3180 add_unwind_entry (output_fr_mem (e1.X_add_number));
800eeca4
JW		 3181}
3182
197865e8 3183static void
800eeca4
JW		 3184dot_saveb (dummy)
3185 int dummy;
3186{
e0c9811a
JW		 3187 expressionS e1, e2;
3188 unsigned int reg;
3189 unsigned char sep;
3190 int brmask;
3191
800eeca4 3192 sep = parse_operand (&e1);
800eeca4 3193 if (e1.X_op != O_constant)
800eeca4 3194 {
e0c9811a
JW		 3195 as_bad ("First operand to .save.b must be a constant.");
3196 return;
800eeca4 3197 }
e0c9811a
JW		 3198 brmask = e1.X_add_number;
3199
3200 if (sep == ',')
3201 {
3202 sep = parse_operand (&e2);
3203 reg = e2.X_add_number - REG_GR;
3204 if (e2.X_op != O_register || reg > 127)
3205 {
3206 as_bad ("Second operand to .save.b must be a general register.");
3207 return;
3208 }
3209 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3210 }
3211 else
3212 add_unwind_entry (output_br_mem (brmask));
3213
3214 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3215 ignore_rest_of_line ();
800eeca4
JW		 3216}
3217
197865e8 3218static void
800eeca4
JW		 3219dot_savegf (dummy)
3220 int dummy;
3221{
3222 expressionS e1, e2;
3223 int sep;
3224 sep = parse_operand (&e1);
3225 if (sep == ',')
3226 parse_operand (&e2);
197865e8 3227
800eeca4
JW		 3228 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3229 as_bad ("Both operands of .save.gf must be constants.");
3230 else
3231 {
3232 int grmask = e1.X_add_number;
3233 int frmask = e2.X_add_number;
3234 add_unwind_entry (output_frgr_mem (grmask, frmask));
3235 }
3236}
3237
197865e8 3238static void
800eeca4
JW		 3239dot_spill (dummy)
3240 int dummy;
3241{
3242 expressionS e;
e0c9811a
JW		 3243 unsigned char sep;
3244
3245 sep = parse_operand (&e);
3246 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3247 ignore_rest_of_line ();
197865e8 3248
800eeca4
JW		 3249 if (e.X_op != O_constant)
3250 as_bad ("Operand to .spill must be a constant");
3251 else
e0c9811a
JW		 3252 add_unwind_entry (output_spill_base (e.X_add_number));
3253}
3254
3255static void
3256dot_spillreg (dummy)
3257 int dummy;
3258{
3259 int sep, ab, xy, reg, treg;
3260 expressionS e1, e2;
3261
3262 sep = parse_operand (&e1);
3263 if (sep != ',')
3264 {
3265 as_bad ("No second operand to .spillreg");
3266 return;
3267 }
3268
3269 parse_operand (&e2);
3270
3271 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
800eeca4 3272 {
e0c9811a
JW		 3273 as_bad ("First operand to .spillreg must be a preserved register");
3274 return;
800eeca4 3275 }
e0c9811a
JW		 3276
3277 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3278 {
3279 as_bad ("Second operand to .spillreg must be a register");
3280 return;
3281 }
3282
3283 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3284}
3285
3286static void
3287dot_spillmem (psprel)
3288 int psprel;
3289{
3290 expressionS e1, e2;
3291 int sep, ab, reg;
3292
3293 sep = parse_operand (&e1);
3294 if (sep != ',')
3295 {
3296 as_bad ("Second operand missing");
3297 return;
3298 }
3299
3300 parse_operand (&e2);
3301
3302 if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
3303 {
3304 as_bad ("First operand to .spill%s must be a preserved register",
3305 psprel ? "psp" : "sp");
3306 return;
3307 }
3308
3309 if (e2.X_op != O_constant)
3310 {
3311 as_bad ("Second operand to .spill%s must be a constant",
3312 psprel ? "psp" : "sp");
3313 return;
3314 }
3315
3316 if (psprel)
3317 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3318 else
3319 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3320}
3321
3322static void
3323dot_spillreg_p (dummy)
3324 int dummy;
3325{
3326 int sep, ab, xy, reg, treg;
3327 expressionS e1, e2, e3;
3328 unsigned int qp;
3329
3330 sep = parse_operand (&e1);
3331 if (sep != ',')
3332 {
3333 as_bad ("No second and third operand to .spillreg.p");
3334 return;
3335 }
3336
3337 sep = parse_operand (&e2);
3338 if (sep != ',')
3339 {
3340 as_bad ("No third operand to .spillreg.p");
3341 return;
3342 }
3343
3344 parse_operand (&e3);
3345
3346 qp = e1.X_add_number - REG_P;
3347
3348 if (e1.X_op != O_register || qp > 63)
3349 {
3350 as_bad ("First operand to .spillreg.p must be a predicate");
3351 return;
3352 }
3353
3354 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3355 {
3356 as_bad ("Second operand to .spillreg.p must be a preserved register");
3357 return;
3358 }
3359
3360 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3361 {
3362 as_bad ("Third operand to .spillreg.p must be a register");
3363 return;
3364 }
3365
3366 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3367}
3368
3369static void
3370dot_spillmem_p (psprel)
3371 int psprel;
3372{
3373 expressionS e1, e2, e3;
3374 int sep, ab, reg;
3375 unsigned int qp;
3376
3377 sep = parse_operand (&e1);
3378 if (sep != ',')
3379 {
3380 as_bad ("Second operand missing");
3381 return;
3382 }
3383
3384 parse_operand (&e2);
3385 if (sep != ',')
3386 {
3387 as_bad ("Second operand missing");
3388 return;
3389 }
3390
3391 parse_operand (&e3);
3392
3393 qp = e1.X_add_number - REG_P;
3394 if (e1.X_op != O_register || qp > 63)
3395 {
3396 as_bad ("First operand to .spill%s_p must be a predicate",
3397 psprel ? "psp" : "sp");
3398 return;
3399 }
3400
3401 if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
3402 {
3403 as_bad ("Second operand to .spill%s_p must be a preserved register",
3404 psprel ? "psp" : "sp");
3405 return;
3406 }
3407
3408 if (e3.X_op != O_constant)
3409 {
3410 as_bad ("Third operand to .spill%s_p must be a constant",
3411 psprel ? "psp" : "sp");
3412 return;
3413 }
3414
3415 if (psprel)
3416 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3417 else
3418 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3419}
3420
3421static void
3422dot_label_state (dummy)
3423 int dummy;
3424{
3425 expressionS e;
3426
3427 parse_operand (&e);
3428 if (e.X_op != O_constant)
3429 {
3430 as_bad ("Operand to .label_state must be a constant");
3431 return;
3432 }
3433 add_unwind_entry (output_label_state (e.X_add_number));
3434}
3435
3436static void
3437dot_copy_state (dummy)
3438 int dummy;
3439{
3440 expressionS e;
3441
3442 parse_operand (&e);
3443 if (e.X_op != O_constant)
3444 {
3445 as_bad ("Operand to .copy_state must be a constant");
3446 return;
3447 }
3448 add_unwind_entry (output_copy_state (e.X_add_number));
800eeca4
JW		 3449}
3450
197865e8 3451static void
800eeca4
JW		 3452dot_unwabi (dummy)
3453 int dummy;
3454{
e0c9811a
JW		 3455 expressionS e1, e2;
3456 unsigned char sep;
3457
3458 sep = parse_operand (&e1);
3459 if (sep != ',')
3460 {
3461 as_bad ("Second operand to .unwabi missing");
3462 return;
3463 }
3464 sep = parse_operand (&e2);
3465 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3466 ignore_rest_of_line ();
3467
3468 if (e1.X_op != O_constant)
3469 {
3470 as_bad ("First operand to .unwabi must be a constant");
3471 return;
3472 }
3473
3474 if (e2.X_op != O_constant)
3475 {
3476 as_bad ("Second operand to .unwabi must be a constant");
3477 return;
3478 }
3479
3480 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
800eeca4
JW		 3481}
3482
197865e8 3483static void
800eeca4
JW		 3484dot_personality (dummy)
3485 int dummy;
3486{
3487 char *name, *p, c;
3488 SKIP_WHITESPACE ();
3489 name = input_line_pointer;
3490 c = get_symbol_end ();
3491 p = input_line_pointer;
e0c9811a 3492 unwind.personality_routine = symbol_find_or_make (name);
800eeca4
JW		 3493 *p = c;
3494 SKIP_WHITESPACE ();
3495 demand_empty_rest_of_line ();
3496}
3497
3498static void
3499dot_proc (dummy)
3500 int dummy;
3501{
3502 char *name, *p, c;
3503 symbolS *sym;
3504
e0c9811a
JW		 3505 unwind.proc_start = expr_build_dot ();
3506 /* Parse names of main and alternate entry points and mark them as
542d6675 3507 function symbols: */
800eeca4
JW		 3508 while (1)
3509 {
3510 SKIP_WHITESPACE ();
3511 name = input_line_pointer;
3512 c = get_symbol_end ();
3513 p = input_line_pointer;
3514 sym = symbol_find_or_make (name);
e0c9811a 3515 if (unwind.proc_start == 0)
542d6675 3516 {
e0c9811a 3517 unwind.proc_start = sym;
800eeca4
JW		 3518 }
3519 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3520 *p = c;
3521 SKIP_WHITESPACE ();
3522 if (*input_line_pointer != ',')
3523 break;
3524 ++input_line_pointer;
3525 }
3526 demand_empty_rest_of_line ();
3527 ia64_do_align (16);
3528
e0c9811a
JW		 3529 unwind.list = unwind.tail = unwind.current_entry = NULL;
3530 unwind.personality_routine = 0;
800eeca4
JW		 3531}
3532
3533static void
3534dot_body (dummy)
3535 int dummy;
3536{
e0c9811a 3537 unwind.prologue = 0;
30d25259
RH		 3538 unwind.prologue_mask = 0;
3539
800eeca4 3540 add_unwind_entry (output_body ());
e0c9811a 3541 demand_empty_rest_of_line ();
800eeca4
JW		 3542}
3543
3544static void
3545dot_prologue (dummy)
3546 int dummy;
3547{
e0c9811a 3548 unsigned char sep;
30d25259 3549 int mask = 0, grsave;
e0c9811a 3550
e0c9811a 3551 if (!is_it_end_of_statement ())
800eeca4
JW		 3552 {
3553 expressionS e1, e2;
800eeca4
JW		 3554 sep = parse_operand (&e1);
3555 if (sep != ',')
3556 as_bad ("No second operand to .prologue");
3557 sep = parse_operand (&e2);
e0c9811a 3558 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
542d6675 3559 ignore_rest_of_line ();
800eeca4
JW		 3560
3561 if (e1.X_op == O_constant)
542d6675 3562 {
30d25259
RH		 3563 mask = e1.X_add_number;
3564
800eeca4 3565 if (e2.X_op == O_constant)
30d25259
RH		 3566 grsave = e2.X_add_number;
3567 else if (e2.X_op == O_register
3568 && (grsave = e2.X_add_number - REG_GR) < 128)
3569 ;
800eeca4 3570 else
30d25259
RH		 3571 as_bad ("Second operand not a constant or general register");
3572
3573 add_unwind_entry (output_prologue_gr (mask, grsave));
800eeca4
JW		 3574 }
3575 else
3576 as_bad ("First operand not a constant");
3577 }
3578 else
3579 add_unwind_entry (output_prologue ());
30d25259
RH		 3580
3581 unwind.prologue = 1;
3582 unwind.prologue_mask = mask;
800eeca4
JW		 3583}
3584
3585static void
3586dot_endp (dummy)
3587 int dummy;
3588{
3589 expressionS e;
3590 unsigned char *ptr;
800eeca4
JW		 3591 long where;
3592 segT saved_seg;
3593 subsegT saved_subseg;
3594
3595 saved_seg = now_seg;
3596 saved_subseg = now_subseg;
3597
3598 expression (&e);
3599 demand_empty_rest_of_line ();
3600
3601 insn_group_break (1, 0, 0);
800eeca4
JW		 3602
3603 /* If there was a .handlerdata, we haven't generated an image yet. */
e0c9811a 3604 if (unwind.info == 0)
800eeca4
JW		 3605 {
3606 generate_unwind_image ();
3607 }
3608
3609 subseg_set (md.last_text_seg, 0);
e0c9811a 3610 unwind.proc_end = expr_build_dot ();
800eeca4
JW		 3611
3612 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3613 ptr = frag_more (24);
3614 where = frag_now_fix () - 24;
3615
3616 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3617 e.X_op = O_pseudo_fixup;
3618 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3619 e.X_add_number = 0;
e0c9811a 3620 e.X_add_symbol = unwind.proc_start;
800eeca4
JW		 3621 ia64_cons_fix_new (frag_now, where, 8, &e);
3622
3623 e.X_op = O_pseudo_fixup;
3624 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3625 e.X_add_number = 0;
e0c9811a 3626 e.X_add_symbol = unwind.proc_end;
800eeca4
JW		 3627 ia64_cons_fix_new (frag_now, where + 8, 8, &e);
3628
e0c9811a 3629 if (unwind.info != 0)
800eeca4
JW		 3630 {
3631 e.X_op = O_pseudo_fixup;
3632 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3633 e.X_add_number = 0;
e0c9811a 3634 e.X_add_symbol = unwind.info;
800eeca4
JW		 3635 ia64_cons_fix_new (frag_now, where + 16, 8, &e);
3636 }
3637 else
3638 md_number_to_chars (ptr + 16, 0, 8);
3639
3640 subseg_set (saved_seg, saved_subseg);
e0c9811a 3641 unwind.proc_start = unwind.proc_end = unwind.info = 0;
800eeca4
JW		 3642}
3643
3644static void
3645dot_template (template)
3646 int template;
3647{
3648 CURR_SLOT.user_template = template;
3649}
3650
3651static void
3652dot_regstk (dummy)
3653 int dummy;
3654{
3655 int ins, locs, outs, rots;
3656
3657 if (is_it_end_of_statement ())
3658 ins = locs = outs = rots = 0;
3659 else
3660 {
3661 ins = get_absolute_expression ();
3662 if (*input_line_pointer++ != ',')
3663 goto err;
3664 locs = get_absolute_expression ();
3665 if (*input_line_pointer++ != ',')
3666 goto err;
3667 outs = get_absolute_expression ();
3668 if (*input_line_pointer++ != ',')
3669 goto err;
3670 rots = get_absolute_expression ();
3671 }
3672 set_regstack (ins, locs, outs, rots);
3673 return;
3674
3675 err:
3676 as_bad ("Comma expected");
3677 ignore_rest_of_line ();
3678}
3679
3680static void
3681dot_rot (type)
3682 int type;
3683{
3684 unsigned num_regs, num_alloced = 0;
3685 struct dynreg **drpp, *dr;
3686 int ch, base_reg = 0;
3687 char *name, *start;
3688 size_t len;
3689
3690 switch (type)
3691 {
3692 case DYNREG_GR: base_reg = REG_GR + 32; break;
3693 case DYNREG_FR: base_reg = REG_FR + 32; break;
3694 case DYNREG_PR: base_reg = REG_P + 16; break;
3695 default: break;
3696 }
3697
542d6675 3698 /* First, remove existing names from hash table. */
800eeca4
JW		 3699 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3700 {
3701 hash_delete (md.dynreg_hash, dr->name);
3702 dr->num_regs = 0;
3703 }
3704
3705 drpp = &md.dynreg[type];
3706 while (1)
3707 {
3708 start = input_line_pointer;
3709 ch = get_symbol_end ();
3710 *input_line_pointer = ch;
3711 len = (input_line_pointer - start);
3712
3713 SKIP_WHITESPACE ();
3714 if (*input_line_pointer != '[')
3715 {
3716 as_bad ("Expected '['");
3717 goto err;
3718 }
3719 ++input_line_pointer; /* skip '[' */
3720
3721 num_regs = get_absolute_expression ();
3722
3723 if (*input_line_pointer++ != ']')
3724 {
3725 as_bad ("Expected ']'");
3726 goto err;
3727 }
3728 SKIP_WHITESPACE ();
3729
3730 num_alloced += num_regs;
3731 switch (type)
3732 {
3733 case DYNREG_GR:
3734 if (num_alloced > md.rot.num_regs)
3735 {
3736 as_bad ("Used more than the declared %d rotating registers",
3737 md.rot.num_regs);
3738 goto err;
3739 }
3740 break;
3741 case DYNREG_FR:
3742 if (num_alloced > 96)
3743 {
3744 as_bad ("Used more than the available 96 rotating registers");
3745 goto err;
3746 }
3747 break;
3748 case DYNREG_PR:
3749 if (num_alloced > 48)
3750 {
3751 as_bad ("Used more than the available 48 rotating registers");
3752 goto err;
3753 }
3754 break;
3755
3756 default:
3757 break;
3758 }
3759
3760 name = obstack_alloc (&notes, len + 1);
3761 memcpy (name, start, len);
3762 name[len] = '\0';
3763
3764 if (!*drpp)
3765 {
3766 *drpp = obstack_alloc (&notes, sizeof (*dr));
3767 memset (*drpp, 0, sizeof (*dr));
3768 }
3769
3770 dr = *drpp;
3771 dr->name = name;
3772 dr->num_regs = num_regs;
3773 dr->base = base_reg;
3774 drpp = &dr->next;
3775 base_reg += num_regs;
3776
3777 if (hash_insert (md.dynreg_hash, name, dr))
3778 {
3779 as_bad ("Attempt to redefine register set `%s'", name);
3780 goto err;
3781 }
3782
3783 if (*input_line_pointer != ',')
3784 break;
3785 ++input_line_pointer; /* skip comma */
3786 SKIP_WHITESPACE ();
3787 }
3788 demand_empty_rest_of_line ();
3789 return;
3790
3791 err:
3792 ignore_rest_of_line ();
3793}
3794
3795static void
3796dot_byteorder (byteorder)
3797 int byteorder;
3798{
3799 target_big_endian = byteorder;
3800}
3801
3802static void
3803dot_psr (dummy)
3804 int dummy;
3805{
3806 char *option;
3807 int ch;
3808
3809 while (1)
3810 {
3811 option = input_line_pointer;
3812 ch = get_symbol_end ();
3813 if (strcmp (option, "lsb") == 0)
3814 md.flags &= ~EF_IA_64_BE;
3815 else if (strcmp (option, "msb") == 0)
3816 md.flags |= EF_IA_64_BE;
3817 else if (strcmp (option, "abi32") == 0)
3818 md.flags &= ~EF_IA_64_ABI64;
3819 else if (strcmp (option, "abi64") == 0)
3820 md.flags |= EF_IA_64_ABI64;
3821 else
3822 as_bad ("Unknown psr option `%s'", option);
3823 *input_line_pointer = ch;
3824
3825 SKIP_WHITESPACE ();
3826 if (*input_line_pointer != ',')
3827 break;
3828
3829 ++input_line_pointer;
3830 SKIP_WHITESPACE ();
3831 }
3832 demand_empty_rest_of_line ();
3833}
3834
3835static void
3836dot_alias (dummy)
3837 int dummy;
3838{
3839 as_bad (".alias not implemented yet");
3840}
3841
3842static void
3843dot_ln (dummy)
3844 int dummy;
3845{
3846 new_logical_line (0, get_absolute_expression ());
3847 demand_empty_rest_of_line ();
3848}
3849
542d6675 3850static char *
800eeca4
JW		 3851parse_section_name ()
3852{
3853 char *name;
3854 int len;
3855
3856 SKIP_WHITESPACE ();
3857 if (*input_line_pointer != '"')
3858 {
3859 as_bad ("Missing section name");
3860 ignore_rest_of_line ();
3861 return 0;
3862 }
3863 name = demand_copy_C_string (&len);
3864 if (!name)
3865 {
3866 ignore_rest_of_line ();
3867 return 0;
3868 }
3869 SKIP_WHITESPACE ();
3870 if (*input_line_pointer != ',')
3871 {
3872 as_bad ("Comma expected after section name");
3873 ignore_rest_of_line ();
3874 return 0;
3875 }
3876 ++input_line_pointer; /* skip comma */
3877 return name;
3878}
3879
3880static void
3881dot_xdata (size)
3882 int size;
3883{
3884 char *name = parse_section_name ();
3885 if (!name)
3886 return;
3887
3888 set_section (name);
3889 cons (size);
3890 obj_elf_previous (0);
3891}
3892
3893/* Why doesn't float_cons() call md_cons_align() the way cons() does? */
542d6675 3894
800eeca4
JW		 3895static void
3896stmt_float_cons (kind)
3897 int kind;
3898{
3899 size_t size;
3900
3901 switch (kind)
3902 {
3903 case 'd': size = 8; break;
3904 case 'x': size = 10; break;
3905
3906 case 'f':
3907 default:
3908 size = 4;
3909 break;
3910 }
3911 ia64_do_align (size);
3912 float_cons (kind);
3913}
3914
3915static void
3916stmt_cons_ua (size)
3917 int size;
3918{
3919 int saved_auto_align = md.auto_align;
3920
3921 md.auto_align = 0;
3922 cons (size);
3923 md.auto_align = saved_auto_align;
3924}
3925
3926static void
3927dot_xfloat_cons (kind)
3928 int kind;
3929{
3930 char *name = parse_section_name ();
3931 if (!name)
3932 return;
3933
3934 set_section (name);
3935 stmt_float_cons (kind);
3936 obj_elf_previous (0);
3937}
3938
3939static void
3940dot_xstringer (zero)
3941 int zero;
3942{
3943 char *name = parse_section_name ();
3944 if (!name)
3945 return;
3946
3947 set_section (name);
3948 stringer (zero);
3949 obj_elf_previous (0);
3950}
3951
3952static void
3953dot_xdata_ua (size)
3954 int size;
3955{
3956 int saved_auto_align = md.auto_align;
3957 char *name = parse_section_name ();
3958 if (!name)
3959 return;
3960
3961 set_section (name);
3962 md.auto_align = 0;
3963 cons (size);
3964 md.auto_align = saved_auto_align;
3965 obj_elf_previous (0);
3966}
3967
3968static void
3969dot_xfloat_cons_ua (kind)
3970 int kind;
3971{
3972 int saved_auto_align = md.auto_align;
3973 char *name = parse_section_name ();
3974 if (!name)
3975 return;
3976
3977 set_section (name);
3978 md.auto_align = 0;
3979 stmt_float_cons (kind);
3980 md.auto_align = saved_auto_align;
3981 obj_elf_previous (0);
3982}
3983
3984/* .reg.val <regname>,value */
542d6675 3985
800eeca4
JW		 3986static void
3987dot_reg_val (dummy)
542d6675 3988 int dummy;
800eeca4
JW		 3989{
3990 expressionS reg;
3991
3992 expression (&reg);
3993 if (reg.X_op != O_register)
3994 {
3995 as_bad (_("Register name expected"));
3996 ignore_rest_of_line ();
3997 }
3998 else if (*input_line_pointer++ != ',')
3999 {
4000 as_bad (_("Comma expected"));
4001 ignore_rest_of_line ();
4002 }
197865e8 4003 else
800eeca4
JW		 4004 {
4005 valueT value = get_absolute_expression ();
4006 int regno = reg.X_add_number;
542d6675
KH		 4007 if (regno < REG_GR || regno > REG_GR + 128)
4008 as_warn (_("Register value annotation ignored"));
800eeca4 4009 else
542d6675
KH		 4010 {
4011 gr_values[regno - REG_GR].known = 1;
4012 gr_values[regno - REG_GR].value = value;
4013 gr_values[regno - REG_GR].path = md.path;
4014 }
800eeca4
JW		 4015 }
4016 demand_empty_rest_of_line ();
4017}
4018
197865e8 4019/* select dv checking mode
800eeca4
JW		 4020 .auto
4021 .explicit
4022 .default
4023
197865e8 4024 A stop is inserted when changing modes
800eeca4 4025 */
542d6675 4026
800eeca4
JW		 4027static void
4028dot_dv_mode (type)
542d6675 4029 int type;
800eeca4
JW		 4030{
4031 if (md.manual_bundling)
4032 as_warn (_("Directive invalid within a bundle"));
4033
4034 if (type == 'E' || type == 'A')
4035 md.mode_explicitly_set = 0;
4036 else
4037 md.mode_explicitly_set = 1;
4038
4039 md.detect_dv = 1;
4040 switch (type)
4041 {
4042 case 'A':
4043 case 'a':
4044 if (md.explicit_mode)
542d6675 4045 insn_group_break (1, 0, 0);
800eeca4
JW		 4046 md.explicit_mode = 0;
4047 break;
4048 case 'E':
4049 case 'e':
4050 if (!md.explicit_mode)
542d6675 4051 insn_group_break (1, 0, 0);
800eeca4
JW		 4052 md.explicit_mode = 1;
4053 break;
4054 default:
4055 case 'd':
4056 if (md.explicit_mode != md.default_explicit_mode)
542d6675 4057 insn_group_break (1, 0, 0);
800eeca4
JW		 4058 md.explicit_mode = md.default_explicit_mode;
4059 md.mode_explicitly_set = 0;
4060 break;
4061 }
4062}
4063
4064static void
4065print_prmask (mask)
542d6675 4066 valueT mask;
800eeca4
JW		 4067{
4068 int regno;
4069 char *comma = "";
542d6675 4070 for (regno = 0; regno < 64; regno++)
800eeca4 4071 {
542d6675
KH		 4072 if (mask & ((valueT) 1 << regno))
4073 {
4074 fprintf (stderr, "%s p%d", comma, regno);
4075 comma = ",";
4076 }
800eeca4
JW		 4077 }
4078}
4079
4080/*
4081 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4082 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4083 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4084 .pred.safe_across_calls p1 [, p2 [,...]]
4085 */
542d6675 4086
800eeca4
JW		 4087static void
4088dot_pred_rel (type)
542d6675 4089 int type;
800eeca4
JW		 4090{
4091 valueT mask = 0;
4092 int count = 0;
4093 int p1 = -1, p2 = -1;
4094
4095 if (type == 0)
4096 {
4097 if (*input_line_pointer != '"')
542d6675
KH		 4098 {
4099 as_bad (_("Missing predicate relation type"));
4100 ignore_rest_of_line ();
4101 return;
4102 }
197865e8 4103 else
542d6675
KH		 4104 {
4105 int len;
4106 char *form = demand_copy_C_string (&len);
4107 if (strcmp (form, "mutex") == 0)
4108 type = 'm';
4109 else if (strcmp (form, "clear") == 0)
4110 type = 'c';
4111 else if (strcmp (form, "imply") == 0)
4112 type = 'i';
4113 else
4114 {
4115 as_bad (_("Unrecognized predicate relation type"));
4116 ignore_rest_of_line ();
4117 return;
4118 }
4119 }
800eeca4 4120 if (*input_line_pointer == ',')
542d6675 4121 ++input_line_pointer;
800eeca4
JW		 4122 SKIP_WHITESPACE ();
4123 }
4124
4125 SKIP_WHITESPACE ();
4126 while (1)
4127 {
4128 valueT bit = 1;
4129 int regno;
197865e8 4130
800eeca4 4131 if (toupper (*input_line_pointer) != 'P'
542d6675
KH		 4132 || (regno = atoi (++input_line_pointer)) < 0
4133 || regno > 63)
4134 {
4135 as_bad (_("Predicate register expected"));
4136 ignore_rest_of_line ();
4137 return;
4138 }
800eeca4 4139 while (isdigit (*input_line_pointer))
542d6675 4140 ++input_line_pointer;
800eeca4 4141 if (p1 == -1)
542d6675 4142 p1 = regno;
800eeca4 4143 else if (p2 == -1)
542d6675 4144 p2 = regno;
800eeca4
JW		 4145 bit <<= regno;
4146 if (mask & bit)
542d6675
KH		 4147 as_warn (_("Duplicate predicate register ignored"));
4148 mask |= bit;
4149 count++;
4150 /* See if it's a range. */
800eeca4 4151 if (*input_line_pointer == '-')
542d6675
KH		 4152 {
4153 valueT stop = 1;
4154 ++input_line_pointer;
4155
4156 if (toupper (*input_line_pointer) != 'P'
4157 || (regno = atoi (++input_line_pointer)) < 0
4158 || regno > 63)
4159 {
4160 as_bad (_("Predicate register expected"));
4161 ignore_rest_of_line ();
4162 return;
4163 }
4164 while (isdigit (*input_line_pointer))
4165 ++input_line_pointer;
4166 stop <<= regno;
4167 if (bit >= stop)
4168 {
4169 as_bad (_("Bad register range"));
4170 ignore_rest_of_line ();
4171 return;
4172 }
4173 while (bit < stop)
4174 {
4175 bit <<= 1;
4176 mask |= bit;
4177 count++;
4178 }
4179 SKIP_WHITESPACE ();
4180 }
800eeca4 4181 if (*input_line_pointer != ',')
542d6675 4182 break;
800eeca4
JW		 4183 ++input_line_pointer;
4184 SKIP_WHITESPACE ();
4185 }
4186
4187 switch (type)
4188 {
4189 case 'c':
4190 if (count == 0)
542d6675 4191 mask = ~(valueT) 0;
800eeca4 4192 clear_qp_mutex (mask);
197865e8 4193 clear_qp_implies (mask, (valueT) 0);
800eeca4
JW		 4194 break;
4195 case 'i':
4196 if (count != 2 || p1 == -1 || p2 == -1)
542d6675 4197 as_bad (_("Predicate source and target required"));
800eeca4 4198 else if (p1 == 0 || p2 == 0)
542d6675 4199 as_bad (_("Use of p0 is not valid in this context"));
800eeca4 4200 else
542d6675 4201 add_qp_imply (p1, p2);
800eeca4
JW		 4202 break;
4203 case 'm':
4204 if (count < 2)
542d6675
KH		 4205 {
4206 as_bad (_("At least two PR arguments expected"));
4207 break;
4208 }
800eeca4 4209 else if (mask & 1)
542d6675
KH		 4210 {
4211 as_bad (_("Use of p0 is not valid in this context"));
4212 break;
4213 }
800eeca4
JW		 4214 add_qp_mutex (mask);
4215 break;
4216 case 's':
4217 /* note that we don't override any existing relations */
4218 if (count == 0)
542d6675
KH		 4219 {
4220 as_bad (_("At least one PR argument expected"));
4221 break;
4222 }
800eeca4 4223 if (md.debug_dv)
542d6675
KH		 4224 {
4225 fprintf (stderr, "Safe across calls: ");
4226 print_prmask (mask);
4227 fprintf (stderr, "\n");
4228 }
800eeca4
JW		 4229 qp_safe_across_calls = mask;
4230 break;
4231 }
4232 demand_empty_rest_of_line ();
4233}
4234
4235/* .entry label [, label [, ...]]
4236 Hint to DV code that the given labels are to be considered entry points.
542d6675
KH		 4237 Otherwise, only global labels are considered entry points. */
4238
800eeca4
JW		 4239static void
4240dot_entry (dummy)
542d6675 4241 int dummy;
800eeca4
JW		 4242{
4243 const char *err;
4244 char *name;
4245 int c;
4246 symbolS *symbolP;
4247
4248 do
4249 {
4250 name = input_line_pointer;
4251 c = get_symbol_end ();
4252 symbolP = symbol_find_or_make (name);
4253
4254 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4255 if (err)
542d6675
KH		 4256 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4257 name, err);
800eeca4
JW		 4258
4259 *input_line_pointer = c;
4260 SKIP_WHITESPACE ();
4261 c = *input_line_pointer;
4262 if (c == ',')
4263 {
4264 input_line_pointer++;
4265 SKIP_WHITESPACE ();
4266 if (*input_line_pointer == '\n')
4267 c = '\n';
4268 }
4269 }
4270 while (c == ',');
4271
4272 demand_empty_rest_of_line ();
4273}
4274
197865e8 4275/* .mem.offset offset, base
542d6675
KH		 4276 "base" is used to distinguish between offsets from a different base. */
4277
800eeca4
JW		 4278static void
4279dot_mem_offset (dummy)
4280 int dummy;
4281{
4282 md.mem_offset.hint = 1;
4283 md.mem_offset.offset = get_absolute_expression ();
4284 if (*input_line_pointer != ',')
4285 {
4286 as_bad (_("Comma expected"));
4287 ignore_rest_of_line ();
4288 return;
4289 }
4290 ++input_line_pointer;
4291 md.mem_offset.base = get_absolute_expression ();
4292 demand_empty_rest_of_line ();
4293}
4294
542d6675 4295/* ia64-specific pseudo-ops: */
800eeca4
JW		 4296const pseudo_typeS md_pseudo_table[] =
4297 {
4298 { "radix", dot_radix, 0 },
4299 { "lcomm", s_lcomm_bytes, 1 },
4300 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4301 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4302 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4303 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4304 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4305 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4306 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4307 { "proc", dot_proc, 0 },
4308 { "body", dot_body, 0 },
4309 { "prologue", dot_prologue, 0 },
4310 { "endp", dot_endp },
4311 { "file", dwarf2_directive_file },
4312 { "loc", dwarf2_directive_loc },
4313
4314 { "fframe", dot_fframe },
4315 { "vframe", dot_vframe },
e0c9811a
JW		 4316 { "vframesp", dot_vframesp },
4317 { "vframepsp", dot_vframepsp },
800eeca4
JW		 4318 { "save", dot_save },
4319 { "restore", dot_restore },
e0c9811a
JW		 4320 { "restorereg", dot_restorereg },
4321 { "restorereg.p", dot_restorereg_p },
800eeca4
JW		 4322 { "handlerdata", dot_handlerdata },
4323 { "unwentry", dot_unwentry },
e0c9811a
JW		 4324 { "altrp", dot_altrp },
4325 { "savesp", dot_savemem, 0 },
4326 { "savepsp", dot_savemem, 1 },
800eeca4
JW		 4327 { "save.g", dot_saveg },
4328 { "save.f", dot_savef },
4329 { "save.b", dot_saveb },
4330 { "save.gf", dot_savegf },
4331 { "spill", dot_spill },
e0c9811a
JW		 4332 { "spillreg", dot_spillreg },
4333 { "spillsp", dot_spillmem, 0 },
4334 { "spillpsp", dot_spillmem, 1 },
4335 { "spillreg.p", dot_spillreg_p },
4336 { "spillsp.p", dot_spillmem_p, 0 },
4337 { "spillpsp.p", dot_spillmem_p, 1 },
197865e8
KH		 4338 { "label_state", dot_label_state },
4339 { "copy_state", dot_copy_state },
800eeca4
JW		 4340 { "unwabi", dot_unwabi },
4341 { "personality", dot_personality },
4342#if 0
4343 { "estate", dot_estate },
4344#endif
4345 { "mii", dot_template, 0x0 },
4346 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4347 { "mlx", dot_template, 0x2 },
4348 { "mmi", dot_template, 0x4 },
4349 { "mfi", dot_template, 0x6 },
4350 { "mmf", dot_template, 0x7 },
4351 { "mib", dot_template, 0x8 },
4352 { "mbb", dot_template, 0x9 },
4353 { "bbb", dot_template, 0xb },
4354 { "mmb", dot_template, 0xc },
4355 { "mfb", dot_template, 0xe },
4356#if 0
4357 { "lb", dot_scope, 0 },
4358 { "le", dot_scope, 1 },
4359#endif
4360 { "align", s_align_bytes, 0 },
4361 { "regstk", dot_regstk, 0 },
4362 { "rotr", dot_rot, DYNREG_GR },
4363 { "rotf", dot_rot, DYNREG_FR },
4364 { "rotp", dot_rot, DYNREG_PR },
4365 { "lsb", dot_byteorder, 0 },
4366 { "msb", dot_byteorder, 1 },
4367 { "psr", dot_psr, 0 },
4368 { "alias", dot_alias, 0 },
4369 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4370
4371 { "xdata1", dot_xdata, 1 },
4372 { "xdata2", dot_xdata, 2 },
4373 { "xdata4", dot_xdata, 4 },
4374 { "xdata8", dot_xdata, 8 },
4375 { "xreal4", dot_xfloat_cons, 'f' },
4376 { "xreal8", dot_xfloat_cons, 'd' },
4377 { "xreal10", dot_xfloat_cons, 'x' },
4378 { "xstring", dot_xstringer, 0 },
4379 { "xstringz", dot_xstringer, 1 },
4380
542d6675 4381 /* unaligned versions: */
800eeca4
JW		 4382 { "xdata2.ua", dot_xdata_ua, 2 },
4383 { "xdata4.ua", dot_xdata_ua, 4 },
4384 { "xdata8.ua", dot_xdata_ua, 8 },
4385 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4386 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4387 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4388
4389 /* annotations/DV checking support */
4390 { "entry", dot_entry, 0 },
4391 { "mem.offset", dot_mem_offset },
4392 { "pred.rel", dot_pred_rel, 0 },
4393 { "pred.rel.clear", dot_pred_rel, 'c' },
4394 { "pred.rel.imply", dot_pred_rel, 'i' },
4395 { "pred.rel.mutex", dot_pred_rel, 'm' },
4396 { "pred.safe_across_calls", dot_pred_rel, 's' },
4397 { "reg.val", dot_reg_val },
4398 { "auto", dot_dv_mode, 'a' },
4399 { "explicit", dot_dv_mode, 'e' },
4400 { "default", dot_dv_mode, 'd' },
4401
4402 { NULL, 0, 0 }
4403 };
4404
4405static const struct pseudo_opcode
4406 {
4407 const char *name;
4408 void (*handler) (int);
4409 int arg;
4410 }
4411pseudo_opcode[] =
4412 {
4413 /* these are more like pseudo-ops, but don't start with a dot */
4414 { "data1", cons, 1 },
4415 { "data2", cons, 2 },
4416 { "data4", cons, 4 },
4417 { "data8", cons, 8 },
4418 { "real4", stmt_float_cons, 'f' },
4419 { "real8", stmt_float_cons, 'd' },
4420 { "real10", stmt_float_cons, 'x' },
4421 { "string", stringer, 0 },
4422 { "stringz", stringer, 1 },
4423
542d6675 4424 /* unaligned versions: */
800eeca4
JW		 4425 { "data2.ua", stmt_cons_ua, 2 },
4426 { "data4.ua", stmt_cons_ua, 4 },
4427 { "data8.ua", stmt_cons_ua, 8 },
4428 { "real4.ua", float_cons, 'f' },
4429 { "real8.ua", float_cons, 'd' },
4430 { "real10.ua", float_cons, 'x' },
4431 };
4432
4433/* Declare a register by creating a symbol for it and entering it in
4434 the symbol table. */
542d6675
KH		 4435
4436static symbolS *
800eeca4
JW		 4437declare_register (name, regnum)
4438 const char *name;
4439 int regnum;
4440{
4441 const char *err;
4442 symbolS *sym;
4443
4444 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4445
4446 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4447 if (err)
4448 as_fatal ("Inserting \"%s\" into register table failed: %s",
4449 name, err);
4450
4451 return sym;
4452}
4453
4454static void
4455declare_register_set (prefix, num_regs, base_regnum)
4456 const char *prefix;
4457 int num_regs;
4458 int base_regnum;
4459{
4460 char name[8];
4461 int i;
4462
4463 for (i = 0; i < num_regs; ++i)
4464 {
4465 sprintf (name, "%s%u", prefix, i);
4466 declare_register (name, base_regnum + i);
4467 }
4468}
4469
4470static unsigned int
4471operand_width (opnd)
4472 enum ia64_opnd opnd;
4473{
4474 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4475 unsigned int bits = 0;
4476 int i;
4477
4478 bits = 0;
4479 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4480 bits += odesc->field[i].bits;
4481
4482 return bits;
4483}
4484
4485static int
4486operand_match (idesc, index, e)
4487 const struct ia64_opcode *idesc;
4488 int index;
4489 expressionS *e;
4490{
4491 enum ia64_opnd opnd = idesc->operands[index];
4492 int bits, relocatable = 0;
4493 struct insn_fix *fix;
4494 bfd_signed_vma val;
4495
4496 switch (opnd)
4497 {
542d6675 4498 /* constants: */
800eeca4
JW		 4499
4500 case IA64_OPND_AR_CCV:
4501 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4502 return 1;
4503 break;
4504
4505 case IA64_OPND_AR_PFS:
4506 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4507 return 1;
4508 break;
4509
4510 case IA64_OPND_GR0:
4511 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4512 return 1;
4513 break;
4514
4515 case IA64_OPND_IP:
4516 if (e->X_op == O_register && e->X_add_number == REG_IP)
4517 return 1;
4518 break;
4519
4520 case IA64_OPND_PR:
4521 if (e->X_op == O_register && e->X_add_number == REG_PR)
4522 return 1;
4523 break;
4524
4525 case IA64_OPND_PR_ROT:
4526 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4527 return 1;
4528 break;
4529
4530 case IA64_OPND_PSR:
4531 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4532 return 1;
4533 break;
4534
4535 case IA64_OPND_PSR_L:
4536 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4537 return 1;
4538 break;
4539
4540 case IA64_OPND_PSR_UM:
4541 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4542 return 1;
4543 break;
4544
4545 case IA64_OPND_C1:
4546 if (e->X_op == O_constant && e->X_add_number == 1)
4547 return 1;
4548 break;
4549
4550 case IA64_OPND_C8:
4551 if (e->X_op == O_constant && e->X_add_number == 8)
4552 return 1;
4553 break;
4554
4555 case IA64_OPND_C16:
4556 if (e->X_op == O_constant && e->X_add_number == 16)
4557 return 1;
4558 break;
4559
542d6675 4560 /* register operands: */
800eeca4
JW		 4561
4562 case IA64_OPND_AR3:
4563 if (e->X_op == O_register && e->X_add_number >= REG_AR
4564 && e->X_add_number < REG_AR + 128)
4565 return 1;
4566 break;
4567
4568 case IA64_OPND_B1:
4569 case IA64_OPND_B2:
4570 if (e->X_op == O_register && e->X_add_number >= REG_BR
4571 && e->X_add_number < REG_BR + 8)
4572 return 1;
4573 break;
4574
4575 case IA64_OPND_CR3:
4576 if (e->X_op == O_register && e->X_add_number >= REG_CR
4577 && e->X_add_number < REG_CR + 128)
4578 return 1;
4579 break;
4580
4581 case IA64_OPND_F1:
4582 case IA64_OPND_F2:
4583 case IA64_OPND_F3:
4584 case IA64_OPND_F4:
4585 if (e->X_op == O_register && e->X_add_number >= REG_FR
4586 && e->X_add_number < REG_FR + 128)
4587 return 1;
4588 break;
4589
4590 case IA64_OPND_P1:
4591 case IA64_OPND_P2:
4592 if (e->X_op == O_register && e->X_add_number >= REG_P
4593 && e->X_add_number < REG_P + 64)
4594 return 1;
4595 break;
4596
4597 case IA64_OPND_R1:
4598 case IA64_OPND_R2:
4599 case IA64_OPND_R3:
4600 if (e->X_op == O_register && e->X_add_number >= REG_GR
4601 && e->X_add_number < REG_GR + 128)
4602 return 1;
4603 break;
4604
4605 case IA64_OPND_R3_2:
4606 if (e->X_op == O_register && e->X_add_number >= REG_GR
4607 && e->X_add_number < REG_GR + 4)
4608 return 1;
4609 break;
4610
542d6675 4611 /* indirect operands: */
800eeca4
JW		 4612 case IA64_OPND_CPUID_R3:
4613 case IA64_OPND_DBR_R3:
4614 case IA64_OPND_DTR_R3:
4615 case IA64_OPND_ITR_R3:
4616 case IA64_OPND_IBR_R3:
4617 case IA64_OPND_MSR_R3:
4618 case IA64_OPND_PKR_R3:
4619 case IA64_OPND_PMC_R3:
4620 case IA64_OPND_PMD_R3:
4621 case IA64_OPND_RR_R3:
4622 if (e->X_op == O_index && e->X_op_symbol
4623 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4624 == opnd - IA64_OPND_CPUID_R3))
4625 return 1;
4626 break;
4627
4628 case IA64_OPND_MR3:
4629 if (e->X_op == O_index && !e->X_op_symbol)
4630 return 1;
4631 break;
4632
542d6675 4633 /* immediate operands: */
800eeca4
JW		 4634 case IA64_OPND_CNT2a:
4635 case IA64_OPND_LEN4:
4636 case IA64_OPND_LEN6:
4637 bits = operand_width (idesc->operands[index]);
4638 if (e->X_op == O_constant
4639 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4640 return 1;
4641 break;
4642
4643 case IA64_OPND_CNT2b:
4644 if (e->X_op == O_constant
4645 && (bfd_vma) (e->X_add_number - 1) < 3)
4646 return 1;
4647 break;
4648
4649 case IA64_OPND_CNT2c:
4650 val = e->X_add_number;
4651 if (e->X_op == O_constant
4652 && (val == 0 || val == 7 || val == 15 || val == 16))
4653 return 1;
4654 break;
4655
4656 case IA64_OPND_SOR:
4657 /* SOR must be an integer multiple of 8 */
4658 if (e->X_add_number & 0x7)
4659 break;
4660 case IA64_OPND_SOF:
4661 case IA64_OPND_SOL:
4662 if (e->X_op == O_constant &&
4663 (bfd_vma) e->X_add_number <= 96)
4664 return 1;
4665 break;
4666
4667 case IA64_OPND_IMMU62:
4668 if (e->X_op == O_constant)
542d6675 4669 {
800eeca4 4670 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
542d6675
KH		 4671 return 1;
4672 }
197865e8 4673 else
542d6675
KH		 4674 {
4675 /* FIXME -- need 62-bit relocation type */
4676 as_bad (_("62-bit relocation not yet implemented"));
4677 }
800eeca4
JW		 4678 break;
4679
4680 case IA64_OPND_IMMU64:
4681 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4682 || e->X_op == O_subtract)
4683 {
4684 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4685 fix->code = BFD_RELOC_IA64_IMM64;
4686 if (e->X_op != O_subtract)
4687 {
4688 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4689 if (e->X_op == O_pseudo_fixup)
4690 e->X_op = O_symbol;
4691 }
4692
4693 fix->opnd = idesc->operands[index];
4694 fix->expr = *e;
4695 fix->is_pcrel = 0;
4696 ++CURR_SLOT.num_fixups;
4697 return 1;
4698 }
4699 else if (e->X_op == O_constant)
4700 return 1;
4701 break;
4702
4703 case IA64_OPND_CCNT5:
4704 case IA64_OPND_CNT5:
4705 case IA64_OPND_CNT6:
4706 case IA64_OPND_CPOS6a:
4707 case IA64_OPND_CPOS6b:
4708 case IA64_OPND_CPOS6c:
4709 case IA64_OPND_IMMU2:
4710 case IA64_OPND_IMMU7a:
4711 case IA64_OPND_IMMU7b:
800eeca4
JW		 4712 case IA64_OPND_IMMU21:
4713 case IA64_OPND_IMMU24:
4714 case IA64_OPND_MBTYPE4:
4715 case IA64_OPND_MHTYPE8:
4716 case IA64_OPND_POS6:
4717 bits = operand_width (idesc->operands[index]);
4718 if (e->X_op == O_constant
4719 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4720 return 1;
4721 break;
4722
bf3ca999
TW		 4723 case IA64_OPND_IMMU9:
4724 bits = operand_width (idesc->operands[index]);
4725 if (e->X_op == O_constant
4726 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
542d6675
KH		 4727 {
4728 int lobits = e->X_add_number & 0x3;
4729 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
4730 e->X_add_number |= (bfd_vma) 0x3;
4731 return 1;
4732 }
bf3ca999
TW		 4733 break;
4734
800eeca4
JW		 4735 case IA64_OPND_IMM44:
4736 /* least 16 bits must be zero */
4737 if ((e->X_add_number & 0xffff) != 0)
542d6675 4738 as_warn (_("lower 16 bits of mask ignored"));
800eeca4
JW		 4739
4740 if (e->X_op == O_constant
4741 && ((e->X_add_number >= 0
4742 && e->X_add_number < ((bfd_vma) 1 << 44))
4743 || (e->X_add_number < 0
4744 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
542d6675
KH		 4745 {
4746 /* sign-extend */
4747 if (e->X_add_number >= 0
4748 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4749 {
4750 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4751 }
4752 return 1;
4753 }
800eeca4
JW		 4754 break;
4755
4756 case IA64_OPND_IMM17:
4757 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4758 if (e->X_op == O_constant
4759 && ((e->X_add_number >= 0
4760 && e->X_add_number < ((bfd_vma) 1 << 17))
4761 || (e->X_add_number < 0
4762 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
542d6675
KH		 4763 {
4764 /* sign-extend */
4765 if (e->X_add_number >= 0
4766 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4767 {
4768 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
4769 }
4770 return 1;
4771 }
800eeca4
JW		 4772 break;
4773
4774 case IA64_OPND_IMM14:
4775 case IA64_OPND_IMM22:
4776 relocatable = 1;
4777 case IA64_OPND_IMM1:
4778 case IA64_OPND_IMM8:
4779 case IA64_OPND_IMM8U4:
4780 case IA64_OPND_IMM8M1:
4781 case IA64_OPND_IMM8M1U4:
4782 case IA64_OPND_IMM8M1U8:
4783 case IA64_OPND_IMM9a:
4784 case IA64_OPND_IMM9b:
4785 bits = operand_width (idesc->operands[index]);
4786 if (relocatable && (e->X_op == O_symbol
4787 || e->X_op == O_subtract
4788 || e->X_op == O_pseudo_fixup))
4789 {
4790 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4791
4792 if (idesc->operands[index] == IA64_OPND_IMM14)
4793 fix->code = BFD_RELOC_IA64_IMM14;
4794 else
4795 fix->code = BFD_RELOC_IA64_IMM22;
4796
4797 if (e->X_op != O_subtract)
4798 {
4799 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4800 if (e->X_op == O_pseudo_fixup)
4801 e->X_op = O_symbol;
4802 }
4803
4804 fix->opnd = idesc->operands[index];
4805 fix->expr = *e;
4806 fix->is_pcrel = 0;
4807 ++CURR_SLOT.num_fixups;
4808 return 1;
4809 }
4810 else if (e->X_op != O_constant
4811 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4812 return 0;
4813
4814 if (opnd == IA64_OPND_IMM8M1U4)
4815 {
4816 /* Zero is not valid for unsigned compares that take an adjusted
4817 constant immediate range. */
4818 if (e->X_add_number == 0)
4819 return 0;
4820
4821 /* Sign-extend 32-bit unsigned numbers, so that the following range
4822 checks will work. */
4823 val = e->X_add_number;
197865e8
KH		 4824 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4825 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 4826 val = ((val << 32) >> 32);
4827
4828 /* Check for 0x100000000. This is valid because
4829 0x100000000-1 is the same as ((uint32_t) -1). */
4830 if (val == ((bfd_signed_vma) 1 << 32))
4831 return 1;
4832
4833 val = val - 1;
4834 }
4835 else if (opnd == IA64_OPND_IMM8M1U8)
4836 {
4837 /* Zero is not valid for unsigned compares that take an adjusted
4838 constant immediate range. */
4839 if (e->X_add_number == 0)
4840 return 0;
4841
4842 /* Check for 0x10000000000000000. */
4843 if (e->X_op == O_big)
4844 {
4845 if (generic_bignum[0] == 0
4846 && generic_bignum[1] == 0
4847 && generic_bignum[2] == 0
4848 && generic_bignum[3] == 0
4849 && generic_bignum[4] == 1)
4850 return 1;
4851 else
4852 return 0;
4853 }
4854 else
4855 val = e->X_add_number - 1;
4856 }
4857 else if (opnd == IA64_OPND_IMM8M1)
4858 val = e->X_add_number - 1;
4859 else if (opnd == IA64_OPND_IMM8U4)
4860 {
4861 /* Sign-extend 32-bit unsigned numbers, so that the following range
4862 checks will work. */
4863 val = e->X_add_number;
197865e8
KH		 4864 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4865 && ((val & ((bfd_vma) 1 << 31)) != 0))
800eeca4
JW		 4866 val = ((val << 32) >> 32);
4867 }
4868 else
4869 val = e->X_add_number;
4870
4871 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
4872 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
4873 return 1;
4874 break;
4875
4876 case IA64_OPND_INC3:
4877 /* +/- 1, 4, 8, 16 */
4878 val = e->X_add_number;
4879 if (val < 0)
4880 val = -val;
4881 if (e->X_op == O_constant
4882 && (val == 1 || val == 4 || val == 8 || val == 16))
4883 return 1;
4884 break;
4885
4886 case IA64_OPND_TGT25:
4887 case IA64_OPND_TGT25b:
4888 case IA64_OPND_TGT25c:
4889 case IA64_OPND_TGT64:
4890 if (e->X_op == O_symbol)
4891 {
4892 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4893 if (opnd == IA64_OPND_TGT25)
4894 fix->code = BFD_RELOC_IA64_PCREL21F;
4895 else if (opnd == IA64_OPND_TGT25b)
4896 fix->code = BFD_RELOC_IA64_PCREL21M;
4897 else if (opnd == IA64_OPND_TGT25c)
4898 fix->code = BFD_RELOC_IA64_PCREL21B;
542d6675 4899 else if (opnd == IA64_OPND_TGT64)
c67e42c9
RH		 4900 fix->code = BFD_RELOC_IA64_PCREL60B;
4901 else
4902 abort ();
4903
800eeca4
JW		 4904 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4905 fix->opnd = idesc->operands[index];
4906 fix->expr = *e;
4907 fix->is_pcrel = 1;
4908 ++CURR_SLOT.num_fixups;
4909 return 1;
4910 }
4911 case IA64_OPND_TAG13:
4912 case IA64_OPND_TAG13b:
4913 switch (e->X_op)
4914 {
4915 case O_constant:
4916 return 1;
4917
4918 case O_symbol:
4919 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4920 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4921 fix->opnd = idesc->operands[index];
4922 fix->expr = *e;
4923 fix->is_pcrel = 1;
4924 ++CURR_SLOT.num_fixups;
4925 return 1;
4926
4927 default:
4928 break;
4929 }
4930 break;
4931
4932 default:
4933 break;
4934 }
4935 return 0;
4936}
4937
4938static int
4939parse_operand (e)
4940 expressionS *e;
4941{
4942 int sep = '\0';
4943
4944 memset (e, 0, sizeof (*e));
4945 e->X_op = O_absent;
4946 SKIP_WHITESPACE ();
4947 if (*input_line_pointer != '}')
4948 expression (e);
4949 sep = *input_line_pointer++;
4950
4951 if (sep == '}')
4952 {
4953 if (!md.manual_bundling)
4954 as_warn ("Found '}' when manual bundling is off");
4955 else
4956 CURR_SLOT.manual_bundling_off = 1;
4957 md.manual_bundling = 0;
4958 sep = '\0';
4959 }
4960 return sep;
4961}
4962
4963/* Returns the next entry in the opcode table that matches the one in
4964 IDESC, and frees the entry in IDESC. If no matching entry is
197865e8 4965 found, NULL is returned instead. */
800eeca4
JW		 4966
4967static struct ia64_opcode *
4968get_next_opcode (struct ia64_opcode *idesc)
4969{
4970 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
4971 ia64_free_opcode (idesc);
4972 return next;
4973}
4974
4975/* Parse the operands for the opcode and find the opcode variant that
4976 matches the specified operands, or NULL if no match is possible. */
542d6675
KH		 4977
4978static struct ia64_opcode *
800eeca4
JW		 4979parse_operands (idesc)
4980 struct ia64_opcode *idesc;
4981{
4982 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
4983 int sep = 0;
4984 enum ia64_opnd expected_operand = IA64_OPND_NIL;
4985 char mnemonic[129];
4986 char *first_arg = 0, *end, *saved_input_pointer;
4987 unsigned int sof;
4988
4989 assert (strlen (idesc->name) <= 128);
4990
4991 strcpy (mnemonic, idesc->name);
4992 if (idesc->operands[2] == IA64_OPND_SOF)
4993 {
4994 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4995 can't parse the first operand until we have parsed the
4996 remaining operands of the "alloc" instruction. */
4997 SKIP_WHITESPACE ();
4998 first_arg = input_line_pointer;
4999 end = strchr (input_line_pointer, '=');
5000 if (!end)
5001 {
5002 as_bad ("Expected separator `='");
5003 return 0;
5004 }
5005 input_line_pointer = end + 1;
5006 ++i;
5007 ++num_outputs;
5008 }
5009
5010 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5011 {
5012 sep = parse_operand (CURR_SLOT.opnd + i);
5013 if (CURR_SLOT.opnd[i].X_op == O_absent)
5014 break;
5015
5016 ++num_operands;
5017
5018 if (sep != '=' && sep != ',')
5019 break;
5020
5021 if (sep == '=')
5022 {
5023 if (num_outputs > 0)
5024 as_bad ("Duplicate equal sign (=) in instruction");
5025 else
5026 num_outputs = i + 1;
5027 }
5028 }
5029 if (sep != '\0')
5030 {
5031 as_bad ("Illegal operand separator `%c'", sep);
5032 return 0;
5033 }
197865e8 5034
800eeca4
JW		 5035 if (idesc->operands[2] == IA64_OPND_SOF)
5036 {
5037 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5038 know (strcmp (idesc->name, "alloc") == 0);
5039 if (num_operands == 5 /* first_arg not included in this count! */
5040 && CURR_SLOT.opnd[2].X_op == O_constant
5041 && CURR_SLOT.opnd[3].X_op == O_constant
5042 && CURR_SLOT.opnd[4].X_op == O_constant
5043 && CURR_SLOT.opnd[5].X_op == O_constant)
5044 {
5045 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5046 CURR_SLOT.opnd[3].X_add_number,
5047 CURR_SLOT.opnd[4].X_add_number,
5048 CURR_SLOT.opnd[5].X_add_number);
5049
542d6675 5050 /* now we can parse the first arg: */
800eeca4
JW		 5051 saved_input_pointer = input_line_pointer;
5052 input_line_pointer = first_arg;
5053 sep = parse_operand (CURR_SLOT.opnd + 0);
5054 if (sep != '=')
5055 --num_outputs; /* force error */
5056 input_line_pointer = saved_input_pointer;
5057
5058 CURR_SLOT.opnd[2].X_add_number = sof;
5059 CURR_SLOT.opnd[3].X_add_number
5060 = sof - CURR_SLOT.opnd[4].X_add_number;
5061 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5062 }
5063 }
5064
5065 highest_unmatched_operand = 0;
5066 expected_operand = idesc->operands[0];
5067 for (; idesc; idesc = get_next_opcode (idesc))
5068 {
5069 if (num_outputs != idesc->num_outputs)
5070 continue; /* mismatch in # of outputs */
5071
5072 CURR_SLOT.num_fixups = 0;
5073 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5074 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
5075 break;
5076
5077 if (i != num_operands)
5078 {
5079 if (i > highest_unmatched_operand)
5080 {
5081 highest_unmatched_operand = i;
5082 expected_operand = idesc->operands[i];
5083 }
5084 continue;
5085 }
5086
5087 if (num_operands < NELEMS (idesc->operands)
5088 && idesc->operands[num_operands])
5089 continue; /* mismatch in number of arguments */
5090
5091 break;
5092 }
5093 if (!idesc)
5094 {
5095 if (expected_operand)
5096 as_bad ("Operand %u of `%s' should be %s",
5097 highest_unmatched_operand + 1, mnemonic,
5098 elf64_ia64_operands[expected_operand].desc);
5099 else
5100 as_bad ("Operand mismatch");
5101 return 0;
5102 }
5103 return idesc;
5104}
5105
5106static void
5107build_insn (slot, insnp)
5108 struct slot *slot;
5109 bfd_vma *insnp;
5110{
5111 const struct ia64_operand *odesc, *o2desc;
5112 struct ia64_opcode *idesc = slot->idesc;
5113 bfd_signed_vma insn, val;
5114 const char *err;
5115 int i;
5116
5117 insn = idesc->opcode | slot->qp_regno;
5118
5119 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5120 {
c67e42c9
RH		 5121 if (slot->opnd[i].X_op == O_register
5122 || slot->opnd[i].X_op == O_constant
5123 || slot->opnd[i].X_op == O_index)
5124 val = slot->opnd[i].X_add_number;
5125 else if (slot->opnd[i].X_op == O_big)
800eeca4 5126 {
c67e42c9
RH		 5127 /* This must be the value 0x10000000000000000. */
5128 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5129 val = 0;
5130 }
5131 else
5132 val = 0;
5133
5134 switch (idesc->operands[i])
5135 {
5136 case IA64_OPND_IMMU64:
800eeca4
JW		 5137 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5138 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5139 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5140 | (((val >> 63) & 0x1) << 36));
c67e42c9
RH		 5141 continue;
5142
5143 case IA64_OPND_IMMU62:
542d6675
KH		 5144 val &= 0x3fffffffffffffffULL;
5145 if (val != slot->opnd[i].X_add_number)
5146 as_warn (_("Value truncated to 62 bits"));
5147 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5148 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
c67e42c9 5149 continue;
800eeca4 5150
c67e42c9
RH		 5151 case IA64_OPND_TGT64:
5152 val >>= 4;
5153 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5154 insn |= ((((val >> 59) & 0x1) << 36)
5155 | (((val >> 0) & 0xfffff) << 13));
5156 continue;
800eeca4 5157
c67e42c9
RH		 5158 case IA64_OPND_AR3:
5159 val -= REG_AR;
5160 break;
5161
5162 case IA64_OPND_B1:
5163 case IA64_OPND_B2:
5164 val -= REG_BR;
5165 break;
5166
5167 case IA64_OPND_CR3:
5168 val -= REG_CR;
5169 break;
5170
5171 case IA64_OPND_F1:
5172 case IA64_OPND_F2:
5173 case IA64_OPND_F3:
5174 case IA64_OPND_F4:
5175 val -= REG_FR;
5176 break;
5177
5178 case IA64_OPND_P1:
5179 case IA64_OPND_P2:
5180 val -= REG_P;
5181 break;
5182
5183 case IA64_OPND_R1:
5184 case IA64_OPND_R2:
5185 case IA64_OPND_R3:
5186 case IA64_OPND_R3_2:
5187 case IA64_OPND_CPUID_R3:
5188 case IA64_OPND_DBR_R3:
5189 case IA64_OPND_DTR_R3:
5190 case IA64_OPND_ITR_R3:
5191 case IA64_OPND_IBR_R3:
5192 case IA64_OPND_MR3:
5193 case IA64_OPND_MSR_R3:
5194 case IA64_OPND_PKR_R3:
5195 case IA64_OPND_PMC_R3:
5196 case IA64_OPND_PMD_R3:
197865e8 5197 case IA64_OPND_RR_R3:
c67e42c9
RH		 5198 val -= REG_GR;
5199 break;
5200
5201 default:
5202 break;
5203 }
5204
5205 odesc = elf64_ia64_operands + idesc->operands[i];
5206 err = (*odesc->insert) (odesc, val, &insn);
5207 if (err)
5208 as_bad_where (slot->src_file, slot->src_line,
5209 "Bad operand value: %s", err);
5210 if (idesc->flags & IA64_OPCODE_PSEUDO)
5211 {
5212 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5213 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5214 {
5215 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5216 (*o2desc->insert) (o2desc, val, &insn);
800eeca4 5217 }
c67e42c9
RH		 5218 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5219 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5220 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
800eeca4 5221 {
c67e42c9
RH		 5222 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5223 (*o2desc->insert) (o2desc, 64 - val, &insn);
800eeca4
JW		 5224 }
5225 }
5226 }
5227 *insnp = insn;
5228}
5229
5230static void
5231emit_one_bundle ()
5232{
5233 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5234 unsigned int manual_bundling = 0;
5235 enum ia64_unit required_unit, insn_unit = 0;
5236 enum ia64_insn_type type[3], insn_type;
5237 unsigned int template, orig_template;
542d6675 5238 bfd_vma insn[3] = { -1, -1, -1 };
800eeca4
JW		 5239 struct ia64_opcode *idesc;
5240 int end_of_insn_group = 0, user_template = -1;
5241 int n, i, j, first, curr;
e0c9811a 5242 unw_rec_list *ptr, *prev;
800eeca4
JW		 5243 bfd_vma t0 = 0, t1 = 0;
5244 struct label_fix *lfix;
5245 struct insn_fix *ifix;
5246 char mnemonic[16];
5247 fixS *fix;
5248 char *f;
5249
5250 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5251 know (first >= 0 & first < NUM_SLOTS);
5252 n = MIN (3, md.num_slots_in_use);
5253
5254 /* Determine template: user user_template if specified, best match
542d6675 5255 otherwise: */
800eeca4
JW		 5256
5257 if (md.slot[first].user_template >= 0)
5258 user_template = template = md.slot[first].user_template;
5259 else
5260 {
032efc85 5261 /* Auto select appropriate template. */
800eeca4
JW		 5262 memset (type, 0, sizeof (type));
5263 curr = first;
5264 for (i = 0; i < n; ++i)
5265 {
032efc85
RH		 5266 if (md.slot[curr].label_fixups && i != 0)
5267 break;
800eeca4
JW		 5268 type[i] = md.slot[curr].idesc->type;
5269 curr = (curr + 1) % NUM_SLOTS;
5270 }
5271 template = best_template[type[0]][type[1]][type[2]];
5272 }
5273
542d6675 5274 /* initialize instructions with appropriate nops: */
800eeca4
JW		 5275 for (i = 0; i < 3; ++i)
5276 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5277
5278 f = frag_more (16);
5279
542d6675 5280 /* now fill in slots with as many insns as possible: */
800eeca4
JW		 5281 curr = first;
5282 idesc = md.slot[curr].idesc;
5283 end_of_insn_group = 0;
5284 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5285 {
e0c9811a
JW		 5286 /* Set the slot number for prologue/body records now as those
5287 refer to the current point, not the point after the
542d6675 5288 instruction has been issued: */
10850f29
JW		 5289 /* Don't try to delete prologue/body records here, as that will cause
5290 them to also be deleted from the master list of unwind records. */
e0c9811a 5291 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
10850f29
JW		 5292 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5293 || ptr->r.type == body)
5294 ptr->slot_number = (unsigned long) f + i;
e0c9811a 5295
800eeca4
JW		 5296 if (idesc->flags & IA64_OPCODE_SLOT2)
5297 {
5298 if (manual_bundling && i != 2)
5299 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5300 "`%s' must be last in bundle", idesc->name);
5301 else
5302 i = 2;
5303 }
5304 if (idesc->flags & IA64_OPCODE_LAST)
5305 {
5306 int required_slot, required_template;
5307
5308 /* If we need a stop bit after an M slot, our only choice is
5309 template 5 (M;;MI). If we need a stop bit after a B
5310 slot, our only choice is to place it at the end of the
5311 bundle, because the only available templates are MIB,
5312 MBB, BBB, MMB, and MFB. We don't handle anything other
5313 than M and B slots because these are the only kind of
5314 instructions that can have the IA64_OPCODE_LAST bit set. */
5315 required_template = template;
5316 switch (idesc->type)
5317 {
5318 case IA64_TYPE_M:
5319 required_slot = 0;
5320 required_template = 5;
5321 break;
5322
5323 case IA64_TYPE_B:
5324 required_slot = 2;
5325 break;
5326
5327 default:
5328 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5329 "Internal error: don't know how to force %s to end"
5330 "of instruction group", idesc->name);
5331 required_slot = i;
5332 break;
5333 }
5334 if (manual_bundling && i != required_slot)
5335 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5336 "`%s' must be last in instruction group",
5337 idesc->name);
5338 if (required_slot < i)
5339 /* Can't fit this instruction. */
5340 break;
5341
5342 i = required_slot;
5343 if (required_template != template)
5344 {
5345 /* If we switch the template, we need to reset the NOPs
5346 after slot i. The slot-types of the instructions ahead
5347 of i never change, so we don't need to worry about
5348 changing NOPs in front of this slot. */
5349 for (j = i; j < 3; ++j)
5350 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5351 }
5352 template = required_template;
5353 }
5354 if (curr != first && md.slot[curr].label_fixups)
5355 {
5356 if (manual_bundling_on)
5357 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5358 "Label must be first in a bundle");
5359 /* This insn must go into the first slot of a bundle. */
5360 break;
5361 }
5362
5363 manual_bundling_on = md.slot[curr].manual_bundling_on;
5364 manual_bundling_off = md.slot[curr].manual_bundling_off;
5365
5366 if (manual_bundling_on)
5367 {
5368 if (curr == first)
5369 manual_bundling = 1;
5370 else
5371 break; /* need to start a new bundle */
5372 }
5373
5374 if (end_of_insn_group && md.num_slots_in_use >= 1)
5375 {
5376 /* We need an instruction group boundary in the middle of a
5377 bundle. See if we can switch to an other template with
5378 an appropriate boundary. */
5379
5380 orig_template = template;
5381 if (i == 1 && (user_template == 4
5382 || (user_template < 0
5383 && (ia64_templ_desc[template].exec_unit[0]
5384 == IA64_UNIT_M))))
5385 {
5386 template = 5;
5387 end_of_insn_group = 0;
5388 }
5389 else if (i == 2 && (user_template == 0
5390 || (user_template < 0
5391 && (ia64_templ_desc[template].exec_unit[1]
5392 == IA64_UNIT_I)))
5393 /* This test makes sure we don't switch the template if
5394 the next instruction is one that needs to be first in
5395 an instruction group. Since all those instructions are
5396 in the M group, there is no way such an instruction can
5397 fit in this bundle even if we switch the template. The
5398 reason we have to check for this is that otherwise we
5399 may end up generating "MI;;I M.." which has the deadly
5400 effect that the second M instruction is no longer the
5401 first in the bundle! --davidm 99/12/16 */
5402 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5403 {
5404 template = 1;
5405 end_of_insn_group = 0;
5406 }
5407 else if (curr != first)
5408 /* can't fit this insn */
5409 break;
5410
5411 if (template != orig_template)
5412 /* if we switch the template, we need to reset the NOPs
5413 after slot i. The slot-types of the instructions ahead
5414 of i never change, so we don't need to worry about
5415 changing NOPs in front of this slot. */
5416 for (j = i; j < 3; ++j)
5417 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5418 }
5419 required_unit = ia64_templ_desc[template].exec_unit[i];
5420
542d6675 5421 /* resolve dynamic opcodes such as "break" and "nop": */
800eeca4
JW		 5422 if (idesc->type == IA64_TYPE_DYN)
5423 {
5424 if ((strcmp (idesc->name, "nop") == 0)
5425 || (strcmp (idesc->name, "break") == 0))
5426 insn_unit = required_unit;
5427 else if (strcmp (idesc->name, "chk.s") == 0)
5428 {
5429 insn_unit = IA64_UNIT_M;
5430 if (required_unit == IA64_UNIT_I)
5431 insn_unit = IA64_UNIT_I;
5432 }
5433 else
5434 as_fatal ("emit_one_bundle: unexpected dynamic op");
5435
5436 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
3d56ab85 5437 ia64_free_opcode (idesc);
800eeca4
JW		 5438 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5439#if 0
5440 know (!idesc->next); /* no resolved dynamic ops have collisions */
5441#endif
5442 }
5443 else
5444 {
5445 insn_type = idesc->type;
5446 insn_unit = IA64_UNIT_NIL;
5447 switch (insn_type)
5448 {
5449 case IA64_TYPE_A:
5450 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5451 insn_unit = required_unit;
5452 break;
542d6675 5453 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
800eeca4
JW		 5454 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5455 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5456 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5457 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5458 default: break;
5459 }
5460 }
5461
5462 if (insn_unit != required_unit)
5463 {
5464 if (required_unit == IA64_UNIT_L
542d6675 5465 && insn_unit == IA64_UNIT_I
800eeca4
JW		 5466 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5467 {
5468 /* we got ourselves an MLX template but the current
197865e8 5469 instruction isn't an X-unit, or an I-unit instruction
800eeca4
JW		 5470 that can go into the X slot of an MLX template. Duh. */
5471 if (md.num_slots_in_use >= NUM_SLOTS)
5472 {
5473 as_bad_where (md.slot[curr].src_file,
5474 md.slot[curr].src_line,
5475 "`%s' can't go in X slot of "
5476 "MLX template", idesc->name);
542d6675 5477 /* drop this insn so we don't livelock: */
800eeca4
JW		 5478 --md.num_slots_in_use;
5479 }
5480 break;
5481 }
5482 continue; /* try next slot */
5483 }
5484
5485 if (debug_type == DEBUG_DWARF2)
5486 {
5487 bfd_vma addr;
5488
f1bcba5b 5489 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
800eeca4
JW		 5490 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5491 }
5492
5493 build_insn (md.slot + curr, insn + i);
5494
10850f29
JW		 5495 /* Set slot counts for non prologue/body unwind records. */
5496 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5497 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5498 && ptr->r.type != body)
5499 ptr->slot_number = (unsigned long) f + i;
5500 md.slot[curr].unwind_record = NULL;
e0c9811a 5501 unwind.next_slot_number = (unsigned long) f + i + ((i == 2)?(0x10-2):1);
10850f29 5502
800eeca4
JW		 5503 if (required_unit == IA64_UNIT_L)
5504 {
5505 know (i == 1);
5506 /* skip one slot for long/X-unit instructions */
5507 ++i;
5508 }
5509 --md.num_slots_in_use;
5510
542d6675 5511 /* now is a good time to fix up the labels for this insn: */
800eeca4
JW		 5512 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5513 {
5514 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5515 symbol_set_frag (lfix->sym, frag_now);
5516 }
f1bcba5b
JW		 5517 /* and fix up the tags also. */
5518 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
5519 {
5520 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
5521 symbol_set_frag (lfix->sym, frag_now);
5522 }
800eeca4
JW		 5523
5524 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5525 {
5526 ifix = md.slot[curr].fixup + j;
5527 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
5528 &ifix->expr, ifix->is_pcrel, ifix->code);
5529 fix->tc_fix_data.opnd = ifix->opnd;
5530 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5531 fix->fx_file = md.slot[curr].src_file;
5532 fix->fx_line = md.slot[curr].src_line;
5533 }
5534
5535 end_of_insn_group = md.slot[curr].end_of_insn_group;
5536
542d6675 5537 /* clear slot: */
800eeca4
JW		 5538 ia64_free_opcode (md.slot[curr].idesc);
5539 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5540 md.slot[curr].user_template = -1;
5541
5542 if (manual_bundling_off)
5543 {
5544 manual_bundling = 0;
5545 break;
5546 }
5547 curr = (curr + 1) % NUM_SLOTS;
5548 idesc = md.slot[curr].idesc;
5549 }
5550 if (manual_bundling)
5551 {
5552 if (md.num_slots_in_use > 0)
5553 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5554 "`%s' does not fit into %s template",
5555 idesc->name, ia64_templ_desc[template].name);
5556 else
5557 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5558 "Missing '}' at end of file");
5559 }
5560 know (md.num_slots_in_use < NUM_SLOTS);
5561
5562 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5563 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5564
5565 md_number_to_chars (f + 0, t0, 8);
5566 md_number_to_chars (f + 8, t1, 8);
5567}
5568
5569int
5570md_parse_option (c, arg)
5571 int c;
5572 char *arg;
5573{
800eeca4
JW		 5574 switch (c)
5575 {
c43c2cc5 5576 /* Switches from the Intel assembler. */
800eeca4
JW		 5577 case 'M':
5578 if (strcmp (arg, "ilp64") == 0
5579 || strcmp (arg, "lp64") == 0
5580 || strcmp (arg, "p64") == 0)
5581 {
5582 md.flags |= EF_IA_64_ABI64;
5583 }
5584 else if (strcmp (arg, "ilp32") == 0)
5585 {
5586 md.flags &= ~EF_IA_64_ABI64;
5587 }
5588 else if (strcmp (arg, "le") == 0)
5589 {
5590 md.flags &= ~EF_IA_64_BE;
5591 }
5592 else if (strcmp (arg, "be") == 0)
5593 {
5594 md.flags |= EF_IA_64_BE;
5595 }
5596 else
5597 return 0;
5598 break;
5599
5600 case 'N':
5601 if (strcmp (arg, "so") == 0)
5602 {
542d6675 5603 /* Suppress signon message. */
800eeca4
JW		 5604 }
5605 else if (strcmp (arg, "pi") == 0)
5606 {
5607 /* Reject privileged instructions. FIXME */
5608 }
5609 else if (strcmp (arg, "us") == 0)
5610 {
5611 /* Allow union of signed and unsigned range. FIXME */
5612 }
5613 else if (strcmp (arg, "close_fcalls") == 0)
5614 {
5615 /* Do not resolve global function calls. */
5616 }
5617 else
5618 return 0;
5619 break;
5620
5621 case 'C':
5622 /* temp[="prefix"] Insert temporary labels into the object file
5623 symbol table prefixed by "prefix".
5624 Default prefix is ":temp:".
5625 */
5626 break;
5627
5628 case 'a':
5629 /* ??? Conflicts with gas' listing option. */
5630 /* indirect=<tgt> Assume unannotated indirect branches behavior
5631 according to <tgt> --
5632 exit: branch out from the current context (default)
5633 labels: all labels in context may be branch targets
5634 */
5635 break;
5636
5637 case 'x':
5638 /* -X conflicts with an ignored option, use -x instead */
5639 md.detect_dv = 1;
5640 if (!arg || strcmp (arg, "explicit") == 0)
542d6675
KH		 5641 {
5642 /* set default mode to explicit */
5643 md.default_explicit_mode = 1;
5644 break;
5645 }
800eeca4 5646 else if (strcmp (arg, "auto") == 0)
542d6675
KH		 5647 {
5648 md.default_explicit_mode = 0;
5649 }
800eeca4 5650 else if (strcmp (arg, "debug") == 0)
542d6675
KH		 5651 {
5652 md.debug_dv = 1;
5653 }
800eeca4 5654 else if (strcmp (arg, "debugx") == 0)
542d6675
KH		 5655 {
5656 md.default_explicit_mode = 1;
5657 md.debug_dv = 1;
5658 }
800eeca4 5659 else
542d6675
KH		 5660 {
5661 as_bad (_("Unrecognized option '-x%s'"), arg);
5662 }
800eeca4
JW		 5663 break;
5664
5665 case 'S':
5666 /* nops Print nops statistics. */
5667 break;
5668
c43c2cc5
JW		 5669 /* GNU specific switches for gcc. */
5670 case OPTION_MCONSTANT_GP:
5671 md.flags |= EF_IA_64_CONS_GP;
5672 break;
5673
5674 case OPTION_MAUTO_PIC:
5675 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
5676 break;
5677
800eeca4
JW		 5678 default:
5679 return 0;
5680 }
5681
5682 return 1;
5683}
5684
5685void
5686md_show_usage (stream)
5687 FILE *stream;
5688{
542d6675 5689 fputs (_("\
800eeca4
JW		 5690IA-64 options:\n\
5691 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5692 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5693 -x | -xexplicit turn on dependency violation checking (default)\n\
5694 -xauto automagically remove dependency violations\n\
5695 -xdebug debug dependency violation checker\n"),
5696 stream);
5697}
5698
44576e1f
RH		 5699/* Return true if TYPE fits in TEMPL at SLOT. */
5700
5701static int
800eeca4
JW		 5702match (int templ, int type, int slot)
5703{
5704 enum ia64_unit unit;
5705 int result;
5706
5707 unit = ia64_templ_desc[templ].exec_unit[slot];
5708 switch (type)
5709 {
5710 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5711 case IA64_TYPE_A:
5712 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5713 break;
5714 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5715 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5716 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5717 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5718 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5719 default: result = 0; break;
5720 }
5721 return result;
5722}
5723
44576e1f
RH		 5724/* Add a bit of extra goodness if a nop of type F or B would fit
5725 in TEMPL at SLOT. */
5726
5727static inline int
5728extra_goodness (int templ, int slot)
5729{
ebeeafe6 5730 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
44576e1f 5731 return 2;
ebeeafe6 5732 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
44576e1f
RH		 5733 return 1;
5734 return 0;
5735}
5736
800eeca4
JW		 5737/* This function is called once, at assembler startup time. It sets
5738 up all the tables, etc. that the MD part of the assembler will need
5739 that can be determined before arguments are parsed. */
5740void
5741md_begin ()
5742{
5743 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum;
5744 const char *err;
5745 char name[8];
5746
5747 md.auto_align = 1;
5748 md.explicit_mode = md.default_explicit_mode;
5749
5750 bfd_set_section_alignment (stdoutput, text_section, 4);
5751
5752 target_big_endian = 0;
5753 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
542d6675
KH		 5754 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5755 &zero_address_frag);
800eeca4
JW		 5756
5757 pseudo_func[FUNC_GP_RELATIVE].u.sym =
542d6675
KH		 5758 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5759 &zero_address_frag);
800eeca4
JW		 5760
5761 pseudo_func[FUNC_LT_RELATIVE].u.sym =
542d6675
KH		 5762 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5763 &zero_address_frag);
800eeca4 5764
c67e42c9 5765 pseudo_func[FUNC_PC_RELATIVE].u.sym =
542d6675
KH		 5766 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5767 &zero_address_frag);
c67e42c9 5768
800eeca4 5769 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
542d6675
KH		 5770 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5771 &zero_address_frag);
800eeca4
JW		 5772
5773 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
542d6675
KH		 5774 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5775 &zero_address_frag);
800eeca4
JW		 5776
5777 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
542d6675
KH		 5778 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5779 &zero_address_frag);
800eeca4
JW		 5780
5781 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
542d6675
KH		 5782 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5783 &zero_address_frag);
800eeca4
JW		 5784
5785 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
542d6675
KH		 5786 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5787 &zero_address_frag);
800eeca4 5788
197865e8 5789 /* Compute the table of best templates. We compute goodness as a
44576e1f
RH		 5790 base 4 value, in which each match counts for 3, each F counts
5791 for 2, each B counts for 1. This should maximize the number of
5792 F and B nops in the chosen bundles, which is good because these
5793 pipelines are least likely to be overcommitted. */
800eeca4
JW		 5794 for (i = 0; i < IA64_NUM_TYPES; ++i)
5795 for (j = 0; j < IA64_NUM_TYPES; ++j)
5796 for (k = 0; k < IA64_NUM_TYPES; ++k)
5797 {
5798 best = 0;
5799 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
5800 {
5801 goodness = 0;
5802 if (match (t, i, 0))
5803 {
5804 if (match (t, j, 1))
5805 {
5806 if (match (t, k, 2))
44576e1f 5807 goodness = 3 + 3 + 3;
800eeca4 5808 else
44576e1f 5809 goodness = 3 + 3 + extra_goodness (t, 2);
800eeca4
JW		 5810 }
5811 else if (match (t, j, 2))
44576e1f 5812 goodness = 3 + 3 + extra_goodness (t, 1);
800eeca4 5813 else
44576e1f
RH		 5814 {
5815 goodness = 3;
5816 goodness += extra_goodness (t, 1);
5817 goodness += extra_goodness (t, 2);
5818 }
800eeca4
JW		 5819 }
5820 else if (match (t, i, 1))
5821 {
5822 if (match (t, j, 2))
44576e1f 5823 goodness = 3 + 3;
800eeca4 5824 else
44576e1f 5825 goodness = 3 + extra_goodness (t, 2);
800eeca4
JW		 5826 }
5827 else if (match (t, i, 2))
44576e1f 5828 goodness = 3 + extra_goodness (t, 1);
800eeca4
JW		 5829
5830 if (goodness > best)
5831 {
5832 best = goodness;
5833 best_template[i][j][k] = t;
5834 }
5835 }
5836 }
5837
5838 for (i = 0; i < NUM_SLOTS; ++i)
5839 md.slot[i].user_template = -1;
5840
5841 md.pseudo_hash = hash_new ();
5842 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
5843 {
5844 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
5845 (void *) (pseudo_opcode + i));
5846 if (err)
5847 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5848 pseudo_opcode[i].name, err);
5849 }
5850
5851 md.reg_hash = hash_new ();
5852 md.dynreg_hash = hash_new ();
5853 md.const_hash = hash_new ();
5854 md.entry_hash = hash_new ();
5855
542d6675 5856 /* general registers: */
800eeca4
JW		 5857
5858 total = 128;
5859 for (i = 0; i < total; ++i)
5860 {
5861 sprintf (name, "r%d", i - REG_GR);
5862 md.regsym[i] = declare_register (name, i);
5863 }
5864
542d6675 5865 /* floating point registers: */
800eeca4
JW		 5866 total += 128;
5867 for (; i < total; ++i)
5868 {
5869 sprintf (name, "f%d", i - REG_FR);
5870 md.regsym[i] = declare_register (name, i);
5871 }
5872
542d6675 5873 /* application registers: */
800eeca4
JW		 5874 total += 128;
5875 ar_base = i;
5876 for (; i < total; ++i)
5877 {
5878 sprintf (name, "ar%d", i - REG_AR);
5879 md.regsym[i] = declare_register (name, i);
5880 }
5881
542d6675 5882 /* control registers: */
800eeca4
JW		 5883 total += 128;
5884 cr_base = i;
5885 for (; i < total; ++i)
5886 {
5887 sprintf (name, "cr%d", i - REG_CR);
5888 md.regsym[i] = declare_register (name, i);
5889 }
5890
542d6675 5891 /* predicate registers: */
800eeca4
JW		 5892 total += 64;
5893 for (; i < total; ++i)
5894 {
5895 sprintf (name, "p%d", i - REG_P);
5896 md.regsym[i] = declare_register (name, i);
5897 }
5898
542d6675 5899 /* branch registers: */
800eeca4
JW		 5900 total += 8;
5901 for (; i < total; ++i)
5902 {
5903 sprintf (name, "b%d", i - REG_BR);
5904 md.regsym[i] = declare_register (name, i);
5905 }
5906
5907 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
5908 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
5909 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
5910 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
5911 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
5912 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
5913 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
5914
5915 for (i = 0; i < NELEMS (indirect_reg); ++i)
5916 {
5917 regnum = indirect_reg[i].regnum;
5918 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
5919 }
5920
542d6675 5921 /* define synonyms for application registers: */
800eeca4
JW		 5922 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
5923 md.regsym[i] = declare_register (ar[i - REG_AR].name,
5924 REG_AR + ar[i - REG_AR].regnum);
5925
542d6675 5926 /* define synonyms for control registers: */
800eeca4
JW		 5927 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
5928 md.regsym[i] = declare_register (cr[i - REG_CR].name,
5929 REG_CR + cr[i - REG_CR].regnum);
5930
5931 declare_register ("gp", REG_GR + 1);
5932 declare_register ("sp", REG_GR + 12);
5933 declare_register ("rp", REG_BR + 0);
5934
542d6675 5935 /* pseudo-registers used to specify unwind info: */
e0c9811a
JW		 5936 declare_register ("psp", REG_PSP);
5937
800eeca4
JW		 5938 declare_register_set ("ret", 4, REG_GR + 8);
5939 declare_register_set ("farg", 8, REG_FR + 8);
5940 declare_register_set ("fret", 8, REG_FR + 8);
5941
5942 for (i = 0; i < NELEMS (const_bits); ++i)
5943 {
5944 err = hash_insert (md.const_hash, const_bits[i].name,
5945 (PTR) (const_bits + i));
5946 if (err)
5947 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5948 name, err);
5949 }
5950
5951 /* Default to 64-bit mode. */
c43c2cc5
JW		 5952 /* ??? This overrides the -M options, but they aren't working anyways. */
5953 md.flags |= EF_IA_64_ABI64;
800eeca4
JW		 5954
5955 md.mem_offset.hint = 0;
5956 md.path = 0;
5957 md.maxpaths = 0;
5958 md.entry_labels = NULL;
5959}
5960
5961void
5962ia64_end_of_source ()
5963{
542d6675 5964 /* terminate insn group upon reaching end of file: */
800eeca4
JW		 5965 insn_group_break (1, 0, 0);
5966
542d6675 5967 /* emits slots we haven't written yet: */
800eeca4
JW		 5968 ia64_flush_insns ();
5969
5970 bfd_set_private_flags (stdoutput, md.flags);
5971
5972 if (debug_type == DEBUG_DWARF2)
5973 dwarf2_finish ();
5974
5975 md.mem_offset.hint = 0;
5976}
5977
5978void
5979ia64_start_line ()
5980{
f1bcba5b
JW		 5981 if (md.qp.X_op == O_register)
5982 as_bad ("qualifying predicate not followed by instruction");
800eeca4
JW		 5983 md.qp.X_op = O_absent;
5984
5985 if (ignore_input ())
5986 return;
5987
5988 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
5989 {
5990 if (md.detect_dv && !md.explicit_mode)
542d6675 5991 as_warn (_("Explicit stops are ignored in auto mode"));
800eeca4 5992 else
542d6675 5993 insn_group_break (1, 0, 0);
800eeca4
JW		 5994 }
5995}
5996
f1bcba5b
JW		 5997/* This is a hook for ia64_frob_label, so that it can distinguish tags from
5998 labels. */
5999static int defining_tag = 0;
6000
800eeca4
JW		 6001int
6002ia64_unrecognized_line (ch)
6003 int ch;
6004{
6005 switch (ch)
6006 {
6007 case '(':
6008 expression (&md.qp);
6009 if (*input_line_pointer++ != ')')
6010 {
6011 as_bad ("Expected ')'");
6012 return 0;
6013 }
6014 if (md.qp.X_op != O_register)
6015 {
6016 as_bad ("Qualifying predicate expected");
6017 return 0;
6018 }
6019 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6020 {
6021 as_bad ("Predicate register expected");
6022 return 0;
6023 }
6024 return 1;
6025
6026 case '{':
6027 if (md.manual_bundling)
6028 as_warn ("Found '{' when manual bundling is already turned on");
6029 else
6030 CURR_SLOT.manual_bundling_on = 1;
6031 md.manual_bundling = 1;
6032
542d6675
KH		 6033 /* Bundling is only acceptable in explicit mode
6034 or when in default automatic mode. */
800eeca4 6035 if (md.detect_dv && !md.explicit_mode)
542d6675
KH		 6036 {
6037 if (!md.mode_explicitly_set
6038 && !md.default_explicit_mode)
6039 dot_dv_mode ('E');
6040 else
6041 as_warn (_("Found '{' after explicit switch to automatic mode"));
6042 }
800eeca4
JW		 6043 return 1;
6044
6045 case '}':
6046 if (!md.manual_bundling)
6047 as_warn ("Found '}' when manual bundling is off");
6048 else
6049 PREV_SLOT.manual_bundling_off = 1;
6050 md.manual_bundling = 0;
6051
6052 /* switch back to automatic mode, if applicable */
197865e8 6053 if (md.detect_dv
542d6675
KH		 6054 && md.explicit_mode
6055 && !md.mode_explicitly_set
6056 && !md.default_explicit_mode)
6057 dot_dv_mode ('A');
800eeca4
JW		 6058
6059 /* Allow '{' to follow on the same line. We also allow ";;", but that
6060 happens automatically because ';' is an end of line marker. */
6061 SKIP_WHITESPACE ();
6062 if (input_line_pointer[0] == '{')
6063 {
6064 input_line_pointer++;
6065 return ia64_unrecognized_line ('{');
6066 }
6067
6068 demand_empty_rest_of_line ();
6069 return 1;
6070
f1bcba5b
JW		 6071 case '[':
6072 {
6073 char *s;
6074 char c;
6075 symbolS *tag;
6076
6077 if (md.qp.X_op == O_register)
6078 {
6079 as_bad ("Tag must come before qualifying predicate.");
6080 return 0;
6081 }
6082 s = input_line_pointer;
6083 c = get_symbol_end ();
6084 if (c != ':')
6085 {
6086 /* Put ':' back for error messages' sake. */
6087 *input_line_pointer++ = ':';
6088 as_bad ("Expected ':'");
6089 return 0;
6090 }
6091 defining_tag = 1;
6092 tag = colon (s);
6093 defining_tag = 0;
6094 /* Put ':' back for error messages' sake. */
6095 *input_line_pointer++ = ':';
6096 if (*input_line_pointer++ != ']')
6097 {
6098 as_bad ("Expected ']'");
6099 return 0;
6100 }
6101 if (! tag)
6102 {
6103 as_bad ("Tag name expected");
6104 return 0;
6105 }
6106 return 1;
6107 }
6108
800eeca4
JW		 6109 default:
6110 break;
6111 }
542d6675
KH		 6112
6113 /* Not a valid line. */
6114 return 0;
800eeca4
JW		 6115}
6116
6117void
6118ia64_frob_label (sym)
6119 struct symbol *sym;
6120{
6121 struct label_fix *fix;
6122
f1bcba5b
JW		 6123 /* Tags need special handling since they are not bundle breaks like
6124 labels. */
6125 if (defining_tag)
6126 {
6127 fix = obstack_alloc (&notes, sizeof (*fix));
6128 fix->sym = sym;
6129 fix->next = CURR_SLOT.tag_fixups;
6130 CURR_SLOT.tag_fixups = fix;
6131
6132 return;
6133 }
6134
800eeca4
JW		 6135 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6136 {
6137 md.last_text_seg = now_seg;
6138 fix = obstack_alloc (&notes, sizeof (*fix));
6139 fix->sym = sym;
6140 fix->next = CURR_SLOT.label_fixups;
6141 CURR_SLOT.label_fixups = fix;
6142
542d6675 6143 /* Keep track of how many code entry points we've seen. */
800eeca4 6144 if (md.path == md.maxpaths)
542d6675
KH		 6145 {
6146 md.maxpaths += 20;
6147 md.entry_labels = (const char **)
6148 xrealloc ((void *) md.entry_labels,
6149 md.maxpaths * sizeof (char *));
6150 }
800eeca4
JW		 6151 md.entry_labels[md.path++] = S_GET_NAME (sym);
6152 }
6153}
6154
6155void
6156ia64_flush_pending_output ()
6157{
6158 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6159 {
6160 /* ??? This causes many unnecessary stop bits to be emitted.
6161 Unfortunately, it isn't clear if it is safe to remove this. */
6162 insn_group_break (1, 0, 0);
6163 ia64_flush_insns ();
6164 }
6165}
6166
6167/* Do ia64-specific expression optimization. All that's done here is
6168 to transform index expressions that are either due to the indexing
6169 of rotating registers or due to the indexing of indirect register
6170 sets. */
6171int
6172ia64_optimize_expr (l, op, r)
6173 expressionS *l;
6174 operatorT op;
6175 expressionS *r;
6176{
6177 unsigned num_regs;
6178
6179 if (op == O_index)
6180 {
6181 if (l->X_op == O_register && r->X_op == O_constant)
6182 {
6183 num_regs = (l->X_add_number >> 16);
6184 if ((unsigned) r->X_add_number >= num_regs)
6185 {
6186 if (!num_regs)
6187 as_bad ("No current frame");
6188 else
6189 as_bad ("Index out of range 0..%u", num_regs - 1);
6190 r->X_add_number = 0;
6191 }
6192 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6193 return 1;
6194 }
6195 else if (l->X_op == O_register && r->X_op == O_register)
6196 {
6197 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6198 || l->X_add_number == IND_MEM)
6199 {
6200 as_bad ("Indirect register set name expected");
6201 l->X_add_number = IND_CPUID;
6202 }
6203 l->X_op = O_index;
6204 l->X_op_symbol = md.regsym[l->X_add_number];
6205 l->X_add_number = r->X_add_number;
6206 return 1;
6207 }
6208 }
6209 return 0;
6210}
6211
6212int
6213ia64_parse_name (name, e)
6214 char *name;
6215 expressionS *e;
6216{
6217 struct const_desc *cdesc;
6218 struct dynreg *dr = 0;
6219 unsigned int regnum;
6220 struct symbol *sym;
6221 char *end;
6222
542d6675 6223 /* first see if NAME is a known register name: */
800eeca4
JW		 6224 sym = hash_find (md.reg_hash, name);
6225 if (sym)
6226 {
6227 e->X_op = O_register;
6228 e->X_add_number = S_GET_VALUE (sym);
6229 return 1;
6230 }
6231
6232 cdesc = hash_find (md.const_hash, name);
6233 if (cdesc)
6234 {
6235 e->X_op = O_constant;
6236 e->X_add_number = cdesc->value;
6237 return 1;
6238 }
6239
542d6675 6240 /* check for inN, locN, or outN: */
800eeca4
JW		 6241 switch (name[0])
6242 {
6243 case 'i':
6244 if (name[1] == 'n' && isdigit (name[2]))
6245 {
6246 dr = &md.in;
6247 name += 2;
6248 }
6249 break;
6250
6251 case 'l':
6252 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6253 {
6254 dr = &md.loc;
6255 name += 3;
6256 }
6257 break;
6258
6259 case 'o':
6260 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6261 {
6262 dr = &md.out;
6263 name += 3;
6264 }
6265 break;
6266
6267 default:
6268 break;
6269 }
6270
6271 if (dr)
6272 {
542d6675 6273 /* The name is inN, locN, or outN; parse the register number. */
800eeca4
JW		 6274 regnum = strtoul (name, &end, 10);
6275 if (end > name && *end == '\0')
6276 {
6277 if ((unsigned) regnum >= dr->num_regs)
6278 {
6279 if (!dr->num_regs)
6280 as_bad ("No current frame");
6281 else
542d6675
KH		 6282 as_bad ("Register number out of range 0..%u",
6283 dr->num_regs - 1);
800eeca4
JW		 6284 regnum = 0;
6285 }
6286 e->X_op = O_register;
6287 e->X_add_number = dr->base + regnum;
6288 return 1;
6289 }
6290 }
6291
6292 if ((dr = hash_find (md.dynreg_hash, name)))
6293 {
6294 /* We've got ourselves the name of a rotating register set.
542d6675
KH		 6295 Store the base register number in the low 16 bits of
6296 X_add_number and the size of the register set in the top 16
6297 bits. */
800eeca4
JW		 6298 e->X_op = O_register;
6299 e->X_add_number = dr->base | (dr->num_regs << 16);
6300 return 1;
6301 }
6302 return 0;
6303}
6304
6305/* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6306
6307char *
6308ia64_canonicalize_symbol_name (name)
6309 char *name;
6310{
542d6675
KH		 6311 size_t len = strlen (name);
6312 if (len > 1 && name[len - 1] == '#')
6313 name[len - 1] = '\0';
800eeca4
JW		 6314 return name;
6315}
6316
6317static int
6318is_conditional_branch (idesc)
542d6675 6319 struct ia64_opcode *idesc;
800eeca4
JW		 6320{
6321 return (strncmp (idesc->name, "br", 2) == 0
542d6675
KH		 6322 && (strcmp (idesc->name, "br") == 0
6323 || strncmp (idesc->name, "br.cond", 7) == 0
6324 || strncmp (idesc->name, "br.call", 7) == 0
6325 || strncmp (idesc->name, "br.ret", 6) == 0
6326 || strcmp (idesc->name, "brl") == 0
6327 || strncmp (idesc->name, "brl.cond", 7) == 0
6328 || strncmp (idesc->name, "brl.call", 7) == 0
6329 || strncmp (idesc->name, "brl.ret", 6) == 0));
800eeca4
JW		 6330}
6331
6332/* Return whether the given opcode is a taken branch. If there's any doubt,
542d6675
KH		 6333 returns zero. */
6334
800eeca4
JW		 6335static int
6336is_taken_branch (idesc)
542d6675 6337 struct ia64_opcode *idesc;
800eeca4
JW		 6338{
6339 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
542d6675 6340 || strncmp (idesc->name, "br.ia", 5) == 0);
800eeca4
JW		 6341}
6342
6343/* Return whether the given opcode is an interruption or rfi. If there's any
542d6675
KH		 6344 doubt, returns zero. */
6345
800eeca4
JW		 6346static int
6347is_interruption_or_rfi (idesc)
542d6675 6348 struct ia64_opcode *idesc;
800eeca4
JW		 6349{
6350 if (strcmp (idesc->name, "rfi") == 0)
6351 return 1;
6352 return 0;
6353}
6354
6355/* Returns the index of the given dependency in the opcode's list of chks, or
6356 -1 if there is no dependency. */
542d6675 6357
800eeca4
JW		 6358static int
6359depends_on (depind, idesc)
542d6675
KH		 6360 int depind;
6361 struct ia64_opcode *idesc;
800eeca4
JW		 6362{
6363 int i;
6364 const struct ia64_opcode_dependency *dep = idesc->dependencies;
542d6675 6365 for (i = 0; i < dep->nchks; i++)
800eeca4 6366 {
542d6675
KH		 6367 if (depind == DEP (dep->chks[i]))
6368 return i;
800eeca4
JW		 6369 }
6370 return -1;
6371}
6372
6373/* Determine a set of specific resources used for a particular resource
6374 class. Returns the number of specific resources identified For those
6375 cases which are not determinable statically, the resource returned is
197865e8 6376 marked nonspecific.
800eeca4
JW		 6377
6378 Meanings of value in 'NOTE':
6379 1) only read/write when the register number is explicitly encoded in the
6380 insn.
6381 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
197865e8 6382 accesses CFM when qualifying predicate is in the rotating region.
800eeca4
JW		 6383 3) general register value is used to specify an indirect register; not
6384 determinable statically.
6385 4) only read the given resource when bits 7:0 of the indirect index
6386 register value does not match the register number of the resource; not
6387 determinable statically.
6388 5) all rules are implementation specific.
6389 6) only when both the index specified by the reader and the index specified
6390 by the writer have the same value in bits 63:61; not determinable
197865e8 6391 statically.
800eeca4 6392 7) only access the specified resource when the corresponding mask bit is
197865e8 6393 set
800eeca4
JW		 6394 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6395 only read when these insns reference FR2-31
6396 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6397 written when these insns write FR32-127
6398 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6399 instruction
6400 11) The target predicates are written independently of PR[qp], but source
6401 registers are only read if PR[qp] is true. Since the state of PR[qp]
6402 cannot statically be determined, all source registers are marked used.
6403 12) This insn only reads the specified predicate register when that
6404 register is the PR[qp].
6405 13) This reference to ld-c only applies to teh GR whose value is loaded
197865e8 6406 with data returned from memory, not the post-incremented address register.
800eeca4
JW		 6407 14) The RSE resource includes the implementation-specific RSE internal
6408 state resources. At least one (and possibly more) of these resources are
6409 read by each instruction listed in IC:rse-readers. At least one (and
6410 possibly more) of these resources are written by each insn listed in
197865e8 6411 IC:rse-writers.
800eeca4 6412 15+16) Represents reserved instructions, which the assembler does not
197865e8 6413 generate.
800eeca4
JW		 6414
6415 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6416 this code; there are no dependency violations based on memory access.
800eeca4
JW		 6417*/
6418
6419#define MAX_SPECS 256
6420#define DV_CHK 1
6421#define DV_REG 0
6422
6423static int
6424specify_resource (dep, idesc, type, specs, note, path)
542d6675
KH		 6425 const struct ia64_dependency *dep;
6426 struct ia64_opcode *idesc;
6427 int type; /* is this a DV chk or a DV reg? */
6428 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6429 int note; /* resource note for this insn's usage */
6430 int path; /* which execution path to examine */
800eeca4
JW		 6431{
6432 int count = 0;
6433 int i;
6434 int rsrc_write = 0;
6435 struct rsrc tmpl;
197865e8 6436
800eeca4
JW		 6437 if (dep->mode == IA64_DV_WAW
6438 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6439 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6440 rsrc_write = 1;
6441
6442 /* template for any resources we identify */
6443 tmpl.dependency = dep;
6444 tmpl.note = note;
6445 tmpl.insn_srlz = tmpl.data_srlz = 0;
6446 tmpl.qp_regno = CURR_SLOT.qp_regno;
6447 tmpl.link_to_qp_branch = 1;
6448 tmpl.mem_offset.hint = 0;
6449 tmpl.specific = 1;
6450 tmpl.index = 0;
7484b8e6 6451 tmpl.cmp_type = CMP_NONE;
800eeca4
JW		 6452
6453#define UNHANDLED \
6454as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6455dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6456#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6457
6458 /* we don't need to track these */
6459 if (dep->semantics == IA64_DVS_NONE)
6460 return 0;
6461
6462 switch (dep->specifier)
6463 {
6464 case IA64_RS_AR_K:
6465 if (note == 1)
542d6675
KH		 6466 {
6467 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6468 {
6469 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6470 if (regno >= 0 && regno <= 7)
6471 {
6472 specs[count] = tmpl;
6473 specs[count++].index = regno;
6474 }
6475 }
6476 }
800eeca4 6477 else if (note == 0)
542d6675
KH		 6478 {
6479 for (i = 0; i < 8; i++)
6480 {
6481 specs[count] = tmpl;
6482 specs[count++].index = i;
6483 }
6484 }
800eeca4 6485 else
542d6675
KH		 6486 {
6487 UNHANDLED;
6488 }
800eeca4
JW		 6489 break;
6490
6491 case IA64_RS_AR_UNAT:
6492 /* This is a mov =AR or mov AR= instruction. */
6493 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6494 {
6495 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6496 if (regno == AR_UNAT)
6497 {
6498 specs[count++] = tmpl;
6499 }
6500 }
6501 else
6502 {
6503 /* This is a spill/fill, or other instruction that modifies the
6504 unat register. */
6505
6506 /* Unless we can determine the specific bits used, mark the whole
6507 thing; bits 8:3 of the memory address indicate the bit used in
6508 UNAT. The .mem.offset hint may be used to eliminate a small
6509 subset of conflicts. */
6510 specs[count] = tmpl;
6511 if (md.mem_offset.hint)
6512 {
542d6675
KH		 6513 if (md.debug_dv)
6514 fprintf (stderr, " Using hint for spill/fill\n");
6515 /* The index isn't actually used, just set it to something
6516 approximating the bit index. */
800eeca4
JW		 6517 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6518 specs[count].mem_offset.hint = 1;
6519 specs[count].mem_offset.offset = md.mem_offset.offset;
6520 specs[count++].mem_offset.base = md.mem_offset.base;
6521 }
6522 else
6523 {
6524 specs[count++].specific = 0;
6525 }
6526 }
6527 break;
6528
6529 case IA64_RS_AR:
6530 if (note == 1)
542d6675
KH		 6531 {
6532 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6533 {
6534 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6535 if ((regno >= 8 && regno <= 15)
6536 || (regno >= 20 && regno <= 23)
6537 || (regno >= 31 && regno <= 39)
6538 || (regno >= 41 && regno <= 47)
6539 || (regno >= 67 && regno <= 111))
6540 {
6541 specs[count] = tmpl;
6542 specs[count++].index = regno;
6543 }
6544 }
6545 }
800eeca4 6546 else
542d6675
KH		 6547 {
6548 UNHANDLED;
6549 }
800eeca4
JW		 6550 break;
6551
6552 case IA64_RS_ARb:
6553 if (note == 1)
542d6675
KH		 6554 {
6555 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6556 {
6557 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6558 if ((regno >= 48 && regno <= 63)
6559 || (regno >= 112 && regno <= 127))
6560 {
6561 specs[count] = tmpl;
6562 specs[count++].index = regno;
6563 }
6564 }
6565 }
800eeca4 6566 else if (note == 0)
542d6675
KH		 6567 {
6568 for (i = 48; i < 64; i++)
6569 {
6570 specs[count] = tmpl;
6571 specs[count++].index = i;
6572 }
6573 for (i = 112; i < 128; i++)
6574 {
6575 specs[count] = tmpl;
6576 specs[count++].index = i;
6577 }
6578 }
197865e8 6579 else
542d6675
KH		 6580 {
6581 UNHANDLED;
6582 }
800eeca4
JW		 6583 break;
6584
6585 case IA64_RS_BR:
6586 if (note != 1)
542d6675
KH		 6587 {
6588 UNHANDLED;
6589 }
800eeca4 6590 else
542d6675
KH		 6591 {
6592 if (rsrc_write)
6593 {
6594 for (i = 0; i < idesc->num_outputs; i++)
6595 if (idesc->operands[i] == IA64_OPND_B1
6596 || idesc->operands[i] == IA64_OPND_B2)
6597 {
6598 specs[count] = tmpl;
6599 specs[count++].index =
6600 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6601 }
6602 }
6603 else
6604 {
6605 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
6606 if (idesc->operands[i] == IA64_OPND_B1
6607 || idesc->operands[i] == IA64_OPND_B2)
6608 {
6609 specs[count] = tmpl;
6610 specs[count++].index =
6611 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6612 }
6613 }
6614 }
800eeca4
JW		 6615 break;
6616
6617 case IA64_RS_CPUID: /* four or more registers */
6618 if (note == 3)
542d6675
KH		 6619 {
6620 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6621 {
6622 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6623 if (regno >= 0 && regno < NELEMS (gr_values)
6624 && KNOWN (regno))
6625 {
6626 specs[count] = tmpl;
6627 specs[count++].index = gr_values[regno].value & 0xFF;
6628 }
6629 else
6630 {
6631 specs[count] = tmpl;
6632 specs[count++].specific = 0;
6633 }
6634 }
6635 }
800eeca4 6636 else
542d6675
KH		 6637 {
6638 UNHANDLED;
6639 }
800eeca4
JW		 6640 break;
6641
6642 case IA64_RS_DBR: /* four or more registers */
6643 if (note == 3)
542d6675
KH		 6644 {
6645 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6646 {
6647 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6648 if (regno >= 0 && regno < NELEMS (gr_values)
6649 && KNOWN (regno))
6650 {
6651 specs[count] = tmpl;
6652 specs[count++].index = gr_values[regno].value & 0xFF;
6653 }
6654 else
6655 {
6656 specs[count] = tmpl;
6657 specs[count++].specific = 0;
6658 }
6659 }
6660 }
800eeca4 6661 else if (note == 0 && !rsrc_write)
542d6675
KH		 6662 {
6663 specs[count] = tmpl;
6664 specs[count++].specific = 0;
6665 }
800eeca4 6666 else
542d6675
KH		 6667 {
6668 UNHANDLED;
6669 }
800eeca4
JW		 6670 break;
6671
6672 case IA64_RS_IBR: /* four or more registers */
6673 if (note == 3)
542d6675
KH		 6674 {
6675 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6676 {
6677 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6678 if (regno >= 0 && regno < NELEMS (gr_values)
6679 && KNOWN (regno))
6680 {
6681 specs[count] = tmpl;
6682 specs[count++].index = gr_values[regno].value & 0xFF;
6683 }
6684 else
6685 {
6686 specs[count] = tmpl;
6687 specs[count++].specific = 0;
6688 }
6689 }
6690 }
800eeca4 6691 else
542d6675
KH		 6692 {
6693 UNHANDLED;
6694 }
800eeca4
JW		 6695 break;
6696
6697 case IA64_RS_MSR:
6698 if (note == 5)
6699 {
6700 /* These are implementation specific. Force all references to
6701 conflict with all other references. */
6702 specs[count] = tmpl;
6703 specs[count++].specific = 0;
6704 }
6705 else
6706 {
6707 UNHANDLED;
6708 }
6709 break;
6710
6711 case IA64_RS_PKR: /* 16 or more registers */
6712 if (note == 3 || note == 4)
542d6675
KH		 6713 {
6714 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6715 {
6716 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6717 if (regno >= 0 && regno < NELEMS (gr_values)
6718 && KNOWN (regno))
6719 {
6720 if (note == 3)
6721 {
6722 specs[count] = tmpl;
6723 specs[count++].index = gr_values[regno].value & 0xFF;
6724 }
6725 else
6726 for (i = 0; i < NELEMS (gr_values); i++)
6727 {
6728 /* Uses all registers *except* the one in R3. */
6729 if (i != (gr_values[regno].value & 0xFF))
6730 {
6731 specs[count] = tmpl;
6732 specs[count++].index = i;
6733 }
6734 }
6735 }
6736 else
6737 {
6738 specs[count] = tmpl;
6739 specs[count++].specific = 0;
6740 }
6741 }
6742 }
6743 else if (note == 0)
6744 {
6745 /* probe et al. */
6746 specs[count] = tmpl;
6747 specs[count++].specific = 0;
6748 }
6749 break;
6750
6751 case IA64_RS_PMC: /* four or more registers */
6752 if (note == 3)
6753 {
6754 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
6755 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
6756
6757 {
6758 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
6759 ? 1 : !rsrc_write);
6760 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
6761 if (regno >= 0 && regno < NELEMS (gr_values)
6762 && KNOWN (regno))
6763 {
6764 specs[count] = tmpl;
6765 specs[count++].index = gr_values[regno].value & 0xFF;
6766 }
6767 else
6768 {
6769 specs[count] = tmpl;
6770 specs[count++].specific = 0;
6771 }
6772 }
6773 }
6774 else
6775 {
6776 UNHANDLED;
6777 }
800eeca4
JW		 6778 break;
6779
6780 case IA64_RS_PMD: /* four or more registers */
6781 if (note == 3)
542d6675
KH		 6782 {
6783 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
6784 {
6785 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6786 if (regno >= 0 && regno < NELEMS (gr_values)
6787 && KNOWN (regno))
6788 {
6789 specs[count] = tmpl;
6790 specs[count++].index = gr_values[regno].value & 0xFF;
6791 }
6792 else
6793 {
6794 specs[count] = tmpl;
6795 specs[count++].specific = 0;
6796 }
6797 }
6798 }
800eeca4 6799 else
542d6675
KH		 6800 {
6801 UNHANDLED;
6802 }
800eeca4
JW		 6803 break;
6804
6805 case IA64_RS_RR: /* eight registers */
6806 if (note == 6)
542d6675
KH		 6807 {
6808 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
6809 {
6810 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6811 if (regno >= 0 && regno < NELEMS (gr_values)
6812 && KNOWN (regno))
6813 {
6814 specs[count] = tmpl;
6815 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
6816 }
6817 else
6818 {
6819 specs[count] = tmpl;
6820 specs[count++].specific = 0;
6821 }
6822 }
6823 }
800eeca4 6824 else if (note == 0 && !rsrc_write)
542d6675
KH		 6825 {
6826 specs[count] = tmpl;
6827 specs[count++].specific = 0;
6828 }
197865e8 6829 else
542d6675
KH		 6830 {
6831 UNHANDLED;
6832 }
800eeca4
JW		 6833 break;
6834
6835 case IA64_RS_CR_IRR:
197865e8 6836 if (note == 0)
542d6675
KH		 6837 {
6838 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6839 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
6840 if (rsrc_write
6841 && idesc->operands[1] == IA64_OPND_CR3
6842 && regno == CR_IVR)
6843 {
6844 for (i = 0; i < 4; i++)
6845 {
6846 specs[count] = tmpl;
6847 specs[count++].index = CR_IRR0 + i;
6848 }
6849 }
6850 }
800eeca4 6851 else if (note == 1)
542d6675
KH		 6852 {
6853 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6854 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6855 && regno >= CR_IRR0
6856 && regno <= CR_IRR3)
6857 {
6858 specs[count] = tmpl;
6859 specs[count++].index = regno;
6860 }
6861 }
800eeca4 6862 else
542d6675
KH		 6863 {
6864 UNHANDLED;
6865 }
800eeca4
JW		 6866 break;
6867
6868 case IA64_RS_CR_LRR:
6869 if (note != 1)
542d6675
KH		 6870 {
6871 UNHANDLED;
6872 }
197865e8 6873 else
542d6675
KH		 6874 {
6875 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6876 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6877 && (regno == CR_LRR0 || regno == CR_LRR1))
6878 {
6879 specs[count] = tmpl;
6880 specs[count++].index = regno;
6881 }
6882 }
800eeca4
JW		 6883 break;
6884
6885 case IA64_RS_CR:
6886 if (note == 1)
542d6675
KH		 6887 {
6888 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
6889 {
6890 specs[count] = tmpl;
6891 specs[count++].index =
6892 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6893 }
6894 }
800eeca4 6895 else
542d6675
KH		 6896 {
6897 UNHANDLED;
6898 }
800eeca4
JW		 6899 break;
6900
6901 case IA64_RS_FR:
6902 case IA64_RS_FRb:
6903 if (note != 1)
542d6675
KH		 6904 {
6905 UNHANDLED;
6906 }
800eeca4 6907 else if (rsrc_write)
542d6675
KH		 6908 {
6909 if (dep->specifier == IA64_RS_FRb
6910 && idesc->operands[0] == IA64_OPND_F1)
6911 {
6912 specs[count] = tmpl;
6913 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
6914 }
6915 }
800eeca4 6916 else
542d6675
KH		 6917 {
6918 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
6919 {
6920 if (idesc->operands[i] == IA64_OPND_F2
6921 || idesc->operands[i] == IA64_OPND_F3
6922 || idesc->operands[i] == IA64_OPND_F4)
6923 {
6924 specs[count] = tmpl;
6925 specs[count++].index =
6926 CURR_SLOT.opnd[i].X_add_number - REG_FR;
6927 }
6928 }
6929 }
800eeca4
JW		 6930 break;
6931
6932 case IA64_RS_GR:
6933 if (note == 13)
542d6675
KH		 6934 {
6935 /* This reference applies only to the GR whose value is loaded with
6936 data returned from memory. */
6937 specs[count] = tmpl;
6938 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
6939 }
800eeca4 6940 else if (note == 1)
542d6675
KH		 6941 {
6942 if (rsrc_write)
6943 {
6944 for (i = 0; i < idesc->num_outputs; i++)
50b81f19
JW		 6945 if (idesc->operands[i] == IA64_OPND_R1
6946 || idesc->operands[i] == IA64_OPND_R2
6947 || idesc->operands[i] == IA64_OPND_R3)
6948 {
6949 specs[count] = tmpl;
197865e8 6950 specs[count++].index =
50b81f19
JW		 6951 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6952 }
6953 if (idesc->flags & IA64_OPCODE_POSTINC)
6954 for (i = 0; i < NELEMS (idesc->operands); i++)
6955 if (idesc->operands[i] == IA64_OPND_MR3)
6956 {
6957 specs[count] = tmpl;
6958 specs[count++].index =
6959 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6960 }
542d6675
KH		 6961 }
6962 else
6963 {
6964 /* Look for anything that reads a GR. */
6965 for (i = 0; i < NELEMS (idesc->operands); i++)
6966 {
6967 if (idesc->operands[i] == IA64_OPND_MR3
6968 || idesc->operands[i] == IA64_OPND_CPUID_R3
6969 || idesc->operands[i] == IA64_OPND_DBR_R3
6970 || idesc->operands[i] == IA64_OPND_IBR_R3
800eeca4 6971 || idesc->operands[i] == IA64_OPND_MSR_R3
542d6675
KH		 6972 || idesc->operands[i] == IA64_OPND_PKR_R3
6973 || idesc->operands[i] == IA64_OPND_PMC_R3
6974 || idesc->operands[i] == IA64_OPND_PMD_R3
6975 || idesc->operands[i] == IA64_OPND_RR_R3
6976 || ((i >= idesc->num_outputs)
6977 && (idesc->operands[i] == IA64_OPND_R1
6978 || idesc->operands[i] == IA64_OPND_R2
6979 || idesc->operands[i] == IA64_OPND_R3
50b81f19
JW		 6980 /* addl source register. */
6981 || idesc->operands[i] == IA64_OPND_R3_2)))
542d6675
KH		 6982 {
6983 specs[count] = tmpl;
6984 specs[count++].index =
6985 CURR_SLOT.opnd[i].X_add_number - REG_GR;
6986 }
6987 }
6988 }
6989 }
197865e8 6990 else
542d6675
KH		 6991 {
6992 UNHANDLED;
6993 }
800eeca4
JW		 6994 break;
6995
139368c9
JW		 6996 /* This is the same as IA64_RS_PRr, except that the register range is
6997 from 1 - 15, and there are no rotating register reads/writes here. */
800eeca4
JW		 6998 case IA64_RS_PR:
6999 if (note == 0)
542d6675 7000 {
139368c9 7001 for (i = 1; i < 16; i++)
542d6675 7002 {
139368c9
JW		 7003 specs[count] = tmpl;
7004 specs[count++].index = i;
7005 }
7006 }
7007 else if (note == 7)
7008 {
7009 valueT mask = 0;
7010 /* Mark only those registers indicated by the mask. */
7011 if (rsrc_write)
7012 {
7013 mask = CURR_SLOT.opnd[2].X_add_number;
7014 for (i = 1; i < 16; i++)
7015 if (mask & ((valueT) 1 << i))
7016 {
7017 specs[count] = tmpl;
7018 specs[count++].index = i;
7019 }
7020 }
7021 else
7022 {
7023 UNHANDLED;
7024 }
7025 }
7026 else if (note == 11) /* note 11 implies note 1 as well */
7027 {
7028 if (rsrc_write)
7029 {
7030 for (i = 0; i < idesc->num_outputs; i++)
7031 {
7032 if (idesc->operands[i] == IA64_OPND_P1
7033 || idesc->operands[i] == IA64_OPND_P2)
7034 {
7035 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7036 if (regno >= 1 && regno < 16)
7037 {
7038 specs[count] = tmpl;
7039 specs[count++].index = regno;
7040 }
7041 }
7042 }
7043 }
7044 else
7045 {
7046 UNHANDLED;
7047 }
7048 }
7049 else if (note == 12)
7050 {
7051 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7052 {
7053 specs[count] = tmpl;
7054 specs[count++].index = CURR_SLOT.qp_regno;
7055 }
7056 }
7057 else if (note == 1)
7058 {
7059 if (rsrc_write)
7060 {
7061 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7062 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7063 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7064 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7065
7066 if ((idesc->operands[0] == IA64_OPND_P1
7067 || idesc->operands[0] == IA64_OPND_P2)
7068 && p1 >= 1 && p1 < 16)
542d6675
KH		 7069 {
7070 specs[count] = tmpl;
139368c9
JW		 7071 specs[count].cmp_type =
7072 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7073 specs[count++].index = p1;
7074 }
7075 if ((idesc->operands[1] == IA64_OPND_P1
7076 || idesc->operands[1] == IA64_OPND_P2)
7077 && p2 >= 1 && p2 < 16)
7078 {
7079 specs[count] = tmpl;
7080 specs[count].cmp_type =
7081 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7082 specs[count++].index = p2;
542d6675
KH		 7083 }
7084 }
7085 else
7086 {
139368c9 7087 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
542d6675
KH		 7088 {
7089 specs[count] = tmpl;
139368c9
JW		 7090 specs[count++].index = CURR_SLOT.qp_regno;
7091 }
7092 if (idesc->operands[1] == IA64_OPND_PR)
7093 {
7094 for (i = 1; i < 16; i++)
7095 {
7096 specs[count] = tmpl;
7097 specs[count++].index = i;
7098 }
542d6675
KH		 7099 }
7100 }
7101 }
139368c9
JW		 7102 else
7103 {
7104 UNHANDLED;
7105 }
7106 break;
7107
7108 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7109 simplified cases of this. */
7110 case IA64_RS_PRr:
7111 if (note == 0)
7112 {
7113 for (i = 16; i < 63; i++)
7114 {
7115 specs[count] = tmpl;
7116 specs[count++].index = i;
7117 }
7118 }
800eeca4 7119 else if (note == 7)
542d6675
KH		 7120 {
7121 valueT mask = 0;
7122 /* Mark only those registers indicated by the mask. */
7123 if (rsrc_write
7124 && idesc->operands[0] == IA64_OPND_PR)
7125 {
7126 mask = CURR_SLOT.opnd[2].X_add_number;
139368c9
JW		 7127 if (mask & ((valueT) 1<<16))
7128 for (i = 16; i < 63; i++)
7129 {
7130 specs[count] = tmpl;
7131 specs[count++].index = i;
7132 }
542d6675
KH		 7133 }
7134 else if (rsrc_write
7135 && idesc->operands[0] == IA64_OPND_PR_ROT)
7136 {
7137 for (i = 16; i < 63; i++)
7138 {
7139 specs[count] = tmpl;
7140 specs[count++].index = i;
7141 }
7142 }
7143 else
7144 {
7145 UNHANDLED;
7146 }
7147 }
800eeca4 7148 else if (note == 11) /* note 11 implies note 1 as well */
542d6675
KH		 7149 {
7150 if (rsrc_write)
7151 {
7152 for (i = 0; i < idesc->num_outputs; i++)
7153 {
7154 if (idesc->operands[i] == IA64_OPND_P1
7155 || idesc->operands[i] == IA64_OPND_P2)
7156 {
7157 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
139368c9 7158 if (regno >= 16 && regno < 63)
542d6675
KH		 7159 {
7160 specs[count] = tmpl;
7161 specs[count++].index = regno;
7162 }
7163 }
7164 }
7165 }
7166 else
7167 {
7168 UNHANDLED;
7169 }
7170 }
800eeca4 7171 else if (note == 12)
542d6675 7172 {
139368c9 7173 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH		 7174 {
7175 specs[count] = tmpl;
7176 specs[count++].index = CURR_SLOT.qp_regno;
7177 }
7178 }
800eeca4 7179 else if (note == 1)
542d6675
KH		 7180 {
7181 if (rsrc_write)
7182 {
7183 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7184 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7484b8e6
TW		 7185 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7186 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7187
542d6675
KH		 7188 if ((idesc->operands[0] == IA64_OPND_P1
7189 || idesc->operands[0] == IA64_OPND_P2)
139368c9 7190 && p1 >= 16 && p1 < 63)
542d6675
KH		 7191 {
7192 specs[count] = tmpl;
4a4f25cf 7193 specs[count].cmp_type =
7484b8e6 7194 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
542d6675
KH		 7195 specs[count++].index = p1;
7196 }
7197 if ((idesc->operands[1] == IA64_OPND_P1
7198 || idesc->operands[1] == IA64_OPND_P2)
139368c9 7199 && p2 >= 16 && p2 < 63)
542d6675
KH		 7200 {
7201 specs[count] = tmpl;
4a4f25cf 7202 specs[count].cmp_type =
7484b8e6 7203 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
542d6675
KH		 7204 specs[count++].index = p2;
7205 }
7206 }
7207 else
7208 {
139368c9 7209 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
542d6675
KH		 7210 {
7211 specs[count] = tmpl;
7212 specs[count++].index = CURR_SLOT.qp_regno;
7213 }
7214 if (idesc->operands[1] == IA64_OPND_PR)
7215 {
139368c9 7216 for (i = 16; i < 63; i++)
542d6675
KH		 7217 {
7218 specs[count] = tmpl;
7219 specs[count++].index = i;
7220 }
7221 }
7222 }
7223 }
197865e8 7224 else
542d6675
KH		 7225 {
7226 UNHANDLED;
7227 }
800eeca4
JW		 7228 break;
7229
7230 case IA64_RS_PSR:
197865e8 7231 /* Verify that the instruction is using the PSR bit indicated in
542d6675 7232 dep->regindex. */
800eeca4 7233 if (note == 0)
542d6675
KH		 7234 {
7235 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7236 {
7237 if (dep->regindex < 6)
7238 {
7239 specs[count++] = tmpl;
7240 }
7241 }
7242 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7243 {
7244 if (dep->regindex < 32
7245 || dep->regindex == 35
7246 || dep->regindex == 36
7247 || (!rsrc_write && dep->regindex == PSR_CPL))
7248 {
7249 specs[count++] = tmpl;
7250 }
7251 }
7252 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7253 {
7254 if (dep->regindex < 32
7255 || dep->regindex == 35
7256 || dep->regindex == 36
7257 || (rsrc_write && dep->regindex == PSR_CPL))
7258 {
7259 specs[count++] = tmpl;
7260 }
7261 }
7262 else
7263 {
7264 /* Several PSR bits have very specific dependencies. */
7265 switch (dep->regindex)
7266 {
7267 default:
7268 specs[count++] = tmpl;
7269 break;
7270 case PSR_IC:
7271 if (rsrc_write)
7272 {
7273 specs[count++] = tmpl;
7274 }
7275 else
7276 {
7277 /* Only certain CR accesses use PSR.ic */
7278 if (idesc->operands[0] == IA64_OPND_CR3
7279 || idesc->operands[1] == IA64_OPND_CR3)
7280 {
7281 int index =
7282 ((idesc->operands[0] == IA64_OPND_CR3)
7283 ? 0 : 1);
7284 int regno =
7285 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7286
7287 switch (regno)
7288 {
7289 default:
7290 break;
7291 case CR_ITIR:
7292 case CR_IFS:
7293 case CR_IIM:
7294 case CR_IIP:
7295 case CR_IPSR:
7296 case CR_ISR:
7297 case CR_IFA:
7298 case CR_IHA:
7299 case CR_IIPA:
7300 specs[count++] = tmpl;
7301 break;
7302 }
7303 }
7304 }
7305 break;
7306 case PSR_CPL:
7307 if (rsrc_write)
7308 {
7309 specs[count++] = tmpl;
7310 }
7311 else
7312 {
7313 /* Only some AR accesses use cpl */
7314 if (idesc->operands[0] == IA64_OPND_AR3
7315 || idesc->operands[1] == IA64_OPND_AR3)
7316 {
7317 int index =
7318 ((idesc->operands[0] == IA64_OPND_AR3)
7319 ? 0 : 1);
7320 int regno =
7321 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7322
7323 if (regno == AR_ITC
7324 || (index == 0
7325 && (regno == AR_ITC
7326 || regno == AR_RSC
7327 || (regno >= AR_K0
7328 && regno <= AR_K7))))
7329 {
7330 specs[count++] = tmpl;
7331 }
7332 }
7333 else
7334 {
7335 specs[count++] = tmpl;
7336 }
7337 break;
7338 }
7339 }
7340 }
7341 }
800eeca4 7342 else if (note == 7)
542d6675
KH		 7343 {
7344 valueT mask = 0;
7345 if (idesc->operands[0] == IA64_OPND_IMMU24)
7346 {
7347 mask = CURR_SLOT.opnd[0].X_add_number;
7348 }
7349 else
7350 {
7351 UNHANDLED;
7352 }
7353 if (mask & ((valueT) 1 << dep->regindex))
7354 {
7355 specs[count++] = tmpl;
7356 }
7357 }
800eeca4 7358 else if (note == 8)
542d6675
KH		 7359 {
7360 int min = dep->regindex == PSR_DFL ? 2 : 32;
7361 int max = dep->regindex == PSR_DFL ? 31 : 127;
7362 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7363 for (i = 0; i < NELEMS (idesc->operands); i++)
7364 {
7365 if (idesc->operands[i] == IA64_OPND_F1
7366 || idesc->operands[i] == IA64_OPND_F2
7367 || idesc->operands[i] == IA64_OPND_F3
7368 || idesc->operands[i] == IA64_OPND_F4)
7369 {
7370 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7371 if (reg >= min && reg <= max)
7372 {
7373 specs[count++] = tmpl;
7374 }
7375 }
7376 }
7377 }
800eeca4 7378 else if (note == 9)
542d6675
KH		 7379 {
7380 int min = dep->regindex == PSR_MFL ? 2 : 32;
7381 int max = dep->regindex == PSR_MFL ? 31 : 127;
7382 /* mfh is read on writes to FR32-127; mfl is read on writes to
7383 FR2-31 */
7384 for (i = 0; i < idesc->num_outputs; i++)
7385 {
7386 if (idesc->operands[i] == IA64_OPND_F1)
7387 {
7388 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7389 if (reg >= min && reg <= max)
7390 {
7391 specs[count++] = tmpl;
7392 }
7393 }
7394 }
7395 }
800eeca4 7396 else if (note == 10)
542d6675
KH		 7397 {
7398 for (i = 0; i < NELEMS (idesc->operands); i++)
7399 {
7400 if (idesc->operands[i] == IA64_OPND_R1
7401 || idesc->operands[i] == IA64_OPND_R2
7402 || idesc->operands[i] == IA64_OPND_R3)
7403 {
7404 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7405 if (regno >= 16 && regno <= 31)
7406 {
7407 specs[count++] = tmpl;
7408 }
7409 }
7410 }
7411 }
800eeca4 7412 else
542d6675
KH		 7413 {
7414 UNHANDLED;
7415 }
800eeca4
JW		 7416 break;
7417
7418 case IA64_RS_AR_FPSR:
7419 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
542d6675
KH		 7420 {
7421 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7422 if (regno == AR_FPSR)
7423 {
7424 specs[count++] = tmpl;
7425 }
7426 }
800eeca4 7427 else
542d6675
KH		 7428 {
7429 specs[count++] = tmpl;
7430 }
800eeca4
JW		 7431 break;
7432
197865e8 7433 case IA64_RS_ARX:
800eeca4
JW		 7434 /* Handle all AR[REG] resources */
7435 if (note == 0 || note == 1)
542d6675
KH		 7436 {
7437 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7438 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7439 && regno == dep->regindex)
7440 {
7441 specs[count++] = tmpl;
7442 }
7443 /* other AR[REG] resources may be affected by AR accesses */
7444 else if (idesc->operands[0] == IA64_OPND_AR3)
7445 {
7446 /* AR[] writes */
7447 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7448 switch (dep->regindex)
7449 {
7450 default:
7451 break;
7452 case AR_BSP:
7453 case AR_RNAT:
7454 if (regno == AR_BSPSTORE)
7455 {
7456 specs[count++] = tmpl;
7457 }
7458 case AR_RSC:
7459 if (!rsrc_write &&
7460 (regno == AR_BSPSTORE
7461 || regno == AR_RNAT))
7462 {
7463 specs[count++] = tmpl;
7464 }
7465 break;
7466 }
7467 }
7468 else if (idesc->operands[1] == IA64_OPND_AR3)
7469 {
7470 /* AR[] reads */
7471 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7472 switch (dep->regindex)
7473 {
7474 default:
7475 break;
7476 case AR_RSC:
7477 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7478 {
7479 specs[count++] = tmpl;
7480 }
7481 break;
7482 }
7483 }
7484 else
7485 {
7486 specs[count++] = tmpl;
7487 }
7488 }
800eeca4 7489 else
542d6675
KH		 7490 {
7491 UNHANDLED;
7492 }
800eeca4
JW		 7493 break;
7494
7495 case IA64_RS_CRX:
7496 /* Handle all CR[REG] resources */
7497 if (note == 0 || note == 1)
542d6675
KH		 7498 {
7499 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7500 {
7501 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7502 if (regno == dep->regindex)
7503 {
7504 specs[count++] = tmpl;
7505 }
7506 else if (!rsrc_write)
7507 {
7508 /* Reads from CR[IVR] affect other resources. */
7509 if (regno == CR_IVR)
7510 {
7511 if ((dep->regindex >= CR_IRR0
7512 && dep->regindex <= CR_IRR3)
7513 || dep->regindex == CR_TPR)
7514 {
7515 specs[count++] = tmpl;
7516 }
7517 }
7518 }
7519 }
7520 else
7521 {
7522 specs[count++] = tmpl;
7523 }
7524 }
800eeca4 7525 else
542d6675
KH		 7526 {
7527 UNHANDLED;
7528 }
800eeca4
JW		 7529 break;
7530
7531 case IA64_RS_INSERVICE:
7532 /* look for write of EOI (67) or read of IVR (65) */
7533 if ((idesc->operands[0] == IA64_OPND_CR3
542d6675
KH		 7534 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7535 || (idesc->operands[1] == IA64_OPND_CR3
7536 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7537 {
7538 specs[count++] = tmpl;
7539 }
800eeca4
JW		 7540 break;
7541
7542 case IA64_RS_GR0:
7543 if (note == 1)
542d6675
KH		 7544 {
7545 specs[count++] = tmpl;
7546 }
800eeca4 7547 else
542d6675
KH		 7548 {
7549 UNHANDLED;
7550 }
800eeca4
JW		 7551 break;
7552
7553 case IA64_RS_CFM:
7554 if (note != 2)
542d6675
KH		 7555 {
7556 specs[count++] = tmpl;
7557 }
800eeca4 7558 else
542d6675
KH		 7559 {
7560 /* Check if any of the registers accessed are in the rotating region.
7561 mov to/from pr accesses CFM only when qp_regno is in the rotating
7562 region */
7563 for (i = 0; i < NELEMS (idesc->operands); i++)
7564 {
7565 if (idesc->operands[i] == IA64_OPND_R1
7566 || idesc->operands[i] == IA64_OPND_R2
7567 || idesc->operands[i] == IA64_OPND_R3)
7568 {
7569 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7570 /* Assumes that md.rot.num_regs is always valid */
7571 if (md.rot.num_regs > 0
7572 && num > 31
7573 && num < 31 + md.rot.num_regs)
7574 {
7575 specs[count] = tmpl;
7576 specs[count++].specific = 0;
7577 }
7578 }
7579 else if (idesc->operands[i] == IA64_OPND_F1
7580 || idesc->operands[i] == IA64_OPND_F2
7581 || idesc->operands[i] == IA64_OPND_F3
7582 || idesc->operands[i] == IA64_OPND_F4)
7583 {
7584 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7585 if (num > 31)
7586 {
7587 specs[count] = tmpl;
7588 specs[count++].specific = 0;
7589 }
7590 }
7591 else if (idesc->operands[i] == IA64_OPND_P1
7592 || idesc->operands[i] == IA64_OPND_P2)
7593 {
7594 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7595 if (num > 15)
7596 {
7597 specs[count] = tmpl;
7598 specs[count++].specific = 0;
7599 }
7600 }
7601 }
7602 if (CURR_SLOT.qp_regno > 15)
7603 {
7604 specs[count] = tmpl;
7605 specs[count++].specific = 0;
7606 }
7607 }
800eeca4
JW		 7608 break;
7609
139368c9
JW		 7610 /* This is the same as IA64_RS_PRr, except simplified to account for
7611 the fact that there is only one register. */
800eeca4
JW		 7612 case IA64_RS_PR63:
7613 if (note == 0)
542d6675
KH		 7614 {
7615 specs[count++] = tmpl;
7616 }
139368c9
JW		 7617 else if (note == 7)
7618 {
7619 valueT mask = 0;
7620 if (idesc->operands[2] == IA64_OPND_IMM17)
7621 mask = CURR_SLOT.opnd[2].X_add_number;
7622 if (mask & ((valueT) 1 << 63))
7623 specs[count++] = tmpl;
7624 }
800eeca4 7625 else if (note == 11)
542d6675
KH		 7626 {
7627 if ((idesc->operands[0] == IA64_OPND_P1
7628 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7629 || (idesc->operands[1] == IA64_OPND_P2
7630 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7631 {
7632 specs[count++] = tmpl;
7633 }
7634 }
800eeca4 7635 else if (note == 12)
542d6675
KH		 7636 {
7637 if (CURR_SLOT.qp_regno == 63)
7638 {
7639 specs[count++] = tmpl;
7640 }
7641 }
800eeca4 7642 else if (note == 1)
542d6675
KH		 7643 {
7644 if (rsrc_write)
7645 {
7484b8e6
TW		 7646 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7647 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7648 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7649 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7650
4a4f25cf 7651 if (p1 == 63
7484b8e6
TW		 7652 && (idesc->operands[0] == IA64_OPND_P1
7653 || idesc->operands[0] == IA64_OPND_P2))
7654 {
7655 specs[count] = tmpl;
4a4f25cf 7656 specs[count++].cmp_type =
7484b8e6
TW		 7657 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7658 }
7659 if (p2 == 63
7660 && (idesc->operands[1] == IA64_OPND_P1
7661 || idesc->operands[1] == IA64_OPND_P2))
7662 {
7663 specs[count] = tmpl;
4a4f25cf 7664 specs[count++].cmp_type =
7484b8e6
TW		 7665 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7666 }
542d6675
KH		 7667 }
7668 else
7669 {
7670 if (CURR_SLOT.qp_regno == 63)
7671 {
7672 specs[count++] = tmpl;
7673 }
7674 }
7675 }
800eeca4 7676 else
542d6675
KH		 7677 {
7678 UNHANDLED;
7679 }
800eeca4
JW		 7680 break;
7681
7682 case IA64_RS_RSE:
7683 /* FIXME we can identify some individual RSE written resources, but RSE
542d6675
KH		 7684 read resources have not yet been completely identified, so for now
7685 treat RSE as a single resource */
800eeca4 7686 if (strncmp (idesc->name, "mov", 3) == 0)
542d6675
KH		 7687 {
7688 if (rsrc_write)
7689 {
7690 if (idesc->operands[0] == IA64_OPND_AR3
7691 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7692 {
7693 specs[count] = tmpl;
7694 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7695 }
7696 }
7697 else
7698 {
7699 if (idesc->operands[0] == IA64_OPND_AR3)
7700 {
7701 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7702 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7703 {
7704 specs[count++] = tmpl;
7705 }
7706 }
7707 else if (idesc->operands[1] == IA64_OPND_AR3)
7708 {
7709 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7710 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7711 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7712 {
7713 specs[count++] = tmpl;
7714 }
7715 }
7716 }
7717 }
197865e8 7718 else
542d6675
KH		 7719 {
7720 specs[count++] = tmpl;
7721 }
800eeca4
JW		 7722 break;
7723
7724 case IA64_RS_ANY:
7725 /* FIXME -- do any of these need to be non-specific? */
7726 specs[count++] = tmpl;
7727 break;
7728
7729 default:
7730 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7731 break;
7732 }
7733
7734 return count;
7735}
7736
7737/* Clear branch flags on marked resources. This breaks the link between the
542d6675
KH		 7738 QP of the marking instruction and a subsequent branch on the same QP. */
7739
800eeca4
JW		 7740static void
7741clear_qp_branch_flag (mask)
542d6675 7742 valueT mask;
800eeca4
JW		 7743{
7744 int i;
542d6675 7745 for (i = 0; i < regdepslen; i++)
800eeca4 7746 {
197865e8 7747 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
800eeca4 7748 if ((bit & mask) != 0)
542d6675
KH		 7749 {
7750 regdeps[i].link_to_qp_branch = 0;
7751 }
800eeca4
JW		 7752 }
7753}
7754
197865e8 7755/* Remove any mutexes which contain any of the PRs indicated in the mask.
800eeca4 7756
542d6675
KH		 7757 Any changes to a PR clears the mutex relations which include that PR. */
7758
800eeca4
JW		 7759static void
7760clear_qp_mutex (mask)
542d6675 7761 valueT mask;
800eeca4
JW		 7762{
7763 int i;
7764
7765 i = 0;
7766 while (i < qp_mutexeslen)
7767 {
7768 if ((qp_mutexes[i].prmask & mask) != 0)
542d6675
KH		 7769 {
7770 if (md.debug_dv)
7771 {
7772 fprintf (stderr, " Clearing mutex relation");
7773 print_prmask (qp_mutexes[i].prmask);
7774 fprintf (stderr, "\n");
7775 }
7776 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
7777 }
800eeca4 7778 else
542d6675 7779 ++i;
800eeca4
JW		 7780 }
7781}
7782
7783/* Clear implies relations which contain PRs in the given masks.
7784 P1_MASK indicates the source of the implies relation, while P2_MASK
542d6675
KH		 7785 indicates the implied PR. */
7786
800eeca4
JW		 7787static void
7788clear_qp_implies (p1_mask, p2_mask)
542d6675
KH		 7789 valueT p1_mask;
7790 valueT p2_mask;
800eeca4
JW		 7791{
7792 int i;
7793
7794 i = 0;
7795 while (i < qp_implieslen)
7796 {
197865e8 7797 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
542d6675
KH		 7798 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
7799 {
7800 if (md.debug_dv)
7801 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
7802 qp_implies[i].p1, qp_implies[i].p2);
7803 qp_implies[i] = qp_implies[--qp_implieslen];
7804 }
197865e8 7805 else
542d6675 7806 ++i;
800eeca4
JW		 7807 }
7808}
7809
542d6675
KH		 7810/* Add the PRs specified to the list of implied relations. */
7811
800eeca4
JW		 7812static void
7813add_qp_imply (p1, p2)
542d6675 7814 int p1, p2;
800eeca4
JW		 7815{
7816 valueT mask;
7817 valueT bit;
7818 int i;
7819
542d6675 7820 /* p0 is not meaningful here. */
800eeca4
JW		 7821 if (p1 == 0 || p2 == 0)
7822 abort ();
7823
7824 if (p1 == p2)
7825 return;
7826
542d6675
KH		 7827 /* If it exists already, ignore it. */
7828 for (i = 0; i < qp_implieslen; i++)
800eeca4 7829 {
197865e8 7830 if (qp_implies[i].p1 == p1
542d6675
KH		 7831 && qp_implies[i].p2 == p2
7832 && qp_implies[i].path == md.path
7833 && !qp_implies[i].p2_branched)
7834 return;
800eeca4
JW		 7835 }
7836
7837 if (qp_implieslen == qp_impliestotlen)
7838 {
7839 qp_impliestotlen += 20;
7840 qp_implies = (struct qp_imply *)
542d6675
KH		 7841 xrealloc ((void *) qp_implies,
7842 qp_impliestotlen * sizeof (struct qp_imply));
800eeca4
JW		 7843 }
7844 if (md.debug_dv)
7845 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
7846 qp_implies[qp_implieslen].p1 = p1;
7847 qp_implies[qp_implieslen].p2 = p2;
7848 qp_implies[qp_implieslen].path = md.path;
7849 qp_implies[qp_implieslen++].p2_branched = 0;
7850
7851 /* Add in the implied transitive relations; for everything that p2 implies,
7852 make p1 imply that, too; for everything that implies p1, make it imply p2
197865e8 7853 as well. */
542d6675 7854 for (i = 0; i < qp_implieslen; i++)
800eeca4
JW		 7855 {
7856 if (qp_implies[i].p1 == p2)
542d6675 7857 add_qp_imply (p1, qp_implies[i].p2);
800eeca4 7858 if (qp_implies[i].p2 == p1)
542d6675 7859 add_qp_imply (qp_implies[i].p1, p2);
800eeca4
JW		 7860 }
7861 /* Add in mutex relations implied by this implies relation; for each mutex
197865e8
KH		 7862 relation containing p2, duplicate it and replace p2 with p1. */
7863 bit = (valueT) 1 << p1;
7864 mask = (valueT) 1 << p2;
542d6675 7865 for (i = 0; i < qp_mutexeslen; i++)
800eeca4
JW		 7866 {
7867 if (qp_mutexes[i].prmask & mask)
542d6675 7868 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
800eeca4
JW		 7869 }
7870}
7871
800eeca4
JW		 7872/* Add the PRs specified in the mask to the mutex list; this means that only
7873 one of the PRs can be true at any time. PR0 should never be included in
7874 the mask. */
542d6675 7875
800eeca4
JW		 7876static void
7877add_qp_mutex (mask)
542d6675 7878 valueT mask;
800eeca4
JW		 7879{
7880 if (mask & 0x1)
7881 abort ();
7882
7883 if (qp_mutexeslen == qp_mutexestotlen)
7884 {
7885 qp_mutexestotlen += 20;
7886 qp_mutexes = (struct qpmutex *)
542d6675
KH		 7887 xrealloc ((void *) qp_mutexes,
7888 qp_mutexestotlen * sizeof (struct qpmutex));
800eeca4
JW		 7889 }
7890 if (md.debug_dv)
7891 {
7892 fprintf (stderr, " Registering mutex on");
7893 print_prmask (mask);
7894 fprintf (stderr, "\n");
7895 }
7896 qp_mutexes[qp_mutexeslen].path = md.path;
7897 qp_mutexes[qp_mutexeslen++].prmask = mask;
7898}
7899
7900static void
7901clear_register_values ()
7902{
7903 int i;
7904 if (md.debug_dv)
7905 fprintf (stderr, " Clearing register values\n");
542d6675 7906 for (i = 1; i < NELEMS (gr_values); i++)
800eeca4
JW		 7907 gr_values[i].known = 0;
7908}
7909
7910/* Keep track of register values/changes which affect DV tracking.
7911
7912 optimization note: should add a flag to classes of insns where otherwise we
542d6675 7913 have to examine a group of strings to identify them. */
800eeca4 7914
800eeca4
JW		 7915static void
7916note_register_values (idesc)
542d6675 7917 struct ia64_opcode *idesc;
800eeca4
JW		 7918{
7919 valueT qp_changemask = 0;
7920 int i;
7921
542d6675
KH		 7922 /* Invalidate values for registers being written to. */
7923 for (i = 0; i < idesc->num_outputs; i++)
800eeca4 7924 {
197865e8 7925 if (idesc->operands[i] == IA64_OPND_R1
542d6675
KH		 7926 || idesc->operands[i] == IA64_OPND_R2
7927 || idesc->operands[i] == IA64_OPND_R3)
7928 {
7929 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7930 if (regno > 0 && regno < NELEMS (gr_values))
7931 gr_values[regno].known = 0;
7932 }
50b81f19
JW		 7933 else if (idesc->operands[i] == IA64_OPND_R3_2)
7934 {
7935 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7936 if (regno > 0 && regno < 4)
7937 gr_values[regno].known = 0;
7938 }
197865e8 7939 else if (idesc->operands[i] == IA64_OPND_P1
542d6675
KH		 7940 || idesc->operands[i] == IA64_OPND_P2)
7941 {
7942 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7943 qp_changemask |= (valueT) 1 << regno;
7944 }
800eeca4 7945 else if (idesc->operands[i] == IA64_OPND_PR)
542d6675
KH		 7946 {
7947 if (idesc->operands[2] & (valueT) 0x10000)
7948 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
7949 else
7950 qp_changemask = idesc->operands[2];
7951 break;
7952 }
800eeca4 7953 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
542d6675
KH		 7954 {
7955 if (idesc->operands[1] & ((valueT) 1 << 43))
7956 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
7957 else
7958 qp_changemask = idesc->operands[1];
7959 qp_changemask &= ~(valueT) 0xFFFF;
7960 break;
7961 }
7962 }
7963
7964 /* Always clear qp branch flags on any PR change. */
7965 /* FIXME there may be exceptions for certain compares. */
800eeca4
JW		 7966 clear_qp_branch_flag (qp_changemask);
7967
542d6675 7968 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
800eeca4
JW		 7969 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
7970 {
197865e8 7971 qp_changemask |= ~(valueT) 0xFFFF;
800eeca4 7972 if (strcmp (idesc->name, "clrrrb.pr") != 0)
542d6675
KH		 7973 {
7974 for (i = 32; i < 32 + md.rot.num_regs; i++)
7975 gr_values[i].known = 0;
7976 }
800eeca4
JW		 7977 clear_qp_mutex (qp_changemask);
7978 clear_qp_implies (qp_changemask, qp_changemask);
7979 }
542d6675
KH		 7980 /* After a call, all register values are undefined, except those marked
7981 as "safe". */
800eeca4 7982 else if (strncmp (idesc->name, "br.call", 6) == 0
542d6675 7983 || strncmp (idesc->name, "brl.call", 7) == 0)
800eeca4 7984 {
56d27c17 7985 /* FIXME keep GR values which are marked as "safe_across_calls" */
800eeca4
JW		 7986 clear_register_values ();
7987 clear_qp_mutex (~qp_safe_across_calls);
7988 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
7989 clear_qp_branch_flag (~qp_safe_across_calls);
7990 }
e9718fe1 7991 else if (is_interruption_or_rfi (idesc)
542d6675 7992 || is_taken_branch (idesc))
e9718fe1
TW		 7993 {
7994 clear_register_values ();
197865e8
KH		 7995 clear_qp_mutex (~(valueT) 0);
7996 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
e9718fe1 7997 }
542d6675 7998 /* Look for mutex and implies relations. */
197865e8 7999 else if ((idesc->operands[0] == IA64_OPND_P1
542d6675
KH		 8000 || idesc->operands[0] == IA64_OPND_P2)
8001 && (idesc->operands[1] == IA64_OPND_P1
8002 || idesc->operands[1] == IA64_OPND_P2))
800eeca4
JW		 8003 {
8004 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
197865e8
KH		 8005 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8006 valueT p1mask = (valueT) 1 << p1;
8007 valueT p2mask = (valueT) 1 << p2;
800eeca4 8008
542d6675 8009 /* If one of the PRs is PR0, we can't really do anything. */
800eeca4 8010 if (p1 == 0 || p2 == 0)
542d6675
KH		 8011 {
8012 if (md.debug_dv)
8013 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8014 }
800eeca4 8015 /* In general, clear mutexes and implies which include P1 or P2,
542d6675 8016 with the following exceptions. */
800eeca4 8017 else if (strstr (idesc->name, ".or.andcm") != NULL)
542d6675
KH		 8018 {
8019 add_qp_mutex (p1mask | p2mask);
8020 clear_qp_implies (p2mask, p1mask);
8021 }
800eeca4 8022 else if (strstr (idesc->name, ".and.orcm") != NULL)
542d6675
KH		 8023 {
8024 add_qp_mutex (p1mask | p2mask);
8025 clear_qp_implies (p1mask, p2mask);
8026 }
800eeca4 8027 else if (strstr (idesc->name, ".and") != NULL)
542d6675
KH		 8028 {
8029 clear_qp_implies (0, p1mask | p2mask);
8030 }
800eeca4 8031 else if (strstr (idesc->name, ".or") != NULL)
542d6675
KH		 8032 {
8033 clear_qp_mutex (p1mask | p2mask);
8034 clear_qp_implies (p1mask | p2mask, 0);
8035 }
800eeca4 8036 else
542d6675
KH		 8037 {
8038 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
8039 if (strstr (idesc->name, ".unc") != NULL)
8040 {
8041 add_qp_mutex (p1mask | p2mask);
8042 if (CURR_SLOT.qp_regno != 0)
8043 {
8044 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8045 CURR_SLOT.qp_regno);
8046 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8047 CURR_SLOT.qp_regno);
8048 }
8049 }
8050 else if (CURR_SLOT.qp_regno == 0)
8051 {
8052 add_qp_mutex (p1mask | p2mask);
8053 }
8054 else
8055 {
8056 clear_qp_mutex (p1mask | p2mask);
8057 }
8058 }
8059 }
8060 /* Look for mov imm insns into GRs. */
800eeca4 8061 else if (idesc->operands[0] == IA64_OPND_R1
542d6675
KH		 8062 && (idesc->operands[1] == IA64_OPND_IMM22
8063 || idesc->operands[1] == IA64_OPND_IMMU64)
8064 && (strcmp (idesc->name, "mov") == 0
8065 || strcmp (idesc->name, "movl") == 0))
800eeca4
JW		 8066 {
8067 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
542d6675
KH		 8068 if (regno > 0 && regno < NELEMS (gr_values))
8069 {
8070 gr_values[regno].known = 1;
8071 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
8072 gr_values[regno].path = md.path;
8073 if (md.debug_dv)
8074 fprintf (stderr, " Know gr%d = 0x%llx\n",
8075 regno, gr_values[regno].value);
8076 }
800eeca4 8077 }
197865e8 8078 else
800eeca4
JW		 8079 {
8080 clear_qp_mutex (qp_changemask);
8081 clear_qp_implies (qp_changemask, qp_changemask);
8082 }
8083}
8084
542d6675
KH		 8085/* Return whether the given predicate registers are currently mutex. */
8086
800eeca4
JW		 8087static int
8088qp_mutex (p1, p2, path)
542d6675
KH		 8089 int p1;
8090 int p2;
8091 int path;
800eeca4
JW		 8092{
8093 int i;
8094 valueT mask;
8095
8096 if (p1 != p2)
8097 {
542d6675
KH		 8098 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
8099 for (i = 0; i < qp_mutexeslen; i++)
8100 {
8101 if (qp_mutexes[i].path >= path
8102 && (qp_mutexes[i].prmask & mask) == mask)
8103 return 1;
8104 }
800eeca4
JW		 8105 }
8106 return 0;
8107}
8108
8109/* Return whether the given resource is in the given insn's list of chks
8110 Return 1 if the conflict is absolutely determined, 2 if it's a potential
542d6675
KH		 8111 conflict. */
8112
800eeca4
JW		 8113static int
8114resources_match (rs, idesc, note, qp_regno, path)
542d6675
KH		 8115 struct rsrc *rs;
8116 struct ia64_opcode *idesc;
8117 int note;
8118 int qp_regno;
8119 int path;
800eeca4
JW		 8120{
8121 struct rsrc specs[MAX_SPECS];
8122 int count;
8123
8124 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8125 we don't need to check. One exception is note 11, which indicates that
8126 target predicates are written regardless of PR[qp]. */
197865e8 8127 if (qp_mutex (rs->qp_regno, qp_regno, path)
800eeca4
JW		 8128 && note != 11)
8129 return 0;
8130
8131 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
8132 while (count-- > 0)
8133 {
8134 /* UNAT checking is a bit more specific than other resources */
8135 if (rs->dependency->specifier == IA64_RS_AR_UNAT
542d6675
KH		 8136 && specs[count].mem_offset.hint
8137 && rs->mem_offset.hint)
8138 {
8139 if (rs->mem_offset.base == specs[count].mem_offset.base)
8140 {
8141 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
8142 ((specs[count].mem_offset.offset >> 3) & 0x3F))
8143 return 1;
8144 else
8145 continue;
8146 }
8147 }
800eeca4 8148
7484b8e6 8149 /* Skip apparent PR write conflicts where both writes are an AND or both
4a4f25cf 8150 writes are an OR. */
7484b8e6 8151 if (rs->dependency->specifier == IA64_RS_PR
afa680f8 8152 || rs->dependency->specifier == IA64_RS_PRr
7484b8e6
TW		 8153 || rs->dependency->specifier == IA64_RS_PR63)
8154 {
8155 if (specs[count].cmp_type != CMP_NONE
8156 && specs[count].cmp_type == rs->cmp_type)
8157 {
8158 if (md.debug_dv)
8159 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
8160 dv_mode[rs->dependency->mode],
afa680f8 8161 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6
TW		 8162 specs[count].index : 63);
8163 continue;
8164 }
8165 if (md.debug_dv)
4a4f25cf 8166 fprintf (stderr,
7484b8e6
TW		 8167 " %s on parallel compare conflict %s vs %s on PR%d\n",
8168 dv_mode[rs->dependency->mode],
4a4f25cf 8169 dv_cmp_type[rs->cmp_type],
7484b8e6 8170 dv_cmp_type[specs[count].cmp_type],
afa680f8 8171 rs->dependency->specifier != IA64_RS_PR63 ?
7484b8e6 8172 specs[count].index : 63);
4a4f25cf 8173
7484b8e6
TW		 8174 }
8175
800eeca4 8176 /* If either resource is not specific, conservatively assume a conflict
197865e8 8177 */
800eeca4 8178 if (!specs[count].specific || !rs->specific)
542d6675 8179 return 2;
800eeca4 8180 else if (specs[count].index == rs->index)
542d6675 8181 return 1;
800eeca4
JW		 8182 }
8183#if 0
8184 if (md.debug_dv)
8185 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
8186#endif
8187
8188 return 0;
8189}
8190
8191/* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8192 insert a stop to create the break. Update all resource dependencies
8193 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8194 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8195 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
542d6675 8196 instruction. */
800eeca4
JW		 8197
8198static void
8199insn_group_break (insert_stop, qp_regno, save_current)
542d6675
KH		 8200 int insert_stop;
8201 int qp_regno;
8202 int save_current;
800eeca4
JW		 8203{
8204 int i;
8205
8206 if (insert_stop && md.num_slots_in_use > 0)
8207 PREV_SLOT.end_of_insn_group = 1;
8208
8209 if (md.debug_dv)
8210 {
197865e8 8211 fprintf (stderr, " Insn group break%s",
542d6675 8212 (insert_stop ? " (w/stop)" : ""));
800eeca4 8213 if (qp_regno != 0)
542d6675 8214 fprintf (stderr, " effective for QP=%d", qp_regno);
800eeca4
JW		 8215 fprintf (stderr, "\n");
8216 }
8217
8218 i = 0;
8219 while (i < regdepslen)
8220 {
8221 const struct ia64_dependency *dep = regdeps[i].dependency;
8222
8223 if (qp_regno != 0
542d6675
KH		 8224 && regdeps[i].qp_regno != qp_regno)
8225 {
8226 ++i;
8227 continue;
8228 }
800eeca4
JW		 8229
8230 if (save_current
542d6675
KH		 8231 && CURR_SLOT.src_file == regdeps[i].file
8232 && CURR_SLOT.src_line == regdeps[i].line)
8233 {
8234 ++i;
8235 continue;
8236 }
800eeca4
JW		 8237
8238 /* clear dependencies which are automatically cleared by a stop, or
542d6675 8239 those that have reached the appropriate state of insn serialization */
800eeca4 8240 if (dep->semantics == IA64_DVS_IMPLIED
542d6675
KH		 8241 || dep->semantics == IA64_DVS_IMPLIEDF
8242 || regdeps[i].insn_srlz == STATE_SRLZ)
8243 {
8244 print_dependency ("Removing", i);
8245 regdeps[i] = regdeps[--regdepslen];
8246 }
800eeca4 8247 else
542d6675
KH		 8248 {
8249 if (dep->semantics == IA64_DVS_DATA
8250 || dep->semantics == IA64_DVS_INSTR
800eeca4 8251 || dep->semantics == IA64_DVS_SPECIFIC)
542d6675
KH		 8252 {
8253 if (regdeps[i].insn_srlz == STATE_NONE)
8254 regdeps[i].insn_srlz = STATE_STOP;
8255 if (regdeps[i].data_srlz == STATE_NONE)
8256 regdeps[i].data_srlz = STATE_STOP;
8257 }
8258 ++i;
8259 }
800eeca4
JW		 8260 }
8261}
8262
542d6675
KH		 8263/* Add the given resource usage spec to the list of active dependencies. */
8264
197865e8 8265static void
800eeca4 8266mark_resource (idesc, dep, spec, depind, path)
542d6675
KH		 8267 struct ia64_opcode *idesc;
8268 const struct ia64_dependency *dep;
8269 struct rsrc *spec;
8270 int depind;
8271 int path;
800eeca4
JW		 8272{
8273 if (regdepslen == regdepstotlen)
8274 {
8275 regdepstotlen += 20;
8276 regdeps = (struct rsrc *)
542d6675
KH		 8277 xrealloc ((void *) regdeps,
8278 regdepstotlen * sizeof(struct rsrc));
800eeca4
JW		 8279 }
8280
8281 regdeps[regdepslen] = *spec;
8282 regdeps[regdepslen].depind = depind;
8283 regdeps[regdepslen].path = path;
8284 regdeps[regdepslen].file = CURR_SLOT.src_file;
8285 regdeps[regdepslen].line = CURR_SLOT.src_line;
8286
8287 print_dependency ("Adding", regdepslen);
8288
8289 ++regdepslen;
8290}
8291
8292static void
8293print_dependency (action, depind)
542d6675
KH		 8294 const char *action;
8295 int depind;
800eeca4
JW		 8296{
8297 if (md.debug_dv)
8298 {
197865e8 8299 fprintf (stderr, " %s %s '%s'",
542d6675
KH		 8300 action, dv_mode[(regdeps[depind].dependency)->mode],
8301 (regdeps[depind].dependency)->name);
800eeca4 8302 if (regdeps[depind].specific && regdeps[depind].index != 0)
542d6675 8303 fprintf (stderr, " (%d)", regdeps[depind].index);
800eeca4 8304 if (regdeps[depind].mem_offset.hint)
542d6675
KH		 8305 fprintf (stderr, " 0x%llx+0x%llx",
8306 regdeps[depind].mem_offset.base,
8307 regdeps[depind].mem_offset.offset);
800eeca4
JW		 8308 fprintf (stderr, "\n");
8309 }
8310}
8311
8312static void
8313instruction_serialization ()
8314{
8315 int i;
8316 if (md.debug_dv)
8317 fprintf (stderr, " Instruction serialization\n");
542d6675 8318 for (i = 0; i < regdepslen; i++)
800eeca4
JW		 8319 if (regdeps[i].insn_srlz == STATE_STOP)
8320 regdeps[i].insn_srlz = STATE_SRLZ;
8321}
8322
8323static void
8324data_serialization ()
8325{
8326 int i = 0;
8327 if (md.debug_dv)
8328 fprintf (stderr, " Data serialization\n");
8329 while (i < regdepslen)
8330 {
8331 if (regdeps[i].data_srlz == STATE_STOP
542d6675
KH		 8332 /* Note: as of 991210, all "other" dependencies are cleared by a
8333 data serialization. This might change with new tables */
8334 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8335 {
8336 print_dependency ("Removing", i);
8337 regdeps[i] = regdeps[--regdepslen];
8338 }
800eeca4 8339 else
542d6675 8340 ++i;
800eeca4
JW		 8341 }
8342}
8343
542d6675
KH		 8344/* Insert stops and serializations as needed to avoid DVs. */
8345
800eeca4
JW		 8346static void
8347remove_marked_resource (rs)
542d6675 8348 struct rsrc *rs;
800eeca4
JW		 8349{
8350 switch (rs->dependency->semantics)
8351 {
8352 case IA64_DVS_SPECIFIC:
8353 if (md.debug_dv)
8354 fprintf (stderr, "Implementation-specific, assume worst case...\n");
197865e8 8355 /* ...fall through... */
800eeca4
JW		 8356 case IA64_DVS_INSTR:
8357 if (md.debug_dv)
542d6675 8358 fprintf (stderr, "Inserting instr serialization\n");
800eeca4 8359 if (rs->insn_srlz < STATE_STOP)
542d6675 8360 insn_group_break (1, 0, 0);
800eeca4 8361 if (rs->insn_srlz < STATE_SRLZ)
542d6675
KH		 8362 {
8363 int oldqp = CURR_SLOT.qp_regno;
8364 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8365 /* Manually jam a srlz.i insn into the stream */
8366 CURR_SLOT.qp_regno = 0;
8367 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8368 instruction_serialization ();
8369 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8370 if (++md.num_slots_in_use >= NUM_SLOTS)
8371 emit_one_bundle ();
8372 CURR_SLOT.qp_regno = oldqp;
8373 CURR_SLOT.idesc = oldidesc;
8374 }
800eeca4
JW		 8375 insn_group_break (1, 0, 0);
8376 break;
8377 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
542d6675
KH		 8378 "other" types of DV are eliminated
8379 by a data serialization */
800eeca4
JW		 8380 case IA64_DVS_DATA:
8381 if (md.debug_dv)
542d6675 8382 fprintf (stderr, "Inserting data serialization\n");
800eeca4 8383 if (rs->data_srlz < STATE_STOP)
542d6675 8384 insn_group_break (1, 0, 0);
800eeca4 8385 {
542d6675
KH		 8386 int oldqp = CURR_SLOT.qp_regno;
8387 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8388 /* Manually jam a srlz.d insn into the stream */
8389 CURR_SLOT.qp_regno = 0;
8390 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8391 data_serialization ();
8392 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8393 if (++md.num_slots_in_use >= NUM_SLOTS)
8394 emit_one_bundle ();
8395 CURR_SLOT.qp_regno = oldqp;
8396 CURR_SLOT.idesc = oldidesc;
800eeca4
JW		 8397 }
8398 break;
8399 case IA64_DVS_IMPLIED:
8400 case IA64_DVS_IMPLIEDF:
8401 if (md.debug_dv)
542d6675 8402 fprintf (stderr, "Inserting stop\n");
800eeca4
JW		 8403 insn_group_break (1, 0, 0);
8404 break;
8405 default:
8406 break;
8407 }
8408}
8409
8410/* Check the resources used by the given opcode against the current dependency
197865e8 8411 list.
800eeca4
JW		 8412
8413 The check is run once for each execution path encountered. In this case,
8414 a unique execution path is the sequence of instructions following a code
8415 entry point, e.g. the following has three execution paths, one starting
8416 at L0, one at L1, and one at L2.
197865e8 8417
800eeca4
JW		 8418 L0: nop
8419 L1: add
8420 L2: add
197865e8 8421 br.ret
800eeca4 8422*/
542d6675 8423
800eeca4
JW		 8424static void
8425check_dependencies (idesc)
542d6675 8426 struct ia64_opcode *idesc;
800eeca4
JW		 8427{
8428 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8429 int path;
8430 int i;
8431
8432 /* Note that the number of marked resources may change within the
197865e8 8433 loop if in auto mode. */
800eeca4
JW		 8434 i = 0;
8435 while (i < regdepslen)
8436 {
8437 struct rsrc *rs = &regdeps[i];
8438 const struct ia64_dependency *dep = rs->dependency;
8439 int chkind;
8440 int note;
8441 int start_over = 0;
8442
8443 if (dep->semantics == IA64_DVS_NONE
542d6675
KH		 8444 || (chkind = depends_on (rs->depind, idesc)) == -1)
8445 {
8446 ++i;
8447 continue;
8448 }
8449
8450 note = NOTE (opdeps->chks[chkind]);
8451
8452 /* Check this resource against each execution path seen thus far. */
8453 for (path = 0; path <= md.path; path++)
8454 {
8455 int matchtype;
8456
8457 /* If the dependency wasn't on the path being checked, ignore it. */
8458 if (rs->path < path)
8459 continue;
8460
8461 /* If the QP for this insn implies a QP which has branched, don't
8462 bother checking. Ed. NOTE: I don't think this check is terribly
8463 useful; what's the point of generating code which will only be
8464 reached if its QP is zero?
8465 This code was specifically inserted to handle the following code,
8466 based on notes from Intel's DV checking code, where p1 implies p2.
8467
8468 mov r4 = 2
8469 (p2) br.cond L
8470 (p1) mov r4 = 7
8471 */
8472 if (CURR_SLOT.qp_regno != 0)
8473 {
8474 int skip = 0;
8475 int implies;
8476 for (implies = 0; implies < qp_implieslen; implies++)
8477 {
8478 if (qp_implies[implies].path >= path
8479 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8480 && qp_implies[implies].p2_branched)
8481 {
8482 skip = 1;
8483 break;
8484 }
8485 }
8486 if (skip)
8487 continue;
8488 }
8489
8490 if ((matchtype = resources_match (rs, idesc, note,
8491 CURR_SLOT.qp_regno, path)) != 0)
8492 {
8493 char msg[1024];
8494 char pathmsg[256] = "";
8495 char indexmsg[256] = "";
8496 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8497
8498 if (path != 0)
8499 sprintf (pathmsg, " when entry is at label '%s'",
8500 md.entry_labels[path - 1]);
8501 if (rs->specific && rs->index != 0)
8502 sprintf (indexmsg, ", specific resource number is %d",
8503 rs->index);
8504 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8505 idesc->name,
8506 (certain ? "violates" : "may violate"),
8507 dv_mode[dep->mode], dep->name,
8508 dv_sem[dep->semantics],
8509 pathmsg, indexmsg);
8510
8511 if (md.explicit_mode)
8512 {
8513 as_warn ("%s", msg);
8514 if (path < md.path)
8515 as_warn (_("Only the first path encountering the conflict "
8516 "is reported"));
8517 as_warn_where (rs->file, rs->line,
8518 _("This is the location of the "
8519 "conflicting usage"));
8520 /* Don't bother checking other paths, to avoid duplicating
8521 the same warning */
8522 break;
8523 }
8524 else
8525 {
8526 if (md.debug_dv)
8527 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
8528
8529 remove_marked_resource (rs);
8530
8531 /* since the set of dependencies has changed, start over */
8532 /* FIXME -- since we're removing dvs as we go, we
8533 probably don't really need to start over... */
8534 start_over = 1;
8535 break;
8536 }
8537 }
8538 }
800eeca4 8539 if (start_over)
542d6675 8540 i = 0;
800eeca4 8541 else
542d6675 8542 ++i;
800eeca4
JW		 8543 }
8544}
8545
542d6675
KH		 8546/* Register new dependencies based on the given opcode. */
8547
800eeca4
JW		 8548static void
8549mark_resources (idesc)
542d6675 8550 struct ia64_opcode *idesc;
800eeca4
JW		 8551{
8552 int i;
8553 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8554 int add_only_qp_reads = 0;
8555
8556 /* A conditional branch only uses its resources if it is taken; if it is
8557 taken, we stop following that path. The other branch types effectively
8558 *always* write their resources. If it's not taken, register only QP
197865e8 8559 reads. */
800eeca4
JW		 8560 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8561 {
8562 add_only_qp_reads = 1;
8563 }
8564
8565 if (md.debug_dv)
8566 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8567
542d6675 8568 for (i = 0; i < opdeps->nregs; i++)
800eeca4
JW		 8569 {
8570 const struct ia64_dependency *dep;
8571 struct rsrc specs[MAX_SPECS];
8572 int note;
8573 int path;
8574 int count;
197865e8 8575
800eeca4 8576 dep = ia64_find_dependency (opdeps->regs[i]);
542d6675 8577 note = NOTE (opdeps->regs[i]);
800eeca4
JW		 8578
8579 if (add_only_qp_reads
542d6675
KH		 8580 && !(dep->mode == IA64_DV_WAR
8581 && (dep->specifier == IA64_RS_PR
139368c9 8582 || dep->specifier == IA64_RS_PRr
542d6675
KH		 8583 || dep->specifier == IA64_RS_PR63)))
8584 continue;
800eeca4
JW		 8585
8586 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8587
8588#if 0
8589 if (md.debug_dv && !count)
542d6675
KH		 8590 fprintf (stderr, " No %s %s usage found (path %d)\n",
8591 dv_mode[dep->mode], dep->name, md.path);
800eeca4 8592#endif
197865e8 8593
800eeca4 8594 while (count-- > 0)
542d6675
KH		 8595 {
8596 mark_resource (idesc, dep, &specs[count],
8597 DEP (opdeps->regs[i]), md.path);
8598 }
800eeca4
JW		 8599
8600 /* The execution path may affect register values, which may in turn
542d6675 8601 affect which indirect-access resources are accessed. */
800eeca4 8602 switch (dep->specifier)
542d6675
KH		 8603 {
8604 default:
8605 break;
8606 case IA64_RS_CPUID:
8607 case IA64_RS_DBR:
8608 case IA64_RS_IBR:
800eeca4 8609 case IA64_RS_MSR:
542d6675
KH		 8610 case IA64_RS_PKR:
8611 case IA64_RS_PMC:
8612 case IA64_RS_PMD:
8613 case IA64_RS_RR:
8614 for (path = 0; path < md.path; path++)
8615 {
8616 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8617 while (count-- > 0)
8618 mark_resource (idesc, dep, &specs[count],
8619 DEP (opdeps->regs[i]), path);
8620 }
8621 break;
8622 }
8623 }
8624}
8625
8626/* Remove dependencies when they no longer apply. */
8627
800eeca4
JW		 8628static void
8629update_dependencies (idesc)
542d6675 8630 struct ia64_opcode *idesc;
800eeca4
JW		 8631{
8632 int i;
8633
8634 if (strcmp (idesc->name, "srlz.i") == 0)
8635 {
8636 instruction_serialization ();
8637 }
8638 else if (strcmp (idesc->name, "srlz.d") == 0)
8639 {
8640 data_serialization ();
8641 }
8642 else if (is_interruption_or_rfi (idesc)
542d6675 8643 || is_taken_branch (idesc))
800eeca4 8644 {
542d6675
KH		 8645 /* Although technically the taken branch doesn't clear dependencies
8646 which require a srlz.[id], we don't follow the branch; the next
8647 instruction is assumed to start with a clean slate. */
800eeca4 8648 regdepslen = 0;
800eeca4
JW		 8649 md.path = 0;
8650 }
8651 else if (is_conditional_branch (idesc)
542d6675 8652 && CURR_SLOT.qp_regno != 0)
800eeca4
JW		 8653 {
8654 int is_call = strstr (idesc->name, ".call") != NULL;
8655
542d6675
KH		 8656 for (i = 0; i < qp_implieslen; i++)
8657 {
8658 /* If the conditional branch's predicate is implied by the predicate
8659 in an existing dependency, remove that dependency. */
8660 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8661 {
8662 int depind = 0;
8663 /* Note that this implied predicate takes a branch so that if
8664 a later insn generates a DV but its predicate implies this
8665 one, we can avoid the false DV warning. */
8666 qp_implies[i].p2_branched = 1;
8667 while (depind < regdepslen)
8668 {
8669 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8670 {
8671 print_dependency ("Removing", depind);
8672 regdeps[depind] = regdeps[--regdepslen];
8673 }
8674 else
8675 ++depind;
8676 }
8677 }
8678 }
800eeca4 8679 /* Any marked resources which have this same predicate should be
542d6675
KH		 8680 cleared, provided that the QP hasn't been modified between the
8681 marking instruction and the branch. */
800eeca4 8682 if (is_call)
542d6675
KH		 8683 {
8684 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8685 }
800eeca4 8686 else
542d6675
KH		 8687 {
8688 i = 0;
8689 while (i < regdepslen)
8690 {
8691 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8692 && regdeps[i].link_to_qp_branch
8693 && (regdeps[i].file != CURR_SLOT.src_file
8694 || regdeps[i].line != CURR_SLOT.src_line))
8695 {
8696 /* Treat like a taken branch */
8697 print_dependency ("Removing", i);
8698 regdeps[i] = regdeps[--regdepslen];
8699 }
8700 else
8701 ++i;
8702 }
8703 }
800eeca4
JW		 8704 }
8705}
8706
8707/* Examine the current instruction for dependency violations. */
542d6675 8708
800eeca4
JW		 8709static int
8710check_dv (idesc)
542d6675 8711 struct ia64_opcode *idesc;
800eeca4
JW		 8712{
8713 if (md.debug_dv)
8714 {
197865e8 8715 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
542d6675
KH		 8716 idesc->name, CURR_SLOT.src_line,
8717 idesc->dependencies->nchks,
8718 idesc->dependencies->nregs);
800eeca4
JW		 8719 }
8720
197865e8 8721 /* Look through the list of currently marked resources; if the current
800eeca4 8722 instruction has the dependency in its chks list which uses that resource,
542d6675 8723 check against the specific resources used. */
800eeca4
JW		 8724 check_dependencies (idesc);
8725
542d6675
KH		 8726 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8727 then add them to the list of marked resources. */
800eeca4
JW		 8728 mark_resources (idesc);
8729
8730 /* There are several types of dependency semantics, and each has its own
197865e8
KH		 8731 requirements for being cleared
8732
800eeca4
JW		 8733 Instruction serialization (insns separated by interruption, rfi, or
8734 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8735
8736 Data serialization (instruction serialization, or writer + srlz.d +
8737 reader, where writer and srlz.d are in separate groups) clears
8738 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8739 always be the case).
8740
8741 Instruction group break (groups separated by stop, taken branch,
8742 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8743 */
8744 update_dependencies (idesc);
8745
8746 /* Sometimes, knowing a register value allows us to avoid giving a false DV
197865e8 8747 warning. Keep track of as many as possible that are useful. */
800eeca4
JW		 8748 note_register_values (idesc);
8749
197865e8 8750 /* We don't need or want this anymore. */
800eeca4
JW		 8751 md.mem_offset.hint = 0;
8752
8753 return 0;
8754}
8755
8756/* Translate one line of assembly. Pseudo ops and labels do not show
8757 here. */
8758void
8759md_assemble (str)
8760 char *str;
8761{
8762 char *saved_input_line_pointer, *mnemonic;
8763 const struct pseudo_opcode *pdesc;
8764 struct ia64_opcode *idesc;
8765 unsigned char qp_regno;
8766 unsigned int flags;
8767 int ch;
8768
8769 saved_input_line_pointer = input_line_pointer;
8770 input_line_pointer = str;
8771
542d6675 8772 /* extract the opcode (mnemonic): */
800eeca4
JW		 8773
8774 mnemonic = input_line_pointer;
8775 ch = get_symbol_end ();
8776 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
8777 if (pdesc)
8778 {
8779 *input_line_pointer = ch;
8780 (*pdesc->handler) (pdesc->arg);
8781 goto done;
8782 }
8783
542d6675 8784 /* Find the instruction descriptor matching the arguments. */
800eeca4
JW		 8785
8786 idesc = ia64_find_opcode (mnemonic);
8787 *input_line_pointer = ch;
8788 if (!idesc)
8789 {
8790 as_bad ("Unknown opcode `%s'", mnemonic);
8791 goto done;
8792 }
8793
8794 idesc = parse_operands (idesc);
8795 if (!idesc)
8796 goto done;
8797
542d6675 8798 /* Handle the dynamic ops we can handle now: */
800eeca4
JW		 8799 if (idesc->type == IA64_TYPE_DYN)
8800 {
8801 if (strcmp (idesc->name, "add") == 0)
8802 {
8803 if (CURR_SLOT.opnd[2].X_op == O_register
8804 && CURR_SLOT.opnd[2].X_add_number < 4)
8805 mnemonic = "addl";
8806 else
8807 mnemonic = "adds";
3d56ab85 8808 ia64_free_opcode (idesc);
800eeca4
JW		 8809 idesc = ia64_find_opcode (mnemonic);
8810#if 0
8811 know (!idesc->next);
8812#endif
8813 }
8814 else if (strcmp (idesc->name, "mov") == 0)
8815 {
8816 enum ia64_opnd opnd1, opnd2;
8817 int rop;
8818
8819 opnd1 = idesc->operands[0];
8820 opnd2 = idesc->operands[1];
8821 if (opnd1 == IA64_OPND_AR3)
8822 rop = 0;
8823 else if (opnd2 == IA64_OPND_AR3)
8824 rop = 1;
8825 else
8826 abort ();
8827 if (CURR_SLOT.opnd[rop].X_op == O_register
8828 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
8829 mnemonic = "mov.i";
8830 else
8831 mnemonic = "mov.m";
3d56ab85 8832 ia64_free_opcode (idesc);
800eeca4
JW		 8833 idesc = ia64_find_opcode (mnemonic);
8834 while (idesc != NULL
8835 && (idesc->operands[0] != opnd1
8836 || idesc->operands[1] != opnd2))
8837 idesc = get_next_opcode (idesc);
8838 }
8839 }
8840
8841 qp_regno = 0;
8842 if (md.qp.X_op == O_register)
f1bcba5b
JW		 8843 {
8844 qp_regno = md.qp.X_add_number - REG_P;
8845 md.qp.X_op = O_absent;
8846 }
800eeca4
JW		 8847
8848 flags = idesc->flags;
8849
8850 if ((flags & IA64_OPCODE_FIRST) != 0)
8851 insn_group_break (1, 0, 0);
8852
8853 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
8854 {
8855 as_bad ("`%s' cannot be predicated", idesc->name);
8856 goto done;
8857 }
8858
542d6675 8859 /* Build the instruction. */
800eeca4
JW		 8860 CURR_SLOT.qp_regno = qp_regno;
8861 CURR_SLOT.idesc = idesc;
8862 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
8863 if (debug_type == DEBUG_DWARF2)
8864 dwarf2_where (&CURR_SLOT.debug_line);
8865
8866 /* Add unwind entry, if there is one. */
e0c9811a 8867 if (unwind.current_entry)
800eeca4 8868 {
e0c9811a
JW		 8869 CURR_SLOT.unwind_record = unwind.current_entry;
8870 unwind.current_entry = NULL;
800eeca4
JW		 8871 }
8872
542d6675 8873 /* Check for dependency violations. */
800eeca4 8874 if (md.detect_dv)
542d6675 8875 check_dv (idesc);
800eeca4
JW		 8876
8877 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8878 if (++md.num_slots_in_use >= NUM_SLOTS)
8879 emit_one_bundle ();
8880
8881 if ((flags & IA64_OPCODE_LAST) != 0)
8882 insn_group_break (1, 0, 0);
8883
8884 md.last_text_seg = now_seg;
8885
8886 done:
8887 input_line_pointer = saved_input_line_pointer;
8888}
8889
8890/* Called when symbol NAME cannot be found in the symbol table.
8891 Should be used for dynamic valued symbols only. */
542d6675
KH		 8892
8893symbolS *
800eeca4
JW		 8894md_undefined_symbol (name)
8895 char *name;
8896{
8897 return 0;
8898}
8899
8900/* Called for any expression that can not be recognized. When the
8901 function is called, `input_line_pointer' will point to the start of
8902 the expression. */
542d6675 8903
800eeca4
JW		 8904void
8905md_operand (e)
8906 expressionS *e;
8907{
8908 enum pseudo_type pseudo_type;
e0c9811a 8909 const char *name;
800eeca4
JW		 8910 size_t len;
8911 int ch, i;
8912
8913 switch (*input_line_pointer)
8914 {
8915 case '@':
542d6675 8916 /* Find what relocation pseudo-function we're dealing with. */
800eeca4
JW		 8917 pseudo_type = 0;
8918 ch = *++input_line_pointer;
8919 for (i = 0; i < NELEMS (pseudo_func); ++i)
8920 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
8921 {
8922 len = strlen (pseudo_func[i].name);
8923 if (strncmp (pseudo_func[i].name + 1,
8924 input_line_pointer + 1, len - 1) == 0
8925 && !is_part_of_name (input_line_pointer[len]))
8926 {
8927 input_line_pointer += len;
8928 pseudo_type = pseudo_func[i].type;
8929 break;
8930 }
8931 }
8932 switch (pseudo_type)
8933 {
8934 case PSEUDO_FUNC_RELOC:
8935 SKIP_WHITESPACE ();
8936 if (*input_line_pointer != '(')
8937 {
8938 as_bad ("Expected '('");
8939 goto err;
8940 }
542d6675
KH		 8941 /* Skip '('. */
8942 ++input_line_pointer;
800eeca4
JW		 8943 expression (e);
8944 if (*input_line_pointer++ != ')')
8945 {
8946 as_bad ("Missing ')'");
8947 goto err;
8948 }
8949 if (e->X_op != O_symbol)
8950 {
8951 if (e->X_op != O_pseudo_fixup)
8952 {
8953 as_bad ("Not a symbolic expression");
8954 goto err;
8955 }
8956 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
8957 && i == FUNC_LT_RELATIVE)
8958 i = FUNC_LT_FPTR_RELATIVE;
8959 else
8960 {
8961 as_bad ("Illegal combination of relocation functions");
8962 goto err;
8963 }
8964 }
542d6675
KH		 8965 /* Make sure gas doesn't get rid of local symbols that are used
8966 in relocs. */
800eeca4
JW		 8967 e->X_op = O_pseudo_fixup;
8968 e->X_op_symbol = pseudo_func[i].u.sym;
8969 break;
8970
8971 case PSEUDO_FUNC_CONST:
8972 e->X_op = O_constant;
8973 e->X_add_number = pseudo_func[i].u.ival;
8974 break;
8975
e0c9811a
JW		 8976 case PSEUDO_FUNC_REG:
8977 e->X_op = O_register;
8978 e->X_add_number = pseudo_func[i].u.ival;
8979 break;
8980
800eeca4 8981 default:
e0c9811a
JW		 8982 name = input_line_pointer - 1;
8983 get_symbol_end ();
8984 as_bad ("Unknown pseudo function `%s'", name);
800eeca4
JW		 8985 goto err;
8986 }
8987 break;
8988
8989 case '[':
8990 ++input_line_pointer;
8991 expression (e);
8992 if (*input_line_pointer != ']')
8993 {
8994 as_bad ("Closing bracket misssing");
8995 goto err;
8996 }
8997 else
8998 {
8999 if (e->X_op != O_register)
9000 as_bad ("Register expected as index");
9001
9002 ++input_line_pointer;
9003 e->X_op = O_index;
9004 }
9005 break;
9006
9007 default:
9008 break;
9009 }
9010 return;
9011
9012 err:
9013 ignore_rest_of_line ();
9014}
9015
9016/* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9017 a section symbol plus some offset. For relocs involving @fptr(),
9018 directives we don't want such adjustments since we need to have the
9019 original symbol's name in the reloc. */
9020int
9021ia64_fix_adjustable (fix)
9022 fixS *fix;
9023{
9024 /* Prevent all adjustments to global symbols */
9025 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9026 return 0;
9027
9028 switch (fix->fx_r_type)
9029 {
9030 case BFD_RELOC_IA64_FPTR64I:
9031 case BFD_RELOC_IA64_FPTR32MSB:
9032 case BFD_RELOC_IA64_FPTR32LSB:
9033 case BFD_RELOC_IA64_FPTR64MSB:
9034 case BFD_RELOC_IA64_FPTR64LSB:
9035 case BFD_RELOC_IA64_LTOFF_FPTR22:
9036 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9037 return 0;
9038 default:
9039 break;
9040 }
9041
9042 return 1;
9043}
9044
9045int
9046ia64_force_relocation (fix)
9047 fixS *fix;
9048{
9049 switch (fix->fx_r_type)
9050 {
9051 case BFD_RELOC_IA64_FPTR64I:
9052 case BFD_RELOC_IA64_FPTR32MSB:
9053 case BFD_RELOC_IA64_FPTR32LSB:
9054 case BFD_RELOC_IA64_FPTR64MSB:
9055 case BFD_RELOC_IA64_FPTR64LSB:
9056
9057 case BFD_RELOC_IA64_LTOFF22:
9058 case BFD_RELOC_IA64_LTOFF64I:
9059 case BFD_RELOC_IA64_LTOFF_FPTR22:
9060 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9061 case BFD_RELOC_IA64_PLTOFF22:
9062 case BFD_RELOC_IA64_PLTOFF64I:
9063 case BFD_RELOC_IA64_PLTOFF64MSB:
9064 case BFD_RELOC_IA64_PLTOFF64LSB:
9065 return 1;
9066
9067 default:
9068 return 0;
9069 }
9070 return 0;
9071}
9072
9073/* Decide from what point a pc-relative relocation is relative to,
9074 relative to the pc-relative fixup. Er, relatively speaking. */
9075long
9076ia64_pcrel_from_section (fix, sec)
9077 fixS *fix;
9078 segT sec;
9079{
9080 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
197865e8 9081
800eeca4
JW		 9082 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
9083 off &= ~0xfUL;
9084
9085 return off;
9086}
9087
9088/* This is called whenever some data item (not an instruction) needs a
9089 fixup. We pick the right reloc code depending on the byteorder
9090 currently in effect. */
9091void
9092ia64_cons_fix_new (f, where, nbytes, exp)
9093 fragS *f;
9094 int where;
9095 int nbytes;
9096 expressionS *exp;
9097{
9098 bfd_reloc_code_real_type code;
9099 fixS *fix;
9100
9101 switch (nbytes)
9102 {
9103 /* There are no reloc for 8 and 16 bit quantities, but we allow
9104 them here since they will work fine as long as the expression
9105 is fully defined at the end of the pass over the source file. */
9106 case 1: code = BFD_RELOC_8; break;
9107 case 2: code = BFD_RELOC_16; break;
9108 case 4:
9109 if (target_big_endian)
9110 code = BFD_RELOC_IA64_DIR32MSB;
9111 else
9112 code = BFD_RELOC_IA64_DIR32LSB;
9113 break;
9114
9115 case 8:
9116 if (target_big_endian)
9117 code = BFD_RELOC_IA64_DIR64MSB;
9118 else
9119 code = BFD_RELOC_IA64_DIR64LSB;
9120 break;
9121
9122 default:
9123 as_bad ("Unsupported fixup size %d", nbytes);
9124 ignore_rest_of_line ();
9125 return;
9126 }
9127 if (exp->X_op == O_pseudo_fixup)
9128 {
9129 /* ??? */
9130 exp->X_op = O_symbol;
9131 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
9132 }
9133 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
9134 /* We need to store the byte order in effect in case we're going
9135 to fix an 8 or 16 bit relocation (for which there no real
9136 relocs available). See md_apply_fix(). */
9137 fix->tc_fix_data.bigendian = target_big_endian;
9138}
9139
9140/* Return the actual relocation we wish to associate with the pseudo
9141 reloc described by SYM and R_TYPE. SYM should be one of the
197865e8 9142 symbols in the pseudo_func array, or NULL. */
800eeca4
JW		 9143
9144static bfd_reloc_code_real_type
9145ia64_gen_real_reloc_type (sym, r_type)
9146 struct symbol *sym;
9147 bfd_reloc_code_real_type r_type;
9148{
9149 bfd_reloc_code_real_type new = 0;
9150
9151 if (sym == NULL)
9152 {
9153 return r_type;
9154 }
9155
9156 switch (S_GET_VALUE (sym))
9157 {
9158 case FUNC_FPTR_RELATIVE:
9159 switch (r_type)
9160 {
9161 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
9162 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
9163 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
9164 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
9165 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
9166 default: break;
9167 }
9168 break;
9169
9170 case FUNC_GP_RELATIVE:
9171 switch (r_type)
9172 {
9173 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
9174 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
9175 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
9176 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
9177 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
9178 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
9179 default: break;
9180 }
9181 break;
9182
9183 case FUNC_LT_RELATIVE:
9184 switch (r_type)
9185 {
9186 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
9187 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
9188 default: break;
9189 }
9190 break;
9191
c67e42c9
RH		 9192 case FUNC_PC_RELATIVE:
9193 switch (r_type)
9194 {
9195 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
9196 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
9197 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
9198 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
9199 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
9200 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
9201 default: break;
9202 }
9203 break;
9204
800eeca4
JW		 9205 case FUNC_PLT_RELATIVE:
9206 switch (r_type)
9207 {
9208 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
9209 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
9210 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
9211 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
9212 default: break;
9213 }
9214 break;
9215
9216 case FUNC_SEC_RELATIVE:
9217 switch (r_type)
9218 {
9219 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
9220 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
9221 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
9222 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
9223 default: break;
9224 }
9225 break;
9226
9227 case FUNC_SEG_RELATIVE:
9228 switch (r_type)
9229 {
9230 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
9231 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
9232 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
9233 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
9234 default: break;
9235 }
9236 break;
9237
9238 case FUNC_LTV_RELATIVE:
9239 switch (r_type)
9240 {
9241 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
9242 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
9243 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
9244 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
9245 default: break;
9246 }
9247 break;
9248
9249 case FUNC_LT_FPTR_RELATIVE:
9250 switch (r_type)
9251 {
9252 case BFD_RELOC_IA64_IMM22:
9253 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9254 case BFD_RELOC_IA64_IMM64:
9255 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9256 default:
9257 break;
9258 }
9259 break;
9260 default:
9261 abort ();
9262 }
9263 /* Hmmmm. Should this ever occur? */
9264 if (new)
9265 return new;
9266 else
9267 return r_type;
9268}
9269
9270/* Here is where generate the appropriate reloc for pseudo relocation
9271 functions. */
9272void
9273ia64_validate_fix (fix)
9274 fixS *fix;
9275{
9276 switch (fix->fx_r_type)
9277 {
9278 case BFD_RELOC_IA64_FPTR64I:
9279 case BFD_RELOC_IA64_FPTR32MSB:
9280 case BFD_RELOC_IA64_FPTR64LSB:
9281 case BFD_RELOC_IA64_LTOFF_FPTR22:
9282 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9283 if (fix->fx_offset != 0)
9284 as_bad_where (fix->fx_file, fix->fx_line,
9285 "No addend allowed in @fptr() relocation");
9286 break;
9287 default:
9288 break;
9289 }
9290
9291 return;
9292}
9293
9294static void
9295fix_insn (fix, odesc, value)
9296 fixS *fix;
9297 const struct ia64_operand *odesc;
9298 valueT value;
9299{
9300 bfd_vma insn[3], t0, t1, control_bits;
9301 const char *err;
9302 char *fixpos;
9303 long slot;
9304
9305 slot = fix->fx_where & 0x3;
9306 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9307
c67e42c9 9308 /* Bundles are always in little-endian byte order */
800eeca4
JW		 9309 t0 = bfd_getl64 (fixpos);
9310 t1 = bfd_getl64 (fixpos + 8);
9311 control_bits = t0 & 0x1f;
9312 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9313 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9314 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9315
c67e42c9
RH		 9316 err = NULL;
9317 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
800eeca4 9318 {
c67e42c9
RH		 9319 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9320 insn[2] |= (((value & 0x7f) << 13)
9321 | (((value >> 7) & 0x1ff) << 27)
9322 | (((value >> 16) & 0x1f) << 22)
9323 | (((value >> 21) & 0x1) << 21)
9324 | (((value >> 63) & 0x1) << 36));
800eeca4 9325 }
c67e42c9
RH		 9326 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9327 {
9328 if (value & ~0x3fffffffffffffffULL)
9329 err = "integer operand out of range";
9330 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9331 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9332 }
9333 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9334 {
9335 value >>= 4;
9336 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9337 insn[2] |= ((((value >> 59) & 0x1) << 36)
9338 | (((value >> 0) & 0xfffff) << 13));
9339 }
9340 else
9341 err = (*odesc->insert) (odesc, value, insn + slot);
9342
9343 if (err)
9344 as_bad_where (fix->fx_file, fix->fx_line, err);
800eeca4
JW		 9345
9346 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9347 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9348 md_number_to_chars (fixpos + 0, t0, 8);
9349 md_number_to_chars (fixpos + 8, t1, 8);
800eeca4
JW		 9350}
9351
9352/* Attempt to simplify or even eliminate a fixup. The return value is
9353 ignored; perhaps it was once meaningful, but now it is historical.
9354 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9355
9356 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
197865e8 9357 (if possible). */
800eeca4
JW		 9358int
9359md_apply_fix3 (fix, valuep, seg)
9360 fixS *fix;
9361 valueT *valuep;
9362 segT seg;
9363{
9364 char *fixpos;
9365 valueT value = *valuep;
9366 int adjust = 0;
9367
9368 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9369
9370 if (fix->fx_pcrel)
9371 {
9372 switch (fix->fx_r_type)
9373 {
9374 case BFD_RELOC_IA64_DIR32MSB:
9375 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9376 adjust = 1;
9377 break;
9378
9379 case BFD_RELOC_IA64_DIR32LSB:
9380 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9381 adjust = 1;
9382 break;
9383
9384 case BFD_RELOC_IA64_DIR64MSB:
9385 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9386 adjust = 1;
9387 break;
9388
9389 case BFD_RELOC_IA64_DIR64LSB:
9390 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9391 adjust = 1;
9392 break;
9393
9394 default:
9395 break;
9396 }
9397 }
9398 if (fix->fx_addsy)
9399 {
9400 switch (fix->fx_r_type)
9401 {
9402 case 0:
9403 as_bad_where (fix->fx_file, fix->fx_line,
9404 "%s must have a constant value",
9405 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9406 break;
9407
9408 default:
9409 break;
9410 }
9411
9412 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
542d6675 9413 work. There should be a better way to handle this. */
800eeca4
JW		 9414 if (adjust)
9415 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9416 }
9417 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9418 {
9419 if (fix->tc_fix_data.bigendian)
9420 number_to_chars_bigendian (fixpos, value, fix->fx_size);
9421 else
9422 number_to_chars_littleendian (fixpos, value, fix->fx_size);
9423 fix->fx_done = 1;
9424 return 1;
9425 }
9426 else
9427 {
9428 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
9429 fix->fx_done = 1;
9430 return 1;
9431 }
9432 return 1;
9433}
9434
9435/* Generate the BFD reloc to be stuck in the object file from the
9436 fixup used internally in the assembler. */
542d6675
KH		 9437
9438arelent *
800eeca4
JW		 9439tc_gen_reloc (sec, fixp)
9440 asection *sec;
9441 fixS *fixp;
9442{
9443 arelent *reloc;
9444
9445 reloc = xmalloc (sizeof (*reloc));
9446 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9447 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9448 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9449 reloc->addend = fixp->fx_offset;
9450 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9451
9452 if (!reloc->howto)
9453 {
9454 as_bad_where (fixp->fx_file, fixp->fx_line,
9455 "Cannot represent %s relocation in object file",
9456 bfd_get_reloc_code_name (fixp->fx_r_type));
9457 }
9458 return reloc;
9459}
9460
9461/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 9462 of type TYPE, and store the appropriate bytes in *LIT. The number
9463 of LITTLENUMS emitted is stored in *SIZE. An error message is
800eeca4
JW		 9464 returned, or NULL on OK. */
9465
9466#define MAX_LITTLENUMS 5
9467
542d6675 9468char *
800eeca4
JW		 9469md_atof (type, lit, size)
9470 int type;
9471 char *lit;
9472 int *size;
9473{
9474 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9475 LITTLENUM_TYPE *word;
9476 char *t;
9477 int prec;
9478
9479 switch (type)
9480 {
9481 /* IEEE floats */
9482 case 'f':
9483 case 'F':
9484 case 's':
9485 case 'S':
9486 prec = 2;
9487 break;
9488
9489 case 'd':
9490 case 'D':
9491 case 'r':
9492 case 'R':
9493 prec = 4;
9494 break;
9495
9496 case 'x':
9497 case 'X':
9498 case 'p':
9499 case 'P':
9500 prec = 5;
9501 break;
9502
9503 default:
9504 *size = 0;
9505 return "Bad call to MD_ATOF()";
9506 }
9507 t = atof_ieee (input_line_pointer, type, words);
9508 if (t)
9509 input_line_pointer = t;
9510 *size = prec * sizeof (LITTLENUM_TYPE);
9511
9512 for (word = words + prec - 1; prec--;)
9513 {
9514 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9515 lit += sizeof (LITTLENUM_TYPE);
9516 }
9517 return 0;
9518}
9519
9520/* Round up a section's size to the appropriate boundary. */
9521valueT
9522md_section_align (seg, size)
9523 segT seg;
9524 valueT size;
9525{
9526 int align = bfd_get_section_alignment (stdoutput, seg);
197865e8 9527 valueT mask = ((valueT) 1 << align) - 1;
800eeca4
JW		 9528
9529 return (size + mask) & ~mask;
9530}
9531
9532/* Handle ia64 specific semantics of the align directive. */
9533
9534int
9535ia64_md_do_align (n, fill, len, max)
9536 int n;
9537 const char *fill;
9538 int len;
9539 int max;
9540{
9541 /* Fill any pending bundle with nops. */
9542 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
9543 ia64_flush_insns ();
9544
9545 /* When we align code in a text section, emit a bundle of 3 nops instead of
9546 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9547 N is log base 2 of the requested alignment. */
9548 if (fill == NULL
9549 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
9550 && n > 4)
9551 {
9552 /* Use mfi bundle of nops with no stop bits. */
9553 static const unsigned char be_nop[]
9554 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9555 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9556 static const unsigned char le_nop[]
9557 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9558 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
197865e8 9559
800eeca4
JW		 9560 /* Make sure we are on a 16-byte boundary, in case someone has been
9561 putting data into a text section. */
9562 frag_align (4, 0, 0);
9563
9564 if (target_big_endian)
9565 frag_align_pattern (n, be_nop, 16, max);
9566 else
9567 frag_align_pattern (n, le_nop, 16, max);
9568 return 1;
9569 }
9570
9571 return 0;
9572}
GDB Binutils - Deliverables
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