Commit | Line | Data |
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252b5132 | 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
219d1afa | 2 | Copyright (C) 1993-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by the OSF and Ralph Campbell. |
4 | Written by Keith Knowles and Ralph Campbell, working independently. | |
5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus | |
6 | Support. | |
7 | ||
8 | This file is part of GAS. | |
9 | ||
10 | GAS is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
13 | any later version. |
14 | ||
15 | GAS is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
23 | 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #include "as.h" | |
26 | #include "config.h" | |
27 | #include "subsegs.h" | |
3882b010 | 28 | #include "safe-ctype.h" |
252b5132 | 29 | |
252b5132 RH |
30 | #include "opcode/mips.h" |
31 | #include "itbl-ops.h" | |
c5dd6aab | 32 | #include "dwarf2dbg.h" |
5862107c | 33 | #include "dw2gencfi.h" |
252b5132 | 34 | |
42429eac RS |
35 | /* Check assumptions made in this file. */ |
36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; | |
37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; | |
38 | ||
252b5132 RH |
39 | #ifdef DEBUG |
40 | #define DBG(x) printf x | |
41 | #else | |
42 | #define DBG(x) | |
43 | #endif | |
44 | ||
263b2574 | 45 | #define streq(a, b) (strcmp (a, b) == 0) |
46 | ||
9e12b7a2 RS |
47 | #define SKIP_SPACE_TABS(S) \ |
48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) | |
49 | ||
252b5132 | 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
17a2f251 TS |
51 | static int mips_output_flavor (void); |
52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } | |
252b5132 RH |
53 | #undef OBJ_PROCESS_STAB |
54 | #undef OUTPUT_FLAVOR | |
55 | #undef S_GET_ALIGN | |
56 | #undef S_GET_SIZE | |
57 | #undef S_SET_ALIGN | |
58 | #undef S_SET_SIZE | |
252b5132 RH |
59 | #undef obj_frob_file |
60 | #undef obj_frob_file_after_relocs | |
61 | #undef obj_frob_symbol | |
62 | #undef obj_pop_insert | |
63 | #undef obj_sec_sym_ok_for_reloc | |
64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES | |
65 | ||
66 | #include "obj-elf.h" | |
67 | /* Fix any of them that we actually care about. */ | |
68 | #undef OUTPUT_FLAVOR | |
69 | #define OUTPUT_FLAVOR mips_output_flavor() | |
252b5132 | 70 | |
252b5132 | 71 | #include "elf/mips.h" |
252b5132 RH |
72 | |
73 | #ifndef ECOFF_DEBUGGING | |
74 | #define NO_ECOFF_DEBUGGING | |
75 | #define ECOFF_DEBUGGING 0 | |
76 | #endif | |
77 | ||
ecb4347a DJ |
78 | int mips_flag_mdebug = -1; |
79 | ||
dcd410fe RO |
80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
81 | linker doesn't know about and discards them, but relocations against them | |
82 | remain, leading to rld crashes. */ | |
83 | #ifdef TE_IRIX | |
84 | int mips_flag_pdr = FALSE; | |
85 | #else | |
86 | int mips_flag_pdr = TRUE; | |
87 | #endif | |
88 | ||
252b5132 RH |
89 | #include "ecoff.h" |
90 | ||
252b5132 | 91 | static char *mips_regmask_frag; |
351cdf24 | 92 | static char *mips_flags_frag; |
252b5132 | 93 | |
85b51719 | 94 | #define ZERO 0 |
741fe287 | 95 | #define ATREG 1 |
df58fc94 RS |
96 | #define S0 16 |
97 | #define S7 23 | |
252b5132 RH |
98 | #define TREG 24 |
99 | #define PIC_CALL_REG 25 | |
100 | #define KT0 26 | |
101 | #define KT1 27 | |
102 | #define GP 28 | |
103 | #define SP 29 | |
104 | #define FP 30 | |
105 | #define RA 31 | |
106 | ||
107 | #define ILLEGAL_REG (32) | |
108 | ||
741fe287 MR |
109 | #define AT mips_opts.at |
110 | ||
252b5132 RH |
111 | extern int target_big_endian; |
112 | ||
252b5132 | 113 | /* The name of the readonly data section. */ |
e8044f35 | 114 | #define RDATA_SECTION_NAME ".rodata" |
252b5132 | 115 | |
a4e06468 RS |
116 | /* Ways in which an instruction can be "appended" to the output. */ |
117 | enum append_method { | |
118 | /* Just add it normally. */ | |
119 | APPEND_ADD, | |
120 | ||
121 | /* Add it normally and then add a nop. */ | |
122 | APPEND_ADD_WITH_NOP, | |
123 | ||
124 | /* Turn an instruction with a delay slot into a "compact" version. */ | |
125 | APPEND_ADD_COMPACT, | |
126 | ||
127 | /* Insert the instruction before the last one. */ | |
128 | APPEND_SWAP | |
129 | }; | |
130 | ||
47e39b9d RS |
131 | /* Information about an instruction, including its format, operands |
132 | and fixups. */ | |
133 | struct mips_cl_insn | |
134 | { | |
135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ | |
136 | const struct mips_opcode *insn_mo; | |
137 | ||
47e39b9d | 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
5c04167a RS |
139 | a copy of INSN_MO->match with the operands filled in. If we have |
140 | decided to use an extended MIPS16 instruction, this includes the | |
141 | extension. */ | |
47e39b9d RS |
142 | unsigned long insn_opcode; |
143 | ||
144 | /* The frag that contains the instruction. */ | |
145 | struct frag *frag; | |
146 | ||
147 | /* The offset into FRAG of the first instruction byte. */ | |
148 | long where; | |
149 | ||
150 | /* The relocs associated with the instruction, if any. */ | |
151 | fixS *fixp[3]; | |
152 | ||
a38419a5 RS |
153 | /* True if this entry cannot be moved from its current position. */ |
154 | unsigned int fixed_p : 1; | |
47e39b9d | 155 | |
708587a4 | 156 | /* True if this instruction occurred in a .set noreorder block. */ |
47e39b9d RS |
157 | unsigned int noreorder_p : 1; |
158 | ||
2fa15973 RS |
159 | /* True for mips16 instructions that jump to an absolute address. */ |
160 | unsigned int mips16_absolute_jump_p : 1; | |
15be625d CM |
161 | |
162 | /* True if this instruction is complete. */ | |
163 | unsigned int complete_p : 1; | |
e407c74b NC |
164 | |
165 | /* True if this instruction is cleared from history by unconditional | |
166 | branch. */ | |
167 | unsigned int cleared_p : 1; | |
47e39b9d RS |
168 | }; |
169 | ||
a325df1d TS |
170 | /* The ABI to use. */ |
171 | enum mips_abi_level | |
172 | { | |
173 | NO_ABI = 0, | |
174 | O32_ABI, | |
175 | O64_ABI, | |
176 | N32_ABI, | |
177 | N64_ABI, | |
178 | EABI_ABI | |
179 | }; | |
180 | ||
181 | /* MIPS ABI we are using for this output file. */ | |
316f5878 | 182 | static enum mips_abi_level mips_abi = NO_ABI; |
a325df1d | 183 | |
143d77c5 EC |
184 | /* Whether or not we have code that can call pic code. */ |
185 | int mips_abicalls = FALSE; | |
186 | ||
aa6975fb ILT |
187 | /* Whether or not we have code which can be put into a shared |
188 | library. */ | |
189 | static bfd_boolean mips_in_shared = TRUE; | |
190 | ||
252b5132 RH |
191 | /* This is the set of options which may be modified by the .set |
192 | pseudo-op. We use a struct so that .set push and .set pop are more | |
193 | reliable. */ | |
194 | ||
e972090a NC |
195 | struct mips_set_options |
196 | { | |
252b5132 RH |
197 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
198 | if it has not been initialized. Changed by `.set mipsN', and the | |
199 | -mipsN command line option, and the default CPU. */ | |
200 | int isa; | |
846ef2d0 RS |
201 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
202 | <asename>', by command line options, and based on the default | |
203 | architecture. */ | |
204 | int ase; | |
252b5132 RH |
205 | /* Whether we are assembling for the mips16 processor. 0 if we are |
206 | not, 1 if we are, and -1 if the value has not been initialized. | |
207 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and | |
208 | -nomips16 command line options, and the default CPU. */ | |
209 | int mips16; | |
df58fc94 RS |
210 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
211 | 1 if we are, and -1 if the value has not been initialized. Changed | |
212 | by `.set micromips' and `.set nomicromips', and the -mmicromips | |
213 | and -mno-micromips command line options, and the default CPU. */ | |
214 | int micromips; | |
252b5132 RH |
215 | /* Non-zero if we should not reorder instructions. Changed by `.set |
216 | reorder' and `.set noreorder'. */ | |
217 | int noreorder; | |
741fe287 MR |
218 | /* Non-zero if we should not permit the register designated "assembler |
219 | temporary" to be used in instructions. The value is the register | |
220 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' | |
221 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ | |
222 | unsigned int at; | |
252b5132 RH |
223 | /* Non-zero if we should warn when a macro instruction expands into |
224 | more than one machine instruction. Changed by `.set nomacro' and | |
225 | `.set macro'. */ | |
226 | int warn_about_macros; | |
227 | /* Non-zero if we should not move instructions. Changed by `.set | |
228 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ | |
229 | int nomove; | |
230 | /* Non-zero if we should not optimize branches by moving the target | |
231 | of the branch into the delay slot. Actually, we don't perform | |
232 | this optimization anyhow. Changed by `.set bopt' and `.set | |
233 | nobopt'. */ | |
234 | int nobopt; | |
235 | /* Non-zero if we should not autoextend mips16 instructions. | |
236 | Changed by `.set autoextend' and `.set noautoextend'. */ | |
237 | int noautoextend; | |
833794fc MR |
238 | /* True if we should only emit 32-bit microMIPS instructions. |
239 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 | |
240 | and -mno-insn32 command line options. */ | |
241 | bfd_boolean insn32; | |
a325df1d TS |
242 | /* Restrict general purpose registers and floating point registers |
243 | to 32 bit. This is initially determined when -mgp32 or -mfp32 | |
244 | is passed but can changed if the assembler code uses .set mipsN. */ | |
bad1aba3 | 245 | int gp; |
0b35dfee | 246 | int fp; |
fef14a42 TS |
247 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
248 | command line option, and the default CPU. */ | |
249 | int arch; | |
aed1a261 RS |
250 | /* True if ".set sym32" is in effect. */ |
251 | bfd_boolean sym32; | |
037b32b9 AN |
252 | /* True if floating-point operations are not allowed. Changed by .set |
253 | softfloat or .set hardfloat, by command line options -msoft-float or | |
254 | -mhard-float. The default is false. */ | |
255 | bfd_boolean soft_float; | |
256 | ||
257 | /* True if only single-precision floating-point operations are allowed. | |
258 | Changed by .set singlefloat or .set doublefloat, command-line options | |
259 | -msingle-float or -mdouble-float. The default is false. */ | |
260 | bfd_boolean single_float; | |
351cdf24 MF |
261 | |
262 | /* 1 if single-precision operations on odd-numbered registers are | |
263 | allowed. */ | |
264 | int oddspreg; | |
252b5132 RH |
265 | }; |
266 | ||
919731af | 267 | /* Specifies whether module level options have been checked yet. */ |
268 | static bfd_boolean file_mips_opts_checked = FALSE; | |
269 | ||
7361da2c AB |
270 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
271 | value has not been initialized. Changed by `.nan legacy' and | |
272 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line | |
273 | options, and the default CPU. */ | |
274 | static int mips_nan2008 = -1; | |
a325df1d | 275 | |
0b35dfee | 276 | /* This is the struct we use to hold the module level set of options. |
bad1aba3 | 277 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
0b35dfee | 278 | fp fields to -1 to indicate that they have not been initialized. */ |
037b32b9 | 279 | |
0b35dfee | 280 | static struct mips_set_options file_mips_opts = |
281 | { | |
282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, | |
283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, | |
284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, | |
bad1aba3 | 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 286 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
0b35dfee | 287 | }; |
252b5132 | 288 | |
0b35dfee | 289 | /* This is similar to file_mips_opts, but for the current set of options. */ |
ba92f887 | 290 | |
e972090a NC |
291 | static struct mips_set_options mips_opts = |
292 | { | |
846ef2d0 | 293 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
b015e599 | 294 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
833794fc | 295 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
bad1aba3 | 296 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
351cdf24 | 297 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
e7af610e | 298 | }; |
252b5132 | 299 | |
846ef2d0 RS |
300 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
301 | static unsigned int file_ase_explicit; | |
302 | ||
252b5132 RH |
303 | /* These variables are filled in with the masks of registers used. |
304 | The object format code reads them and puts them in the appropriate | |
305 | place. */ | |
306 | unsigned long mips_gprmask; | |
307 | unsigned long mips_cprmask[4]; | |
308 | ||
738f4d98 | 309 | /* True if any MIPS16 code was produced. */ |
a4672219 TS |
310 | static int file_ase_mips16; |
311 | ||
3994f87e TS |
312 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
313 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
314 | || mips_opts.isa == ISA_MIPS32R3 \ |
315 | || mips_opts.isa == ISA_MIPS32R5 \ | |
3994f87e | 316 | || mips_opts.isa == ISA_MIPS64 \ |
ae52f483 AB |
317 | || mips_opts.isa == ISA_MIPS64R2 \ |
318 | || mips_opts.isa == ISA_MIPS64R3 \ | |
319 | || mips_opts.isa == ISA_MIPS64R5) | |
3994f87e | 320 | |
df58fc94 RS |
321 | /* True if any microMIPS code was produced. */ |
322 | static int file_ase_micromips; | |
323 | ||
b12dd2e4 CF |
324 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
325 | #ifdef TE_IRIX | |
1180b5a4 | 326 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
b12dd2e4 | 327 | #else |
1180b5a4 RS |
328 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
329 | because there's no place for any addend, the only acceptable | |
330 | expression is a bare symbol. */ | |
331 | #define MIPS_JALR_HINT_P(EXPR) \ | |
332 | (!HAVE_IN_PLACE_ADDENDS \ | |
333 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) | |
b12dd2e4 CF |
334 | #endif |
335 | ||
ec68c924 | 336 | /* The argument of the -march= flag. The architecture we are assembling. */ |
316f5878 | 337 | static const char *mips_arch_string; |
ec68c924 EC |
338 | |
339 | /* The argument of the -mtune= flag. The architecture for which we | |
340 | are optimizing. */ | |
341 | static int mips_tune = CPU_UNKNOWN; | |
316f5878 | 342 | static const char *mips_tune_string; |
ec68c924 | 343 | |
316f5878 | 344 | /* True when generating 32-bit code for a 64-bit processor. */ |
252b5132 RH |
345 | static int mips_32bitmode = 0; |
346 | ||
316f5878 RS |
347 | /* True if the given ABI requires 32-bit registers. */ |
348 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) | |
349 | ||
350 | /* Likewise 64-bit registers. */ | |
707bfff6 | 351 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
134c0c8b | 352 | ((ABI) == N32_ABI \ |
707bfff6 | 353 | || (ABI) == N64_ABI \ |
316f5878 RS |
354 | || (ABI) == O64_ABI) |
355 | ||
7361da2c AB |
356 | #define ISA_IS_R6(ISA) \ |
357 | ((ISA) == ISA_MIPS32R6 \ | |
358 | || (ISA) == ISA_MIPS64R6) | |
359 | ||
ad3fea08 | 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
707bfff6 TS |
361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
362 | ((ISA) == ISA_MIPS3 \ | |
363 | || (ISA) == ISA_MIPS4 \ | |
364 | || (ISA) == ISA_MIPS5 \ | |
365 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
366 | || (ISA) == ISA_MIPS64R2 \ |
367 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
368 | || (ISA) == ISA_MIPS64R5 \ |
369 | || (ISA) == ISA_MIPS64R6) | |
9ce8a5dd | 370 | |
ad3fea08 TS |
371 | /* Return true if ISA supports 64 bit wide float registers. */ |
372 | #define ISA_HAS_64BIT_FPRS(ISA) \ | |
373 | ((ISA) == ISA_MIPS3 \ | |
374 | || (ISA) == ISA_MIPS4 \ | |
375 | || (ISA) == ISA_MIPS5 \ | |
376 | || (ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
377 | || (ISA) == ISA_MIPS32R3 \ |
378 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 379 | || (ISA) == ISA_MIPS32R6 \ |
ad3fea08 | 380 | || (ISA) == ISA_MIPS64 \ |
ae52f483 AB |
381 | || (ISA) == ISA_MIPS64R2 \ |
382 | || (ISA) == ISA_MIPS64R3 \ | |
7361da2c AB |
383 | || (ISA) == ISA_MIPS64R5 \ |
384 | || (ISA) == ISA_MIPS64R6) | |
ad3fea08 | 385 | |
af7ee8bf CD |
386 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
387 | instructions. */ | |
707bfff6 | 388 | #define ISA_HAS_DROR(ISA) \ |
df58fc94 | 389 | ((ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
390 | || (ISA) == ISA_MIPS64R3 \ |
391 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 392 | || (ISA) == ISA_MIPS64R6 \ |
df58fc94 RS |
393 | || (mips_opts.micromips \ |
394 | && ISA_HAS_64BIT_REGS (ISA)) \ | |
395 | ) | |
af7ee8bf CD |
396 | |
397 | /* Return true if ISA supports 32-bit right rotate (ror et al.) | |
398 | instructions. */ | |
707bfff6 TS |
399 | #define ISA_HAS_ROR(ISA) \ |
400 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
401 | || (ISA) == ISA_MIPS32R3 \ |
402 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 403 | || (ISA) == ISA_MIPS32R6 \ |
707bfff6 | 404 | || (ISA) == ISA_MIPS64R2 \ |
ae52f483 AB |
405 | || (ISA) == ISA_MIPS64R3 \ |
406 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 407 | || (ISA) == ISA_MIPS64R6 \ |
846ef2d0 | 408 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
df58fc94 RS |
409 | || mips_opts.micromips \ |
410 | ) | |
707bfff6 | 411 | |
7455baf8 | 412 | /* Return true if ISA supports single-precision floats in odd registers. */ |
351cdf24 MF |
413 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
414 | (((ISA) == ISA_MIPS32 \ | |
415 | || (ISA) == ISA_MIPS32R2 \ | |
416 | || (ISA) == ISA_MIPS32R3 \ | |
417 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c | 418 | || (ISA) == ISA_MIPS32R6 \ |
351cdf24 MF |
419 | || (ISA) == ISA_MIPS64 \ |
420 | || (ISA) == ISA_MIPS64R2 \ | |
421 | || (ISA) == ISA_MIPS64R3 \ | |
422 | || (ISA) == ISA_MIPS64R5 \ | |
7361da2c | 423 | || (ISA) == ISA_MIPS64R6 \ |
351cdf24 MF |
424 | || (CPU) == CPU_R5900) \ |
425 | && (CPU) != CPU_LOONGSON_3A) | |
af7ee8bf | 426 | |
ad3fea08 TS |
427 | /* Return true if ISA supports move to/from high part of a 64-bit |
428 | floating-point register. */ | |
429 | #define ISA_HAS_MXHC1(ISA) \ | |
430 | ((ISA) == ISA_MIPS32R2 \ | |
ae52f483 AB |
431 | || (ISA) == ISA_MIPS32R3 \ |
432 | || (ISA) == ISA_MIPS32R5 \ | |
7361da2c AB |
433 | || (ISA) == ISA_MIPS32R6 \ |
434 | || (ISA) == ISA_MIPS64R2 \ | |
435 | || (ISA) == ISA_MIPS64R3 \ | |
436 | || (ISA) == ISA_MIPS64R5 \ | |
437 | || (ISA) == ISA_MIPS64R6) | |
438 | ||
439 | /* Return true if ISA supports legacy NAN. */ | |
440 | #define ISA_HAS_LEGACY_NAN(ISA) \ | |
441 | ((ISA) == ISA_MIPS1 \ | |
442 | || (ISA) == ISA_MIPS2 \ | |
443 | || (ISA) == ISA_MIPS3 \ | |
444 | || (ISA) == ISA_MIPS4 \ | |
445 | || (ISA) == ISA_MIPS5 \ | |
446 | || (ISA) == ISA_MIPS32 \ | |
447 | || (ISA) == ISA_MIPS32R2 \ | |
448 | || (ISA) == ISA_MIPS32R3 \ | |
449 | || (ISA) == ISA_MIPS32R5 \ | |
450 | || (ISA) == ISA_MIPS64 \ | |
ae52f483 AB |
451 | || (ISA) == ISA_MIPS64R2 \ |
452 | || (ISA) == ISA_MIPS64R3 \ | |
453 | || (ISA) == ISA_MIPS64R5) | |
ad3fea08 | 454 | |
bad1aba3 | 455 | #define GPR_SIZE \ |
456 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ | |
457 | ? 32 \ | |
458 | : mips_opts.gp) | |
ca4e0257 | 459 | |
bad1aba3 | 460 | #define FPR_SIZE \ |
461 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ | |
462 | ? 32 \ | |
463 | : mips_opts.fp) | |
ca4e0257 | 464 | |
316f5878 | 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
e013f690 | 466 | |
316f5878 | 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
e013f690 | 468 | |
3b91255e RS |
469 | /* True if relocations are stored in-place. */ |
470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) | |
471 | ||
aed1a261 RS |
472 | /* The ABI-derived address size. */ |
473 | #define HAVE_64BIT_ADDRESSES \ | |
bad1aba3 | 474 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
aed1a261 | 475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
e013f690 | 476 | |
aed1a261 RS |
477 | /* The size of symbolic constants (i.e., expressions of the form |
478 | "SYMBOL" or "SYMBOL + OFFSET"). */ | |
479 | #define HAVE_32BIT_SYMBOLS \ | |
480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) | |
481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) | |
ca4e0257 | 482 | |
b7c7d6c1 TS |
483 | /* Addresses are loaded in different ways, depending on the address size |
484 | in use. The n32 ABI Documentation also mandates the use of additions | |
485 | with overflow checking, but existing implementations don't follow it. */ | |
f899b4b8 | 486 | #define ADDRESS_ADD_INSN \ |
b7c7d6c1 | 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
f899b4b8 TS |
488 | |
489 | #define ADDRESS_ADDI_INSN \ | |
b7c7d6c1 | 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
f899b4b8 TS |
491 | |
492 | #define ADDRESS_LOAD_INSN \ | |
493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") | |
494 | ||
495 | #define ADDRESS_STORE_INSN \ | |
496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") | |
497 | ||
a4672219 | 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
3396de36 TS |
499 | #define CPU_HAS_MIPS16(cpu) \ |
500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ | |
501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) | |
a4672219 | 502 | |
2309ddf2 | 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
df58fc94 RS |
504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
505 | ||
60b63b72 RS |
506 | /* True if CPU has a dror instruction. */ |
507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) | |
508 | ||
509 | /* True if CPU has a ror instruction. */ | |
510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) | |
511 | ||
dd6a37e7 | 512 | /* True if CPU is in the Octeon family */ |
2c629856 N |
513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
514 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) | |
dd6a37e7 | 515 | |
dd3cbb7e | 516 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
dd6a37e7 | 517 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
dd3cbb7e | 518 | |
0aa27725 RS |
519 | /* True, if CPU has support for ldc1 and sdc1. */ |
520 | #define CPU_HAS_LDC1_SDC1(CPU) \ | |
521 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) | |
522 | ||
c8978940 CD |
523 | /* True if mflo and mfhi can be immediately followed by instructions |
524 | which write to the HI and LO registers. | |
525 | ||
526 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
527 | (at least) two instructions between the reads of HI/LO and | |
528 | instructions which write them, and later ISAs do not. Contradicting | |
529 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
530 | the UM for the NEC Vr5000) document needing the instructions between | |
531 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
532 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
533 | earlier-ISA CPUs for which CPU documentation declares that the | |
534 | instructions are really interlocked. */ | |
535 | #define hilo_interlocks \ | |
536 | (mips_opts.isa == ISA_MIPS32 \ | |
537 | || mips_opts.isa == ISA_MIPS32R2 \ | |
ae52f483 AB |
538 | || mips_opts.isa == ISA_MIPS32R3 \ |
539 | || mips_opts.isa == ISA_MIPS32R5 \ | |
7361da2c | 540 | || mips_opts.isa == ISA_MIPS32R6 \ |
c8978940 CD |
541 | || mips_opts.isa == ISA_MIPS64 \ |
542 | || mips_opts.isa == ISA_MIPS64R2 \ | |
ae52f483 AB |
543 | || mips_opts.isa == ISA_MIPS64R3 \ |
544 | || mips_opts.isa == ISA_MIPS64R5 \ | |
7361da2c | 545 | || mips_opts.isa == ISA_MIPS64R6 \ |
c8978940 | 546 | || mips_opts.arch == CPU_R4010 \ |
e407c74b | 547 | || mips_opts.arch == CPU_R5900 \ |
c8978940 CD |
548 | || mips_opts.arch == CPU_R10000 \ |
549 | || mips_opts.arch == CPU_R12000 \ | |
3aa3176b TS |
550 | || mips_opts.arch == CPU_R14000 \ |
551 | || mips_opts.arch == CPU_R16000 \ | |
c8978940 | 552 | || mips_opts.arch == CPU_RM7000 \ |
c8978940 | 553 | || mips_opts.arch == CPU_VR5500 \ |
df58fc94 | 554 | || mips_opts.micromips \ |
c8978940 | 555 | ) |
252b5132 RH |
556 | |
557 | /* Whether the processor uses hardware interlocks to protect reads | |
81912461 ILT |
558 | from the GPRs after they are loaded from memory, and thus does not |
559 | require nops to be inserted. This applies to instructions marked | |
67dc82bc | 560 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
df58fc94 RS |
561 | level I and microMIPS mode instructions are always interlocked. */ |
562 | #define gpr_interlocks \ | |
563 | (mips_opts.isa != ISA_MIPS1 \ | |
564 | || mips_opts.arch == CPU_R3900 \ | |
e407c74b | 565 | || mips_opts.arch == CPU_R5900 \ |
df58fc94 RS |
566 | || mips_opts.micromips \ |
567 | ) | |
252b5132 | 568 | |
81912461 ILT |
569 | /* Whether the processor uses hardware interlocks to avoid delays |
570 | required by coprocessor instructions, and thus does not require | |
571 | nops to be inserted. This applies to instructions marked | |
43885403 MF |
572 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
573 | instructions marked INSN_WRITE_COND_CODE and ones marked | |
81912461 | 574 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
df58fc94 RS |
575 | levels I, II, and III and microMIPS mode instructions are always |
576 | interlocked. */ | |
bdaaa2e1 | 577 | /* Itbl support may require additional care here. */ |
81912461 ILT |
578 | #define cop_interlocks \ |
579 | ((mips_opts.isa != ISA_MIPS1 \ | |
580 | && mips_opts.isa != ISA_MIPS2 \ | |
581 | && mips_opts.isa != ISA_MIPS3) \ | |
582 | || mips_opts.arch == CPU_R4300 \ | |
df58fc94 | 583 | || mips_opts.micromips \ |
81912461 ILT |
584 | ) |
585 | ||
586 | /* Whether the processor uses hardware interlocks to protect reads | |
587 | from coprocessor registers after they are loaded from memory, and | |
588 | thus does not require nops to be inserted. This applies to | |
589 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only | |
df58fc94 RS |
590 | requires at MIPS ISA level I and microMIPS mode instructions are |
591 | always interlocked. */ | |
592 | #define cop_mem_interlocks \ | |
593 | (mips_opts.isa != ISA_MIPS1 \ | |
594 | || mips_opts.micromips \ | |
595 | ) | |
252b5132 | 596 | |
6b76fefe CM |
597 | /* Is this a mfhi or mflo instruction? */ |
598 | #define MF_HILO_INSN(PINFO) \ | |
b19e8a9b AN |
599 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
600 | ||
df58fc94 RS |
601 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
602 | has been selected. This implies, in particular, that addresses of text | |
603 | labels have their LSB set. */ | |
604 | #define HAVE_CODE_COMPRESSION \ | |
605 | ((mips_opts.mips16 | mips_opts.micromips) != 0) | |
606 | ||
42429eac | 607 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
bad1aba3 | 608 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
42429eac RS |
609 | #define GPR_SMIN (-GPR_SMAX - 1) |
610 | ||
252b5132 RH |
611 | /* MIPS PIC level. */ |
612 | ||
a161fe53 | 613 | enum mips_pic_level mips_pic; |
252b5132 | 614 | |
c9914766 | 615 | /* 1 if we should generate 32 bit offsets from the $gp register in |
252b5132 | 616 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
c9914766 | 617 | static int mips_big_got = 0; |
252b5132 RH |
618 | |
619 | /* 1 if trap instructions should used for overflow rather than break | |
620 | instructions. */ | |
c9914766 | 621 | static int mips_trap = 0; |
252b5132 | 622 | |
119d663a | 623 | /* 1 if double width floating point constants should not be constructed |
b6ff326e | 624 | by assembling two single width halves into two single width floating |
119d663a NC |
625 | point registers which just happen to alias the double width destination |
626 | register. On some architectures this aliasing can be disabled by a bit | |
d547a75e | 627 | in the status register, and the setting of this bit cannot be determined |
119d663a NC |
628 | automatically at assemble time. */ |
629 | static int mips_disable_float_construction; | |
630 | ||
252b5132 RH |
631 | /* Non-zero if any .set noreorder directives were used. */ |
632 | ||
633 | static int mips_any_noreorder; | |
634 | ||
6b76fefe CM |
635 | /* Non-zero if nops should be inserted when the register referenced in |
636 | an mfhi/mflo instruction is read in the next two instructions. */ | |
637 | static int mips_7000_hilo_fix; | |
638 | ||
02ffd3e4 | 639 | /* The size of objects in the small data section. */ |
156c2f8b | 640 | static unsigned int g_switch_value = 8; |
252b5132 RH |
641 | /* Whether the -G option was used. */ |
642 | static int g_switch_seen = 0; | |
643 | ||
644 | #define N_RMASK 0xc4 | |
645 | #define N_VFP 0xd4 | |
646 | ||
647 | /* If we can determine in advance that GP optimization won't be | |
648 | possible, we can skip the relaxation stuff that tries to produce | |
649 | GP-relative references. This makes delay slot optimization work | |
650 | better. | |
651 | ||
652 | This function can only provide a guess, but it seems to work for | |
fba2b7f9 GK |
653 | gcc output. It needs to guess right for gcc, otherwise gcc |
654 | will put what it thinks is a GP-relative instruction in a branch | |
655 | delay slot. | |
252b5132 RH |
656 | |
657 | I don't know if a fix is needed for the SVR4_PIC mode. I've only | |
658 | fixed it for the non-PIC mode. KR 95/04/07 */ | |
17a2f251 | 659 | static int nopic_need_relax (symbolS *, int); |
252b5132 RH |
660 | |
661 | /* handle of the OPCODE hash table */ | |
662 | static struct hash_control *op_hash = NULL; | |
663 | ||
664 | /* The opcode hash table we use for the mips16. */ | |
665 | static struct hash_control *mips16_op_hash = NULL; | |
666 | ||
df58fc94 RS |
667 | /* The opcode hash table we use for the microMIPS ASE. */ |
668 | static struct hash_control *micromips_op_hash = NULL; | |
669 | ||
252b5132 RH |
670 | /* This array holds the chars that always start a comment. If the |
671 | pre-processor is disabled, these aren't very useful */ | |
672 | const char comment_chars[] = "#"; | |
673 | ||
674 | /* This array holds the chars that only start a comment at the beginning of | |
675 | a line. If the line seems to have the form '# 123 filename' | |
676 | .line and .file directives will appear in the pre-processed output */ | |
677 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
678 | first line of the input file. This is because the compiler outputs | |
bdaaa2e1 | 679 | #NO_APP at the beginning of its output. */ |
252b5132 RH |
680 | /* Also note that C style comments are always supported. */ |
681 | const char line_comment_chars[] = "#"; | |
682 | ||
bdaaa2e1 | 683 | /* This array holds machine specific line separator characters. */ |
63a0b638 | 684 | const char line_separator_chars[] = ";"; |
252b5132 RH |
685 | |
686 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
687 | const char EXP_CHARS[] = "eE"; | |
688 | ||
689 | /* Chars that mean this number is a floating point constant */ | |
690 | /* As in 0f12.456 */ | |
691 | /* or 0d1.2345e12 */ | |
692 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
693 | ||
694 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be | |
695 | changed in read.c . Ideally it shouldn't have to know about it at all, | |
696 | but nothing is ideal around here. | |
697 | */ | |
698 | ||
e3de51ce RS |
699 | /* Types of printf format used for instruction-related error messages. |
700 | "I" means int ("%d") and "S" means string ("%s"). */ | |
701 | enum mips_insn_error_format { | |
702 | ERR_FMT_PLAIN, | |
703 | ERR_FMT_I, | |
704 | ERR_FMT_SS, | |
705 | }; | |
706 | ||
707 | /* Information about an error that was found while assembling the current | |
708 | instruction. */ | |
709 | struct mips_insn_error { | |
710 | /* We sometimes need to match an instruction against more than one | |
711 | opcode table entry. Errors found during this matching are reported | |
712 | against a particular syntactic argument rather than against the | |
713 | instruction as a whole. We grade these messages so that errors | |
714 | against argument N have a greater priority than an error against | |
715 | any argument < N, since the former implies that arguments up to N | |
716 | were acceptable and that the opcode entry was therefore a closer match. | |
717 | If several matches report an error against the same argument, | |
718 | we only use that error if it is the same in all cases. | |
719 | ||
720 | min_argnum is the minimum argument number for which an error message | |
721 | should be accepted. It is 0 if MSG is against the instruction as | |
722 | a whole. */ | |
723 | int min_argnum; | |
724 | ||
725 | /* The printf()-style message, including its format and arguments. */ | |
726 | enum mips_insn_error_format format; | |
727 | const char *msg; | |
728 | union { | |
729 | int i; | |
730 | const char *ss[2]; | |
731 | } u; | |
732 | }; | |
733 | ||
734 | /* The error that should be reported for the current instruction. */ | |
735 | static struct mips_insn_error insn_error; | |
252b5132 RH |
736 | |
737 | static int auto_align = 1; | |
738 | ||
739 | /* When outputting SVR4 PIC code, the assembler needs to know the | |
740 | offset in the stack frame from which to restore the $gp register. | |
741 | This is set by the .cprestore pseudo-op, and saved in this | |
742 | variable. */ | |
743 | static offsetT mips_cprestore_offset = -1; | |
744 | ||
67c1ffbe | 745 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
6478892d | 746 | more optimizations, it can use a register value instead of a memory-saved |
956cd1d6 | 747 | offset and even an other register than $gp as global pointer. */ |
6478892d TS |
748 | static offsetT mips_cpreturn_offset = -1; |
749 | static int mips_cpreturn_register = -1; | |
750 | static int mips_gp_register = GP; | |
def2e0dd | 751 | static int mips_gprel_offset = 0; |
6478892d | 752 | |
7a621144 DJ |
753 | /* Whether mips_cprestore_offset has been set in the current function |
754 | (or whether it has already been warned about, if not). */ | |
755 | static int mips_cprestore_valid = 0; | |
756 | ||
252b5132 RH |
757 | /* This is the register which holds the stack frame, as set by the |
758 | .frame pseudo-op. This is needed to implement .cprestore. */ | |
759 | static int mips_frame_reg = SP; | |
760 | ||
7a621144 DJ |
761 | /* Whether mips_frame_reg has been set in the current function |
762 | (or whether it has already been warned about, if not). */ | |
763 | static int mips_frame_reg_valid = 0; | |
764 | ||
252b5132 RH |
765 | /* To output NOP instructions correctly, we need to keep information |
766 | about the previous two instructions. */ | |
767 | ||
768 | /* Whether we are optimizing. The default value of 2 means to remove | |
769 | unneeded NOPs and swap branch instructions when possible. A value | |
770 | of 1 means to not swap branches. A value of 0 means to always | |
771 | insert NOPs. */ | |
772 | static int mips_optimize = 2; | |
773 | ||
774 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is | |
775 | equivalent to seeing no -g option at all. */ | |
776 | static int mips_debug = 0; | |
777 | ||
7d8e00cf RS |
778 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
779 | #define MAX_VR4130_NOPS 4 | |
780 | ||
781 | /* The maximum number of NOPs needed to fill delay slots. */ | |
782 | #define MAX_DELAY_NOPS 2 | |
783 | ||
784 | /* The maximum number of NOPs needed for any purpose. */ | |
785 | #define MAX_NOPS 4 | |
71400594 RS |
786 | |
787 | /* A list of previous instructions, with index 0 being the most recent. | |
788 | We need to look back MAX_NOPS instructions when filling delay slots | |
789 | or working around processor errata. We need to look back one | |
790 | instruction further if we're thinking about using history[0] to | |
791 | fill a branch delay slot. */ | |
792 | static struct mips_cl_insn history[1 + MAX_NOPS]; | |
252b5132 | 793 | |
fc76e730 | 794 | /* Arrays of operands for each instruction. */ |
14daeee3 | 795 | #define MAX_OPERANDS 6 |
fc76e730 RS |
796 | struct mips_operand_array { |
797 | const struct mips_operand *operand[MAX_OPERANDS]; | |
798 | }; | |
799 | static struct mips_operand_array *mips_operands; | |
800 | static struct mips_operand_array *mips16_operands; | |
801 | static struct mips_operand_array *micromips_operands; | |
802 | ||
1e915849 | 803 | /* Nop instructions used by emit_nop. */ |
df58fc94 RS |
804 | static struct mips_cl_insn nop_insn; |
805 | static struct mips_cl_insn mips16_nop_insn; | |
806 | static struct mips_cl_insn micromips_nop16_insn; | |
807 | static struct mips_cl_insn micromips_nop32_insn; | |
1e915849 RS |
808 | |
809 | /* The appropriate nop for the current mode. */ | |
833794fc MR |
810 | #define NOP_INSN (mips_opts.mips16 \ |
811 | ? &mips16_nop_insn \ | |
812 | : (mips_opts.micromips \ | |
813 | ? (mips_opts.insn32 \ | |
814 | ? µmips_nop32_insn \ | |
815 | : µmips_nop16_insn) \ | |
816 | : &nop_insn)) | |
df58fc94 RS |
817 | |
818 | /* The size of NOP_INSN in bytes. */ | |
833794fc MR |
819 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
820 | || (mips_opts.micromips && !mips_opts.insn32)) \ | |
821 | ? 2 : 4) | |
252b5132 | 822 | |
252b5132 RH |
823 | /* If this is set, it points to a frag holding nop instructions which |
824 | were inserted before the start of a noreorder section. If those | |
825 | nops turn out to be unnecessary, the size of the frag can be | |
826 | decreased. */ | |
827 | static fragS *prev_nop_frag; | |
828 | ||
829 | /* The number of nop instructions we created in prev_nop_frag. */ | |
830 | static int prev_nop_frag_holds; | |
831 | ||
832 | /* The number of nop instructions that we know we need in | |
bdaaa2e1 | 833 | prev_nop_frag. */ |
252b5132 RH |
834 | static int prev_nop_frag_required; |
835 | ||
836 | /* The number of instructions we've seen since prev_nop_frag. */ | |
837 | static int prev_nop_frag_since; | |
838 | ||
e8044f35 RS |
839 | /* Relocations against symbols are sometimes done in two parts, with a HI |
840 | relocation and a LO relocation. Each relocation has only 16 bits of | |
841 | space to store an addend. This means that in order for the linker to | |
842 | handle carries correctly, it must be able to locate both the HI and | |
843 | the LO relocation. This means that the relocations must appear in | |
844 | order in the relocation table. | |
252b5132 RH |
845 | |
846 | In order to implement this, we keep track of each unmatched HI | |
847 | relocation. We then sort them so that they immediately precede the | |
bdaaa2e1 | 848 | corresponding LO relocation. */ |
252b5132 | 849 | |
e972090a NC |
850 | struct mips_hi_fixup |
851 | { | |
252b5132 RH |
852 | /* Next HI fixup. */ |
853 | struct mips_hi_fixup *next; | |
854 | /* This fixup. */ | |
855 | fixS *fixp; | |
856 | /* The section this fixup is in. */ | |
857 | segT seg; | |
858 | }; | |
859 | ||
860 | /* The list of unmatched HI relocs. */ | |
861 | ||
862 | static struct mips_hi_fixup *mips_hi_fixup_list; | |
863 | ||
64bdfcaf RS |
864 | /* The frag containing the last explicit relocation operator. |
865 | Null if explicit relocations have not been used. */ | |
866 | ||
867 | static fragS *prev_reloc_op_frag; | |
868 | ||
252b5132 RH |
869 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
870 | ||
e972090a NC |
871 | static const unsigned int mips16_to_32_reg_map[] = |
872 | { | |
252b5132 RH |
873 | 16, 17, 2, 3, 4, 5, 6, 7 |
874 | }; | |
60b63b72 | 875 | |
df58fc94 RS |
876 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
877 | ||
df58fc94 | 878 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
df58fc94 RS |
879 | |
880 | /* The microMIPS registers with type h. */ | |
e76ff5ab | 881 | static const unsigned int micromips_to_32_reg_h_map1[] = |
df58fc94 RS |
882 | { |
883 | 5, 5, 6, 4, 4, 4, 4, 4 | |
884 | }; | |
e76ff5ab | 885 | static const unsigned int micromips_to_32_reg_h_map2[] = |
df58fc94 RS |
886 | { |
887 | 6, 7, 7, 21, 22, 5, 6, 7 | |
888 | }; | |
889 | ||
df58fc94 RS |
890 | /* The microMIPS registers with type m. */ |
891 | static const unsigned int micromips_to_32_reg_m_map[] = | |
892 | { | |
893 | 0, 17, 2, 3, 16, 18, 19, 20 | |
894 | }; | |
895 | ||
896 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map | |
897 | ||
71400594 RS |
898 | /* Classifies the kind of instructions we're interested in when |
899 | implementing -mfix-vr4120. */ | |
c67a084a NC |
900 | enum fix_vr4120_class |
901 | { | |
71400594 RS |
902 | FIX_VR4120_MACC, |
903 | FIX_VR4120_DMACC, | |
904 | FIX_VR4120_MULT, | |
905 | FIX_VR4120_DMULT, | |
906 | FIX_VR4120_DIV, | |
907 | FIX_VR4120_MTHILO, | |
908 | NUM_FIX_VR4120_CLASSES | |
909 | }; | |
910 | ||
c67a084a NC |
911 | /* ...likewise -mfix-loongson2f-jump. */ |
912 | static bfd_boolean mips_fix_loongson2f_jump; | |
913 | ||
914 | /* ...likewise -mfix-loongson2f-nop. */ | |
915 | static bfd_boolean mips_fix_loongson2f_nop; | |
916 | ||
917 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ | |
918 | static bfd_boolean mips_fix_loongson2f; | |
919 | ||
71400594 RS |
920 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
921 | there must be at least one other instruction between an instruction | |
922 | of type X and an instruction of type Y. */ | |
923 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; | |
924 | ||
925 | /* True if -mfix-vr4120 is in force. */ | |
d766e8ec | 926 | static int mips_fix_vr4120; |
4a6a3df4 | 927 | |
7d8e00cf RS |
928 | /* ...likewise -mfix-vr4130. */ |
929 | static int mips_fix_vr4130; | |
930 | ||
6a32d874 CM |
931 | /* ...likewise -mfix-24k. */ |
932 | static int mips_fix_24k; | |
933 | ||
a8d14a88 CM |
934 | /* ...likewise -mfix-rm7000 */ |
935 | static int mips_fix_rm7000; | |
936 | ||
d954098f DD |
937 | /* ...likewise -mfix-cn63xxp1 */ |
938 | static bfd_boolean mips_fix_cn63xxp1; | |
939 | ||
4a6a3df4 AO |
940 | /* We don't relax branches by default, since this causes us to expand |
941 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we | |
942 | fail to compute the offset before expanding the macro to the most | |
943 | efficient expansion. */ | |
944 | ||
945 | static int mips_relax_branch; | |
8b10b0b3 MR |
946 | |
947 | /* TRUE if checks are suppressed for invalid branches between ISA modes. | |
948 | Needed for broken assembly produced by some GCC versions and some | |
949 | sloppy code out there, where branches to data labels are present. */ | |
950 | static bfd_boolean mips_ignore_branch_isa; | |
252b5132 | 951 | \f |
4d7206a2 RS |
952 | /* The expansion of many macros depends on the type of symbol that |
953 | they refer to. For example, when generating position-dependent code, | |
954 | a macro that refers to a symbol may have two different expansions, | |
955 | one which uses GP-relative addresses and one which uses absolute | |
956 | addresses. When generating SVR4-style PIC, a macro may have | |
957 | different expansions for local and global symbols. | |
958 | ||
959 | We handle these situations by generating both sequences and putting | |
960 | them in variant frags. In position-dependent code, the first sequence | |
961 | will be the GP-relative one and the second sequence will be the | |
962 | absolute one. In SVR4 PIC, the first sequence will be for global | |
963 | symbols and the second will be for local symbols. | |
964 | ||
584892a6 RS |
965 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
966 | SECOND are the lengths of the two sequences in bytes. These fields | |
967 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, | |
968 | the subtype has the following flags: | |
4d7206a2 | 969 | |
ce8ad872 MR |
970 | RELAX_PIC |
971 | Set if generating PIC code. | |
972 | ||
584892a6 RS |
973 | RELAX_USE_SECOND |
974 | Set if it has been decided that we should use the second | |
975 | sequence instead of the first. | |
976 | ||
977 | RELAX_SECOND_LONGER | |
978 | Set in the first variant frag if the macro's second implementation | |
979 | is longer than its first. This refers to the macro as a whole, | |
980 | not an individual relaxation. | |
981 | ||
982 | RELAX_NOMACRO | |
983 | Set in the first variant frag if the macro appeared in a .set nomacro | |
984 | block and if one alternative requires a warning but the other does not. | |
985 | ||
986 | RELAX_DELAY_SLOT | |
987 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch | |
988 | delay slot. | |
4d7206a2 | 989 | |
df58fc94 RS |
990 | RELAX_DELAY_SLOT_16BIT |
991 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a | |
992 | 16-bit instruction. | |
993 | ||
994 | RELAX_DELAY_SLOT_SIZE_FIRST | |
995 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of | |
996 | the macro is of the wrong size for the branch delay slot. | |
997 | ||
998 | RELAX_DELAY_SLOT_SIZE_SECOND | |
999 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of | |
1000 | the macro is of the wrong size for the branch delay slot. | |
1001 | ||
4d7206a2 RS |
1002 | The frag's "opcode" points to the first fixup for relaxable code. |
1003 | ||
1004 | Relaxable macros are generated using a sequence such as: | |
1005 | ||
1006 | relax_start (SYMBOL); | |
1007 | ... generate first expansion ... | |
1008 | relax_switch (); | |
1009 | ... generate second expansion ... | |
1010 | relax_end (); | |
1011 | ||
1012 | The code and fixups for the unwanted alternative are discarded | |
1013 | by md_convert_frag. */ | |
ce8ad872 MR |
1014 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
1015 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) | |
4d7206a2 | 1016 | |
584892a6 RS |
1017 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
1018 | #define RELAX_SECOND(X) ((X) & 0xff) | |
ce8ad872 MR |
1019 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
1020 | #define RELAX_USE_SECOND 0x20000 | |
1021 | #define RELAX_SECOND_LONGER 0x40000 | |
1022 | #define RELAX_NOMACRO 0x80000 | |
1023 | #define RELAX_DELAY_SLOT 0x100000 | |
1024 | #define RELAX_DELAY_SLOT_16BIT 0x200000 | |
1025 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 | |
1026 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 | |
252b5132 | 1027 | |
4a6a3df4 AO |
1028 | /* Branch without likely bit. If label is out of range, we turn: |
1029 | ||
134c0c8b | 1030 | beq reg1, reg2, label |
4a6a3df4 AO |
1031 | delay slot |
1032 | ||
1033 | into | |
1034 | ||
1035 | bne reg1, reg2, 0f | |
1036 | nop | |
1037 | j label | |
1038 | 0: delay slot | |
1039 | ||
1040 | with the following opcode replacements: | |
1041 | ||
1042 | beq <-> bne | |
1043 | blez <-> bgtz | |
1044 | bltz <-> bgez | |
1045 | bc1f <-> bc1t | |
1046 | ||
1047 | bltzal <-> bgezal (with jal label instead of j label) | |
1048 | ||
1049 | Even though keeping the delay slot instruction in the delay slot of | |
1050 | the branch would be more efficient, it would be very tricky to do | |
1051 | correctly, because we'd have to introduce a variable frag *after* | |
1052 | the delay slot instruction, and expand that instead. Let's do it | |
1053 | the easy way for now, even if the branch-not-taken case now costs | |
1054 | one additional instruction. Out-of-range branches are not supposed | |
1055 | to be common, anyway. | |
1056 | ||
1057 | Branch likely. If label is out of range, we turn: | |
1058 | ||
1059 | beql reg1, reg2, label | |
1060 | delay slot (annulled if branch not taken) | |
1061 | ||
1062 | into | |
1063 | ||
1064 | beql reg1, reg2, 1f | |
1065 | nop | |
1066 | beql $0, $0, 2f | |
1067 | nop | |
1068 | 1: j[al] label | |
1069 | delay slot (executed only if branch taken) | |
1070 | 2: | |
1071 | ||
1072 | It would be possible to generate a shorter sequence by losing the | |
1073 | likely bit, generating something like: | |
b34976b6 | 1074 | |
4a6a3df4 AO |
1075 | bne reg1, reg2, 0f |
1076 | nop | |
1077 | j[al] label | |
1078 | delay slot (executed only if branch taken) | |
1079 | 0: | |
1080 | ||
1081 | beql -> bne | |
1082 | bnel -> beq | |
1083 | blezl -> bgtz | |
1084 | bgtzl -> blez | |
1085 | bltzl -> bgez | |
1086 | bgezl -> bltz | |
1087 | bc1fl -> bc1t | |
1088 | bc1tl -> bc1f | |
1089 | ||
1090 | bltzall -> bgezal (with jal label instead of j label) | |
1091 | bgezall -> bltzal (ditto) | |
1092 | ||
1093 | ||
1094 | but it's not clear that it would actually improve performance. */ | |
ce8ad872 MR |
1095 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
1096 | uncond, likely, link, toofar) \ | |
66b3e8da MR |
1097 | ((relax_substateT) \ |
1098 | (0xc0000000 \ | |
1099 | | ((at) & 0x1f) \ | |
ce8ad872 MR |
1100 | | ((pic) ? 0x20 : 0) \ |
1101 | | ((toofar) ? 0x40 : 0) \ | |
1102 | | ((link) ? 0x80 : 0) \ | |
1103 | | ((likely) ? 0x100 : 0) \ | |
1104 | | ((uncond) ? 0x200 : 0))) | |
4a6a3df4 | 1105 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
ce8ad872 MR |
1106 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
1107 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) | |
1108 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) | |
1109 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) | |
1110 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) | |
66b3e8da | 1111 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
4a6a3df4 | 1112 | |
252b5132 RH |
1113 | /* For mips16 code, we use an entirely different form of relaxation. |
1114 | mips16 supports two versions of most instructions which take | |
1115 | immediate values: a small one which takes some small value, and a | |
1116 | larger one which takes a 16 bit value. Since branches also follow | |
1117 | this pattern, relaxing these values is required. | |
1118 | ||
1119 | We can assemble both mips16 and normal MIPS code in a single | |
1120 | object. Therefore, we need to support this type of relaxation at | |
1121 | the same time that we support the relaxation described above. We | |
1122 | use the high bit of the subtype field to distinguish these cases. | |
1123 | ||
1124 | The information we store for this type of relaxation is the | |
1125 | argument code found in the opcode file for this relocation, whether | |
1126 | the user explicitly requested a small or extended form, and whether | |
1127 | the relocation is in a jump or jal delay slot. That tells us the | |
1128 | size of the value, and how it should be stored. We also store | |
1129 | whether the fragment is considered to be extended or not. We also | |
1130 | store whether this is known to be a branch to a different section, | |
1131 | whether we have tried to relax this frag yet, and whether we have | |
1132 | ever extended a PC relative fragment because of a shift count. */ | |
25499ac7 | 1133 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
8507b6e7 MR |
1134 | small, ext, \ |
1135 | dslot, jal_dslot) \ | |
252b5132 RH |
1136 | (0x80000000 \ |
1137 | | ((type) & 0xff) \ | |
25499ac7 MR |
1138 | | ((e2) ? 0x100 : 0) \ |
1139 | | ((pic) ? 0x200 : 0) \ | |
1140 | | ((sym32) ? 0x400 : 0) \ | |
1141 | | ((nomacro) ? 0x800 : 0) \ | |
1142 | | ((small) ? 0x1000 : 0) \ | |
1143 | | ((ext) ? 0x2000 : 0) \ | |
1144 | | ((dslot) ? 0x4000 : 0) \ | |
1145 | | ((jal_dslot) ? 0x8000 : 0)) | |
8507b6e7 | 1146 | |
4a6a3df4 | 1147 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
252b5132 | 1148 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
25499ac7 MR |
1149 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
1150 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) | |
1151 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) | |
1152 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) | |
1153 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) | |
1154 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) | |
1155 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) | |
1156 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) | |
1157 | ||
1158 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) | |
1159 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) | |
1160 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) | |
1161 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) | |
1162 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) | |
1163 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) | |
1164 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) | |
1165 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) | |
1166 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) | |
885add95 | 1167 | |
df58fc94 RS |
1168 | /* For microMIPS code, we use relaxation similar to one we use for |
1169 | MIPS16 code. Some instructions that take immediate values support | |
1170 | two encodings: a small one which takes some small value, and a | |
1171 | larger one which takes a 16 bit value. As some branches also follow | |
1172 | this pattern, relaxing these values is required. | |
1173 | ||
1174 | We can assemble both microMIPS and normal MIPS code in a single | |
1175 | object. Therefore, we need to support this type of relaxation at | |
1176 | the same time that we support the relaxation described above. We | |
1177 | use one of the high bits of the subtype field to distinguish these | |
1178 | cases. | |
1179 | ||
1180 | The information we store for this type of relaxation is the argument | |
1181 | code found in the opcode file for this relocation, the register | |
8484fb75 MR |
1182 | selected as the assembler temporary, whether in the 32-bit |
1183 | instruction mode, whether the branch is unconditional, whether it is | |
7bd374a4 MR |
1184 | compact, whether there is no delay-slot instruction available to fill |
1185 | in, whether it stores the link address implicitly in $ra, whether | |
1186 | relaxation of out-of-range 32-bit branches to a sequence of | |
8484fb75 MR |
1187 | instructions is enabled, and whether the displacement of a branch is |
1188 | too large to fit as an immediate argument of a 16-bit and a 32-bit | |
1189 | branch, respectively. */ | |
ce8ad872 | 1190 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
7bd374a4 | 1191 | uncond, compact, link, nods, \ |
40209cad MR |
1192 | relax32, toofar16, toofar32) \ |
1193 | (0x40000000 \ | |
1194 | | ((type) & 0xff) \ | |
1195 | | (((at) & 0x1f) << 8) \ | |
8484fb75 | 1196 | | ((insn32) ? 0x2000 : 0) \ |
ce8ad872 MR |
1197 | | ((pic) ? 0x4000 : 0) \ |
1198 | | ((uncond) ? 0x8000 : 0) \ | |
1199 | | ((compact) ? 0x10000 : 0) \ | |
1200 | | ((link) ? 0x20000 : 0) \ | |
1201 | | ((nods) ? 0x40000 : 0) \ | |
1202 | | ((relax32) ? 0x80000 : 0) \ | |
1203 | | ((toofar16) ? 0x100000 : 0) \ | |
1204 | | ((toofar32) ? 0x200000 : 0)) | |
df58fc94 RS |
1205 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
1206 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) | |
1207 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) | |
8484fb75 | 1208 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
ce8ad872 MR |
1209 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
1210 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) | |
1211 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) | |
1212 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) | |
1213 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) | |
1214 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) | |
1215 | ||
1216 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) | |
1217 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) | |
1218 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) | |
1219 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) | |
1220 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) | |
1221 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) | |
df58fc94 | 1222 | |
43c0598f RS |
1223 | /* Sign-extend 16-bit value X. */ |
1224 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) | |
1225 | ||
885add95 CD |
1226 | /* Is the given value a sign-extended 32-bit value? */ |
1227 | #define IS_SEXT_32BIT_NUM(x) \ | |
1228 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
1229 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
1230 | ||
1231 | /* Is the given value a sign-extended 16-bit value? */ | |
1232 | #define IS_SEXT_16BIT_NUM(x) \ | |
1233 | (((x) &~ (offsetT) 0x7fff) == 0 \ | |
1234 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) | |
1235 | ||
df58fc94 RS |
1236 | /* Is the given value a sign-extended 12-bit value? */ |
1237 | #define IS_SEXT_12BIT_NUM(x) \ | |
1238 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) | |
1239 | ||
7f3c4072 CM |
1240 | /* Is the given value a sign-extended 9-bit value? */ |
1241 | #define IS_SEXT_9BIT_NUM(x) \ | |
1242 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) | |
1243 | ||
2051e8c4 MR |
1244 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
1245 | #define IS_ZEXT_32BIT_NUM(x) \ | |
1246 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
1247 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
1248 | ||
bf12938e RS |
1249 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
1250 | SHIFT places. */ | |
1251 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ | |
1252 | (((STRUCT) >> (SHIFT)) & (MASK)) | |
1253 | ||
bf12938e | 1254 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
df58fc94 RS |
1255 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
1256 | (!(MICROMIPS) \ | |
1257 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ | |
1258 | : EXTRACT_BITS ((INSN).insn_opcode, \ | |
1259 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) | |
bf12938e RS |
1260 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
1261 | EXTRACT_BITS ((INSN).insn_opcode, \ | |
1262 | MIPS16OP_MASK_##FIELD, \ | |
1263 | MIPS16OP_SH_##FIELD) | |
5c04167a RS |
1264 | |
1265 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ | |
1266 | #define MIPS16_EXTEND (0xf000U << 16) | |
4d7206a2 | 1267 | \f |
df58fc94 RS |
1268 | /* Whether or not we are emitting a branch-likely macro. */ |
1269 | static bfd_boolean emit_branch_likely_macro = FALSE; | |
1270 | ||
4d7206a2 RS |
1271 | /* Global variables used when generating relaxable macros. See the |
1272 | comment above RELAX_ENCODE for more details about how relaxation | |
1273 | is used. */ | |
1274 | static struct { | |
1275 | /* 0 if we're not emitting a relaxable macro. | |
1276 | 1 if we're emitting the first of the two relaxation alternatives. | |
1277 | 2 if we're emitting the second alternative. */ | |
1278 | int sequence; | |
1279 | ||
1280 | /* The first relaxable fixup in the current frag. (In other words, | |
1281 | the first fixup that refers to relaxable code.) */ | |
1282 | fixS *first_fixup; | |
1283 | ||
1284 | /* sizes[0] says how many bytes of the first alternative are stored in | |
1285 | the current frag. Likewise sizes[1] for the second alternative. */ | |
1286 | unsigned int sizes[2]; | |
1287 | ||
1288 | /* The symbol on which the choice of sequence depends. */ | |
1289 | symbolS *symbol; | |
1290 | } mips_relax; | |
252b5132 | 1291 | \f |
584892a6 RS |
1292 | /* Global variables used to decide whether a macro needs a warning. */ |
1293 | static struct { | |
1294 | /* True if the macro is in a branch delay slot. */ | |
1295 | bfd_boolean delay_slot_p; | |
1296 | ||
df58fc94 RS |
1297 | /* Set to the length in bytes required if the macro is in a delay slot |
1298 | that requires a specific length of instruction, otherwise zero. */ | |
1299 | unsigned int delay_slot_length; | |
1300 | ||
584892a6 RS |
1301 | /* For relaxable macros, sizes[0] is the length of the first alternative |
1302 | in bytes and sizes[1] is the length of the second alternative. | |
1303 | For non-relaxable macros, both elements give the length of the | |
1304 | macro in bytes. */ | |
1305 | unsigned int sizes[2]; | |
1306 | ||
df58fc94 RS |
1307 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
1308 | instruction of the first alternative in bytes and first_insn_sizes[1] | |
1309 | is the length of the first instruction of the second alternative. | |
1310 | For non-relaxable macros, both elements give the length of the first | |
1311 | instruction in bytes. | |
1312 | ||
1313 | Set to zero if we haven't yet seen the first instruction. */ | |
1314 | unsigned int first_insn_sizes[2]; | |
1315 | ||
1316 | /* For relaxable macros, insns[0] is the number of instructions for the | |
1317 | first alternative and insns[1] is the number of instructions for the | |
1318 | second alternative. | |
1319 | ||
1320 | For non-relaxable macros, both elements give the number of | |
1321 | instructions for the macro. */ | |
1322 | unsigned int insns[2]; | |
1323 | ||
584892a6 RS |
1324 | /* The first variant frag for this macro. */ |
1325 | fragS *first_frag; | |
1326 | } mips_macro_warning; | |
1327 | \f | |
252b5132 RH |
1328 | /* Prototypes for static functions. */ |
1329 | ||
252b5132 RH |
1330 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
1331 | ||
b34976b6 | 1332 | static void append_insn |
df58fc94 RS |
1333 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
1334 | bfd_boolean expansionp); | |
7d10b47d | 1335 | static void mips_no_prev_insn (void); |
c67a084a | 1336 | static void macro_build (expressionS *, const char *, const char *, ...); |
b34976b6 | 1337 | static void mips16_macro_build |
03ea81db | 1338 | (expressionS *, const char *, const char *, va_list *); |
67c0d1eb | 1339 | static void load_register (int, expressionS *, int); |
584892a6 RS |
1340 | static void macro_start (void); |
1341 | static void macro_end (void); | |
833794fc | 1342 | static void macro (struct mips_cl_insn *ip, char *str); |
17a2f251 | 1343 | static void mips16_macro (struct mips_cl_insn * ip); |
17a2f251 TS |
1344 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
1345 | static void mips16_ip (char *str, struct mips_cl_insn * ip); | |
25499ac7 | 1346 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
b34976b6 | 1347 | static void mips16_immed |
3b4dbbbf | 1348 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
43c0598f | 1349 | unsigned int, unsigned long *); |
5e0116d5 | 1350 | static size_t my_getSmallExpression |
17a2f251 TS |
1351 | (expressionS *, bfd_reloc_code_real_type *, char *); |
1352 | static void my_getExpression (expressionS *, char *); | |
1353 | static void s_align (int); | |
1354 | static void s_change_sec (int); | |
1355 | static void s_change_section (int); | |
1356 | static void s_cons (int); | |
1357 | static void s_float_cons (int); | |
1358 | static void s_mips_globl (int); | |
1359 | static void s_option (int); | |
1360 | static void s_mipsset (int); | |
1361 | static void s_abicalls (int); | |
1362 | static void s_cpload (int); | |
1363 | static void s_cpsetup (int); | |
1364 | static void s_cplocal (int); | |
1365 | static void s_cprestore (int); | |
1366 | static void s_cpreturn (int); | |
741d6ea8 JM |
1367 | static void s_dtprelword (int); |
1368 | static void s_dtpreldword (int); | |
d0f13682 CLT |
1369 | static void s_tprelword (int); |
1370 | static void s_tpreldword (int); | |
17a2f251 TS |
1371 | static void s_gpvalue (int); |
1372 | static void s_gpword (int); | |
1373 | static void s_gpdword (int); | |
a3f278e2 | 1374 | static void s_ehword (int); |
17a2f251 TS |
1375 | static void s_cpadd (int); |
1376 | static void s_insn (int); | |
ba92f887 | 1377 | static void s_nan (int); |
919731af | 1378 | static void s_module (int); |
17a2f251 TS |
1379 | static void s_mips_ent (int); |
1380 | static void s_mips_end (int); | |
1381 | static void s_mips_frame (int); | |
1382 | static void s_mips_mask (int reg_type); | |
1383 | static void s_mips_stab (int); | |
1384 | static void s_mips_weakext (int); | |
1385 | static void s_mips_file (int); | |
1386 | static void s_mips_loc (int); | |
9e009953 | 1387 | static bfd_boolean pic_need_relax (symbolS *); |
4a6a3df4 | 1388 | static int relaxed_branch_length (fragS *, asection *, int); |
df58fc94 RS |
1389 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
1390 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); | |
919731af | 1391 | static void file_mips_check_options (void); |
e7af610e NC |
1392 | |
1393 | /* Table and functions used to map between CPU/ISA names, and | |
1394 | ISA levels, and CPU numbers. */ | |
1395 | ||
e972090a NC |
1396 | struct mips_cpu_info |
1397 | { | |
e7af610e | 1398 | const char *name; /* CPU or ISA name. */ |
d16afab6 RS |
1399 | int flags; /* MIPS_CPU_* flags. */ |
1400 | int ase; /* Set of ASEs implemented by the CPU. */ | |
e7af610e NC |
1401 | int isa; /* ISA level. */ |
1402 | int cpu; /* CPU number (default CPU if ISA). */ | |
1403 | }; | |
1404 | ||
ad3fea08 | 1405 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
ad3fea08 | 1406 | |
17a2f251 TS |
1407 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
1408 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); | |
1409 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); | |
252b5132 | 1410 | \f |
c31f3936 RS |
1411 | /* Command-line options. */ |
1412 | const char *md_shortopts = "O::g::G:"; | |
1413 | ||
1414 | enum options | |
1415 | { | |
1416 | OPTION_MARCH = OPTION_MD_BASE, | |
1417 | OPTION_MTUNE, | |
1418 | OPTION_MIPS1, | |
1419 | OPTION_MIPS2, | |
1420 | OPTION_MIPS3, | |
1421 | OPTION_MIPS4, | |
1422 | OPTION_MIPS5, | |
1423 | OPTION_MIPS32, | |
1424 | OPTION_MIPS64, | |
1425 | OPTION_MIPS32R2, | |
ae52f483 AB |
1426 | OPTION_MIPS32R3, |
1427 | OPTION_MIPS32R5, | |
7361da2c | 1428 | OPTION_MIPS32R6, |
c31f3936 | 1429 | OPTION_MIPS64R2, |
ae52f483 AB |
1430 | OPTION_MIPS64R3, |
1431 | OPTION_MIPS64R5, | |
7361da2c | 1432 | OPTION_MIPS64R6, |
c31f3936 RS |
1433 | OPTION_MIPS16, |
1434 | OPTION_NO_MIPS16, | |
1435 | OPTION_MIPS3D, | |
1436 | OPTION_NO_MIPS3D, | |
1437 | OPTION_MDMX, | |
1438 | OPTION_NO_MDMX, | |
1439 | OPTION_DSP, | |
1440 | OPTION_NO_DSP, | |
1441 | OPTION_MT, | |
1442 | OPTION_NO_MT, | |
1443 | OPTION_VIRT, | |
1444 | OPTION_NO_VIRT, | |
56d438b1 CF |
1445 | OPTION_MSA, |
1446 | OPTION_NO_MSA, | |
c31f3936 RS |
1447 | OPTION_SMARTMIPS, |
1448 | OPTION_NO_SMARTMIPS, | |
1449 | OPTION_DSPR2, | |
1450 | OPTION_NO_DSPR2, | |
8f4f9071 MF |
1451 | OPTION_DSPR3, |
1452 | OPTION_NO_DSPR3, | |
c31f3936 RS |
1453 | OPTION_EVA, |
1454 | OPTION_NO_EVA, | |
7d64c587 AB |
1455 | OPTION_XPA, |
1456 | OPTION_NO_XPA, | |
c31f3936 RS |
1457 | OPTION_MICROMIPS, |
1458 | OPTION_NO_MICROMIPS, | |
1459 | OPTION_MCU, | |
1460 | OPTION_NO_MCU, | |
25499ac7 MR |
1461 | OPTION_MIPS16E2, |
1462 | OPTION_NO_MIPS16E2, | |
730c3174 SE |
1463 | OPTION_CRC, |
1464 | OPTION_NO_CRC, | |
c31f3936 RS |
1465 | OPTION_M4650, |
1466 | OPTION_NO_M4650, | |
1467 | OPTION_M4010, | |
1468 | OPTION_NO_M4010, | |
1469 | OPTION_M4100, | |
1470 | OPTION_NO_M4100, | |
1471 | OPTION_M3900, | |
1472 | OPTION_NO_M3900, | |
1473 | OPTION_M7000_HILO_FIX, | |
1474 | OPTION_MNO_7000_HILO_FIX, | |
1475 | OPTION_FIX_24K, | |
1476 | OPTION_NO_FIX_24K, | |
a8d14a88 CM |
1477 | OPTION_FIX_RM7000, |
1478 | OPTION_NO_FIX_RM7000, | |
c31f3936 RS |
1479 | OPTION_FIX_LOONGSON2F_JUMP, |
1480 | OPTION_NO_FIX_LOONGSON2F_JUMP, | |
1481 | OPTION_FIX_LOONGSON2F_NOP, | |
1482 | OPTION_NO_FIX_LOONGSON2F_NOP, | |
1483 | OPTION_FIX_VR4120, | |
1484 | OPTION_NO_FIX_VR4120, | |
1485 | OPTION_FIX_VR4130, | |
1486 | OPTION_NO_FIX_VR4130, | |
1487 | OPTION_FIX_CN63XXP1, | |
1488 | OPTION_NO_FIX_CN63XXP1, | |
1489 | OPTION_TRAP, | |
1490 | OPTION_BREAK, | |
1491 | OPTION_EB, | |
1492 | OPTION_EL, | |
1493 | OPTION_FP32, | |
1494 | OPTION_GP32, | |
1495 | OPTION_CONSTRUCT_FLOATS, | |
1496 | OPTION_NO_CONSTRUCT_FLOATS, | |
1497 | OPTION_FP64, | |
351cdf24 | 1498 | OPTION_FPXX, |
c31f3936 RS |
1499 | OPTION_GP64, |
1500 | OPTION_RELAX_BRANCH, | |
1501 | OPTION_NO_RELAX_BRANCH, | |
8b10b0b3 MR |
1502 | OPTION_IGNORE_BRANCH_ISA, |
1503 | OPTION_NO_IGNORE_BRANCH_ISA, | |
833794fc MR |
1504 | OPTION_INSN32, |
1505 | OPTION_NO_INSN32, | |
c31f3936 RS |
1506 | OPTION_MSHARED, |
1507 | OPTION_MNO_SHARED, | |
1508 | OPTION_MSYM32, | |
1509 | OPTION_MNO_SYM32, | |
1510 | OPTION_SOFT_FLOAT, | |
1511 | OPTION_HARD_FLOAT, | |
1512 | OPTION_SINGLE_FLOAT, | |
1513 | OPTION_DOUBLE_FLOAT, | |
1514 | OPTION_32, | |
c31f3936 RS |
1515 | OPTION_CALL_SHARED, |
1516 | OPTION_CALL_NONPIC, | |
1517 | OPTION_NON_SHARED, | |
1518 | OPTION_XGOT, | |
1519 | OPTION_MABI, | |
1520 | OPTION_N32, | |
1521 | OPTION_64, | |
1522 | OPTION_MDEBUG, | |
1523 | OPTION_NO_MDEBUG, | |
1524 | OPTION_PDR, | |
1525 | OPTION_NO_PDR, | |
1526 | OPTION_MVXWORKS_PIC, | |
ba92f887 | 1527 | OPTION_NAN, |
351cdf24 MF |
1528 | OPTION_ODD_SPREG, |
1529 | OPTION_NO_ODD_SPREG, | |
c31f3936 RS |
1530 | OPTION_END_OF_ENUM |
1531 | }; | |
1532 | ||
1533 | struct option md_longopts[] = | |
1534 | { | |
1535 | /* Options which specify architecture. */ | |
1536 | {"march", required_argument, NULL, OPTION_MARCH}, | |
1537 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1538 | {"mips0", no_argument, NULL, OPTION_MIPS1}, | |
1539 | {"mips1", no_argument, NULL, OPTION_MIPS1}, | |
1540 | {"mips2", no_argument, NULL, OPTION_MIPS2}, | |
1541 | {"mips3", no_argument, NULL, OPTION_MIPS3}, | |
1542 | {"mips4", no_argument, NULL, OPTION_MIPS4}, | |
1543 | {"mips5", no_argument, NULL, OPTION_MIPS5}, | |
1544 | {"mips32", no_argument, NULL, OPTION_MIPS32}, | |
1545 | {"mips64", no_argument, NULL, OPTION_MIPS64}, | |
1546 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, | |
ae52f483 AB |
1547 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
1548 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, | |
7361da2c | 1549 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
c31f3936 | 1550 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
ae52f483 AB |
1551 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
1552 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, | |
7361da2c | 1553 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
c31f3936 RS |
1554 | |
1555 | /* Options which specify Application Specific Extensions (ASEs). */ | |
1556 | {"mips16", no_argument, NULL, OPTION_MIPS16}, | |
1557 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, | |
1558 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, | |
1559 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, | |
1560 | {"mdmx", no_argument, NULL, OPTION_MDMX}, | |
1561 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, | |
1562 | {"mdsp", no_argument, NULL, OPTION_DSP}, | |
1563 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, | |
1564 | {"mmt", no_argument, NULL, OPTION_MT}, | |
1565 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, | |
1566 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, | |
1567 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, | |
1568 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, | |
1569 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, | |
8f4f9071 MF |
1570 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
1571 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, | |
c31f3936 RS |
1572 | {"meva", no_argument, NULL, OPTION_EVA}, |
1573 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, | |
1574 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, | |
1575 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, | |
1576 | {"mmcu", no_argument, NULL, OPTION_MCU}, | |
1577 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, | |
1578 | {"mvirt", no_argument, NULL, OPTION_VIRT}, | |
1579 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, | |
56d438b1 CF |
1580 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
1581 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, | |
7d64c587 AB |
1582 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
1583 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, | |
25499ac7 MR |
1584 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
1585 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, | |
730c3174 SE |
1586 | {"mcrc", no_argument, NULL, OPTION_CRC}, |
1587 | {"mno-crc", no_argument, NULL, OPTION_NO_CRC}, | |
c31f3936 RS |
1588 | |
1589 | /* Old-style architecture options. Don't add more of these. */ | |
1590 | {"m4650", no_argument, NULL, OPTION_M4650}, | |
1591 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, | |
1592 | {"m4010", no_argument, NULL, OPTION_M4010}, | |
1593 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, | |
1594 | {"m4100", no_argument, NULL, OPTION_M4100}, | |
1595 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, | |
1596 | {"m3900", no_argument, NULL, OPTION_M3900}, | |
1597 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, | |
1598 | ||
1599 | /* Options which enable bug fixes. */ | |
1600 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, | |
1601 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1602 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, | |
1603 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, | |
1604 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, | |
1605 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, | |
1606 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, | |
1607 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, | |
1608 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, | |
1609 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, | |
1610 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, | |
1611 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, | |
1612 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, | |
a8d14a88 CM |
1613 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
1614 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, | |
c31f3936 RS |
1615 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
1616 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, | |
1617 | ||
1618 | /* Miscellaneous options. */ | |
1619 | {"trap", no_argument, NULL, OPTION_TRAP}, | |
1620 | {"no-break", no_argument, NULL, OPTION_TRAP}, | |
1621 | {"break", no_argument, NULL, OPTION_BREAK}, | |
1622 | {"no-trap", no_argument, NULL, OPTION_BREAK}, | |
1623 | {"EB", no_argument, NULL, OPTION_EB}, | |
1624 | {"EL", no_argument, NULL, OPTION_EL}, | |
1625 | {"mfp32", no_argument, NULL, OPTION_FP32}, | |
1626 | {"mgp32", no_argument, NULL, OPTION_GP32}, | |
1627 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, | |
1628 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, | |
1629 | {"mfp64", no_argument, NULL, OPTION_FP64}, | |
351cdf24 | 1630 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
c31f3936 RS |
1631 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
1632 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, | |
1633 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, | |
8b10b0b3 MR |
1634 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
1635 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, | |
833794fc MR |
1636 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
1637 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, | |
c31f3936 RS |
1638 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
1639 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, | |
1640 | {"msym32", no_argument, NULL, OPTION_MSYM32}, | |
1641 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, | |
1642 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, | |
1643 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, | |
1644 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, | |
1645 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, | |
351cdf24 MF |
1646 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
1647 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, | |
c31f3936 RS |
1648 | |
1649 | /* Strictly speaking this next option is ELF specific, | |
1650 | but we allow it for other ports as well in order to | |
1651 | make testing easier. */ | |
1652 | {"32", no_argument, NULL, OPTION_32}, | |
1653 | ||
1654 | /* ELF-specific options. */ | |
c31f3936 RS |
1655 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
1656 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, | |
1657 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, | |
1658 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, | |
1659 | {"xgot", no_argument, NULL, OPTION_XGOT}, | |
1660 | {"mabi", required_argument, NULL, OPTION_MABI}, | |
1661 | {"n32", no_argument, NULL, OPTION_N32}, | |
1662 | {"64", no_argument, NULL, OPTION_64}, | |
1663 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, | |
1664 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, | |
1665 | {"mpdr", no_argument, NULL, OPTION_PDR}, | |
1666 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, | |
1667 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, | |
ba92f887 | 1668 | {"mnan", required_argument, NULL, OPTION_NAN}, |
c31f3936 RS |
1669 | |
1670 | {NULL, no_argument, NULL, 0} | |
1671 | }; | |
1672 | size_t md_longopts_size = sizeof (md_longopts); | |
1673 | \f | |
c6278170 RS |
1674 | /* Information about either an Application Specific Extension or an |
1675 | optional architecture feature that, for simplicity, we treat in the | |
1676 | same way as an ASE. */ | |
1677 | struct mips_ase | |
1678 | { | |
1679 | /* The name of the ASE, used in both the command-line and .set options. */ | |
1680 | const char *name; | |
1681 | ||
1682 | /* The associated ASE_* flags. If the ASE is available on both 32-bit | |
1683 | and 64-bit architectures, the flags here refer to the subset that | |
1684 | is available on both. */ | |
1685 | unsigned int flags; | |
1686 | ||
1687 | /* The ASE_* flag used for instructions that are available on 64-bit | |
1688 | architectures but that are not included in FLAGS. */ | |
1689 | unsigned int flags64; | |
1690 | ||
1691 | /* The command-line options that turn the ASE on and off. */ | |
1692 | int option_on; | |
1693 | int option_off; | |
1694 | ||
1695 | /* The minimum required architecture revisions for MIPS32, MIPS64, | |
1696 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ | |
1697 | int mips32_rev; | |
1698 | int mips64_rev; | |
1699 | int micromips32_rev; | |
1700 | int micromips64_rev; | |
7361da2c AB |
1701 | |
1702 | /* The architecture where the ASE was removed or -1 if the extension has not | |
1703 | been removed. */ | |
1704 | int rem_rev; | |
c6278170 RS |
1705 | }; |
1706 | ||
1707 | /* A table of all supported ASEs. */ | |
1708 | static const struct mips_ase mips_ases[] = { | |
1709 | { "dsp", ASE_DSP, ASE_DSP64, | |
1710 | OPTION_DSP, OPTION_NO_DSP, | |
7361da2c AB |
1711 | 2, 2, 2, 2, |
1712 | -1 }, | |
c6278170 RS |
1713 | |
1714 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, | |
1715 | OPTION_DSPR2, OPTION_NO_DSPR2, | |
7361da2c AB |
1716 | 2, 2, 2, 2, |
1717 | -1 }, | |
c6278170 | 1718 | |
8f4f9071 MF |
1719 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
1720 | OPTION_DSPR3, OPTION_NO_DSPR3, | |
1721 | 6, 6, -1, -1, | |
1722 | -1 }, | |
1723 | ||
c6278170 RS |
1724 | { "eva", ASE_EVA, 0, |
1725 | OPTION_EVA, OPTION_NO_EVA, | |
7361da2c AB |
1726 | 2, 2, 2, 2, |
1727 | -1 }, | |
c6278170 RS |
1728 | |
1729 | { "mcu", ASE_MCU, 0, | |
1730 | OPTION_MCU, OPTION_NO_MCU, | |
7361da2c AB |
1731 | 2, 2, 2, 2, |
1732 | -1 }, | |
c6278170 RS |
1733 | |
1734 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ | |
1735 | { "mdmx", ASE_MDMX, 0, | |
1736 | OPTION_MDMX, OPTION_NO_MDMX, | |
7361da2c AB |
1737 | -1, 1, -1, -1, |
1738 | 6 }, | |
c6278170 RS |
1739 | |
1740 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ | |
1741 | { "mips3d", ASE_MIPS3D, 0, | |
1742 | OPTION_MIPS3D, OPTION_NO_MIPS3D, | |
7361da2c AB |
1743 | 2, 1, -1, -1, |
1744 | 6 }, | |
c6278170 RS |
1745 | |
1746 | { "mt", ASE_MT, 0, | |
1747 | OPTION_MT, OPTION_NO_MT, | |
7361da2c AB |
1748 | 2, 2, -1, -1, |
1749 | -1 }, | |
c6278170 RS |
1750 | |
1751 | { "smartmips", ASE_SMARTMIPS, 0, | |
1752 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, | |
7361da2c AB |
1753 | 1, -1, -1, -1, |
1754 | 6 }, | |
c6278170 RS |
1755 | |
1756 | { "virt", ASE_VIRT, ASE_VIRT64, | |
1757 | OPTION_VIRT, OPTION_NO_VIRT, | |
7361da2c AB |
1758 | 2, 2, 2, 2, |
1759 | -1 }, | |
56d438b1 CF |
1760 | |
1761 | { "msa", ASE_MSA, ASE_MSA64, | |
1762 | OPTION_MSA, OPTION_NO_MSA, | |
7361da2c AB |
1763 | 2, 2, 2, 2, |
1764 | -1 }, | |
7d64c587 AB |
1765 | |
1766 | { "xpa", ASE_XPA, 0, | |
1767 | OPTION_XPA, OPTION_NO_XPA, | |
909b4e3d | 1768 | 2, 2, 2, 2, |
7361da2c | 1769 | -1 }, |
25499ac7 MR |
1770 | |
1771 | { "mips16e2", ASE_MIPS16E2, 0, | |
1772 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, | |
1773 | 2, 2, -1, -1, | |
1774 | 6 }, | |
730c3174 SE |
1775 | |
1776 | { "crc", ASE_CRC, ASE_CRC64, | |
1777 | OPTION_CRC, OPTION_NO_CRC, | |
1778 | 6, 6, -1, -1, | |
1779 | -1 }, | |
c6278170 RS |
1780 | }; |
1781 | ||
1782 | /* The set of ASEs that require -mfp64. */ | |
82bda27b | 1783 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
c6278170 RS |
1784 | |
1785 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ | |
1786 | static const unsigned int mips_ase_groups[] = { | |
8f4f9071 | 1787 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
c6278170 RS |
1788 | }; |
1789 | \f | |
252b5132 RH |
1790 | /* Pseudo-op table. |
1791 | ||
1792 | The following pseudo-ops from the Kane and Heinrich MIPS book | |
1793 | should be defined here, but are currently unsupported: .alias, | |
1794 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. | |
1795 | ||
1796 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1797 | specific to the type of debugging information being generated, and | |
1798 | should be defined by the object format: .aent, .begin, .bend, | |
1799 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, | |
1800 | .vreg. | |
1801 | ||
1802 | The following pseudo-ops from the Kane and Heinrich MIPS book are | |
1803 | not MIPS CPU specific, but are also not specific to the object file | |
1804 | format. This file is probably the best place to define them, but | |
d84bcf09 | 1805 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
252b5132 | 1806 | |
e972090a NC |
1807 | static const pseudo_typeS mips_pseudo_table[] = |
1808 | { | |
beae10d5 | 1809 | /* MIPS specific pseudo-ops. */ |
252b5132 RH |
1810 | {"option", s_option, 0}, |
1811 | {"set", s_mipsset, 0}, | |
1812 | {"rdata", s_change_sec, 'r'}, | |
1813 | {"sdata", s_change_sec, 's'}, | |
1814 | {"livereg", s_ignore, 0}, | |
1815 | {"abicalls", s_abicalls, 0}, | |
1816 | {"cpload", s_cpload, 0}, | |
6478892d TS |
1817 | {"cpsetup", s_cpsetup, 0}, |
1818 | {"cplocal", s_cplocal, 0}, | |
252b5132 | 1819 | {"cprestore", s_cprestore, 0}, |
6478892d | 1820 | {"cpreturn", s_cpreturn, 0}, |
741d6ea8 JM |
1821 | {"dtprelword", s_dtprelword, 0}, |
1822 | {"dtpreldword", s_dtpreldword, 0}, | |
d0f13682 CLT |
1823 | {"tprelword", s_tprelword, 0}, |
1824 | {"tpreldword", s_tpreldword, 0}, | |
6478892d | 1825 | {"gpvalue", s_gpvalue, 0}, |
252b5132 | 1826 | {"gpword", s_gpword, 0}, |
10181a0d | 1827 | {"gpdword", s_gpdword, 0}, |
a3f278e2 | 1828 | {"ehword", s_ehword, 0}, |
252b5132 RH |
1829 | {"cpadd", s_cpadd, 0}, |
1830 | {"insn", s_insn, 0}, | |
ba92f887 | 1831 | {"nan", s_nan, 0}, |
919731af | 1832 | {"module", s_module, 0}, |
252b5132 | 1833 | |
beae10d5 | 1834 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
252b5132 | 1835 | chips. */ |
38a57ae7 | 1836 | {"asciiz", stringer, 8 + 1}, |
252b5132 RH |
1837 | {"bss", s_change_sec, 'b'}, |
1838 | {"err", s_err, 0}, | |
1839 | {"half", s_cons, 1}, | |
1840 | {"dword", s_cons, 3}, | |
1841 | {"weakext", s_mips_weakext, 0}, | |
7c752c2a TS |
1842 | {"origin", s_org, 0}, |
1843 | {"repeat", s_rept, 0}, | |
252b5132 | 1844 | |
998b3c36 MR |
1845 | /* For MIPS this is non-standard, but we define it for consistency. */ |
1846 | {"sbss", s_change_sec, 'B'}, | |
1847 | ||
beae10d5 | 1848 | /* These pseudo-ops are defined in read.c, but must be overridden |
252b5132 RH |
1849 | here for one reason or another. */ |
1850 | {"align", s_align, 0}, | |
1851 | {"byte", s_cons, 0}, | |
1852 | {"data", s_change_sec, 'd'}, | |
1853 | {"double", s_float_cons, 'd'}, | |
1854 | {"float", s_float_cons, 'f'}, | |
1855 | {"globl", s_mips_globl, 0}, | |
1856 | {"global", s_mips_globl, 0}, | |
1857 | {"hword", s_cons, 1}, | |
1858 | {"int", s_cons, 2}, | |
1859 | {"long", s_cons, 2}, | |
1860 | {"octa", s_cons, 4}, | |
1861 | {"quad", s_cons, 3}, | |
cca86cc8 | 1862 | {"section", s_change_section, 0}, |
252b5132 RH |
1863 | {"short", s_cons, 1}, |
1864 | {"single", s_float_cons, 'f'}, | |
754e2bb9 | 1865 | {"stabd", s_mips_stab, 'd'}, |
252b5132 | 1866 | {"stabn", s_mips_stab, 'n'}, |
754e2bb9 | 1867 | {"stabs", s_mips_stab, 's'}, |
252b5132 RH |
1868 | {"text", s_change_sec, 't'}, |
1869 | {"word", s_cons, 2}, | |
add56521 | 1870 | |
add56521 | 1871 | { "extern", ecoff_directive_extern, 0}, |
add56521 | 1872 | |
43841e91 | 1873 | { NULL, NULL, 0 }, |
252b5132 RH |
1874 | }; |
1875 | ||
e972090a NC |
1876 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
1877 | { | |
beae10d5 KH |
1878 | /* These pseudo-ops should be defined by the object file format. |
1879 | However, a.out doesn't support them, so we have versions here. */ | |
252b5132 RH |
1880 | {"aent", s_mips_ent, 1}, |
1881 | {"bgnb", s_ignore, 0}, | |
1882 | {"end", s_mips_end, 0}, | |
1883 | {"endb", s_ignore, 0}, | |
1884 | {"ent", s_mips_ent, 0}, | |
c5dd6aab | 1885 | {"file", s_mips_file, 0}, |
252b5132 RH |
1886 | {"fmask", s_mips_mask, 'F'}, |
1887 | {"frame", s_mips_frame, 0}, | |
c5dd6aab | 1888 | {"loc", s_mips_loc, 0}, |
252b5132 RH |
1889 | {"mask", s_mips_mask, 'R'}, |
1890 | {"verstamp", s_ignore, 0}, | |
43841e91 | 1891 | { NULL, NULL, 0 }, |
252b5132 RH |
1892 | }; |
1893 | ||
3ae8dd8d MR |
1894 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
1895 | purpose of the `.dc.a' internal pseudo-op. */ | |
1896 | ||
1897 | int | |
1898 | mips_address_bytes (void) | |
1899 | { | |
919731af | 1900 | file_mips_check_options (); |
3ae8dd8d MR |
1901 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
1902 | } | |
1903 | ||
17a2f251 | 1904 | extern void pop_insert (const pseudo_typeS *); |
252b5132 RH |
1905 | |
1906 | void | |
17a2f251 | 1907 | mips_pop_insert (void) |
252b5132 RH |
1908 | { |
1909 | pop_insert (mips_pseudo_table); | |
1910 | if (! ECOFF_DEBUGGING) | |
1911 | pop_insert (mips_nonecoff_pseudo_table); | |
1912 | } | |
1913 | \f | |
1914 | /* Symbols labelling the current insn. */ | |
1915 | ||
e972090a NC |
1916 | struct insn_label_list |
1917 | { | |
252b5132 RH |
1918 | struct insn_label_list *next; |
1919 | symbolS *label; | |
1920 | }; | |
1921 | ||
252b5132 | 1922 | static struct insn_label_list *free_insn_labels; |
742a56fe | 1923 | #define label_list tc_segment_info_data.labels |
252b5132 | 1924 | |
17a2f251 | 1925 | static void mips_clear_insn_labels (void); |
df58fc94 RS |
1926 | static void mips_mark_labels (void); |
1927 | static void mips_compressed_mark_labels (void); | |
252b5132 RH |
1928 | |
1929 | static inline void | |
17a2f251 | 1930 | mips_clear_insn_labels (void) |
252b5132 | 1931 | { |
ed9e98c2 | 1932 | struct insn_label_list **pl; |
a8dbcb85 | 1933 | segment_info_type *si; |
252b5132 | 1934 | |
a8dbcb85 TS |
1935 | if (now_seg) |
1936 | { | |
1937 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
1938 | ; | |
3739860c | 1939 | |
a8dbcb85 TS |
1940 | si = seg_info (now_seg); |
1941 | *pl = si->label_list; | |
1942 | si->label_list = NULL; | |
1943 | } | |
252b5132 | 1944 | } |
a8dbcb85 | 1945 | |
df58fc94 RS |
1946 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
1947 | ||
1948 | static inline void | |
1949 | mips_mark_labels (void) | |
1950 | { | |
1951 | if (HAVE_CODE_COMPRESSION) | |
1952 | mips_compressed_mark_labels (); | |
1953 | } | |
252b5132 RH |
1954 | \f |
1955 | static char *expr_end; | |
1956 | ||
e423441d | 1957 | /* An expression in a macro instruction. This is set by mips_ip and |
b0e6f033 | 1958 | mips16_ip and when populated is always an O_constant. */ |
252b5132 RH |
1959 | |
1960 | static expressionS imm_expr; | |
252b5132 | 1961 | |
77bd4346 RS |
1962 | /* The relocatable field in an instruction and the relocs associated |
1963 | with it. These variables are used for instructions like LUI and | |
1964 | JAL as well as true offsets. They are also used for address | |
1965 | operands in macros. */ | |
252b5132 | 1966 | |
77bd4346 | 1967 | static expressionS offset_expr; |
f6688943 TS |
1968 | static bfd_reloc_code_real_type offset_reloc[3] |
1969 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 1970 | |
df58fc94 RS |
1971 | /* This is set to the resulting size of the instruction to be produced |
1972 | by mips16_ip if an explicit extension is used or by mips_ip if an | |
1973 | explicit size is supplied. */ | |
252b5132 | 1974 | |
df58fc94 | 1975 | static unsigned int forced_insn_length; |
252b5132 | 1976 | |
e1b47bd5 RS |
1977 | /* True if we are assembling an instruction. All dot symbols defined during |
1978 | this time should be treated as code labels. */ | |
1979 | ||
1980 | static bfd_boolean mips_assembling_insn; | |
1981 | ||
ecb4347a DJ |
1982 | /* The pdr segment for per procedure frame/regmask info. Not used for |
1983 | ECOFF debugging. */ | |
252b5132 RH |
1984 | |
1985 | static segT pdr_seg; | |
252b5132 | 1986 | |
e013f690 TS |
1987 | /* The default target format to use. */ |
1988 | ||
aeffff67 RS |
1989 | #if defined (TE_FreeBSD) |
1990 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" | |
1991 | #elif defined (TE_TMIPS) | |
1992 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" | |
1993 | #else | |
1994 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" | |
1995 | #endif | |
1996 | ||
e013f690 | 1997 | const char * |
17a2f251 | 1998 | mips_target_format (void) |
e013f690 TS |
1999 | { |
2000 | switch (OUTPUT_FLAVOR) | |
2001 | { | |
e013f690 | 2002 | case bfd_target_elf_flavour: |
0a44bf69 RS |
2003 | #ifdef TE_VXWORKS |
2004 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) | |
2005 | return (target_big_endian | |
2006 | ? "elf32-bigmips-vxworks" | |
2007 | : "elf32-littlemips-vxworks"); | |
2008 | #endif | |
e013f690 | 2009 | return (target_big_endian |
cfe86eaa | 2010 | ? (HAVE_64BIT_OBJECTS |
aeffff67 | 2011 | ? ELF_TARGET ("elf64-", "big") |
cfe86eaa | 2012 | : (HAVE_NEWABI |
aeffff67 RS |
2013 | ? ELF_TARGET ("elf32-n", "big") |
2014 | : ELF_TARGET ("elf32-", "big"))) | |
cfe86eaa | 2015 | : (HAVE_64BIT_OBJECTS |
aeffff67 | 2016 | ? ELF_TARGET ("elf64-", "little") |
cfe86eaa | 2017 | : (HAVE_NEWABI |
aeffff67 RS |
2018 | ? ELF_TARGET ("elf32-n", "little") |
2019 | : ELF_TARGET ("elf32-", "little")))); | |
e013f690 TS |
2020 | default: |
2021 | abort (); | |
2022 | return NULL; | |
2023 | } | |
2024 | } | |
2025 | ||
c6278170 RS |
2026 | /* Return the ISA revision that is currently in use, or 0 if we are |
2027 | generating code for MIPS V or below. */ | |
2028 | ||
2029 | static int | |
2030 | mips_isa_rev (void) | |
2031 | { | |
2032 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) | |
2033 | return 2; | |
2034 | ||
ae52f483 AB |
2035 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
2036 | return 3; | |
2037 | ||
2038 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) | |
2039 | return 5; | |
2040 | ||
7361da2c AB |
2041 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
2042 | return 6; | |
2043 | ||
c6278170 RS |
2044 | /* microMIPS implies revision 2 or above. */ |
2045 | if (mips_opts.micromips) | |
2046 | return 2; | |
2047 | ||
2048 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) | |
2049 | return 1; | |
2050 | ||
2051 | return 0; | |
2052 | } | |
2053 | ||
2054 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ | |
2055 | ||
2056 | static unsigned int | |
2057 | mips_ase_mask (unsigned int flags) | |
2058 | { | |
2059 | unsigned int i; | |
2060 | ||
2061 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) | |
2062 | if (flags & mips_ase_groups[i]) | |
2063 | flags |= mips_ase_groups[i]; | |
2064 | return flags; | |
2065 | } | |
2066 | ||
2067 | /* Check whether the current ISA supports ASE. Issue a warning if | |
2068 | appropriate. */ | |
2069 | ||
2070 | static void | |
2071 | mips_check_isa_supports_ase (const struct mips_ase *ase) | |
2072 | { | |
2073 | const char *base; | |
2074 | int min_rev, size; | |
2075 | static unsigned int warned_isa; | |
2076 | static unsigned int warned_fp32; | |
2077 | ||
2078 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) | |
2079 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; | |
2080 | else | |
2081 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; | |
2082 | if ((min_rev < 0 || mips_isa_rev () < min_rev) | |
2083 | && (warned_isa & ase->flags) != ase->flags) | |
2084 | { | |
2085 | warned_isa |= ase->flags; | |
2086 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2087 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2088 | if (min_rev < 0) | |
1661c76c | 2089 | as_warn (_("the %d-bit %s architecture does not support the" |
c6278170 RS |
2090 | " `%s' extension"), size, base, ase->name); |
2091 | else | |
1661c76c | 2092 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
c6278170 RS |
2093 | ase->name, base, size, min_rev); |
2094 | } | |
7361da2c AB |
2095 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
2096 | && (warned_isa & ase->flags) != ase->flags) | |
2097 | { | |
2098 | warned_isa |= ase->flags; | |
2099 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; | |
2100 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; | |
2101 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), | |
2102 | ase->name, base, size, ase->rem_rev); | |
2103 | } | |
2104 | ||
c6278170 | 2105 | if ((ase->flags & FP64_ASES) |
0b35dfee | 2106 | && mips_opts.fp != 64 |
c6278170 RS |
2107 | && (warned_fp32 & ase->flags) != ase->flags) |
2108 | { | |
2109 | warned_fp32 |= ase->flags; | |
1661c76c | 2110 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
c6278170 RS |
2111 | } |
2112 | } | |
2113 | ||
2114 | /* Check all enabled ASEs to see whether they are supported by the | |
2115 | chosen architecture. */ | |
2116 | ||
2117 | static void | |
2118 | mips_check_isa_supports_ases (void) | |
2119 | { | |
2120 | unsigned int i, mask; | |
2121 | ||
2122 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2123 | { | |
2124 | mask = mips_ase_mask (mips_ases[i].flags); | |
2125 | if ((mips_opts.ase & mask) == mips_ases[i].flags) | |
2126 | mips_check_isa_supports_ase (&mips_ases[i]); | |
2127 | } | |
2128 | } | |
2129 | ||
2130 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags | |
2131 | that were affected. */ | |
2132 | ||
2133 | static unsigned int | |
919731af | 2134 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
2135 | bfd_boolean enabled_p) | |
c6278170 RS |
2136 | { |
2137 | unsigned int mask; | |
2138 | ||
2139 | mask = mips_ase_mask (ase->flags); | |
919731af | 2140 | opts->ase &= ~mask; |
92cebb3d MR |
2141 | |
2142 | /* Clear combination ASE flags, which need to be recalculated based on | |
2143 | updated regular ASE settings. */ | |
9785fc2a | 2144 | opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT); |
92cebb3d | 2145 | |
c6278170 | 2146 | if (enabled_p) |
919731af | 2147 | opts->ase |= ase->flags; |
25499ac7 | 2148 | |
9785fc2a MR |
2149 | /* The Virtualization ASE has eXtended Physical Addressing (XPA) |
2150 | instructions which are only valid when both ASEs are enabled. | |
2151 | This sets the ASE_XPA_VIRT flag when both ASEs are present. */ | |
2152 | if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) | |
2153 | { | |
2154 | opts->ase |= ASE_XPA_VIRT; | |
2155 | mask |= ASE_XPA_VIRT; | |
2156 | } | |
25499ac7 MR |
2157 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) |
2158 | { | |
2159 | opts->ase |= ASE_MIPS16E2_MT; | |
2160 | mask |= ASE_MIPS16E2_MT; | |
2161 | } | |
2162 | ||
c6278170 RS |
2163 | return mask; |
2164 | } | |
2165 | ||
2166 | /* Return the ASE called NAME, or null if none. */ | |
2167 | ||
2168 | static const struct mips_ase * | |
2169 | mips_lookup_ase (const char *name) | |
2170 | { | |
2171 | unsigned int i; | |
2172 | ||
2173 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
2174 | if (strcmp (name, mips_ases[i].name) == 0) | |
2175 | return &mips_ases[i]; | |
2176 | return NULL; | |
2177 | } | |
2178 | ||
df58fc94 | 2179 | /* Return the length of a microMIPS instruction in bytes. If bits of |
100b4f2e MR |
2180 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
2181 | otherwise it is a 32-bit instruction. */ | |
df58fc94 RS |
2182 | |
2183 | static inline unsigned int | |
2184 | micromips_insn_length (const struct mips_opcode *mo) | |
2185 | { | |
7fd53920 | 2186 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
df58fc94 RS |
2187 | } |
2188 | ||
5c04167a RS |
2189 | /* Return the length of MIPS16 instruction OPCODE. */ |
2190 | ||
2191 | static inline unsigned int | |
2192 | mips16_opcode_length (unsigned long opcode) | |
2193 | { | |
2194 | return (opcode >> 16) == 0 ? 2 : 4; | |
2195 | } | |
2196 | ||
1e915849 RS |
2197 | /* Return the length of instruction INSN. */ |
2198 | ||
2199 | static inline unsigned int | |
2200 | insn_length (const struct mips_cl_insn *insn) | |
2201 | { | |
df58fc94 RS |
2202 | if (mips_opts.micromips) |
2203 | return micromips_insn_length (insn->insn_mo); | |
2204 | else if (mips_opts.mips16) | |
5c04167a | 2205 | return mips16_opcode_length (insn->insn_opcode); |
df58fc94 | 2206 | else |
1e915849 | 2207 | return 4; |
1e915849 RS |
2208 | } |
2209 | ||
2210 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
2211 | ||
2212 | static void | |
2213 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) | |
2214 | { | |
2215 | size_t i; | |
2216 | ||
2217 | insn->insn_mo = mo; | |
1e915849 RS |
2218 | insn->insn_opcode = mo->match; |
2219 | insn->frag = NULL; | |
2220 | insn->where = 0; | |
2221 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2222 | insn->fixp[i] = NULL; | |
2223 | insn->fixed_p = (mips_opts.noreorder > 0); | |
2224 | insn->noreorder_p = (mips_opts.noreorder > 0); | |
2225 | insn->mips16_absolute_jump_p = 0; | |
15be625d | 2226 | insn->complete_p = 0; |
e407c74b | 2227 | insn->cleared_p = 0; |
1e915849 RS |
2228 | } |
2229 | ||
fc76e730 RS |
2230 | /* Get a list of all the operands in INSN. */ |
2231 | ||
2232 | static const struct mips_operand_array * | |
2233 | insn_operands (const struct mips_cl_insn *insn) | |
2234 | { | |
2235 | if (insn->insn_mo >= &mips_opcodes[0] | |
2236 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) | |
2237 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; | |
2238 | ||
2239 | if (insn->insn_mo >= &mips16_opcodes[0] | |
2240 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) | |
2241 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; | |
2242 | ||
2243 | if (insn->insn_mo >= µmips_opcodes[0] | |
2244 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) | |
2245 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; | |
2246 | ||
2247 | abort (); | |
2248 | } | |
2249 | ||
2250 | /* Get a description of operand OPNO of INSN. */ | |
2251 | ||
2252 | static const struct mips_operand * | |
2253 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) | |
2254 | { | |
2255 | const struct mips_operand_array *operands; | |
2256 | ||
2257 | operands = insn_operands (insn); | |
2258 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) | |
2259 | abort (); | |
2260 | return operands->operand[opno]; | |
2261 | } | |
2262 | ||
e077a1c8 RS |
2263 | /* Install UVAL as the value of OPERAND in INSN. */ |
2264 | ||
2265 | static inline void | |
2266 | insn_insert_operand (struct mips_cl_insn *insn, | |
2267 | const struct mips_operand *operand, unsigned int uval) | |
2268 | { | |
25499ac7 MR |
2269 | if (mips_opts.mips16 |
2270 | && operand->type == OP_INT && operand->lsb == 0 | |
2271 | && mips_opcode_32bit_p (insn->insn_mo)) | |
2272 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); | |
2273 | else | |
2274 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); | |
e077a1c8 RS |
2275 | } |
2276 | ||
fc76e730 RS |
2277 | /* Extract the value of OPERAND from INSN. */ |
2278 | ||
2279 | static inline unsigned | |
2280 | insn_extract_operand (const struct mips_cl_insn *insn, | |
2281 | const struct mips_operand *operand) | |
2282 | { | |
2283 | return mips_extract_operand (operand, insn->insn_opcode); | |
2284 | } | |
2285 | ||
df58fc94 | 2286 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
742a56fe RS |
2287 | |
2288 | static void | |
df58fc94 | 2289 | mips_record_compressed_mode (void) |
742a56fe RS |
2290 | { |
2291 | segment_info_type *si; | |
2292 | ||
2293 | si = seg_info (now_seg); | |
2294 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) | |
2295 | si->tc_segment_info_data.mips16 = mips_opts.mips16; | |
df58fc94 RS |
2296 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
2297 | si->tc_segment_info_data.micromips = mips_opts.micromips; | |
742a56fe RS |
2298 | } |
2299 | ||
4d68580a RS |
2300 | /* Read a standard MIPS instruction from BUF. */ |
2301 | ||
2302 | static unsigned long | |
2303 | read_insn (char *buf) | |
2304 | { | |
2305 | if (target_big_endian) | |
2306 | return bfd_getb32 ((bfd_byte *) buf); | |
2307 | else | |
2308 | return bfd_getl32 ((bfd_byte *) buf); | |
2309 | } | |
2310 | ||
2311 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to | |
2312 | the next byte. */ | |
2313 | ||
2314 | static char * | |
2315 | write_insn (char *buf, unsigned int insn) | |
2316 | { | |
2317 | md_number_to_chars (buf, insn, 4); | |
2318 | return buf + 4; | |
2319 | } | |
2320 | ||
2321 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it | |
2322 | has length LENGTH. */ | |
2323 | ||
2324 | static unsigned long | |
2325 | read_compressed_insn (char *buf, unsigned int length) | |
2326 | { | |
2327 | unsigned long insn; | |
2328 | unsigned int i; | |
2329 | ||
2330 | insn = 0; | |
2331 | for (i = 0; i < length; i += 2) | |
2332 | { | |
2333 | insn <<= 16; | |
2334 | if (target_big_endian) | |
2335 | insn |= bfd_getb16 ((char *) buf); | |
2336 | else | |
2337 | insn |= bfd_getl16 ((char *) buf); | |
2338 | buf += 2; | |
2339 | } | |
2340 | return insn; | |
2341 | } | |
2342 | ||
5c04167a RS |
2343 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
2344 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ | |
2345 | ||
2346 | static char * | |
2347 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) | |
2348 | { | |
2349 | unsigned int i; | |
2350 | ||
2351 | for (i = 0; i < length; i += 2) | |
2352 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); | |
2353 | return buf + length; | |
2354 | } | |
2355 | ||
1e915849 RS |
2356 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
2357 | ||
2358 | static void | |
2359 | install_insn (const struct mips_cl_insn *insn) | |
2360 | { | |
2361 | char *f = insn->frag->fr_literal + insn->where; | |
5c04167a RS |
2362 | if (HAVE_CODE_COMPRESSION) |
2363 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); | |
1e915849 | 2364 | else |
4d68580a | 2365 | write_insn (f, insn->insn_opcode); |
df58fc94 | 2366 | mips_record_compressed_mode (); |
1e915849 RS |
2367 | } |
2368 | ||
2369 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
2370 | and install the opcode in the new location. */ | |
2371 | ||
2372 | static void | |
2373 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) | |
2374 | { | |
2375 | size_t i; | |
2376 | ||
2377 | insn->frag = frag; | |
2378 | insn->where = where; | |
2379 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) | |
2380 | if (insn->fixp[i] != NULL) | |
2381 | { | |
2382 | insn->fixp[i]->fx_frag = frag; | |
2383 | insn->fixp[i]->fx_where = where; | |
2384 | } | |
2385 | install_insn (insn); | |
2386 | } | |
2387 | ||
2388 | /* Add INSN to the end of the output. */ | |
2389 | ||
2390 | static void | |
2391 | add_fixed_insn (struct mips_cl_insn *insn) | |
2392 | { | |
2393 | char *f = frag_more (insn_length (insn)); | |
2394 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
2395 | } | |
2396 | ||
2397 | /* Start a variant frag and move INSN to the start of the variant part, | |
2398 | marking it as fixed. The other arguments are as for frag_var. */ | |
2399 | ||
2400 | static void | |
2401 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, | |
2402 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
2403 | { | |
2404 | frag_grow (max_chars); | |
2405 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
2406 | insn->fixed_p = 1; | |
2407 | frag_var (rs_machine_dependent, max_chars, var, | |
2408 | subtype, symbol, offset, NULL); | |
2409 | } | |
2410 | ||
2411 | /* Insert N copies of INSN into the history buffer, starting at | |
2412 | position FIRST. Neither FIRST nor N need to be clipped. */ | |
2413 | ||
2414 | static void | |
2415 | insert_into_history (unsigned int first, unsigned int n, | |
2416 | const struct mips_cl_insn *insn) | |
2417 | { | |
2418 | if (mips_relax.sequence != 2) | |
2419 | { | |
2420 | unsigned int i; | |
2421 | ||
2422 | for (i = ARRAY_SIZE (history); i-- > first;) | |
2423 | if (i >= first + n) | |
2424 | history[i] = history[i - n]; | |
2425 | else | |
2426 | history[i] = *insn; | |
2427 | } | |
2428 | } | |
2429 | ||
e3de51ce RS |
2430 | /* Clear the error in insn_error. */ |
2431 | ||
2432 | static void | |
2433 | clear_insn_error (void) | |
2434 | { | |
2435 | memset (&insn_error, 0, sizeof (insn_error)); | |
2436 | } | |
2437 | ||
2438 | /* Possibly record error message MSG for the current instruction. | |
2439 | If the error is about a particular argument, ARGNUM is the 1-based | |
2440 | number of that argument, otherwise it is 0. FORMAT is the format | |
2441 | of MSG. Return true if MSG was used, false if the current message | |
2442 | was kept. */ | |
2443 | ||
2444 | static bfd_boolean | |
2445 | set_insn_error_format (int argnum, enum mips_insn_error_format format, | |
2446 | const char *msg) | |
2447 | { | |
2448 | if (argnum == 0) | |
2449 | { | |
2450 | /* Give priority to errors against specific arguments, and to | |
2451 | the first whole-instruction message. */ | |
2452 | if (insn_error.msg) | |
2453 | return FALSE; | |
2454 | } | |
2455 | else | |
2456 | { | |
2457 | /* Keep insn_error if it is against a later argument. */ | |
2458 | if (argnum < insn_error.min_argnum) | |
2459 | return FALSE; | |
2460 | ||
2461 | /* If both errors are against the same argument but are different, | |
2462 | give up on reporting a specific error for this argument. | |
2463 | See the comment about mips_insn_error for details. */ | |
2464 | if (argnum == insn_error.min_argnum | |
2465 | && insn_error.msg | |
2466 | && strcmp (insn_error.msg, msg) != 0) | |
2467 | { | |
2468 | insn_error.msg = 0; | |
2469 | insn_error.min_argnum += 1; | |
2470 | return FALSE; | |
2471 | } | |
2472 | } | |
2473 | insn_error.min_argnum = argnum; | |
2474 | insn_error.format = format; | |
2475 | insn_error.msg = msg; | |
2476 | return TRUE; | |
2477 | } | |
2478 | ||
2479 | /* Record an instruction error with no % format fields. ARGNUM and MSG are | |
2480 | as for set_insn_error_format. */ | |
2481 | ||
2482 | static void | |
2483 | set_insn_error (int argnum, const char *msg) | |
2484 | { | |
2485 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); | |
2486 | } | |
2487 | ||
2488 | /* Record an instruction error with one %d field I. ARGNUM and MSG are | |
2489 | as for set_insn_error_format. */ | |
2490 | ||
2491 | static void | |
2492 | set_insn_error_i (int argnum, const char *msg, int i) | |
2493 | { | |
2494 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) | |
2495 | insn_error.u.i = i; | |
2496 | } | |
2497 | ||
2498 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG | |
2499 | are as for set_insn_error_format. */ | |
2500 | ||
2501 | static void | |
2502 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) | |
2503 | { | |
2504 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) | |
2505 | { | |
2506 | insn_error.u.ss[0] = s1; | |
2507 | insn_error.u.ss[1] = s2; | |
2508 | } | |
2509 | } | |
2510 | ||
2511 | /* Report the error in insn_error, which is against assembly code STR. */ | |
2512 | ||
2513 | static void | |
2514 | report_insn_error (const char *str) | |
2515 | { | |
e1fa0163 | 2516 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
e3de51ce | 2517 | |
e3de51ce RS |
2518 | switch (insn_error.format) |
2519 | { | |
2520 | case ERR_FMT_PLAIN: | |
2521 | as_bad (msg, str); | |
2522 | break; | |
2523 | ||
2524 | case ERR_FMT_I: | |
2525 | as_bad (msg, insn_error.u.i, str); | |
2526 | break; | |
2527 | ||
2528 | case ERR_FMT_SS: | |
2529 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); | |
2530 | break; | |
2531 | } | |
e1fa0163 NC |
2532 | |
2533 | free ((char *) msg); | |
e3de51ce RS |
2534 | } |
2535 | ||
71400594 RS |
2536 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
2537 | the idea is to make it obvious at a glance that each errata is | |
2538 | included. */ | |
2539 | ||
2540 | static void | |
2541 | init_vr4120_conflicts (void) | |
2542 | { | |
2543 | #define CONFLICT(FIRST, SECOND) \ | |
2544 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND | |
2545 | ||
2546 | /* Errata 21 - [D]DIV[U] after [D]MACC */ | |
2547 | CONFLICT (MACC, DIV); | |
2548 | CONFLICT (DMACC, DIV); | |
2549 | ||
2550 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ | |
2551 | CONFLICT (DMULT, DMULT); | |
2552 | CONFLICT (DMULT, DMACC); | |
2553 | CONFLICT (DMACC, DMULT); | |
2554 | CONFLICT (DMACC, DMACC); | |
2555 | ||
2556 | /* Errata 24 - MT{LO,HI} after [D]MACC */ | |
2557 | CONFLICT (MACC, MTHILO); | |
2558 | CONFLICT (DMACC, MTHILO); | |
2559 | ||
2560 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU | |
2561 | instruction is executed immediately after a MACC or DMACC | |
2562 | instruction, the result of [either instruction] is incorrect." */ | |
2563 | CONFLICT (MACC, MULT); | |
2564 | CONFLICT (MACC, DMULT); | |
2565 | CONFLICT (DMACC, MULT); | |
2566 | CONFLICT (DMACC, DMULT); | |
2567 | ||
2568 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is | |
2569 | executed immediately after a DMULT, DMULTU, DIV, DIVU, | |
2570 | DDIV or DDIVU instruction, the result of the MACC or | |
2571 | DMACC instruction is incorrect.". */ | |
2572 | CONFLICT (DMULT, MACC); | |
2573 | CONFLICT (DMULT, DMACC); | |
2574 | CONFLICT (DIV, MACC); | |
2575 | CONFLICT (DIV, DMACC); | |
2576 | ||
2577 | #undef CONFLICT | |
2578 | } | |
2579 | ||
707bfff6 TS |
2580 | struct regname { |
2581 | const char *name; | |
2582 | unsigned int num; | |
2583 | }; | |
2584 | ||
14daeee3 | 2585 | #define RNUM_MASK 0x00000ff |
56d438b1 | 2586 | #define RTYPE_MASK 0x0ffff00 |
14daeee3 RS |
2587 | #define RTYPE_NUM 0x0000100 |
2588 | #define RTYPE_FPU 0x0000200 | |
2589 | #define RTYPE_FCC 0x0000400 | |
2590 | #define RTYPE_VEC 0x0000800 | |
2591 | #define RTYPE_GP 0x0001000 | |
2592 | #define RTYPE_CP0 0x0002000 | |
2593 | #define RTYPE_PC 0x0004000 | |
2594 | #define RTYPE_ACC 0x0008000 | |
2595 | #define RTYPE_CCC 0x0010000 | |
2596 | #define RTYPE_VI 0x0020000 | |
2597 | #define RTYPE_VF 0x0040000 | |
2598 | #define RTYPE_R5900_I 0x0080000 | |
2599 | #define RTYPE_R5900_Q 0x0100000 | |
2600 | #define RTYPE_R5900_R 0x0200000 | |
2601 | #define RTYPE_R5900_ACC 0x0400000 | |
56d438b1 | 2602 | #define RTYPE_MSA 0x0800000 |
14daeee3 | 2603 | #define RWARN 0x8000000 |
707bfff6 TS |
2604 | |
2605 | #define GENERIC_REGISTER_NUMBERS \ | |
2606 | {"$0", RTYPE_NUM | 0}, \ | |
2607 | {"$1", RTYPE_NUM | 1}, \ | |
2608 | {"$2", RTYPE_NUM | 2}, \ | |
2609 | {"$3", RTYPE_NUM | 3}, \ | |
2610 | {"$4", RTYPE_NUM | 4}, \ | |
2611 | {"$5", RTYPE_NUM | 5}, \ | |
2612 | {"$6", RTYPE_NUM | 6}, \ | |
2613 | {"$7", RTYPE_NUM | 7}, \ | |
2614 | {"$8", RTYPE_NUM | 8}, \ | |
2615 | {"$9", RTYPE_NUM | 9}, \ | |
2616 | {"$10", RTYPE_NUM | 10}, \ | |
2617 | {"$11", RTYPE_NUM | 11}, \ | |
2618 | {"$12", RTYPE_NUM | 12}, \ | |
2619 | {"$13", RTYPE_NUM | 13}, \ | |
2620 | {"$14", RTYPE_NUM | 14}, \ | |
2621 | {"$15", RTYPE_NUM | 15}, \ | |
2622 | {"$16", RTYPE_NUM | 16}, \ | |
2623 | {"$17", RTYPE_NUM | 17}, \ | |
2624 | {"$18", RTYPE_NUM | 18}, \ | |
2625 | {"$19", RTYPE_NUM | 19}, \ | |
2626 | {"$20", RTYPE_NUM | 20}, \ | |
2627 | {"$21", RTYPE_NUM | 21}, \ | |
2628 | {"$22", RTYPE_NUM | 22}, \ | |
2629 | {"$23", RTYPE_NUM | 23}, \ | |
2630 | {"$24", RTYPE_NUM | 24}, \ | |
2631 | {"$25", RTYPE_NUM | 25}, \ | |
2632 | {"$26", RTYPE_NUM | 26}, \ | |
2633 | {"$27", RTYPE_NUM | 27}, \ | |
2634 | {"$28", RTYPE_NUM | 28}, \ | |
2635 | {"$29", RTYPE_NUM | 29}, \ | |
2636 | {"$30", RTYPE_NUM | 30}, \ | |
3739860c | 2637 | {"$31", RTYPE_NUM | 31} |
707bfff6 TS |
2638 | |
2639 | #define FPU_REGISTER_NAMES \ | |
2640 | {"$f0", RTYPE_FPU | 0}, \ | |
2641 | {"$f1", RTYPE_FPU | 1}, \ | |
2642 | {"$f2", RTYPE_FPU | 2}, \ | |
2643 | {"$f3", RTYPE_FPU | 3}, \ | |
2644 | {"$f4", RTYPE_FPU | 4}, \ | |
2645 | {"$f5", RTYPE_FPU | 5}, \ | |
2646 | {"$f6", RTYPE_FPU | 6}, \ | |
2647 | {"$f7", RTYPE_FPU | 7}, \ | |
2648 | {"$f8", RTYPE_FPU | 8}, \ | |
2649 | {"$f9", RTYPE_FPU | 9}, \ | |
2650 | {"$f10", RTYPE_FPU | 10}, \ | |
2651 | {"$f11", RTYPE_FPU | 11}, \ | |
2652 | {"$f12", RTYPE_FPU | 12}, \ | |
2653 | {"$f13", RTYPE_FPU | 13}, \ | |
2654 | {"$f14", RTYPE_FPU | 14}, \ | |
2655 | {"$f15", RTYPE_FPU | 15}, \ | |
2656 | {"$f16", RTYPE_FPU | 16}, \ | |
2657 | {"$f17", RTYPE_FPU | 17}, \ | |
2658 | {"$f18", RTYPE_FPU | 18}, \ | |
2659 | {"$f19", RTYPE_FPU | 19}, \ | |
2660 | {"$f20", RTYPE_FPU | 20}, \ | |
2661 | {"$f21", RTYPE_FPU | 21}, \ | |
2662 | {"$f22", RTYPE_FPU | 22}, \ | |
2663 | {"$f23", RTYPE_FPU | 23}, \ | |
2664 | {"$f24", RTYPE_FPU | 24}, \ | |
2665 | {"$f25", RTYPE_FPU | 25}, \ | |
2666 | {"$f26", RTYPE_FPU | 26}, \ | |
2667 | {"$f27", RTYPE_FPU | 27}, \ | |
2668 | {"$f28", RTYPE_FPU | 28}, \ | |
2669 | {"$f29", RTYPE_FPU | 29}, \ | |
2670 | {"$f30", RTYPE_FPU | 30}, \ | |
2671 | {"$f31", RTYPE_FPU | 31} | |
2672 | ||
2673 | #define FPU_CONDITION_CODE_NAMES \ | |
2674 | {"$fcc0", RTYPE_FCC | 0}, \ | |
2675 | {"$fcc1", RTYPE_FCC | 1}, \ | |
2676 | {"$fcc2", RTYPE_FCC | 2}, \ | |
2677 | {"$fcc3", RTYPE_FCC | 3}, \ | |
2678 | {"$fcc4", RTYPE_FCC | 4}, \ | |
2679 | {"$fcc5", RTYPE_FCC | 5}, \ | |
2680 | {"$fcc6", RTYPE_FCC | 6}, \ | |
2681 | {"$fcc7", RTYPE_FCC | 7} | |
2682 | ||
2683 | #define COPROC_CONDITION_CODE_NAMES \ | |
2684 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ | |
2685 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ | |
2686 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ | |
2687 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ | |
2688 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ | |
2689 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ | |
2690 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ | |
2691 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} | |
2692 | ||
2693 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ | |
2694 | {"$a4", RTYPE_GP | 8}, \ | |
2695 | {"$a5", RTYPE_GP | 9}, \ | |
2696 | {"$a6", RTYPE_GP | 10}, \ | |
2697 | {"$a7", RTYPE_GP | 11}, \ | |
2698 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ | |
2699 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ | |
2700 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ | |
2701 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ | |
2702 | {"$t0", RTYPE_GP | 12}, \ | |
2703 | {"$t1", RTYPE_GP | 13}, \ | |
2704 | {"$t2", RTYPE_GP | 14}, \ | |
2705 | {"$t3", RTYPE_GP | 15} | |
2706 | ||
2707 | #define O32_SYMBOLIC_REGISTER_NAMES \ | |
2708 | {"$t0", RTYPE_GP | 8}, \ | |
2709 | {"$t1", RTYPE_GP | 9}, \ | |
2710 | {"$t2", RTYPE_GP | 10}, \ | |
2711 | {"$t3", RTYPE_GP | 11}, \ | |
2712 | {"$t4", RTYPE_GP | 12}, \ | |
2713 | {"$t5", RTYPE_GP | 13}, \ | |
2714 | {"$t6", RTYPE_GP | 14}, \ | |
2715 | {"$t7", RTYPE_GP | 15}, \ | |
2716 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ | |
2717 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ | |
2718 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ | |
3739860c | 2719 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
707bfff6 TS |
2720 | |
2721 | /* Remaining symbolic register names */ | |
2722 | #define SYMBOLIC_REGISTER_NAMES \ | |
2723 | {"$zero", RTYPE_GP | 0}, \ | |
2724 | {"$at", RTYPE_GP | 1}, \ | |
2725 | {"$AT", RTYPE_GP | 1}, \ | |
2726 | {"$v0", RTYPE_GP | 2}, \ | |
2727 | {"$v1", RTYPE_GP | 3}, \ | |
2728 | {"$a0", RTYPE_GP | 4}, \ | |
2729 | {"$a1", RTYPE_GP | 5}, \ | |
2730 | {"$a2", RTYPE_GP | 6}, \ | |
2731 | {"$a3", RTYPE_GP | 7}, \ | |
2732 | {"$s0", RTYPE_GP | 16}, \ | |
2733 | {"$s1", RTYPE_GP | 17}, \ | |
2734 | {"$s2", RTYPE_GP | 18}, \ | |
2735 | {"$s3", RTYPE_GP | 19}, \ | |
2736 | {"$s4", RTYPE_GP | 20}, \ | |
2737 | {"$s5", RTYPE_GP | 21}, \ | |
2738 | {"$s6", RTYPE_GP | 22}, \ | |
2739 | {"$s7", RTYPE_GP | 23}, \ | |
2740 | {"$t8", RTYPE_GP | 24}, \ | |
2741 | {"$t9", RTYPE_GP | 25}, \ | |
2742 | {"$k0", RTYPE_GP | 26}, \ | |
2743 | {"$kt0", RTYPE_GP | 26}, \ | |
2744 | {"$k1", RTYPE_GP | 27}, \ | |
2745 | {"$kt1", RTYPE_GP | 27}, \ | |
2746 | {"$gp", RTYPE_GP | 28}, \ | |
2747 | {"$sp", RTYPE_GP | 29}, \ | |
2748 | {"$s8", RTYPE_GP | 30}, \ | |
2749 | {"$fp", RTYPE_GP | 30}, \ | |
2750 | {"$ra", RTYPE_GP | 31} | |
2751 | ||
2752 | #define MIPS16_SPECIAL_REGISTER_NAMES \ | |
2753 | {"$pc", RTYPE_PC | 0} | |
2754 | ||
2755 | #define MDMX_VECTOR_REGISTER_NAMES \ | |
2756 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ | |
2757 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ | |
2758 | {"$v2", RTYPE_VEC | 2}, \ | |
2759 | {"$v3", RTYPE_VEC | 3}, \ | |
2760 | {"$v4", RTYPE_VEC | 4}, \ | |
2761 | {"$v5", RTYPE_VEC | 5}, \ | |
2762 | {"$v6", RTYPE_VEC | 6}, \ | |
2763 | {"$v7", RTYPE_VEC | 7}, \ | |
2764 | {"$v8", RTYPE_VEC | 8}, \ | |
2765 | {"$v9", RTYPE_VEC | 9}, \ | |
2766 | {"$v10", RTYPE_VEC | 10}, \ | |
2767 | {"$v11", RTYPE_VEC | 11}, \ | |
2768 | {"$v12", RTYPE_VEC | 12}, \ | |
2769 | {"$v13", RTYPE_VEC | 13}, \ | |
2770 | {"$v14", RTYPE_VEC | 14}, \ | |
2771 | {"$v15", RTYPE_VEC | 15}, \ | |
2772 | {"$v16", RTYPE_VEC | 16}, \ | |
2773 | {"$v17", RTYPE_VEC | 17}, \ | |
2774 | {"$v18", RTYPE_VEC | 18}, \ | |
2775 | {"$v19", RTYPE_VEC | 19}, \ | |
2776 | {"$v20", RTYPE_VEC | 20}, \ | |
2777 | {"$v21", RTYPE_VEC | 21}, \ | |
2778 | {"$v22", RTYPE_VEC | 22}, \ | |
2779 | {"$v23", RTYPE_VEC | 23}, \ | |
2780 | {"$v24", RTYPE_VEC | 24}, \ | |
2781 | {"$v25", RTYPE_VEC | 25}, \ | |
2782 | {"$v26", RTYPE_VEC | 26}, \ | |
2783 | {"$v27", RTYPE_VEC | 27}, \ | |
2784 | {"$v28", RTYPE_VEC | 28}, \ | |
2785 | {"$v29", RTYPE_VEC | 29}, \ | |
2786 | {"$v30", RTYPE_VEC | 30}, \ | |
2787 | {"$v31", RTYPE_VEC | 31} | |
2788 | ||
14daeee3 RS |
2789 | #define R5900_I_NAMES \ |
2790 | {"$I", RTYPE_R5900_I | 0} | |
2791 | ||
2792 | #define R5900_Q_NAMES \ | |
2793 | {"$Q", RTYPE_R5900_Q | 0} | |
2794 | ||
2795 | #define R5900_R_NAMES \ | |
2796 | {"$R", RTYPE_R5900_R | 0} | |
2797 | ||
2798 | #define R5900_ACC_NAMES \ | |
2799 | {"$ACC", RTYPE_R5900_ACC | 0 } | |
2800 | ||
707bfff6 TS |
2801 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
2802 | {"$ac0", RTYPE_ACC | 0}, \ | |
2803 | {"$ac1", RTYPE_ACC | 1}, \ | |
2804 | {"$ac2", RTYPE_ACC | 2}, \ | |
2805 | {"$ac3", RTYPE_ACC | 3} | |
2806 | ||
2807 | static const struct regname reg_names[] = { | |
2808 | GENERIC_REGISTER_NUMBERS, | |
2809 | FPU_REGISTER_NAMES, | |
2810 | FPU_CONDITION_CODE_NAMES, | |
2811 | COPROC_CONDITION_CODE_NAMES, | |
2812 | ||
2813 | /* The $txx registers depends on the abi, | |
2814 | these will be added later into the symbol table from | |
3739860c | 2815 | one of the tables below once mips_abi is set after |
707bfff6 TS |
2816 | parsing of arguments from the command line. */ |
2817 | SYMBOLIC_REGISTER_NAMES, | |
2818 | ||
2819 | MIPS16_SPECIAL_REGISTER_NAMES, | |
2820 | MDMX_VECTOR_REGISTER_NAMES, | |
14daeee3 RS |
2821 | R5900_I_NAMES, |
2822 | R5900_Q_NAMES, | |
2823 | R5900_R_NAMES, | |
2824 | R5900_ACC_NAMES, | |
707bfff6 TS |
2825 | MIPS_DSP_ACCUMULATOR_NAMES, |
2826 | {0, 0} | |
2827 | }; | |
2828 | ||
2829 | static const struct regname reg_names_o32[] = { | |
2830 | O32_SYMBOLIC_REGISTER_NAMES, | |
2831 | {0, 0} | |
2832 | }; | |
2833 | ||
2834 | static const struct regname reg_names_n32n64[] = { | |
2835 | N32N64_SYMBOLIC_REGISTER_NAMES, | |
2836 | {0, 0} | |
2837 | }; | |
2838 | ||
a92713e6 RS |
2839 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
2840 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one | |
2841 | of these register symbols, return the associated vector register, | |
2842 | otherwise return SYMVAL itself. */ | |
df58fc94 | 2843 | |
a92713e6 RS |
2844 | static unsigned int |
2845 | mips_prefer_vec_regno (unsigned int symval) | |
707bfff6 | 2846 | { |
a92713e6 RS |
2847 | if ((symval & -2) == (RTYPE_GP | 2)) |
2848 | return RTYPE_VEC | (symval & 1); | |
2849 | return symval; | |
2850 | } | |
2851 | ||
14daeee3 RS |
2852 | /* Return true if string [S, E) is a valid register name, storing its |
2853 | symbol value in *SYMVAL_PTR if so. */ | |
a92713e6 RS |
2854 | |
2855 | static bfd_boolean | |
14daeee3 | 2856 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
a92713e6 | 2857 | { |
707bfff6 | 2858 | char save_c; |
14daeee3 | 2859 | symbolS *symbol; |
707bfff6 TS |
2860 | |
2861 | /* Terminate name. */ | |
2862 | save_c = *e; | |
2863 | *e = '\0'; | |
2864 | ||
a92713e6 RS |
2865 | /* Look up the name. */ |
2866 | symbol = symbol_find (s); | |
2867 | *e = save_c; | |
2868 | ||
2869 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) | |
2870 | return FALSE; | |
2871 | ||
14daeee3 RS |
2872 | *symval_ptr = S_GET_VALUE (symbol); |
2873 | return TRUE; | |
2874 | } | |
2875 | ||
2876 | /* Return true if the string at *SPTR is a valid register name. Allow it | |
2877 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR | |
2878 | is nonnull. | |
2879 | ||
2880 | When returning true, move *SPTR past the register, store the | |
2881 | register's symbol value in *SYMVAL_PTR and the channel mask in | |
2882 | *CHANNELS_PTR (if nonnull). The symbol value includes the register | |
2883 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask | |
2884 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ | |
2885 | ||
2886 | static bfd_boolean | |
2887 | mips_parse_register (char **sptr, unsigned int *symval_ptr, | |
2888 | unsigned int *channels_ptr) | |
2889 | { | |
2890 | char *s, *e, *m; | |
2891 | const char *q; | |
2892 | unsigned int channels, symval, bit; | |
2893 | ||
2894 | /* Find end of name. */ | |
2895 | s = e = *sptr; | |
2896 | if (is_name_beginner (*e)) | |
2897 | ++e; | |
2898 | while (is_part_of_name (*e)) | |
2899 | ++e; | |
2900 | ||
2901 | channels = 0; | |
2902 | if (!mips_parse_register_1 (s, e, &symval)) | |
2903 | { | |
2904 | if (!channels_ptr) | |
2905 | return FALSE; | |
2906 | ||
2907 | /* Eat characters from the end of the string that are valid | |
2908 | channel suffixes. The preceding register must be $ACC or | |
2909 | end with a digit, so there is no ambiguity. */ | |
2910 | bit = 1; | |
2911 | m = e; | |
2912 | for (q = "wzyx"; *q; q++, bit <<= 1) | |
2913 | if (m > s && m[-1] == *q) | |
2914 | { | |
2915 | --m; | |
2916 | channels |= bit; | |
2917 | } | |
2918 | ||
2919 | if (channels == 0 | |
2920 | || !mips_parse_register_1 (s, m, &symval) | |
2921 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) | |
2922 | return FALSE; | |
2923 | } | |
2924 | ||
a92713e6 | 2925 | *sptr = e; |
14daeee3 RS |
2926 | *symval_ptr = symval; |
2927 | if (channels_ptr) | |
2928 | *channels_ptr = channels; | |
a92713e6 RS |
2929 | return TRUE; |
2930 | } | |
2931 | ||
2932 | /* Check if SPTR points at a valid register specifier according to TYPES. | |
2933 | If so, then return 1, advance S to consume the specifier and store | |
2934 | the register's number in REGNOP, otherwise return 0. */ | |
2935 | ||
2936 | static int | |
2937 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) | |
2938 | { | |
2939 | unsigned int regno; | |
2940 | ||
14daeee3 | 2941 | if (mips_parse_register (s, ®no, NULL)) |
707bfff6 | 2942 | { |
a92713e6 RS |
2943 | if (types & RTYPE_VEC) |
2944 | regno = mips_prefer_vec_regno (regno); | |
2945 | if (regno & types) | |
2946 | regno &= RNUM_MASK; | |
2947 | else | |
2948 | regno = ~0; | |
707bfff6 | 2949 | } |
a92713e6 | 2950 | else |
707bfff6 | 2951 | { |
a92713e6 | 2952 | if (types & RWARN) |
1661c76c | 2953 | as_warn (_("unrecognized register name `%s'"), *s); |
a92713e6 | 2954 | regno = ~0; |
707bfff6 | 2955 | } |
707bfff6 | 2956 | if (regnop) |
a92713e6 RS |
2957 | *regnop = regno; |
2958 | return regno <= RNUM_MASK; | |
707bfff6 TS |
2959 | } |
2960 | ||
14daeee3 RS |
2961 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
2962 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ | |
2963 | ||
2964 | static char * | |
2965 | mips_parse_vu0_channels (char *s, unsigned int *channels) | |
2966 | { | |
2967 | unsigned int i; | |
2968 | ||
2969 | *channels = 0; | |
2970 | for (i = 0; i < 4; i++) | |
2971 | if (*s == "xyzw"[i]) | |
2972 | { | |
2973 | *channels |= 1 << (3 - i); | |
2974 | ++s; | |
2975 | } | |
2976 | return s; | |
2977 | } | |
2978 | ||
a92713e6 RS |
2979 | /* Token types for parsed operand lists. */ |
2980 | enum mips_operand_token_type { | |
2981 | /* A plain register, e.g. $f2. */ | |
2982 | OT_REG, | |
df58fc94 | 2983 | |
14daeee3 RS |
2984 | /* A 4-bit XYZW channel mask. */ |
2985 | OT_CHANNELS, | |
2986 | ||
56d438b1 CF |
2987 | /* A constant vector index, e.g. [1]. */ |
2988 | OT_INTEGER_INDEX, | |
2989 | ||
2990 | /* A register vector index, e.g. [$2]. */ | |
2991 | OT_REG_INDEX, | |
df58fc94 | 2992 | |
a92713e6 RS |
2993 | /* A continuous range of registers, e.g. $s0-$s4. */ |
2994 | OT_REG_RANGE, | |
2995 | ||
2996 | /* A (possibly relocated) expression. */ | |
2997 | OT_INTEGER, | |
2998 | ||
2999 | /* A floating-point value. */ | |
3000 | OT_FLOAT, | |
3001 | ||
3002 | /* A single character. This can be '(', ')' or ',', but '(' only appears | |
3003 | before OT_REGs. */ | |
3004 | OT_CHAR, | |
3005 | ||
14daeee3 RS |
3006 | /* A doubled character, either "--" or "++". */ |
3007 | OT_DOUBLE_CHAR, | |
3008 | ||
a92713e6 RS |
3009 | /* The end of the operand list. */ |
3010 | OT_END | |
3011 | }; | |
3012 | ||
3013 | /* A parsed operand token. */ | |
3014 | struct mips_operand_token | |
3015 | { | |
3016 | /* The type of token. */ | |
3017 | enum mips_operand_token_type type; | |
3018 | union | |
3019 | { | |
56d438b1 | 3020 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
a92713e6 RS |
3021 | unsigned int regno; |
3022 | ||
14daeee3 RS |
3023 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
3024 | unsigned int channels; | |
3025 | ||
56d438b1 CF |
3026 | /* The integer value of an OT_INTEGER_INDEX. */ |
3027 | addressT index; | |
a92713e6 RS |
3028 | |
3029 | /* The two register symbol values involved in an OT_REG_RANGE. */ | |
3030 | struct { | |
3031 | unsigned int regno1; | |
3032 | unsigned int regno2; | |
3033 | } reg_range; | |
3034 | ||
3035 | /* The value of an OT_INTEGER. The value is represented as an | |
3036 | expression and the relocation operators that were applied to | |
3037 | that expression. The reloc entries are BFD_RELOC_UNUSED if no | |
3038 | relocation operators were used. */ | |
3039 | struct { | |
3040 | expressionS value; | |
3041 | bfd_reloc_code_real_type relocs[3]; | |
3042 | } integer; | |
3043 | ||
3044 | /* The binary data for an OT_FLOAT constant, and the number of bytes | |
3045 | in the constant. */ | |
3046 | struct { | |
3047 | unsigned char data[8]; | |
3048 | int length; | |
3049 | } flt; | |
3050 | ||
14daeee3 | 3051 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
a92713e6 RS |
3052 | char ch; |
3053 | } u; | |
3054 | }; | |
3055 | ||
3056 | /* An obstack used to construct lists of mips_operand_tokens. */ | |
3057 | static struct obstack mips_operand_tokens; | |
3058 | ||
3059 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ | |
3060 | ||
3061 | static void | |
3062 | mips_add_token (struct mips_operand_token *token, | |
3063 | enum mips_operand_token_type type) | |
3064 | { | |
3065 | token->type = type; | |
3066 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); | |
3067 | } | |
3068 | ||
3069 | /* Check whether S is '(' followed by a register name. Add OT_CHAR | |
3070 | and OT_REG tokens for them if so, and return a pointer to the first | |
3071 | unconsumed character. Return null otherwise. */ | |
3072 | ||
3073 | static char * | |
3074 | mips_parse_base_start (char *s) | |
3075 | { | |
3076 | struct mips_operand_token token; | |
14daeee3 RS |
3077 | unsigned int regno, channels; |
3078 | bfd_boolean decrement_p; | |
df58fc94 | 3079 | |
a92713e6 RS |
3080 | if (*s != '(') |
3081 | return 0; | |
3082 | ||
3083 | ++s; | |
3084 | SKIP_SPACE_TABS (s); | |
14daeee3 RS |
3085 | |
3086 | /* Only match "--" as part of a base expression. In other contexts "--X" | |
3087 | is a double negative. */ | |
3088 | decrement_p = (s[0] == '-' && s[1] == '-'); | |
3089 | if (decrement_p) | |
3090 | { | |
3091 | s += 2; | |
3092 | SKIP_SPACE_TABS (s); | |
3093 | } | |
3094 | ||
3095 | /* Allow a channel specifier because that leads to better error messages | |
3096 | than treating something like "$vf0x++" as an expression. */ | |
3097 | if (!mips_parse_register (&s, ®no, &channels)) | |
a92713e6 RS |
3098 | return 0; |
3099 | ||
3100 | token.u.ch = '('; | |
3101 | mips_add_token (&token, OT_CHAR); | |
3102 | ||
14daeee3 RS |
3103 | if (decrement_p) |
3104 | { | |
3105 | token.u.ch = '-'; | |
3106 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3107 | } | |
3108 | ||
a92713e6 RS |
3109 | token.u.regno = regno; |
3110 | mips_add_token (&token, OT_REG); | |
3111 | ||
14daeee3 RS |
3112 | if (channels) |
3113 | { | |
3114 | token.u.channels = channels; | |
3115 | mips_add_token (&token, OT_CHANNELS); | |
3116 | } | |
3117 | ||
3118 | /* For consistency, only match "++" as part of base expressions too. */ | |
3119 | SKIP_SPACE_TABS (s); | |
3120 | if (s[0] == '+' && s[1] == '+') | |
3121 | { | |
3122 | s += 2; | |
3123 | token.u.ch = '+'; | |
3124 | mips_add_token (&token, OT_DOUBLE_CHAR); | |
3125 | } | |
3126 | ||
a92713e6 RS |
3127 | return s; |
3128 | } | |
3129 | ||
3130 | /* Parse one or more tokens from S. Return a pointer to the first | |
3131 | unconsumed character on success. Return null if an error was found | |
3132 | and store the error text in insn_error. FLOAT_FORMAT is as for | |
3133 | mips_parse_arguments. */ | |
3134 | ||
3135 | static char * | |
3136 | mips_parse_argument_token (char *s, char float_format) | |
3137 | { | |
6d4af3c2 AM |
3138 | char *end, *save_in; |
3139 | const char *err; | |
14daeee3 | 3140 | unsigned int regno1, regno2, channels; |
a92713e6 RS |
3141 | struct mips_operand_token token; |
3142 | ||
3143 | /* First look for "($reg", since we want to treat that as an | |
3144 | OT_CHAR and OT_REG rather than an expression. */ | |
3145 | end = mips_parse_base_start (s); | |
3146 | if (end) | |
3147 | return end; | |
3148 | ||
3149 | /* Handle other characters that end up as OT_CHARs. */ | |
3150 | if (*s == ')' || *s == ',') | |
3151 | { | |
3152 | token.u.ch = *s; | |
3153 | mips_add_token (&token, OT_CHAR); | |
3154 | ++s; | |
3155 | return s; | |
3156 | } | |
3157 | ||
3158 | /* Handle tokens that start with a register. */ | |
14daeee3 | 3159 | if (mips_parse_register (&s, ®no1, &channels)) |
df58fc94 | 3160 | { |
14daeee3 RS |
3161 | if (channels) |
3162 | { | |
3163 | /* A register and a VU0 channel suffix. */ | |
3164 | token.u.regno = regno1; | |
3165 | mips_add_token (&token, OT_REG); | |
3166 | ||
3167 | token.u.channels = channels; | |
3168 | mips_add_token (&token, OT_CHANNELS); | |
3169 | return s; | |
3170 | } | |
3171 | ||
a92713e6 RS |
3172 | SKIP_SPACE_TABS (s); |
3173 | if (*s == '-') | |
df58fc94 | 3174 | { |
a92713e6 RS |
3175 | /* A register range. */ |
3176 | ++s; | |
3177 | SKIP_SPACE_TABS (s); | |
14daeee3 | 3178 | if (!mips_parse_register (&s, ®no2, NULL)) |
a92713e6 | 3179 | { |
1661c76c | 3180 | set_insn_error (0, _("invalid register range")); |
a92713e6 RS |
3181 | return 0; |
3182 | } | |
df58fc94 | 3183 | |
a92713e6 RS |
3184 | token.u.reg_range.regno1 = regno1; |
3185 | token.u.reg_range.regno2 = regno2; | |
3186 | mips_add_token (&token, OT_REG_RANGE); | |
3187 | return s; | |
3188 | } | |
a92713e6 | 3189 | |
56d438b1 CF |
3190 | /* Add the register itself. */ |
3191 | token.u.regno = regno1; | |
3192 | mips_add_token (&token, OT_REG); | |
3193 | ||
3194 | /* Check for a vector index. */ | |
3195 | if (*s == '[') | |
3196 | { | |
a92713e6 RS |
3197 | ++s; |
3198 | SKIP_SPACE_TABS (s); | |
56d438b1 CF |
3199 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
3200 | mips_add_token (&token, OT_REG_INDEX); | |
3201 | else | |
a92713e6 | 3202 | { |
56d438b1 CF |
3203 | expressionS element; |
3204 | ||
3205 | my_getExpression (&element, s); | |
3206 | if (element.X_op != O_constant) | |
3207 | { | |
3208 | set_insn_error (0, _("vector element must be constant")); | |
3209 | return 0; | |
3210 | } | |
3211 | s = expr_end; | |
3212 | token.u.index = element.X_add_number; | |
3213 | mips_add_token (&token, OT_INTEGER_INDEX); | |
a92713e6 | 3214 | } |
a92713e6 RS |
3215 | SKIP_SPACE_TABS (s); |
3216 | if (*s != ']') | |
3217 | { | |
1661c76c | 3218 | set_insn_error (0, _("missing `]'")); |
a92713e6 RS |
3219 | return 0; |
3220 | } | |
3221 | ++s; | |
df58fc94 | 3222 | } |
a92713e6 | 3223 | return s; |
df58fc94 RS |
3224 | } |
3225 | ||
a92713e6 RS |
3226 | if (float_format) |
3227 | { | |
3228 | /* First try to treat expressions as floats. */ | |
3229 | save_in = input_line_pointer; | |
3230 | input_line_pointer = s; | |
3231 | err = md_atof (float_format, (char *) token.u.flt.data, | |
3232 | &token.u.flt.length); | |
3233 | end = input_line_pointer; | |
3234 | input_line_pointer = save_in; | |
3235 | if (err && *err) | |
3236 | { | |
e3de51ce | 3237 | set_insn_error (0, err); |
a92713e6 RS |
3238 | return 0; |
3239 | } | |
3240 | if (s != end) | |
3241 | { | |
3242 | mips_add_token (&token, OT_FLOAT); | |
3243 | return end; | |
3244 | } | |
3245 | } | |
3246 | ||
3247 | /* Treat everything else as an integer expression. */ | |
3248 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; | |
3249 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; | |
3250 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; | |
3251 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); | |
3252 | s = expr_end; | |
3253 | mips_add_token (&token, OT_INTEGER); | |
3254 | return s; | |
3255 | } | |
3256 | ||
3257 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' | |
3258 | if expressions should be treated as 32-bit floating-point constants, | |
3259 | 'd' if they should be treated as 64-bit floating-point constants, | |
3260 | or 0 if they should be treated as integer expressions (the usual case). | |
3261 | ||
3262 | Return a list of tokens on success, otherwise return 0. The caller | |
3263 | must obstack_free the list after use. */ | |
3264 | ||
3265 | static struct mips_operand_token * | |
3266 | mips_parse_arguments (char *s, char float_format) | |
3267 | { | |
3268 | struct mips_operand_token token; | |
3269 | ||
3270 | SKIP_SPACE_TABS (s); | |
3271 | while (*s) | |
3272 | { | |
3273 | s = mips_parse_argument_token (s, float_format); | |
3274 | if (!s) | |
3275 | { | |
3276 | obstack_free (&mips_operand_tokens, | |
3277 | obstack_finish (&mips_operand_tokens)); | |
3278 | return 0; | |
3279 | } | |
3280 | SKIP_SPACE_TABS (s); | |
3281 | } | |
3282 | mips_add_token (&token, OT_END); | |
3283 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); | |
df58fc94 RS |
3284 | } |
3285 | ||
d301a56b RS |
3286 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
3287 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ | |
037b32b9 AN |
3288 | |
3289 | static bfd_boolean | |
f79e2745 | 3290 | is_opcode_valid (const struct mips_opcode *mo) |
037b32b9 AN |
3291 | { |
3292 | int isa = mips_opts.isa; | |
846ef2d0 | 3293 | int ase = mips_opts.ase; |
037b32b9 | 3294 | int fp_s, fp_d; |
c6278170 | 3295 | unsigned int i; |
037b32b9 | 3296 | |
be0fcbee | 3297 | if (ISA_HAS_64BIT_REGS (isa)) |
c6278170 RS |
3298 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
3299 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3300 | ase |= mips_ases[i].flags64; | |
037b32b9 | 3301 | |
d301a56b | 3302 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
037b32b9 AN |
3303 | return FALSE; |
3304 | ||
3305 | /* Check whether the instruction or macro requires single-precision or | |
3306 | double-precision floating-point support. Note that this information is | |
3307 | stored differently in the opcode table for insns and macros. */ | |
3308 | if (mo->pinfo == INSN_MACRO) | |
3309 | { | |
3310 | fp_s = mo->pinfo2 & INSN2_M_FP_S; | |
3311 | fp_d = mo->pinfo2 & INSN2_M_FP_D; | |
3312 | } | |
3313 | else | |
3314 | { | |
3315 | fp_s = mo->pinfo & FP_S; | |
3316 | fp_d = mo->pinfo & FP_D; | |
3317 | } | |
3318 | ||
3319 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) | |
3320 | return FALSE; | |
3321 | ||
3322 | if (fp_s && mips_opts.soft_float) | |
3323 | return FALSE; | |
3324 | ||
3325 | return TRUE; | |
3326 | } | |
3327 | ||
3328 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently | |
3329 | selected ISA and architecture. */ | |
3330 | ||
3331 | static bfd_boolean | |
3332 | is_opcode_valid_16 (const struct mips_opcode *mo) | |
3333 | { | |
25499ac7 MR |
3334 | int isa = mips_opts.isa; |
3335 | int ase = mips_opts.ase; | |
3336 | unsigned int i; | |
3337 | ||
3338 | if (ISA_HAS_64BIT_REGS (isa)) | |
3339 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
3340 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) | |
3341 | ase |= mips_ases[i].flags64; | |
3342 | ||
3343 | return opcode_is_member (mo, isa, ase, mips_opts.arch); | |
037b32b9 AN |
3344 | } |
3345 | ||
df58fc94 | 3346 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
7fd53920 MR |
3347 | explicitly requested. Always TRUE in the standard MIPS mode. |
3348 | Use is_size_valid_16 for MIPS16 opcodes. */ | |
df58fc94 RS |
3349 | |
3350 | static bfd_boolean | |
3351 | is_size_valid (const struct mips_opcode *mo) | |
3352 | { | |
3353 | if (!mips_opts.micromips) | |
3354 | return TRUE; | |
3355 | ||
833794fc MR |
3356 | if (mips_opts.insn32) |
3357 | { | |
3358 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) | |
3359 | return FALSE; | |
3360 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) | |
3361 | return FALSE; | |
3362 | } | |
df58fc94 RS |
3363 | if (!forced_insn_length) |
3364 | return TRUE; | |
3365 | if (mo->pinfo == INSN_MACRO) | |
3366 | return FALSE; | |
3367 | return forced_insn_length == micromips_insn_length (mo); | |
3368 | } | |
3369 | ||
7fd53920 MR |
3370 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
3371 | explicitly requested. */ | |
3372 | ||
3373 | static bfd_boolean | |
3374 | is_size_valid_16 (const struct mips_opcode *mo) | |
3375 | { | |
3376 | if (!forced_insn_length) | |
3377 | return TRUE; | |
3378 | if (mo->pinfo == INSN_MACRO) | |
3379 | return FALSE; | |
3380 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) | |
3381 | return FALSE; | |
0674ee5d MR |
3382 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
3383 | return FALSE; | |
7fd53920 MR |
3384 | return TRUE; |
3385 | } | |
3386 | ||
df58fc94 | 3387 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
e64af278 MR |
3388 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
3389 | ||
3390 | We don't accept macros in 16-bit delay slots to avoid a case where | |
3391 | a macro expansion fails because it relies on a preceding 32-bit real | |
3392 | instruction to have matched and does not handle the operands correctly. | |
3393 | The only macros that may expand to 16-bit instructions are JAL that | |
3394 | cannot be placed in a delay slot anyway, and corner cases of BALIGN | |
3395 | and BGT (that likewise cannot be placed in a delay slot) that decay to | |
3396 | a NOP. In all these cases the macros precede any corresponding real | |
3397 | instruction definitions in the opcode table, so they will match in the | |
3398 | second pass where the size of the delay slot is ignored and therefore | |
3399 | produce correct code. */ | |
df58fc94 RS |
3400 | |
3401 | static bfd_boolean | |
3402 | is_delay_slot_valid (const struct mips_opcode *mo) | |
3403 | { | |
3404 | if (!mips_opts.micromips) | |
3405 | return TRUE; | |
3406 | ||
3407 | if (mo->pinfo == INSN_MACRO) | |
c06dec14 | 3408 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
df58fc94 RS |
3409 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
3410 | && micromips_insn_length (mo) != 4) | |
3411 | return FALSE; | |
3412 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 | |
3413 | && micromips_insn_length (mo) != 2) | |
3414 | return FALSE; | |
3415 | ||
3416 | return TRUE; | |
3417 | } | |
3418 | ||
fc76e730 RS |
3419 | /* For consistency checking, verify that all bits of OPCODE are specified |
3420 | either by the match/mask part of the instruction definition, or by the | |
3421 | operand list. Also build up a list of operands in OPERANDS. | |
3422 | ||
3423 | INSN_BITS says which bits of the instruction are significant. | |
3424 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND | |
3425 | provides the mips_operand description of each operand. DECODE_OPERAND | |
3426 | is null for MIPS16 instructions. */ | |
ab902481 RS |
3427 | |
3428 | static int | |
3429 | validate_mips_insn (const struct mips_opcode *opcode, | |
3430 | unsigned long insn_bits, | |
fc76e730 RS |
3431 | const struct mips_operand *(*decode_operand) (const char *), |
3432 | struct mips_operand_array *operands) | |
ab902481 RS |
3433 | { |
3434 | const char *s; | |
fc76e730 | 3435 | unsigned long used_bits, doubled, undefined, opno, mask; |
ab902481 RS |
3436 | const struct mips_operand *operand; |
3437 | ||
fc76e730 RS |
3438 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
3439 | if ((mask & opcode->match) != opcode->match) | |
ab902481 RS |
3440 | { |
3441 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), | |
3442 | opcode->name, opcode->args); | |
3443 | return 0; | |
3444 | } | |
3445 | used_bits = 0; | |
fc76e730 | 3446 | opno = 0; |
14daeee3 RS |
3447 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
3448 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); | |
ab902481 RS |
3449 | for (s = opcode->args; *s; ++s) |
3450 | switch (*s) | |
3451 | { | |
3452 | case ',': | |
3453 | case '(': | |
3454 | case ')': | |
3455 | break; | |
3456 | ||
14daeee3 RS |
3457 | case '#': |
3458 | s++; | |
3459 | break; | |
3460 | ||
ab902481 | 3461 | default: |
fc76e730 | 3462 | if (!decode_operand) |
7fd53920 | 3463 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
fc76e730 RS |
3464 | else |
3465 | operand = decode_operand (s); | |
3466 | if (!operand && opcode->pinfo != INSN_MACRO) | |
ab902481 RS |
3467 | { |
3468 | as_bad (_("internal: unknown operand type: %s %s"), | |
3469 | opcode->name, opcode->args); | |
3470 | return 0; | |
3471 | } | |
fc76e730 RS |
3472 | gas_assert (opno < MAX_OPERANDS); |
3473 | operands->operand[opno] = operand; | |
25499ac7 MR |
3474 | if (!decode_operand && operand |
3475 | && operand->type == OP_INT && operand->lsb == 0 | |
3476 | && mips_opcode_32bit_p (opcode)) | |
3477 | used_bits |= mips16_immed_extend (-1, operand->size); | |
3478 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) | |
fc76e730 | 3479 | { |
14daeee3 | 3480 | used_bits = mips_insert_operand (operand, used_bits, -1); |
fc76e730 RS |
3481 | if (operand->type == OP_MDMX_IMM_REG) |
3482 | /* Bit 5 is the format selector (OB vs QH). The opcode table | |
3483 | has separate entries for each format. */ | |
3484 | used_bits &= ~(1 << (operand->lsb + 5)); | |
3485 | if (operand->type == OP_ENTRY_EXIT_LIST) | |
3486 | used_bits &= ~(mask & 0x700); | |
38bf472a MR |
3487 | /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous |
3488 | operand field that cannot be fully described with LSB/SIZE. */ | |
3489 | if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6) | |
3490 | used_bits &= ~0x6000; | |
fc76e730 | 3491 | } |
ab902481 | 3492 | /* Skip prefix characters. */ |
7361da2c | 3493 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
ab902481 | 3494 | ++s; |
fc76e730 | 3495 | opno += 1; |
ab902481 RS |
3496 | break; |
3497 | } | |
fc76e730 | 3498 | doubled = used_bits & mask & insn_bits; |
ab902481 RS |
3499 | if (doubled) |
3500 | { | |
3501 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" | |
3502 | " %s %s"), doubled, opcode->name, opcode->args); | |
3503 | return 0; | |
3504 | } | |
fc76e730 | 3505 | used_bits |= mask; |
ab902481 | 3506 | undefined = ~used_bits & insn_bits; |
fc76e730 | 3507 | if (opcode->pinfo != INSN_MACRO && undefined) |
ab902481 RS |
3508 | { |
3509 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), | |
3510 | undefined, opcode->name, opcode->args); | |
3511 | return 0; | |
3512 | } | |
3513 | used_bits &= ~insn_bits; | |
3514 | if (used_bits) | |
3515 | { | |
3516 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), | |
3517 | used_bits, opcode->name, opcode->args); | |
3518 | return 0; | |
3519 | } | |
3520 | return 1; | |
3521 | } | |
3522 | ||
fc76e730 RS |
3523 | /* The MIPS16 version of validate_mips_insn. */ |
3524 | ||
3525 | static int | |
3526 | validate_mips16_insn (const struct mips_opcode *opcode, | |
3527 | struct mips_operand_array *operands) | |
3528 | { | |
7fd53920 | 3529 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
fc76e730 | 3530 | |
7fd53920 | 3531 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
fc76e730 RS |
3532 | } |
3533 | ||
ab902481 RS |
3534 | /* The microMIPS version of validate_mips_insn. */ |
3535 | ||
3536 | static int | |
fc76e730 RS |
3537 | validate_micromips_insn (const struct mips_opcode *opc, |
3538 | struct mips_operand_array *operands) | |
ab902481 RS |
3539 | { |
3540 | unsigned long insn_bits; | |
3541 | unsigned long major; | |
3542 | unsigned int length; | |
3543 | ||
fc76e730 RS |
3544 | if (opc->pinfo == INSN_MACRO) |
3545 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, | |
3546 | operands); | |
3547 | ||
ab902481 RS |
3548 | length = micromips_insn_length (opc); |
3549 | if (length != 2 && length != 4) | |
3550 | { | |
1661c76c | 3551 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
ab902481 RS |
3552 | "%s %s"), length, opc->name, opc->args); |
3553 | return 0; | |
3554 | } | |
3555 | major = opc->match >> (10 + 8 * (length - 2)); | |
3556 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) | |
3557 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) | |
3558 | { | |
1661c76c | 3559 | as_bad (_("internal error: bad microMIPS opcode " |
ab902481 RS |
3560 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
3561 | return 0; | |
3562 | } | |
3563 | ||
3564 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ | |
3565 | insn_bits = 1 << 4 * length; | |
3566 | insn_bits <<= 4 * length; | |
3567 | insn_bits -= 1; | |
fc76e730 RS |
3568 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
3569 | operands); | |
ab902481 RS |
3570 | } |
3571 | ||
707bfff6 TS |
3572 | /* This function is called once, at assembler startup time. It should set up |
3573 | all the tables, etc. that the MD part of the assembler will need. */ | |
156c2f8b | 3574 | |
252b5132 | 3575 | void |
17a2f251 | 3576 | md_begin (void) |
252b5132 | 3577 | { |
3994f87e | 3578 | const char *retval = NULL; |
156c2f8b | 3579 | int i = 0; |
252b5132 | 3580 | int broken = 0; |
1f25f5d3 | 3581 | |
0a44bf69 RS |
3582 | if (mips_pic != NO_PIC) |
3583 | { | |
3584 | if (g_switch_seen && g_switch_value != 0) | |
3585 | as_bad (_("-G may not be used in position-independent code")); | |
3586 | g_switch_value = 0; | |
3587 | } | |
00acd688 CM |
3588 | else if (mips_abicalls) |
3589 | { | |
3590 | if (g_switch_seen && g_switch_value != 0) | |
3591 | as_bad (_("-G may not be used with abicalls")); | |
3592 | g_switch_value = 0; | |
3593 | } | |
0a44bf69 | 3594 | |
0b35dfee | 3595 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
1661c76c | 3596 | as_warn (_("could not set architecture and machine")); |
252b5132 | 3597 | |
252b5132 RH |
3598 | op_hash = hash_new (); |
3599 | ||
fc76e730 | 3600 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
252b5132 RH |
3601 | for (i = 0; i < NUMOPCODES;) |
3602 | { | |
3603 | const char *name = mips_opcodes[i].name; | |
3604 | ||
17a2f251 | 3605 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
252b5132 RH |
3606 | if (retval != NULL) |
3607 | { | |
3608 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), | |
3609 | mips_opcodes[i].name, retval); | |
3610 | /* Probably a memory allocation problem? Give up now. */ | |
1661c76c | 3611 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3612 | } |
3613 | do | |
3614 | { | |
fc76e730 RS |
3615 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
3616 | decode_mips_operand, &mips_operands[i])) | |
3617 | broken = 1; | |
3618 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) | |
252b5132 | 3619 | { |
fc76e730 RS |
3620 | create_insn (&nop_insn, mips_opcodes + i); |
3621 | if (mips_fix_loongson2f_nop) | |
3622 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; | |
3623 | nop_insn.fixed_p = 1; | |
252b5132 RH |
3624 | } |
3625 | ++i; | |
3626 | } | |
3627 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); | |
3628 | } | |
3629 | ||
3630 | mips16_op_hash = hash_new (); | |
fc76e730 RS |
3631 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
3632 | bfd_mips16_num_opcodes); | |
252b5132 RH |
3633 | |
3634 | i = 0; | |
3635 | while (i < bfd_mips16_num_opcodes) | |
3636 | { | |
3637 | const char *name = mips16_opcodes[i].name; | |
3638 | ||
17a2f251 | 3639 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
252b5132 RH |
3640 | if (retval != NULL) |
3641 | as_fatal (_("internal: can't hash `%s': %s"), | |
3642 | mips16_opcodes[i].name, retval); | |
3643 | do | |
3644 | { | |
fc76e730 RS |
3645 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
3646 | broken = 1; | |
1e915849 RS |
3647 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
3648 | { | |
3649 | create_insn (&mips16_nop_insn, mips16_opcodes + i); | |
3650 | mips16_nop_insn.fixed_p = 1; | |
3651 | } | |
252b5132 RH |
3652 | ++i; |
3653 | } | |
3654 | while (i < bfd_mips16_num_opcodes | |
3655 | && strcmp (mips16_opcodes[i].name, name) == 0); | |
3656 | } | |
3657 | ||
df58fc94 | 3658 | micromips_op_hash = hash_new (); |
fc76e730 RS |
3659 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
3660 | bfd_micromips_num_opcodes); | |
df58fc94 RS |
3661 | |
3662 | i = 0; | |
3663 | while (i < bfd_micromips_num_opcodes) | |
3664 | { | |
3665 | const char *name = micromips_opcodes[i].name; | |
3666 | ||
3667 | retval = hash_insert (micromips_op_hash, name, | |
3668 | (void *) µmips_opcodes[i]); | |
3669 | if (retval != NULL) | |
3670 | as_fatal (_("internal: can't hash `%s': %s"), | |
3671 | micromips_opcodes[i].name, retval); | |
3672 | do | |
fc76e730 RS |
3673 | { |
3674 | struct mips_cl_insn *micromips_nop_insn; | |
3675 | ||
3676 | if (!validate_micromips_insn (µmips_opcodes[i], | |
3677 | µmips_operands[i])) | |
3678 | broken = 1; | |
3679 | ||
3680 | if (micromips_opcodes[i].pinfo != INSN_MACRO) | |
3681 | { | |
3682 | if (micromips_insn_length (micromips_opcodes + i) == 2) | |
3683 | micromips_nop_insn = µmips_nop16_insn; | |
3684 | else if (micromips_insn_length (micromips_opcodes + i) == 4) | |
3685 | micromips_nop_insn = µmips_nop32_insn; | |
3686 | else | |
3687 | continue; | |
3688 | ||
3689 | if (micromips_nop_insn->insn_mo == NULL | |
3690 | && strcmp (name, "nop") == 0) | |
3691 | { | |
3692 | create_insn (micromips_nop_insn, micromips_opcodes + i); | |
3693 | micromips_nop_insn->fixed_p = 1; | |
3694 | } | |
3695 | } | |
3696 | } | |
df58fc94 RS |
3697 | while (++i < bfd_micromips_num_opcodes |
3698 | && strcmp (micromips_opcodes[i].name, name) == 0); | |
3699 | } | |
3700 | ||
252b5132 | 3701 | if (broken) |
1661c76c | 3702 | as_fatal (_("broken assembler, no assembly attempted")); |
252b5132 RH |
3703 | |
3704 | /* We add all the general register names to the symbol table. This | |
3705 | helps us detect invalid uses of them. */ | |
3739860c | 3706 | for (i = 0; reg_names[i].name; i++) |
707bfff6 | 3707 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
8fc4ee9b | 3708 | reg_names[i].num, /* & RNUM_MASK, */ |
707bfff6 TS |
3709 | &zero_address_frag)); |
3710 | if (HAVE_NEWABI) | |
3739860c | 3711 | for (i = 0; reg_names_n32n64[i].name; i++) |
707bfff6 | 3712 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
8fc4ee9b | 3713 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
252b5132 | 3714 | &zero_address_frag)); |
707bfff6 | 3715 | else |
3739860c | 3716 | for (i = 0; reg_names_o32[i].name; i++) |
707bfff6 | 3717 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
8fc4ee9b | 3718 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
6047c971 | 3719 | &zero_address_frag)); |
6047c971 | 3720 | |
14daeee3 RS |
3721 | for (i = 0; i < 32; i++) |
3722 | { | |
92fce9bd | 3723 | char regname[6]; |
14daeee3 RS |
3724 | |
3725 | /* R5900 VU0 floating-point register. */ | |
92fce9bd | 3726 | sprintf (regname, "$vf%d", i); |
14daeee3 RS |
3727 | symbol_table_insert (symbol_new (regname, reg_section, |
3728 | RTYPE_VF | i, &zero_address_frag)); | |
3729 | ||
3730 | /* R5900 VU0 integer register. */ | |
92fce9bd | 3731 | sprintf (regname, "$vi%d", i); |
14daeee3 RS |
3732 | symbol_table_insert (symbol_new (regname, reg_section, |
3733 | RTYPE_VI | i, &zero_address_frag)); | |
3734 | ||
56d438b1 | 3735 | /* MSA register. */ |
92fce9bd | 3736 | sprintf (regname, "$w%d", i); |
56d438b1 CF |
3737 | symbol_table_insert (symbol_new (regname, reg_section, |
3738 | RTYPE_MSA | i, &zero_address_frag)); | |
14daeee3 RS |
3739 | } |
3740 | ||
a92713e6 RS |
3741 | obstack_init (&mips_operand_tokens); |
3742 | ||
7d10b47d | 3743 | mips_no_prev_insn (); |
252b5132 RH |
3744 | |
3745 | mips_gprmask = 0; | |
3746 | mips_cprmask[0] = 0; | |
3747 | mips_cprmask[1] = 0; | |
3748 | mips_cprmask[2] = 0; | |
3749 | mips_cprmask[3] = 0; | |
3750 | ||
3751 | /* set the default alignment for the text section (2**2) */ | |
3752 | record_alignment (text_section, 2); | |
3753 | ||
4d0d148d | 3754 | bfd_set_gp_size (stdoutput, g_switch_value); |
252b5132 | 3755 | |
f3ded42a RS |
3756 | /* On a native system other than VxWorks, sections must be aligned |
3757 | to 16 byte boundaries. When configured for an embedded ELF | |
3758 | target, we don't bother. */ | |
3759 | if (strncmp (TARGET_OS, "elf", 3) != 0 | |
3760 | && strncmp (TARGET_OS, "vxworks", 7) != 0) | |
252b5132 | 3761 | { |
f3ded42a RS |
3762 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
3763 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); | |
3764 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); | |
3765 | } | |
252b5132 | 3766 | |
f3ded42a RS |
3767 | /* Create a .reginfo section for register masks and a .mdebug |
3768 | section for debugging information. */ | |
3769 | { | |
3770 | segT seg; | |
3771 | subsegT subseg; | |
3772 | flagword flags; | |
3773 | segT sec; | |
3774 | ||
3775 | seg = now_seg; | |
3776 | subseg = now_subseg; | |
3777 | ||
3778 | /* The ABI says this section should be loaded so that the | |
3779 | running program can access it. However, we don't load it | |
3780 | if we are configured for an embedded target */ | |
3781 | flags = SEC_READONLY | SEC_DATA; | |
3782 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
3783 | flags |= SEC_ALLOC | SEC_LOAD; | |
3784 | ||
3785 | if (mips_abi != N64_ABI) | |
252b5132 | 3786 | { |
f3ded42a | 3787 | sec = subseg_new (".reginfo", (subsegT) 0); |
bdaaa2e1 | 3788 | |
f3ded42a RS |
3789 | bfd_set_section_flags (stdoutput, sec, flags); |
3790 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); | |
252b5132 | 3791 | |
f3ded42a RS |
3792 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
3793 | } | |
3794 | else | |
3795 | { | |
3796 | /* The 64-bit ABI uses a .MIPS.options section rather than | |
3797 | .reginfo section. */ | |
3798 | sec = subseg_new (".MIPS.options", (subsegT) 0); | |
3799 | bfd_set_section_flags (stdoutput, sec, flags); | |
3800 | bfd_set_section_alignment (stdoutput, sec, 3); | |
252b5132 | 3801 | |
f3ded42a RS |
3802 | /* Set up the option header. */ |
3803 | { | |
3804 | Elf_Internal_Options opthdr; | |
3805 | char *f; | |
3806 | ||
3807 | opthdr.kind = ODK_REGINFO; | |
3808 | opthdr.size = (sizeof (Elf_External_Options) | |
3809 | + sizeof (Elf64_External_RegInfo)); | |
3810 | opthdr.section = 0; | |
3811 | opthdr.info = 0; | |
3812 | f = frag_more (sizeof (Elf_External_Options)); | |
3813 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, | |
3814 | (Elf_External_Options *) f); | |
3815 | ||
3816 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); | |
3817 | } | |
3818 | } | |
252b5132 | 3819 | |
351cdf24 MF |
3820 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
3821 | bfd_set_section_flags (stdoutput, sec, | |
3822 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); | |
3823 | bfd_set_section_alignment (stdoutput, sec, 3); | |
3824 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); | |
3825 | ||
f3ded42a RS |
3826 | if (ECOFF_DEBUGGING) |
3827 | { | |
3828 | sec = subseg_new (".mdebug", (subsegT) 0); | |
3829 | (void) bfd_set_section_flags (stdoutput, sec, | |
3830 | SEC_HAS_CONTENTS | SEC_READONLY); | |
3831 | (void) bfd_set_section_alignment (stdoutput, sec, 2); | |
252b5132 | 3832 | } |
f3ded42a RS |
3833 | else if (mips_flag_pdr) |
3834 | { | |
3835 | pdr_seg = subseg_new (".pdr", (subsegT) 0); | |
3836 | (void) bfd_set_section_flags (stdoutput, pdr_seg, | |
3837 | SEC_READONLY | SEC_RELOC | |
3838 | | SEC_DEBUGGING); | |
3839 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); | |
3840 | } | |
3841 | ||
3842 | subseg_set (seg, subseg); | |
3843 | } | |
252b5132 | 3844 | |
71400594 RS |
3845 | if (mips_fix_vr4120) |
3846 | init_vr4120_conflicts (); | |
252b5132 RH |
3847 | } |
3848 | ||
351cdf24 MF |
3849 | static inline void |
3850 | fpabi_incompatible_with (int fpabi, const char *what) | |
3851 | { | |
3852 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), | |
3853 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3854 | } | |
3855 | ||
3856 | static inline void | |
3857 | fpabi_requires (int fpabi, const char *what) | |
3858 | { | |
3859 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), | |
3860 | Tag_GNU_MIPS_ABI_FP, fpabi, what); | |
3861 | } | |
3862 | ||
3863 | /* Check -mabi and register sizes against the specified FP ABI. */ | |
3864 | static void | |
3865 | check_fpabi (int fpabi) | |
3866 | { | |
351cdf24 MF |
3867 | switch (fpabi) |
3868 | { | |
3869 | case Val_GNU_MIPS_ABI_FP_DOUBLE: | |
ea79f94a MF |
3870 | if (file_mips_opts.soft_float) |
3871 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3872 | else if (file_mips_opts.single_float) | |
3873 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3874 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
3875 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); | |
3876 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) | |
3877 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); | |
351cdf24 MF |
3878 | break; |
3879 | ||
3880 | case Val_GNU_MIPS_ABI_FP_XX: | |
3881 | if (mips_abi != O32_ABI) | |
3882 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3883 | else if (file_mips_opts.soft_float) |
3884 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3885 | else if (file_mips_opts.single_float) | |
3886 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3887 | else if (file_mips_opts.fp != 0) |
3888 | fpabi_requires (fpabi, "fp=xx"); | |
351cdf24 MF |
3889 | break; |
3890 | ||
3891 | case Val_GNU_MIPS_ABI_FP_64A: | |
3892 | case Val_GNU_MIPS_ABI_FP_64: | |
3893 | if (mips_abi != O32_ABI) | |
3894 | fpabi_requires (fpabi, "-mabi=32"); | |
ea79f94a MF |
3895 | else if (file_mips_opts.soft_float) |
3896 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3897 | else if (file_mips_opts.single_float) | |
3898 | fpabi_incompatible_with (fpabi, "singlefloat"); | |
351cdf24 MF |
3899 | else if (file_mips_opts.fp != 64) |
3900 | fpabi_requires (fpabi, "fp=64"); | |
3901 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) | |
3902 | fpabi_incompatible_with (fpabi, "nooddspreg"); | |
3903 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) | |
3904 | fpabi_requires (fpabi, "nooddspreg"); | |
351cdf24 MF |
3905 | break; |
3906 | ||
3907 | case Val_GNU_MIPS_ABI_FP_SINGLE: | |
3908 | if (file_mips_opts.soft_float) | |
3909 | fpabi_incompatible_with (fpabi, "softfloat"); | |
3910 | else if (!file_mips_opts.single_float) | |
3911 | fpabi_requires (fpabi, "singlefloat"); | |
3912 | break; | |
3913 | ||
3914 | case Val_GNU_MIPS_ABI_FP_SOFT: | |
3915 | if (!file_mips_opts.soft_float) | |
3916 | fpabi_requires (fpabi, "softfloat"); | |
3917 | break; | |
3918 | ||
3919 | case Val_GNU_MIPS_ABI_FP_OLD_64: | |
3920 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), | |
3921 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
3922 | break; | |
3923 | ||
3350cc01 CM |
3924 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
3925 | /* Silently ignore compatibility value. */ | |
3926 | break; | |
3927 | ||
351cdf24 MF |
3928 | default: |
3929 | as_warn (_(".gnu_attribute %d,%d is not a recognized" | |
3930 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); | |
3931 | break; | |
3932 | } | |
351cdf24 MF |
3933 | } |
3934 | ||
919731af | 3935 | /* Perform consistency checks on the current options. */ |
3936 | ||
3937 | static void | |
3938 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) | |
3939 | { | |
3940 | /* Check the size of integer registers agrees with the ABI and ISA. */ | |
3941 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) | |
3942 | as_bad (_("`gp=64' used with a 32-bit processor")); | |
3943 | else if (abi_checks | |
3944 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3945 | as_bad (_("`gp=32' used with a 64-bit ABI")); | |
3946 | else if (abi_checks | |
3947 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) | |
3948 | as_bad (_("`gp=64' used with a 32-bit ABI")); | |
3949 | ||
3950 | /* Check the size of the float registers agrees with the ABI and ISA. */ | |
3951 | switch (opts->fp) | |
3952 | { | |
351cdf24 MF |
3953 | case 0: |
3954 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) | |
3955 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); | |
3956 | else if (opts->single_float == 1) | |
3957 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); | |
3958 | break; | |
919731af | 3959 | case 64: |
3960 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) | |
3961 | as_bad (_("`fp=64' used with a 32-bit fpu")); | |
3962 | else if (abi_checks | |
3963 | && ABI_NEEDS_32BIT_REGS (mips_abi) | |
3964 | && !ISA_HAS_MXHC1 (opts->isa)) | |
3965 | as_warn (_("`fp=64' used with a 32-bit ABI")); | |
3966 | break; | |
3967 | case 32: | |
3968 | if (abi_checks | |
3969 | && ABI_NEEDS_64BIT_REGS (mips_abi)) | |
3970 | as_warn (_("`fp=32' used with a 64-bit ABI")); | |
5f4678bb | 3971 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
7361da2c | 3972 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
919731af | 3973 | break; |
3974 | default: | |
3975 | as_bad (_("Unknown size of floating point registers")); | |
3976 | break; | |
3977 | } | |
3978 | ||
351cdf24 MF |
3979 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
3980 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); | |
3981 | ||
919731af | 3982 | if (opts->micromips == 1 && opts->mips16 == 1) |
1357373c | 3983 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
5f4678bb | 3984 | else if (ISA_IS_R6 (opts->isa) |
7361da2c AB |
3985 | && (opts->micromips == 1 |
3986 | || opts->mips16 == 1)) | |
1357373c | 3987 | as_fatal (_("`%s' cannot be used with `%s'"), |
7361da2c | 3988 | opts->micromips ? "micromips" : "mips16", |
5f4678bb | 3989 | mips_cpu_info_from_isa (opts->isa)->name); |
7361da2c AB |
3990 | |
3991 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) | |
3992 | as_fatal (_("branch relaxation is not supported in `%s'"), | |
3993 | mips_cpu_info_from_isa (opts->isa)->name); | |
919731af | 3994 | } |
3995 | ||
3996 | /* Perform consistency checks on the module level options exactly once. | |
3997 | This is a deferred check that happens: | |
3998 | at the first .set directive | |
3999 | or, at the first pseudo op that generates code (inc .dc.a) | |
4000 | or, at the first instruction | |
4001 | or, at the end. */ | |
4002 | ||
4003 | static void | |
4004 | file_mips_check_options (void) | |
4005 | { | |
4006 | const struct mips_cpu_info *arch_info = 0; | |
4007 | ||
4008 | if (file_mips_opts_checked) | |
4009 | return; | |
4010 | ||
4011 | /* The following code determines the register size. | |
4012 | Similar code was added to GCC 3.3 (see override_options() in | |
4013 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
4014 | as much as possible. */ | |
4015 | ||
4016 | if (file_mips_opts.gp < 0) | |
4017 | { | |
4018 | /* Infer the integer register size from the ABI and processor. | |
4019 | Restrict ourselves to 32-bit registers if that's all the | |
4020 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
4021 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) | |
4022 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) | |
4023 | ? 32 : 64; | |
4024 | } | |
4025 | ||
4026 | if (file_mips_opts.fp < 0) | |
4027 | { | |
4028 | /* No user specified float register size. | |
4029 | ??? GAS treats single-float processors as though they had 64-bit | |
4030 | float registers (although it complains when double-precision | |
4031 | instructions are used). As things stand, saying they have 32-bit | |
4032 | registers would lead to spurious "register must be even" messages. | |
4033 | So here we assume float registers are never smaller than the | |
4034 | integer ones. */ | |
4035 | if (file_mips_opts.gp == 64) | |
4036 | /* 64-bit integer registers implies 64-bit float registers. */ | |
4037 | file_mips_opts.fp = 64; | |
4038 | else if ((file_mips_opts.ase & FP64_ASES) | |
4039 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) | |
4040 | /* Handle ASEs that require 64-bit float registers, if possible. */ | |
4041 | file_mips_opts.fp = 64; | |
7361da2c AB |
4042 | else if (ISA_IS_R6 (mips_opts.isa)) |
4043 | /* R6 implies 64-bit float registers. */ | |
4044 | file_mips_opts.fp = 64; | |
919731af | 4045 | else |
4046 | /* 32-bit float registers. */ | |
4047 | file_mips_opts.fp = 32; | |
4048 | } | |
4049 | ||
4050 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); | |
4051 | ||
351cdf24 MF |
4052 | /* Disable operations on odd-numbered floating-point registers by default |
4053 | when using the FPXX ABI. */ | |
4054 | if (file_mips_opts.oddspreg < 0) | |
4055 | { | |
4056 | if (file_mips_opts.fp == 0) | |
4057 | file_mips_opts.oddspreg = 0; | |
4058 | else | |
4059 | file_mips_opts.oddspreg = 1; | |
4060 | } | |
4061 | ||
919731af | 4062 | /* End of GCC-shared inference code. */ |
4063 | ||
4064 | /* This flag is set when we have a 64-bit capable CPU but use only | |
4065 | 32-bit wide registers. Note that EABI does not use it. */ | |
4066 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) | |
4067 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) | |
4068 | || mips_abi == O32_ABI)) | |
4069 | mips_32bitmode = 1; | |
4070 | ||
4071 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) | |
4072 | as_bad (_("trap exception not supported at ISA 1")); | |
4073 | ||
4074 | /* If the selected architecture includes support for ASEs, enable | |
4075 | generation of code for them. */ | |
4076 | if (file_mips_opts.mips16 == -1) | |
4077 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; | |
4078 | if (file_mips_opts.micromips == -1) | |
4079 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) | |
4080 | ? 1 : 0; | |
4081 | ||
7361da2c AB |
4082 | if (mips_nan2008 == -1) |
4083 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; | |
4084 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) | |
4085 | as_fatal (_("`%s' does not support legacy NaN"), | |
4086 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); | |
4087 | ||
919731af | 4088 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
4089 | being selected implicitly. */ | |
4090 | if (file_mips_opts.fp != 64) | |
4091 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; | |
4092 | ||
4093 | /* If the user didn't explicitly select or deselect a particular ASE, | |
4094 | use the default setting for the CPU. */ | |
4095 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); | |
4096 | ||
4097 | /* Set up the current options. These may change throughout assembly. */ | |
4098 | mips_opts = file_mips_opts; | |
4099 | ||
4100 | mips_check_isa_supports_ases (); | |
4101 | mips_check_options (&file_mips_opts, TRUE); | |
4102 | file_mips_opts_checked = TRUE; | |
4103 | ||
4104 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) | |
4105 | as_warn (_("could not set architecture and machine")); | |
4106 | } | |
4107 | ||
252b5132 | 4108 | void |
17a2f251 | 4109 | md_assemble (char *str) |
252b5132 RH |
4110 | { |
4111 | struct mips_cl_insn insn; | |
f6688943 TS |
4112 | bfd_reloc_code_real_type unused_reloc[3] |
4113 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 4114 | |
919731af | 4115 | file_mips_check_options (); |
4116 | ||
252b5132 | 4117 | imm_expr.X_op = O_absent; |
252b5132 | 4118 | offset_expr.X_op = O_absent; |
f6688943 TS |
4119 | offset_reloc[0] = BFD_RELOC_UNUSED; |
4120 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
4121 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 | 4122 | |
e1b47bd5 RS |
4123 | mips_mark_labels (); |
4124 | mips_assembling_insn = TRUE; | |
e3de51ce | 4125 | clear_insn_error (); |
e1b47bd5 | 4126 | |
252b5132 RH |
4127 | if (mips_opts.mips16) |
4128 | mips16_ip (str, &insn); | |
4129 | else | |
4130 | { | |
4131 | mips_ip (str, &insn); | |
beae10d5 KH |
4132 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
4133 | str, insn.insn_opcode)); | |
252b5132 RH |
4134 | } |
4135 | ||
e3de51ce RS |
4136 | if (insn_error.msg) |
4137 | report_insn_error (str); | |
e1b47bd5 | 4138 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
252b5132 | 4139 | { |
584892a6 | 4140 | macro_start (); |
252b5132 RH |
4141 | if (mips_opts.mips16) |
4142 | mips16_macro (&insn); | |
4143 | else | |
833794fc | 4144 | macro (&insn, str); |
584892a6 | 4145 | macro_end (); |
252b5132 RH |
4146 | } |
4147 | else | |
4148 | { | |
77bd4346 | 4149 | if (offset_expr.X_op != O_absent) |
df58fc94 | 4150 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
252b5132 | 4151 | else |
df58fc94 | 4152 | append_insn (&insn, NULL, unused_reloc, FALSE); |
252b5132 | 4153 | } |
e1b47bd5 RS |
4154 | |
4155 | mips_assembling_insn = FALSE; | |
252b5132 RH |
4156 | } |
4157 | ||
738e5348 RS |
4158 | /* Convenience functions for abstracting away the differences between |
4159 | MIPS16 and non-MIPS16 relocations. */ | |
4160 | ||
4161 | static inline bfd_boolean | |
4162 | mips16_reloc_p (bfd_reloc_code_real_type reloc) | |
4163 | { | |
4164 | switch (reloc) | |
4165 | { | |
4166 | case BFD_RELOC_MIPS16_JMP: | |
4167 | case BFD_RELOC_MIPS16_GPREL: | |
4168 | case BFD_RELOC_MIPS16_GOT16: | |
4169 | case BFD_RELOC_MIPS16_CALL16: | |
4170 | case BFD_RELOC_MIPS16_HI16_S: | |
4171 | case BFD_RELOC_MIPS16_HI16: | |
4172 | case BFD_RELOC_MIPS16_LO16: | |
c9775dde | 4173 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
738e5348 RS |
4174 | return TRUE; |
4175 | ||
4176 | default: | |
4177 | return FALSE; | |
4178 | } | |
4179 | } | |
4180 | ||
df58fc94 RS |
4181 | static inline bfd_boolean |
4182 | micromips_reloc_p (bfd_reloc_code_real_type reloc) | |
4183 | { | |
4184 | switch (reloc) | |
4185 | { | |
4186 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
4187 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4188 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
4189 | case BFD_RELOC_MICROMIPS_GPREL16: | |
4190 | case BFD_RELOC_MICROMIPS_JMP: | |
4191 | case BFD_RELOC_MICROMIPS_HI16: | |
4192 | case BFD_RELOC_MICROMIPS_HI16_S: | |
4193 | case BFD_RELOC_MICROMIPS_LO16: | |
4194 | case BFD_RELOC_MICROMIPS_LITERAL: | |
4195 | case BFD_RELOC_MICROMIPS_GOT16: | |
4196 | case BFD_RELOC_MICROMIPS_CALL16: | |
4197 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
4198 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
4199 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
4200 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
4201 | case BFD_RELOC_MICROMIPS_SUB: | |
4202 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
4203 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
4204 | case BFD_RELOC_MICROMIPS_GOT_DISP: | |
4205 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
4206 | case BFD_RELOC_MICROMIPS_HIGHER: | |
4207 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
4208 | case BFD_RELOC_MICROMIPS_JALR: | |
4209 | return TRUE; | |
4210 | ||
4211 | default: | |
4212 | return FALSE; | |
4213 | } | |
4214 | } | |
4215 | ||
2309ddf2 MR |
4216 | static inline bfd_boolean |
4217 | jmp_reloc_p (bfd_reloc_code_real_type reloc) | |
4218 | { | |
4219 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; | |
4220 | } | |
4221 | ||
0e9c5a5c MR |
4222 | static inline bfd_boolean |
4223 | b_reloc_p (bfd_reloc_code_real_type reloc) | |
4224 | { | |
4225 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 | |
4226 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 | |
4227 | || reloc == BFD_RELOC_16_PCREL_S2 | |
c9775dde | 4228 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
0e9c5a5c MR |
4229 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
4230 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
4231 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
4232 | } | |
4233 | ||
738e5348 RS |
4234 | static inline bfd_boolean |
4235 | got16_reloc_p (bfd_reloc_code_real_type reloc) | |
4236 | { | |
2309ddf2 | 4237 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
df58fc94 | 4238 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
738e5348 RS |
4239 | } |
4240 | ||
4241 | static inline bfd_boolean | |
4242 | hi16_reloc_p (bfd_reloc_code_real_type reloc) | |
4243 | { | |
2309ddf2 | 4244 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
df58fc94 | 4245 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
738e5348 RS |
4246 | } |
4247 | ||
4248 | static inline bfd_boolean | |
4249 | lo16_reloc_p (bfd_reloc_code_real_type reloc) | |
4250 | { | |
2309ddf2 | 4251 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
df58fc94 RS |
4252 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
4253 | } | |
4254 | ||
df58fc94 RS |
4255 | static inline bfd_boolean |
4256 | jalr_reloc_p (bfd_reloc_code_real_type reloc) | |
4257 | { | |
2309ddf2 | 4258 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
738e5348 RS |
4259 | } |
4260 | ||
f2ae14a1 RS |
4261 | static inline bfd_boolean |
4262 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) | |
4263 | { | |
4264 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL | |
4265 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); | |
4266 | } | |
4267 | ||
2de39019 CM |
4268 | /* Return true if RELOC is a PC-relative relocation that does not have |
4269 | full address range. */ | |
4270 | ||
4271 | static inline bfd_boolean | |
4272 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) | |
4273 | { | |
4274 | switch (reloc) | |
4275 | { | |
4276 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 4277 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
2de39019 CM |
4278 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
4279 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
4280 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
7361da2c AB |
4281 | case BFD_RELOC_MIPS_21_PCREL_S2: |
4282 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
4283 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
4284 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
2de39019 CM |
4285 | return TRUE; |
4286 | ||
b47468a6 | 4287 | case BFD_RELOC_32_PCREL: |
7361da2c AB |
4288 | case BFD_RELOC_HI16_S_PCREL: |
4289 | case BFD_RELOC_LO16_PCREL: | |
b47468a6 CM |
4290 | return HAVE_64BIT_ADDRESSES; |
4291 | ||
2de39019 CM |
4292 | default: |
4293 | return FALSE; | |
4294 | } | |
4295 | } | |
b47468a6 | 4296 | |
5919d012 | 4297 | /* Return true if the given relocation might need a matching %lo(). |
0a44bf69 RS |
4298 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
4299 | need a matching %lo() when applied to local symbols. */ | |
5919d012 RS |
4300 | |
4301 | static inline bfd_boolean | |
17a2f251 | 4302 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
5919d012 | 4303 | { |
3b91255e | 4304 | return (HAVE_IN_PLACE_ADDENDS |
738e5348 | 4305 | && (hi16_reloc_p (reloc) |
0a44bf69 RS |
4306 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
4307 | all GOT16 relocations evaluate to "G". */ | |
738e5348 RS |
4308 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
4309 | } | |
4310 | ||
4311 | /* Return the type of %lo() reloc needed by RELOC, given that | |
4312 | reloc_needs_lo_p. */ | |
4313 | ||
4314 | static inline bfd_reloc_code_real_type | |
4315 | matching_lo_reloc (bfd_reloc_code_real_type reloc) | |
4316 | { | |
df58fc94 RS |
4317 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
4318 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 | |
4319 | : BFD_RELOC_LO16)); | |
5919d012 RS |
4320 | } |
4321 | ||
4322 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 | |
4323 | relocation. */ | |
4324 | ||
4325 | static inline bfd_boolean | |
17a2f251 | 4326 | fixup_has_matching_lo_p (fixS *fixp) |
5919d012 RS |
4327 | { |
4328 | return (fixp->fx_next != NULL | |
738e5348 | 4329 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
5919d012 RS |
4330 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
4331 | && fixp->fx_offset == fixp->fx_next->fx_offset); | |
4332 | } | |
4333 | ||
462427c4 RS |
4334 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
4335 | says whether the labels refer to text or data. */ | |
404a8071 RS |
4336 | |
4337 | static void | |
462427c4 | 4338 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
404a8071 RS |
4339 | { |
4340 | struct insn_label_list *l; | |
4341 | valueT val; | |
4342 | ||
462427c4 | 4343 | for (l = labels; l != NULL; l = l->next) |
404a8071 | 4344 | { |
9c2799c2 | 4345 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
404a8071 RS |
4346 | symbol_set_frag (l->label, frag_now); |
4347 | val = (valueT) frag_now_fix (); | |
df58fc94 | 4348 | /* MIPS16/microMIPS text labels are stored as odd. */ |
462427c4 | 4349 | if (text_p && HAVE_CODE_COMPRESSION) |
404a8071 RS |
4350 | ++val; |
4351 | S_SET_VALUE (l->label, val); | |
4352 | } | |
4353 | } | |
4354 | ||
462427c4 RS |
4355 | /* Move all labels in insn_labels to the current insertion point |
4356 | and treat them as text labels. */ | |
4357 | ||
4358 | static void | |
4359 | mips_move_text_labels (void) | |
4360 | { | |
4361 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); | |
4362 | } | |
4363 | ||
9e009953 MR |
4364 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
4365 | ||
5f0fe04b TS |
4366 | static bfd_boolean |
4367 | s_is_linkonce (symbolS *sym, segT from_seg) | |
4368 | { | |
4369 | bfd_boolean linkonce = FALSE; | |
4370 | segT symseg = S_GET_SEGMENT (sym); | |
4371 | ||
4372 | if (symseg != from_seg && !S_IS_LOCAL (sym)) | |
4373 | { | |
4374 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) | |
4375 | linkonce = TRUE; | |
5f0fe04b TS |
4376 | /* The GNU toolchain uses an extension for ELF: a section |
4377 | beginning with the magic string .gnu.linkonce is a | |
4378 | linkonce section. */ | |
4379 | if (strncmp (segment_name (symseg), ".gnu.linkonce", | |
4380 | sizeof ".gnu.linkonce" - 1) == 0) | |
4381 | linkonce = TRUE; | |
5f0fe04b TS |
4382 | } |
4383 | return linkonce; | |
4384 | } | |
4385 | ||
e1b47bd5 | 4386 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
df58fc94 RS |
4387 | linker to handle them specially, such as generating jalx instructions |
4388 | when needed. We also make them odd for the duration of the assembly, | |
4389 | in order to generate the right sort of code. We will make them even | |
252b5132 RH |
4390 | in the adjust_symtab routine, while leaving them marked. This is |
4391 | convenient for the debugger and the disassembler. The linker knows | |
4392 | to make them odd again. */ | |
4393 | ||
4394 | static void | |
e1b47bd5 | 4395 | mips_compressed_mark_label (symbolS *label) |
252b5132 | 4396 | { |
df58fc94 | 4397 | gas_assert (HAVE_CODE_COMPRESSION); |
a8dbcb85 | 4398 | |
f3ded42a RS |
4399 | if (mips_opts.mips16) |
4400 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); | |
4401 | else | |
4402 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); | |
e1b47bd5 RS |
4403 | if ((S_GET_VALUE (label) & 1) == 0 |
4404 | /* Don't adjust the address if the label is global or weak, or | |
4405 | in a link-once section, since we'll be emitting symbol reloc | |
4406 | references to it which will be patched up by the linker, and | |
4407 | the final value of the symbol may or may not be MIPS16/microMIPS. */ | |
4408 | && !S_IS_WEAK (label) | |
4409 | && !S_IS_EXTERNAL (label) | |
4410 | && !s_is_linkonce (label, now_seg)) | |
4411 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); | |
4412 | } | |
4413 | ||
4414 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ | |
4415 | ||
4416 | static void | |
4417 | mips_compressed_mark_labels (void) | |
4418 | { | |
4419 | struct insn_label_list *l; | |
4420 | ||
4421 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) | |
4422 | mips_compressed_mark_label (l->label); | |
252b5132 RH |
4423 | } |
4424 | ||
4d7206a2 RS |
4425 | /* End the current frag. Make it a variant frag and record the |
4426 | relaxation info. */ | |
4427 | ||
4428 | static void | |
4429 | relax_close_frag (void) | |
4430 | { | |
584892a6 | 4431 | mips_macro_warning.first_frag = frag_now; |
4d7206a2 | 4432 | frag_var (rs_machine_dependent, 0, 0, |
ce8ad872 MR |
4433 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
4434 | mips_pic != NO_PIC), | |
4d7206a2 RS |
4435 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
4436 | ||
4437 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); | |
4438 | mips_relax.first_fixup = 0; | |
4439 | } | |
4440 | ||
4441 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. | |
4442 | See the comment above RELAX_ENCODE for more details. */ | |
4443 | ||
4444 | static void | |
4445 | relax_start (symbolS *symbol) | |
4446 | { | |
9c2799c2 | 4447 | gas_assert (mips_relax.sequence == 0); |
4d7206a2 RS |
4448 | mips_relax.sequence = 1; |
4449 | mips_relax.symbol = symbol; | |
4450 | } | |
4451 | ||
4452 | /* Start generating the second version of a relaxable sequence. | |
4453 | See the comment above RELAX_ENCODE for more details. */ | |
252b5132 RH |
4454 | |
4455 | static void | |
4d7206a2 RS |
4456 | relax_switch (void) |
4457 | { | |
9c2799c2 | 4458 | gas_assert (mips_relax.sequence == 1); |
4d7206a2 RS |
4459 | mips_relax.sequence = 2; |
4460 | } | |
4461 | ||
4462 | /* End the current relaxable sequence. */ | |
4463 | ||
4464 | static void | |
4465 | relax_end (void) | |
4466 | { | |
9c2799c2 | 4467 | gas_assert (mips_relax.sequence == 2); |
4d7206a2 RS |
4468 | relax_close_frag (); |
4469 | mips_relax.sequence = 0; | |
4470 | } | |
4471 | ||
11625dd8 RS |
4472 | /* Return true if IP is a delayed branch or jump. */ |
4473 | ||
4474 | static inline bfd_boolean | |
4475 | delayed_branch_p (const struct mips_cl_insn *ip) | |
4476 | { | |
4477 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4478 | | INSN_COND_BRANCH_DELAY | |
4479 | | INSN_COND_BRANCH_LIKELY)) != 0; | |
4480 | } | |
4481 | ||
4482 | /* Return true if IP is a compact branch or jump. */ | |
4483 | ||
4484 | static inline bfd_boolean | |
4485 | compact_branch_p (const struct mips_cl_insn *ip) | |
4486 | { | |
26545944 RS |
4487 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
4488 | | INSN2_COND_BRANCH)) != 0; | |
11625dd8 RS |
4489 | } |
4490 | ||
4491 | /* Return true if IP is an unconditional branch or jump. */ | |
4492 | ||
4493 | static inline bfd_boolean | |
4494 | uncond_branch_p (const struct mips_cl_insn *ip) | |
4495 | { | |
4496 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 | |
26545944 | 4497 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
11625dd8 RS |
4498 | } |
4499 | ||
4500 | /* Return true if IP is a branch-likely instruction. */ | |
4501 | ||
4502 | static inline bfd_boolean | |
4503 | branch_likely_p (const struct mips_cl_insn *ip) | |
4504 | { | |
4505 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; | |
4506 | } | |
4507 | ||
14fe068b RS |
4508 | /* Return the type of nop that should be used to fill the delay slot |
4509 | of delayed branch IP. */ | |
4510 | ||
4511 | static struct mips_cl_insn * | |
4512 | get_delay_slot_nop (const struct mips_cl_insn *ip) | |
4513 | { | |
4514 | if (mips_opts.micromips | |
4515 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) | |
4516 | return µmips_nop32_insn; | |
4517 | return NOP_INSN; | |
4518 | } | |
4519 | ||
fc76e730 RS |
4520 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
4521 | in operand N. */ | |
df58fc94 RS |
4522 | |
4523 | static unsigned int | |
fc76e730 | 4524 | insn_read_mask (const struct mips_opcode *opcode) |
df58fc94 | 4525 | { |
fc76e730 RS |
4526 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
4527 | } | |
df58fc94 | 4528 | |
fc76e730 RS |
4529 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
4530 | in operand N. */ | |
4531 | ||
4532 | static unsigned int | |
4533 | insn_write_mask (const struct mips_opcode *opcode) | |
4534 | { | |
4535 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; | |
4536 | } | |
4537 | ||
4538 | /* Return a mask of the registers specified by operand OPERAND of INSN. | |
4539 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4540 | is set. */ | |
4541 | ||
4542 | static unsigned int | |
4543 | operand_reg_mask (const struct mips_cl_insn *insn, | |
4544 | const struct mips_operand *operand, | |
4545 | unsigned int type_mask) | |
4546 | { | |
4547 | unsigned int uval, vsel; | |
4548 | ||
4549 | switch (operand->type) | |
df58fc94 | 4550 | { |
fc76e730 RS |
4551 | case OP_INT: |
4552 | case OP_MAPPED_INT: | |
4553 | case OP_MSB: | |
4554 | case OP_PCREL: | |
4555 | case OP_PERF_REG: | |
4556 | case OP_ADDIUSP_INT: | |
4557 | case OP_ENTRY_EXIT_LIST: | |
4558 | case OP_REPEAT_DEST_REG: | |
4559 | case OP_REPEAT_PREV_REG: | |
4560 | case OP_PC: | |
14daeee3 RS |
4561 | case OP_VU0_SUFFIX: |
4562 | case OP_VU0_MATCH_SUFFIX: | |
56d438b1 | 4563 | case OP_IMM_INDEX: |
fc76e730 RS |
4564 | abort (); |
4565 | ||
25499ac7 MR |
4566 | case OP_REG28: |
4567 | return 1 << 28; | |
4568 | ||
fc76e730 | 4569 | case OP_REG: |
0f35dbc4 | 4570 | case OP_OPTIONAL_REG: |
fc76e730 RS |
4571 | { |
4572 | const struct mips_reg_operand *reg_op; | |
4573 | ||
4574 | reg_op = (const struct mips_reg_operand *) operand; | |
4575 | if (!(type_mask & (1 << reg_op->reg_type))) | |
4576 | return 0; | |
4577 | uval = insn_extract_operand (insn, operand); | |
4578 | return 1 << mips_decode_reg_operand (reg_op, uval); | |
4579 | } | |
4580 | ||
4581 | case OP_REG_PAIR: | |
4582 | { | |
4583 | const struct mips_reg_pair_operand *pair_op; | |
4584 | ||
4585 | pair_op = (const struct mips_reg_pair_operand *) operand; | |
4586 | if (!(type_mask & (1 << pair_op->reg_type))) | |
4587 | return 0; | |
4588 | uval = insn_extract_operand (insn, operand); | |
4589 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); | |
4590 | } | |
4591 | ||
4592 | case OP_CLO_CLZ_DEST: | |
4593 | if (!(type_mask & (1 << OP_REG_GP))) | |
4594 | return 0; | |
4595 | uval = insn_extract_operand (insn, operand); | |
4596 | return (1 << (uval & 31)) | (1 << (uval >> 5)); | |
4597 | ||
7361da2c AB |
4598 | case OP_SAME_RS_RT: |
4599 | if (!(type_mask & (1 << OP_REG_GP))) | |
4600 | return 0; | |
4601 | uval = insn_extract_operand (insn, operand); | |
4602 | gas_assert ((uval & 31) == (uval >> 5)); | |
4603 | return 1 << (uval & 31); | |
4604 | ||
4605 | case OP_CHECK_PREV: | |
4606 | case OP_NON_ZERO_REG: | |
4607 | if (!(type_mask & (1 << OP_REG_GP))) | |
4608 | return 0; | |
4609 | uval = insn_extract_operand (insn, operand); | |
4610 | return 1 << (uval & 31); | |
4611 | ||
fc76e730 RS |
4612 | case OP_LWM_SWM_LIST: |
4613 | abort (); | |
4614 | ||
4615 | case OP_SAVE_RESTORE_LIST: | |
4616 | abort (); | |
4617 | ||
4618 | case OP_MDMX_IMM_REG: | |
4619 | if (!(type_mask & (1 << OP_REG_VEC))) | |
4620 | return 0; | |
4621 | uval = insn_extract_operand (insn, operand); | |
4622 | vsel = uval >> 5; | |
4623 | if ((vsel & 0x18) == 0x18) | |
4624 | return 0; | |
4625 | return 1 << (uval & 31); | |
56d438b1 CF |
4626 | |
4627 | case OP_REG_INDEX: | |
4628 | if (!(type_mask & (1 << OP_REG_GP))) | |
4629 | return 0; | |
4630 | return 1 << insn_extract_operand (insn, operand); | |
df58fc94 | 4631 | } |
fc76e730 RS |
4632 | abort (); |
4633 | } | |
4634 | ||
4635 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, | |
4636 | where bit N of OPNO_MASK is set if operand N should be included. | |
4637 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK | |
4638 | is set. */ | |
4639 | ||
4640 | static unsigned int | |
4641 | insn_reg_mask (const struct mips_cl_insn *insn, | |
4642 | unsigned int type_mask, unsigned int opno_mask) | |
4643 | { | |
4644 | unsigned int opno, reg_mask; | |
4645 | ||
4646 | opno = 0; | |
4647 | reg_mask = 0; | |
4648 | while (opno_mask != 0) | |
4649 | { | |
4650 | if (opno_mask & 1) | |
4651 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); | |
4652 | opno_mask >>= 1; | |
4653 | opno += 1; | |
4654 | } | |
4655 | return reg_mask; | |
df58fc94 RS |
4656 | } |
4657 | ||
4c260379 RS |
4658 | /* Return the mask of core registers that IP reads. */ |
4659 | ||
4660 | static unsigned int | |
4661 | gpr_read_mask (const struct mips_cl_insn *ip) | |
4662 | { | |
4663 | unsigned long pinfo, pinfo2; | |
4664 | unsigned int mask; | |
4665 | ||
fc76e730 | 4666 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
4c260379 RS |
4667 | pinfo = ip->insn_mo->pinfo; |
4668 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 | 4669 | if (pinfo & INSN_UDI) |
4c260379 | 4670 | { |
fc76e730 RS |
4671 | /* UDI instructions have traditionally been assumed to read RS |
4672 | and RT. */ | |
4673 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); | |
4674 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); | |
4c260379 | 4675 | } |
fc76e730 RS |
4676 | if (pinfo & INSN_READ_GPR_24) |
4677 | mask |= 1 << 24; | |
4678 | if (pinfo2 & INSN2_READ_GPR_16) | |
4679 | mask |= 1 << 16; | |
4680 | if (pinfo2 & INSN2_READ_SP) | |
4681 | mask |= 1 << SP; | |
26545944 | 4682 | if (pinfo2 & INSN2_READ_GPR_31) |
fc76e730 | 4683 | mask |= 1 << 31; |
fe35f09f RS |
4684 | /* Don't include register 0. */ |
4685 | return mask & ~1; | |
4c260379 RS |
4686 | } |
4687 | ||
4688 | /* Return the mask of core registers that IP writes. */ | |
4689 | ||
4690 | static unsigned int | |
4691 | gpr_write_mask (const struct mips_cl_insn *ip) | |
4692 | { | |
4693 | unsigned long pinfo, pinfo2; | |
4694 | unsigned int mask; | |
4695 | ||
fc76e730 | 4696 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
4c260379 RS |
4697 | pinfo = ip->insn_mo->pinfo; |
4698 | pinfo2 = ip->insn_mo->pinfo2; | |
fc76e730 RS |
4699 | if (pinfo & INSN_WRITE_GPR_24) |
4700 | mask |= 1 << 24; | |
4701 | if (pinfo & INSN_WRITE_GPR_31) | |
4702 | mask |= 1 << 31; | |
4703 | if (pinfo & INSN_UDI) | |
4704 | /* UDI instructions have traditionally been assumed to write to RD. */ | |
4705 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); | |
4706 | if (pinfo2 & INSN2_WRITE_SP) | |
4707 | mask |= 1 << SP; | |
fe35f09f RS |
4708 | /* Don't include register 0. */ |
4709 | return mask & ~1; | |
4c260379 RS |
4710 | } |
4711 | ||
4712 | /* Return the mask of floating-point registers that IP reads. */ | |
4713 | ||
4714 | static unsigned int | |
4715 | fpr_read_mask (const struct mips_cl_insn *ip) | |
4716 | { | |
fc76e730 | 4717 | unsigned long pinfo; |
4c260379 RS |
4718 | unsigned int mask; |
4719 | ||
9d5de888 CF |
4720 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4721 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4722 | insn_read_mask (ip->insn_mo)); |
4c260379 | 4723 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4724 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4725 | (This is overly pessimistic for things like cvt.d.s.) */ | |
bad1aba3 | 4726 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4727 | mask |= mask << 1; |
4728 | return mask; | |
4729 | } | |
4730 | ||
4731 | /* Return the mask of floating-point registers that IP writes. */ | |
4732 | ||
4733 | static unsigned int | |
4734 | fpr_write_mask (const struct mips_cl_insn *ip) | |
4735 | { | |
fc76e730 | 4736 | unsigned long pinfo; |
4c260379 RS |
4737 | unsigned int mask; |
4738 | ||
9d5de888 CF |
4739 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
4740 | | (1 << OP_REG_MSA)), | |
fc76e730 | 4741 | insn_write_mask (ip->insn_mo)); |
4c260379 | 4742 | pinfo = ip->insn_mo->pinfo; |
4c260379 RS |
4743 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
4744 | (This is overly pessimistic for things like cvt.s.d.) */ | |
bad1aba3 | 4745 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
4c260379 RS |
4746 | mask |= mask << 1; |
4747 | return mask; | |
4748 | } | |
4749 | ||
a1d78564 RS |
4750 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
4751 | Check whether that is allowed. */ | |
4752 | ||
4753 | static bfd_boolean | |
4754 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) | |
4755 | { | |
4756 | const char *s = insn->name; | |
351cdf24 MF |
4757 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
4758 | || FPR_SIZE == 64) | |
4759 | && mips_opts.oddspreg; | |
a1d78564 RS |
4760 | |
4761 | if (insn->pinfo == INSN_MACRO) | |
4762 | /* Let a macro pass, we'll catch it later when it is expanded. */ | |
4763 | return TRUE; | |
4764 | ||
351cdf24 MF |
4765 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
4766 | otherwise it depends on oddspreg. */ | |
4767 | if ((insn->pinfo & FP_S) | |
4768 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY | |
43885403 | 4769 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
351cdf24 | 4770 | return FPR_SIZE == 32 || oddspreg; |
a1d78564 | 4771 | |
351cdf24 MF |
4772 | /* Allow odd registers for single-precision ops and double-precision if the |
4773 | floating-point registers are 64-bit wide. */ | |
4774 | switch (insn->pinfo & (FP_S | FP_D)) | |
4775 | { | |
4776 | case FP_S: | |
4777 | case 0: | |
4778 | return oddspreg; | |
4779 | case FP_D: | |
4780 | return FPR_SIZE == 64; | |
4781 | default: | |
4782 | break; | |
a1d78564 RS |
4783 | } |
4784 | ||
351cdf24 MF |
4785 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
4786 | s = strchr (insn->name, '.'); | |
4787 | if (s != NULL && opnum == 2) | |
4788 | s = strchr (s + 1, '.'); | |
4789 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) | |
4790 | return oddspreg; | |
a1d78564 | 4791 | |
351cdf24 | 4792 | return FPR_SIZE == 64; |
a1d78564 RS |
4793 | } |
4794 | ||
a1d78564 RS |
4795 | /* Information about an instruction argument that we're trying to match. */ |
4796 | struct mips_arg_info | |
4797 | { | |
4798 | /* The instruction so far. */ | |
4799 | struct mips_cl_insn *insn; | |
4800 | ||
a92713e6 RS |
4801 | /* The first unconsumed operand token. */ |
4802 | struct mips_operand_token *token; | |
4803 | ||
a1d78564 RS |
4804 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
4805 | int opnum; | |
4806 | ||
4807 | /* The 1-based argument number, for error reporting. This does not | |
4808 | count elided optional registers, etc.. */ | |
4809 | int argnum; | |
4810 | ||
4811 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ | |
4812 | unsigned int last_regno; | |
4813 | ||
4814 | /* If the first operand was an OP_REG, this is the register that it | |
4815 | specified, otherwise it is ILLEGAL_REG. */ | |
4816 | unsigned int dest_regno; | |
4817 | ||
4818 | /* The value of the last OP_INT operand. Only used for OP_MSB, | |
4819 | where it gives the lsb position. */ | |
4820 | unsigned int last_op_int; | |
4821 | ||
60f20e8b | 4822 | /* If true, match routines should assume that no later instruction |
2b0f3761 | 4823 | alternative matches and should therefore be as accommodating as |
60f20e8b RS |
4824 | possible. Match routines should not report errors if something |
4825 | is only invalid for !LAX_MATCH. */ | |
4826 | bfd_boolean lax_match; | |
a1d78564 | 4827 | |
a1d78564 RS |
4828 | /* True if a reference to the current AT register was seen. */ |
4829 | bfd_boolean seen_at; | |
4830 | }; | |
4831 | ||
1a00e612 RS |
4832 | /* Record that the argument is out of range. */ |
4833 | ||
4834 | static void | |
4835 | match_out_of_range (struct mips_arg_info *arg) | |
4836 | { | |
4837 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); | |
4838 | } | |
4839 | ||
4840 | /* Record that the argument isn't constant but needs to be. */ | |
4841 | ||
4842 | static void | |
4843 | match_not_constant (struct mips_arg_info *arg) | |
4844 | { | |
4845 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), | |
4846 | arg->argnum); | |
4847 | } | |
4848 | ||
a92713e6 RS |
4849 | /* Try to match an OT_CHAR token for character CH. Consume the token |
4850 | and return true on success, otherwise return false. */ | |
a1d78564 | 4851 | |
a92713e6 RS |
4852 | static bfd_boolean |
4853 | match_char (struct mips_arg_info *arg, char ch) | |
a1d78564 | 4854 | { |
a92713e6 RS |
4855 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
4856 | { | |
4857 | ++arg->token; | |
4858 | if (ch == ',') | |
4859 | arg->argnum += 1; | |
4860 | return TRUE; | |
4861 | } | |
4862 | return FALSE; | |
4863 | } | |
a1d78564 | 4864 | |
a92713e6 RS |
4865 | /* Try to get an expression from the next tokens in ARG. Consume the |
4866 | tokens and return true on success, storing the expression value in | |
4867 | VALUE and relocation types in R. */ | |
4868 | ||
4869 | static bfd_boolean | |
4870 | match_expression (struct mips_arg_info *arg, expressionS *value, | |
4871 | bfd_reloc_code_real_type *r) | |
4872 | { | |
d436c1c2 RS |
4873 | /* If the next token is a '(' that was parsed as being part of a base |
4874 | expression, assume we have an elided offset. The later match will fail | |
4875 | if this turns out to be wrong. */ | |
4876 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') | |
a1d78564 | 4877 | { |
d436c1c2 RS |
4878 | value->X_op = O_constant; |
4879 | value->X_add_number = 0; | |
4880 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; | |
a92713e6 RS |
4881 | return TRUE; |
4882 | } | |
4883 | ||
d436c1c2 RS |
4884 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
4885 | For plain registers the default error seems more appropriate. */ | |
4886 | if (arg->token->type == OT_INTEGER | |
4887 | && arg->token->u.integer.value.X_op == O_register) | |
a92713e6 | 4888 | { |
d436c1c2 RS |
4889 | set_insn_error (arg->argnum, _("register value used as expression")); |
4890 | return FALSE; | |
a1d78564 | 4891 | } |
d436c1c2 RS |
4892 | |
4893 | if (arg->token->type == OT_INTEGER) | |
a92713e6 | 4894 | { |
d436c1c2 RS |
4895 | *value = arg->token->u.integer.value; |
4896 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); | |
4897 | ++arg->token; | |
4898 | return TRUE; | |
a92713e6 | 4899 | } |
a92713e6 | 4900 | |
d436c1c2 RS |
4901 | set_insn_error_i |
4902 | (arg->argnum, _("operand %d must be an immediate expression"), | |
4903 | arg->argnum); | |
4904 | return FALSE; | |
a92713e6 RS |
4905 | } |
4906 | ||
4907 | /* Try to get a constant expression from the next tokens in ARG. Consume | |
de194d85 | 4908 | the tokens and return true on success, storing the constant value |
a54d5f8b | 4909 | in *VALUE. */ |
a92713e6 RS |
4910 | |
4911 | static bfd_boolean | |
1a00e612 | 4912 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
a92713e6 RS |
4913 | { |
4914 | expressionS ex; | |
4915 | bfd_reloc_code_real_type r[3]; | |
a1d78564 | 4916 | |
a92713e6 RS |
4917 | if (!match_expression (arg, &ex, r)) |
4918 | return FALSE; | |
4919 | ||
4920 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) | |
a1d78564 RS |
4921 | *value = ex.X_add_number; |
4922 | else | |
4923 | { | |
c96425c5 MR |
4924 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
4925 | match_out_of_range (arg); | |
4926 | else | |
4927 | match_not_constant (arg); | |
1a00e612 | 4928 | return FALSE; |
a1d78564 | 4929 | } |
a92713e6 | 4930 | return TRUE; |
a1d78564 RS |
4931 | } |
4932 | ||
4933 | /* Return the RTYPE_* flags for a register operand of type TYPE that | |
4934 | appears in instruction OPCODE. */ | |
4935 | ||
4936 | static unsigned int | |
4937 | convert_reg_type (const struct mips_opcode *opcode, | |
4938 | enum mips_reg_operand_type type) | |
4939 | { | |
4940 | switch (type) | |
4941 | { | |
4942 | case OP_REG_GP: | |
4943 | return RTYPE_NUM | RTYPE_GP; | |
4944 | ||
4945 | case OP_REG_FP: | |
4946 | /* Allow vector register names for MDMX if the instruction is a 64-bit | |
4947 | FPR load, store or move (including moves to and from GPRs). */ | |
4948 | if ((mips_opts.ase & ASE_MDMX) | |
4949 | && (opcode->pinfo & FP_D) | |
43885403 | 4950 | && (opcode->pinfo & (INSN_COPROC_MOVE |
a1d78564 | 4951 | | INSN_COPROC_MEMORY_DELAY |
43885403 | 4952 | | INSN_LOAD_COPROC |
67dc82bc | 4953 | | INSN_LOAD_MEMORY |
a1d78564 RS |
4954 | | INSN_STORE_MEMORY))) |
4955 | return RTYPE_FPU | RTYPE_VEC; | |
4956 | return RTYPE_FPU; | |
4957 | ||
4958 | case OP_REG_CCC: | |
4959 | if (opcode->pinfo & (FP_D | FP_S)) | |
4960 | return RTYPE_CCC | RTYPE_FCC; | |
4961 | return RTYPE_CCC; | |
4962 | ||
4963 | case OP_REG_VEC: | |
4964 | if (opcode->membership & INSN_5400) | |
4965 | return RTYPE_FPU; | |
4966 | return RTYPE_FPU | RTYPE_VEC; | |
4967 | ||
4968 | case OP_REG_ACC: | |
4969 | return RTYPE_ACC; | |
4970 | ||
4971 | case OP_REG_COPRO: | |
4972 | if (opcode->name[strlen (opcode->name) - 1] == '0') | |
4973 | return RTYPE_NUM | RTYPE_CP0; | |
4974 | return RTYPE_NUM; | |
4975 | ||
4976 | case OP_REG_HW: | |
4977 | return RTYPE_NUM; | |
14daeee3 RS |
4978 | |
4979 | case OP_REG_VI: | |
4980 | return RTYPE_NUM | RTYPE_VI; | |
4981 | ||
4982 | case OP_REG_VF: | |
4983 | return RTYPE_NUM | RTYPE_VF; | |
4984 | ||
4985 | case OP_REG_R5900_I: | |
4986 | return RTYPE_R5900_I; | |
4987 | ||
4988 | case OP_REG_R5900_Q: | |
4989 | return RTYPE_R5900_Q; | |
4990 | ||
4991 | case OP_REG_R5900_R: | |
4992 | return RTYPE_R5900_R; | |
4993 | ||
4994 | case OP_REG_R5900_ACC: | |
4995 | return RTYPE_R5900_ACC; | |
56d438b1 CF |
4996 | |
4997 | case OP_REG_MSA: | |
4998 | return RTYPE_MSA; | |
4999 | ||
5000 | case OP_REG_MSA_CTRL: | |
5001 | return RTYPE_NUM; | |
a1d78564 RS |
5002 | } |
5003 | abort (); | |
5004 | } | |
5005 | ||
5006 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ | |
5007 | ||
5008 | static void | |
5009 | check_regno (struct mips_arg_info *arg, | |
5010 | enum mips_reg_operand_type type, unsigned int regno) | |
5011 | { | |
5012 | if (AT && type == OP_REG_GP && regno == AT) | |
5013 | arg->seen_at = TRUE; | |
5014 | ||
5015 | if (type == OP_REG_FP | |
5016 | && (regno & 1) != 0 | |
a1d78564 | 5017 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
351cdf24 MF |
5018 | { |
5019 | /* This was a warning prior to introducing O32 FPXX and FP64 support | |
5020 | so maintain a warning for FP32 but raise an error for the new | |
5021 | cases. */ | |
5022 | if (FPR_SIZE == 32) | |
5023 | as_warn (_("float register should be even, was %d"), regno); | |
5024 | else | |
5025 | as_bad (_("float register should be even, was %d"), regno); | |
5026 | } | |
a1d78564 RS |
5027 | |
5028 | if (type == OP_REG_CCC) | |
5029 | { | |
5030 | const char *name; | |
5031 | size_t length; | |
5032 | ||
5033 | name = arg->insn->insn_mo->name; | |
5034 | length = strlen (name); | |
5035 | if ((regno & 1) != 0 | |
5036 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) | |
5037 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) | |
1661c76c | 5038 | as_warn (_("condition code register should be even for %s, was %d"), |
a1d78564 RS |
5039 | name, regno); |
5040 | ||
5041 | if ((regno & 3) != 0 | |
5042 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) | |
1661c76c | 5043 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
a1d78564 RS |
5044 | name, regno); |
5045 | } | |
5046 | } | |
5047 | ||
a92713e6 RS |
5048 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
5049 | a register of type TYPE. Return true on success, storing the register | |
5050 | number in *REGNO and warning about any dubious uses. */ | |
5051 | ||
5052 | static bfd_boolean | |
5053 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5054 | unsigned int symval, unsigned int *regno) | |
5055 | { | |
5056 | if (type == OP_REG_VEC) | |
5057 | symval = mips_prefer_vec_regno (symval); | |
5058 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) | |
5059 | return FALSE; | |
5060 | ||
5061 | *regno = symval & RNUM_MASK; | |
5062 | check_regno (arg, type, *regno); | |
5063 | return TRUE; | |
5064 | } | |
5065 | ||
5066 | /* Try to interpret the next token in ARG as a register of type TYPE. | |
5067 | Consume the token and return true on success, storing the register | |
5068 | number in *REGNO. Return false on failure. */ | |
5069 | ||
5070 | static bfd_boolean | |
5071 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5072 | unsigned int *regno) | |
5073 | { | |
5074 | if (arg->token->type == OT_REG | |
5075 | && match_regno (arg, type, arg->token->u.regno, regno)) | |
5076 | { | |
5077 | ++arg->token; | |
5078 | return TRUE; | |
5079 | } | |
5080 | return FALSE; | |
5081 | } | |
5082 | ||
5083 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. | |
5084 | Consume the token and return true on success, storing the register numbers | |
5085 | in *REGNO1 and *REGNO2. Return false on failure. */ | |
5086 | ||
5087 | static bfd_boolean | |
5088 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, | |
5089 | unsigned int *regno1, unsigned int *regno2) | |
5090 | { | |
5091 | if (match_reg (arg, type, regno1)) | |
5092 | { | |
5093 | *regno2 = *regno1; | |
5094 | return TRUE; | |
5095 | } | |
5096 | if (arg->token->type == OT_REG_RANGE | |
5097 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) | |
5098 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) | |
5099 | && *regno1 <= *regno2) | |
5100 | { | |
5101 | ++arg->token; | |
5102 | return TRUE; | |
5103 | } | |
5104 | return FALSE; | |
5105 | } | |
5106 | ||
a1d78564 RS |
5107 | /* OP_INT matcher. */ |
5108 | ||
a92713e6 | 5109 | static bfd_boolean |
a1d78564 | 5110 | match_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5111 | const struct mips_operand *operand_base) |
a1d78564 RS |
5112 | { |
5113 | const struct mips_int_operand *operand; | |
3ccad066 | 5114 | unsigned int uval; |
a1d78564 RS |
5115 | int min_val, max_val, factor; |
5116 | offsetT sval; | |
a1d78564 RS |
5117 | |
5118 | operand = (const struct mips_int_operand *) operand_base; | |
5119 | factor = 1 << operand->shift; | |
3ccad066 RS |
5120 | min_val = mips_int_operand_min (operand); |
5121 | max_val = mips_int_operand_max (operand); | |
a1d78564 | 5122 | |
d436c1c2 RS |
5123 | if (operand_base->lsb == 0 |
5124 | && operand_base->size == 16 | |
5125 | && operand->shift == 0 | |
5126 | && operand->bias == 0 | |
5127 | && (operand->max_val == 32767 || operand->max_val == 65535)) | |
a1d78564 RS |
5128 | { |
5129 | /* The operand can be relocated. */ | |
a92713e6 RS |
5130 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
5131 | return FALSE; | |
5132 | ||
c96425c5 MR |
5133 | if (offset_expr.X_op == O_big) |
5134 | { | |
5135 | match_out_of_range (arg); | |
5136 | return FALSE; | |
5137 | } | |
5138 | ||
a92713e6 | 5139 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
33eaf5de | 5140 | /* Relocation operators were used. Accept the argument and |
a1d78564 RS |
5141 | leave the relocation value in offset_expr and offset_relocs |
5142 | for the caller to process. */ | |
a92713e6 RS |
5143 | return TRUE; |
5144 | ||
5145 | if (offset_expr.X_op != O_constant) | |
a1d78564 | 5146 | { |
60f20e8b RS |
5147 | /* Accept non-constant operands if no later alternative matches, |
5148 | leaving it for the caller to process. */ | |
5149 | if (!arg->lax_match) | |
602b88e3 MR |
5150 | { |
5151 | match_not_constant (arg); | |
5152 | return FALSE; | |
5153 | } | |
a92713e6 RS |
5154 | offset_reloc[0] = BFD_RELOC_LO16; |
5155 | return TRUE; | |
a1d78564 | 5156 | } |
a92713e6 | 5157 | |
a1d78564 RS |
5158 | /* Clear the global state; we're going to install the operand |
5159 | ourselves. */ | |
a92713e6 | 5160 | sval = offset_expr.X_add_number; |
a1d78564 | 5161 | offset_expr.X_op = O_absent; |
60f20e8b RS |
5162 | |
5163 | /* For compatibility with older assemblers, we accept | |
5164 | 0x8000-0xffff as signed 16-bit numbers when only | |
5165 | signed numbers are allowed. */ | |
5166 | if (sval > max_val) | |
5167 | { | |
5168 | max_val = ((1 << operand_base->size) - 1) << operand->shift; | |
5169 | if (!arg->lax_match && sval <= max_val) | |
20c59b84 MR |
5170 | { |
5171 | match_out_of_range (arg); | |
5172 | return FALSE; | |
5173 | } | |
60f20e8b | 5174 | } |
a1d78564 RS |
5175 | } |
5176 | else | |
5177 | { | |
1a00e612 | 5178 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5179 | return FALSE; |
a1d78564 RS |
5180 | } |
5181 | ||
5182 | arg->last_op_int = sval; | |
5183 | ||
1a00e612 | 5184 | if (sval < min_val || sval > max_val || sval % factor) |
a1d78564 | 5185 | { |
1a00e612 RS |
5186 | match_out_of_range (arg); |
5187 | return FALSE; | |
a1d78564 RS |
5188 | } |
5189 | ||
5190 | uval = (unsigned int) sval >> operand->shift; | |
5191 | uval -= operand->bias; | |
5192 | ||
5193 | /* Handle -mfix-cn63xxp1. */ | |
5194 | if (arg->opnum == 1 | |
5195 | && mips_fix_cn63xxp1 | |
5196 | && !mips_opts.micromips | |
5197 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) | |
5198 | switch (uval) | |
5199 | { | |
5200 | case 5: | |
5201 | case 25: | |
5202 | case 26: | |
5203 | case 27: | |
5204 | case 28: | |
5205 | case 29: | |
5206 | case 30: | |
5207 | case 31: | |
5208 | /* These are ok. */ | |
5209 | break; | |
5210 | ||
5211 | default: | |
5212 | /* The rest must be changed to 28. */ | |
5213 | uval = 28; | |
5214 | break; | |
5215 | } | |
5216 | ||
5217 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5218 | return TRUE; |
a1d78564 RS |
5219 | } |
5220 | ||
5221 | /* OP_MAPPED_INT matcher. */ | |
5222 | ||
a92713e6 | 5223 | static bfd_boolean |
a1d78564 | 5224 | match_mapped_int_operand (struct mips_arg_info *arg, |
a92713e6 | 5225 | const struct mips_operand *operand_base) |
a1d78564 RS |
5226 | { |
5227 | const struct mips_mapped_int_operand *operand; | |
5228 | unsigned int uval, num_vals; | |
5229 | offsetT sval; | |
5230 | ||
5231 | operand = (const struct mips_mapped_int_operand *) operand_base; | |
1a00e612 | 5232 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5233 | return FALSE; |
a1d78564 RS |
5234 | |
5235 | num_vals = 1 << operand_base->size; | |
5236 | for (uval = 0; uval < num_vals; uval++) | |
5237 | if (operand->int_map[uval] == sval) | |
5238 | break; | |
5239 | if (uval == num_vals) | |
1a00e612 RS |
5240 | { |
5241 | match_out_of_range (arg); | |
5242 | return FALSE; | |
5243 | } | |
a1d78564 RS |
5244 | |
5245 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5246 | return TRUE; |
a1d78564 RS |
5247 | } |
5248 | ||
5249 | /* OP_MSB matcher. */ | |
5250 | ||
a92713e6 | 5251 | static bfd_boolean |
a1d78564 | 5252 | match_msb_operand (struct mips_arg_info *arg, |
a92713e6 | 5253 | const struct mips_operand *operand_base) |
a1d78564 RS |
5254 | { |
5255 | const struct mips_msb_operand *operand; | |
5256 | int min_val, max_val, max_high; | |
5257 | offsetT size, sval, high; | |
5258 | ||
5259 | operand = (const struct mips_msb_operand *) operand_base; | |
5260 | min_val = operand->bias; | |
5261 | max_val = min_val + (1 << operand_base->size) - 1; | |
5262 | max_high = operand->opsize; | |
5263 | ||
1a00e612 | 5264 | if (!match_const_int (arg, &size)) |
a92713e6 | 5265 | return FALSE; |
a1d78564 RS |
5266 | |
5267 | high = size + arg->last_op_int; | |
5268 | sval = operand->add_lsb ? high : size; | |
5269 | ||
5270 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) | |
5271 | { | |
1a00e612 RS |
5272 | match_out_of_range (arg); |
5273 | return FALSE; | |
a1d78564 RS |
5274 | } |
5275 | insn_insert_operand (arg->insn, operand_base, sval - min_val); | |
a92713e6 | 5276 | return TRUE; |
a1d78564 RS |
5277 | } |
5278 | ||
5279 | /* OP_REG matcher. */ | |
5280 | ||
a92713e6 | 5281 | static bfd_boolean |
a1d78564 | 5282 | match_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5283 | const struct mips_operand *operand_base) |
a1d78564 RS |
5284 | { |
5285 | const struct mips_reg_operand *operand; | |
a92713e6 | 5286 | unsigned int regno, uval, num_vals; |
a1d78564 RS |
5287 | |
5288 | operand = (const struct mips_reg_operand *) operand_base; | |
a92713e6 RS |
5289 | if (!match_reg (arg, operand->reg_type, ®no)) |
5290 | return FALSE; | |
a1d78564 RS |
5291 | |
5292 | if (operand->reg_map) | |
5293 | { | |
5294 | num_vals = 1 << operand->root.size; | |
5295 | for (uval = 0; uval < num_vals; uval++) | |
5296 | if (operand->reg_map[uval] == regno) | |
5297 | break; | |
5298 | if (num_vals == uval) | |
a92713e6 | 5299 | return FALSE; |
a1d78564 RS |
5300 | } |
5301 | else | |
5302 | uval = regno; | |
5303 | ||
a1d78564 RS |
5304 | arg->last_regno = regno; |
5305 | if (arg->opnum == 1) | |
5306 | arg->dest_regno = regno; | |
5307 | insn_insert_operand (arg->insn, operand_base, uval); | |
a92713e6 | 5308 | return TRUE; |
a1d78564 RS |
5309 | } |
5310 | ||
5311 | /* OP_REG_PAIR matcher. */ | |
5312 | ||
a92713e6 | 5313 | static bfd_boolean |
a1d78564 | 5314 | match_reg_pair_operand (struct mips_arg_info *arg, |
a92713e6 | 5315 | const struct mips_operand *operand_base) |
a1d78564 RS |
5316 | { |
5317 | const struct mips_reg_pair_operand *operand; | |
a92713e6 | 5318 | unsigned int regno1, regno2, uval, num_vals; |
a1d78564 RS |
5319 | |
5320 | operand = (const struct mips_reg_pair_operand *) operand_base; | |
a92713e6 RS |
5321 | if (!match_reg (arg, operand->reg_type, ®no1) |
5322 | || !match_char (arg, ',') | |
5323 | || !match_reg (arg, operand->reg_type, ®no2)) | |
5324 | return FALSE; | |
a1d78564 RS |
5325 | |
5326 | num_vals = 1 << operand_base->size; | |
5327 | for (uval = 0; uval < num_vals; uval++) | |
5328 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) | |
5329 | break; | |
5330 | if (uval == num_vals) | |
a92713e6 | 5331 | return FALSE; |
a1d78564 | 5332 | |
a1d78564 | 5333 | insn_insert_operand (arg->insn, operand_base, uval); |
a92713e6 | 5334 | return TRUE; |
a1d78564 RS |
5335 | } |
5336 | ||
5337 | /* OP_PCREL matcher. The caller chooses the relocation type. */ | |
5338 | ||
a92713e6 RS |
5339 | static bfd_boolean |
5340 | match_pcrel_operand (struct mips_arg_info *arg) | |
a1d78564 | 5341 | { |
a92713e6 RS |
5342 | bfd_reloc_code_real_type r[3]; |
5343 | ||
5344 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; | |
a1d78564 RS |
5345 | } |
5346 | ||
5347 | /* OP_PERF_REG matcher. */ | |
5348 | ||
a92713e6 | 5349 | static bfd_boolean |
a1d78564 | 5350 | match_perf_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5351 | const struct mips_operand *operand) |
a1d78564 RS |
5352 | { |
5353 | offsetT sval; | |
5354 | ||
1a00e612 | 5355 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5356 | return FALSE; |
a1d78564 RS |
5357 | |
5358 | if (sval != 0 | |
5359 | && (sval != 1 | |
5360 | || (mips_opts.arch == CPU_R5900 | |
5361 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 | |
5362 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) | |
5363 | { | |
1a00e612 RS |
5364 | set_insn_error (arg->argnum, _("invalid performance register")); |
5365 | return FALSE; | |
a1d78564 RS |
5366 | } |
5367 | ||
5368 | insn_insert_operand (arg->insn, operand, sval); | |
a92713e6 | 5369 | return TRUE; |
a1d78564 RS |
5370 | } |
5371 | ||
5372 | /* OP_ADDIUSP matcher. */ | |
5373 | ||
a92713e6 | 5374 | static bfd_boolean |
a1d78564 | 5375 | match_addiusp_operand (struct mips_arg_info *arg, |
a92713e6 | 5376 | const struct mips_operand *operand) |
a1d78564 RS |
5377 | { |
5378 | offsetT sval; | |
5379 | unsigned int uval; | |
5380 | ||
1a00e612 | 5381 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5382 | return FALSE; |
a1d78564 RS |
5383 | |
5384 | if (sval % 4) | |
1a00e612 RS |
5385 | { |
5386 | match_out_of_range (arg); | |
5387 | return FALSE; | |
5388 | } | |
a1d78564 RS |
5389 | |
5390 | sval /= 4; | |
5391 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) | |
1a00e612 RS |
5392 | { |
5393 | match_out_of_range (arg); | |
5394 | return FALSE; | |
5395 | } | |
a1d78564 RS |
5396 | |
5397 | uval = (unsigned int) sval; | |
5398 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); | |
5399 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5400 | return TRUE; |
a1d78564 RS |
5401 | } |
5402 | ||
5403 | /* OP_CLO_CLZ_DEST matcher. */ | |
5404 | ||
a92713e6 | 5405 | static bfd_boolean |
a1d78564 | 5406 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
a92713e6 | 5407 | const struct mips_operand *operand) |
a1d78564 RS |
5408 | { |
5409 | unsigned int regno; | |
5410 | ||
a92713e6 RS |
5411 | if (!match_reg (arg, OP_REG_GP, ®no)) |
5412 | return FALSE; | |
a1d78564 | 5413 | |
a1d78564 | 5414 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
a92713e6 | 5415 | return TRUE; |
a1d78564 RS |
5416 | } |
5417 | ||
7361da2c AB |
5418 | /* OP_CHECK_PREV matcher. */ |
5419 | ||
5420 | static bfd_boolean | |
5421 | match_check_prev_operand (struct mips_arg_info *arg, | |
5422 | const struct mips_operand *operand_base) | |
5423 | { | |
5424 | const struct mips_check_prev_operand *operand; | |
5425 | unsigned int regno; | |
5426 | ||
5427 | operand = (const struct mips_check_prev_operand *) operand_base; | |
5428 | ||
5429 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5430 | return FALSE; | |
5431 | ||
5432 | if (!operand->zero_ok && regno == 0) | |
5433 | return FALSE; | |
5434 | ||
5435 | if ((operand->less_than_ok && regno < arg->last_regno) | |
5436 | || (operand->greater_than_ok && regno > arg->last_regno) | |
5437 | || (operand->equal_ok && regno == arg->last_regno)) | |
5438 | { | |
5439 | arg->last_regno = regno; | |
5440 | insn_insert_operand (arg->insn, operand_base, regno); | |
5441 | return TRUE; | |
5442 | } | |
5443 | ||
5444 | return FALSE; | |
5445 | } | |
5446 | ||
5447 | /* OP_SAME_RS_RT matcher. */ | |
5448 | ||
5449 | static bfd_boolean | |
5450 | match_same_rs_rt_operand (struct mips_arg_info *arg, | |
5451 | const struct mips_operand *operand) | |
5452 | { | |
5453 | unsigned int regno; | |
5454 | ||
5455 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5456 | return FALSE; | |
5457 | ||
5458 | if (regno == 0) | |
5459 | { | |
5460 | set_insn_error (arg->argnum, _("the source register must not be $0")); | |
5461 | return FALSE; | |
5462 | } | |
5463 | ||
5464 | arg->last_regno = regno; | |
5465 | ||
5466 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); | |
5467 | return TRUE; | |
5468 | } | |
5469 | ||
a1d78564 RS |
5470 | /* OP_LWM_SWM_LIST matcher. */ |
5471 | ||
a92713e6 | 5472 | static bfd_boolean |
a1d78564 | 5473 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
a92713e6 | 5474 | const struct mips_operand *operand) |
a1d78564 | 5475 | { |
a92713e6 RS |
5476 | unsigned int reglist, sregs, ra, regno1, regno2; |
5477 | struct mips_arg_info reset; | |
a1d78564 | 5478 | |
a92713e6 RS |
5479 | reglist = 0; |
5480 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) | |
5481 | return FALSE; | |
5482 | do | |
5483 | { | |
5484 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) | |
5485 | { | |
5486 | reglist |= 1 << FP; | |
5487 | regno2 = S7; | |
5488 | } | |
5489 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); | |
5490 | reset = *arg; | |
5491 | } | |
5492 | while (match_char (arg, ',') | |
5493 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); | |
5494 | *arg = reset; | |
a1d78564 RS |
5495 | |
5496 | if (operand->size == 2) | |
5497 | { | |
5498 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: | |
5499 | ||
5500 | s0, ra | |
5501 | s0, s1, ra, s2, s3 | |
5502 | s0-s2, ra | |
5503 | ||
5504 | and any permutations of these. */ | |
5505 | if ((reglist & 0xfff1ffff) != 0x80010000) | |
a92713e6 | 5506 | return FALSE; |
a1d78564 RS |
5507 | |
5508 | sregs = (reglist >> 17) & 7; | |
5509 | ra = 0; | |
5510 | } | |
5511 | else | |
5512 | { | |
5513 | /* The list must include at least one of ra and s0-sN, | |
5514 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, | |
5515 | which are $23 and $30 respectively.) E.g.: | |
5516 | ||
5517 | ra | |
5518 | s0 | |
5519 | ra, s0, s1, s2 | |
5520 | s0-s8 | |
5521 | s0-s5, ra | |
5522 | ||
5523 | and any permutations of these. */ | |
5524 | if ((reglist & 0x3f00ffff) != 0) | |
a92713e6 | 5525 | return FALSE; |
a1d78564 RS |
5526 | |
5527 | ra = (reglist >> 27) & 0x10; | |
5528 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); | |
5529 | } | |
5530 | sregs += 1; | |
5531 | if ((sregs & -sregs) != sregs) | |
a92713e6 | 5532 | return FALSE; |
a1d78564 RS |
5533 | |
5534 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); | |
a92713e6 | 5535 | return TRUE; |
a1d78564 RS |
5536 | } |
5537 | ||
364215c8 RS |
5538 | /* OP_ENTRY_EXIT_LIST matcher. */ |
5539 | ||
a92713e6 | 5540 | static unsigned int |
364215c8 | 5541 | match_entry_exit_operand (struct mips_arg_info *arg, |
a92713e6 | 5542 | const struct mips_operand *operand) |
364215c8 RS |
5543 | { |
5544 | unsigned int mask; | |
5545 | bfd_boolean is_exit; | |
5546 | ||
5547 | /* The format is the same for both ENTRY and EXIT, but the constraints | |
5548 | are different. */ | |
5549 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; | |
5550 | mask = (is_exit ? 7 << 3 : 0); | |
a92713e6 | 5551 | do |
364215c8 RS |
5552 | { |
5553 | unsigned int regno1, regno2; | |
5554 | bfd_boolean is_freg; | |
5555 | ||
a92713e6 | 5556 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
364215c8 | 5557 | is_freg = FALSE; |
a92713e6 | 5558 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
364215c8 RS |
5559 | is_freg = TRUE; |
5560 | else | |
a92713e6 | 5561 | return FALSE; |
364215c8 RS |
5562 | |
5563 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) | |
5564 | { | |
5565 | mask &= ~(7 << 3); | |
5566 | mask |= (5 + regno2) << 3; | |
5567 | } | |
5568 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) | |
5569 | mask |= (regno2 - 3) << 3; | |
5570 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) | |
5571 | mask |= (regno2 - 15) << 1; | |
5572 | else if (regno1 == RA && regno2 == RA) | |
5573 | mask |= 1; | |
5574 | else | |
a92713e6 | 5575 | return FALSE; |
364215c8 | 5576 | } |
a92713e6 RS |
5577 | while (match_char (arg, ',')); |
5578 | ||
364215c8 | 5579 | insn_insert_operand (arg->insn, operand, mask); |
a92713e6 | 5580 | return TRUE; |
364215c8 RS |
5581 | } |
5582 | ||
38bf472a MR |
5583 | /* Encode regular MIPS SAVE/RESTORE instruction operands according to |
5584 | the argument register mask AMASK, the number of static registers | |
5585 | saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5586 | respectively, and the frame size FRAME_SIZE. */ | |
5587 | ||
5588 | static unsigned int | |
5589 | mips_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5590 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5591 | unsigned int frame_size) | |
5592 | { | |
5593 | return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15) | |
5594 | | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6)); | |
5595 | } | |
5596 | ||
5597 | /* Encode MIPS16 SAVE/RESTORE instruction operands according to the | |
5598 | argument register mask AMASK, the number of static registers saved | |
5599 | NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1 | |
5600 | respectively, and the frame size FRAME_SIZE. */ | |
5601 | ||
5602 | static unsigned int | |
5603 | mips16_encode_save_restore (unsigned int amask, unsigned int nsreg, | |
5604 | unsigned int ra, unsigned int s0, unsigned int s1, | |
5605 | unsigned int frame_size) | |
5606 | { | |
5607 | unsigned int args; | |
5608 | ||
5609 | args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf); | |
5610 | if (nsreg || amask || frame_size == 0 || frame_size > 16) | |
5611 | args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16) | |
5612 | | ((frame_size & 0xf0) << 16)); | |
5613 | return args; | |
5614 | } | |
5615 | ||
364215c8 RS |
5616 | /* OP_SAVE_RESTORE_LIST matcher. */ |
5617 | ||
a92713e6 RS |
5618 | static bfd_boolean |
5619 | match_save_restore_list_operand (struct mips_arg_info *arg) | |
364215c8 RS |
5620 | { |
5621 | unsigned int opcode, args, statics, sregs; | |
5622 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; | |
38bf472a | 5623 | unsigned int arg_mask, ra, s0, s1; |
364215c8 | 5624 | offsetT frame_size; |
364215c8 | 5625 | |
364215c8 RS |
5626 | opcode = arg->insn->insn_opcode; |
5627 | frame_size = 0; | |
5628 | num_frame_sizes = 0; | |
5629 | args = 0; | |
5630 | statics = 0; | |
5631 | sregs = 0; | |
38bf472a MR |
5632 | ra = 0; |
5633 | s0 = 0; | |
5634 | s1 = 0; | |
a92713e6 | 5635 | do |
364215c8 RS |
5636 | { |
5637 | unsigned int regno1, regno2; | |
5638 | ||
a92713e6 | 5639 | if (arg->token->type == OT_INTEGER) |
364215c8 RS |
5640 | { |
5641 | /* Handle the frame size. */ | |
1a00e612 | 5642 | if (!match_const_int (arg, &frame_size)) |
a92713e6 | 5643 | return FALSE; |
364215c8 | 5644 | num_frame_sizes += 1; |
364215c8 RS |
5645 | } |
5646 | else | |
5647 | { | |
a92713e6 RS |
5648 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
5649 | return FALSE; | |
364215c8 RS |
5650 | |
5651 | while (regno1 <= regno2) | |
5652 | { | |
5653 | if (regno1 >= 4 && regno1 <= 7) | |
5654 | { | |
5655 | if (num_frame_sizes == 0) | |
5656 | /* args $a0-$a3 */ | |
5657 | args |= 1 << (regno1 - 4); | |
5658 | else | |
5659 | /* statics $a0-$a3 */ | |
5660 | statics |= 1 << (regno1 - 4); | |
5661 | } | |
5662 | else if (regno1 >= 16 && regno1 <= 23) | |
5663 | /* $s0-$s7 */ | |
5664 | sregs |= 1 << (regno1 - 16); | |
5665 | else if (regno1 == 30) | |
5666 | /* $s8 */ | |
5667 | sregs |= 1 << 8; | |
5668 | else if (regno1 == 31) | |
5669 | /* Add $ra to insn. */ | |
38bf472a | 5670 | ra = 1; |
364215c8 | 5671 | else |
a92713e6 | 5672 | return FALSE; |
364215c8 RS |
5673 | regno1 += 1; |
5674 | if (regno1 == 24) | |
5675 | regno1 = 30; | |
5676 | } | |
5677 | } | |
364215c8 | 5678 | } |
a92713e6 | 5679 | while (match_char (arg, ',')); |
364215c8 RS |
5680 | |
5681 | /* Encode args/statics combination. */ | |
5682 | if (args & statics) | |
a92713e6 | 5683 | return FALSE; |
364215c8 RS |
5684 | else if (args == 0xf) |
5685 | /* All $a0-$a3 are args. */ | |
38bf472a | 5686 | arg_mask = MIPS_SVRS_ALL_ARGS; |
364215c8 RS |
5687 | else if (statics == 0xf) |
5688 | /* All $a0-$a3 are statics. */ | |
38bf472a | 5689 | arg_mask = MIPS_SVRS_ALL_STATICS; |
364215c8 RS |
5690 | else |
5691 | { | |
5692 | /* Count arg registers. */ | |
5693 | num_args = 0; | |
5694 | while (args & 0x1) | |
5695 | { | |
5696 | args >>= 1; | |
5697 | num_args += 1; | |
5698 | } | |
5699 | if (args != 0) | |
a92713e6 | 5700 | return FALSE; |
364215c8 RS |
5701 | |
5702 | /* Count static registers. */ | |
5703 | num_statics = 0; | |
5704 | while (statics & 0x8) | |
5705 | { | |
5706 | statics = (statics << 1) & 0xf; | |
5707 | num_statics += 1; | |
5708 | } | |
5709 | if (statics != 0) | |
a92713e6 | 5710 | return FALSE; |
364215c8 RS |
5711 | |
5712 | /* Encode args/statics. */ | |
38bf472a | 5713 | arg_mask = (num_args << 2) | num_statics; |
364215c8 RS |
5714 | } |
5715 | ||
5716 | /* Encode $s0/$s1. */ | |
5717 | if (sregs & (1 << 0)) /* $s0 */ | |
38bf472a | 5718 | s0 = 1; |
364215c8 | 5719 | if (sregs & (1 << 1)) /* $s1 */ |
38bf472a | 5720 | s1 = 1; |
364215c8 RS |
5721 | sregs >>= 2; |
5722 | ||
5723 | /* Encode $s2-$s8. */ | |
5724 | num_sregs = 0; | |
5725 | while (sregs & 1) | |
5726 | { | |
5727 | sregs >>= 1; | |
5728 | num_sregs += 1; | |
5729 | } | |
5730 | if (sregs != 0) | |
a92713e6 | 5731 | return FALSE; |
364215c8 RS |
5732 | |
5733 | /* Encode frame size. */ | |
5734 | if (num_frame_sizes == 0) | |
1a00e612 RS |
5735 | { |
5736 | set_insn_error (arg->argnum, _("missing frame size")); | |
5737 | return FALSE; | |
5738 | } | |
5739 | if (num_frame_sizes > 1) | |
5740 | { | |
5741 | set_insn_error (arg->argnum, _("frame size specified twice")); | |
5742 | return FALSE; | |
5743 | } | |
5744 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) | |
5745 | { | |
5746 | set_insn_error (arg->argnum, _("invalid frame size")); | |
5747 | return FALSE; | |
5748 | } | |
38bf472a | 5749 | frame_size /= 8; |
364215c8 | 5750 | |
364215c8 | 5751 | /* Finally build the instruction. */ |
38bf472a MR |
5752 | if (mips_opts.mips16) |
5753 | opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5754 | frame_size); | |
5755 | else if (!mips_opts.micromips) | |
5756 | opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1, | |
5757 | frame_size); | |
5758 | else | |
5759 | abort (); | |
5760 | ||
364215c8 | 5761 | arg->insn->insn_opcode = opcode; |
a92713e6 | 5762 | return TRUE; |
364215c8 RS |
5763 | } |
5764 | ||
a1d78564 RS |
5765 | /* OP_MDMX_IMM_REG matcher. */ |
5766 | ||
a92713e6 | 5767 | static bfd_boolean |
a1d78564 | 5768 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
a92713e6 | 5769 | const struct mips_operand *operand) |
a1d78564 | 5770 | { |
a92713e6 | 5771 | unsigned int regno, uval; |
a1d78564 RS |
5772 | bfd_boolean is_qh; |
5773 | const struct mips_opcode *opcode; | |
5774 | ||
5775 | /* The mips_opcode records whether this is an octobyte or quadhalf | |
5776 | instruction. Start out with that bit in place. */ | |
5777 | opcode = arg->insn->insn_mo; | |
5778 | uval = mips_extract_operand (operand, opcode->match); | |
5779 | is_qh = (uval != 0); | |
5780 | ||
56d438b1 | 5781 | if (arg->token->type == OT_REG) |
a1d78564 RS |
5782 | { |
5783 | if ((opcode->membership & INSN_5400) | |
5784 | && strcmp (opcode->name, "rzu.ob") == 0) | |
5785 | { | |
1a00e612 RS |
5786 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
5787 | arg->argnum); | |
5788 | return FALSE; | |
a1d78564 RS |
5789 | } |
5790 | ||
56d438b1 CF |
5791 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
5792 | return FALSE; | |
5793 | ++arg->token; | |
5794 | ||
a1d78564 RS |
5795 | /* Check whether this is a vector register or a broadcast of |
5796 | a single element. */ | |
56d438b1 | 5797 | if (arg->token->type == OT_INTEGER_INDEX) |
a1d78564 | 5798 | { |
56d438b1 | 5799 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
a1d78564 | 5800 | { |
1a00e612 RS |
5801 | set_insn_error (arg->argnum, _("invalid element selector")); |
5802 | return FALSE; | |
a1d78564 | 5803 | } |
56d438b1 CF |
5804 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
5805 | ++arg->token; | |
a1d78564 RS |
5806 | } |
5807 | else | |
5808 | { | |
5809 | /* A full vector. */ | |
5810 | if ((opcode->membership & INSN_5400) | |
5811 | && (strcmp (opcode->name, "sll.ob") == 0 | |
5812 | || strcmp (opcode->name, "srl.ob") == 0)) | |
5813 | { | |
1a00e612 RS |
5814 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
5815 | arg->argnum); | |
5816 | return FALSE; | |
a1d78564 RS |
5817 | } |
5818 | ||
5819 | if (is_qh) | |
5820 | uval |= MDMX_FMTSEL_VEC_QH << 5; | |
5821 | else | |
5822 | uval |= MDMX_FMTSEL_VEC_OB << 5; | |
5823 | } | |
a1d78564 RS |
5824 | uval |= regno; |
5825 | } | |
5826 | else | |
5827 | { | |
5828 | offsetT sval; | |
5829 | ||
1a00e612 | 5830 | if (!match_const_int (arg, &sval)) |
a92713e6 | 5831 | return FALSE; |
a1d78564 RS |
5832 | if (sval < 0 || sval > 31) |
5833 | { | |
1a00e612 RS |
5834 | match_out_of_range (arg); |
5835 | return FALSE; | |
a1d78564 RS |
5836 | } |
5837 | uval |= (sval & 31); | |
5838 | if (is_qh) | |
5839 | uval |= MDMX_FMTSEL_IMM_QH << 5; | |
5840 | else | |
5841 | uval |= MDMX_FMTSEL_IMM_OB << 5; | |
5842 | } | |
5843 | insn_insert_operand (arg->insn, operand, uval); | |
a92713e6 | 5844 | return TRUE; |
a1d78564 RS |
5845 | } |
5846 | ||
56d438b1 CF |
5847 | /* OP_IMM_INDEX matcher. */ |
5848 | ||
5849 | static bfd_boolean | |
5850 | match_imm_index_operand (struct mips_arg_info *arg, | |
5851 | const struct mips_operand *operand) | |
5852 | { | |
5853 | unsigned int max_val; | |
5854 | ||
5855 | if (arg->token->type != OT_INTEGER_INDEX) | |
5856 | return FALSE; | |
5857 | ||
5858 | max_val = (1 << operand->size) - 1; | |
5859 | if (arg->token->u.index > max_val) | |
5860 | { | |
5861 | match_out_of_range (arg); | |
5862 | return FALSE; | |
5863 | } | |
5864 | insn_insert_operand (arg->insn, operand, arg->token->u.index); | |
5865 | ++arg->token; | |
5866 | return TRUE; | |
5867 | } | |
5868 | ||
5869 | /* OP_REG_INDEX matcher. */ | |
5870 | ||
5871 | static bfd_boolean | |
5872 | match_reg_index_operand (struct mips_arg_info *arg, | |
5873 | const struct mips_operand *operand) | |
5874 | { | |
5875 | unsigned int regno; | |
5876 | ||
5877 | if (arg->token->type != OT_REG_INDEX) | |
5878 | return FALSE; | |
5879 | ||
5880 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) | |
5881 | return FALSE; | |
5882 | ||
5883 | insn_insert_operand (arg->insn, operand, regno); | |
5884 | ++arg->token; | |
5885 | return TRUE; | |
5886 | } | |
5887 | ||
a1d78564 RS |
5888 | /* OP_PC matcher. */ |
5889 | ||
a92713e6 RS |
5890 | static bfd_boolean |
5891 | match_pc_operand (struct mips_arg_info *arg) | |
a1d78564 | 5892 | { |
a92713e6 RS |
5893 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
5894 | { | |
5895 | ++arg->token; | |
5896 | return TRUE; | |
5897 | } | |
5898 | return FALSE; | |
a1d78564 RS |
5899 | } |
5900 | ||
25499ac7 MR |
5901 | /* OP_REG28 matcher. */ |
5902 | ||
5903 | static bfd_boolean | |
5904 | match_reg28_operand (struct mips_arg_info *arg) | |
5905 | { | |
5906 | unsigned int regno; | |
5907 | ||
5908 | if (arg->token->type == OT_REG | |
5909 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) | |
5910 | && regno == GP) | |
5911 | { | |
5912 | ++arg->token; | |
5913 | return TRUE; | |
5914 | } | |
5915 | return FALSE; | |
5916 | } | |
5917 | ||
7361da2c AB |
5918 | /* OP_NON_ZERO_REG matcher. */ |
5919 | ||
5920 | static bfd_boolean | |
5921 | match_non_zero_reg_operand (struct mips_arg_info *arg, | |
5922 | const struct mips_operand *operand) | |
5923 | { | |
5924 | unsigned int regno; | |
5925 | ||
5926 | if (!match_reg (arg, OP_REG_GP, ®no)) | |
5927 | return FALSE; | |
5928 | ||
5929 | if (regno == 0) | |
5930 | return FALSE; | |
5931 | ||
5932 | arg->last_regno = regno; | |
5933 | insn_insert_operand (arg->insn, operand, regno); | |
5934 | return TRUE; | |
5935 | } | |
5936 | ||
a1d78564 RS |
5937 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
5938 | register that we need to match. */ | |
5939 | ||
a92713e6 RS |
5940 | static bfd_boolean |
5941 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) | |
a1d78564 RS |
5942 | { |
5943 | unsigned int regno; | |
5944 | ||
a92713e6 | 5945 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
a1d78564 RS |
5946 | } |
5947 | ||
33f46696 MR |
5948 | /* Try to match a floating-point constant from ARG for LI.S or LI.D. |
5949 | LENGTH is the length of the value in bytes (4 for float, 8 for double) | |
5950 | and USING_GPRS says whether the destination is a GPR rather than an FPR. | |
89565f1b RS |
5951 | |
5952 | Return the constant in IMM and OFFSET as follows: | |
5953 | ||
5954 | - If the constant should be loaded via memory, set IMM to O_absent and | |
5955 | OFFSET to the memory address. | |
5956 | ||
5957 | - Otherwise, if the constant should be loaded into two 32-bit registers, | |
5958 | set IMM to the O_constant to load into the high register and OFFSET | |
5959 | to the corresponding value for the low register. | |
5960 | ||
5961 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. | |
5962 | ||
5963 | These constants only appear as the last operand in an instruction, | |
5964 | and every instruction that accepts them in any variant accepts them | |
5965 | in all variants. This means we don't have to worry about backing out | |
5966 | any changes if the instruction does not match. We just match | |
5967 | unconditionally and report an error if the constant is invalid. */ | |
5968 | ||
a92713e6 RS |
5969 | static bfd_boolean |
5970 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, | |
5971 | expressionS *offset, int length, bfd_boolean using_gprs) | |
89565f1b | 5972 | { |
a92713e6 | 5973 | char *p; |
89565f1b RS |
5974 | segT seg, new_seg; |
5975 | subsegT subseg; | |
5976 | const char *newname; | |
a92713e6 | 5977 | unsigned char *data; |
89565f1b RS |
5978 | |
5979 | /* Where the constant is placed is based on how the MIPS assembler | |
5980 | does things: | |
5981 | ||
5982 | length == 4 && using_gprs -- immediate value only | |
5983 | length == 8 && using_gprs -- .rdata or immediate value | |
5984 | length == 4 && !using_gprs -- .lit4 or immediate value | |
5985 | length == 8 && !using_gprs -- .lit8 or immediate value | |
5986 | ||
5987 | The .lit4 and .lit8 sections are only used if permitted by the | |
5988 | -G argument. */ | |
a92713e6 | 5989 | if (arg->token->type != OT_FLOAT) |
1a00e612 RS |
5990 | { |
5991 | set_insn_error (arg->argnum, _("floating-point expression required")); | |
5992 | return FALSE; | |
5993 | } | |
a92713e6 RS |
5994 | |
5995 | gas_assert (arg->token->u.flt.length == length); | |
5996 | data = arg->token->u.flt.data; | |
5997 | ++arg->token; | |
89565f1b RS |
5998 | |
5999 | /* Handle 32-bit constants for which an immediate value is best. */ | |
6000 | if (length == 4 | |
6001 | && (using_gprs | |
6002 | || g_switch_value < 4 | |
6003 | || (data[0] == 0 && data[1] == 0) | |
6004 | || (data[2] == 0 && data[3] == 0))) | |
6005 | { | |
6006 | imm->X_op = O_constant; | |
6007 | if (!target_big_endian) | |
6008 | imm->X_add_number = bfd_getl32 (data); | |
6009 | else | |
6010 | imm->X_add_number = bfd_getb32 (data); | |
6011 | offset->X_op = O_absent; | |
a92713e6 | 6012 | return TRUE; |
89565f1b RS |
6013 | } |
6014 | ||
6015 | /* Handle 64-bit constants for which an immediate value is best. */ | |
6016 | if (length == 8 | |
6017 | && !mips_disable_float_construction | |
351cdf24 MF |
6018 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
6019 | GPRs are at least as wide as the FPRs or MTHC1 is available. | |
6020 | Unlike most tests for 32-bit floating-point registers this check | |
6021 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not | |
6022 | permit 64-bit moves without MXHC1. | |
6023 | Force the constant into memory otherwise. */ | |
6024 | && (using_gprs | |
6025 | || GPR_SIZE == 64 | |
6026 | || ISA_HAS_MXHC1 (mips_opts.isa) | |
6027 | || FPR_SIZE == 32) | |
89565f1b RS |
6028 | && ((data[0] == 0 && data[1] == 0) |
6029 | || (data[2] == 0 && data[3] == 0)) | |
6030 | && ((data[4] == 0 && data[5] == 0) | |
6031 | || (data[6] == 0 && data[7] == 0))) | |
6032 | { | |
6033 | /* The value is simple enough to load with a couple of instructions. | |
6034 | If using 32-bit registers, set IMM to the high order 32 bits and | |
6035 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire | |
6036 | 64 bit constant. */ | |
351cdf24 | 6037 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
89565f1b RS |
6038 | { |
6039 | imm->X_op = O_constant; | |
6040 | offset->X_op = O_constant; | |
6041 | if (!target_big_endian) | |
6042 | { | |
6043 | imm->X_add_number = bfd_getl32 (data + 4); | |
6044 | offset->X_add_number = bfd_getl32 (data); | |
6045 | } | |
6046 | else | |
6047 | { | |
6048 | imm->X_add_number = bfd_getb32 (data); | |
6049 | offset->X_add_number = bfd_getb32 (data + 4); | |
6050 | } | |
6051 | if (offset->X_add_number == 0) | |
6052 | offset->X_op = O_absent; | |
6053 | } | |
6054 | else | |
6055 | { | |
6056 | imm->X_op = O_constant; | |
6057 | if (!target_big_endian) | |
6058 | imm->X_add_number = bfd_getl64 (data); | |
6059 | else | |
6060 | imm->X_add_number = bfd_getb64 (data); | |
6061 | offset->X_op = O_absent; | |
6062 | } | |
a92713e6 | 6063 | return TRUE; |
89565f1b RS |
6064 | } |
6065 | ||
6066 | /* Switch to the right section. */ | |
6067 | seg = now_seg; | |
6068 | subseg = now_subseg; | |
6069 | if (length == 4) | |
6070 | { | |
6071 | gas_assert (!using_gprs && g_switch_value >= 4); | |
6072 | newname = ".lit4"; | |
6073 | } | |
6074 | else | |
6075 | { | |
6076 | if (using_gprs || g_switch_value < 8) | |
6077 | newname = RDATA_SECTION_NAME; | |
6078 | else | |
6079 | newname = ".lit8"; | |
6080 | } | |
6081 | ||
6082 | new_seg = subseg_new (newname, (subsegT) 0); | |
6083 | bfd_set_section_flags (stdoutput, new_seg, | |
6084 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); | |
6085 | frag_align (length == 4 ? 2 : 3, 0, 0); | |
6086 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
6087 | record_alignment (new_seg, 4); | |
6088 | else | |
6089 | record_alignment (new_seg, length == 4 ? 2 : 3); | |
6090 | if (seg == now_seg) | |
1661c76c | 6091 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
89565f1b RS |
6092 | |
6093 | /* Set the argument to the current address in the section. */ | |
6094 | imm->X_op = O_absent; | |
6095 | offset->X_op = O_symbol; | |
6096 | offset->X_add_symbol = symbol_temp_new_now (); | |
6097 | offset->X_add_number = 0; | |
6098 | ||
6099 | /* Put the floating point number into the section. */ | |
6100 | p = frag_more (length); | |
6101 | memcpy (p, data, length); | |
6102 | ||
6103 | /* Switch back to the original section. */ | |
6104 | subseg_set (seg, subseg); | |
a92713e6 | 6105 | return TRUE; |
89565f1b RS |
6106 | } |
6107 | ||
14daeee3 RS |
6108 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
6109 | them. */ | |
6110 | ||
6111 | static bfd_boolean | |
6112 | match_vu0_suffix_operand (struct mips_arg_info *arg, | |
6113 | const struct mips_operand *operand, | |
6114 | bfd_boolean match_p) | |
6115 | { | |
6116 | unsigned int uval; | |
6117 | ||
6118 | /* The operand can be an XYZW mask or a single 2-bit channel index | |
6119 | (with X being 0). */ | |
6120 | gas_assert (operand->size == 2 || operand->size == 4); | |
6121 | ||
ee5734f0 | 6122 | /* The suffix can be omitted when it is already part of the opcode. */ |
14daeee3 | 6123 | if (arg->token->type != OT_CHANNELS) |
ee5734f0 | 6124 | return match_p; |
14daeee3 RS |
6125 | |
6126 | uval = arg->token->u.channels; | |
6127 | if (operand->size == 2) | |
6128 | { | |
6129 | /* Check that a single bit is set and convert it into a 2-bit index. */ | |
6130 | if ((uval & -uval) != uval) | |
6131 | return FALSE; | |
6132 | uval = 4 - ffs (uval); | |
6133 | } | |
6134 | ||
6135 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) | |
6136 | return FALSE; | |
6137 | ||
6138 | ++arg->token; | |
6139 | if (!match_p) | |
6140 | insn_insert_operand (arg->insn, operand, uval); | |
6141 | return TRUE; | |
6142 | } | |
6143 | ||
33f46696 MR |
6144 | /* Try to match a token from ARG against OPERAND. Consume the token |
6145 | and return true on success, otherwise return false. */ | |
a1d78564 | 6146 | |
a92713e6 | 6147 | static bfd_boolean |
a1d78564 | 6148 | match_operand (struct mips_arg_info *arg, |
a92713e6 | 6149 | const struct mips_operand *operand) |
a1d78564 RS |
6150 | { |
6151 | switch (operand->type) | |
6152 | { | |
6153 | case OP_INT: | |
a92713e6 | 6154 | return match_int_operand (arg, operand); |
a1d78564 RS |
6155 | |
6156 | case OP_MAPPED_INT: | |
a92713e6 | 6157 | return match_mapped_int_operand (arg, operand); |
a1d78564 RS |
6158 | |
6159 | case OP_MSB: | |
a92713e6 | 6160 | return match_msb_operand (arg, operand); |
a1d78564 RS |
6161 | |
6162 | case OP_REG: | |
0f35dbc4 | 6163 | case OP_OPTIONAL_REG: |
a92713e6 | 6164 | return match_reg_operand (arg, operand); |
a1d78564 RS |
6165 | |
6166 | case OP_REG_PAIR: | |
a92713e6 | 6167 | return match_reg_pair_operand (arg, operand); |
a1d78564 RS |
6168 | |
6169 | case OP_PCREL: | |
a92713e6 | 6170 | return match_pcrel_operand (arg); |
a1d78564 RS |
6171 | |
6172 | case OP_PERF_REG: | |
a92713e6 | 6173 | return match_perf_reg_operand (arg, operand); |
a1d78564 RS |
6174 | |
6175 | case OP_ADDIUSP_INT: | |
a92713e6 | 6176 | return match_addiusp_operand (arg, operand); |
a1d78564 RS |
6177 | |
6178 | case OP_CLO_CLZ_DEST: | |
a92713e6 | 6179 | return match_clo_clz_dest_operand (arg, operand); |
a1d78564 RS |
6180 | |
6181 | case OP_LWM_SWM_LIST: | |
a92713e6 | 6182 | return match_lwm_swm_list_operand (arg, operand); |
a1d78564 RS |
6183 | |
6184 | case OP_ENTRY_EXIT_LIST: | |
a92713e6 | 6185 | return match_entry_exit_operand (arg, operand); |
364215c8 | 6186 | |
a1d78564 | 6187 | case OP_SAVE_RESTORE_LIST: |
a92713e6 | 6188 | return match_save_restore_list_operand (arg); |
a1d78564 RS |
6189 | |
6190 | case OP_MDMX_IMM_REG: | |
a92713e6 | 6191 | return match_mdmx_imm_reg_operand (arg, operand); |
a1d78564 RS |
6192 | |
6193 | case OP_REPEAT_DEST_REG: | |
a92713e6 | 6194 | return match_tied_reg_operand (arg, arg->dest_regno); |
a1d78564 RS |
6195 | |
6196 | case OP_REPEAT_PREV_REG: | |
a92713e6 | 6197 | return match_tied_reg_operand (arg, arg->last_regno); |
a1d78564 RS |
6198 | |
6199 | case OP_PC: | |
a92713e6 | 6200 | return match_pc_operand (arg); |
14daeee3 | 6201 | |
25499ac7 MR |
6202 | case OP_REG28: |
6203 | return match_reg28_operand (arg); | |
6204 | ||
14daeee3 RS |
6205 | case OP_VU0_SUFFIX: |
6206 | return match_vu0_suffix_operand (arg, operand, FALSE); | |
6207 | ||
6208 | case OP_VU0_MATCH_SUFFIX: | |
6209 | return match_vu0_suffix_operand (arg, operand, TRUE); | |
56d438b1 CF |
6210 | |
6211 | case OP_IMM_INDEX: | |
6212 | return match_imm_index_operand (arg, operand); | |
6213 | ||
6214 | case OP_REG_INDEX: | |
6215 | return match_reg_index_operand (arg, operand); | |
7361da2c AB |
6216 | |
6217 | case OP_SAME_RS_RT: | |
6218 | return match_same_rs_rt_operand (arg, operand); | |
6219 | ||
6220 | case OP_CHECK_PREV: | |
6221 | return match_check_prev_operand (arg, operand); | |
6222 | ||
6223 | case OP_NON_ZERO_REG: | |
6224 | return match_non_zero_reg_operand (arg, operand); | |
a1d78564 RS |
6225 | } |
6226 | abort (); | |
6227 | } | |
6228 | ||
6229 | /* ARG is the state after successfully matching an instruction. | |
6230 | Issue any queued-up warnings. */ | |
6231 | ||
6232 | static void | |
6233 | check_completed_insn (struct mips_arg_info *arg) | |
6234 | { | |
6235 | if (arg->seen_at) | |
6236 | { | |
6237 | if (AT == ATREG) | |
1661c76c | 6238 | as_warn (_("used $at without \".set noat\"")); |
a1d78564 | 6239 | else |
1661c76c | 6240 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
a1d78564 RS |
6241 | } |
6242 | } | |
a1d78564 | 6243 | |
85fcb30f RS |
6244 | /* Return true if modifying general-purpose register REG needs a delay. */ |
6245 | ||
6246 | static bfd_boolean | |
6247 | reg_needs_delay (unsigned int reg) | |
6248 | { | |
6249 | unsigned long prev_pinfo; | |
6250 | ||
6251 | prev_pinfo = history[0].insn_mo->pinfo; | |
6252 | if (!mips_opts.noreorder | |
67dc82bc | 6253 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
43885403 | 6254 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
85fcb30f RS |
6255 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
6256 | return TRUE; | |
6257 | ||
6258 | return FALSE; | |
6259 | } | |
6260 | ||
71400594 RS |
6261 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
6262 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected | |
6263 | by VR4120 errata. */ | |
4d7206a2 | 6264 | |
71400594 RS |
6265 | static unsigned int |
6266 | classify_vr4120_insn (const char *name) | |
252b5132 | 6267 | { |
71400594 RS |
6268 | if (strncmp (name, "macc", 4) == 0) |
6269 | return FIX_VR4120_MACC; | |
6270 | if (strncmp (name, "dmacc", 5) == 0) | |
6271 | return FIX_VR4120_DMACC; | |
6272 | if (strncmp (name, "mult", 4) == 0) | |
6273 | return FIX_VR4120_MULT; | |
6274 | if (strncmp (name, "dmult", 5) == 0) | |
6275 | return FIX_VR4120_DMULT; | |
6276 | if (strstr (name, "div")) | |
6277 | return FIX_VR4120_DIV; | |
6278 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) | |
6279 | return FIX_VR4120_MTHILO; | |
6280 | return NUM_FIX_VR4120_CLASSES; | |
6281 | } | |
252b5132 | 6282 | |
a8d14a88 CM |
6283 | #define INSN_ERET 0x42000018 |
6284 | #define INSN_DERET 0x4200001f | |
6285 | #define INSN_DMULT 0x1c | |
6286 | #define INSN_DMULTU 0x1d | |
ff239038 | 6287 | |
71400594 RS |
6288 | /* Return the number of instructions that must separate INSN1 and INSN2, |
6289 | where INSN1 is the earlier instruction. Return the worst-case value | |
6290 | for any INSN2 if INSN2 is null. */ | |
252b5132 | 6291 | |
71400594 RS |
6292 | static unsigned int |
6293 | insns_between (const struct mips_cl_insn *insn1, | |
6294 | const struct mips_cl_insn *insn2) | |
6295 | { | |
6296 | unsigned long pinfo1, pinfo2; | |
4c260379 | 6297 | unsigned int mask; |
71400594 | 6298 | |
85fcb30f RS |
6299 | /* If INFO2 is null, pessimistically assume that all flags are set for |
6300 | the second instruction. */ | |
71400594 RS |
6301 | pinfo1 = insn1->insn_mo->pinfo; |
6302 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; | |
252b5132 | 6303 | |
71400594 RS |
6304 | /* For most targets, write-after-read dependencies on the HI and LO |
6305 | registers must be separated by at least two instructions. */ | |
6306 | if (!hilo_interlocks) | |
252b5132 | 6307 | { |
71400594 RS |
6308 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
6309 | return 2; | |
6310 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) | |
6311 | return 2; | |
6312 | } | |
6313 | ||
6314 | /* If we're working around r7000 errata, there must be two instructions | |
6315 | between an mfhi or mflo and any instruction that uses the result. */ | |
6316 | if (mips_7000_hilo_fix | |
df58fc94 | 6317 | && !mips_opts.micromips |
71400594 | 6318 | && MF_HILO_INSN (pinfo1) |
85fcb30f | 6319 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
71400594 RS |
6320 | return 2; |
6321 | ||
ff239038 CM |
6322 | /* If we're working around 24K errata, one instruction is required |
6323 | if an ERET or DERET is followed by a branch instruction. */ | |
df58fc94 | 6324 | if (mips_fix_24k && !mips_opts.micromips) |
ff239038 CM |
6325 | { |
6326 | if (insn1->insn_opcode == INSN_ERET | |
6327 | || insn1->insn_opcode == INSN_DERET) | |
6328 | { | |
6329 | if (insn2 == NULL | |
6330 | || insn2->insn_opcode == INSN_ERET | |
6331 | || insn2->insn_opcode == INSN_DERET | |
11625dd8 | 6332 | || delayed_branch_p (insn2)) |
ff239038 CM |
6333 | return 1; |
6334 | } | |
6335 | } | |
6336 | ||
a8d14a88 CM |
6337 | /* If we're working around PMC RM7000 errata, there must be three |
6338 | nops between a dmult and a load instruction. */ | |
6339 | if (mips_fix_rm7000 && !mips_opts.micromips) | |
6340 | { | |
6341 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT | |
6342 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) | |
6343 | { | |
6344 | if (pinfo2 & INSN_LOAD_MEMORY) | |
6345 | return 3; | |
6346 | } | |
6347 | } | |
6348 | ||
71400594 RS |
6349 | /* If working around VR4120 errata, check for combinations that need |
6350 | a single intervening instruction. */ | |
df58fc94 | 6351 | if (mips_fix_vr4120 && !mips_opts.micromips) |
71400594 RS |
6352 | { |
6353 | unsigned int class1, class2; | |
252b5132 | 6354 | |
71400594 RS |
6355 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
6356 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) | |
252b5132 | 6357 | { |
71400594 RS |
6358 | if (insn2 == NULL) |
6359 | return 1; | |
6360 | class2 = classify_vr4120_insn (insn2->insn_mo->name); | |
6361 | if (vr4120_conflicts[class1] & (1 << class2)) | |
6362 | return 1; | |
252b5132 | 6363 | } |
71400594 RS |
6364 | } |
6365 | ||
df58fc94 | 6366 | if (!HAVE_CODE_COMPRESSION) |
71400594 RS |
6367 | { |
6368 | /* Check for GPR or coprocessor load delays. All such delays | |
6369 | are on the RT register. */ | |
6370 | /* Itbl support may require additional care here. */ | |
67dc82bc | 6371 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
43885403 | 6372 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
252b5132 | 6373 | { |
85fcb30f | 6374 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
71400594 RS |
6375 | return 1; |
6376 | } | |
6377 | ||
6378 | /* Check for generic coprocessor hazards. | |
6379 | ||
6380 | This case is not handled very well. There is no special | |
6381 | knowledge of CP0 handling, and the coprocessors other than | |
6382 | the floating point unit are not distinguished at all. */ | |
6383 | /* Itbl support may require additional care here. FIXME! | |
6384 | Need to modify this to include knowledge about | |
6385 | user specified delays! */ | |
43885403 | 6386 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
71400594 RS |
6387 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
6388 | { | |
6389 | /* Handle cases where INSN1 writes to a known general coprocessor | |
6390 | register. There must be a one instruction delay before INSN2 | |
6391 | if INSN2 reads that register, otherwise no delay is needed. */ | |
4c260379 RS |
6392 | mask = fpr_write_mask (insn1); |
6393 | if (mask != 0) | |
252b5132 | 6394 | { |
4c260379 | 6395 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
71400594 | 6396 | return 1; |
252b5132 RH |
6397 | } |
6398 | else | |
6399 | { | |
71400594 RS |
6400 | /* Read-after-write dependencies on the control registers |
6401 | require a two-instruction gap. */ | |
6402 | if ((pinfo1 & INSN_WRITE_COND_CODE) | |
6403 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6404 | return 2; | |
6405 | ||
6406 | /* We don't know exactly what INSN1 does. If INSN2 is | |
6407 | also a coprocessor instruction, assume there must be | |
6408 | a one instruction gap. */ | |
6409 | if (pinfo2 & INSN_COP) | |
6410 | return 1; | |
252b5132 RH |
6411 | } |
6412 | } | |
6b76fefe | 6413 | |
71400594 RS |
6414 | /* Check for read-after-write dependencies on the coprocessor |
6415 | control registers in cases where INSN1 does not need a general | |
6416 | coprocessor delay. This means that INSN1 is a floating point | |
6417 | comparison instruction. */ | |
6418 | /* Itbl support may require additional care here. */ | |
6419 | else if (!cop_interlocks | |
6420 | && (pinfo1 & INSN_WRITE_COND_CODE) | |
6421 | && (pinfo2 & INSN_READ_COND_CODE)) | |
6422 | return 1; | |
6423 | } | |
6b76fefe | 6424 | |
7361da2c AB |
6425 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
6426 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait | |
6427 | and pause. */ | |
6428 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) | |
6429 | && ((pinfo2 & INSN_NO_DELAY_SLOT) | |
6430 | || (insn2 && delayed_branch_p (insn2)))) | |
6431 | return 1; | |
6432 | ||
71400594 RS |
6433 | return 0; |
6434 | } | |
6b76fefe | 6435 | |
7d8e00cf RS |
6436 | /* Return the number of nops that would be needed to work around the |
6437 | VR4130 mflo/mfhi errata if instruction INSN immediately followed | |
932d1a1b RS |
6438 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
6439 | that are contained within the first IGNORE instructions of HIST. */ | |
7d8e00cf RS |
6440 | |
6441 | static int | |
932d1a1b | 6442 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
7d8e00cf RS |
6443 | const struct mips_cl_insn *insn) |
6444 | { | |
4c260379 RS |
6445 | int i, j; |
6446 | unsigned int mask; | |
7d8e00cf RS |
6447 | |
6448 | /* Check if the instruction writes to HI or LO. MTHI and MTLO | |
6449 | are not affected by the errata. */ | |
6450 | if (insn != 0 | |
6451 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 | |
6452 | || strcmp (insn->insn_mo->name, "mtlo") == 0 | |
6453 | || strcmp (insn->insn_mo->name, "mthi") == 0)) | |
6454 | return 0; | |
6455 | ||
6456 | /* Search for the first MFLO or MFHI. */ | |
6457 | for (i = 0; i < MAX_VR4130_NOPS; i++) | |
91d6fa6a | 6458 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
7d8e00cf RS |
6459 | { |
6460 | /* Extract the destination register. */ | |
4c260379 | 6461 | mask = gpr_write_mask (&hist[i]); |
7d8e00cf RS |
6462 | |
6463 | /* No nops are needed if INSN reads that register. */ | |
4c260379 | 6464 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
7d8e00cf RS |
6465 | return 0; |
6466 | ||
6467 | /* ...or if any of the intervening instructions do. */ | |
6468 | for (j = 0; j < i; j++) | |
4c260379 | 6469 | if (gpr_read_mask (&hist[j]) & mask) |
7d8e00cf RS |
6470 | return 0; |
6471 | ||
932d1a1b RS |
6472 | if (i >= ignore) |
6473 | return MAX_VR4130_NOPS - i; | |
7d8e00cf RS |
6474 | } |
6475 | return 0; | |
6476 | } | |
6477 | ||
134c0c8b MR |
6478 | #define BASE_REG_EQ(INSN1, INSN2) \ |
6479 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ | |
15be625d CM |
6480 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
6481 | ||
6482 | /* Return the minimum alignment for this store instruction. */ | |
6483 | ||
6484 | static int | |
6485 | fix_24k_align_to (const struct mips_opcode *mo) | |
6486 | { | |
6487 | if (strcmp (mo->name, "sh") == 0) | |
6488 | return 2; | |
6489 | ||
6490 | if (strcmp (mo->name, "swc1") == 0 | |
6491 | || strcmp (mo->name, "swc2") == 0 | |
6492 | || strcmp (mo->name, "sw") == 0 | |
6493 | || strcmp (mo->name, "sc") == 0 | |
6494 | || strcmp (mo->name, "s.s") == 0) | |
6495 | return 4; | |
6496 | ||
6497 | if (strcmp (mo->name, "sdc1") == 0 | |
6498 | || strcmp (mo->name, "sdc2") == 0 | |
6499 | || strcmp (mo->name, "s.d") == 0) | |
6500 | return 8; | |
6501 | ||
6502 | /* sb, swl, swr */ | |
6503 | return 1; | |
6504 | } | |
6505 | ||
6506 | struct fix_24k_store_info | |
6507 | { | |
6508 | /* Immediate offset, if any, for this store instruction. */ | |
6509 | short off; | |
6510 | /* Alignment required by this store instruction. */ | |
6511 | int align_to; | |
6512 | /* True for register offsets. */ | |
6513 | int register_offset; | |
6514 | }; | |
6515 | ||
6516 | /* Comparison function used by qsort. */ | |
6517 | ||
6518 | static int | |
6519 | fix_24k_sort (const void *a, const void *b) | |
6520 | { | |
6521 | const struct fix_24k_store_info *pos1 = a; | |
6522 | const struct fix_24k_store_info *pos2 = b; | |
6523 | ||
6524 | return (pos1->off - pos2->off); | |
6525 | } | |
6526 | ||
6527 | /* INSN is a store instruction. Try to record the store information | |
6528 | in STINFO. Return false if the information isn't known. */ | |
6529 | ||
6530 | static bfd_boolean | |
6531 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, | |
ab9794cf | 6532 | const struct mips_cl_insn *insn) |
15be625d CM |
6533 | { |
6534 | /* The instruction must have a known offset. */ | |
6535 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) | |
6536 | return FALSE; | |
6537 | ||
6538 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; | |
6539 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); | |
6540 | return TRUE; | |
6541 | } | |
6542 | ||
932d1a1b RS |
6543 | /* Return the number of nops that would be needed to work around the 24k |
6544 | "lost data on stores during refill" errata if instruction INSN | |
6545 | immediately followed the 2 instructions described by HIST. | |
6546 | Ignore hazards that are contained within the first IGNORE | |
6547 | instructions of HIST. | |
6548 | ||
6549 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer | |
6550 | for the data cache refills and store data. The following describes | |
6551 | the scenario where the store data could be lost. | |
6552 | ||
6553 | * A data cache miss, due to either a load or a store, causing fill | |
6554 | data to be supplied by the memory subsystem | |
6555 | * The first three doublewords of fill data are returned and written | |
6556 | into the cache | |
6557 | * A sequence of four stores occurs in consecutive cycles around the | |
6558 | final doubleword of the fill: | |
6559 | * Store A | |
6560 | * Store B | |
6561 | * Store C | |
6562 | * Zero, One or more instructions | |
6563 | * Store D | |
6564 | ||
6565 | The four stores A-D must be to different doublewords of the line that | |
6566 | is being filled. The fourth instruction in the sequence above permits | |
6567 | the fill of the final doubleword to be transferred from the FSB into | |
6568 | the cache. In the sequence above, the stores may be either integer | |
6569 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, | |
6570 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to | |
6571 | different doublewords on the line. If the floating point unit is | |
6572 | running in 1:2 mode, it is not possible to create the sequence above | |
6573 | using only floating point store instructions. | |
15be625d CM |
6574 | |
6575 | In this case, the cache line being filled is incorrectly marked | |
6576 | invalid, thereby losing the data from any store to the line that | |
6577 | occurs between the original miss and the completion of the five | |
6578 | cycle sequence shown above. | |
6579 | ||
932d1a1b | 6580 | The workarounds are: |
15be625d | 6581 | |
932d1a1b RS |
6582 | * Run the data cache in write-through mode. |
6583 | * Insert a non-store instruction between | |
6584 | Store A and Store B or Store B and Store C. */ | |
3739860c | 6585 | |
15be625d | 6586 | static int |
932d1a1b | 6587 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
15be625d CM |
6588 | const struct mips_cl_insn *insn) |
6589 | { | |
6590 | struct fix_24k_store_info pos[3]; | |
6591 | int align, i, base_offset; | |
6592 | ||
932d1a1b RS |
6593 | if (ignore >= 2) |
6594 | return 0; | |
6595 | ||
ab9794cf RS |
6596 | /* If the previous instruction wasn't a store, there's nothing to |
6597 | worry about. */ | |
15be625d CM |
6598 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
6599 | return 0; | |
6600 | ||
ab9794cf RS |
6601 | /* If the instructions after the previous one are unknown, we have |
6602 | to assume the worst. */ | |
6603 | if (!insn) | |
15be625d CM |
6604 | return 1; |
6605 | ||
ab9794cf RS |
6606 | /* Check whether we are dealing with three consecutive stores. */ |
6607 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 | |
6608 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) | |
15be625d CM |
6609 | return 0; |
6610 | ||
6611 | /* If we don't know the relationship between the store addresses, | |
6612 | assume the worst. */ | |
ab9794cf | 6613 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
15be625d CM |
6614 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
6615 | return 1; | |
6616 | ||
6617 | if (!fix_24k_record_store_info (&pos[0], insn) | |
6618 | || !fix_24k_record_store_info (&pos[1], &hist[0]) | |
6619 | || !fix_24k_record_store_info (&pos[2], &hist[1])) | |
6620 | return 1; | |
6621 | ||
6622 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); | |
6623 | ||
6624 | /* Pick a value of ALIGN and X such that all offsets are adjusted by | |
6625 | X bytes and such that the base register + X is known to be aligned | |
6626 | to align bytes. */ | |
6627 | ||
6628 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) | |
6629 | align = 8; | |
6630 | else | |
6631 | { | |
6632 | align = pos[0].align_to; | |
6633 | base_offset = pos[0].off; | |
6634 | for (i = 1; i < 3; i++) | |
6635 | if (align < pos[i].align_to) | |
6636 | { | |
6637 | align = pos[i].align_to; | |
6638 | base_offset = pos[i].off; | |
6639 | } | |
6640 | for (i = 0; i < 3; i++) | |
6641 | pos[i].off -= base_offset; | |
6642 | } | |
6643 | ||
6644 | pos[0].off &= ~align + 1; | |
6645 | pos[1].off &= ~align + 1; | |
6646 | pos[2].off &= ~align + 1; | |
6647 | ||
6648 | /* If any two stores write to the same chunk, they also write to the | |
6649 | same doubleword. The offsets are still sorted at this point. */ | |
6650 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) | |
6651 | return 0; | |
6652 | ||
6653 | /* A range of at least 9 bytes is needed for the stores to be in | |
6654 | non-overlapping doublewords. */ | |
6655 | if (pos[2].off - pos[0].off <= 8) | |
6656 | return 0; | |
6657 | ||
6658 | if (pos[2].off - pos[1].off >= 24 | |
6659 | || pos[1].off - pos[0].off >= 24 | |
6660 | || pos[2].off - pos[0].off >= 32) | |
6661 | return 0; | |
6662 | ||
6663 | return 1; | |
6664 | } | |
6665 | ||
71400594 | 6666 | /* Return the number of nops that would be needed if instruction INSN |
91d6fa6a | 6667 | immediately followed the MAX_NOPS instructions given by HIST, |
932d1a1b RS |
6668 | where HIST[0] is the most recent instruction. Ignore hazards |
6669 | between INSN and the first IGNORE instructions in HIST. | |
6670 | ||
6671 | If INSN is null, return the worse-case number of nops for any | |
6672 | instruction. */ | |
bdaaa2e1 | 6673 | |
71400594 | 6674 | static int |
932d1a1b | 6675 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6676 | const struct mips_cl_insn *insn) |
6677 | { | |
6678 | int i, nops, tmp_nops; | |
bdaaa2e1 | 6679 | |
71400594 | 6680 | nops = 0; |
932d1a1b | 6681 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
65b02341 | 6682 | { |
91d6fa6a | 6683 | tmp_nops = insns_between (hist + i, insn) - i; |
65b02341 RS |
6684 | if (tmp_nops > nops) |
6685 | nops = tmp_nops; | |
6686 | } | |
7d8e00cf | 6687 | |
df58fc94 | 6688 | if (mips_fix_vr4130 && !mips_opts.micromips) |
7d8e00cf | 6689 | { |
932d1a1b | 6690 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
7d8e00cf RS |
6691 | if (tmp_nops > nops) |
6692 | nops = tmp_nops; | |
6693 | } | |
6694 | ||
df58fc94 | 6695 | if (mips_fix_24k && !mips_opts.micromips) |
15be625d | 6696 | { |
932d1a1b | 6697 | tmp_nops = nops_for_24k (ignore, hist, insn); |
15be625d CM |
6698 | if (tmp_nops > nops) |
6699 | nops = tmp_nops; | |
6700 | } | |
6701 | ||
71400594 RS |
6702 | return nops; |
6703 | } | |
252b5132 | 6704 | |
71400594 | 6705 | /* The variable arguments provide NUM_INSNS extra instructions that |
91d6fa6a | 6706 | might be added to HIST. Return the largest number of nops that |
932d1a1b RS |
6707 | would be needed after the extended sequence, ignoring hazards |
6708 | in the first IGNORE instructions. */ | |
252b5132 | 6709 | |
71400594 | 6710 | static int |
932d1a1b RS |
6711 | nops_for_sequence (int num_insns, int ignore, |
6712 | const struct mips_cl_insn *hist, ...) | |
71400594 RS |
6713 | { |
6714 | va_list args; | |
6715 | struct mips_cl_insn buffer[MAX_NOPS]; | |
6716 | struct mips_cl_insn *cursor; | |
6717 | int nops; | |
6718 | ||
91d6fa6a | 6719 | va_start (args, hist); |
71400594 | 6720 | cursor = buffer + num_insns; |
91d6fa6a | 6721 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
71400594 RS |
6722 | while (cursor > buffer) |
6723 | *--cursor = *va_arg (args, const struct mips_cl_insn *); | |
6724 | ||
932d1a1b | 6725 | nops = nops_for_insn (ignore, buffer, NULL); |
71400594 RS |
6726 | va_end (args); |
6727 | return nops; | |
6728 | } | |
252b5132 | 6729 | |
71400594 RS |
6730 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
6731 | worst-case delay for the branch target. */ | |
252b5132 | 6732 | |
71400594 | 6733 | static int |
932d1a1b | 6734 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
71400594 RS |
6735 | const struct mips_cl_insn *insn) |
6736 | { | |
6737 | int nops, tmp_nops; | |
60b63b72 | 6738 | |
932d1a1b | 6739 | nops = nops_for_insn (ignore, hist, insn); |
11625dd8 | 6740 | if (delayed_branch_p (insn)) |
71400594 | 6741 | { |
932d1a1b | 6742 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
14fe068b | 6743 | hist, insn, get_delay_slot_nop (insn)); |
71400594 RS |
6744 | if (tmp_nops > nops) |
6745 | nops = tmp_nops; | |
6746 | } | |
11625dd8 | 6747 | else if (compact_branch_p (insn)) |
71400594 | 6748 | { |
932d1a1b | 6749 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
71400594 RS |
6750 | if (tmp_nops > nops) |
6751 | nops = tmp_nops; | |
6752 | } | |
6753 | return nops; | |
6754 | } | |
6755 | ||
c67a084a NC |
6756 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
6757 | ||
6758 | static void | |
6759 | fix_loongson2f_nop (struct mips_cl_insn * ip) | |
6760 | { | |
df58fc94 | 6761 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6762 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
6763 | ip->insn_opcode = LOONGSON2F_NOP_INSN; | |
6764 | } | |
6765 | ||
6766 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region | |
6767 | jr target pc &= 'hffff_ffff_cfff_ffff. */ | |
6768 | ||
6769 | static void | |
6770 | fix_loongson2f_jump (struct mips_cl_insn * ip) | |
6771 | { | |
df58fc94 | 6772 | gas_assert (!HAVE_CODE_COMPRESSION); |
c67a084a NC |
6773 | if (strcmp (ip->insn_mo->name, "j") == 0 |
6774 | || strcmp (ip->insn_mo->name, "jr") == 0 | |
6775 | || strcmp (ip->insn_mo->name, "jalr") == 0) | |
6776 | { | |
6777 | int sreg; | |
6778 | expressionS ep; | |
6779 | ||
6780 | if (! mips_opts.at) | |
6781 | return; | |
6782 | ||
df58fc94 | 6783 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
c67a084a NC |
6784 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
6785 | return; | |
6786 | ||
6787 | ep.X_op = O_constant; | |
6788 | ep.X_add_number = 0xcfff0000; | |
6789 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); | |
6790 | ep.X_add_number = 0xffff; | |
6791 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); | |
6792 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); | |
6793 | } | |
6794 | } | |
6795 | ||
6796 | static void | |
6797 | fix_loongson2f (struct mips_cl_insn * ip) | |
6798 | { | |
6799 | if (mips_fix_loongson2f_nop) | |
6800 | fix_loongson2f_nop (ip); | |
6801 | ||
6802 | if (mips_fix_loongson2f_jump) | |
6803 | fix_loongson2f_jump (ip); | |
6804 | } | |
6805 | ||
a4e06468 RS |
6806 | /* IP is a branch that has a delay slot, and we need to fill it |
6807 | automatically. Return true if we can do that by swapping IP | |
e407c74b NC |
6808 | with the previous instruction. |
6809 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6810 | RELOC_TYPE. */ | |
a4e06468 RS |
6811 | |
6812 | static bfd_boolean | |
e407c74b | 6813 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6814 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6815 | { |
2b0c8b40 | 6816 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
a4e06468 | 6817 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
9d5de888 | 6818 | unsigned int fpr_read, prev_fpr_write; |
a4e06468 RS |
6819 | |
6820 | /* -O2 and above is required for this optimization. */ | |
6821 | if (mips_optimize < 2) | |
6822 | return FALSE; | |
6823 | ||
6824 | /* If we have seen .set volatile or .set nomove, don't optimize. */ | |
6825 | if (mips_opts.nomove) | |
6826 | return FALSE; | |
6827 | ||
6828 | /* We can't swap if the previous instruction's position is fixed. */ | |
6829 | if (history[0].fixed_p) | |
6830 | return FALSE; | |
6831 | ||
6832 | /* If the previous previous insn was in a .set noreorder, we can't | |
6833 | swap. Actually, the MIPS assembler will swap in this situation. | |
6834 | However, gcc configured -with-gnu-as will generate code like | |
6835 | ||
6836 | .set noreorder | |
6837 | lw $4,XXX | |
6838 | .set reorder | |
6839 | INSN | |
6840 | bne $4,$0,foo | |
6841 | ||
6842 | in which we can not swap the bne and INSN. If gcc is not configured | |
6843 | -with-gnu-as, it does not output the .set pseudo-ops. */ | |
6844 | if (history[1].noreorder_p) | |
6845 | return FALSE; | |
6846 | ||
87333bb7 MR |
6847 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
6848 | This means that the previous instruction was a 4-byte one anyhow. */ | |
a4e06468 RS |
6849 | if (mips_opts.mips16 && history[0].fixp[0]) |
6850 | return FALSE; | |
6851 | ||
6852 | /* If the branch is itself the target of a branch, we can not swap. | |
6853 | We cheat on this; all we check for is whether there is a label on | |
6854 | this instruction. If there are any branches to anything other than | |
6855 | a label, users must use .set noreorder. */ | |
6856 | if (seg_info (now_seg)->label_list) | |
6857 | return FALSE; | |
6858 | ||
6859 | /* If the previous instruction is in a variant frag other than this | |
2309ddf2 | 6860 | branch's one, we cannot do the swap. This does not apply to |
9301f9c3 MR |
6861 | MIPS16 code, which uses variant frags for different purposes. */ |
6862 | if (!mips_opts.mips16 | |
a4e06468 RS |
6863 | && history[0].frag |
6864 | && history[0].frag->fr_type == rs_machine_dependent) | |
6865 | return FALSE; | |
6866 | ||
bcd530a7 RS |
6867 | /* We do not swap with instructions that cannot architecturally |
6868 | be placed in a branch delay slot, such as SYNC or ERET. We | |
6869 | also refrain from swapping with a trap instruction, since it | |
6870 | complicates trap handlers to have the trap instruction be in | |
6871 | a delay slot. */ | |
a4e06468 | 6872 | prev_pinfo = history[0].insn_mo->pinfo; |
bcd530a7 | 6873 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
a4e06468 RS |
6874 | return FALSE; |
6875 | ||
6876 | /* Check for conflicts between the branch and the instructions | |
6877 | before the candidate delay slot. */ | |
6878 | if (nops_for_insn (0, history + 1, ip) > 0) | |
6879 | return FALSE; | |
6880 | ||
6881 | /* Check for conflicts between the swapped sequence and the | |
6882 | target of the branch. */ | |
6883 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) | |
6884 | return FALSE; | |
6885 | ||
6886 | /* If the branch reads a register that the previous | |
6887 | instruction sets, we can not swap. */ | |
6888 | gpr_read = gpr_read_mask (ip); | |
6889 | prev_gpr_write = gpr_write_mask (&history[0]); | |
6890 | if (gpr_read & prev_gpr_write) | |
6891 | return FALSE; | |
6892 | ||
9d5de888 CF |
6893 | fpr_read = fpr_read_mask (ip); |
6894 | prev_fpr_write = fpr_write_mask (&history[0]); | |
6895 | if (fpr_read & prev_fpr_write) | |
6896 | return FALSE; | |
6897 | ||
a4e06468 RS |
6898 | /* If the branch writes a register that the previous |
6899 | instruction sets, we can not swap. */ | |
6900 | gpr_write = gpr_write_mask (ip); | |
6901 | if (gpr_write & prev_gpr_write) | |
6902 | return FALSE; | |
6903 | ||
6904 | /* If the branch writes a register that the previous | |
6905 | instruction reads, we can not swap. */ | |
6906 | prev_gpr_read = gpr_read_mask (&history[0]); | |
6907 | if (gpr_write & prev_gpr_read) | |
6908 | return FALSE; | |
6909 | ||
6910 | /* If one instruction sets a condition code and the | |
6911 | other one uses a condition code, we can not swap. */ | |
6912 | pinfo = ip->insn_mo->pinfo; | |
6913 | if ((pinfo & INSN_READ_COND_CODE) | |
6914 | && (prev_pinfo & INSN_WRITE_COND_CODE)) | |
6915 | return FALSE; | |
6916 | if ((pinfo & INSN_WRITE_COND_CODE) | |
6917 | && (prev_pinfo & INSN_READ_COND_CODE)) | |
6918 | return FALSE; | |
6919 | ||
6920 | /* If the previous instruction uses the PC, we can not swap. */ | |
2b0c8b40 | 6921 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
26545944 | 6922 | if (prev_pinfo2 & INSN2_READ_PC) |
2b0c8b40 | 6923 | return FALSE; |
a4e06468 | 6924 | |
df58fc94 RS |
6925 | /* If the previous instruction has an incorrect size for a fixed |
6926 | branch delay slot in microMIPS mode, we cannot swap. */ | |
2309ddf2 MR |
6927 | pinfo2 = ip->insn_mo->pinfo2; |
6928 | if (mips_opts.micromips | |
6929 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) | |
6930 | && insn_length (history) != 2) | |
6931 | return FALSE; | |
6932 | if (mips_opts.micromips | |
6933 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) | |
6934 | && insn_length (history) != 4) | |
6935 | return FALSE; | |
6936 | ||
e407c74b NC |
6937 | /* On R5900 short loops need to be fixed by inserting a nop in |
6938 | the branch delay slots. | |
6939 | A short loop can be terminated too early. */ | |
6940 | if (mips_opts.arch == CPU_R5900 | |
6941 | /* Check if instruction has a parameter, ignore "j $31". */ | |
6942 | && (address_expr != NULL) | |
6943 | /* Parameter must be 16 bit. */ | |
6944 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) | |
6945 | /* Branch to same segment. */ | |
41065f5e | 6946 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
e407c74b | 6947 | /* Branch to same code fragment. */ |
41065f5e | 6948 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
e407c74b | 6949 | /* Can only calculate branch offset if value is known. */ |
41065f5e | 6950 | && symbol_constant_p (address_expr->X_add_symbol) |
e407c74b NC |
6951 | /* Check if branch is really conditional. */ |
6952 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ | |
6953 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
6954 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
6955 | { | |
6956 | int distance; | |
6957 | /* Check if loop is shorter than 6 instructions including | |
6958 | branch and delay slot. */ | |
41065f5e | 6959 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
e407c74b NC |
6960 | if (distance <= 20) |
6961 | { | |
6962 | int i; | |
6963 | int rv; | |
6964 | ||
6965 | rv = FALSE; | |
6966 | /* When the loop includes branches or jumps, | |
6967 | it is not a short loop. */ | |
6968 | for (i = 0; i < (distance / 4); i++) | |
6969 | { | |
6970 | if ((history[i].cleared_p) | |
41065f5e | 6971 | || delayed_branch_p (&history[i])) |
e407c74b NC |
6972 | { |
6973 | rv = TRUE; | |
6974 | break; | |
6975 | } | |
6976 | } | |
535b785f | 6977 | if (!rv) |
e407c74b NC |
6978 | { |
6979 | /* Insert nop after branch to fix short loop. */ | |
6980 | return FALSE; | |
6981 | } | |
6982 | } | |
6983 | } | |
6984 | ||
a4e06468 RS |
6985 | return TRUE; |
6986 | } | |
6987 | ||
e407c74b NC |
6988 | /* Decide how we should add IP to the instruction stream. |
6989 | ADDRESS_EXPR is an operand of the instruction to be used with | |
6990 | RELOC_TYPE. */ | |
a4e06468 RS |
6991 | |
6992 | static enum append_method | |
e407c74b | 6993 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
26545944 | 6994 | bfd_reloc_code_real_type *reloc_type) |
a4e06468 | 6995 | { |
a4e06468 RS |
6996 | /* The relaxed version of a macro sequence must be inherently |
6997 | hazard-free. */ | |
6998 | if (mips_relax.sequence == 2) | |
6999 | return APPEND_ADD; | |
7000 | ||
3b821a28 | 7001 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
a4e06468 RS |
7002 | if (mips_opts.noreorder) |
7003 | return APPEND_ADD; | |
7004 | ||
7005 | /* Otherwise, it's our responsibility to fill branch delay slots. */ | |
11625dd8 | 7006 | if (delayed_branch_p (ip)) |
a4e06468 | 7007 | { |
e407c74b NC |
7008 | if (!branch_likely_p (ip) |
7009 | && can_swap_branch_p (ip, address_expr, reloc_type)) | |
a4e06468 RS |
7010 | return APPEND_SWAP; |
7011 | ||
7012 | if (mips_opts.mips16 | |
7013 | && ISA_SUPPORTS_MIPS16E | |
fc76e730 | 7014 | && gpr_read_mask (ip) != 0) |
a4e06468 RS |
7015 | return APPEND_ADD_COMPACT; |
7016 | ||
7bd374a4 MR |
7017 | if (mips_opts.micromips |
7018 | && ((ip->insn_opcode & 0xffe0) == 0x4580 | |
7019 | || (!forced_insn_length | |
7020 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 | |
7021 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) | |
7022 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 | |
7023 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) | |
7024 | return APPEND_ADD_COMPACT; | |
7025 | ||
a4e06468 RS |
7026 | return APPEND_ADD_WITH_NOP; |
7027 | } | |
7028 | ||
a4e06468 RS |
7029 | return APPEND_ADD; |
7030 | } | |
7031 | ||
7bd374a4 MR |
7032 | /* IP is an instruction whose opcode we have just changed, END points |
7033 | to the end of the opcode table processed. Point IP->insn_mo to the | |
7034 | new opcode's definition. */ | |
ceb94aa5 RS |
7035 | |
7036 | static void | |
7bd374a4 | 7037 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
ceb94aa5 | 7038 | { |
7bd374a4 | 7039 | const struct mips_opcode *mo; |
ceb94aa5 | 7040 | |
ceb94aa5 | 7041 | for (mo = ip->insn_mo; mo < end; mo++) |
7bd374a4 MR |
7042 | if (mo->pinfo != INSN_MACRO |
7043 | && (ip->insn_opcode & mo->mask) == mo->match) | |
ceb94aa5 RS |
7044 | { |
7045 | ip->insn_mo = mo; | |
7046 | return; | |
7047 | } | |
7048 | abort (); | |
7049 | } | |
7050 | ||
7bd374a4 MR |
7051 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
7052 | Point IP->insn_mo to the new opcode's definition. */ | |
7053 | ||
7054 | static void | |
7055 | find_altered_mips16_opcode (struct mips_cl_insn *ip) | |
7056 | { | |
7057 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); | |
7058 | } | |
7059 | ||
7060 | /* IP is a microMIPS instruction whose opcode we have just changed. | |
7061 | Point IP->insn_mo to the new opcode's definition. */ | |
7062 | ||
7063 | static void | |
7064 | find_altered_micromips_opcode (struct mips_cl_insn *ip) | |
7065 | { | |
7066 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); | |
7067 | } | |
7068 | ||
df58fc94 RS |
7069 | /* For microMIPS macros, we need to generate a local number label |
7070 | as the target of branches. */ | |
7071 | #define MICROMIPS_LABEL_CHAR '\037' | |
7072 | static unsigned long micromips_target_label; | |
7073 | static char micromips_target_name[32]; | |
7074 | ||
7075 | static char * | |
7076 | micromips_label_name (void) | |
7077 | { | |
7078 | char *p = micromips_target_name; | |
7079 | char symbol_name_temporary[24]; | |
7080 | unsigned long l; | |
7081 | int i; | |
7082 | ||
7083 | if (*p) | |
7084 | return p; | |
7085 | ||
7086 | i = 0; | |
7087 | l = micromips_target_label; | |
7088 | #ifdef LOCAL_LABEL_PREFIX | |
7089 | *p++ = LOCAL_LABEL_PREFIX; | |
7090 | #endif | |
7091 | *p++ = 'L'; | |
7092 | *p++ = MICROMIPS_LABEL_CHAR; | |
7093 | do | |
7094 | { | |
7095 | symbol_name_temporary[i++] = l % 10 + '0'; | |
7096 | l /= 10; | |
7097 | } | |
7098 | while (l != 0); | |
7099 | while (i > 0) | |
7100 | *p++ = symbol_name_temporary[--i]; | |
7101 | *p = '\0'; | |
7102 | ||
7103 | return micromips_target_name; | |
7104 | } | |
7105 | ||
7106 | static void | |
7107 | micromips_label_expr (expressionS *label_expr) | |
7108 | { | |
7109 | label_expr->X_op = O_symbol; | |
7110 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); | |
7111 | label_expr->X_add_number = 0; | |
7112 | } | |
7113 | ||
7114 | static void | |
7115 | micromips_label_inc (void) | |
7116 | { | |
7117 | micromips_target_label++; | |
7118 | *micromips_target_name = '\0'; | |
7119 | } | |
7120 | ||
7121 | static void | |
7122 | micromips_add_label (void) | |
7123 | { | |
7124 | symbolS *s; | |
7125 | ||
7126 | s = colon (micromips_label_name ()); | |
7127 | micromips_label_inc (); | |
f3ded42a | 7128 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
df58fc94 RS |
7129 | } |
7130 | ||
7131 | /* If assembling microMIPS code, then return the microMIPS reloc | |
7132 | corresponding to the requested one if any. Otherwise return | |
7133 | the reloc unchanged. */ | |
7134 | ||
7135 | static bfd_reloc_code_real_type | |
7136 | micromips_map_reloc (bfd_reloc_code_real_type reloc) | |
7137 | { | |
7138 | static const bfd_reloc_code_real_type relocs[][2] = | |
7139 | { | |
7140 | /* Keep sorted incrementally by the left-hand key. */ | |
7141 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, | |
7142 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, | |
7143 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, | |
7144 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, | |
7145 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, | |
7146 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, | |
7147 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, | |
7148 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, | |
7149 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, | |
7150 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, | |
7151 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, | |
7152 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, | |
7153 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, | |
7154 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, | |
7155 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, | |
7156 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, | |
7157 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, | |
7158 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, | |
7159 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, | |
7160 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, | |
7161 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, | |
7162 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, | |
7163 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, | |
7164 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, | |
7165 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, | |
7166 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, | |
7167 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } | |
7168 | }; | |
7169 | bfd_reloc_code_real_type r; | |
7170 | size_t i; | |
7171 | ||
7172 | if (!mips_opts.micromips) | |
7173 | return reloc; | |
7174 | for (i = 0; i < ARRAY_SIZE (relocs); i++) | |
7175 | { | |
7176 | r = relocs[i][0]; | |
7177 | if (r > reloc) | |
7178 | return reloc; | |
7179 | if (r == reloc) | |
7180 | return relocs[i][1]; | |
7181 | } | |
7182 | return reloc; | |
7183 | } | |
7184 | ||
b886a2ab RS |
7185 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
7186 | Return true on success, storing the resolved value in RESULT. */ | |
7187 | ||
7188 | static bfd_boolean | |
7189 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, | |
7190 | offsetT *result) | |
7191 | { | |
7192 | switch (reloc) | |
7193 | { | |
7194 | case BFD_RELOC_MIPS_HIGHEST: | |
7195 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
7196 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; | |
7197 | return TRUE; | |
7198 | ||
7199 | case BFD_RELOC_MIPS_HIGHER: | |
7200 | case BFD_RELOC_MICROMIPS_HIGHER: | |
7201 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; | |
7202 | return TRUE; | |
7203 | ||
7204 | case BFD_RELOC_HI16_S: | |
41947d9e | 7205 | case BFD_RELOC_HI16_S_PCREL: |
b886a2ab RS |
7206 | case BFD_RELOC_MICROMIPS_HI16_S: |
7207 | case BFD_RELOC_MIPS16_HI16_S: | |
7208 | *result = ((operand + 0x8000) >> 16) & 0xffff; | |
7209 | return TRUE; | |
7210 | ||
7211 | case BFD_RELOC_HI16: | |
7212 | case BFD_RELOC_MICROMIPS_HI16: | |
7213 | case BFD_RELOC_MIPS16_HI16: | |
7214 | *result = (operand >> 16) & 0xffff; | |
7215 | return TRUE; | |
7216 | ||
7217 | case BFD_RELOC_LO16: | |
41947d9e | 7218 | case BFD_RELOC_LO16_PCREL: |
b886a2ab RS |
7219 | case BFD_RELOC_MICROMIPS_LO16: |
7220 | case BFD_RELOC_MIPS16_LO16: | |
7221 | *result = operand & 0xffff; | |
7222 | return TRUE; | |
7223 | ||
7224 | case BFD_RELOC_UNUSED: | |
7225 | *result = operand; | |
7226 | return TRUE; | |
7227 | ||
7228 | default: | |
7229 | return FALSE; | |
7230 | } | |
7231 | } | |
7232 | ||
71400594 RS |
7233 | /* Output an instruction. IP is the instruction information. |
7234 | ADDRESS_EXPR is an operand of the instruction to be used with | |
df58fc94 RS |
7235 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
7236 | a macro expansion. */ | |
71400594 RS |
7237 | |
7238 | static void | |
7239 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, | |
df58fc94 | 7240 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
71400594 | 7241 | { |
14fe068b | 7242 | unsigned long prev_pinfo2, pinfo; |
71400594 | 7243 | bfd_boolean relaxed_branch = FALSE; |
a4e06468 | 7244 | enum append_method method; |
2309ddf2 | 7245 | bfd_boolean relax32; |
2b0c8b40 | 7246 | int branch_disp; |
71400594 | 7247 | |
2309ddf2 | 7248 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
c67a084a NC |
7249 | fix_loongson2f (ip); |
7250 | ||
738f4d98 | 7251 | file_ase_mips16 |= mips_opts.mips16; |
df58fc94 | 7252 | file_ase_micromips |= mips_opts.micromips; |
738f4d98 | 7253 | |
df58fc94 | 7254 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
71400594 | 7255 | pinfo = ip->insn_mo->pinfo; |
df58fc94 | 7256 | |
7bd374a4 MR |
7257 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
7258 | kind of nop in relaxation if required. */ | |
df58fc94 RS |
7259 | if (mips_opts.micromips |
7260 | && !expansionp | |
7bd374a4 MR |
7261 | && !(history[0].frag |
7262 | && history[0].frag->fr_type == rs_machine_dependent | |
7263 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
7264 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
df58fc94 RS |
7265 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
7266 | && micromips_insn_length (ip->insn_mo) != 2) | |
7267 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 | |
7268 | && micromips_insn_length (ip->insn_mo) != 4))) | |
1661c76c | 7269 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
df58fc94 | 7270 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
71400594 | 7271 | |
15be625d CM |
7272 | if (address_expr == NULL) |
7273 | ip->complete_p = 1; | |
b886a2ab RS |
7274 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
7275 | && reloc_type[1] == BFD_RELOC_UNUSED | |
7276 | && reloc_type[2] == BFD_RELOC_UNUSED | |
15be625d CM |
7277 | && address_expr->X_op == O_constant) |
7278 | { | |
15be625d CM |
7279 | switch (*reloc_type) |
7280 | { | |
15be625d | 7281 | case BFD_RELOC_MIPS_JMP: |
df58fc94 RS |
7282 | { |
7283 | int shift; | |
7284 | ||
17c6c9d9 MR |
7285 | /* Shift is 2, unusually, for microMIPS JALX. */ |
7286 | shift = (mips_opts.micromips | |
7287 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; | |
df58fc94 RS |
7288 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
7289 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7290 | (unsigned long) address_expr->X_add_number); | |
7291 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7292 | & 0x3ffffff); | |
335574df | 7293 | ip->complete_p = 1; |
df58fc94 | 7294 | } |
15be625d CM |
7295 | break; |
7296 | ||
7297 | case BFD_RELOC_MIPS16_JMP: | |
7298 | if ((address_expr->X_add_number & 3) != 0) | |
7299 | as_bad (_("jump to misaligned address (0x%lx)"), | |
7300 | (unsigned long) address_expr->X_add_number); | |
7301 | ip->insn_opcode |= | |
7302 | (((address_expr->X_add_number & 0x7c0000) << 3) | |
7303 | | ((address_expr->X_add_number & 0xf800000) >> 7) | |
7304 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); | |
335574df | 7305 | ip->complete_p = 1; |
15be625d CM |
7306 | break; |
7307 | ||
7308 | case BFD_RELOC_16_PCREL_S2: | |
df58fc94 RS |
7309 | { |
7310 | int shift; | |
7311 | ||
7312 | shift = mips_opts.micromips ? 1 : 2; | |
7313 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7314 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7315 | (unsigned long) address_expr->X_add_number); | |
7316 | if (!mips_relax_branch) | |
7317 | { | |
7318 | if ((address_expr->X_add_number + (1 << (shift + 15))) | |
7319 | & ~((1 << (shift + 16)) - 1)) | |
7320 | as_bad (_("branch address range overflow (0x%lx)"), | |
7321 | (unsigned long) address_expr->X_add_number); | |
7322 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7323 | & 0xffff); | |
7324 | } | |
df58fc94 | 7325 | } |
15be625d CM |
7326 | break; |
7327 | ||
7361da2c AB |
7328 | case BFD_RELOC_MIPS_21_PCREL_S2: |
7329 | { | |
7330 | int shift; | |
7331 | ||
7332 | shift = 2; | |
7333 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7334 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7335 | (unsigned long) address_expr->X_add_number); | |
7336 | if ((address_expr->X_add_number + (1 << (shift + 20))) | |
7337 | & ~((1 << (shift + 21)) - 1)) | |
7338 | as_bad (_("branch address range overflow (0x%lx)"), | |
7339 | (unsigned long) address_expr->X_add_number); | |
7340 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7341 | & 0x1fffff); | |
7342 | } | |
7343 | break; | |
7344 | ||
7345 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
7346 | { | |
7347 | int shift; | |
7348 | ||
7349 | shift = 2; | |
7350 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) | |
7351 | as_bad (_("branch to misaligned address (0x%lx)"), | |
7352 | (unsigned long) address_expr->X_add_number); | |
7353 | if ((address_expr->X_add_number + (1 << (shift + 25))) | |
7354 | & ~((1 << (shift + 26)) - 1)) | |
7355 | as_bad (_("branch address range overflow (0x%lx)"), | |
7356 | (unsigned long) address_expr->X_add_number); | |
7357 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) | |
7358 | & 0x3ffffff); | |
7359 | } | |
7360 | break; | |
7361 | ||
15be625d | 7362 | default: |
b886a2ab RS |
7363 | { |
7364 | offsetT value; | |
7365 | ||
7366 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, | |
7367 | &value)) | |
7368 | { | |
7369 | ip->insn_opcode |= value & 0xffff; | |
7370 | ip->complete_p = 1; | |
7371 | } | |
7372 | } | |
7373 | break; | |
7374 | } | |
15be625d CM |
7375 | } |
7376 | ||
71400594 RS |
7377 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
7378 | { | |
7379 | /* There are a lot of optimizations we could do that we don't. | |
7380 | In particular, we do not, in general, reorder instructions. | |
7381 | If you use gcc with optimization, it will reorder | |
7382 | instructions and generally do much more optimization then we | |
7383 | do here; repeating all that work in the assembler would only | |
7384 | benefit hand written assembly code, and does not seem worth | |
7385 | it. */ | |
7386 | int nops = (mips_optimize == 0 | |
932d1a1b RS |
7387 | ? nops_for_insn (0, history, NULL) |
7388 | : nops_for_insn_or_target (0, history, ip)); | |
71400594 | 7389 | if (nops > 0) |
252b5132 RH |
7390 | { |
7391 | fragS *old_frag; | |
7392 | unsigned long old_frag_offset; | |
7393 | int i; | |
252b5132 RH |
7394 | |
7395 | old_frag = frag_now; | |
7396 | old_frag_offset = frag_now_fix (); | |
7397 | ||
7398 | for (i = 0; i < nops; i++) | |
14fe068b RS |
7399 | add_fixed_insn (NOP_INSN); |
7400 | insert_into_history (0, nops, NOP_INSN); | |
252b5132 RH |
7401 | |
7402 | if (listing) | |
7403 | { | |
7404 | listing_prev_line (); | |
7405 | /* We may be at the start of a variant frag. In case we | |
7406 | are, make sure there is enough space for the frag | |
7407 | after the frags created by listing_prev_line. The | |
7408 | argument to frag_grow here must be at least as large | |
7409 | as the argument to all other calls to frag_grow in | |
7410 | this file. We don't have to worry about being in the | |
7411 | middle of a variant frag, because the variants insert | |
7412 | all needed nop instructions themselves. */ | |
7413 | frag_grow (40); | |
7414 | } | |
7415 | ||
462427c4 | 7416 | mips_move_text_labels (); |
252b5132 RH |
7417 | |
7418 | #ifndef NO_ECOFF_DEBUGGING | |
7419 | if (ECOFF_DEBUGGING) | |
7420 | ecoff_fix_loc (old_frag, old_frag_offset); | |
7421 | #endif | |
7422 | } | |
71400594 RS |
7423 | } |
7424 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) | |
7425 | { | |
932d1a1b RS |
7426 | int nops; |
7427 | ||
7428 | /* Work out how many nops in prev_nop_frag are needed by IP, | |
7429 | ignoring hazards generated by the first prev_nop_frag_since | |
7430 | instructions. */ | |
7431 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); | |
9c2799c2 | 7432 | gas_assert (nops <= prev_nop_frag_holds); |
252b5132 | 7433 | |
71400594 RS |
7434 | /* Enforce NOPS as a minimum. */ |
7435 | if (nops > prev_nop_frag_required) | |
7436 | prev_nop_frag_required = nops; | |
252b5132 | 7437 | |
71400594 RS |
7438 | if (prev_nop_frag_holds == prev_nop_frag_required) |
7439 | { | |
7440 | /* Settle for the current number of nops. Update the history | |
7441 | accordingly (for the benefit of any future .set reorder code). */ | |
7442 | prev_nop_frag = NULL; | |
7443 | insert_into_history (prev_nop_frag_since, | |
7444 | prev_nop_frag_holds, NOP_INSN); | |
7445 | } | |
7446 | else | |
7447 | { | |
7448 | /* Allow this instruction to replace one of the nops that was | |
7449 | tentatively added to prev_nop_frag. */ | |
df58fc94 | 7450 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
71400594 RS |
7451 | prev_nop_frag_holds--; |
7452 | prev_nop_frag_since++; | |
252b5132 RH |
7453 | } |
7454 | } | |
7455 | ||
e407c74b | 7456 | method = get_append_method (ip, address_expr, reloc_type); |
2b0c8b40 | 7457 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
a4e06468 | 7458 | |
e410add4 RS |
7459 | dwarf2_emit_insn (0); |
7460 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, | |
7461 | so "move" the instruction address accordingly. | |
7462 | ||
7463 | Also, it doesn't seem appropriate for the assembler to reorder .loc | |
7464 | entries. If this instruction is a branch that we are going to swap | |
7465 | with the previous instruction, the two instructions should be | |
7466 | treated as a unit, and the debug information for both instructions | |
7467 | should refer to the start of the branch sequence. Using the | |
7468 | current position is certainly wrong when swapping a 32-bit branch | |
7469 | and a 16-bit delay slot, since the current position would then be | |
7470 | in the middle of a branch. */ | |
7471 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); | |
58e2ea4d | 7472 | |
df58fc94 RS |
7473 | relax32 = (mips_relax_branch |
7474 | /* Don't try branch relaxation within .set nomacro, or within | |
7475 | .set noat if we use $at for PIC computations. If it turns | |
7476 | out that the branch was out-of-range, we'll get an error. */ | |
7477 | && !mips_opts.warn_about_macros | |
7478 | && (mips_opts.at || mips_pic == NO_PIC) | |
3bf0dbfb MR |
7479 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
7480 | as they have no complementing branches. */ | |
7481 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); | |
df58fc94 RS |
7482 | |
7483 | if (!HAVE_CODE_COMPRESSION | |
7484 | && address_expr | |
7485 | && relax32 | |
0b25d3e6 | 7486 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
11625dd8 | 7487 | && delayed_branch_p (ip)) |
4a6a3df4 | 7488 | { |
895921c9 | 7489 | relaxed_branch = TRUE; |
1e915849 RS |
7490 | add_relaxed_insn (ip, (relaxed_branch_length |
7491 | (NULL, NULL, | |
11625dd8 RS |
7492 | uncond_branch_p (ip) ? -1 |
7493 | : branch_likely_p (ip) ? 1 | |
1e915849 RS |
7494 | : 0)), 4, |
7495 | RELAX_BRANCH_ENCODE | |
ce8ad872 | 7496 | (AT, mips_pic != NO_PIC, |
11625dd8 RS |
7497 | uncond_branch_p (ip), |
7498 | branch_likely_p (ip), | |
1e915849 RS |
7499 | pinfo & INSN_WRITE_GPR_31, |
7500 | 0), | |
7501 | address_expr->X_add_symbol, | |
7502 | address_expr->X_add_number); | |
4a6a3df4 AO |
7503 | *reloc_type = BFD_RELOC_UNUSED; |
7504 | } | |
df58fc94 RS |
7505 | else if (mips_opts.micromips |
7506 | && address_expr | |
7507 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) | |
7508 | || *reloc_type > BFD_RELOC_UNUSED) | |
40209cad MR |
7509 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
7510 | /* Don't try branch relaxation when users specify | |
7511 | 16-bit/32-bit instructions. */ | |
7512 | && !forced_insn_length) | |
df58fc94 | 7513 | { |
7bd374a4 MR |
7514 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
7515 | && *reloc_type > BFD_RELOC_UNUSED); | |
df58fc94 | 7516 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
11625dd8 | 7517 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
7bd374a4 MR |
7518 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
7519 | int nods = method == APPEND_ADD_WITH_NOP; | |
df58fc94 | 7520 | int al = pinfo & INSN_WRITE_GPR_31; |
7bd374a4 | 7521 | int length32 = nods ? 8 : 4; |
df58fc94 RS |
7522 | |
7523 | gas_assert (address_expr != NULL); | |
7524 | gas_assert (!mips_relax.sequence); | |
7525 | ||
2b0c8b40 | 7526 | relaxed_branch = TRUE; |
7bd374a4 MR |
7527 | if (nods) |
7528 | method = APPEND_ADD; | |
7529 | if (relax32) | |
7530 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); | |
7531 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, | |
8484fb75 | 7532 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
ce8ad872 | 7533 | mips_pic != NO_PIC, |
7bd374a4 | 7534 | uncond, compact, al, nods, |
40209cad | 7535 | relax32, 0, 0), |
df58fc94 RS |
7536 | address_expr->X_add_symbol, |
7537 | address_expr->X_add_number); | |
7538 | *reloc_type = BFD_RELOC_UNUSED; | |
7539 | } | |
7540 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) | |
252b5132 | 7541 | { |
7fd53920 MR |
7542 | bfd_boolean require_unextended; |
7543 | bfd_boolean require_extended; | |
88a7ef16 MR |
7544 | symbolS *symbol; |
7545 | offsetT offset; | |
7546 | ||
7fd53920 MR |
7547 | if (forced_insn_length != 0) |
7548 | { | |
7549 | require_unextended = forced_insn_length == 2; | |
7550 | require_extended = forced_insn_length == 4; | |
7551 | } | |
7552 | else | |
7553 | { | |
7554 | require_unextended = (mips_opts.noautoextend | |
7555 | && !mips_opcode_32bit_p (ip->insn_mo)); | |
7556 | require_extended = 0; | |
7557 | } | |
7558 | ||
252b5132 | 7559 | /* We need to set up a variant frag. */ |
df58fc94 | 7560 | gas_assert (address_expr != NULL); |
88a7ef16 MR |
7561 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
7562 | symbol created by `make_expr_symbol' may not get a necessary | |
7563 | external relocation produced. */ | |
7564 | if (address_expr->X_op == O_symbol) | |
7565 | { | |
7566 | symbol = address_expr->X_add_symbol; | |
7567 | offset = address_expr->X_add_number; | |
7568 | } | |
7569 | else | |
7570 | { | |
7571 | symbol = make_expr_symbol (address_expr); | |
82d808ed | 7572 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
88a7ef16 MR |
7573 | offset = 0; |
7574 | } | |
8507b6e7 | 7575 | add_relaxed_insn (ip, 12, 0, |
1e915849 RS |
7576 | RELAX_MIPS16_ENCODE |
7577 | (*reloc_type - BFD_RELOC_UNUSED, | |
25499ac7 | 7578 | mips_opts.ase & ASE_MIPS16E2, |
8507b6e7 MR |
7579 | mips_pic != NO_PIC, |
7580 | HAVE_32BIT_SYMBOLS, | |
7581 | mips_opts.warn_about_macros, | |
7fd53920 | 7582 | require_unextended, require_extended, |
11625dd8 | 7583 | delayed_branch_p (&history[0]), |
1e915849 | 7584 | history[0].mips16_absolute_jump_p), |
88a7ef16 | 7585 | symbol, offset); |
252b5132 | 7586 | } |
5c04167a | 7587 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
9497f5ac | 7588 | { |
11625dd8 | 7589 | if (!delayed_branch_p (ip)) |
b8ee1a6e DU |
7590 | /* Make sure there is enough room to swap this instruction with |
7591 | a following jump instruction. */ | |
7592 | frag_grow (6); | |
1e915849 | 7593 | add_fixed_insn (ip); |
252b5132 RH |
7594 | } |
7595 | else | |
7596 | { | |
7597 | if (mips_opts.mips16 | |
7598 | && mips_opts.noreorder | |
11625dd8 | 7599 | && delayed_branch_p (&history[0])) |
252b5132 RH |
7600 | as_warn (_("extended instruction in delay slot")); |
7601 | ||
4d7206a2 RS |
7602 | if (mips_relax.sequence) |
7603 | { | |
7604 | /* If we've reached the end of this frag, turn it into a variant | |
7605 | frag and record the information for the instructions we've | |
7606 | written so far. */ | |
7607 | if (frag_room () < 4) | |
7608 | relax_close_frag (); | |
df58fc94 | 7609 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
4d7206a2 RS |
7610 | } |
7611 | ||
584892a6 | 7612 | if (mips_relax.sequence != 2) |
df58fc94 RS |
7613 | { |
7614 | if (mips_macro_warning.first_insn_sizes[0] == 0) | |
7615 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); | |
7616 | mips_macro_warning.sizes[0] += insn_length (ip); | |
7617 | mips_macro_warning.insns[0]++; | |
7618 | } | |
584892a6 | 7619 | if (mips_relax.sequence != 1) |
df58fc94 RS |
7620 | { |
7621 | if (mips_macro_warning.first_insn_sizes[1] == 0) | |
7622 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); | |
7623 | mips_macro_warning.sizes[1] += insn_length (ip); | |
7624 | mips_macro_warning.insns[1]++; | |
7625 | } | |
584892a6 | 7626 | |
1e915849 RS |
7627 | if (mips_opts.mips16) |
7628 | { | |
7629 | ip->fixed_p = 1; | |
7630 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); | |
7631 | } | |
7632 | add_fixed_insn (ip); | |
252b5132 RH |
7633 | } |
7634 | ||
9fe77896 | 7635 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
252b5132 | 7636 | { |
df58fc94 | 7637 | bfd_reloc_code_real_type final_type[3]; |
2309ddf2 | 7638 | reloc_howto_type *howto0; |
9fe77896 RS |
7639 | reloc_howto_type *howto; |
7640 | int i; | |
34ce925e | 7641 | |
df58fc94 RS |
7642 | /* Perform any necessary conversion to microMIPS relocations |
7643 | and find out how many relocations there actually are. */ | |
7644 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) | |
7645 | final_type[i] = micromips_map_reloc (reloc_type[i]); | |
7646 | ||
9fe77896 RS |
7647 | /* In a compound relocation, it is the final (outermost) |
7648 | operator that determines the relocated field. */ | |
2309ddf2 | 7649 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
e8044f35 RS |
7650 | if (!howto) |
7651 | abort (); | |
2309ddf2 MR |
7652 | |
7653 | if (i > 1) | |
7654 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); | |
9fe77896 RS |
7655 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
7656 | bfd_get_reloc_size (howto), | |
7657 | address_expr, | |
2309ddf2 MR |
7658 | howto0 && howto0->pc_relative, |
7659 | final_type[0]); | |
ce8ad872 MR |
7660 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
7661 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; | |
9fe77896 RS |
7662 | |
7663 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ | |
2309ddf2 | 7664 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
9fe77896 RS |
7665 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
7666 | ||
7667 | /* These relocations can have an addend that won't fit in | |
7668 | 4 octets for 64bit assembly. */ | |
bad1aba3 | 7669 | if (GPR_SIZE == 64 |
9fe77896 RS |
7670 | && ! howto->partial_inplace |
7671 | && (reloc_type[0] == BFD_RELOC_16 | |
7672 | || reloc_type[0] == BFD_RELOC_32 | |
7673 | || reloc_type[0] == BFD_RELOC_MIPS_JMP | |
7674 | || reloc_type[0] == BFD_RELOC_GPREL16 | |
7675 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL | |
7676 | || reloc_type[0] == BFD_RELOC_GPREL32 | |
7677 | || reloc_type[0] == BFD_RELOC_64 | |
7678 | || reloc_type[0] == BFD_RELOC_CTOR | |
7679 | || reloc_type[0] == BFD_RELOC_MIPS_SUB | |
7680 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST | |
7681 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER | |
7682 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP | |
7683 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 | |
7684 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT | |
7685 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL | |
7686 | || hi16_reloc_p (reloc_type[0]) | |
7687 | || lo16_reloc_p (reloc_type[0]))) | |
7688 | ip->fixp[0]->fx_no_overflow = 1; | |
7689 | ||
ddaf2c41 MR |
7690 | /* These relocations can have an addend that won't fit in 2 octets. */ |
7691 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
7692 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) | |
7693 | ip->fixp[0]->fx_no_overflow = 1; | |
7694 | ||
9fe77896 RS |
7695 | if (mips_relax.sequence) |
7696 | { | |
7697 | if (mips_relax.first_fixup == 0) | |
7698 | mips_relax.first_fixup = ip->fixp[0]; | |
7699 | } | |
7700 | else if (reloc_needs_lo_p (*reloc_type)) | |
7701 | { | |
7702 | struct mips_hi_fixup *hi_fixup; | |
7703 | ||
7704 | /* Reuse the last entry if it already has a matching %lo. */ | |
7705 | hi_fixup = mips_hi_fixup_list; | |
7706 | if (hi_fixup == 0 | |
7707 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) | |
4d7206a2 | 7708 | { |
325801bd | 7709 | hi_fixup = XNEW (struct mips_hi_fixup); |
9fe77896 RS |
7710 | hi_fixup->next = mips_hi_fixup_list; |
7711 | mips_hi_fixup_list = hi_fixup; | |
4d7206a2 | 7712 | } |
9fe77896 RS |
7713 | hi_fixup->fixp = ip->fixp[0]; |
7714 | hi_fixup->seg = now_seg; | |
7715 | } | |
252b5132 | 7716 | |
9fe77896 RS |
7717 | /* Add fixups for the second and third relocations, if given. |
7718 | Note that the ABI allows the second relocation to be | |
7719 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the | |
7720 | moment we only use RSS_UNDEF, but we could add support | |
7721 | for the others if it ever becomes necessary. */ | |
7722 | for (i = 1; i < 3; i++) | |
7723 | if (reloc_type[i] != BFD_RELOC_UNUSED) | |
7724 | { | |
7725 | ip->fixp[i] = fix_new (ip->frag, ip->where, | |
7726 | ip->fixp[0]->fx_size, NULL, 0, | |
df58fc94 | 7727 | FALSE, final_type[i]); |
f6688943 | 7728 | |
9fe77896 RS |
7729 | /* Use fx_tcbit to mark compound relocs. */ |
7730 | ip->fixp[0]->fx_tcbit = 1; | |
7731 | ip->fixp[i]->fx_tcbit = 1; | |
7732 | } | |
252b5132 | 7733 | } |
252b5132 RH |
7734 | |
7735 | /* Update the register mask information. */ | |
4c260379 RS |
7736 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
7737 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); | |
252b5132 | 7738 | |
a4e06468 | 7739 | switch (method) |
252b5132 | 7740 | { |
a4e06468 RS |
7741 | case APPEND_ADD: |
7742 | insert_into_history (0, 1, ip); | |
7743 | break; | |
7744 | ||
7745 | case APPEND_ADD_WITH_NOP: | |
14fe068b RS |
7746 | { |
7747 | struct mips_cl_insn *nop; | |
7748 | ||
7749 | insert_into_history (0, 1, ip); | |
7750 | nop = get_delay_slot_nop (ip); | |
7751 | add_fixed_insn (nop); | |
7752 | insert_into_history (0, 1, nop); | |
7753 | if (mips_relax.sequence) | |
7754 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); | |
7755 | } | |
a4e06468 RS |
7756 | break; |
7757 | ||
7758 | case APPEND_ADD_COMPACT: | |
7759 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ | |
7bd374a4 MR |
7760 | if (mips_opts.mips16) |
7761 | { | |
7762 | ip->insn_opcode |= 0x0080; | |
7763 | find_altered_mips16_opcode (ip); | |
7764 | } | |
7765 | /* Convert microMIPS instructions. */ | |
7766 | else if (mips_opts.micromips) | |
7767 | { | |
7768 | /* jr16->jrc */ | |
7769 | if ((ip->insn_opcode & 0xffe0) == 0x4580) | |
7770 | ip->insn_opcode |= 0x0020; | |
7771 | /* b16->bc */ | |
7772 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) | |
7773 | ip->insn_opcode = 0x40e00000; | |
7774 | /* beqz16->beqzc, bnez16->bnezc */ | |
7775 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) | |
7776 | { | |
7777 | unsigned long regno; | |
7778 | ||
7779 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; | |
7780 | regno &= MICROMIPSOP_MASK_MD; | |
7781 | regno = micromips_to_32_reg_d_map[regno]; | |
7782 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) | |
7783 | | (regno << MICROMIPSOP_SH_RS) | |
7784 | | 0x40a00000) ^ 0x00400000; | |
7785 | } | |
7786 | /* beqz->beqzc, bnez->bnezc */ | |
7787 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) | |
7788 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) | |
7789 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7790 | | 0x40a00000) ^ 0x00400000; | |
7791 | /* beq $0->beqzc, bne $0->bnezc */ | |
7792 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) | |
7793 | ip->insn_opcode = (((ip->insn_opcode >> | |
7794 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) | |
7795 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) | |
7796 | | ((ip->insn_opcode >> 7) & 0x00400000) | |
7797 | | 0x40a00000) ^ 0x00400000; | |
7798 | else | |
7799 | abort (); | |
7800 | find_altered_micromips_opcode (ip); | |
7801 | } | |
7802 | else | |
7803 | abort (); | |
a4e06468 RS |
7804 | install_insn (ip); |
7805 | insert_into_history (0, 1, ip); | |
7806 | break; | |
7807 | ||
7808 | case APPEND_SWAP: | |
7809 | { | |
7810 | struct mips_cl_insn delay = history[0]; | |
99e7978b MF |
7811 | |
7812 | if (relaxed_branch || delay.frag != ip->frag) | |
a4e06468 RS |
7813 | { |
7814 | /* Add the delay slot instruction to the end of the | |
7815 | current frag and shrink the fixed part of the | |
7816 | original frag. If the branch occupies the tail of | |
7817 | the latter, move it backwards to cover the gap. */ | |
2b0c8b40 | 7818 | delay.frag->fr_fix -= branch_disp; |
a4e06468 | 7819 | if (delay.frag == ip->frag) |
2b0c8b40 | 7820 | move_insn (ip, ip->frag, ip->where - branch_disp); |
a4e06468 RS |
7821 | add_fixed_insn (&delay); |
7822 | } | |
7823 | else | |
7824 | { | |
5e35670b MR |
7825 | /* If this is not a relaxed branch and we are in the |
7826 | same frag, then just swap the instructions. */ | |
7827 | move_insn (ip, delay.frag, delay.where); | |
7828 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); | |
a4e06468 RS |
7829 | } |
7830 | history[0] = *ip; | |
7831 | delay.fixed_p = 1; | |
7832 | insert_into_history (0, 1, &delay); | |
7833 | } | |
7834 | break; | |
252b5132 RH |
7835 | } |
7836 | ||
13408f1e | 7837 | /* If we have just completed an unconditional branch, clear the history. */ |
11625dd8 RS |
7838 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
7839 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) | |
e407c74b NC |
7840 | { |
7841 | unsigned int i; | |
7842 | ||
79850f26 | 7843 | mips_no_prev_insn (); |
13408f1e | 7844 | |
e407c74b | 7845 | for (i = 0; i < ARRAY_SIZE (history); i++) |
79850f26 | 7846 | history[i].cleared_p = 1; |
e407c74b NC |
7847 | } |
7848 | ||
df58fc94 RS |
7849 | /* We need to emit a label at the end of branch-likely macros. */ |
7850 | if (emit_branch_likely_macro) | |
7851 | { | |
7852 | emit_branch_likely_macro = FALSE; | |
7853 | micromips_add_label (); | |
7854 | } | |
7855 | ||
252b5132 RH |
7856 | /* We just output an insn, so the next one doesn't have a label. */ |
7857 | mips_clear_insn_labels (); | |
252b5132 RH |
7858 | } |
7859 | ||
e407c74b NC |
7860 | /* Forget that there was any previous instruction or label. |
7861 | When BRANCH is true, the branch history is also flushed. */ | |
252b5132 RH |
7862 | |
7863 | static void | |
7d10b47d | 7864 | mips_no_prev_insn (void) |
252b5132 | 7865 | { |
7d10b47d RS |
7866 | prev_nop_frag = NULL; |
7867 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); | |
252b5132 RH |
7868 | mips_clear_insn_labels (); |
7869 | } | |
7870 | ||
7d10b47d RS |
7871 | /* This function must be called before we emit something other than |
7872 | instructions. It is like mips_no_prev_insn except that it inserts | |
7873 | any NOPS that might be needed by previous instructions. */ | |
252b5132 | 7874 | |
7d10b47d RS |
7875 | void |
7876 | mips_emit_delays (void) | |
252b5132 RH |
7877 | { |
7878 | if (! mips_opts.noreorder) | |
7879 | { | |
932d1a1b | 7880 | int nops = nops_for_insn (0, history, NULL); |
252b5132 RH |
7881 | if (nops > 0) |
7882 | { | |
7d10b47d RS |
7883 | while (nops-- > 0) |
7884 | add_fixed_insn (NOP_INSN); | |
462427c4 | 7885 | mips_move_text_labels (); |
7d10b47d RS |
7886 | } |
7887 | } | |
7888 | mips_no_prev_insn (); | |
7889 | } | |
7890 | ||
7891 | /* Start a (possibly nested) noreorder block. */ | |
7892 | ||
7893 | static void | |
7894 | start_noreorder (void) | |
7895 | { | |
7896 | if (mips_opts.noreorder == 0) | |
7897 | { | |
7898 | unsigned int i; | |
7899 | int nops; | |
7900 | ||
7901 | /* None of the instructions before the .set noreorder can be moved. */ | |
7902 | for (i = 0; i < ARRAY_SIZE (history); i++) | |
7903 | history[i].fixed_p = 1; | |
7904 | ||
7905 | /* Insert any nops that might be needed between the .set noreorder | |
7906 | block and the previous instructions. We will later remove any | |
7907 | nops that turn out not to be needed. */ | |
932d1a1b | 7908 | nops = nops_for_insn (0, history, NULL); |
7d10b47d RS |
7909 | if (nops > 0) |
7910 | { | |
7911 | if (mips_optimize != 0) | |
252b5132 RH |
7912 | { |
7913 | /* Record the frag which holds the nop instructions, so | |
7914 | that we can remove them if we don't need them. */ | |
df58fc94 | 7915 | frag_grow (nops * NOP_INSN_SIZE); |
252b5132 RH |
7916 | prev_nop_frag = frag_now; |
7917 | prev_nop_frag_holds = nops; | |
7918 | prev_nop_frag_required = 0; | |
7919 | prev_nop_frag_since = 0; | |
7920 | } | |
7921 | ||
7922 | for (; nops > 0; --nops) | |
1e915849 | 7923 | add_fixed_insn (NOP_INSN); |
252b5132 | 7924 | |
7d10b47d RS |
7925 | /* Move on to a new frag, so that it is safe to simply |
7926 | decrease the size of prev_nop_frag. */ | |
7927 | frag_wane (frag_now); | |
7928 | frag_new (0); | |
462427c4 | 7929 | mips_move_text_labels (); |
252b5132 | 7930 | } |
df58fc94 | 7931 | mips_mark_labels (); |
7d10b47d | 7932 | mips_clear_insn_labels (); |
252b5132 | 7933 | } |
7d10b47d RS |
7934 | mips_opts.noreorder++; |
7935 | mips_any_noreorder = 1; | |
7936 | } | |
252b5132 | 7937 | |
7d10b47d | 7938 | /* End a nested noreorder block. */ |
252b5132 | 7939 | |
7d10b47d RS |
7940 | static void |
7941 | end_noreorder (void) | |
7942 | { | |
7943 | mips_opts.noreorder--; | |
7944 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) | |
7945 | { | |
7946 | /* Commit to inserting prev_nop_frag_required nops and go back to | |
7947 | handling nop insertion the .set reorder way. */ | |
7948 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) | |
df58fc94 | 7949 | * NOP_INSN_SIZE); |
7d10b47d RS |
7950 | insert_into_history (prev_nop_frag_since, |
7951 | prev_nop_frag_required, NOP_INSN); | |
7952 | prev_nop_frag = NULL; | |
7953 | } | |
252b5132 RH |
7954 | } |
7955 | ||
97d87491 RS |
7956 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
7957 | higher bits unset. */ | |
7958 | ||
7959 | static void | |
7960 | normalize_constant_expr (expressionS *ex) | |
7961 | { | |
7962 | if (ex->X_op == O_constant | |
7963 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7964 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7965 | - 0x80000000); | |
7966 | } | |
7967 | ||
7968 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and | |
7969 | all higher bits unset. */ | |
7970 | ||
7971 | static void | |
7972 | normalize_address_expr (expressionS *ex) | |
7973 | { | |
7974 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) | |
7975 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) | |
7976 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
7977 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
7978 | - 0x80000000); | |
7979 | } | |
7980 | ||
7981 | /* Try to match TOKENS against OPCODE, storing the result in INSN. | |
7982 | Return true if the match was successful. | |
7983 | ||
7984 | OPCODE_EXTRA is a value that should be ORed into the opcode | |
7985 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if | |
7986 | there are more alternatives after OPCODE and SOFT_MATCH is | |
7987 | as for mips_arg_info. */ | |
7988 | ||
7989 | static bfd_boolean | |
7990 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
7991 | struct mips_operand_token *tokens, unsigned int opcode_extra, | |
60f20e8b | 7992 | bfd_boolean lax_match, bfd_boolean complete_p) |
97d87491 RS |
7993 | { |
7994 | const char *args; | |
7995 | struct mips_arg_info arg; | |
7996 | const struct mips_operand *operand; | |
7997 | char c; | |
7998 | ||
7999 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8000 | offset_expr.X_op = O_absent; |
8001 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8002 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8003 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8004 | ||
8005 | create_insn (insn, opcode); | |
60f20e8b RS |
8006 | /* When no opcode suffix is specified, assume ".xyzw". */ |
8007 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) | |
8008 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; | |
8009 | else | |
8010 | insn->insn_opcode |= opcode_extra; | |
97d87491 RS |
8011 | memset (&arg, 0, sizeof (arg)); |
8012 | arg.insn = insn; | |
8013 | arg.token = tokens; | |
8014 | arg.argnum = 1; | |
8015 | arg.last_regno = ILLEGAL_REG; | |
8016 | arg.dest_regno = ILLEGAL_REG; | |
60f20e8b | 8017 | arg.lax_match = lax_match; |
97d87491 RS |
8018 | for (args = opcode->args;; ++args) |
8019 | { | |
8020 | if (arg.token->type == OT_END) | |
8021 | { | |
8022 | /* Handle unary instructions in which only one operand is given. | |
8023 | The source is then the same as the destination. */ | |
8024 | if (arg.opnum == 1 && *args == ',') | |
8025 | { | |
8026 | operand = (mips_opts.micromips | |
8027 | ? decode_micromips_operand (args + 1) | |
8028 | : decode_mips_operand (args + 1)); | |
8029 | if (operand && mips_optional_operand_p (operand)) | |
8030 | { | |
8031 | arg.token = tokens; | |
8032 | arg.argnum = 1; | |
8033 | continue; | |
8034 | } | |
8035 | } | |
8036 | ||
8037 | /* Treat elided base registers as $0. */ | |
8038 | if (strcmp (args, "(b)") == 0) | |
8039 | args += 3; | |
8040 | ||
8041 | if (args[0] == '+') | |
8042 | switch (args[1]) | |
8043 | { | |
8044 | case 'K': | |
8045 | case 'N': | |
8046 | /* The register suffix is optional. */ | |
8047 | args += 2; | |
8048 | break; | |
8049 | } | |
8050 | ||
8051 | /* Fail the match if there were too few operands. */ | |
8052 | if (*args) | |
8053 | return FALSE; | |
8054 | ||
8055 | /* Successful match. */ | |
60f20e8b RS |
8056 | if (!complete_p) |
8057 | return TRUE; | |
e3de51ce | 8058 | clear_insn_error (); |
97d87491 RS |
8059 | if (arg.dest_regno == arg.last_regno |
8060 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) | |
8061 | { | |
8062 | if (arg.opnum == 2) | |
e3de51ce | 8063 | set_insn_error |
1661c76c | 8064 | (0, _("source and destination must be different")); |
97d87491 | 8065 | else if (arg.last_regno == 31) |
e3de51ce | 8066 | set_insn_error |
1661c76c | 8067 | (0, _("a destination register must be supplied")); |
97d87491 | 8068 | } |
173d3447 CF |
8069 | else if (arg.last_regno == 31 |
8070 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 | |
8071 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) | |
8072 | set_insn_error (0, _("the source register must not be $31")); | |
97d87491 RS |
8073 | check_completed_insn (&arg); |
8074 | return TRUE; | |
8075 | } | |
8076 | ||
8077 | /* Fail the match if the line has too many operands. */ | |
8078 | if (*args == 0) | |
8079 | return FALSE; | |
8080 | ||
8081 | /* Handle characters that need to match exactly. */ | |
8082 | if (*args == '(' || *args == ')' || *args == ',') | |
8083 | { | |
8084 | if (match_char (&arg, *args)) | |
8085 | continue; | |
8086 | return FALSE; | |
8087 | } | |
8088 | if (*args == '#') | |
8089 | { | |
8090 | ++args; | |
8091 | if (arg.token->type == OT_DOUBLE_CHAR | |
8092 | && arg.token->u.ch == *args) | |
8093 | { | |
8094 | ++arg.token; | |
8095 | continue; | |
8096 | } | |
8097 | return FALSE; | |
8098 | } | |
8099 | ||
8100 | /* Handle special macro operands. Work out the properties of | |
8101 | other operands. */ | |
8102 | arg.opnum += 1; | |
97d87491 RS |
8103 | switch (*args) |
8104 | { | |
7361da2c AB |
8105 | case '-': |
8106 | switch (args[1]) | |
8107 | { | |
8108 | case 'A': | |
8109 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; | |
8110 | break; | |
8111 | ||
8112 | case 'B': | |
8113 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; | |
8114 | break; | |
8115 | } | |
8116 | break; | |
8117 | ||
97d87491 RS |
8118 | case '+': |
8119 | switch (args[1]) | |
8120 | { | |
97d87491 RS |
8121 | case 'i': |
8122 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8123 | break; | |
7361da2c AB |
8124 | |
8125 | case '\'': | |
8126 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; | |
8127 | break; | |
8128 | ||
8129 | case '\"': | |
8130 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; | |
8131 | break; | |
97d87491 RS |
8132 | } |
8133 | break; | |
8134 | ||
97d87491 | 8135 | case 'I': |
1a00e612 RS |
8136 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8137 | return FALSE; | |
8138 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8139 | if (GPR_SIZE == 32) |
97d87491 RS |
8140 | normalize_constant_expr (&imm_expr); |
8141 | continue; | |
8142 | ||
8143 | case 'A': | |
8144 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8145 | { | |
8146 | /* Assume that the offset has been elided and that what | |
8147 | we saw was a base register. The match will fail later | |
8148 | if that assumption turns out to be wrong. */ | |
8149 | offset_expr.X_op = O_constant; | |
8150 | offset_expr.X_add_number = 0; | |
8151 | } | |
97d87491 | 8152 | else |
1a00e612 RS |
8153 | { |
8154 | if (!match_expression (&arg, &offset_expr, offset_reloc)) | |
8155 | return FALSE; | |
8156 | normalize_address_expr (&offset_expr); | |
8157 | } | |
97d87491 RS |
8158 | continue; |
8159 | ||
8160 | case 'F': | |
8161 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8162 | 8, TRUE)) | |
1a00e612 | 8163 | return FALSE; |
97d87491 RS |
8164 | continue; |
8165 | ||
8166 | case 'L': | |
8167 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8168 | 8, FALSE)) | |
1a00e612 | 8169 | return FALSE; |
97d87491 RS |
8170 | continue; |
8171 | ||
8172 | case 'f': | |
8173 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8174 | 4, TRUE)) | |
1a00e612 | 8175 | return FALSE; |
97d87491 RS |
8176 | continue; |
8177 | ||
8178 | case 'l': | |
8179 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, | |
8180 | 4, FALSE)) | |
1a00e612 | 8181 | return FALSE; |
97d87491 RS |
8182 | continue; |
8183 | ||
97d87491 RS |
8184 | case 'p': |
8185 | *offset_reloc = BFD_RELOC_16_PCREL_S2; | |
8186 | break; | |
8187 | ||
8188 | case 'a': | |
8189 | *offset_reloc = BFD_RELOC_MIPS_JMP; | |
8190 | break; | |
8191 | ||
8192 | case 'm': | |
8193 | gas_assert (mips_opts.micromips); | |
8194 | c = args[1]; | |
8195 | switch (c) | |
8196 | { | |
8197 | case 'D': | |
8198 | case 'E': | |
8199 | if (!forced_insn_length) | |
8200 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; | |
8201 | else if (c == 'D') | |
8202 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; | |
8203 | else | |
8204 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; | |
8205 | break; | |
8206 | } | |
8207 | break; | |
8208 | } | |
8209 | ||
8210 | operand = (mips_opts.micromips | |
8211 | ? decode_micromips_operand (args) | |
8212 | : decode_mips_operand (args)); | |
8213 | if (!operand) | |
8214 | abort (); | |
8215 | ||
8216 | /* Skip prefixes. */ | |
7361da2c | 8217 | if (*args == '+' || *args == 'm' || *args == '-') |
97d87491 RS |
8218 | args++; |
8219 | ||
8220 | if (mips_optional_operand_p (operand) | |
8221 | && args[1] == ',' | |
8222 | && (arg.token[0].type != OT_REG | |
8223 | || arg.token[1].type == OT_END)) | |
8224 | { | |
8225 | /* Assume that the register has been elided and is the | |
8226 | same as the first operand. */ | |
8227 | arg.token = tokens; | |
8228 | arg.argnum = 1; | |
8229 | } | |
8230 | ||
8231 | if (!match_operand (&arg, operand)) | |
8232 | return FALSE; | |
8233 | } | |
8234 | } | |
8235 | ||
8236 | /* Like match_insn, but for MIPS16. */ | |
8237 | ||
8238 | static bfd_boolean | |
8239 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, | |
1a00e612 | 8240 | struct mips_operand_token *tokens) |
97d87491 RS |
8241 | { |
8242 | const char *args; | |
8243 | const struct mips_operand *operand; | |
8244 | const struct mips_operand *ext_operand; | |
82d808ed | 8245 | bfd_boolean pcrel = FALSE; |
7fd53920 | 8246 | int required_insn_length; |
97d87491 RS |
8247 | struct mips_arg_info arg; |
8248 | int relax_char; | |
8249 | ||
7fd53920 MR |
8250 | if (forced_insn_length) |
8251 | required_insn_length = forced_insn_length; | |
8252 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) | |
8253 | required_insn_length = 2; | |
8254 | else | |
8255 | required_insn_length = 0; | |
8256 | ||
97d87491 RS |
8257 | create_insn (insn, opcode); |
8258 | imm_expr.X_op = O_absent; | |
97d87491 RS |
8259 | offset_expr.X_op = O_absent; |
8260 | offset_reloc[0] = BFD_RELOC_UNUSED; | |
8261 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
8262 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
8263 | relax_char = 0; | |
8264 | ||
8265 | memset (&arg, 0, sizeof (arg)); | |
8266 | arg.insn = insn; | |
8267 | arg.token = tokens; | |
8268 | arg.argnum = 1; | |
8269 | arg.last_regno = ILLEGAL_REG; | |
8270 | arg.dest_regno = ILLEGAL_REG; | |
97d87491 RS |
8271 | relax_char = 0; |
8272 | for (args = opcode->args;; ++args) | |
8273 | { | |
8274 | int c; | |
8275 | ||
8276 | if (arg.token->type == OT_END) | |
8277 | { | |
8278 | offsetT value; | |
8279 | ||
8280 | /* Handle unary instructions in which only one operand is given. | |
8281 | The source is then the same as the destination. */ | |
8282 | if (arg.opnum == 1 && *args == ',') | |
8283 | { | |
8284 | operand = decode_mips16_operand (args[1], FALSE); | |
8285 | if (operand && mips_optional_operand_p (operand)) | |
8286 | { | |
8287 | arg.token = tokens; | |
8288 | arg.argnum = 1; | |
8289 | continue; | |
8290 | } | |
8291 | } | |
8292 | ||
8293 | /* Fail the match if there were too few operands. */ | |
8294 | if (*args) | |
8295 | return FALSE; | |
8296 | ||
8297 | /* Successful match. Stuff the immediate value in now, if | |
8298 | we can. */ | |
e3de51ce | 8299 | clear_insn_error (); |
97d87491 RS |
8300 | if (opcode->pinfo == INSN_MACRO) |
8301 | { | |
8302 | gas_assert (relax_char == 0 || relax_char == 'p'); | |
8303 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); | |
8304 | } | |
8305 | else if (relax_char | |
8306 | && offset_expr.X_op == O_constant | |
82d808ed | 8307 | && !pcrel |
97d87491 RS |
8308 | && calculate_reloc (*offset_reloc, |
8309 | offset_expr.X_add_number, | |
8310 | &value)) | |
8311 | { | |
8312 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, | |
7fd53920 | 8313 | required_insn_length, &insn->insn_opcode); |
97d87491 RS |
8314 | offset_expr.X_op = O_absent; |
8315 | *offset_reloc = BFD_RELOC_UNUSED; | |
8316 | } | |
8317 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) | |
8318 | { | |
7fd53920 | 8319 | if (required_insn_length == 2) |
e3de51ce | 8320 | set_insn_error (0, _("invalid unextended operand value")); |
25499ac7 | 8321 | else if (!mips_opcode_32bit_p (opcode)) |
1da43acc MR |
8322 | { |
8323 | forced_insn_length = 4; | |
8324 | insn->insn_opcode |= MIPS16_EXTEND; | |
8325 | } | |
97d87491 RS |
8326 | } |
8327 | else if (relax_char) | |
8328 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; | |
8329 | ||
8330 | check_completed_insn (&arg); | |
8331 | return TRUE; | |
8332 | } | |
8333 | ||
8334 | /* Fail the match if the line has too many operands. */ | |
8335 | if (*args == 0) | |
8336 | return FALSE; | |
8337 | ||
8338 | /* Handle characters that need to match exactly. */ | |
8339 | if (*args == '(' || *args == ')' || *args == ',') | |
8340 | { | |
8341 | if (match_char (&arg, *args)) | |
8342 | continue; | |
8343 | return FALSE; | |
8344 | } | |
8345 | ||
8346 | arg.opnum += 1; | |
8347 | c = *args; | |
8348 | switch (c) | |
8349 | { | |
8350 | case 'p': | |
8351 | case 'q': | |
8352 | case 'A': | |
8353 | case 'B': | |
8354 | case 'E': | |
25499ac7 MR |
8355 | case 'V': |
8356 | case 'u': | |
97d87491 RS |
8357 | relax_char = c; |
8358 | break; | |
8359 | ||
8360 | case 'I': | |
1a00e612 RS |
8361 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
8362 | return FALSE; | |
8363 | imm_expr.X_op = O_constant; | |
bad1aba3 | 8364 | if (GPR_SIZE == 32) |
97d87491 RS |
8365 | normalize_constant_expr (&imm_expr); |
8366 | continue; | |
8367 | ||
8368 | case 'a': | |
8369 | case 'i': | |
8370 | *offset_reloc = BFD_RELOC_MIPS16_JMP; | |
97d87491 RS |
8371 | break; |
8372 | } | |
8373 | ||
7fd53920 | 8374 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
97d87491 RS |
8375 | if (!operand) |
8376 | abort (); | |
8377 | ||
82d808ed MR |
8378 | if (operand->type == OP_PCREL) |
8379 | pcrel = TRUE; | |
8380 | else | |
97d87491 RS |
8381 | { |
8382 | ext_operand = decode_mips16_operand (c, TRUE); | |
8383 | if (operand != ext_operand) | |
8384 | { | |
8385 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') | |
8386 | { | |
8387 | offset_expr.X_op = O_constant; | |
8388 | offset_expr.X_add_number = 0; | |
8389 | relax_char = c; | |
8390 | continue; | |
8391 | } | |
8392 | ||
1a7bf198 | 8393 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
97d87491 RS |
8394 | return FALSE; |
8395 | ||
8396 | /* '8' is used for SLTI(U) and has traditionally not | |
8397 | been allowed to take relocation operators. */ | |
8398 | if (offset_reloc[0] != BFD_RELOC_UNUSED | |
8399 | && (ext_operand->size != 16 || c == '8')) | |
e295202f MR |
8400 | { |
8401 | match_not_constant (&arg); | |
8402 | return FALSE; | |
8403 | } | |
97d87491 | 8404 | |
c96425c5 MR |
8405 | if (offset_expr.X_op == O_big) |
8406 | { | |
8407 | match_out_of_range (&arg); | |
8408 | return FALSE; | |
8409 | } | |
8410 | ||
97d87491 RS |
8411 | relax_char = c; |
8412 | continue; | |
8413 | } | |
8414 | } | |
8415 | ||
8416 | if (mips_optional_operand_p (operand) | |
8417 | && args[1] == ',' | |
8418 | && (arg.token[0].type != OT_REG | |
8419 | || arg.token[1].type == OT_END)) | |
8420 | { | |
8421 | /* Assume that the register has been elided and is the | |
8422 | same as the first operand. */ | |
8423 | arg.token = tokens; | |
8424 | arg.argnum = 1; | |
8425 | } | |
8426 | ||
8427 | if (!match_operand (&arg, operand)) | |
8428 | return FALSE; | |
8429 | } | |
8430 | } | |
8431 | ||
60f20e8b RS |
8432 | /* Record that the current instruction is invalid for the current ISA. */ |
8433 | ||
8434 | static void | |
8435 | match_invalid_for_isa (void) | |
8436 | { | |
8437 | set_insn_error_ss | |
1661c76c | 8438 | (0, _("opcode not supported on this processor: %s (%s)"), |
60f20e8b RS |
8439 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
8440 | mips_cpu_info_from_isa (mips_opts.isa)->name); | |
8441 | } | |
8442 | ||
8443 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. | |
8444 | Return true if a definite match or failure was found, storing any match | |
8445 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode | |
8446 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already | |
8447 | tried and failed to match under normal conditions and now want to try a | |
8448 | more relaxed match. */ | |
8449 | ||
8450 | static bfd_boolean | |
8451 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8452 | const struct mips_opcode *past, struct mips_operand_token *tokens, | |
8453 | int opcode_extra, bfd_boolean lax_match) | |
8454 | { | |
8455 | const struct mips_opcode *opcode; | |
8456 | const struct mips_opcode *invalid_delay_slot; | |
8457 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; | |
8458 | ||
8459 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8460 | current ISA or forced_length. */ | |
8461 | invalid_delay_slot = 0; | |
8462 | seen_valid_for_isa = FALSE; | |
8463 | seen_valid_for_size = FALSE; | |
8464 | opcode = first; | |
8465 | do | |
8466 | { | |
8467 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8468 | if (is_opcode_valid (opcode)) | |
8469 | { | |
8470 | seen_valid_for_isa = TRUE; | |
8471 | if (is_size_valid (opcode)) | |
8472 | { | |
8473 | bfd_boolean delay_slot_ok; | |
8474 | ||
8475 | seen_valid_for_size = TRUE; | |
8476 | delay_slot_ok = is_delay_slot_valid (opcode); | |
8477 | if (match_insn (insn, opcode, tokens, opcode_extra, | |
8478 | lax_match, delay_slot_ok)) | |
8479 | { | |
8480 | if (!delay_slot_ok) | |
8481 | { | |
8482 | if (!invalid_delay_slot) | |
8483 | invalid_delay_slot = opcode; | |
8484 | } | |
8485 | else | |
8486 | return TRUE; | |
8487 | } | |
8488 | } | |
8489 | } | |
8490 | ++opcode; | |
8491 | } | |
8492 | while (opcode < past && strcmp (opcode->name, first->name) == 0); | |
8493 | ||
8494 | /* If the only matches we found had the wrong length for the delay slot, | |
8495 | pick the first such match. We'll issue an appropriate warning later. */ | |
8496 | if (invalid_delay_slot) | |
8497 | { | |
8498 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, | |
8499 | lax_match, TRUE)) | |
8500 | return TRUE; | |
8501 | abort (); | |
8502 | } | |
8503 | ||
8504 | /* Handle the case where we didn't try to match an instruction because | |
8505 | all the alternatives were incompatible with the current ISA. */ | |
8506 | if (!seen_valid_for_isa) | |
8507 | { | |
8508 | match_invalid_for_isa (); | |
8509 | return TRUE; | |
8510 | } | |
8511 | ||
8512 | /* Handle the case where we didn't try to match an instruction because | |
8513 | all the alternatives were of the wrong size. */ | |
8514 | if (!seen_valid_for_size) | |
8515 | { | |
8516 | if (mips_opts.insn32) | |
1661c76c | 8517 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
60f20e8b RS |
8518 | else |
8519 | set_insn_error_i | |
1661c76c | 8520 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
60f20e8b RS |
8521 | 8 * forced_insn_length); |
8522 | return TRUE; | |
8523 | } | |
8524 | ||
8525 | return FALSE; | |
8526 | } | |
8527 | ||
8528 | /* Like match_insns, but for MIPS16. */ | |
8529 | ||
8530 | static bfd_boolean | |
8531 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, | |
8532 | struct mips_operand_token *tokens) | |
8533 | { | |
8534 | const struct mips_opcode *opcode; | |
8535 | bfd_boolean seen_valid_for_isa; | |
7fd53920 | 8536 | bfd_boolean seen_valid_for_size; |
60f20e8b RS |
8537 | |
8538 | /* Search for a match, ignoring alternatives that don't satisfy the | |
8539 | current ISA. There are no separate entries for extended forms so | |
8540 | we deal with forced_length later. */ | |
8541 | seen_valid_for_isa = FALSE; | |
7fd53920 | 8542 | seen_valid_for_size = FALSE; |
60f20e8b RS |
8543 | opcode = first; |
8544 | do | |
8545 | { | |
8546 | gas_assert (strcmp (opcode->name, first->name) == 0); | |
8547 | if (is_opcode_valid_16 (opcode)) | |
8548 | { | |
8549 | seen_valid_for_isa = TRUE; | |
7fd53920 MR |
8550 | if (is_size_valid_16 (opcode)) |
8551 | { | |
8552 | seen_valid_for_size = TRUE; | |
8553 | if (match_mips16_insn (insn, opcode, tokens)) | |
8554 | return TRUE; | |
8555 | } | |
60f20e8b RS |
8556 | } |
8557 | ++opcode; | |
8558 | } | |
8559 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] | |
8560 | && strcmp (opcode->name, first->name) == 0); | |
8561 | ||
8562 | /* Handle the case where we didn't try to match an instruction because | |
8563 | all the alternatives were incompatible with the current ISA. */ | |
8564 | if (!seen_valid_for_isa) | |
8565 | { | |
8566 | match_invalid_for_isa (); | |
8567 | return TRUE; | |
8568 | } | |
8569 | ||
7fd53920 MR |
8570 | /* Handle the case where we didn't try to match an instruction because |
8571 | all the alternatives were of the wrong size. */ | |
8572 | if (!seen_valid_for_size) | |
8573 | { | |
8574 | if (forced_insn_length == 2) | |
8575 | set_insn_error | |
8576 | (0, _("unrecognized unextended version of MIPS16 opcode")); | |
8577 | else | |
8578 | set_insn_error | |
8579 | (0, _("unrecognized extended version of MIPS16 opcode")); | |
8580 | return TRUE; | |
8581 | } | |
8582 | ||
60f20e8b RS |
8583 | return FALSE; |
8584 | } | |
8585 | ||
584892a6 RS |
8586 | /* Set up global variables for the start of a new macro. */ |
8587 | ||
8588 | static void | |
8589 | macro_start (void) | |
8590 | { | |
8591 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); | |
df58fc94 RS |
8592 | memset (&mips_macro_warning.first_insn_sizes, 0, |
8593 | sizeof (mips_macro_warning.first_insn_sizes)); | |
8594 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); | |
584892a6 | 8595 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
11625dd8 | 8596 | && delayed_branch_p (&history[0])); |
7bd374a4 MR |
8597 | if (history[0].frag |
8598 | && history[0].frag->fr_type == rs_machine_dependent | |
8599 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) | |
8600 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) | |
8601 | mips_macro_warning.delay_slot_length = 0; | |
8602 | else | |
8603 | switch (history[0].insn_mo->pinfo2 | |
8604 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) | |
8605 | { | |
8606 | case INSN2_BRANCH_DELAY_32BIT: | |
8607 | mips_macro_warning.delay_slot_length = 4; | |
8608 | break; | |
8609 | case INSN2_BRANCH_DELAY_16BIT: | |
8610 | mips_macro_warning.delay_slot_length = 2; | |
8611 | break; | |
8612 | default: | |
8613 | mips_macro_warning.delay_slot_length = 0; | |
8614 | break; | |
8615 | } | |
df58fc94 | 8616 | mips_macro_warning.first_frag = NULL; |
584892a6 RS |
8617 | } |
8618 | ||
df58fc94 RS |
8619 | /* Given that a macro is longer than one instruction or of the wrong size, |
8620 | return the appropriate warning for it. Return null if no warning is | |
8621 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, | |
8622 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, | |
8623 | and RELAX_NOMACRO. */ | |
584892a6 RS |
8624 | |
8625 | static const char * | |
8626 | macro_warning (relax_substateT subtype) | |
8627 | { | |
8628 | if (subtype & RELAX_DELAY_SLOT) | |
1661c76c | 8629 | return _("macro instruction expanded into multiple instructions" |
584892a6 RS |
8630 | " in a branch delay slot"); |
8631 | else if (subtype & RELAX_NOMACRO) | |
1661c76c | 8632 | return _("macro instruction expanded into multiple instructions"); |
df58fc94 RS |
8633 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
8634 | | RELAX_DELAY_SLOT_SIZE_SECOND)) | |
8635 | return ((subtype & RELAX_DELAY_SLOT_16BIT) | |
1661c76c | 8636 | ? _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8637 | " in a 16-bit branch delay slot") |
1661c76c | 8638 | : _("macro instruction expanded into a wrong size instruction" |
df58fc94 | 8639 | " in a 32-bit branch delay slot")); |
584892a6 RS |
8640 | else |
8641 | return 0; | |
8642 | } | |
8643 | ||
8644 | /* Finish up a macro. Emit warnings as appropriate. */ | |
8645 | ||
8646 | static void | |
8647 | macro_end (void) | |
8648 | { | |
df58fc94 RS |
8649 | /* Relaxation warning flags. */ |
8650 | relax_substateT subtype = 0; | |
8651 | ||
8652 | /* Check delay slot size requirements. */ | |
8653 | if (mips_macro_warning.delay_slot_length == 2) | |
8654 | subtype |= RELAX_DELAY_SLOT_16BIT; | |
8655 | if (mips_macro_warning.delay_slot_length != 0) | |
584892a6 | 8656 | { |
df58fc94 RS |
8657 | if (mips_macro_warning.delay_slot_length |
8658 | != mips_macro_warning.first_insn_sizes[0]) | |
8659 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; | |
8660 | if (mips_macro_warning.delay_slot_length | |
8661 | != mips_macro_warning.first_insn_sizes[1]) | |
8662 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; | |
8663 | } | |
584892a6 | 8664 | |
df58fc94 RS |
8665 | /* Check instruction count requirements. */ |
8666 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) | |
8667 | { | |
8668 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) | |
584892a6 RS |
8669 | subtype |= RELAX_SECOND_LONGER; |
8670 | if (mips_opts.warn_about_macros) | |
8671 | subtype |= RELAX_NOMACRO; | |
8672 | if (mips_macro_warning.delay_slot_p) | |
8673 | subtype |= RELAX_DELAY_SLOT; | |
df58fc94 | 8674 | } |
584892a6 | 8675 | |
df58fc94 RS |
8676 | /* If both alternatives fail to fill a delay slot correctly, |
8677 | emit the warning now. */ | |
8678 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 | |
8679 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) | |
8680 | { | |
8681 | relax_substateT s; | |
8682 | const char *msg; | |
8683 | ||
8684 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
8685 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
8686 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
8687 | msg = macro_warning (s); | |
8688 | if (msg != NULL) | |
8689 | as_warn ("%s", msg); | |
8690 | subtype &= ~s; | |
8691 | } | |
8692 | ||
8693 | /* If both implementations are longer than 1 instruction, then emit the | |
8694 | warning now. */ | |
8695 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) | |
8696 | { | |
8697 | relax_substateT s; | |
8698 | const char *msg; | |
8699 | ||
8700 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); | |
8701 | msg = macro_warning (s); | |
8702 | if (msg != NULL) | |
8703 | as_warn ("%s", msg); | |
8704 | subtype &= ~s; | |
584892a6 | 8705 | } |
df58fc94 RS |
8706 | |
8707 | /* If any flags still set, then one implementation might need a warning | |
8708 | and the other either will need one of a different kind or none at all. | |
8709 | Pass any remaining flags over to relaxation. */ | |
8710 | if (mips_macro_warning.first_frag != NULL) | |
8711 | mips_macro_warning.first_frag->fr_subtype |= subtype; | |
584892a6 RS |
8712 | } |
8713 | ||
df58fc94 RS |
8714 | /* Instruction operand formats used in macros that vary between |
8715 | standard MIPS and microMIPS code. */ | |
8716 | ||
833794fc | 8717 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
df58fc94 RS |
8718 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
8719 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; | |
8720 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; | |
8721 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; | |
833794fc | 8722 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
df58fc94 RS |
8723 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
8724 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; | |
8725 | ||
833794fc | 8726 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
7361da2c AB |
8727 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
8728 | : cop12_fmt[mips_opts.micromips]) | |
df58fc94 RS |
8729 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
8730 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) | |
8731 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) | |
7361da2c AB |
8732 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
8733 | : mem12_fmt[mips_opts.micromips]) | |
833794fc | 8734 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
df58fc94 RS |
8735 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
8736 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) | |
8737 | ||
6e1304d8 RS |
8738 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
8739 | The first argument in *ARGS will be either the code for a single | |
8740 | relocation or -1 followed by the three codes that make up a | |
8741 | composite relocation. */ | |
8742 | ||
8743 | static void | |
8744 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) | |
8745 | { | |
8746 | int i, next; | |
8747 | ||
8748 | next = va_arg (*args, int); | |
8749 | if (next >= 0) | |
8750 | r[0] = (bfd_reloc_code_real_type) next; | |
8751 | else | |
f2ae14a1 RS |
8752 | { |
8753 | for (i = 0; i < 3; i++) | |
8754 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); | |
8755 | /* This function is only used for 16-bit relocation fields. | |
8756 | To make the macro code simpler, treat an unrelocated value | |
8757 | in the same way as BFD_RELOC_LO16. */ | |
8758 | if (r[0] == BFD_RELOC_UNUSED) | |
8759 | r[0] = BFD_RELOC_LO16; | |
8760 | } | |
6e1304d8 RS |
8761 | } |
8762 | ||
252b5132 RH |
8763 | /* Build an instruction created by a macro expansion. This is passed |
8764 | a pointer to the count of instructions created so far, an | |
8765 | expression, the name of the instruction to build, an operand format | |
8766 | string, and corresponding arguments. */ | |
8767 | ||
252b5132 | 8768 | static void |
67c0d1eb | 8769 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
252b5132 | 8770 | { |
df58fc94 | 8771 | const struct mips_opcode *mo = NULL; |
f6688943 | 8772 | bfd_reloc_code_real_type r[3]; |
df58fc94 | 8773 | const struct mips_opcode *amo; |
e077a1c8 | 8774 | const struct mips_operand *operand; |
df58fc94 RS |
8775 | struct hash_control *hash; |
8776 | struct mips_cl_insn insn; | |
252b5132 | 8777 | va_list args; |
e077a1c8 | 8778 | unsigned int uval; |
252b5132 | 8779 | |
252b5132 | 8780 | va_start (args, fmt); |
252b5132 | 8781 | |
252b5132 RH |
8782 | if (mips_opts.mips16) |
8783 | { | |
03ea81db | 8784 | mips16_macro_build (ep, name, fmt, &args); |
252b5132 RH |
8785 | va_end (args); |
8786 | return; | |
8787 | } | |
8788 | ||
f6688943 TS |
8789 | r[0] = BFD_RELOC_UNUSED; |
8790 | r[1] = BFD_RELOC_UNUSED; | |
8791 | r[2] = BFD_RELOC_UNUSED; | |
df58fc94 RS |
8792 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
8793 | amo = (struct mips_opcode *) hash_find (hash, name); | |
8794 | gas_assert (amo); | |
8795 | gas_assert (strcmp (name, amo->name) == 0); | |
1e915849 | 8796 | |
df58fc94 | 8797 | do |
8b082fb1 TS |
8798 | { |
8799 | /* Search until we get a match for NAME. It is assumed here that | |
df58fc94 | 8800 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
33eaf5de | 8801 | We try to match an instruction that fulfills the branch delay |
df58fc94 RS |
8802 | slot instruction length requirement (if any) of the previous |
8803 | instruction. While doing this we record the first instruction | |
8804 | seen that matches all the other conditions and use it anyway | |
8805 | if the requirement cannot be met; we will issue an appropriate | |
8806 | warning later on. */ | |
8807 | if (strcmp (fmt, amo->args) == 0 | |
8808 | && amo->pinfo != INSN_MACRO | |
8809 | && is_opcode_valid (amo) | |
8810 | && is_size_valid (amo)) | |
8811 | { | |
8812 | if (is_delay_slot_valid (amo)) | |
8813 | { | |
8814 | mo = amo; | |
8815 | break; | |
8816 | } | |
8817 | else if (!mo) | |
8818 | mo = amo; | |
8819 | } | |
8b082fb1 | 8820 | |
df58fc94 RS |
8821 | ++amo; |
8822 | gas_assert (amo->name); | |
252b5132 | 8823 | } |
df58fc94 | 8824 | while (strcmp (name, amo->name) == 0); |
252b5132 | 8825 | |
df58fc94 | 8826 | gas_assert (mo); |
1e915849 | 8827 | create_insn (&insn, mo); |
e077a1c8 | 8828 | for (; *fmt; ++fmt) |
252b5132 | 8829 | { |
e077a1c8 | 8830 | switch (*fmt) |
252b5132 | 8831 | { |
252b5132 RH |
8832 | case ',': |
8833 | case '(': | |
8834 | case ')': | |
252b5132 | 8835 | case 'z': |
e077a1c8 | 8836 | break; |
252b5132 RH |
8837 | |
8838 | case 'i': | |
8839 | case 'j': | |
6e1304d8 | 8840 | macro_read_relocs (&args, r); |
9c2799c2 | 8841 | gas_assert (*r == BFD_RELOC_GPREL16 |
e391c024 RS |
8842 | || *r == BFD_RELOC_MIPS_HIGHER |
8843 | || *r == BFD_RELOC_HI16_S | |
8844 | || *r == BFD_RELOC_LO16 | |
8845 | || *r == BFD_RELOC_MIPS_GOT_OFST); | |
e077a1c8 | 8846 | break; |
e391c024 RS |
8847 | |
8848 | case 'o': | |
8849 | macro_read_relocs (&args, r); | |
e077a1c8 | 8850 | break; |
252b5132 RH |
8851 | |
8852 | case 'u': | |
6e1304d8 | 8853 | macro_read_relocs (&args, r); |
9c2799c2 | 8854 | gas_assert (ep != NULL |
90ecf173 MR |
8855 | && (ep->X_op == O_constant |
8856 | || (ep->X_op == O_symbol | |
8857 | && (*r == BFD_RELOC_MIPS_HIGHEST | |
8858 | || *r == BFD_RELOC_HI16_S | |
8859 | || *r == BFD_RELOC_HI16 | |
8860 | || *r == BFD_RELOC_GPREL16 | |
8861 | || *r == BFD_RELOC_MIPS_GOT_HI16 | |
8862 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); | |
e077a1c8 | 8863 | break; |
252b5132 RH |
8864 | |
8865 | case 'p': | |
9c2799c2 | 8866 | gas_assert (ep != NULL); |
bad36eac | 8867 | |
252b5132 RH |
8868 | /* |
8869 | * This allows macro() to pass an immediate expression for | |
8870 | * creating short branches without creating a symbol. | |
bad36eac DJ |
8871 | * |
8872 | * We don't allow branch relaxation for these branches, as | |
8873 | * they should only appear in ".set nomacro" anyway. | |
252b5132 RH |
8874 | */ |
8875 | if (ep->X_op == O_constant) | |
8876 | { | |
df58fc94 RS |
8877 | /* For microMIPS we always use relocations for branches. |
8878 | So we should not resolve immediate values. */ | |
8879 | gas_assert (!mips_opts.micromips); | |
8880 | ||
bad36eac DJ |
8881 | if ((ep->X_add_number & 3) != 0) |
8882 | as_bad (_("branch to misaligned address (0x%lx)"), | |
8883 | (unsigned long) ep->X_add_number); | |
8884 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) | |
8885 | as_bad (_("branch address range overflow (0x%lx)"), | |
8886 | (unsigned long) ep->X_add_number); | |
252b5132 RH |
8887 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
8888 | ep = NULL; | |
8889 | } | |
8890 | else | |
0b25d3e6 | 8891 | *r = BFD_RELOC_16_PCREL_S2; |
e077a1c8 | 8892 | break; |
252b5132 RH |
8893 | |
8894 | case 'a': | |
9c2799c2 | 8895 | gas_assert (ep != NULL); |
f6688943 | 8896 | *r = BFD_RELOC_MIPS_JMP; |
e077a1c8 | 8897 | break; |
d43b4baf | 8898 | |
252b5132 | 8899 | default: |
e077a1c8 RS |
8900 | operand = (mips_opts.micromips |
8901 | ? decode_micromips_operand (fmt) | |
8902 | : decode_mips_operand (fmt)); | |
8903 | if (!operand) | |
8904 | abort (); | |
8905 | ||
8906 | uval = va_arg (args, int); | |
8907 | if (operand->type == OP_CLO_CLZ_DEST) | |
8908 | uval |= (uval << 5); | |
8909 | insn_insert_operand (&insn, operand, uval); | |
8910 | ||
7361da2c | 8911 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
e077a1c8 RS |
8912 | ++fmt; |
8913 | break; | |
252b5132 | 8914 | } |
252b5132 RH |
8915 | } |
8916 | va_end (args); | |
9c2799c2 | 8917 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 8918 | |
df58fc94 | 8919 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
8920 | } |
8921 | ||
8922 | static void | |
67c0d1eb | 8923 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
03ea81db | 8924 | va_list *args) |
252b5132 | 8925 | { |
1e915849 | 8926 | struct mips_opcode *mo; |
252b5132 | 8927 | struct mips_cl_insn insn; |
e077a1c8 | 8928 | const struct mips_operand *operand; |
f6688943 TS |
8929 | bfd_reloc_code_real_type r[3] |
8930 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; | |
252b5132 | 8931 | |
1e915849 | 8932 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
9c2799c2 NC |
8933 | gas_assert (mo); |
8934 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 | 8935 | |
1e915849 | 8936 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
252b5132 | 8937 | { |
1e915849 | 8938 | ++mo; |
9c2799c2 NC |
8939 | gas_assert (mo->name); |
8940 | gas_assert (strcmp (name, mo->name) == 0); | |
252b5132 RH |
8941 | } |
8942 | ||
1e915849 | 8943 | create_insn (&insn, mo); |
e077a1c8 | 8944 | for (; *fmt; ++fmt) |
252b5132 RH |
8945 | { |
8946 | int c; | |
8947 | ||
e077a1c8 | 8948 | c = *fmt; |
252b5132 RH |
8949 | switch (c) |
8950 | { | |
252b5132 RH |
8951 | case ',': |
8952 | case '(': | |
8953 | case ')': | |
e077a1c8 | 8954 | break; |
252b5132 | 8955 | |
d8722d76 | 8956 | case '.': |
252b5132 RH |
8957 | case 'S': |
8958 | case 'P': | |
8959 | case 'R': | |
e077a1c8 | 8960 | break; |
252b5132 RH |
8961 | |
8962 | case '<': | |
252b5132 | 8963 | case '5': |
d8722d76 | 8964 | case 'F': |
252b5132 RH |
8965 | case 'H': |
8966 | case 'W': | |
8967 | case 'D': | |
8968 | case 'j': | |
8969 | case '8': | |
8970 | case 'V': | |
8971 | case 'C': | |
8972 | case 'U': | |
8973 | case 'k': | |
8974 | case 'K': | |
8975 | case 'p': | |
8976 | case 'q': | |
8977 | { | |
b886a2ab RS |
8978 | offsetT value; |
8979 | ||
9c2799c2 | 8980 | gas_assert (ep != NULL); |
252b5132 RH |
8981 | |
8982 | if (ep->X_op != O_constant) | |
874e8986 | 8983 | *r = (int) BFD_RELOC_UNUSED + c; |
b886a2ab | 8984 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
252b5132 | 8985 | { |
b886a2ab | 8986 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
252b5132 | 8987 | ep = NULL; |
f6688943 | 8988 | *r = BFD_RELOC_UNUSED; |
252b5132 RH |
8989 | } |
8990 | } | |
e077a1c8 | 8991 | break; |
252b5132 | 8992 | |
e077a1c8 RS |
8993 | default: |
8994 | operand = decode_mips16_operand (c, FALSE); | |
8995 | if (!operand) | |
8996 | abort (); | |
252b5132 | 8997 | |
4a06e5a2 | 8998 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
e077a1c8 RS |
8999 | break; |
9000 | } | |
252b5132 RH |
9001 | } |
9002 | ||
9c2799c2 | 9003 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
252b5132 | 9004 | |
df58fc94 | 9005 | append_insn (&insn, ep, r, TRUE); |
252b5132 RH |
9006 | } |
9007 | ||
438c16b8 TS |
9008 | /* |
9009 | * Generate a "jalr" instruction with a relocation hint to the called | |
9010 | * function. This occurs in NewABI PIC code. | |
9011 | */ | |
9012 | static void | |
df58fc94 | 9013 | macro_build_jalr (expressionS *ep, int cprestore) |
438c16b8 | 9014 | { |
df58fc94 RS |
9015 | static const bfd_reloc_code_real_type jalr_relocs[2] |
9016 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; | |
9017 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; | |
9018 | const char *jalr; | |
685736be | 9019 | char *f = NULL; |
b34976b6 | 9020 | |
1180b5a4 | 9021 | if (MIPS_JALR_HINT_P (ep)) |
f21f8242 | 9022 | { |
cc3d92a5 | 9023 | frag_grow (8); |
f21f8242 AO |
9024 | f = frag_more (0); |
9025 | } | |
2906b037 | 9026 | if (mips_opts.micromips) |
df58fc94 | 9027 | { |
833794fc MR |
9028 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
9029 | ? "jalr" : "jalrs"); | |
e64af278 | 9030 | if (MIPS_JALR_HINT_P (ep) |
833794fc | 9031 | || mips_opts.insn32 |
e64af278 | 9032 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
df58fc94 RS |
9033 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
9034 | else | |
9035 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); | |
9036 | } | |
2906b037 MR |
9037 | else |
9038 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); | |
1180b5a4 | 9039 | if (MIPS_JALR_HINT_P (ep)) |
df58fc94 | 9040 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
438c16b8 TS |
9041 | } |
9042 | ||
252b5132 RH |
9043 | /* |
9044 | * Generate a "lui" instruction. | |
9045 | */ | |
9046 | static void | |
67c0d1eb | 9047 | macro_build_lui (expressionS *ep, int regnum) |
252b5132 | 9048 | { |
9c2799c2 | 9049 | gas_assert (! mips_opts.mips16); |
252b5132 | 9050 | |
df58fc94 | 9051 | if (ep->X_op != O_constant) |
252b5132 | 9052 | { |
9c2799c2 | 9053 | gas_assert (ep->X_op == O_symbol); |
bbe506e8 TS |
9054 | /* _gp_disp is a special case, used from s_cpload. |
9055 | __gnu_local_gp is used if mips_no_shared. */ | |
9c2799c2 | 9056 | gas_assert (mips_pic == NO_PIC |
78e1bb40 | 9057 | || (! HAVE_NEWABI |
aa6975fb ILT |
9058 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
9059 | || (! mips_in_shared | |
bbe506e8 TS |
9060 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
9061 | "__gnu_local_gp") == 0)); | |
252b5132 RH |
9062 | } |
9063 | ||
df58fc94 | 9064 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
252b5132 RH |
9065 | } |
9066 | ||
885add95 CD |
9067 | /* Generate a sequence of instructions to do a load or store from a constant |
9068 | offset off of a base register (breg) into/from a target register (treg), | |
9069 | using AT if necessary. */ | |
9070 | static void | |
67c0d1eb RS |
9071 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
9072 | int treg, int breg, int dbl) | |
885add95 | 9073 | { |
9c2799c2 | 9074 | gas_assert (ep->X_op == O_constant); |
885add95 | 9075 | |
256ab948 | 9076 | /* Sign-extending 32-bit constants makes their handling easier. */ |
2051e8c4 MR |
9077 | if (!dbl) |
9078 | normalize_constant_expr (ep); | |
256ab948 | 9079 | |
67c1ffbe | 9080 | /* Right now, this routine can only handle signed 32-bit constants. */ |
ecd13cd3 | 9081 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
885add95 CD |
9082 | as_warn (_("operand overflow")); |
9083 | ||
9084 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) | |
9085 | { | |
9086 | /* Signed 16-bit offset will fit in the op. Easy! */ | |
67c0d1eb | 9087 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
885add95 CD |
9088 | } |
9089 | else | |
9090 | { | |
9091 | /* 32-bit offset, need multiple instructions and AT, like: | |
9092 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) | |
9093 | addu $tempreg,$tempreg,$breg | |
9094 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) | |
9095 | to handle the complete offset. */ | |
67c0d1eb RS |
9096 | macro_build_lui (ep, AT); |
9097 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); | |
9098 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); | |
885add95 | 9099 | |
741fe287 | 9100 | if (!mips_opts.at) |
1661c76c | 9101 | as_bad (_("macro used $at after \".set noat\"")); |
885add95 CD |
9102 | } |
9103 | } | |
9104 | ||
252b5132 RH |
9105 | /* set_at() |
9106 | * Generates code to set the $at register to true (one) | |
9107 | * if reg is less than the immediate expression. | |
9108 | */ | |
9109 | static void | |
67c0d1eb | 9110 | set_at (int reg, int unsignedp) |
252b5132 | 9111 | { |
b0e6f033 | 9112 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 9113 | && imm_expr.X_add_number < 0x8000) |
67c0d1eb RS |
9114 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
9115 | AT, reg, BFD_RELOC_LO16); | |
252b5132 RH |
9116 | else |
9117 | { | |
bad1aba3 | 9118 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 9119 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
252b5132 RH |
9120 | } |
9121 | } | |
9122 | ||
252b5132 RH |
9123 | /* Count the leading zeroes by performing a binary chop. This is a |
9124 | bulky bit of source, but performance is a LOT better for the | |
9125 | majority of values than a simple loop to count the bits: | |
9126 | for (lcnt = 0; (lcnt < 32); lcnt++) | |
9127 | if ((v) & (1 << (31 - lcnt))) | |
9128 | break; | |
9129 | However it is not code size friendly, and the gain will drop a bit | |
9130 | on certain cached systems. | |
9131 | */ | |
9132 | #define COUNT_TOP_ZEROES(v) \ | |
9133 | (((v) & ~0xffff) == 0 \ | |
9134 | ? ((v) & ~0xff) == 0 \ | |
9135 | ? ((v) & ~0xf) == 0 \ | |
9136 | ? ((v) & ~0x3) == 0 \ | |
9137 | ? ((v) & ~0x1) == 0 \ | |
9138 | ? !(v) \ | |
9139 | ? 32 \ | |
9140 | : 31 \ | |
9141 | : 30 \ | |
9142 | : ((v) & ~0x7) == 0 \ | |
9143 | ? 29 \ | |
9144 | : 28 \ | |
9145 | : ((v) & ~0x3f) == 0 \ | |
9146 | ? ((v) & ~0x1f) == 0 \ | |
9147 | ? 27 \ | |
9148 | : 26 \ | |
9149 | : ((v) & ~0x7f) == 0 \ | |
9150 | ? 25 \ | |
9151 | : 24 \ | |
9152 | : ((v) & ~0xfff) == 0 \ | |
9153 | ? ((v) & ~0x3ff) == 0 \ | |
9154 | ? ((v) & ~0x1ff) == 0 \ | |
9155 | ? 23 \ | |
9156 | : 22 \ | |
9157 | : ((v) & ~0x7ff) == 0 \ | |
9158 | ? 21 \ | |
9159 | : 20 \ | |
9160 | : ((v) & ~0x3fff) == 0 \ | |
9161 | ? ((v) & ~0x1fff) == 0 \ | |
9162 | ? 19 \ | |
9163 | : 18 \ | |
9164 | : ((v) & ~0x7fff) == 0 \ | |
9165 | ? 17 \ | |
9166 | : 16 \ | |
9167 | : ((v) & ~0xffffff) == 0 \ | |
9168 | ? ((v) & ~0xfffff) == 0 \ | |
9169 | ? ((v) & ~0x3ffff) == 0 \ | |
9170 | ? ((v) & ~0x1ffff) == 0 \ | |
9171 | ? 15 \ | |
9172 | : 14 \ | |
9173 | : ((v) & ~0x7ffff) == 0 \ | |
9174 | ? 13 \ | |
9175 | : 12 \ | |
9176 | : ((v) & ~0x3fffff) == 0 \ | |
9177 | ? ((v) & ~0x1fffff) == 0 \ | |
9178 | ? 11 \ | |
9179 | : 10 \ | |
9180 | : ((v) & ~0x7fffff) == 0 \ | |
9181 | ? 9 \ | |
9182 | : 8 \ | |
9183 | : ((v) & ~0xfffffff) == 0 \ | |
9184 | ? ((v) & ~0x3ffffff) == 0 \ | |
9185 | ? ((v) & ~0x1ffffff) == 0 \ | |
9186 | ? 7 \ | |
9187 | : 6 \ | |
9188 | : ((v) & ~0x7ffffff) == 0 \ | |
9189 | ? 5 \ | |
9190 | : 4 \ | |
9191 | : ((v) & ~0x3fffffff) == 0 \ | |
9192 | ? ((v) & ~0x1fffffff) == 0 \ | |
9193 | ? 3 \ | |
9194 | : 2 \ | |
9195 | : ((v) & ~0x7fffffff) == 0 \ | |
9196 | ? 1 \ | |
9197 | : 0) | |
9198 | ||
9199 | /* load_register() | |
67c1ffbe | 9200 | * This routine generates the least number of instructions necessary to load |
252b5132 RH |
9201 | * an absolute expression value into a register. |
9202 | */ | |
9203 | static void | |
67c0d1eb | 9204 | load_register (int reg, expressionS *ep, int dbl) |
252b5132 RH |
9205 | { |
9206 | int freg; | |
9207 | expressionS hi32, lo32; | |
9208 | ||
9209 | if (ep->X_op != O_big) | |
9210 | { | |
9c2799c2 | 9211 | gas_assert (ep->X_op == O_constant); |
256ab948 TS |
9212 | |
9213 | /* Sign-extending 32-bit constants makes their handling easier. */ | |
2051e8c4 MR |
9214 | if (!dbl) |
9215 | normalize_constant_expr (ep); | |
256ab948 TS |
9216 | |
9217 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) | |
252b5132 RH |
9218 | { |
9219 | /* We can handle 16 bit signed values with an addiu to | |
9220 | $zero. No need to ever use daddiu here, since $zero and | |
9221 | the result are always correct in 32 bit mode. */ | |
67c0d1eb | 9222 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9223 | return; |
9224 | } | |
9225 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) | |
9226 | { | |
9227 | /* We can handle 16 bit unsigned values with an ori to | |
9228 | $zero. */ | |
67c0d1eb | 9229 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9230 | return; |
9231 | } | |
256ab948 | 9232 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
252b5132 RH |
9233 | { |
9234 | /* 32 bit values require an lui. */ | |
df58fc94 | 9235 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9236 | if ((ep->X_add_number & 0xffff) != 0) |
67c0d1eb | 9237 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
252b5132 RH |
9238 | return; |
9239 | } | |
9240 | } | |
9241 | ||
9242 | /* The value is larger than 32 bits. */ | |
9243 | ||
bad1aba3 | 9244 | if (!dbl || GPR_SIZE == 32) |
252b5132 | 9245 | { |
55e08f71 NC |
9246 | char value[32]; |
9247 | ||
9248 | sprintf_vma (value, ep->X_add_number); | |
1661c76c | 9249 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
67c0d1eb | 9250 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
252b5132 RH |
9251 | return; |
9252 | } | |
9253 | ||
9254 | if (ep->X_op != O_big) | |
9255 | { | |
9256 | hi32 = *ep; | |
9257 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9258 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; | |
9259 | hi32.X_add_number &= 0xffffffff; | |
9260 | lo32 = *ep; | |
9261 | lo32.X_add_number &= 0xffffffff; | |
9262 | } | |
9263 | else | |
9264 | { | |
9c2799c2 | 9265 | gas_assert (ep->X_add_number > 2); |
252b5132 RH |
9266 | if (ep->X_add_number == 3) |
9267 | generic_bignum[3] = 0; | |
9268 | else if (ep->X_add_number > 4) | |
1661c76c | 9269 | as_bad (_("number larger than 64 bits")); |
252b5132 RH |
9270 | lo32.X_op = O_constant; |
9271 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); | |
9272 | hi32.X_op = O_constant; | |
9273 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); | |
9274 | } | |
9275 | ||
9276 | if (hi32.X_add_number == 0) | |
9277 | freg = 0; | |
9278 | else | |
9279 | { | |
9280 | int shift, bit; | |
9281 | unsigned long hi, lo; | |
9282 | ||
956cd1d6 | 9283 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
beae10d5 KH |
9284 | { |
9285 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) | |
9286 | { | |
67c0d1eb | 9287 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9288 | return; |
9289 | } | |
9290 | if (lo32.X_add_number & 0x80000000) | |
9291 | { | |
df58fc94 | 9292 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
252b5132 | 9293 | if (lo32.X_add_number & 0xffff) |
67c0d1eb | 9294 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
beae10d5 KH |
9295 | return; |
9296 | } | |
9297 | } | |
252b5132 RH |
9298 | |
9299 | /* Check for 16bit shifted constant. We know that hi32 is | |
9300 | non-zero, so start the mask on the first bit of the hi32 | |
9301 | value. */ | |
9302 | shift = 17; | |
9303 | do | |
beae10d5 KH |
9304 | { |
9305 | unsigned long himask, lomask; | |
9306 | ||
9307 | if (shift < 32) | |
9308 | { | |
9309 | himask = 0xffff >> (32 - shift); | |
9310 | lomask = (0xffff << shift) & 0xffffffff; | |
9311 | } | |
9312 | else | |
9313 | { | |
9314 | himask = 0xffff << (shift - 32); | |
9315 | lomask = 0; | |
9316 | } | |
9317 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 | |
9318 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) | |
9319 | { | |
9320 | expressionS tmp; | |
9321 | ||
9322 | tmp.X_op = O_constant; | |
9323 | if (shift < 32) | |
9324 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) | |
9325 | | (lo32.X_add_number >> shift)); | |
9326 | else | |
9327 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); | |
67c0d1eb | 9328 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
df58fc94 | 9329 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9330 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9331 | return; |
9332 | } | |
f9419b05 | 9333 | ++shift; |
beae10d5 KH |
9334 | } |
9335 | while (shift <= (64 - 16)); | |
252b5132 RH |
9336 | |
9337 | /* Find the bit number of the lowest one bit, and store the | |
9338 | shifted value in hi/lo. */ | |
9339 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); | |
9340 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); | |
9341 | if (lo != 0) | |
9342 | { | |
9343 | bit = 0; | |
9344 | while ((lo & 1) == 0) | |
9345 | { | |
9346 | lo >>= 1; | |
9347 | ++bit; | |
9348 | } | |
9349 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); | |
9350 | hi >>= bit; | |
9351 | } | |
9352 | else | |
9353 | { | |
9354 | bit = 32; | |
9355 | while ((hi & 1) == 0) | |
9356 | { | |
9357 | hi >>= 1; | |
9358 | ++bit; | |
9359 | } | |
9360 | lo = hi; | |
9361 | hi = 0; | |
9362 | } | |
9363 | ||
9364 | /* Optimize if the shifted value is a (power of 2) - 1. */ | |
9365 | if ((hi == 0 && ((lo + 1) & lo) == 0) | |
9366 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) | |
beae10d5 KH |
9367 | { |
9368 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); | |
252b5132 | 9369 | if (shift != 0) |
beae10d5 | 9370 | { |
252b5132 RH |
9371 | expressionS tmp; |
9372 | ||
9373 | /* This instruction will set the register to be all | |
9374 | ones. */ | |
beae10d5 KH |
9375 | tmp.X_op = O_constant; |
9376 | tmp.X_add_number = (offsetT) -1; | |
67c0d1eb | 9377 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
beae10d5 KH |
9378 | if (bit != 0) |
9379 | { | |
9380 | bit += shift; | |
df58fc94 | 9381 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
67c0d1eb | 9382 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
beae10d5 | 9383 | } |
df58fc94 | 9384 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
67c0d1eb | 9385 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
beae10d5 KH |
9386 | return; |
9387 | } | |
9388 | } | |
252b5132 RH |
9389 | |
9390 | /* Sign extend hi32 before calling load_register, because we can | |
9391 | generally get better code when we load a sign extended value. */ | |
9392 | if ((hi32.X_add_number & 0x80000000) != 0) | |
beae10d5 | 9393 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
67c0d1eb | 9394 | load_register (reg, &hi32, 0); |
252b5132 RH |
9395 | freg = reg; |
9396 | } | |
9397 | if ((lo32.X_add_number & 0xffff0000) == 0) | |
9398 | { | |
9399 | if (freg != 0) | |
9400 | { | |
df58fc94 | 9401 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
252b5132 RH |
9402 | freg = reg; |
9403 | } | |
9404 | } | |
9405 | else | |
9406 | { | |
9407 | expressionS mid16; | |
9408 | ||
956cd1d6 | 9409 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
beae10d5 | 9410 | { |
df58fc94 RS |
9411 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
9412 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); | |
beae10d5 KH |
9413 | return; |
9414 | } | |
252b5132 RH |
9415 | |
9416 | if (freg != 0) | |
9417 | { | |
df58fc94 | 9418 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
252b5132 RH |
9419 | freg = reg; |
9420 | } | |
9421 | mid16 = lo32; | |
9422 | mid16.X_add_number >>= 16; | |
67c0d1eb | 9423 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
df58fc94 | 9424 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
252b5132 RH |
9425 | freg = reg; |
9426 | } | |
9427 | if ((lo32.X_add_number & 0xffff) != 0) | |
67c0d1eb | 9428 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
252b5132 RH |
9429 | } |
9430 | ||
269137b2 TS |
9431 | static inline void |
9432 | load_delay_nop (void) | |
9433 | { | |
9434 | if (!gpr_interlocks) | |
9435 | macro_build (NULL, "nop", ""); | |
9436 | } | |
9437 | ||
252b5132 RH |
9438 | /* Load an address into a register. */ |
9439 | ||
9440 | static void | |
67c0d1eb | 9441 | load_address (int reg, expressionS *ep, int *used_at) |
252b5132 | 9442 | { |
252b5132 RH |
9443 | if (ep->X_op != O_constant |
9444 | && ep->X_op != O_symbol) | |
9445 | { | |
9446 | as_bad (_("expression too complex")); | |
9447 | ep->X_op = O_constant; | |
9448 | } | |
9449 | ||
9450 | if (ep->X_op == O_constant) | |
9451 | { | |
67c0d1eb | 9452 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
9453 | return; |
9454 | } | |
9455 | ||
9456 | if (mips_pic == NO_PIC) | |
9457 | { | |
9458 | /* If this is a reference to a GP relative symbol, we want | |
cdf6fd85 | 9459 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
9460 | Otherwise we want |
9461 | lui $reg,<sym> (BFD_RELOC_HI16_S) | |
9462 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
d6bc6245 | 9463 | If we have an addend, we always use the latter form. |
76b3015f | 9464 | |
d6bc6245 TS |
9465 | With 64bit address space and a usable $at we want |
9466 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9467 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
9468 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9469 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
9470 | dsll32 $reg,0 | |
3a482fd5 | 9471 | daddu $reg,$reg,$at |
76b3015f | 9472 | |
c03099e6 | 9473 | If $at is already in use, we use a path which is suboptimal |
d6bc6245 TS |
9474 | on superscalar processors. |
9475 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
9476 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
9477 | dsll $reg,16 | |
9478 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) | |
9479 | dsll $reg,16 | |
9480 | daddiu $reg,<sym> (BFD_RELOC_LO16) | |
6caf9ef4 TS |
9481 | |
9482 | For GP relative symbols in 64bit address space we can use | |
9483 | the same sequence as in 32bit address space. */ | |
aed1a261 | 9484 | if (HAVE_64BIT_SYMBOLS) |
d6bc6245 | 9485 | { |
6caf9ef4 TS |
9486 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
9487 | && !nopic_need_relax (ep->X_add_symbol, 1)) | |
9488 | { | |
9489 | relax_start (ep->X_add_symbol); | |
9490 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, | |
9491 | mips_gp_register, BFD_RELOC_GPREL16); | |
9492 | relax_switch (); | |
9493 | } | |
d6bc6245 | 9494 | |
741fe287 | 9495 | if (*used_at == 0 && mips_opts.at) |
d6bc6245 | 9496 | { |
df58fc94 RS |
9497 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
9498 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); | |
67c0d1eb RS |
9499 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9500 | BFD_RELOC_MIPS_HIGHER); | |
9501 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); | |
df58fc94 | 9502 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
67c0d1eb | 9503 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
d6bc6245 TS |
9504 | *used_at = 1; |
9505 | } | |
9506 | else | |
9507 | { | |
df58fc94 | 9508 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb RS |
9509 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
9510 | BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 9511 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9512 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
df58fc94 | 9513 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
67c0d1eb | 9514 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
d6bc6245 | 9515 | } |
6caf9ef4 TS |
9516 | |
9517 | if (mips_relax.sequence) | |
9518 | relax_end (); | |
d6bc6245 | 9519 | } |
252b5132 RH |
9520 | else |
9521 | { | |
d6bc6245 | 9522 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 9523 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
d6bc6245 | 9524 | { |
4d7206a2 | 9525 | relax_start (ep->X_add_symbol); |
67c0d1eb | 9526 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
17a2f251 | 9527 | mips_gp_register, BFD_RELOC_GPREL16); |
4d7206a2 | 9528 | relax_switch (); |
d6bc6245 | 9529 | } |
67c0d1eb RS |
9530 | macro_build_lui (ep, reg); |
9531 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", | |
9532 | reg, reg, BFD_RELOC_LO16); | |
4d7206a2 RS |
9533 | if (mips_relax.sequence) |
9534 | relax_end (); | |
d6bc6245 | 9535 | } |
252b5132 | 9536 | } |
0a44bf69 | 9537 | else if (!mips_big_got) |
252b5132 RH |
9538 | { |
9539 | expressionS ex; | |
9540 | ||
9541 | /* If this is a reference to an external symbol, we want | |
9542 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9543 | Otherwise we want | |
9544 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
9545 | nop | |
9546 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
f5040a92 AO |
9547 | If there is a constant, it must be added in after. |
9548 | ||
ed6fb7bd | 9549 | If we have NewABI, we want |
f5040a92 AO |
9550 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
9551 | unless we're referencing a global symbol with a non-zero | |
9552 | offset, in which case cst must be added separately. */ | |
ed6fb7bd SC |
9553 | if (HAVE_NEWABI) |
9554 | { | |
f5040a92 AO |
9555 | if (ep->X_add_number) |
9556 | { | |
4d7206a2 | 9557 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9558 | ep->X_add_number = 0; |
4d7206a2 | 9559 | relax_start (ep->X_add_symbol); |
67c0d1eb RS |
9560 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9561 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
9562 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9563 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9564 | ex.X_op = O_constant; | |
67c0d1eb | 9565 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9566 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9567 | ep->X_add_number = ex.X_add_number; |
4d7206a2 | 9568 | relax_switch (); |
f5040a92 | 9569 | } |
67c0d1eb | 9570 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9571 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
4d7206a2 RS |
9572 | if (mips_relax.sequence) |
9573 | relax_end (); | |
ed6fb7bd SC |
9574 | } |
9575 | else | |
9576 | { | |
f5040a92 AO |
9577 | ex.X_add_number = ep->X_add_number; |
9578 | ep->X_add_number = 0; | |
67c0d1eb RS |
9579 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
9580 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 9581 | load_delay_nop (); |
4d7206a2 RS |
9582 | relax_start (ep->X_add_symbol); |
9583 | relax_switch (); | |
67c0d1eb | 9584 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9585 | BFD_RELOC_LO16); |
4d7206a2 | 9586 | relax_end (); |
ed6fb7bd | 9587 | |
f5040a92 AO |
9588 | if (ex.X_add_number != 0) |
9589 | { | |
9590 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9591 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9592 | ex.X_op = O_constant; | |
67c0d1eb | 9593 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 9594 | reg, reg, BFD_RELOC_LO16); |
f5040a92 | 9595 | } |
252b5132 RH |
9596 | } |
9597 | } | |
0a44bf69 | 9598 | else if (mips_big_got) |
252b5132 RH |
9599 | { |
9600 | expressionS ex; | |
252b5132 RH |
9601 | |
9602 | /* This is the large GOT case. If this is a reference to an | |
9603 | external symbol, we want | |
9604 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
9605 | addu $reg,$reg,$gp | |
9606 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) | |
f5040a92 AO |
9607 | |
9608 | Otherwise, for a reference to a local symbol in old ABI, we want | |
252b5132 RH |
9609 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
9610 | nop | |
9611 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) | |
684022ea | 9612 | If there is a constant, it must be added in after. |
f5040a92 AO |
9613 | |
9614 | In the NewABI, for local symbols, with or without offsets, we want: | |
438c16b8 TS |
9615 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
9616 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
f5040a92 | 9617 | */ |
438c16b8 TS |
9618 | if (HAVE_NEWABI) |
9619 | { | |
4d7206a2 | 9620 | ex.X_add_number = ep->X_add_number; |
f5040a92 | 9621 | ep->X_add_number = 0; |
4d7206a2 | 9622 | relax_start (ep->X_add_symbol); |
df58fc94 | 9623 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9624 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9625 | reg, reg, mips_gp_register); | |
9626 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9627 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
f5040a92 AO |
9628 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
9629 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9630 | else if (ex.X_add_number) | |
9631 | { | |
9632 | ex.X_op = O_constant; | |
67c0d1eb RS |
9633 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9634 | BFD_RELOC_LO16); | |
f5040a92 AO |
9635 | } |
9636 | ||
9637 | ep->X_add_number = ex.X_add_number; | |
4d7206a2 | 9638 | relax_switch (); |
67c0d1eb | 9639 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9640 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
67c0d1eb RS |
9641 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9642 | BFD_RELOC_MIPS_GOT_OFST); | |
4d7206a2 | 9643 | relax_end (); |
438c16b8 | 9644 | } |
252b5132 | 9645 | else |
438c16b8 | 9646 | { |
f5040a92 AO |
9647 | ex.X_add_number = ep->X_add_number; |
9648 | ep->X_add_number = 0; | |
4d7206a2 | 9649 | relax_start (ep->X_add_symbol); |
df58fc94 | 9650 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
9651 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
9652 | reg, reg, mips_gp_register); | |
9653 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", | |
9654 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); | |
4d7206a2 RS |
9655 | relax_switch (); |
9656 | if (reg_needs_delay (mips_gp_register)) | |
438c16b8 TS |
9657 | { |
9658 | /* We need a nop before loading from $gp. This special | |
9659 | check is required because the lui which starts the main | |
9660 | instruction stream does not refer to $gp, and so will not | |
9661 | insert the nop which may be required. */ | |
67c0d1eb | 9662 | macro_build (NULL, "nop", ""); |
438c16b8 | 9663 | } |
67c0d1eb | 9664 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
17a2f251 | 9665 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
269137b2 | 9666 | load_delay_nop (); |
67c0d1eb | 9667 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
17a2f251 | 9668 | BFD_RELOC_LO16); |
4d7206a2 | 9669 | relax_end (); |
438c16b8 | 9670 | |
f5040a92 AO |
9671 | if (ex.X_add_number != 0) |
9672 | { | |
9673 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) | |
9674 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
9675 | ex.X_op = O_constant; | |
67c0d1eb RS |
9676 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
9677 | BFD_RELOC_LO16); | |
f5040a92 | 9678 | } |
252b5132 RH |
9679 | } |
9680 | } | |
252b5132 RH |
9681 | else |
9682 | abort (); | |
8fc2e39e | 9683 | |
741fe287 | 9684 | if (!mips_opts.at && *used_at == 1) |
1661c76c | 9685 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
9686 | } |
9687 | ||
ea1fb5dc RS |
9688 | /* Move the contents of register SOURCE into register DEST. */ |
9689 | ||
9690 | static void | |
67c0d1eb | 9691 | move_register (int dest, int source) |
ea1fb5dc | 9692 | { |
df58fc94 RS |
9693 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
9694 | instruction specifically requires a 32-bit one. */ | |
9695 | if (mips_opts.micromips | |
833794fc | 9696 | && !mips_opts.insn32 |
df58fc94 | 9697 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
7951ca42 | 9698 | macro_build (NULL, "move", "mp,mj", dest, source); |
df58fc94 | 9699 | else |
40fc1451 | 9700 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
ea1fb5dc RS |
9701 | } |
9702 | ||
4d7206a2 | 9703 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
f6a22291 MR |
9704 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
9705 | The two alternatives are: | |
4d7206a2 | 9706 | |
33eaf5de | 9707 | Global symbol Local symbol |
4d7206a2 RS |
9708 | ------------- ------------ |
9709 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) | |
9710 | ... ... | |
9711 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) | |
9712 | ||
9713 | load_got_offset emits the first instruction and add_got_offset | |
f6a22291 MR |
9714 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
9715 | a sequence to add a 32-bit offset using a scratch register. */ | |
4d7206a2 RS |
9716 | |
9717 | static void | |
67c0d1eb | 9718 | load_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9719 | { |
9720 | expressionS global; | |
9721 | ||
9722 | global = *local; | |
9723 | global.X_add_number = 0; | |
9724 | ||
9725 | relax_start (local->X_add_symbol); | |
67c0d1eb RS |
9726 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9727 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 | 9728 | relax_switch (); |
67c0d1eb RS |
9729 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
9730 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
4d7206a2 RS |
9731 | relax_end (); |
9732 | } | |
9733 | ||
9734 | static void | |
67c0d1eb | 9735 | add_got_offset (int dest, expressionS *local) |
4d7206a2 RS |
9736 | { |
9737 | expressionS global; | |
9738 | ||
9739 | global.X_op = O_constant; | |
9740 | global.X_op_symbol = NULL; | |
9741 | global.X_add_symbol = NULL; | |
9742 | global.X_add_number = local->X_add_number; | |
9743 | ||
9744 | relax_start (local->X_add_symbol); | |
67c0d1eb | 9745 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
4d7206a2 RS |
9746 | dest, dest, BFD_RELOC_LO16); |
9747 | relax_switch (); | |
67c0d1eb | 9748 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
4d7206a2 RS |
9749 | relax_end (); |
9750 | } | |
9751 | ||
f6a22291 MR |
9752 | static void |
9753 | add_got_offset_hilo (int dest, expressionS *local, int tmp) | |
9754 | { | |
9755 | expressionS global; | |
9756 | int hold_mips_optimize; | |
9757 | ||
9758 | global.X_op = O_constant; | |
9759 | global.X_op_symbol = NULL; | |
9760 | global.X_add_symbol = NULL; | |
9761 | global.X_add_number = local->X_add_number; | |
9762 | ||
9763 | relax_start (local->X_add_symbol); | |
9764 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); | |
9765 | relax_switch (); | |
9766 | /* Set mips_optimize around the lui instruction to avoid | |
9767 | inserting an unnecessary nop after the lw. */ | |
9768 | hold_mips_optimize = mips_optimize; | |
9769 | mips_optimize = 2; | |
9770 | macro_build_lui (&global, tmp); | |
9771 | mips_optimize = hold_mips_optimize; | |
9772 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); | |
9773 | relax_end (); | |
9774 | ||
9775 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); | |
9776 | } | |
9777 | ||
df58fc94 RS |
9778 | /* Emit a sequence of instructions to emulate a branch likely operation. |
9779 | BR is an ordinary branch corresponding to one to be emulated. BRNEG | |
9780 | is its complementing branch with the original condition negated. | |
9781 | CALL is set if the original branch specified the link operation. | |
9782 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. | |
9783 | ||
9784 | Code like this is produced in the noreorder mode: | |
9785 | ||
9786 | BRNEG <args>, 1f | |
9787 | nop | |
9788 | b <sym> | |
9789 | delay slot (executed only if branch taken) | |
9790 | 1: | |
9791 | ||
9792 | or, if CALL is set: | |
9793 | ||
9794 | BRNEG <args>, 1f | |
9795 | nop | |
9796 | bal <sym> | |
9797 | delay slot (executed only if branch taken) | |
9798 | 1: | |
9799 | ||
9800 | In the reorder mode the delay slot would be filled with a nop anyway, | |
9801 | so code produced is simply: | |
9802 | ||
9803 | BR <args>, <sym> | |
9804 | nop | |
9805 | ||
9806 | This function is used when producing code for the microMIPS ASE that | |
9807 | does not implement branch likely instructions in hardware. */ | |
9808 | ||
9809 | static void | |
9810 | macro_build_branch_likely (const char *br, const char *brneg, | |
9811 | int call, expressionS *ep, const char *fmt, | |
9812 | unsigned int sreg, unsigned int treg) | |
9813 | { | |
9814 | int noreorder = mips_opts.noreorder; | |
9815 | expressionS expr1; | |
9816 | ||
9817 | gas_assert (mips_opts.micromips); | |
9818 | start_noreorder (); | |
9819 | if (noreorder) | |
9820 | { | |
9821 | micromips_label_expr (&expr1); | |
9822 | macro_build (&expr1, brneg, fmt, sreg, treg); | |
9823 | macro_build (NULL, "nop", ""); | |
9824 | macro_build (ep, call ? "bal" : "b", "p"); | |
9825 | ||
9826 | /* Set to true so that append_insn adds a label. */ | |
9827 | emit_branch_likely_macro = TRUE; | |
9828 | } | |
9829 | else | |
9830 | { | |
9831 | macro_build (ep, br, fmt, sreg, treg); | |
9832 | macro_build (NULL, "nop", ""); | |
9833 | } | |
9834 | end_noreorder (); | |
9835 | } | |
9836 | ||
9837 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as | |
9838 | the condition code tested. EP specifies the branch target. */ | |
9839 | ||
9840 | static void | |
9841 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) | |
9842 | { | |
9843 | const int call = 0; | |
9844 | const char *brneg; | |
9845 | const char *br; | |
9846 | ||
9847 | switch (type) | |
9848 | { | |
9849 | case M_BC1FL: | |
9850 | br = "bc1f"; | |
9851 | brneg = "bc1t"; | |
9852 | break; | |
9853 | case M_BC1TL: | |
9854 | br = "bc1t"; | |
9855 | brneg = "bc1f"; | |
9856 | break; | |
9857 | case M_BC2FL: | |
9858 | br = "bc2f"; | |
9859 | brneg = "bc2t"; | |
9860 | break; | |
9861 | case M_BC2TL: | |
9862 | br = "bc2t"; | |
9863 | brneg = "bc2f"; | |
9864 | break; | |
9865 | default: | |
9866 | abort (); | |
9867 | } | |
9868 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); | |
9869 | } | |
9870 | ||
9871 | /* Emit a two-argument branch macro specified by TYPE, using SREG as | |
9872 | the register tested. EP specifies the branch target. */ | |
9873 | ||
9874 | static void | |
9875 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) | |
9876 | { | |
9877 | const char *brneg = NULL; | |
9878 | const char *br; | |
9879 | int call = 0; | |
9880 | ||
9881 | switch (type) | |
9882 | { | |
9883 | case M_BGEZ: | |
9884 | br = "bgez"; | |
9885 | break; | |
9886 | case M_BGEZL: | |
9887 | br = mips_opts.micromips ? "bgez" : "bgezl"; | |
9888 | brneg = "bltz"; | |
9889 | break; | |
9890 | case M_BGEZALL: | |
9891 | gas_assert (mips_opts.micromips); | |
833794fc | 9892 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
df58fc94 RS |
9893 | brneg = "bltz"; |
9894 | call = 1; | |
9895 | break; | |
9896 | case M_BGTZ: | |
9897 | br = "bgtz"; | |
9898 | break; | |
9899 | case M_BGTZL: | |
9900 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; | |
9901 | brneg = "blez"; | |
9902 | break; | |
9903 | case M_BLEZ: | |
9904 | br = "blez"; | |
9905 | break; | |
9906 | case M_BLEZL: | |
9907 | br = mips_opts.micromips ? "blez" : "blezl"; | |
9908 | brneg = "bgtz"; | |
9909 | break; | |
9910 | case M_BLTZ: | |
9911 | br = "bltz"; | |
9912 | break; | |
9913 | case M_BLTZL: | |
9914 | br = mips_opts.micromips ? "bltz" : "bltzl"; | |
9915 | brneg = "bgez"; | |
9916 | break; | |
9917 | case M_BLTZALL: | |
9918 | gas_assert (mips_opts.micromips); | |
833794fc | 9919 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
df58fc94 RS |
9920 | brneg = "bgez"; |
9921 | call = 1; | |
9922 | break; | |
9923 | default: | |
9924 | abort (); | |
9925 | } | |
9926 | if (mips_opts.micromips && brneg) | |
9927 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); | |
9928 | else | |
9929 | macro_build (ep, br, "s,p", sreg); | |
9930 | } | |
9931 | ||
9932 | /* Emit a three-argument branch macro specified by TYPE, using SREG and | |
9933 | TREG as the registers tested. EP specifies the branch target. */ | |
9934 | ||
9935 | static void | |
9936 | macro_build_branch_rsrt (int type, expressionS *ep, | |
9937 | unsigned int sreg, unsigned int treg) | |
9938 | { | |
9939 | const char *brneg = NULL; | |
9940 | const int call = 0; | |
9941 | const char *br; | |
9942 | ||
9943 | switch (type) | |
9944 | { | |
9945 | case M_BEQ: | |
9946 | case M_BEQ_I: | |
9947 | br = "beq"; | |
9948 | break; | |
9949 | case M_BEQL: | |
9950 | case M_BEQL_I: | |
9951 | br = mips_opts.micromips ? "beq" : "beql"; | |
9952 | brneg = "bne"; | |
9953 | break; | |
9954 | case M_BNE: | |
9955 | case M_BNE_I: | |
9956 | br = "bne"; | |
9957 | break; | |
9958 | case M_BNEL: | |
9959 | case M_BNEL_I: | |
9960 | br = mips_opts.micromips ? "bne" : "bnel"; | |
9961 | brneg = "beq"; | |
9962 | break; | |
9963 | default: | |
9964 | abort (); | |
9965 | } | |
9966 | if (mips_opts.micromips && brneg) | |
9967 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); | |
9968 | else | |
9969 | macro_build (ep, br, "s,t,p", sreg, treg); | |
9970 | } | |
9971 | ||
f2ae14a1 RS |
9972 | /* Return the high part that should be loaded in order to make the low |
9973 | part of VALUE accessible using an offset of OFFBITS bits. */ | |
9974 | ||
9975 | static offsetT | |
9976 | offset_high_part (offsetT value, unsigned int offbits) | |
9977 | { | |
9978 | offsetT bias; | |
9979 | addressT low_mask; | |
9980 | ||
9981 | if (offbits == 0) | |
9982 | return value; | |
9983 | bias = 1 << (offbits - 1); | |
9984 | low_mask = bias * 2 - 1; | |
9985 | return (value + bias) & ~low_mask; | |
9986 | } | |
9987 | ||
9988 | /* Return true if the value stored in offset_expr and offset_reloc | |
9989 | fits into a signed offset of OFFBITS bits. RANGE is the maximum | |
9990 | amount that the caller wants to add without inducing overflow | |
9991 | and ALIGN is the known alignment of the value in bytes. */ | |
9992 | ||
9993 | static bfd_boolean | |
9994 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) | |
9995 | { | |
9996 | if (offbits == 16) | |
9997 | { | |
9998 | /* Accept any relocation operator if overflow isn't a concern. */ | |
9999 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) | |
10000 | return TRUE; | |
10001 | ||
10002 | /* These relocations are guaranteed not to overflow in correct links. */ | |
10003 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL | |
10004 | || gprel16_reloc_p (*offset_reloc)) | |
10005 | return TRUE; | |
10006 | } | |
10007 | if (offset_expr.X_op == O_constant | |
10008 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 | |
10009 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) | |
10010 | return TRUE; | |
10011 | return FALSE; | |
10012 | } | |
10013 | ||
252b5132 RH |
10014 | /* |
10015 | * Build macros | |
10016 | * This routine implements the seemingly endless macro or synthesized | |
10017 | * instructions and addressing modes in the mips assembly language. Many | |
10018 | * of these macros are simple and are similar to each other. These could | |
67c1ffbe | 10019 | * probably be handled by some kind of table or grammar approach instead of |
252b5132 RH |
10020 | * this verbose method. Others are not simple macros but are more like |
10021 | * optimizing code generation. | |
10022 | * One interesting optimization is when several store macros appear | |
67c1ffbe | 10023 | * consecutively that would load AT with the upper half of the same address. |
2b0f3761 | 10024 | * The ensuing load upper instructions are omitted. This implies some kind |
252b5132 RH |
10025 | * of global optimization. We currently only optimize within a single macro. |
10026 | * For many of the load and store macros if the address is specified as a | |
10027 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we | |
10028 | * first load register 'at' with zero and use it as the base register. The | |
10029 | * mips assembler simply uses register $zero. Just one tiny optimization | |
10030 | * we're missing. | |
10031 | */ | |
10032 | static void | |
833794fc | 10033 | macro (struct mips_cl_insn *ip, char *str) |
252b5132 | 10034 | { |
c0ebe874 RS |
10035 | const struct mips_operand_array *operands; |
10036 | unsigned int breg, i; | |
741fe287 | 10037 | unsigned int tempreg; |
252b5132 | 10038 | int mask; |
43841e91 | 10039 | int used_at = 0; |
df58fc94 | 10040 | expressionS label_expr; |
252b5132 | 10041 | expressionS expr1; |
df58fc94 | 10042 | expressionS *ep; |
252b5132 RH |
10043 | const char *s; |
10044 | const char *s2; | |
10045 | const char *fmt; | |
10046 | int likely = 0; | |
252b5132 | 10047 | int coproc = 0; |
7f3c4072 | 10048 | int offbits = 16; |
1abe91b1 | 10049 | int call = 0; |
df58fc94 RS |
10050 | int jals = 0; |
10051 | int dbl = 0; | |
10052 | int imm = 0; | |
10053 | int ust = 0; | |
10054 | int lp = 0; | |
f2ae14a1 | 10055 | bfd_boolean large_offset; |
252b5132 | 10056 | int off; |
252b5132 | 10057 | int hold_mips_optimize; |
f2ae14a1 | 10058 | unsigned int align; |
c0ebe874 | 10059 | unsigned int op[MAX_OPERANDS]; |
252b5132 | 10060 | |
9c2799c2 | 10061 | gas_assert (! mips_opts.mips16); |
252b5132 | 10062 | |
c0ebe874 RS |
10063 | operands = insn_operands (ip); |
10064 | for (i = 0; i < MAX_OPERANDS; i++) | |
10065 | if (operands->operand[i]) | |
10066 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
10067 | else | |
10068 | op[i] = -1; | |
10069 | ||
252b5132 RH |
10070 | mask = ip->insn_mo->mask; |
10071 | ||
df58fc94 RS |
10072 | label_expr.X_op = O_constant; |
10073 | label_expr.X_op_symbol = NULL; | |
10074 | label_expr.X_add_symbol = NULL; | |
10075 | label_expr.X_add_number = 0; | |
10076 | ||
252b5132 RH |
10077 | expr1.X_op = O_constant; |
10078 | expr1.X_op_symbol = NULL; | |
10079 | expr1.X_add_symbol = NULL; | |
10080 | expr1.X_add_number = 1; | |
f2ae14a1 | 10081 | align = 1; |
252b5132 RH |
10082 | |
10083 | switch (mask) | |
10084 | { | |
10085 | case M_DABS: | |
10086 | dbl = 1; | |
1a0670f3 | 10087 | /* Fall through. */ |
252b5132 | 10088 | case M_ABS: |
df58fc94 RS |
10089 | /* bgez $a0,1f |
10090 | move v0,$a0 | |
10091 | sub v0,$zero,$a0 | |
10092 | 1: | |
10093 | */ | |
252b5132 | 10094 | |
7d10b47d | 10095 | start_noreorder (); |
252b5132 | 10096 | |
df58fc94 RS |
10097 | if (mips_opts.micromips) |
10098 | micromips_label_expr (&label_expr); | |
10099 | else | |
10100 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10101 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
10102 | if (op[0] == op[1]) | |
a605d2b3 | 10103 | macro_build (NULL, "nop", ""); |
252b5132 | 10104 | else |
c0ebe874 RS |
10105 | move_register (op[0], op[1]); |
10106 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); | |
df58fc94 RS |
10107 | if (mips_opts.micromips) |
10108 | micromips_add_label (); | |
252b5132 | 10109 | |
7d10b47d | 10110 | end_noreorder (); |
8fc2e39e | 10111 | break; |
252b5132 RH |
10112 | |
10113 | case M_ADD_I: | |
10114 | s = "addi"; | |
10115 | s2 = "add"; | |
10116 | goto do_addi; | |
10117 | case M_ADDU_I: | |
10118 | s = "addiu"; | |
10119 | s2 = "addu"; | |
10120 | goto do_addi; | |
10121 | case M_DADD_I: | |
10122 | dbl = 1; | |
10123 | s = "daddi"; | |
10124 | s2 = "dadd"; | |
df58fc94 RS |
10125 | if (!mips_opts.micromips) |
10126 | goto do_addi; | |
b0e6f033 | 10127 | if (imm_expr.X_add_number >= -0x200 |
df58fc94 RS |
10128 | && imm_expr.X_add_number < 0x200) |
10129 | { | |
b0e6f033 RS |
10130 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
10131 | (int) imm_expr.X_add_number); | |
df58fc94 RS |
10132 | break; |
10133 | } | |
10134 | goto do_addi_i; | |
252b5132 RH |
10135 | case M_DADDU_I: |
10136 | dbl = 1; | |
10137 | s = "daddiu"; | |
10138 | s2 = "daddu"; | |
10139 | do_addi: | |
b0e6f033 | 10140 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
10141 | && imm_expr.X_add_number < 0x8000) |
10142 | { | |
c0ebe874 | 10143 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 10144 | break; |
252b5132 | 10145 | } |
df58fc94 | 10146 | do_addi_i: |
8fc2e39e | 10147 | used_at = 1; |
67c0d1eb | 10148 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 10149 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10150 | break; |
10151 | ||
10152 | case M_AND_I: | |
10153 | s = "andi"; | |
10154 | s2 = "and"; | |
10155 | goto do_bit; | |
10156 | case M_OR_I: | |
10157 | s = "ori"; | |
10158 | s2 = "or"; | |
10159 | goto do_bit; | |
10160 | case M_NOR_I: | |
10161 | s = ""; | |
10162 | s2 = "nor"; | |
10163 | goto do_bit; | |
10164 | case M_XOR_I: | |
10165 | s = "xori"; | |
10166 | s2 = "xor"; | |
10167 | do_bit: | |
b0e6f033 | 10168 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
10169 | && imm_expr.X_add_number < 0x10000) |
10170 | { | |
10171 | if (mask != M_NOR_I) | |
c0ebe874 | 10172 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
252b5132 RH |
10173 | else |
10174 | { | |
67c0d1eb | 10175 | macro_build (&imm_expr, "ori", "t,r,i", |
c0ebe874 RS |
10176 | op[0], op[1], BFD_RELOC_LO16); |
10177 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); | |
252b5132 | 10178 | } |
8fc2e39e | 10179 | break; |
252b5132 RH |
10180 | } |
10181 | ||
8fc2e39e | 10182 | used_at = 1; |
bad1aba3 | 10183 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 10184 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
10185 | break; |
10186 | ||
8b082fb1 TS |
10187 | case M_BALIGN: |
10188 | switch (imm_expr.X_add_number) | |
10189 | { | |
10190 | case 0: | |
10191 | macro_build (NULL, "nop", ""); | |
10192 | break; | |
10193 | case 2: | |
c0ebe874 | 10194 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
8b082fb1 | 10195 | break; |
03f66e8a MR |
10196 | case 1: |
10197 | case 3: | |
c0ebe874 | 10198 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
90ecf173 | 10199 | (int) imm_expr.X_add_number); |
8b082fb1 | 10200 | break; |
03f66e8a MR |
10201 | default: |
10202 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), | |
10203 | (unsigned long) imm_expr.X_add_number); | |
10204 | break; | |
8b082fb1 TS |
10205 | } |
10206 | break; | |
10207 | ||
df58fc94 RS |
10208 | case M_BC1FL: |
10209 | case M_BC1TL: | |
10210 | case M_BC2FL: | |
10211 | case M_BC2TL: | |
10212 | gas_assert (mips_opts.micromips); | |
10213 | macro_build_branch_ccl (mask, &offset_expr, | |
10214 | EXTRACT_OPERAND (1, BCC, *ip)); | |
10215 | break; | |
10216 | ||
252b5132 | 10217 | case M_BEQ_I: |
252b5132 | 10218 | case M_BEQL_I: |
252b5132 | 10219 | case M_BNE_I: |
252b5132 | 10220 | case M_BNEL_I: |
b0e6f033 | 10221 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10222 | op[1] = 0; |
df58fc94 | 10223 | else |
252b5132 | 10224 | { |
c0ebe874 | 10225 | op[1] = AT; |
df58fc94 | 10226 | used_at = 1; |
bad1aba3 | 10227 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
252b5132 | 10228 | } |
df58fc94 RS |
10229 | /* Fall through. */ |
10230 | case M_BEQL: | |
10231 | case M_BNEL: | |
c0ebe874 | 10232 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
252b5132 RH |
10233 | break; |
10234 | ||
10235 | case M_BGEL: | |
10236 | likely = 1; | |
1a0670f3 | 10237 | /* Fall through. */ |
252b5132 | 10238 | case M_BGE: |
c0ebe874 RS |
10239 | if (op[1] == 0) |
10240 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); | |
10241 | else if (op[0] == 0) | |
10242 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); | |
df58fc94 | 10243 | else |
252b5132 | 10244 | { |
df58fc94 | 10245 | used_at = 1; |
c0ebe874 | 10246 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10247 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10248 | &offset_expr, AT, ZERO); | |
252b5132 | 10249 | } |
df58fc94 RS |
10250 | break; |
10251 | ||
10252 | case M_BGEZL: | |
10253 | case M_BGEZALL: | |
10254 | case M_BGTZL: | |
10255 | case M_BLEZL: | |
10256 | case M_BLTZL: | |
10257 | case M_BLTZALL: | |
c0ebe874 | 10258 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
252b5132 RH |
10259 | break; |
10260 | ||
10261 | case M_BGTL_I: | |
10262 | likely = 1; | |
1a0670f3 | 10263 | /* Fall through. */ |
252b5132 | 10264 | case M_BGT_I: |
90ecf173 | 10265 | /* Check for > max integer. */ |
b0e6f033 | 10266 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 RH |
10267 | { |
10268 | do_false: | |
90ecf173 | 10269 | /* Result is always false. */ |
252b5132 | 10270 | if (! likely) |
a605d2b3 | 10271 | macro_build (NULL, "nop", ""); |
252b5132 | 10272 | else |
df58fc94 | 10273 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
8fc2e39e | 10274 | break; |
252b5132 | 10275 | } |
f9419b05 | 10276 | ++imm_expr.X_add_number; |
252b5132 RH |
10277 | /* FALLTHROUGH */ |
10278 | case M_BGE_I: | |
10279 | case M_BGEL_I: | |
10280 | if (mask == M_BGEL_I) | |
10281 | likely = 1; | |
b0e6f033 | 10282 | if (imm_expr.X_add_number == 0) |
252b5132 | 10283 | { |
df58fc94 | 10284 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
c0ebe874 | 10285 | &offset_expr, op[0]); |
8fc2e39e | 10286 | break; |
252b5132 | 10287 | } |
b0e6f033 | 10288 | if (imm_expr.X_add_number == 1) |
252b5132 | 10289 | { |
df58fc94 | 10290 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
c0ebe874 | 10291 | &offset_expr, op[0]); |
8fc2e39e | 10292 | break; |
252b5132 | 10293 | } |
b0e6f033 | 10294 | if (imm_expr.X_add_number <= GPR_SMIN) |
252b5132 RH |
10295 | { |
10296 | do_true: | |
10297 | /* result is always true */ | |
1661c76c | 10298 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
67c0d1eb | 10299 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 10300 | break; |
252b5132 | 10301 | } |
8fc2e39e | 10302 | used_at = 1; |
c0ebe874 | 10303 | set_at (op[0], 0); |
df58fc94 RS |
10304 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10305 | &offset_expr, AT, ZERO); | |
252b5132 RH |
10306 | break; |
10307 | ||
10308 | case M_BGEUL: | |
10309 | likely = 1; | |
1a0670f3 | 10310 | /* Fall through. */ |
252b5132 | 10311 | case M_BGEU: |
c0ebe874 | 10312 | if (op[1] == 0) |
252b5132 | 10313 | goto do_true; |
c0ebe874 | 10314 | else if (op[0] == 0) |
df58fc94 | 10315 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10316 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10317 | else |
252b5132 | 10318 | { |
df58fc94 | 10319 | used_at = 1; |
c0ebe874 | 10320 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10321 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10322 | &offset_expr, AT, ZERO); | |
252b5132 | 10323 | } |
252b5132 RH |
10324 | break; |
10325 | ||
10326 | case M_BGTUL_I: | |
10327 | likely = 1; | |
1a0670f3 | 10328 | /* Fall through. */ |
252b5132 | 10329 | case M_BGTU_I: |
c0ebe874 | 10330 | if (op[0] == 0 |
bad1aba3 | 10331 | || (GPR_SIZE == 32 |
f01dc953 | 10332 | && imm_expr.X_add_number == -1)) |
252b5132 | 10333 | goto do_false; |
f9419b05 | 10334 | ++imm_expr.X_add_number; |
252b5132 RH |
10335 | /* FALLTHROUGH */ |
10336 | case M_BGEU_I: | |
10337 | case M_BGEUL_I: | |
10338 | if (mask == M_BGEUL_I) | |
10339 | likely = 1; | |
b0e6f033 | 10340 | if (imm_expr.X_add_number == 0) |
252b5132 | 10341 | goto do_true; |
b0e6f033 | 10342 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10343 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10344 | &offset_expr, op[0], ZERO); |
df58fc94 | 10345 | else |
252b5132 | 10346 | { |
df58fc94 | 10347 | used_at = 1; |
c0ebe874 | 10348 | set_at (op[0], 1); |
df58fc94 RS |
10349 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10350 | &offset_expr, AT, ZERO); | |
252b5132 | 10351 | } |
252b5132 RH |
10352 | break; |
10353 | ||
10354 | case M_BGTL: | |
10355 | likely = 1; | |
1a0670f3 | 10356 | /* Fall through. */ |
252b5132 | 10357 | case M_BGT: |
c0ebe874 RS |
10358 | if (op[1] == 0) |
10359 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); | |
10360 | else if (op[0] == 0) | |
10361 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); | |
df58fc94 | 10362 | else |
252b5132 | 10363 | { |
df58fc94 | 10364 | used_at = 1; |
c0ebe874 | 10365 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10366 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10367 | &offset_expr, AT, ZERO); | |
252b5132 | 10368 | } |
252b5132 RH |
10369 | break; |
10370 | ||
10371 | case M_BGTUL: | |
10372 | likely = 1; | |
1a0670f3 | 10373 | /* Fall through. */ |
252b5132 | 10374 | case M_BGTU: |
c0ebe874 | 10375 | if (op[1] == 0) |
df58fc94 | 10376 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 RS |
10377 | &offset_expr, op[0], ZERO); |
10378 | else if (op[0] == 0) | |
df58fc94 RS |
10379 | goto do_false; |
10380 | else | |
252b5132 | 10381 | { |
df58fc94 | 10382 | used_at = 1; |
c0ebe874 | 10383 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10384 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10385 | &offset_expr, AT, ZERO); | |
252b5132 | 10386 | } |
252b5132 RH |
10387 | break; |
10388 | ||
10389 | case M_BLEL: | |
10390 | likely = 1; | |
1a0670f3 | 10391 | /* Fall through. */ |
252b5132 | 10392 | case M_BLE: |
c0ebe874 RS |
10393 | if (op[1] == 0) |
10394 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); | |
10395 | else if (op[0] == 0) | |
10396 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); | |
df58fc94 | 10397 | else |
252b5132 | 10398 | { |
df58fc94 | 10399 | used_at = 1; |
c0ebe874 | 10400 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10401 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10402 | &offset_expr, AT, ZERO); | |
252b5132 | 10403 | } |
252b5132 RH |
10404 | break; |
10405 | ||
10406 | case M_BLEL_I: | |
10407 | likely = 1; | |
1a0670f3 | 10408 | /* Fall through. */ |
252b5132 | 10409 | case M_BLE_I: |
b0e6f033 | 10410 | if (imm_expr.X_add_number >= GPR_SMAX) |
252b5132 | 10411 | goto do_true; |
f9419b05 | 10412 | ++imm_expr.X_add_number; |
252b5132 RH |
10413 | /* FALLTHROUGH */ |
10414 | case M_BLT_I: | |
10415 | case M_BLTL_I: | |
10416 | if (mask == M_BLTL_I) | |
10417 | likely = 1; | |
b0e6f033 | 10418 | if (imm_expr.X_add_number == 0) |
c0ebe874 | 10419 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
b0e6f033 | 10420 | else if (imm_expr.X_add_number == 1) |
c0ebe874 | 10421 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
df58fc94 | 10422 | else |
252b5132 | 10423 | { |
df58fc94 | 10424 | used_at = 1; |
c0ebe874 | 10425 | set_at (op[0], 0); |
df58fc94 RS |
10426 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10427 | &offset_expr, AT, ZERO); | |
252b5132 | 10428 | } |
252b5132 RH |
10429 | break; |
10430 | ||
10431 | case M_BLEUL: | |
10432 | likely = 1; | |
1a0670f3 | 10433 | /* Fall through. */ |
252b5132 | 10434 | case M_BLEU: |
c0ebe874 | 10435 | if (op[1] == 0) |
df58fc94 | 10436 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 RS |
10437 | &offset_expr, op[0], ZERO); |
10438 | else if (op[0] == 0) | |
df58fc94 RS |
10439 | goto do_true; |
10440 | else | |
252b5132 | 10441 | { |
df58fc94 | 10442 | used_at = 1; |
c0ebe874 | 10443 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
df58fc94 RS |
10444 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
10445 | &offset_expr, AT, ZERO); | |
252b5132 | 10446 | } |
252b5132 RH |
10447 | break; |
10448 | ||
10449 | case M_BLEUL_I: | |
10450 | likely = 1; | |
1a0670f3 | 10451 | /* Fall through. */ |
252b5132 | 10452 | case M_BLEU_I: |
c0ebe874 | 10453 | if (op[0] == 0 |
bad1aba3 | 10454 | || (GPR_SIZE == 32 |
f01dc953 | 10455 | && imm_expr.X_add_number == -1)) |
252b5132 | 10456 | goto do_true; |
f9419b05 | 10457 | ++imm_expr.X_add_number; |
252b5132 RH |
10458 | /* FALLTHROUGH */ |
10459 | case M_BLTU_I: | |
10460 | case M_BLTUL_I: | |
10461 | if (mask == M_BLTUL_I) | |
10462 | likely = 1; | |
b0e6f033 | 10463 | if (imm_expr.X_add_number == 0) |
252b5132 | 10464 | goto do_false; |
b0e6f033 | 10465 | else if (imm_expr.X_add_number == 1) |
df58fc94 | 10466 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
c0ebe874 | 10467 | &offset_expr, op[0], ZERO); |
df58fc94 | 10468 | else |
252b5132 | 10469 | { |
df58fc94 | 10470 | used_at = 1; |
c0ebe874 | 10471 | set_at (op[0], 1); |
df58fc94 RS |
10472 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10473 | &offset_expr, AT, ZERO); | |
252b5132 | 10474 | } |
252b5132 RH |
10475 | break; |
10476 | ||
10477 | case M_BLTL: | |
10478 | likely = 1; | |
1a0670f3 | 10479 | /* Fall through. */ |
252b5132 | 10480 | case M_BLT: |
c0ebe874 RS |
10481 | if (op[1] == 0) |
10482 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); | |
10483 | else if (op[0] == 0) | |
10484 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); | |
df58fc94 | 10485 | else |
252b5132 | 10486 | { |
df58fc94 | 10487 | used_at = 1; |
c0ebe874 | 10488 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10489 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10490 | &offset_expr, AT, ZERO); | |
252b5132 | 10491 | } |
252b5132 RH |
10492 | break; |
10493 | ||
10494 | case M_BLTUL: | |
10495 | likely = 1; | |
1a0670f3 | 10496 | /* Fall through. */ |
252b5132 | 10497 | case M_BLTU: |
c0ebe874 | 10498 | if (op[1] == 0) |
252b5132 | 10499 | goto do_false; |
c0ebe874 | 10500 | else if (op[0] == 0) |
df58fc94 | 10501 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
c0ebe874 | 10502 | &offset_expr, ZERO, op[1]); |
df58fc94 | 10503 | else |
252b5132 | 10504 | { |
df58fc94 | 10505 | used_at = 1; |
c0ebe874 | 10506 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
df58fc94 RS |
10507 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
10508 | &offset_expr, AT, ZERO); | |
252b5132 | 10509 | } |
252b5132 RH |
10510 | break; |
10511 | ||
10512 | case M_DDIV_3: | |
10513 | dbl = 1; | |
1a0670f3 | 10514 | /* Fall through. */ |
252b5132 RH |
10515 | case M_DIV_3: |
10516 | s = "mflo"; | |
10517 | goto do_div3; | |
10518 | case M_DREM_3: | |
10519 | dbl = 1; | |
1a0670f3 | 10520 | /* Fall through. */ |
252b5132 RH |
10521 | case M_REM_3: |
10522 | s = "mfhi"; | |
10523 | do_div3: | |
c0ebe874 | 10524 | if (op[2] == 0) |
252b5132 | 10525 | { |
1661c76c | 10526 | as_warn (_("divide by zero")); |
252b5132 | 10527 | if (mips_trap) |
df58fc94 | 10528 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10529 | else |
df58fc94 | 10530 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10531 | break; |
252b5132 RH |
10532 | } |
10533 | ||
7d10b47d | 10534 | start_noreorder (); |
252b5132 RH |
10535 | if (mips_trap) |
10536 | { | |
c0ebe874 RS |
10537 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10538 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
252b5132 RH |
10539 | } |
10540 | else | |
10541 | { | |
df58fc94 RS |
10542 | if (mips_opts.micromips) |
10543 | micromips_label_expr (&label_expr); | |
10544 | else | |
10545 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10546 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10547 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); | |
df58fc94 RS |
10548 | macro_build (NULL, "break", BRK_FMT, 7); |
10549 | if (mips_opts.micromips) | |
10550 | micromips_add_label (); | |
252b5132 RH |
10551 | } |
10552 | expr1.X_add_number = -1; | |
8fc2e39e | 10553 | used_at = 1; |
f6a22291 | 10554 | load_register (AT, &expr1, dbl); |
df58fc94 RS |
10555 | if (mips_opts.micromips) |
10556 | micromips_label_expr (&label_expr); | |
10557 | else | |
10558 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); | |
c0ebe874 | 10559 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
252b5132 RH |
10560 | if (dbl) |
10561 | { | |
10562 | expr1.X_add_number = 1; | |
f6a22291 | 10563 | load_register (AT, &expr1, dbl); |
df58fc94 | 10564 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
252b5132 RH |
10565 | } |
10566 | else | |
10567 | { | |
10568 | expr1.X_add_number = 0x80000000; | |
df58fc94 | 10569 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
252b5132 RH |
10570 | } |
10571 | if (mips_trap) | |
10572 | { | |
c0ebe874 | 10573 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
252b5132 RH |
10574 | /* We want to close the noreorder block as soon as possible, so |
10575 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10576 | end_noreorder (); |
252b5132 RH |
10577 | } |
10578 | else | |
10579 | { | |
df58fc94 RS |
10580 | if (mips_opts.micromips) |
10581 | micromips_label_expr (&label_expr); | |
10582 | else | |
10583 | label_expr.X_add_number = 8; | |
c0ebe874 | 10584 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
a605d2b3 | 10585 | macro_build (NULL, "nop", ""); |
252b5132 RH |
10586 | |
10587 | /* We want to close the noreorder block as soon as possible, so | |
10588 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10589 | end_noreorder (); |
252b5132 | 10590 | |
df58fc94 | 10591 | macro_build (NULL, "break", BRK_FMT, 6); |
252b5132 | 10592 | } |
df58fc94 RS |
10593 | if (mips_opts.micromips) |
10594 | micromips_add_label (); | |
c0ebe874 | 10595 | macro_build (NULL, s, MFHL_FMT, op[0]); |
252b5132 RH |
10596 | break; |
10597 | ||
10598 | case M_DIV_3I: | |
10599 | s = "div"; | |
10600 | s2 = "mflo"; | |
10601 | goto do_divi; | |
10602 | case M_DIVU_3I: | |
10603 | s = "divu"; | |
10604 | s2 = "mflo"; | |
10605 | goto do_divi; | |
10606 | case M_REM_3I: | |
10607 | s = "div"; | |
10608 | s2 = "mfhi"; | |
10609 | goto do_divi; | |
10610 | case M_REMU_3I: | |
10611 | s = "divu"; | |
10612 | s2 = "mfhi"; | |
10613 | goto do_divi; | |
10614 | case M_DDIV_3I: | |
10615 | dbl = 1; | |
10616 | s = "ddiv"; | |
10617 | s2 = "mflo"; | |
10618 | goto do_divi; | |
10619 | case M_DDIVU_3I: | |
10620 | dbl = 1; | |
10621 | s = "ddivu"; | |
10622 | s2 = "mflo"; | |
10623 | goto do_divi; | |
10624 | case M_DREM_3I: | |
10625 | dbl = 1; | |
10626 | s = "ddiv"; | |
10627 | s2 = "mfhi"; | |
10628 | goto do_divi; | |
10629 | case M_DREMU_3I: | |
10630 | dbl = 1; | |
10631 | s = "ddivu"; | |
10632 | s2 = "mfhi"; | |
10633 | do_divi: | |
b0e6f033 | 10634 | if (imm_expr.X_add_number == 0) |
252b5132 | 10635 | { |
1661c76c | 10636 | as_warn (_("divide by zero")); |
252b5132 | 10637 | if (mips_trap) |
df58fc94 | 10638 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
252b5132 | 10639 | else |
df58fc94 | 10640 | macro_build (NULL, "break", BRK_FMT, 7); |
8fc2e39e | 10641 | break; |
252b5132 | 10642 | } |
b0e6f033 | 10643 | if (imm_expr.X_add_number == 1) |
252b5132 RH |
10644 | { |
10645 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10646 | move_register (op[0], op[1]); |
252b5132 | 10647 | else |
c0ebe874 | 10648 | move_register (op[0], ZERO); |
8fc2e39e | 10649 | break; |
252b5132 | 10650 | } |
b0e6f033 | 10651 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
252b5132 RH |
10652 | { |
10653 | if (strcmp (s2, "mflo") == 0) | |
c0ebe874 | 10654 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
252b5132 | 10655 | else |
c0ebe874 | 10656 | move_register (op[0], ZERO); |
8fc2e39e | 10657 | break; |
252b5132 RH |
10658 | } |
10659 | ||
8fc2e39e | 10660 | used_at = 1; |
67c0d1eb | 10661 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
10662 | macro_build (NULL, s, "z,s,t", op[1], AT); |
10663 | macro_build (NULL, s2, MFHL_FMT, op[0]); | |
252b5132 RH |
10664 | break; |
10665 | ||
10666 | case M_DIVU_3: | |
10667 | s = "divu"; | |
10668 | s2 = "mflo"; | |
10669 | goto do_divu3; | |
10670 | case M_REMU_3: | |
10671 | s = "divu"; | |
10672 | s2 = "mfhi"; | |
10673 | goto do_divu3; | |
10674 | case M_DDIVU_3: | |
10675 | s = "ddivu"; | |
10676 | s2 = "mflo"; | |
10677 | goto do_divu3; | |
10678 | case M_DREMU_3: | |
10679 | s = "ddivu"; | |
10680 | s2 = "mfhi"; | |
10681 | do_divu3: | |
7d10b47d | 10682 | start_noreorder (); |
252b5132 RH |
10683 | if (mips_trap) |
10684 | { | |
c0ebe874 RS |
10685 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
10686 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10687 | /* We want to close the noreorder block as soon as possible, so |
10688 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10689 | end_noreorder (); |
252b5132 RH |
10690 | } |
10691 | else | |
10692 | { | |
df58fc94 RS |
10693 | if (mips_opts.micromips) |
10694 | micromips_label_expr (&label_expr); | |
10695 | else | |
10696 | label_expr.X_add_number = 8; | |
c0ebe874 RS |
10697 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
10698 | macro_build (NULL, s, "z,s,t", op[1], op[2]); | |
252b5132 RH |
10699 | |
10700 | /* We want to close the noreorder block as soon as possible, so | |
10701 | that later insns are available for delay slot filling. */ | |
7d10b47d | 10702 | end_noreorder (); |
df58fc94 RS |
10703 | macro_build (NULL, "break", BRK_FMT, 7); |
10704 | if (mips_opts.micromips) | |
10705 | micromips_add_label (); | |
252b5132 | 10706 | } |
c0ebe874 | 10707 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
8fc2e39e | 10708 | break; |
252b5132 | 10709 | |
1abe91b1 MR |
10710 | case M_DLCA_AB: |
10711 | dbl = 1; | |
1a0670f3 | 10712 | /* Fall through. */ |
1abe91b1 MR |
10713 | case M_LCA_AB: |
10714 | call = 1; | |
10715 | goto do_la; | |
252b5132 RH |
10716 | case M_DLA_AB: |
10717 | dbl = 1; | |
1a0670f3 | 10718 | /* Fall through. */ |
252b5132 | 10719 | case M_LA_AB: |
1abe91b1 | 10720 | do_la: |
252b5132 RH |
10721 | /* Load the address of a symbol into a register. If breg is not |
10722 | zero, we then add a base register to it. */ | |
10723 | ||
c0ebe874 | 10724 | breg = op[2]; |
bad1aba3 | 10725 | if (dbl && GPR_SIZE == 32) |
ece794d9 MF |
10726 | as_warn (_("dla used to load 32-bit register; recommend using la " |
10727 | "instead")); | |
3bec30a8 | 10728 | |
90ecf173 | 10729 | if (!dbl && HAVE_64BIT_OBJECTS) |
ece794d9 MF |
10730 | as_warn (_("la used to load 64-bit address; recommend using dla " |
10731 | "instead")); | |
3bec30a8 | 10732 | |
f2ae14a1 | 10733 | if (small_offset_p (0, align, 16)) |
0c11417f | 10734 | { |
c0ebe874 | 10735 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
f2ae14a1 | 10736 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
8fc2e39e | 10737 | break; |
0c11417f MR |
10738 | } |
10739 | ||
c0ebe874 | 10740 | if (mips_opts.at && (op[0] == breg)) |
afdbd6d0 CD |
10741 | { |
10742 | tempreg = AT; | |
10743 | used_at = 1; | |
10744 | } | |
10745 | else | |
c0ebe874 | 10746 | tempreg = op[0]; |
afdbd6d0 | 10747 | |
252b5132 RH |
10748 | if (offset_expr.X_op != O_symbol |
10749 | && offset_expr.X_op != O_constant) | |
10750 | { | |
1661c76c | 10751 | as_bad (_("expression too complex")); |
252b5132 RH |
10752 | offset_expr.X_op = O_constant; |
10753 | } | |
10754 | ||
252b5132 | 10755 | if (offset_expr.X_op == O_constant) |
aed1a261 | 10756 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
252b5132 RH |
10757 | else if (mips_pic == NO_PIC) |
10758 | { | |
d6bc6245 | 10759 | /* If this is a reference to a GP relative symbol, we want |
cdf6fd85 | 10760 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
252b5132 RH |
10761 | Otherwise we want |
10762 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10763 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10764 | If we have a constant, we need two instructions anyhow, | |
d6bc6245 | 10765 | so we may as well always use the latter form. |
76b3015f | 10766 | |
6caf9ef4 TS |
10767 | With 64bit address space and a usable $at we want |
10768 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10769 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
10770 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10771 | daddiu $at,<sym> (BFD_RELOC_LO16) | |
10772 | dsll32 $tempreg,0 | |
10773 | daddu $tempreg,$tempreg,$at | |
10774 | ||
10775 | If $at is already in use, we use a path which is suboptimal | |
10776 | on superscalar processors. | |
10777 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
10778 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
10779 | dsll $tempreg,16 | |
10780 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
10781 | dsll $tempreg,16 | |
10782 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) | |
10783 | ||
10784 | For GP relative symbols in 64bit address space we can use | |
10785 | the same sequence as in 32bit address space. */ | |
aed1a261 | 10786 | if (HAVE_64BIT_SYMBOLS) |
252b5132 | 10787 | { |
6caf9ef4 TS |
10788 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
10789 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) | |
10790 | { | |
10791 | relax_start (offset_expr.X_add_symbol); | |
10792 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10793 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
10794 | relax_switch (); | |
10795 | } | |
d6bc6245 | 10796 | |
741fe287 | 10797 | if (used_at == 0 && mips_opts.at) |
98d3f06f | 10798 | { |
df58fc94 | 10799 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10800 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 10801 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10802 | AT, BFD_RELOC_HI16_S); |
67c0d1eb | 10803 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10804 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
67c0d1eb | 10805 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10806 | AT, AT, BFD_RELOC_LO16); |
df58fc94 | 10807 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 10808 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
98d3f06f KH |
10809 | used_at = 1; |
10810 | } | |
10811 | else | |
10812 | { | |
df58fc94 | 10813 | macro_build (&offset_expr, "lui", LUI_FMT, |
17a2f251 | 10814 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
67c0d1eb | 10815 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10816 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
df58fc94 | 10817 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10818 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10819 | tempreg, tempreg, BFD_RELOC_HI16_S); |
df58fc94 | 10820 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb | 10821 | macro_build (&offset_expr, "daddiu", "t,r,j", |
17a2f251 | 10822 | tempreg, tempreg, BFD_RELOC_LO16); |
98d3f06f | 10823 | } |
6caf9ef4 TS |
10824 | |
10825 | if (mips_relax.sequence) | |
10826 | relax_end (); | |
98d3f06f KH |
10827 | } |
10828 | else | |
10829 | { | |
10830 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 10831 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
98d3f06f | 10832 | { |
4d7206a2 | 10833 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10834 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10835 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); | |
4d7206a2 | 10836 | relax_switch (); |
98d3f06f | 10837 | } |
6943caf0 | 10838 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
1661c76c | 10839 | as_bad (_("offset too large")); |
67c0d1eb RS |
10840 | macro_build_lui (&offset_expr, tempreg); |
10841 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
10842 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
10843 | if (mips_relax.sequence) |
10844 | relax_end (); | |
98d3f06f | 10845 | } |
252b5132 | 10846 | } |
0a44bf69 | 10847 | else if (!mips_big_got && !HAVE_NEWABI) |
252b5132 | 10848 | { |
9117d219 NC |
10849 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
10850 | ||
252b5132 RH |
10851 | /* If this is a reference to an external symbol, and there |
10852 | is no constant, we want | |
10853 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
1abe91b1 | 10854 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 | 10855 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
252b5132 RH |
10856 | For a local symbol, we want |
10857 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10858 | nop | |
10859 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
10860 | ||
10861 | If we have a small constant, and this is a reference to | |
10862 | an external symbol, we want | |
10863 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10864 | nop | |
10865 | addiu $tempreg,$tempreg,<constant> | |
10866 | For a local symbol, we want the same instruction | |
10867 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
10868 | addiu instruction. | |
10869 | ||
10870 | If we have a large constant, and this is a reference to | |
10871 | an external symbol, we want | |
10872 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
10873 | lui $at,<hiconstant> | |
10874 | addiu $at,$at,<loconstant> | |
10875 | addu $tempreg,$tempreg,$at | |
10876 | For a local symbol, we want the same instruction | |
10877 | sequence, but we output a BFD_RELOC_LO16 reloc on the | |
ed6fb7bd | 10878 | addiu instruction. |
ed6fb7bd SC |
10879 | */ |
10880 | ||
4d7206a2 | 10881 | if (offset_expr.X_add_number == 0) |
252b5132 | 10882 | { |
0a44bf69 RS |
10883 | if (mips_pic == SVR4_PIC |
10884 | && breg == 0 | |
10885 | && (call || tempreg == PIC_CALL_REG)) | |
4d7206a2 RS |
10886 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
10887 | ||
10888 | relax_start (offset_expr.X_add_symbol); | |
67c0d1eb RS |
10889 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10890 | lw_reloc_type, mips_gp_register); | |
4d7206a2 | 10891 | if (breg != 0) |
252b5132 RH |
10892 | { |
10893 | /* We're going to put in an addu instruction using | |
10894 | tempreg, so we may as well insert the nop right | |
10895 | now. */ | |
269137b2 | 10896 | load_delay_nop (); |
252b5132 | 10897 | } |
4d7206a2 | 10898 | relax_switch (); |
67c0d1eb RS |
10899 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
10900 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 10901 | load_delay_nop (); |
67c0d1eb RS |
10902 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
10903 | tempreg, tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 10904 | relax_end (); |
252b5132 RH |
10905 | /* FIXME: If breg == 0, and the next instruction uses |
10906 | $tempreg, then if this variant case is used an extra | |
10907 | nop will be generated. */ | |
10908 | } | |
4d7206a2 RS |
10909 | else if (offset_expr.X_add_number >= -0x8000 |
10910 | && offset_expr.X_add_number < 0x8000) | |
252b5132 | 10911 | { |
67c0d1eb | 10912 | load_got_offset (tempreg, &offset_expr); |
269137b2 | 10913 | load_delay_nop (); |
67c0d1eb | 10914 | add_got_offset (tempreg, &offset_expr); |
252b5132 RH |
10915 | } |
10916 | else | |
10917 | { | |
4d7206a2 RS |
10918 | expr1.X_add_number = offset_expr.X_add_number; |
10919 | offset_expr.X_add_number = | |
43c0598f | 10920 | SEXT_16BIT (offset_expr.X_add_number); |
67c0d1eb | 10921 | load_got_offset (tempreg, &offset_expr); |
f6a22291 | 10922 | offset_expr.X_add_number = expr1.X_add_number; |
252b5132 RH |
10923 | /* If we are going to add in a base register, and the |
10924 | target register and the base register are the same, | |
10925 | then we are using AT as a temporary register. Since | |
10926 | we want to load the constant into AT, we add our | |
10927 | current AT (from the global offset table) and the | |
10928 | register into the register now, and pretend we were | |
10929 | not using a base register. */ | |
c0ebe874 | 10930 | if (breg == op[0]) |
252b5132 | 10931 | { |
269137b2 | 10932 | load_delay_nop (); |
67c0d1eb | 10933 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 10934 | op[0], AT, breg); |
252b5132 | 10935 | breg = 0; |
c0ebe874 | 10936 | tempreg = op[0]; |
252b5132 | 10937 | } |
f6a22291 | 10938 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
252b5132 RH |
10939 | used_at = 1; |
10940 | } | |
10941 | } | |
0a44bf69 | 10942 | else if (!mips_big_got && HAVE_NEWABI) |
f5040a92 | 10943 | { |
67c0d1eb | 10944 | int add_breg_early = 0; |
f5040a92 AO |
10945 | |
10946 | /* If this is a reference to an external, and there is no | |
10947 | constant, or local symbol (*), with or without a | |
10948 | constant, we want | |
10949 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
1abe91b1 | 10950 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
10951 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
10952 | ||
10953 | If we have a small constant, and this is a reference to | |
10954 | an external symbol, we want | |
10955 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10956 | addiu $tempreg,$tempreg,<constant> | |
10957 | ||
10958 | If we have a large constant, and this is a reference to | |
10959 | an external symbol, we want | |
10960 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) | |
10961 | lui $at,<hiconstant> | |
10962 | addiu $at,$at,<loconstant> | |
10963 | addu $tempreg,$tempreg,$at | |
10964 | ||
10965 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for | |
10966 | local symbols, even though it introduces an additional | |
10967 | instruction. */ | |
10968 | ||
f5040a92 AO |
10969 | if (offset_expr.X_add_number) |
10970 | { | |
4d7206a2 | 10971 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
10972 | offset_expr.X_add_number = 0; |
10973 | ||
4d7206a2 | 10974 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
10975 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
10976 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
10977 | |
10978 | if (expr1.X_add_number >= -0x8000 | |
10979 | && expr1.X_add_number < 0x8000) | |
10980 | { | |
67c0d1eb RS |
10981 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
10982 | tempreg, tempreg, BFD_RELOC_LO16); | |
f5040a92 | 10983 | } |
ecd13cd3 | 10984 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 10985 | { |
c0ebe874 RS |
10986 | unsigned int dreg; |
10987 | ||
f5040a92 AO |
10988 | /* If we are going to add in a base register, and the |
10989 | target register and the base register are the same, | |
10990 | then we are using AT as a temporary register. Since | |
10991 | we want to load the constant into AT, we add our | |
10992 | current AT (from the global offset table) and the | |
10993 | register into the register now, and pretend we were | |
10994 | not using a base register. */ | |
c0ebe874 | 10995 | if (breg != op[0]) |
f5040a92 AO |
10996 | dreg = tempreg; |
10997 | else | |
10998 | { | |
9c2799c2 | 10999 | gas_assert (tempreg == AT); |
67c0d1eb | 11000 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11001 | op[0], AT, breg); |
11002 | dreg = op[0]; | |
67c0d1eb | 11003 | add_breg_early = 1; |
f5040a92 AO |
11004 | } |
11005 | ||
f6a22291 | 11006 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11007 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11008 | dreg, dreg, AT); |
f5040a92 | 11009 | |
f5040a92 AO |
11010 | used_at = 1; |
11011 | } | |
11012 | else | |
11013 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11014 | ||
4d7206a2 | 11015 | relax_switch (); |
f5040a92 AO |
11016 | offset_expr.X_add_number = expr1.X_add_number; |
11017 | ||
67c0d1eb RS |
11018 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11019 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
11020 | if (add_breg_early) | |
f5040a92 | 11021 | { |
67c0d1eb | 11022 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11023 | op[0], tempreg, breg); |
f5040a92 | 11024 | breg = 0; |
c0ebe874 | 11025 | tempreg = op[0]; |
f5040a92 | 11026 | } |
4d7206a2 | 11027 | relax_end (); |
f5040a92 | 11028 | } |
4d7206a2 | 11029 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
f5040a92 | 11030 | { |
4d7206a2 | 11031 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11032 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11033 | BFD_RELOC_MIPS_CALL16, mips_gp_register); | |
4d7206a2 | 11034 | relax_switch (); |
67c0d1eb RS |
11035 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11036 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
4d7206a2 | 11037 | relax_end (); |
f5040a92 | 11038 | } |
4d7206a2 | 11039 | else |
f5040a92 | 11040 | { |
67c0d1eb RS |
11041 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11042 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); | |
f5040a92 AO |
11043 | } |
11044 | } | |
0a44bf69 | 11045 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 11046 | { |
67c0d1eb | 11047 | int gpdelay; |
9117d219 NC |
11048 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11049 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
ed6fb7bd | 11050 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
252b5132 RH |
11051 | |
11052 | /* This is the large GOT case. If this is a reference to an | |
11053 | external symbol, and there is no constant, we want | |
11054 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11055 | addu $tempreg,$tempreg,$gp | |
11056 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11057 | or for lca or if tempreg is PIC_CALL_REG |
9117d219 NC |
11058 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11059 | addu $tempreg,$tempreg,$gp | |
11060 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
252b5132 RH |
11061 | For a local symbol, we want |
11062 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11063 | nop | |
11064 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
11065 | ||
11066 | If we have a small constant, and this is a reference to | |
11067 | an external symbol, we want | |
11068 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11069 | addu $tempreg,$tempreg,$gp | |
11070 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11071 | nop | |
11072 | addiu $tempreg,$tempreg,<constant> | |
11073 | For a local symbol, we want | |
11074 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11075 | nop | |
11076 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) | |
11077 | ||
11078 | If we have a large constant, and this is a reference to | |
11079 | an external symbol, we want | |
11080 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11081 | addu $tempreg,$tempreg,$gp | |
11082 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11083 | lui $at,<hiconstant> | |
11084 | addiu $at,$at,<loconstant> | |
11085 | addu $tempreg,$tempreg,$at | |
11086 | For a local symbol, we want | |
11087 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11088 | lui $at,<hiconstant> | |
11089 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) | |
11090 | addu $tempreg,$tempreg,$at | |
f5040a92 | 11091 | */ |
438c16b8 | 11092 | |
252b5132 RH |
11093 | expr1.X_add_number = offset_expr.X_add_number; |
11094 | offset_expr.X_add_number = 0; | |
4d7206a2 | 11095 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 11096 | gpdelay = reg_needs_delay (mips_gp_register); |
1abe91b1 MR |
11097 | if (expr1.X_add_number == 0 && breg == 0 |
11098 | && (call || tempreg == PIC_CALL_REG)) | |
9117d219 NC |
11099 | { |
11100 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11101 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11102 | } | |
df58fc94 | 11103 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11104 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11105 | tempreg, tempreg, mips_gp_register); |
67c0d1eb | 11106 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 11107 | tempreg, lw_reloc_type, tempreg); |
252b5132 RH |
11108 | if (expr1.X_add_number == 0) |
11109 | { | |
67c0d1eb | 11110 | if (breg != 0) |
252b5132 RH |
11111 | { |
11112 | /* We're going to put in an addu instruction using | |
11113 | tempreg, so we may as well insert the nop right | |
11114 | now. */ | |
269137b2 | 11115 | load_delay_nop (); |
252b5132 | 11116 | } |
252b5132 RH |
11117 | } |
11118 | else if (expr1.X_add_number >= -0x8000 | |
11119 | && expr1.X_add_number < 0x8000) | |
11120 | { | |
269137b2 | 11121 | load_delay_nop (); |
67c0d1eb | 11122 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11123 | tempreg, tempreg, BFD_RELOC_LO16); |
252b5132 RH |
11124 | } |
11125 | else | |
11126 | { | |
c0ebe874 RS |
11127 | unsigned int dreg; |
11128 | ||
252b5132 RH |
11129 | /* If we are going to add in a base register, and the |
11130 | target register and the base register are the same, | |
11131 | then we are using AT as a temporary register. Since | |
11132 | we want to load the constant into AT, we add our | |
11133 | current AT (from the global offset table) and the | |
11134 | register into the register now, and pretend we were | |
11135 | not using a base register. */ | |
c0ebe874 | 11136 | if (breg != op[0]) |
67c0d1eb | 11137 | dreg = tempreg; |
252b5132 RH |
11138 | else |
11139 | { | |
9c2799c2 | 11140 | gas_assert (tempreg == AT); |
269137b2 | 11141 | load_delay_nop (); |
67c0d1eb | 11142 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11143 | op[0], AT, breg); |
11144 | dreg = op[0]; | |
252b5132 RH |
11145 | } |
11146 | ||
f6a22291 | 11147 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11148 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
252b5132 | 11149 | |
252b5132 RH |
11150 | used_at = 1; |
11151 | } | |
43c0598f | 11152 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
4d7206a2 | 11153 | relax_switch (); |
252b5132 | 11154 | |
67c0d1eb | 11155 | if (gpdelay) |
252b5132 RH |
11156 | { |
11157 | /* This is needed because this instruction uses $gp, but | |
f5040a92 | 11158 | the first instruction on the main stream does not. */ |
67c0d1eb | 11159 | macro_build (NULL, "nop", ""); |
252b5132 | 11160 | } |
ed6fb7bd | 11161 | |
67c0d1eb RS |
11162 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11163 | local_reloc_type, mips_gp_register); | |
f5040a92 | 11164 | if (expr1.X_add_number >= -0x8000 |
252b5132 RH |
11165 | && expr1.X_add_number < 0x8000) |
11166 | { | |
269137b2 | 11167 | load_delay_nop (); |
67c0d1eb RS |
11168 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11169 | tempreg, tempreg, BFD_RELOC_LO16); | |
252b5132 | 11170 | /* FIXME: If add_number is 0, and there was no base |
f5040a92 AO |
11171 | register, the external symbol case ended with a load, |
11172 | so if the symbol turns out to not be external, and | |
11173 | the next instruction uses tempreg, an unnecessary nop | |
11174 | will be inserted. */ | |
252b5132 RH |
11175 | } |
11176 | else | |
11177 | { | |
c0ebe874 | 11178 | if (breg == op[0]) |
252b5132 RH |
11179 | { |
11180 | /* We must add in the base register now, as in the | |
f5040a92 | 11181 | external symbol case. */ |
9c2799c2 | 11182 | gas_assert (tempreg == AT); |
269137b2 | 11183 | load_delay_nop (); |
67c0d1eb | 11184 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11185 | op[0], AT, breg); |
11186 | tempreg = op[0]; | |
252b5132 | 11187 | /* We set breg to 0 because we have arranged to add |
f5040a92 | 11188 | it in in both cases. */ |
252b5132 RH |
11189 | breg = 0; |
11190 | } | |
11191 | ||
67c0d1eb RS |
11192 | macro_build_lui (&expr1, AT); |
11193 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
17a2f251 | 11194 | AT, AT, BFD_RELOC_LO16); |
67c0d1eb | 11195 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11196 | tempreg, tempreg, AT); |
8fc2e39e | 11197 | used_at = 1; |
252b5132 | 11198 | } |
4d7206a2 | 11199 | relax_end (); |
252b5132 | 11200 | } |
0a44bf69 | 11201 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 11202 | { |
f5040a92 AO |
11203 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
11204 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; | |
67c0d1eb | 11205 | int add_breg_early = 0; |
f5040a92 AO |
11206 | |
11207 | /* This is the large GOT case. If this is a reference to an | |
11208 | external symbol, and there is no constant, we want | |
11209 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11210 | add $tempreg,$tempreg,$gp | |
11211 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
1abe91b1 | 11212 | or for lca or if tempreg is PIC_CALL_REG |
f5040a92 AO |
11213 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
11214 | add $tempreg,$tempreg,$gp | |
11215 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) | |
11216 | ||
11217 | If we have a small constant, and this is a reference to | |
11218 | an external symbol, we want | |
11219 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11220 | add $tempreg,$tempreg,$gp | |
11221 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11222 | addi $tempreg,$tempreg,<constant> | |
11223 | ||
11224 | If we have a large constant, and this is a reference to | |
11225 | an external symbol, we want | |
11226 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
11227 | addu $tempreg,$tempreg,$gp | |
11228 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
11229 | lui $at,<hiconstant> | |
11230 | addi $at,$at,<loconstant> | |
11231 | add $tempreg,$tempreg,$at | |
11232 | ||
11233 | If we have NewABI, and we know it's a local symbol, we want | |
11234 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
11235 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) | |
11236 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ | |
11237 | ||
4d7206a2 | 11238 | relax_start (offset_expr.X_add_symbol); |
f5040a92 | 11239 | |
4d7206a2 | 11240 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
11241 | offset_expr.X_add_number = 0; |
11242 | ||
1abe91b1 MR |
11243 | if (expr1.X_add_number == 0 && breg == 0 |
11244 | && (call || tempreg == PIC_CALL_REG)) | |
f5040a92 AO |
11245 | { |
11246 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; | |
11247 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; | |
11248 | } | |
df58fc94 | 11249 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
67c0d1eb | 11250 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 11251 | tempreg, tempreg, mips_gp_register); |
67c0d1eb RS |
11252 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11253 | tempreg, lw_reloc_type, tempreg); | |
f5040a92 AO |
11254 | |
11255 | if (expr1.X_add_number == 0) | |
4d7206a2 | 11256 | ; |
f5040a92 AO |
11257 | else if (expr1.X_add_number >= -0x8000 |
11258 | && expr1.X_add_number < 0x8000) | |
11259 | { | |
67c0d1eb | 11260 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
17a2f251 | 11261 | tempreg, tempreg, BFD_RELOC_LO16); |
f5040a92 | 11262 | } |
ecd13cd3 | 11263 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
f5040a92 | 11264 | { |
c0ebe874 RS |
11265 | unsigned int dreg; |
11266 | ||
f5040a92 AO |
11267 | /* If we are going to add in a base register, and the |
11268 | target register and the base register are the same, | |
11269 | then we are using AT as a temporary register. Since | |
11270 | we want to load the constant into AT, we add our | |
11271 | current AT (from the global offset table) and the | |
11272 | register into the register now, and pretend we were | |
11273 | not using a base register. */ | |
c0ebe874 | 11274 | if (breg != op[0]) |
f5040a92 AO |
11275 | dreg = tempreg; |
11276 | else | |
11277 | { | |
9c2799c2 | 11278 | gas_assert (tempreg == AT); |
67c0d1eb | 11279 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 RS |
11280 | op[0], AT, breg); |
11281 | dreg = op[0]; | |
67c0d1eb | 11282 | add_breg_early = 1; |
f5040a92 AO |
11283 | } |
11284 | ||
f6a22291 | 11285 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
67c0d1eb | 11286 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
f5040a92 | 11287 | |
f5040a92 AO |
11288 | used_at = 1; |
11289 | } | |
11290 | else | |
11291 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); | |
11292 | ||
4d7206a2 | 11293 | relax_switch (); |
f5040a92 | 11294 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
11295 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
11296 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
11297 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, | |
11298 | tempreg, BFD_RELOC_MIPS_GOT_OFST); | |
11299 | if (add_breg_early) | |
f5040a92 | 11300 | { |
67c0d1eb | 11301 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
c0ebe874 | 11302 | op[0], tempreg, breg); |
f5040a92 | 11303 | breg = 0; |
c0ebe874 | 11304 | tempreg = op[0]; |
f5040a92 | 11305 | } |
4d7206a2 | 11306 | relax_end (); |
f5040a92 | 11307 | } |
252b5132 RH |
11308 | else |
11309 | abort (); | |
11310 | ||
11311 | if (breg != 0) | |
c0ebe874 | 11312 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
252b5132 RH |
11313 | break; |
11314 | ||
52b6b6b9 | 11315 | case M_MSGSND: |
df58fc94 | 11316 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11317 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
c7af4273 | 11318 | break; |
52b6b6b9 JM |
11319 | |
11320 | case M_MSGLD: | |
df58fc94 | 11321 | gas_assert (!mips_opts.micromips); |
c8276761 | 11322 | macro_build (NULL, "c2", "C", 0x02); |
c7af4273 | 11323 | break; |
52b6b6b9 JM |
11324 | |
11325 | case M_MSGLD_T: | |
df58fc94 | 11326 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11327 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
c7af4273 | 11328 | break; |
52b6b6b9 JM |
11329 | |
11330 | case M_MSGWAIT: | |
df58fc94 | 11331 | gas_assert (!mips_opts.micromips); |
52b6b6b9 | 11332 | macro_build (NULL, "c2", "C", 3); |
c7af4273 | 11333 | break; |
52b6b6b9 JM |
11334 | |
11335 | case M_MSGWAIT_T: | |
df58fc94 | 11336 | gas_assert (!mips_opts.micromips); |
c0ebe874 | 11337 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
c7af4273 | 11338 | break; |
52b6b6b9 | 11339 | |
252b5132 RH |
11340 | case M_J_A: |
11341 | /* The j instruction may not be used in PIC code, since it | |
11342 | requires an absolute address. We convert it to a b | |
11343 | instruction. */ | |
11344 | if (mips_pic == NO_PIC) | |
67c0d1eb | 11345 | macro_build (&offset_expr, "j", "a"); |
252b5132 | 11346 | else |
67c0d1eb | 11347 | macro_build (&offset_expr, "b", "p"); |
8fc2e39e | 11348 | break; |
252b5132 RH |
11349 | |
11350 | /* The jal instructions must be handled as macros because when | |
11351 | generating PIC code they expand to multi-instruction | |
11352 | sequences. Normally they are simple instructions. */ | |
df58fc94 | 11353 | case M_JALS_1: |
c0ebe874 RS |
11354 | op[1] = op[0]; |
11355 | op[0] = RA; | |
df58fc94 RS |
11356 | /* Fall through. */ |
11357 | case M_JALS_2: | |
11358 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11359 | if (mips_opts.insn32) |
11360 | { | |
1661c76c | 11361 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11362 | break; |
11363 | } | |
df58fc94 RS |
11364 | jals = 1; |
11365 | goto jal; | |
252b5132 | 11366 | case M_JAL_1: |
c0ebe874 RS |
11367 | op[1] = op[0]; |
11368 | op[0] = RA; | |
252b5132 RH |
11369 | /* Fall through. */ |
11370 | case M_JAL_2: | |
df58fc94 | 11371 | jal: |
3e722fb5 | 11372 | if (mips_pic == NO_PIC) |
df58fc94 RS |
11373 | { |
11374 | s = jals ? "jalrs" : "jalr"; | |
e64af278 | 11375 | if (mips_opts.micromips |
833794fc | 11376 | && !mips_opts.insn32 |
c0ebe874 | 11377 | && op[0] == RA |
e64af278 | 11378 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11379 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11380 | else |
c0ebe874 | 11381 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
df58fc94 | 11382 | } |
0a44bf69 | 11383 | else |
252b5132 | 11384 | { |
df58fc94 RS |
11385 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
11386 | && mips_cprestore_offset >= 0); | |
11387 | ||
c0ebe874 | 11388 | if (op[1] != PIC_CALL_REG) |
252b5132 | 11389 | as_warn (_("MIPS PIC call to register other than $25")); |
bdaaa2e1 | 11390 | |
833794fc MR |
11391 | s = ((mips_opts.micromips |
11392 | && !mips_opts.insn32 | |
11393 | && (!mips_opts.noreorder || cprestore)) | |
df58fc94 | 11394 | ? "jalrs" : "jalr"); |
e64af278 | 11395 | if (mips_opts.micromips |
833794fc | 11396 | && !mips_opts.insn32 |
c0ebe874 | 11397 | && op[0] == RA |
e64af278 | 11398 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
c0ebe874 | 11399 | macro_build (NULL, s, "mj", op[1]); |
df58fc94 | 11400 | else |
c0ebe874 | 11401 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
0a44bf69 | 11402 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
252b5132 | 11403 | { |
6478892d | 11404 | if (mips_cprestore_offset < 0) |
1661c76c | 11405 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11406 | else |
11407 | { | |
90ecf173 | 11408 | if (!mips_frame_reg_valid) |
7a621144 | 11409 | { |
1661c76c | 11410 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11411 | /* Quiet this warning. */ |
11412 | mips_frame_reg_valid = 1; | |
11413 | } | |
90ecf173 | 11414 | if (!mips_cprestore_valid) |
7a621144 | 11415 | { |
1661c76c | 11416 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11417 | /* Quiet this warning. */ |
11418 | mips_cprestore_valid = 1; | |
11419 | } | |
d3fca0b5 MR |
11420 | if (mips_opts.noreorder) |
11421 | macro_build (NULL, "nop", ""); | |
6478892d | 11422 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11423 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11424 | mips_gp_register, |
256ab948 TS |
11425 | mips_frame_reg, |
11426 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11427 | } |
252b5132 RH |
11428 | } |
11429 | } | |
252b5132 | 11430 | |
8fc2e39e | 11431 | break; |
252b5132 | 11432 | |
df58fc94 RS |
11433 | case M_JALS_A: |
11434 | gas_assert (mips_opts.micromips); | |
833794fc MR |
11435 | if (mips_opts.insn32) |
11436 | { | |
1661c76c | 11437 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
833794fc MR |
11438 | break; |
11439 | } | |
df58fc94 RS |
11440 | jals = 1; |
11441 | /* Fall through. */ | |
252b5132 RH |
11442 | case M_JAL_A: |
11443 | if (mips_pic == NO_PIC) | |
df58fc94 | 11444 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
252b5132 RH |
11445 | else if (mips_pic == SVR4_PIC) |
11446 | { | |
11447 | /* If this is a reference to an external symbol, and we are | |
11448 | using a small GOT, we want | |
11449 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) | |
11450 | nop | |
f9419b05 | 11451 | jalr $ra,$25 |
252b5132 RH |
11452 | nop |
11453 | lw $gp,cprestore($sp) | |
11454 | The cprestore value is set using the .cprestore | |
11455 | pseudo-op. If we are using a big GOT, we want | |
11456 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) | |
11457 | addu $25,$25,$gp | |
11458 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) | |
11459 | nop | |
f9419b05 | 11460 | jalr $ra,$25 |
252b5132 RH |
11461 | nop |
11462 | lw $gp,cprestore($sp) | |
11463 | If the symbol is not external, we want | |
11464 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
11465 | nop | |
11466 | addiu $25,$25,<sym> (BFD_RELOC_LO16) | |
f9419b05 | 11467 | jalr $ra,$25 |
252b5132 | 11468 | nop |
438c16b8 | 11469 | lw $gp,cprestore($sp) |
f5040a92 AO |
11470 | |
11471 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 | |
11472 | sequences above, minus nops, unless the symbol is local, | |
11473 | which enables us to use GOT_PAGE/GOT_OFST (big got) or | |
11474 | GOT_DISP. */ | |
438c16b8 | 11475 | if (HAVE_NEWABI) |
252b5132 | 11476 | { |
90ecf173 | 11477 | if (!mips_big_got) |
f5040a92 | 11478 | { |
4d7206a2 | 11479 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb RS |
11480 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11481 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
f5040a92 | 11482 | mips_gp_register); |
4d7206a2 | 11483 | relax_switch (); |
67c0d1eb RS |
11484 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11485 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, | |
4d7206a2 RS |
11486 | mips_gp_register); |
11487 | relax_end (); | |
f5040a92 AO |
11488 | } |
11489 | else | |
11490 | { | |
4d7206a2 | 11491 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 11492 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11493 | BFD_RELOC_MIPS_CALL_HI16); |
11494 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11495 | PIC_CALL_REG, mips_gp_register); | |
11496 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11497 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11498 | PIC_CALL_REG); | |
4d7206a2 | 11499 | relax_switch (); |
67c0d1eb RS |
11500 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11501 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, | |
11502 | mips_gp_register); | |
11503 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11504 | PIC_CALL_REG, PIC_CALL_REG, | |
17a2f251 | 11505 | BFD_RELOC_MIPS_GOT_OFST); |
4d7206a2 | 11506 | relax_end (); |
f5040a92 | 11507 | } |
684022ea | 11508 | |
df58fc94 | 11509 | macro_build_jalr (&offset_expr, 0); |
252b5132 RH |
11510 | } |
11511 | else | |
11512 | { | |
4d7206a2 | 11513 | relax_start (offset_expr.X_add_symbol); |
90ecf173 | 11514 | if (!mips_big_got) |
438c16b8 | 11515 | { |
67c0d1eb RS |
11516 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11517 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, | |
17a2f251 | 11518 | mips_gp_register); |
269137b2 | 11519 | load_delay_nop (); |
4d7206a2 | 11520 | relax_switch (); |
438c16b8 | 11521 | } |
252b5132 | 11522 | else |
252b5132 | 11523 | { |
67c0d1eb RS |
11524 | int gpdelay; |
11525 | ||
11526 | gpdelay = reg_needs_delay (mips_gp_register); | |
df58fc94 | 11527 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
67c0d1eb RS |
11528 | BFD_RELOC_MIPS_CALL_HI16); |
11529 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, | |
11530 | PIC_CALL_REG, mips_gp_register); | |
11531 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", | |
11532 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, | |
11533 | PIC_CALL_REG); | |
269137b2 | 11534 | load_delay_nop (); |
4d7206a2 | 11535 | relax_switch (); |
67c0d1eb RS |
11536 | if (gpdelay) |
11537 | macro_build (NULL, "nop", ""); | |
252b5132 | 11538 | } |
67c0d1eb RS |
11539 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
11540 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, | |
4d7206a2 | 11541 | mips_gp_register); |
269137b2 | 11542 | load_delay_nop (); |
67c0d1eb RS |
11543 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
11544 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); | |
4d7206a2 | 11545 | relax_end (); |
df58fc94 | 11546 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
438c16b8 | 11547 | |
6478892d | 11548 | if (mips_cprestore_offset < 0) |
1661c76c | 11549 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
6478892d TS |
11550 | else |
11551 | { | |
90ecf173 | 11552 | if (!mips_frame_reg_valid) |
7a621144 | 11553 | { |
1661c76c | 11554 | as_warn (_("no .frame pseudo-op used in PIC code")); |
7a621144 DJ |
11555 | /* Quiet this warning. */ |
11556 | mips_frame_reg_valid = 1; | |
11557 | } | |
90ecf173 | 11558 | if (!mips_cprestore_valid) |
7a621144 | 11559 | { |
1661c76c | 11560 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
7a621144 DJ |
11561 | /* Quiet this warning. */ |
11562 | mips_cprestore_valid = 1; | |
11563 | } | |
6478892d | 11564 | if (mips_opts.noreorder) |
67c0d1eb | 11565 | macro_build (NULL, "nop", ""); |
6478892d | 11566 | expr1.X_add_number = mips_cprestore_offset; |
134c0c8b | 11567 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
f899b4b8 | 11568 | mips_gp_register, |
256ab948 TS |
11569 | mips_frame_reg, |
11570 | HAVE_64BIT_ADDRESSES); | |
6478892d | 11571 | } |
252b5132 RH |
11572 | } |
11573 | } | |
0a44bf69 | 11574 | else if (mips_pic == VXWORKS_PIC) |
1661c76c | 11575 | as_bad (_("non-PIC jump used in PIC library")); |
252b5132 RH |
11576 | else |
11577 | abort (); | |
11578 | ||
8fc2e39e | 11579 | break; |
252b5132 | 11580 | |
7f3c4072 | 11581 | case M_LBUE_AB: |
7f3c4072 CM |
11582 | s = "lbue"; |
11583 | fmt = "t,+j(b)"; | |
11584 | offbits = 9; | |
11585 | goto ld_st; | |
11586 | case M_LHUE_AB: | |
7f3c4072 CM |
11587 | s = "lhue"; |
11588 | fmt = "t,+j(b)"; | |
11589 | offbits = 9; | |
11590 | goto ld_st; | |
11591 | case M_LBE_AB: | |
7f3c4072 CM |
11592 | s = "lbe"; |
11593 | fmt = "t,+j(b)"; | |
11594 | offbits = 9; | |
11595 | goto ld_st; | |
11596 | case M_LHE_AB: | |
7f3c4072 CM |
11597 | s = "lhe"; |
11598 | fmt = "t,+j(b)"; | |
11599 | offbits = 9; | |
11600 | goto ld_st; | |
11601 | case M_LLE_AB: | |
7f3c4072 CM |
11602 | s = "lle"; |
11603 | fmt = "t,+j(b)"; | |
11604 | offbits = 9; | |
11605 | goto ld_st; | |
11606 | case M_LWE_AB: | |
7f3c4072 CM |
11607 | s = "lwe"; |
11608 | fmt = "t,+j(b)"; | |
11609 | offbits = 9; | |
11610 | goto ld_st; | |
11611 | case M_LWLE_AB: | |
7f3c4072 CM |
11612 | s = "lwle"; |
11613 | fmt = "t,+j(b)"; | |
11614 | offbits = 9; | |
11615 | goto ld_st; | |
11616 | case M_LWRE_AB: | |
7f3c4072 CM |
11617 | s = "lwre"; |
11618 | fmt = "t,+j(b)"; | |
11619 | offbits = 9; | |
11620 | goto ld_st; | |
11621 | case M_SBE_AB: | |
7f3c4072 CM |
11622 | s = "sbe"; |
11623 | fmt = "t,+j(b)"; | |
11624 | offbits = 9; | |
11625 | goto ld_st; | |
11626 | case M_SCE_AB: | |
7f3c4072 CM |
11627 | s = "sce"; |
11628 | fmt = "t,+j(b)"; | |
11629 | offbits = 9; | |
11630 | goto ld_st; | |
11631 | case M_SHE_AB: | |
7f3c4072 CM |
11632 | s = "she"; |
11633 | fmt = "t,+j(b)"; | |
11634 | offbits = 9; | |
11635 | goto ld_st; | |
11636 | case M_SWE_AB: | |
7f3c4072 CM |
11637 | s = "swe"; |
11638 | fmt = "t,+j(b)"; | |
11639 | offbits = 9; | |
11640 | goto ld_st; | |
11641 | case M_SWLE_AB: | |
7f3c4072 CM |
11642 | s = "swle"; |
11643 | fmt = "t,+j(b)"; | |
11644 | offbits = 9; | |
11645 | goto ld_st; | |
11646 | case M_SWRE_AB: | |
7f3c4072 CM |
11647 | s = "swre"; |
11648 | fmt = "t,+j(b)"; | |
11649 | offbits = 9; | |
11650 | goto ld_st; | |
dec0624d | 11651 | case M_ACLR_AB: |
dec0624d | 11652 | s = "aclr"; |
dec0624d | 11653 | fmt = "\\,~(b)"; |
7f3c4072 | 11654 | offbits = 12; |
dec0624d MR |
11655 | goto ld_st; |
11656 | case M_ASET_AB: | |
dec0624d | 11657 | s = "aset"; |
dec0624d | 11658 | fmt = "\\,~(b)"; |
7f3c4072 | 11659 | offbits = 12; |
dec0624d | 11660 | goto ld_st; |
252b5132 RH |
11661 | case M_LB_AB: |
11662 | s = "lb"; | |
df58fc94 | 11663 | fmt = "t,o(b)"; |
252b5132 RH |
11664 | goto ld; |
11665 | case M_LBU_AB: | |
11666 | s = "lbu"; | |
df58fc94 | 11667 | fmt = "t,o(b)"; |
252b5132 RH |
11668 | goto ld; |
11669 | case M_LH_AB: | |
11670 | s = "lh"; | |
df58fc94 | 11671 | fmt = "t,o(b)"; |
252b5132 RH |
11672 | goto ld; |
11673 | case M_LHU_AB: | |
11674 | s = "lhu"; | |
df58fc94 | 11675 | fmt = "t,o(b)"; |
252b5132 RH |
11676 | goto ld; |
11677 | case M_LW_AB: | |
11678 | s = "lw"; | |
df58fc94 | 11679 | fmt = "t,o(b)"; |
252b5132 RH |
11680 | goto ld; |
11681 | case M_LWC0_AB: | |
df58fc94 | 11682 | gas_assert (!mips_opts.micromips); |
252b5132 | 11683 | s = "lwc0"; |
df58fc94 | 11684 | fmt = "E,o(b)"; |
bdaaa2e1 | 11685 | /* Itbl support may require additional care here. */ |
252b5132 | 11686 | coproc = 1; |
df58fc94 | 11687 | goto ld_st; |
252b5132 RH |
11688 | case M_LWC1_AB: |
11689 | s = "lwc1"; | |
df58fc94 | 11690 | fmt = "T,o(b)"; |
bdaaa2e1 | 11691 | /* Itbl support may require additional care here. */ |
252b5132 | 11692 | coproc = 1; |
df58fc94 | 11693 | goto ld_st; |
252b5132 RH |
11694 | case M_LWC2_AB: |
11695 | s = "lwc2"; | |
df58fc94 | 11696 | fmt = COP12_FMT; |
7361da2c AB |
11697 | offbits = (mips_opts.micromips ? 12 |
11698 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11699 | : 16); | |
bdaaa2e1 | 11700 | /* Itbl support may require additional care here. */ |
252b5132 | 11701 | coproc = 1; |
df58fc94 | 11702 | goto ld_st; |
252b5132 | 11703 | case M_LWC3_AB: |
df58fc94 | 11704 | gas_assert (!mips_opts.micromips); |
252b5132 | 11705 | s = "lwc3"; |
df58fc94 | 11706 | fmt = "E,o(b)"; |
bdaaa2e1 | 11707 | /* Itbl support may require additional care here. */ |
252b5132 | 11708 | coproc = 1; |
df58fc94 | 11709 | goto ld_st; |
252b5132 RH |
11710 | case M_LWL_AB: |
11711 | s = "lwl"; | |
df58fc94 | 11712 | fmt = MEM12_FMT; |
7f3c4072 | 11713 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11714 | goto ld_st; |
252b5132 RH |
11715 | case M_LWR_AB: |
11716 | s = "lwr"; | |
df58fc94 | 11717 | fmt = MEM12_FMT; |
7f3c4072 | 11718 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11719 | goto ld_st; |
252b5132 | 11720 | case M_LDC1_AB: |
252b5132 | 11721 | s = "ldc1"; |
df58fc94 | 11722 | fmt = "T,o(b)"; |
bdaaa2e1 | 11723 | /* Itbl support may require additional care here. */ |
252b5132 | 11724 | coproc = 1; |
df58fc94 | 11725 | goto ld_st; |
252b5132 RH |
11726 | case M_LDC2_AB: |
11727 | s = "ldc2"; | |
df58fc94 | 11728 | fmt = COP12_FMT; |
7361da2c AB |
11729 | offbits = (mips_opts.micromips ? 12 |
11730 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11731 | : 16); | |
bdaaa2e1 | 11732 | /* Itbl support may require additional care here. */ |
252b5132 | 11733 | coproc = 1; |
df58fc94 | 11734 | goto ld_st; |
c77c0862 | 11735 | case M_LQC2_AB: |
c77c0862 | 11736 | s = "lqc2"; |
14daeee3 | 11737 | fmt = "+7,o(b)"; |
c77c0862 RS |
11738 | /* Itbl support may require additional care here. */ |
11739 | coproc = 1; | |
11740 | goto ld_st; | |
252b5132 RH |
11741 | case M_LDC3_AB: |
11742 | s = "ldc3"; | |
df58fc94 | 11743 | fmt = "E,o(b)"; |
bdaaa2e1 | 11744 | /* Itbl support may require additional care here. */ |
252b5132 | 11745 | coproc = 1; |
df58fc94 | 11746 | goto ld_st; |
252b5132 RH |
11747 | case M_LDL_AB: |
11748 | s = "ldl"; | |
df58fc94 | 11749 | fmt = MEM12_FMT; |
7f3c4072 | 11750 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11751 | goto ld_st; |
252b5132 RH |
11752 | case M_LDR_AB: |
11753 | s = "ldr"; | |
df58fc94 | 11754 | fmt = MEM12_FMT; |
7f3c4072 | 11755 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11756 | goto ld_st; |
252b5132 RH |
11757 | case M_LL_AB: |
11758 | s = "ll"; | |
7361da2c AB |
11759 | fmt = LL_SC_FMT; |
11760 | offbits = (mips_opts.micromips ? 12 | |
11761 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11762 | : 16); | |
252b5132 RH |
11763 | goto ld; |
11764 | case M_LLD_AB: | |
11765 | s = "lld"; | |
7361da2c AB |
11766 | fmt = LL_SC_FMT; |
11767 | offbits = (mips_opts.micromips ? 12 | |
11768 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11769 | : 16); | |
252b5132 RH |
11770 | goto ld; |
11771 | case M_LWU_AB: | |
11772 | s = "lwu"; | |
df58fc94 | 11773 | fmt = MEM12_FMT; |
7f3c4072 | 11774 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11775 | goto ld; |
11776 | case M_LWP_AB: | |
df58fc94 RS |
11777 | gas_assert (mips_opts.micromips); |
11778 | s = "lwp"; | |
11779 | fmt = "t,~(b)"; | |
7f3c4072 | 11780 | offbits = 12; |
df58fc94 RS |
11781 | lp = 1; |
11782 | goto ld; | |
11783 | case M_LDP_AB: | |
df58fc94 RS |
11784 | gas_assert (mips_opts.micromips); |
11785 | s = "ldp"; | |
11786 | fmt = "t,~(b)"; | |
7f3c4072 | 11787 | offbits = 12; |
df58fc94 RS |
11788 | lp = 1; |
11789 | goto ld; | |
11790 | case M_LWM_AB: | |
df58fc94 RS |
11791 | gas_assert (mips_opts.micromips); |
11792 | s = "lwm"; | |
11793 | fmt = "n,~(b)"; | |
7f3c4072 | 11794 | offbits = 12; |
df58fc94 RS |
11795 | goto ld_st; |
11796 | case M_LDM_AB: | |
df58fc94 RS |
11797 | gas_assert (mips_opts.micromips); |
11798 | s = "ldm"; | |
11799 | fmt = "n,~(b)"; | |
7f3c4072 | 11800 | offbits = 12; |
df58fc94 RS |
11801 | goto ld_st; |
11802 | ||
252b5132 | 11803 | ld: |
f19ccbda | 11804 | /* We don't want to use $0 as tempreg. */ |
c0ebe874 | 11805 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
df58fc94 | 11806 | goto ld_st; |
252b5132 | 11807 | else |
c0ebe874 | 11808 | tempreg = op[0] + lp; |
df58fc94 RS |
11809 | goto ld_noat; |
11810 | ||
252b5132 RH |
11811 | case M_SB_AB: |
11812 | s = "sb"; | |
df58fc94 RS |
11813 | fmt = "t,o(b)"; |
11814 | goto ld_st; | |
252b5132 RH |
11815 | case M_SH_AB: |
11816 | s = "sh"; | |
df58fc94 RS |
11817 | fmt = "t,o(b)"; |
11818 | goto ld_st; | |
252b5132 RH |
11819 | case M_SW_AB: |
11820 | s = "sw"; | |
df58fc94 RS |
11821 | fmt = "t,o(b)"; |
11822 | goto ld_st; | |
252b5132 | 11823 | case M_SWC0_AB: |
df58fc94 | 11824 | gas_assert (!mips_opts.micromips); |
252b5132 | 11825 | s = "swc0"; |
df58fc94 | 11826 | fmt = "E,o(b)"; |
bdaaa2e1 | 11827 | /* Itbl support may require additional care here. */ |
252b5132 | 11828 | coproc = 1; |
df58fc94 | 11829 | goto ld_st; |
252b5132 RH |
11830 | case M_SWC1_AB: |
11831 | s = "swc1"; | |
df58fc94 | 11832 | fmt = "T,o(b)"; |
bdaaa2e1 | 11833 | /* Itbl support may require additional care here. */ |
252b5132 | 11834 | coproc = 1; |
df58fc94 | 11835 | goto ld_st; |
252b5132 RH |
11836 | case M_SWC2_AB: |
11837 | s = "swc2"; | |
df58fc94 | 11838 | fmt = COP12_FMT; |
7361da2c AB |
11839 | offbits = (mips_opts.micromips ? 12 |
11840 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11841 | : 16); | |
bdaaa2e1 | 11842 | /* Itbl support may require additional care here. */ |
252b5132 | 11843 | coproc = 1; |
df58fc94 | 11844 | goto ld_st; |
252b5132 | 11845 | case M_SWC3_AB: |
df58fc94 | 11846 | gas_assert (!mips_opts.micromips); |
252b5132 | 11847 | s = "swc3"; |
df58fc94 | 11848 | fmt = "E,o(b)"; |
bdaaa2e1 | 11849 | /* Itbl support may require additional care here. */ |
252b5132 | 11850 | coproc = 1; |
df58fc94 | 11851 | goto ld_st; |
252b5132 RH |
11852 | case M_SWL_AB: |
11853 | s = "swl"; | |
df58fc94 | 11854 | fmt = MEM12_FMT; |
7f3c4072 | 11855 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11856 | goto ld_st; |
252b5132 RH |
11857 | case M_SWR_AB: |
11858 | s = "swr"; | |
df58fc94 | 11859 | fmt = MEM12_FMT; |
7f3c4072 | 11860 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11861 | goto ld_st; |
252b5132 RH |
11862 | case M_SC_AB: |
11863 | s = "sc"; | |
7361da2c AB |
11864 | fmt = LL_SC_FMT; |
11865 | offbits = (mips_opts.micromips ? 12 | |
11866 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11867 | : 16); | |
df58fc94 | 11868 | goto ld_st; |
252b5132 RH |
11869 | case M_SCD_AB: |
11870 | s = "scd"; | |
7361da2c AB |
11871 | fmt = LL_SC_FMT; |
11872 | offbits = (mips_opts.micromips ? 12 | |
11873 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11874 | : 16); | |
df58fc94 | 11875 | goto ld_st; |
d43b4baf TS |
11876 | case M_CACHE_AB: |
11877 | s = "cache"; | |
7361da2c AB |
11878 | fmt = (mips_opts.micromips ? "k,~(b)" |
11879 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11880 | : "k,o(b)"); | |
11881 | offbits = (mips_opts.micromips ? 12 | |
11882 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11883 | : 16); | |
7f3c4072 CM |
11884 | goto ld_st; |
11885 | case M_CACHEE_AB: | |
7f3c4072 CM |
11886 | s = "cachee"; |
11887 | fmt = "k,+j(b)"; | |
11888 | offbits = 9; | |
df58fc94 | 11889 | goto ld_st; |
3eebd5eb MR |
11890 | case M_PREF_AB: |
11891 | s = "pref"; | |
7361da2c AB |
11892 | fmt = (mips_opts.micromips ? "k,~(b)" |
11893 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" | |
11894 | : "k,o(b)"); | |
11895 | offbits = (mips_opts.micromips ? 12 | |
11896 | : ISA_IS_R6 (mips_opts.isa) ? 9 | |
11897 | : 16); | |
7f3c4072 CM |
11898 | goto ld_st; |
11899 | case M_PREFE_AB: | |
7f3c4072 CM |
11900 | s = "prefe"; |
11901 | fmt = "k,+j(b)"; | |
11902 | offbits = 9; | |
df58fc94 | 11903 | goto ld_st; |
252b5132 | 11904 | case M_SDC1_AB: |
252b5132 | 11905 | s = "sdc1"; |
df58fc94 | 11906 | fmt = "T,o(b)"; |
252b5132 | 11907 | coproc = 1; |
bdaaa2e1 | 11908 | /* Itbl support may require additional care here. */ |
df58fc94 | 11909 | goto ld_st; |
252b5132 RH |
11910 | case M_SDC2_AB: |
11911 | s = "sdc2"; | |
df58fc94 | 11912 | fmt = COP12_FMT; |
7361da2c AB |
11913 | offbits = (mips_opts.micromips ? 12 |
11914 | : ISA_IS_R6 (mips_opts.isa) ? 11 | |
11915 | : 16); | |
c77c0862 RS |
11916 | /* Itbl support may require additional care here. */ |
11917 | coproc = 1; | |
11918 | goto ld_st; | |
11919 | case M_SQC2_AB: | |
c77c0862 | 11920 | s = "sqc2"; |
14daeee3 | 11921 | fmt = "+7,o(b)"; |
bdaaa2e1 | 11922 | /* Itbl support may require additional care here. */ |
252b5132 | 11923 | coproc = 1; |
df58fc94 | 11924 | goto ld_st; |
252b5132 | 11925 | case M_SDC3_AB: |
df58fc94 | 11926 | gas_assert (!mips_opts.micromips); |
252b5132 | 11927 | s = "sdc3"; |
df58fc94 | 11928 | fmt = "E,o(b)"; |
bdaaa2e1 | 11929 | /* Itbl support may require additional care here. */ |
252b5132 | 11930 | coproc = 1; |
df58fc94 | 11931 | goto ld_st; |
252b5132 RH |
11932 | case M_SDL_AB: |
11933 | s = "sdl"; | |
df58fc94 | 11934 | fmt = MEM12_FMT; |
7f3c4072 | 11935 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 | 11936 | goto ld_st; |
252b5132 RH |
11937 | case M_SDR_AB: |
11938 | s = "sdr"; | |
df58fc94 | 11939 | fmt = MEM12_FMT; |
7f3c4072 | 11940 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
11941 | goto ld_st; |
11942 | case M_SWP_AB: | |
df58fc94 RS |
11943 | gas_assert (mips_opts.micromips); |
11944 | s = "swp"; | |
11945 | fmt = "t,~(b)"; | |
7f3c4072 | 11946 | offbits = 12; |
df58fc94 RS |
11947 | goto ld_st; |
11948 | case M_SDP_AB: | |
df58fc94 RS |
11949 | gas_assert (mips_opts.micromips); |
11950 | s = "sdp"; | |
11951 | fmt = "t,~(b)"; | |
7f3c4072 | 11952 | offbits = 12; |
df58fc94 RS |
11953 | goto ld_st; |
11954 | case M_SWM_AB: | |
df58fc94 RS |
11955 | gas_assert (mips_opts.micromips); |
11956 | s = "swm"; | |
11957 | fmt = "n,~(b)"; | |
7f3c4072 | 11958 | offbits = 12; |
df58fc94 RS |
11959 | goto ld_st; |
11960 | case M_SDM_AB: | |
df58fc94 RS |
11961 | gas_assert (mips_opts.micromips); |
11962 | s = "sdm"; | |
11963 | fmt = "n,~(b)"; | |
7f3c4072 | 11964 | offbits = 12; |
df58fc94 RS |
11965 | |
11966 | ld_st: | |
8fc2e39e | 11967 | tempreg = AT; |
df58fc94 | 11968 | ld_noat: |
c0ebe874 | 11969 | breg = op[2]; |
f2ae14a1 RS |
11970 | if (small_offset_p (0, align, 16)) |
11971 | { | |
11972 | /* The first case exists for M_LD_AB and M_SD_AB, which are | |
11973 | macros for o32 but which should act like normal instructions | |
11974 | otherwise. */ | |
11975 | if (offbits == 16) | |
c0ebe874 | 11976 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
11977 | offset_reloc[1], offset_reloc[2], breg); |
11978 | else if (small_offset_p (0, align, offbits)) | |
11979 | { | |
11980 | if (offbits == 0) | |
c0ebe874 | 11981 | macro_build (NULL, s, fmt, op[0], breg); |
f2ae14a1 | 11982 | else |
c0ebe874 | 11983 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 11984 | (int) offset_expr.X_add_number, breg); |
f2ae14a1 RS |
11985 | } |
11986 | else | |
11987 | { | |
11988 | if (tempreg == AT) | |
11989 | used_at = 1; | |
11990 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", | |
11991 | tempreg, breg, -1, offset_reloc[0], | |
11992 | offset_reloc[1], offset_reloc[2]); | |
11993 | if (offbits == 0) | |
c0ebe874 | 11994 | macro_build (NULL, s, fmt, op[0], tempreg); |
f2ae14a1 | 11995 | else |
c0ebe874 | 11996 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
f2ae14a1 RS |
11997 | } |
11998 | break; | |
11999 | } | |
12000 | ||
12001 | if (tempreg == AT) | |
12002 | used_at = 1; | |
12003 | ||
252b5132 RH |
12004 | if (offset_expr.X_op != O_constant |
12005 | && offset_expr.X_op != O_symbol) | |
12006 | { | |
1661c76c | 12007 | as_bad (_("expression too complex")); |
252b5132 RH |
12008 | offset_expr.X_op = O_constant; |
12009 | } | |
12010 | ||
2051e8c4 MR |
12011 | if (HAVE_32BIT_ADDRESSES |
12012 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12013 | { |
12014 | char value [32]; | |
12015 | ||
12016 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12017 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12018 | } |
2051e8c4 | 12019 | |
252b5132 RH |
12020 | /* A constant expression in PIC code can be handled just as it |
12021 | is in non PIC code. */ | |
aed1a261 RS |
12022 | if (offset_expr.X_op == O_constant) |
12023 | { | |
f2ae14a1 RS |
12024 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
12025 | offbits == 0 ? 16 : offbits); | |
12026 | offset_expr.X_add_number -= expr1.X_add_number; | |
df58fc94 | 12027 | |
f2ae14a1 RS |
12028 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
12029 | if (breg != 0) | |
12030 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12031 | tempreg, tempreg, breg); | |
7f3c4072 | 12032 | if (offbits == 0) |
dd6a37e7 | 12033 | { |
f2ae14a1 | 12034 | if (offset_expr.X_add_number != 0) |
dd6a37e7 | 12035 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
f2ae14a1 | 12036 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
c0ebe874 | 12037 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12038 | } |
7f3c4072 | 12039 | else if (offbits == 16) |
c0ebe874 | 12040 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
df58fc94 | 12041 | else |
c0ebe874 | 12042 | macro_build (NULL, s, fmt, op[0], |
c8276761 | 12043 | (int) offset_expr.X_add_number, tempreg); |
df58fc94 | 12044 | } |
7f3c4072 | 12045 | else if (offbits != 16) |
df58fc94 | 12046 | { |
7f3c4072 | 12047 | /* The offset field is too narrow to be used for a low-part |
2b0f3761 | 12048 | relocation, so load the whole address into the auxiliary |
f2ae14a1 RS |
12049 | register. */ |
12050 | load_address (tempreg, &offset_expr, &used_at); | |
12051 | if (breg != 0) | |
12052 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12053 | tempreg, tempreg, breg); | |
7f3c4072 | 12054 | if (offbits == 0) |
c0ebe874 | 12055 | macro_build (NULL, s, fmt, op[0], tempreg); |
dd6a37e7 | 12056 | else |
c0ebe874 | 12057 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
aed1a261 RS |
12058 | } |
12059 | else if (mips_pic == NO_PIC) | |
252b5132 RH |
12060 | { |
12061 | /* If this is a reference to a GP relative symbol, and there | |
12062 | is no base register, we want | |
c0ebe874 | 12063 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
252b5132 RH |
12064 | Otherwise, if there is no base register, we want |
12065 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 | 12066 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
252b5132 RH |
12067 | If we have a constant, we need two instructions anyhow, |
12068 | so we always use the latter form. | |
12069 | ||
12070 | If we have a base register, and this is a reference to a | |
12071 | GP relative symbol, we want | |
12072 | addu $tempreg,$breg,$gp | |
c0ebe874 | 12073 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
252b5132 RH |
12074 | Otherwise we want |
12075 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12076 | addu $tempreg,$tempreg,$breg | |
c0ebe874 | 12077 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 | 12078 | With a constant we always use the latter case. |
76b3015f | 12079 | |
d6bc6245 TS |
12080 | With 64bit address space and no base register and $at usable, |
12081 | we want | |
12082 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12083 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12084 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12085 | dsll32 $tempreg,0 | |
12086 | daddu $tempreg,$at | |
c0ebe874 | 12087 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12088 | If we have a base register, we want |
12089 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12090 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
12091 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12092 | daddu $at,$breg | |
12093 | dsll32 $tempreg,0 | |
12094 | daddu $tempreg,$at | |
c0ebe874 | 12095 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12096 | |
12097 | Without $at we can't generate the optimal path for superscalar | |
12098 | processors here since this would require two temporary registers. | |
12099 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12100 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12101 | dsll $tempreg,16 | |
12102 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12103 | dsll $tempreg,16 | |
c0ebe874 | 12104 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
d6bc6245 TS |
12105 | If we have a base register, we want |
12106 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) | |
12107 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) | |
12108 | dsll $tempreg,16 | |
12109 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) | |
12110 | dsll $tempreg,16 | |
12111 | daddu $tempreg,$tempreg,$breg | |
c0ebe874 | 12112 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
6373ee54 | 12113 | |
6caf9ef4 | 12114 | For GP relative symbols in 64bit address space we can use |
aed1a261 RS |
12115 | the same sequence as in 32bit address space. */ |
12116 | if (HAVE_64BIT_SYMBOLS) | |
d6bc6245 | 12117 | { |
aed1a261 | 12118 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 TS |
12119 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
12120 | { | |
12121 | relax_start (offset_expr.X_add_symbol); | |
12122 | if (breg == 0) | |
12123 | { | |
c0ebe874 | 12124 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12125 | BFD_RELOC_GPREL16, mips_gp_register); |
12126 | } | |
12127 | else | |
12128 | { | |
12129 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
12130 | tempreg, breg, mips_gp_register); | |
c0ebe874 | 12131 | macro_build (&offset_expr, s, fmt, op[0], |
6caf9ef4 TS |
12132 | BFD_RELOC_GPREL16, tempreg); |
12133 | } | |
12134 | relax_switch (); | |
12135 | } | |
d6bc6245 | 12136 | |
741fe287 | 12137 | if (used_at == 0 && mips_opts.at) |
d6bc6245 | 12138 | { |
df58fc94 | 12139 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb | 12140 | BFD_RELOC_MIPS_HIGHEST); |
df58fc94 | 12141 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
67c0d1eb RS |
12142 | BFD_RELOC_HI16_S); |
12143 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12144 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
d6bc6245 | 12145 | if (breg != 0) |
67c0d1eb | 12146 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
df58fc94 | 12147 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
67c0d1eb | 12148 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
c0ebe874 | 12149 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
67c0d1eb | 12150 | tempreg); |
d6bc6245 TS |
12151 | used_at = 1; |
12152 | } | |
12153 | else | |
12154 | { | |
df58fc94 | 12155 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
67c0d1eb RS |
12156 | BFD_RELOC_MIPS_HIGHEST); |
12157 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, | |
12158 | tempreg, BFD_RELOC_MIPS_HIGHER); | |
df58fc94 | 12159 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
67c0d1eb RS |
12160 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
12161 | tempreg, BFD_RELOC_HI16_S); | |
df58fc94 | 12162 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
d6bc6245 | 12163 | if (breg != 0) |
67c0d1eb | 12164 | macro_build (NULL, "daddu", "d,v,t", |
17a2f251 | 12165 | tempreg, tempreg, breg); |
c0ebe874 | 12166 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12167 | BFD_RELOC_LO16, tempreg); |
d6bc6245 | 12168 | } |
6caf9ef4 TS |
12169 | |
12170 | if (mips_relax.sequence) | |
12171 | relax_end (); | |
8fc2e39e | 12172 | break; |
d6bc6245 | 12173 | } |
256ab948 | 12174 | |
252b5132 RH |
12175 | if (breg == 0) |
12176 | { | |
67c0d1eb | 12177 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12178 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12179 | { |
4d7206a2 | 12180 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12181 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
67c0d1eb | 12182 | mips_gp_register); |
4d7206a2 | 12183 | relax_switch (); |
252b5132 | 12184 | } |
67c0d1eb | 12185 | macro_build_lui (&offset_expr, tempreg); |
c0ebe874 | 12186 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12187 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12188 | if (mips_relax.sequence) |
12189 | relax_end (); | |
252b5132 RH |
12190 | } |
12191 | else | |
12192 | { | |
67c0d1eb | 12193 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
6caf9ef4 | 12194 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12195 | { |
4d7206a2 | 12196 | relax_start (offset_expr.X_add_symbol); |
67c0d1eb | 12197 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12198 | tempreg, breg, mips_gp_register); |
c0ebe874 | 12199 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12200 | BFD_RELOC_GPREL16, tempreg); |
4d7206a2 | 12201 | relax_switch (); |
252b5132 | 12202 | } |
67c0d1eb RS |
12203 | macro_build_lui (&offset_expr, tempreg); |
12204 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12205 | tempreg, tempreg, breg); |
c0ebe874 | 12206 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12207 | BFD_RELOC_LO16, tempreg); |
4d7206a2 RS |
12208 | if (mips_relax.sequence) |
12209 | relax_end (); | |
252b5132 RH |
12210 | } |
12211 | } | |
0a44bf69 | 12212 | else if (!mips_big_got) |
252b5132 | 12213 | { |
ed6fb7bd | 12214 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
f9419b05 | 12215 | |
252b5132 RH |
12216 | /* If this is a reference to an external symbol, we want |
12217 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12218 | nop | |
c0ebe874 | 12219 | <op> op[0],0($tempreg) |
252b5132 RH |
12220 | Otherwise we want |
12221 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12222 | nop | |
12223 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12224 | <op> op[0],0($tempreg) |
f5040a92 AO |
12225 | |
12226 | For NewABI, we want | |
12227 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12228 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
f5040a92 | 12229 | |
252b5132 RH |
12230 | If there is a base register, we add it to $tempreg before |
12231 | the <op>. If there is a constant, we stick it in the | |
12232 | <op> instruction. We don't handle constants larger than | |
12233 | 16 bits, because we have no way to load the upper 16 bits | |
12234 | (actually, we could handle them for the subset of cases | |
12235 | in which we are not using $at). */ | |
9c2799c2 | 12236 | gas_assert (offset_expr.X_op == O_symbol); |
f5040a92 AO |
12237 | if (HAVE_NEWABI) |
12238 | { | |
67c0d1eb RS |
12239 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12240 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12241 | if (breg != 0) |
67c0d1eb | 12242 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12243 | tempreg, tempreg, breg); |
c0ebe874 | 12244 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12245 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
f5040a92 AO |
12246 | break; |
12247 | } | |
252b5132 RH |
12248 | expr1.X_add_number = offset_expr.X_add_number; |
12249 | offset_expr.X_add_number = 0; | |
12250 | if (expr1.X_add_number < -0x8000 | |
12251 | || expr1.X_add_number >= 0x8000) | |
12252 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb RS |
12253 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12254 | lw_reloc_type, mips_gp_register); | |
269137b2 | 12255 | load_delay_nop (); |
4d7206a2 RS |
12256 | relax_start (offset_expr.X_add_symbol); |
12257 | relax_switch (); | |
67c0d1eb RS |
12258 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12259 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 | 12260 | relax_end (); |
252b5132 | 12261 | if (breg != 0) |
67c0d1eb | 12262 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12263 | tempreg, tempreg, breg); |
c0ebe874 | 12264 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12265 | } |
0a44bf69 | 12266 | else if (mips_big_got && !HAVE_NEWABI) |
252b5132 | 12267 | { |
67c0d1eb | 12268 | int gpdelay; |
252b5132 RH |
12269 | |
12270 | /* If this is a reference to an external symbol, we want | |
12271 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12272 | addu $tempreg,$tempreg,$gp | |
12273 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12274 | <op> op[0],0($tempreg) |
252b5132 RH |
12275 | Otherwise we want |
12276 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12277 | nop | |
12278 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) | |
c0ebe874 | 12279 | <op> op[0],0($tempreg) |
252b5132 RH |
12280 | If there is a base register, we add it to $tempreg before |
12281 | the <op>. If there is a constant, we stick it in the | |
12282 | <op> instruction. We don't handle constants larger than | |
12283 | 16 bits, because we have no way to load the upper 16 bits | |
12284 | (actually, we could handle them for the subset of cases | |
f5040a92 | 12285 | in which we are not using $at). */ |
9c2799c2 | 12286 | gas_assert (offset_expr.X_op == O_symbol); |
252b5132 RH |
12287 | expr1.X_add_number = offset_expr.X_add_number; |
12288 | offset_expr.X_add_number = 0; | |
12289 | if (expr1.X_add_number < -0x8000 | |
12290 | || expr1.X_add_number >= 0x8000) | |
12291 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12292 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12293 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12294 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12295 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12296 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12297 | mips_gp_register); | |
12298 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12299 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
4d7206a2 | 12300 | relax_switch (); |
67c0d1eb RS |
12301 | if (gpdelay) |
12302 | macro_build (NULL, "nop", ""); | |
12303 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12304 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12305 | load_delay_nop (); |
67c0d1eb RS |
12306 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
12307 | tempreg, BFD_RELOC_LO16); | |
4d7206a2 RS |
12308 | relax_end (); |
12309 | ||
252b5132 | 12310 | if (breg != 0) |
67c0d1eb | 12311 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12312 | tempreg, tempreg, breg); |
c0ebe874 | 12313 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
252b5132 | 12314 | } |
0a44bf69 | 12315 | else if (mips_big_got && HAVE_NEWABI) |
f5040a92 | 12316 | { |
f5040a92 AO |
12317 | /* If this is a reference to an external symbol, we want |
12318 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12319 | add $tempreg,$tempreg,$gp | |
12320 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) | |
c0ebe874 | 12321 | <op> op[0],<ofst>($tempreg) |
f5040a92 AO |
12322 | Otherwise, for local symbols, we want: |
12323 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) | |
c0ebe874 | 12324 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
9c2799c2 | 12325 | gas_assert (offset_expr.X_op == O_symbol); |
4d7206a2 | 12326 | expr1.X_add_number = offset_expr.X_add_number; |
f5040a92 AO |
12327 | offset_expr.X_add_number = 0; |
12328 | if (expr1.X_add_number < -0x8000 | |
12329 | || expr1.X_add_number >= 0x8000) | |
12330 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
4d7206a2 | 12331 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12332 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
17a2f251 | 12333 | BFD_RELOC_MIPS_GOT_HI16); |
67c0d1eb RS |
12334 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
12335 | mips_gp_register); | |
12336 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, | |
12337 | BFD_RELOC_MIPS_GOT_LO16, tempreg); | |
f5040a92 | 12338 | if (breg != 0) |
67c0d1eb | 12339 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12340 | tempreg, tempreg, breg); |
c0ebe874 | 12341 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
684022ea | 12342 | |
4d7206a2 | 12343 | relax_switch (); |
f5040a92 | 12344 | offset_expr.X_add_number = expr1.X_add_number; |
67c0d1eb RS |
12345 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
12346 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); | |
f5040a92 | 12347 | if (breg != 0) |
67c0d1eb | 12348 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12349 | tempreg, tempreg, breg); |
c0ebe874 | 12350 | macro_build (&offset_expr, s, fmt, op[0], |
17a2f251 | 12351 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
4d7206a2 | 12352 | relax_end (); |
f5040a92 | 12353 | } |
252b5132 RH |
12354 | else |
12355 | abort (); | |
12356 | ||
252b5132 RH |
12357 | break; |
12358 | ||
833794fc MR |
12359 | case M_JRADDIUSP: |
12360 | gas_assert (mips_opts.micromips); | |
12361 | gas_assert (mips_opts.insn32); | |
12362 | start_noreorder (); | |
12363 | macro_build (NULL, "jr", "s", RA); | |
c0ebe874 | 12364 | expr1.X_add_number = op[0] << 2; |
833794fc MR |
12365 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
12366 | end_noreorder (); | |
12367 | break; | |
12368 | ||
12369 | case M_JRC: | |
12370 | gas_assert (mips_opts.micromips); | |
12371 | gas_assert (mips_opts.insn32); | |
c0ebe874 | 12372 | macro_build (NULL, "jr", "s", op[0]); |
833794fc MR |
12373 | if (mips_opts.noreorder) |
12374 | macro_build (NULL, "nop", ""); | |
12375 | break; | |
12376 | ||
252b5132 RH |
12377 | case M_LI: |
12378 | case M_LI_S: | |
c0ebe874 | 12379 | load_register (op[0], &imm_expr, 0); |
8fc2e39e | 12380 | break; |
252b5132 RH |
12381 | |
12382 | case M_DLI: | |
c0ebe874 | 12383 | load_register (op[0], &imm_expr, 1); |
8fc2e39e | 12384 | break; |
252b5132 RH |
12385 | |
12386 | case M_LI_SS: | |
12387 | if (imm_expr.X_op == O_constant) | |
12388 | { | |
8fc2e39e | 12389 | used_at = 1; |
67c0d1eb | 12390 | load_register (AT, &imm_expr, 0); |
c0ebe874 | 12391 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12392 | break; |
12393 | } | |
12394 | else | |
12395 | { | |
b0e6f033 RS |
12396 | gas_assert (imm_expr.X_op == O_absent |
12397 | && offset_expr.X_op == O_symbol | |
90ecf173 MR |
12398 | && strcmp (segment_name (S_GET_SEGMENT |
12399 | (offset_expr.X_add_symbol)), | |
12400 | ".lit4") == 0 | |
12401 | && offset_expr.X_add_number == 0); | |
c0ebe874 | 12402 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
17a2f251 | 12403 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
8fc2e39e | 12404 | break; |
252b5132 RH |
12405 | } |
12406 | ||
12407 | case M_LI_D: | |
ca4e0257 RS |
12408 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
12409 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high | |
12410 | order 32 bits of the value and the low order 32 bits are either | |
12411 | zero or in OFFSET_EXPR. */ | |
b0e6f033 | 12412 | if (imm_expr.X_op == O_constant) |
252b5132 | 12413 | { |
bad1aba3 | 12414 | if (GPR_SIZE == 64) |
c0ebe874 | 12415 | load_register (op[0], &imm_expr, 1); |
252b5132 RH |
12416 | else |
12417 | { | |
12418 | int hreg, lreg; | |
12419 | ||
12420 | if (target_big_endian) | |
12421 | { | |
c0ebe874 RS |
12422 | hreg = op[0]; |
12423 | lreg = op[0] + 1; | |
252b5132 RH |
12424 | } |
12425 | else | |
12426 | { | |
c0ebe874 RS |
12427 | hreg = op[0] + 1; |
12428 | lreg = op[0]; | |
252b5132 RH |
12429 | } |
12430 | ||
12431 | if (hreg <= 31) | |
67c0d1eb | 12432 | load_register (hreg, &imm_expr, 0); |
252b5132 RH |
12433 | if (lreg <= 31) |
12434 | { | |
12435 | if (offset_expr.X_op == O_absent) | |
67c0d1eb | 12436 | move_register (lreg, 0); |
252b5132 RH |
12437 | else |
12438 | { | |
9c2799c2 | 12439 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12440 | load_register (lreg, &offset_expr, 0); |
252b5132 RH |
12441 | } |
12442 | } | |
12443 | } | |
8fc2e39e | 12444 | break; |
252b5132 | 12445 | } |
b0e6f033 | 12446 | gas_assert (imm_expr.X_op == O_absent); |
252b5132 RH |
12447 | |
12448 | /* We know that sym is in the .rdata section. First we get the | |
12449 | upper 16 bits of the address. */ | |
12450 | if (mips_pic == NO_PIC) | |
12451 | { | |
67c0d1eb | 12452 | macro_build_lui (&offset_expr, AT); |
8fc2e39e | 12453 | used_at = 1; |
252b5132 | 12454 | } |
0a44bf69 | 12455 | else |
252b5132 | 12456 | { |
67c0d1eb RS |
12457 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12458 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
8fc2e39e | 12459 | used_at = 1; |
252b5132 | 12460 | } |
bdaaa2e1 | 12461 | |
252b5132 | 12462 | /* Now we load the register(s). */ |
bad1aba3 | 12463 | if (GPR_SIZE == 64) |
8fc2e39e TS |
12464 | { |
12465 | used_at = 1; | |
c0ebe874 RS |
12466 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
12467 | BFD_RELOC_LO16, AT); | |
8fc2e39e | 12468 | } |
252b5132 RH |
12469 | else |
12470 | { | |
8fc2e39e | 12471 | used_at = 1; |
c0ebe874 RS |
12472 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
12473 | BFD_RELOC_LO16, AT); | |
12474 | if (op[0] != RA) | |
252b5132 RH |
12475 | { |
12476 | /* FIXME: How in the world do we deal with the possible | |
12477 | overflow here? */ | |
12478 | offset_expr.X_add_number += 4; | |
67c0d1eb | 12479 | macro_build (&offset_expr, "lw", "t,o(b)", |
c0ebe874 | 12480 | op[0] + 1, BFD_RELOC_LO16, AT); |
252b5132 RH |
12481 | } |
12482 | } | |
252b5132 RH |
12483 | break; |
12484 | ||
12485 | case M_LI_DD: | |
ca4e0257 RS |
12486 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
12487 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 | |
12488 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of | |
12489 | the value and the low order 32 bits are either zero or in | |
12490 | OFFSET_EXPR. */ | |
b0e6f033 | 12491 | if (imm_expr.X_op == O_constant) |
252b5132 | 12492 | { |
8fc2e39e | 12493 | used_at = 1; |
bad1aba3 | 12494 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
351cdf24 MF |
12495 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
12496 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); | |
252b5132 RH |
12497 | else |
12498 | { | |
351cdf24 MF |
12499 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
12500 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); | |
12501 | else if (FPR_SIZE != 32) | |
12502 | as_bad (_("Unable to generate `%s' compliant code " | |
12503 | "without mthc1"), | |
12504 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); | |
12505 | else | |
12506 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); | |
252b5132 | 12507 | if (offset_expr.X_op == O_absent) |
c0ebe874 | 12508 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
252b5132 RH |
12509 | else |
12510 | { | |
9c2799c2 | 12511 | gas_assert (offset_expr.X_op == O_constant); |
67c0d1eb | 12512 | load_register (AT, &offset_expr, 0); |
c0ebe874 | 12513 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
252b5132 RH |
12514 | } |
12515 | } | |
12516 | break; | |
12517 | } | |
12518 | ||
b0e6f033 RS |
12519 | gas_assert (imm_expr.X_op == O_absent |
12520 | && offset_expr.X_op == O_symbol | |
90ecf173 | 12521 | && offset_expr.X_add_number == 0); |
252b5132 RH |
12522 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
12523 | if (strcmp (s, ".lit8") == 0) | |
134c0c8b MR |
12524 | { |
12525 | op[2] = mips_gp_register; | |
f2ae14a1 RS |
12526 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
12527 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12528 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
252b5132 RH |
12529 | } |
12530 | else | |
12531 | { | |
9c2799c2 | 12532 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
8fc2e39e | 12533 | used_at = 1; |
0a44bf69 | 12534 | if (mips_pic != NO_PIC) |
67c0d1eb RS |
12535 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
12536 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
252b5132 RH |
12537 | else |
12538 | { | |
12539 | /* FIXME: This won't work for a 64 bit address. */ | |
67c0d1eb | 12540 | macro_build_lui (&offset_expr, AT); |
252b5132 | 12541 | } |
bdaaa2e1 | 12542 | |
c0ebe874 | 12543 | op[2] = AT; |
f2ae14a1 RS |
12544 | offset_reloc[0] = BFD_RELOC_LO16; |
12545 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12546 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
134c0c8b | 12547 | } |
f2ae14a1 RS |
12548 | align = 8; |
12549 | /* Fall through */ | |
c4a68bea | 12550 | |
252b5132 RH |
12551 | case M_L_DAB: |
12552 | /* | |
12553 | * The MIPS assembler seems to check for X_add_number not | |
12554 | * being double aligned and generating: | |
12555 | * lui at,%hi(foo+1) | |
12556 | * addu at,at,v1 | |
12557 | * addiu at,at,%lo(foo+1) | |
12558 | * lwc1 f2,0(at) | |
12559 | * lwc1 f3,4(at) | |
12560 | * But, the resulting address is the same after relocation so why | |
12561 | * generate the extra instruction? | |
12562 | */ | |
bdaaa2e1 | 12563 | /* Itbl support may require additional care here. */ |
252b5132 | 12564 | coproc = 1; |
df58fc94 | 12565 | fmt = "T,o(b)"; |
0aa27725 | 12566 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12567 | { |
12568 | s = "ldc1"; | |
df58fc94 | 12569 | goto ld_st; |
252b5132 | 12570 | } |
252b5132 | 12571 | s = "lwc1"; |
252b5132 RH |
12572 | goto ldd_std; |
12573 | ||
12574 | case M_S_DAB: | |
df58fc94 RS |
12575 | gas_assert (!mips_opts.micromips); |
12576 | /* Itbl support may require additional care here. */ | |
12577 | coproc = 1; | |
12578 | fmt = "T,o(b)"; | |
0aa27725 | 12579 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
252b5132 RH |
12580 | { |
12581 | s = "sdc1"; | |
df58fc94 | 12582 | goto ld_st; |
252b5132 | 12583 | } |
252b5132 | 12584 | s = "swc1"; |
252b5132 RH |
12585 | goto ldd_std; |
12586 | ||
e407c74b NC |
12587 | case M_LQ_AB: |
12588 | fmt = "t,o(b)"; | |
12589 | s = "lq"; | |
12590 | goto ld; | |
12591 | ||
12592 | case M_SQ_AB: | |
12593 | fmt = "t,o(b)"; | |
12594 | s = "sq"; | |
12595 | goto ld_st; | |
12596 | ||
252b5132 | 12597 | case M_LD_AB: |
df58fc94 | 12598 | fmt = "t,o(b)"; |
bad1aba3 | 12599 | if (GPR_SIZE == 64) |
252b5132 RH |
12600 | { |
12601 | s = "ld"; | |
12602 | goto ld; | |
12603 | } | |
252b5132 | 12604 | s = "lw"; |
252b5132 RH |
12605 | goto ldd_std; |
12606 | ||
12607 | case M_SD_AB: | |
df58fc94 | 12608 | fmt = "t,o(b)"; |
bad1aba3 | 12609 | if (GPR_SIZE == 64) |
252b5132 RH |
12610 | { |
12611 | s = "sd"; | |
df58fc94 | 12612 | goto ld_st; |
252b5132 | 12613 | } |
252b5132 | 12614 | s = "sw"; |
252b5132 RH |
12615 | |
12616 | ldd_std: | |
f2ae14a1 RS |
12617 | /* Even on a big endian machine $fn comes before $fn+1. We have |
12618 | to adjust when loading from memory. We set coproc if we must | |
12619 | load $fn+1 first. */ | |
12620 | /* Itbl support may require additional care here. */ | |
12621 | if (!target_big_endian) | |
12622 | coproc = 0; | |
12623 | ||
c0ebe874 | 12624 | breg = op[2]; |
f2ae14a1 RS |
12625 | if (small_offset_p (0, align, 16)) |
12626 | { | |
12627 | ep = &offset_expr; | |
12628 | if (!small_offset_p (4, align, 16)) | |
12629 | { | |
12630 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, | |
12631 | -1, offset_reloc[0], offset_reloc[1], | |
12632 | offset_reloc[2]); | |
12633 | expr1.X_add_number = 0; | |
12634 | ep = &expr1; | |
12635 | breg = AT; | |
12636 | used_at = 1; | |
12637 | offset_reloc[0] = BFD_RELOC_LO16; | |
12638 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
12639 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
12640 | } | |
c0ebe874 | 12641 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
f2ae14a1 RS |
12642 | { |
12643 | ep->X_add_number += 4; | |
c0ebe874 | 12644 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
f2ae14a1 RS |
12645 | offset_reloc[1], offset_reloc[2], breg); |
12646 | ep->X_add_number -= 4; | |
c0ebe874 | 12647 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
f2ae14a1 RS |
12648 | offset_reloc[1], offset_reloc[2], breg); |
12649 | } | |
12650 | else | |
12651 | { | |
c0ebe874 | 12652 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
f2ae14a1 RS |
12653 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12654 | breg); | |
12655 | ep->X_add_number += 4; | |
c0ebe874 | 12656 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
f2ae14a1 RS |
12657 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
12658 | breg); | |
12659 | } | |
12660 | break; | |
12661 | } | |
12662 | ||
252b5132 RH |
12663 | if (offset_expr.X_op != O_symbol |
12664 | && offset_expr.X_op != O_constant) | |
12665 | { | |
1661c76c | 12666 | as_bad (_("expression too complex")); |
252b5132 RH |
12667 | offset_expr.X_op = O_constant; |
12668 | } | |
12669 | ||
2051e8c4 MR |
12670 | if (HAVE_32BIT_ADDRESSES |
12671 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) | |
55e08f71 NC |
12672 | { |
12673 | char value [32]; | |
12674 | ||
12675 | sprintf_vma (value, offset_expr.X_add_number); | |
1661c76c | 12676 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
55e08f71 | 12677 | } |
2051e8c4 | 12678 | |
90ecf173 | 12679 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
252b5132 RH |
12680 | { |
12681 | /* If this is a reference to a GP relative symbol, we want | |
c0ebe874 RS |
12682 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
12683 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12684 | If we have a base register, we use this |
12685 | addu $at,$breg,$gp | |
c0ebe874 RS |
12686 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
12687 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) | |
252b5132 RH |
12688 | If this is not a GP relative symbol, we want |
12689 | lui $at,<sym> (BFD_RELOC_HI16_S) | |
c0ebe874 RS |
12690 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12691 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12692 | If there is a base register, we add it to $at after the |
12693 | lui instruction. If there is a constant, we always use | |
12694 | the last case. */ | |
39a59cf8 MR |
12695 | if (offset_expr.X_op == O_symbol |
12696 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET | |
6caf9ef4 | 12697 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
252b5132 | 12698 | { |
4d7206a2 | 12699 | relax_start (offset_expr.X_add_symbol); |
252b5132 RH |
12700 | if (breg == 0) |
12701 | { | |
c9914766 | 12702 | tempreg = mips_gp_register; |
252b5132 RH |
12703 | } |
12704 | else | |
12705 | { | |
67c0d1eb | 12706 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
17a2f251 | 12707 | AT, breg, mips_gp_register); |
252b5132 | 12708 | tempreg = AT; |
252b5132 RH |
12709 | used_at = 1; |
12710 | } | |
12711 | ||
beae10d5 | 12712 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12713 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12714 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12715 | offset_expr.X_add_number += 4; |
12716 | ||
12717 | /* Set mips_optimize to 2 to avoid inserting an | |
12718 | undesired nop. */ | |
12719 | hold_mips_optimize = mips_optimize; | |
12720 | mips_optimize = 2; | |
beae10d5 | 12721 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12722 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12723 | BFD_RELOC_GPREL16, tempreg); |
252b5132 RH |
12724 | mips_optimize = hold_mips_optimize; |
12725 | ||
4d7206a2 | 12726 | relax_switch (); |
252b5132 | 12727 | |
0970e49e | 12728 | offset_expr.X_add_number -= 4; |
252b5132 | 12729 | } |
8fc2e39e | 12730 | used_at = 1; |
f2ae14a1 RS |
12731 | if (offset_high_part (offset_expr.X_add_number, 16) |
12732 | != offset_high_part (offset_expr.X_add_number + 4, 16)) | |
12733 | { | |
12734 | load_address (AT, &offset_expr, &used_at); | |
12735 | offset_expr.X_op = O_constant; | |
12736 | offset_expr.X_add_number = 0; | |
12737 | } | |
12738 | else | |
12739 | macro_build_lui (&offset_expr, AT); | |
252b5132 | 12740 | if (breg != 0) |
67c0d1eb | 12741 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12742 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12743 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12744 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12745 | /* FIXME: How do we handle overflow here? */ |
12746 | offset_expr.X_add_number += 4; | |
beae10d5 | 12747 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12748 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12749 | BFD_RELOC_LO16, AT); |
4d7206a2 RS |
12750 | if (mips_relax.sequence) |
12751 | relax_end (); | |
bdaaa2e1 | 12752 | } |
0a44bf69 | 12753 | else if (!mips_big_got) |
252b5132 | 12754 | { |
252b5132 RH |
12755 | /* If this is a reference to an external symbol, we want |
12756 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12757 | nop | |
c0ebe874 RS |
12758 | <op> op[0],0($at) |
12759 | <op> op[0]+1,4($at) | |
252b5132 RH |
12760 | Otherwise we want |
12761 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12762 | nop | |
c0ebe874 RS |
12763 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12764 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12765 | If there is a base register we add it to $at before the |
12766 | lwc1 instructions. If there is a constant we include it | |
12767 | in the lwc1 instructions. */ | |
12768 | used_at = 1; | |
12769 | expr1.X_add_number = offset_expr.X_add_number; | |
252b5132 RH |
12770 | if (expr1.X_add_number < -0x8000 |
12771 | || expr1.X_add_number >= 0x8000 - 4) | |
12772 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12773 | load_got_offset (AT, &offset_expr); |
269137b2 | 12774 | load_delay_nop (); |
252b5132 | 12775 | if (breg != 0) |
67c0d1eb | 12776 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
252b5132 RH |
12777 | |
12778 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12779 | nop. */ | |
12780 | hold_mips_optimize = mips_optimize; | |
12781 | mips_optimize = 2; | |
4d7206a2 | 12782 | |
beae10d5 | 12783 | /* Itbl support may require additional care here. */ |
4d7206a2 | 12784 | relax_start (offset_expr.X_add_symbol); |
c0ebe874 | 12785 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12786 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12787 | expr1.X_add_number += 4; |
c0ebe874 | 12788 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12789 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12790 | relax_switch (); |
c0ebe874 | 12791 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12792 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12793 | offset_expr.X_add_number += 4; |
c0ebe874 | 12794 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12795 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12796 | relax_end (); |
252b5132 | 12797 | |
4d7206a2 | 12798 | mips_optimize = hold_mips_optimize; |
252b5132 | 12799 | } |
0a44bf69 | 12800 | else if (mips_big_got) |
252b5132 | 12801 | { |
67c0d1eb | 12802 | int gpdelay; |
252b5132 RH |
12803 | |
12804 | /* If this is a reference to an external symbol, we want | |
12805 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) | |
12806 | addu $at,$at,$gp | |
12807 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) | |
12808 | nop | |
c0ebe874 RS |
12809 | <op> op[0],0($at) |
12810 | <op> op[0]+1,4($at) | |
252b5132 RH |
12811 | Otherwise we want |
12812 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) | |
12813 | nop | |
c0ebe874 RS |
12814 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
12815 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) | |
252b5132 RH |
12816 | If there is a base register we add it to $at before the |
12817 | lwc1 instructions. If there is a constant we include it | |
12818 | in the lwc1 instructions. */ | |
12819 | used_at = 1; | |
12820 | expr1.X_add_number = offset_expr.X_add_number; | |
12821 | offset_expr.X_add_number = 0; | |
12822 | if (expr1.X_add_number < -0x8000 | |
12823 | || expr1.X_add_number >= 0x8000 - 4) | |
12824 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); | |
67c0d1eb | 12825 | gpdelay = reg_needs_delay (mips_gp_register); |
4d7206a2 | 12826 | relax_start (offset_expr.X_add_symbol); |
df58fc94 | 12827 | macro_build (&offset_expr, "lui", LUI_FMT, |
67c0d1eb RS |
12828 | AT, BFD_RELOC_MIPS_GOT_HI16); |
12829 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
17a2f251 | 12830 | AT, AT, mips_gp_register); |
67c0d1eb | 12831 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
17a2f251 | 12832 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
269137b2 | 12833 | load_delay_nop (); |
252b5132 | 12834 | if (breg != 0) |
67c0d1eb | 12835 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12836 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12837 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
17a2f251 | 12838 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12839 | expr1.X_add_number += 4; |
12840 | ||
12841 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12842 | nop. */ | |
12843 | hold_mips_optimize = mips_optimize; | |
12844 | mips_optimize = 2; | |
beae10d5 | 12845 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12846 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
17a2f251 | 12847 | BFD_RELOC_LO16, AT); |
252b5132 RH |
12848 | mips_optimize = hold_mips_optimize; |
12849 | expr1.X_add_number -= 4; | |
12850 | ||
4d7206a2 RS |
12851 | relax_switch (); |
12852 | offset_expr.X_add_number = expr1.X_add_number; | |
67c0d1eb RS |
12853 | if (gpdelay) |
12854 | macro_build (NULL, "nop", ""); | |
12855 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, | |
12856 | BFD_RELOC_MIPS_GOT16, mips_gp_register); | |
269137b2 | 12857 | load_delay_nop (); |
252b5132 | 12858 | if (breg != 0) |
67c0d1eb | 12859 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
beae10d5 | 12860 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12861 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
67c0d1eb | 12862 | BFD_RELOC_LO16, AT); |
4d7206a2 | 12863 | offset_expr.X_add_number += 4; |
252b5132 RH |
12864 | |
12865 | /* Set mips_optimize to 2 to avoid inserting an undesired | |
12866 | nop. */ | |
12867 | hold_mips_optimize = mips_optimize; | |
12868 | mips_optimize = 2; | |
beae10d5 | 12869 | /* Itbl support may require additional care here. */ |
c0ebe874 | 12870 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
67c0d1eb | 12871 | BFD_RELOC_LO16, AT); |
252b5132 | 12872 | mips_optimize = hold_mips_optimize; |
4d7206a2 | 12873 | relax_end (); |
252b5132 | 12874 | } |
252b5132 RH |
12875 | else |
12876 | abort (); | |
12877 | ||
252b5132 | 12878 | break; |
3739860c | 12879 | |
dd6a37e7 | 12880 | case M_SAA_AB: |
dd6a37e7 | 12881 | s = "saa"; |
0db377d0 | 12882 | goto saa_saad; |
dd6a37e7 | 12883 | case M_SAAD_AB: |
dd6a37e7 | 12884 | s = "saad"; |
0db377d0 MR |
12885 | saa_saad: |
12886 | gas_assert (!mips_opts.micromips); | |
7f3c4072 | 12887 | offbits = 0; |
dd6a37e7 AP |
12888 | fmt = "t,(b)"; |
12889 | goto ld_st; | |
12890 | ||
252b5132 RH |
12891 | /* New code added to support COPZ instructions. |
12892 | This code builds table entries out of the macros in mip_opcodes. | |
12893 | R4000 uses interlocks to handle coproc delays. | |
12894 | Other chips (like the R3000) require nops to be inserted for delays. | |
12895 | ||
f72c8c98 | 12896 | FIXME: Currently, we require that the user handle delays. |
252b5132 RH |
12897 | In order to fill delay slots for non-interlocked chips, |
12898 | we must have a way to specify delays based on the coprocessor. | |
12899 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. | |
12900 | What are the side-effects of the cop instruction? | |
12901 | What cache support might we have and what are its effects? | |
12902 | Both coprocessor & memory require delays. how long??? | |
bdaaa2e1 | 12903 | What registers are read/set/modified? |
252b5132 RH |
12904 | |
12905 | If an itbl is provided to interpret cop instructions, | |
bdaaa2e1 | 12906 | this knowledge can be encoded in the itbl spec. */ |
252b5132 RH |
12907 | |
12908 | case M_COP0: | |
12909 | s = "c0"; | |
12910 | goto copz; | |
12911 | case M_COP1: | |
12912 | s = "c1"; | |
12913 | goto copz; | |
12914 | case M_COP2: | |
12915 | s = "c2"; | |
12916 | goto copz; | |
12917 | case M_COP3: | |
12918 | s = "c3"; | |
12919 | copz: | |
df58fc94 | 12920 | gas_assert (!mips_opts.micromips); |
252b5132 RH |
12921 | /* For now we just do C (same as Cz). The parameter will be |
12922 | stored in insn_opcode by mips_ip. */ | |
c8276761 | 12923 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
8fc2e39e | 12924 | break; |
252b5132 | 12925 | |
ea1fb5dc | 12926 | case M_MOVE: |
c0ebe874 | 12927 | move_register (op[0], op[1]); |
8fc2e39e | 12928 | break; |
ea1fb5dc | 12929 | |
833794fc MR |
12930 | case M_MOVEP: |
12931 | gas_assert (mips_opts.micromips); | |
12932 | gas_assert (mips_opts.insn32); | |
c0ebe874 RS |
12933 | move_register (micromips_to_32_reg_h_map1[op[0]], |
12934 | micromips_to_32_reg_m_map[op[1]]); | |
12935 | move_register (micromips_to_32_reg_h_map2[op[0]], | |
12936 | micromips_to_32_reg_n_map[op[2]]); | |
833794fc MR |
12937 | break; |
12938 | ||
252b5132 RH |
12939 | case M_DMUL: |
12940 | dbl = 1; | |
1a0670f3 | 12941 | /* Fall through. */ |
252b5132 | 12942 | case M_MUL: |
e407c74b | 12943 | if (mips_opts.arch == CPU_R5900) |
c0ebe874 RS |
12944 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
12945 | op[2]); | |
e407c74b NC |
12946 | else |
12947 | { | |
c0ebe874 RS |
12948 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
12949 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
e407c74b | 12950 | } |
8fc2e39e | 12951 | break; |
252b5132 RH |
12952 | |
12953 | case M_DMUL_I: | |
12954 | dbl = 1; | |
1a0670f3 | 12955 | /* Fall through. */ |
252b5132 RH |
12956 | case M_MUL_I: |
12957 | /* The MIPS assembler some times generates shifts and adds. I'm | |
12958 | not trying to be that fancy. GCC should do this for us | |
12959 | anyway. */ | |
8fc2e39e | 12960 | used_at = 1; |
67c0d1eb | 12961 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12962 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
12963 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
252b5132 RH |
12964 | break; |
12965 | ||
12966 | case M_DMULO_I: | |
12967 | dbl = 1; | |
1a0670f3 | 12968 | /* Fall through. */ |
252b5132 RH |
12969 | case M_MULO_I: |
12970 | imm = 1; | |
12971 | goto do_mulo; | |
12972 | ||
12973 | case M_DMULO: | |
12974 | dbl = 1; | |
1a0670f3 | 12975 | /* Fall through. */ |
252b5132 RH |
12976 | case M_MULO: |
12977 | do_mulo: | |
7d10b47d | 12978 | start_noreorder (); |
8fc2e39e | 12979 | used_at = 1; |
252b5132 | 12980 | if (imm) |
67c0d1eb | 12981 | load_register (AT, &imm_expr, dbl); |
c0ebe874 RS |
12982 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
12983 | op[1], imm ? AT : op[2]); | |
12984 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); | |
12985 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); | |
df58fc94 | 12986 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
252b5132 | 12987 | if (mips_trap) |
c0ebe874 | 12988 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
252b5132 RH |
12989 | else |
12990 | { | |
df58fc94 RS |
12991 | if (mips_opts.micromips) |
12992 | micromips_label_expr (&label_expr); | |
12993 | else | |
12994 | label_expr.X_add_number = 8; | |
c0ebe874 | 12995 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
a605d2b3 | 12996 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
12997 | macro_build (NULL, "break", BRK_FMT, 6); |
12998 | if (mips_opts.micromips) | |
12999 | micromips_add_label (); | |
252b5132 | 13000 | } |
7d10b47d | 13001 | end_noreorder (); |
c0ebe874 | 13002 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 RH |
13003 | break; |
13004 | ||
13005 | case M_DMULOU_I: | |
13006 | dbl = 1; | |
1a0670f3 | 13007 | /* Fall through. */ |
252b5132 RH |
13008 | case M_MULOU_I: |
13009 | imm = 1; | |
13010 | goto do_mulou; | |
13011 | ||
13012 | case M_DMULOU: | |
13013 | dbl = 1; | |
1a0670f3 | 13014 | /* Fall through. */ |
252b5132 RH |
13015 | case M_MULOU: |
13016 | do_mulou: | |
7d10b47d | 13017 | start_noreorder (); |
8fc2e39e | 13018 | used_at = 1; |
252b5132 | 13019 | if (imm) |
67c0d1eb RS |
13020 | load_register (AT, &imm_expr, dbl); |
13021 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", | |
c0ebe874 | 13022 | op[1], imm ? AT : op[2]); |
df58fc94 | 13023 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
c0ebe874 | 13024 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
252b5132 | 13025 | if (mips_trap) |
df58fc94 | 13026 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
252b5132 RH |
13027 | else |
13028 | { | |
df58fc94 RS |
13029 | if (mips_opts.micromips) |
13030 | micromips_label_expr (&label_expr); | |
13031 | else | |
13032 | label_expr.X_add_number = 8; | |
13033 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); | |
a605d2b3 | 13034 | macro_build (NULL, "nop", ""); |
df58fc94 RS |
13035 | macro_build (NULL, "break", BRK_FMT, 6); |
13036 | if (mips_opts.micromips) | |
13037 | micromips_add_label (); | |
252b5132 | 13038 | } |
7d10b47d | 13039 | end_noreorder (); |
252b5132 RH |
13040 | break; |
13041 | ||
771c7ce4 | 13042 | case M_DROL: |
fef14a42 | 13043 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13044 | { |
c0ebe874 | 13045 | if (op[0] == op[1]) |
82dd0097 CD |
13046 | { |
13047 | tempreg = AT; | |
13048 | used_at = 1; | |
13049 | } | |
13050 | else | |
c0ebe874 RS |
13051 | tempreg = op[0]; |
13052 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); | |
13053 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13054 | break; |
82dd0097 | 13055 | } |
8fc2e39e | 13056 | used_at = 1; |
c0ebe874 RS |
13057 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13058 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); | |
13059 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); | |
13060 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13061 | break; |
13062 | ||
252b5132 | 13063 | case M_ROL: |
fef14a42 | 13064 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13065 | { |
c0ebe874 | 13066 | if (op[0] == op[1]) |
82dd0097 CD |
13067 | { |
13068 | tempreg = AT; | |
13069 | used_at = 1; | |
13070 | } | |
13071 | else | |
c0ebe874 RS |
13072 | tempreg = op[0]; |
13073 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); | |
13074 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); | |
8fc2e39e | 13075 | break; |
82dd0097 | 13076 | } |
8fc2e39e | 13077 | used_at = 1; |
c0ebe874 RS |
13078 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13079 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); | |
13080 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); | |
13081 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13082 | break; |
13083 | ||
771c7ce4 TS |
13084 | case M_DROL_I: |
13085 | { | |
13086 | unsigned int rot; | |
e0471c16 TS |
13087 | const char *l; |
13088 | const char *rr; | |
771c7ce4 | 13089 | |
771c7ce4 | 13090 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13091 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
60b63b72 RS |
13092 | { |
13093 | rot = (64 - rot) & 0x3f; | |
13094 | if (rot >= 32) | |
c0ebe874 | 13095 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
60b63b72 | 13096 | else |
c0ebe874 | 13097 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13098 | break; |
60b63b72 | 13099 | } |
483fc7cd | 13100 | if (rot == 0) |
483fc7cd | 13101 | { |
c0ebe874 | 13102 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13103 | break; |
483fc7cd | 13104 | } |
82dd0097 | 13105 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
91d6fa6a | 13106 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 | 13107 | rot &= 0x1f; |
8fc2e39e | 13108 | used_at = 1; |
c0ebe874 RS |
13109 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
13110 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13111 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13112 | } |
13113 | break; | |
13114 | ||
252b5132 | 13115 | case M_ROL_I: |
771c7ce4 TS |
13116 | { |
13117 | unsigned int rot; | |
13118 | ||
771c7ce4 | 13119 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13120 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
60b63b72 | 13121 | { |
c0ebe874 RS |
13122 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
13123 | (32 - rot) & 0x1f); | |
8fc2e39e | 13124 | break; |
60b63b72 | 13125 | } |
483fc7cd | 13126 | if (rot == 0) |
483fc7cd | 13127 | { |
c0ebe874 | 13128 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13129 | break; |
483fc7cd | 13130 | } |
8fc2e39e | 13131 | used_at = 1; |
c0ebe874 RS |
13132 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
13133 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13134 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13135 | } |
13136 | break; | |
13137 | ||
13138 | case M_DROR: | |
fef14a42 | 13139 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 | 13140 | { |
c0ebe874 | 13141 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13142 | break; |
82dd0097 | 13143 | } |
8fc2e39e | 13144 | used_at = 1; |
c0ebe874 RS |
13145 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
13146 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); | |
13147 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); | |
13148 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13149 | break; |
13150 | ||
13151 | case M_ROR: | |
fef14a42 | 13152 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13153 | { |
c0ebe874 | 13154 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
8fc2e39e | 13155 | break; |
82dd0097 | 13156 | } |
8fc2e39e | 13157 | used_at = 1; |
c0ebe874 RS |
13158 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
13159 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); | |
13160 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); | |
13161 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
252b5132 RH |
13162 | break; |
13163 | ||
771c7ce4 TS |
13164 | case M_DROR_I: |
13165 | { | |
13166 | unsigned int rot; | |
e0471c16 TS |
13167 | const char *l; |
13168 | const char *rr; | |
771c7ce4 | 13169 | |
771c7ce4 | 13170 | rot = imm_expr.X_add_number & 0x3f; |
fef14a42 | 13171 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
82dd0097 CD |
13172 | { |
13173 | if (rot >= 32) | |
c0ebe874 | 13174 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
82dd0097 | 13175 | else |
c0ebe874 | 13176 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13177 | break; |
82dd0097 | 13178 | } |
483fc7cd | 13179 | if (rot == 0) |
483fc7cd | 13180 | { |
c0ebe874 | 13181 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13182 | break; |
483fc7cd | 13183 | } |
91d6fa6a | 13184 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
82dd0097 CD |
13185 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
13186 | rot &= 0x1f; | |
8fc2e39e | 13187 | used_at = 1; |
c0ebe874 RS |
13188 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
13189 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13190 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 TS |
13191 | } |
13192 | break; | |
13193 | ||
252b5132 | 13194 | case M_ROR_I: |
771c7ce4 TS |
13195 | { |
13196 | unsigned int rot; | |
13197 | ||
771c7ce4 | 13198 | rot = imm_expr.X_add_number & 0x1f; |
fef14a42 | 13199 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
82dd0097 | 13200 | { |
c0ebe874 | 13201 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
8fc2e39e | 13202 | break; |
82dd0097 | 13203 | } |
483fc7cd | 13204 | if (rot == 0) |
483fc7cd | 13205 | { |
c0ebe874 | 13206 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
8fc2e39e | 13207 | break; |
483fc7cd | 13208 | } |
8fc2e39e | 13209 | used_at = 1; |
c0ebe874 RS |
13210 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
13211 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); | |
13212 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); | |
771c7ce4 | 13213 | } |
252b5132 RH |
13214 | break; |
13215 | ||
252b5132 | 13216 | case M_SEQ: |
c0ebe874 RS |
13217 | if (op[1] == 0) |
13218 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); | |
13219 | else if (op[2] == 0) | |
13220 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13221 | else |
13222 | { | |
c0ebe874 RS |
13223 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13224 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 | 13225 | } |
8fc2e39e | 13226 | break; |
252b5132 RH |
13227 | |
13228 | case M_SEQ_I: | |
b0e6f033 | 13229 | if (imm_expr.X_add_number == 0) |
252b5132 | 13230 | { |
c0ebe874 | 13231 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13232 | break; |
252b5132 | 13233 | } |
c0ebe874 | 13234 | if (op[1] == 0) |
252b5132 | 13235 | { |
1661c76c | 13236 | as_warn (_("instruction %s: result is always false"), |
252b5132 | 13237 | ip->insn_mo->name); |
c0ebe874 | 13238 | move_register (op[0], 0); |
8fc2e39e | 13239 | break; |
252b5132 | 13240 | } |
dd3cbb7e NC |
13241 | if (CPU_HAS_SEQ (mips_opts.arch) |
13242 | && -512 <= imm_expr.X_add_number | |
13243 | && imm_expr.X_add_number < 512) | |
13244 | { | |
c0ebe874 | 13245 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
750bdd57 | 13246 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13247 | break; |
13248 | } | |
b0e6f033 | 13249 | if (imm_expr.X_add_number >= 0 |
252b5132 | 13250 | && imm_expr.X_add_number < 0x10000) |
c0ebe874 | 13251 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
b0e6f033 | 13252 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13253 | && imm_expr.X_add_number < 0) |
13254 | { | |
13255 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13256 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13257 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13258 | } |
dd3cbb7e NC |
13259 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13260 | { | |
13261 | used_at = 1; | |
bad1aba3 | 13262 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13263 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13264 | break; |
13265 | } | |
252b5132 RH |
13266 | else |
13267 | { | |
bad1aba3 | 13268 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13269 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13270 | used_at = 1; |
13271 | } | |
c0ebe874 | 13272 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13273 | break; |
252b5132 | 13274 | |
c0ebe874 | 13275 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
252b5132 RH |
13276 | s = "slt"; |
13277 | goto sge; | |
13278 | case M_SGEU: | |
13279 | s = "sltu"; | |
13280 | sge: | |
c0ebe874 RS |
13281 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
13282 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13283 | break; |
252b5132 | 13284 | |
c0ebe874 | 13285 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
252b5132 | 13286 | case M_SGEU_I: |
b0e6f033 | 13287 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 | 13288 | && imm_expr.X_add_number < 0x8000) |
c0ebe874 RS |
13289 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
13290 | op[0], op[1], BFD_RELOC_LO16); | |
252b5132 RH |
13291 | else |
13292 | { | |
bad1aba3 | 13293 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
67c0d1eb | 13294 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
c0ebe874 | 13295 | op[0], op[1], AT); |
252b5132 RH |
13296 | used_at = 1; |
13297 | } | |
c0ebe874 | 13298 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
8fc2e39e | 13299 | break; |
252b5132 | 13300 | |
c0ebe874 | 13301 | case M_SGT: /* X > Y <==> Y < X */ |
252b5132 RH |
13302 | s = "slt"; |
13303 | goto sgt; | |
13304 | case M_SGTU: | |
13305 | s = "sltu"; | |
13306 | sgt: | |
c0ebe874 | 13307 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
8fc2e39e | 13308 | break; |
252b5132 | 13309 | |
c0ebe874 | 13310 | case M_SGT_I: /* X > I <==> I < X */ |
252b5132 RH |
13311 | s = "slt"; |
13312 | goto sgti; | |
13313 | case M_SGTU_I: | |
13314 | s = "sltu"; | |
13315 | sgti: | |
8fc2e39e | 13316 | used_at = 1; |
bad1aba3 | 13317 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13318 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
252b5132 RH |
13319 | break; |
13320 | ||
c0ebe874 | 13321 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
252b5132 RH |
13322 | s = "slt"; |
13323 | goto sle; | |
13324 | case M_SLEU: | |
13325 | s = "sltu"; | |
13326 | sle: | |
c0ebe874 RS |
13327 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
13328 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
8fc2e39e | 13329 | break; |
252b5132 | 13330 | |
c0ebe874 | 13331 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
252b5132 RH |
13332 | s = "slt"; |
13333 | goto slei; | |
13334 | case M_SLEU_I: | |
13335 | s = "sltu"; | |
13336 | slei: | |
8fc2e39e | 13337 | used_at = 1; |
bad1aba3 | 13338 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 RS |
13339 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
13340 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); | |
252b5132 RH |
13341 | break; |
13342 | ||
13343 | case M_SLT_I: | |
b0e6f033 | 13344 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13345 | && imm_expr.X_add_number < 0x8000) |
13346 | { | |
c0ebe874 RS |
13347 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
13348 | BFD_RELOC_LO16); | |
8fc2e39e | 13349 | break; |
252b5132 | 13350 | } |
8fc2e39e | 13351 | used_at = 1; |
bad1aba3 | 13352 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13353 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13354 | break; |
13355 | ||
13356 | case M_SLTU_I: | |
b0e6f033 | 13357 | if (imm_expr.X_add_number >= -0x8000 |
252b5132 RH |
13358 | && imm_expr.X_add_number < 0x8000) |
13359 | { | |
c0ebe874 | 13360 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
17a2f251 | 13361 | BFD_RELOC_LO16); |
8fc2e39e | 13362 | break; |
252b5132 | 13363 | } |
8fc2e39e | 13364 | used_at = 1; |
bad1aba3 | 13365 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13366 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13367 | break; |
13368 | ||
13369 | case M_SNE: | |
c0ebe874 RS |
13370 | if (op[1] == 0) |
13371 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); | |
13372 | else if (op[2] == 0) | |
13373 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); | |
252b5132 RH |
13374 | else |
13375 | { | |
c0ebe874 RS |
13376 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
13377 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); | |
252b5132 | 13378 | } |
8fc2e39e | 13379 | break; |
252b5132 RH |
13380 | |
13381 | case M_SNE_I: | |
b0e6f033 | 13382 | if (imm_expr.X_add_number == 0) |
252b5132 | 13383 | { |
c0ebe874 | 13384 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
8fc2e39e | 13385 | break; |
252b5132 | 13386 | } |
c0ebe874 | 13387 | if (op[1] == 0) |
252b5132 | 13388 | { |
1661c76c | 13389 | as_warn (_("instruction %s: result is always true"), |
252b5132 | 13390 | ip->insn_mo->name); |
bad1aba3 | 13391 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
c0ebe874 | 13392 | op[0], 0, BFD_RELOC_LO16); |
8fc2e39e | 13393 | break; |
252b5132 | 13394 | } |
dd3cbb7e NC |
13395 | if (CPU_HAS_SEQ (mips_opts.arch) |
13396 | && -512 <= imm_expr.X_add_number | |
13397 | && imm_expr.X_add_number < 512) | |
13398 | { | |
c0ebe874 | 13399 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
750bdd57 | 13400 | (int) imm_expr.X_add_number); |
dd3cbb7e NC |
13401 | break; |
13402 | } | |
b0e6f033 | 13403 | if (imm_expr.X_add_number >= 0 |
252b5132 RH |
13404 | && imm_expr.X_add_number < 0x10000) |
13405 | { | |
c0ebe874 RS |
13406 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
13407 | BFD_RELOC_LO16); | |
252b5132 | 13408 | } |
b0e6f033 | 13409 | else if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13410 | && imm_expr.X_add_number < 0) |
13411 | { | |
13412 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
bad1aba3 | 13413 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
c0ebe874 | 13414 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
252b5132 | 13415 | } |
dd3cbb7e NC |
13416 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
13417 | { | |
13418 | used_at = 1; | |
bad1aba3 | 13419 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13420 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
dd3cbb7e NC |
13421 | break; |
13422 | } | |
252b5132 RH |
13423 | else |
13424 | { | |
bad1aba3 | 13425 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13426 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13427 | used_at = 1; |
13428 | } | |
c0ebe874 | 13429 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
8fc2e39e | 13430 | break; |
252b5132 | 13431 | |
df58fc94 RS |
13432 | case M_SUB_I: |
13433 | s = "addi"; | |
13434 | s2 = "sub"; | |
13435 | goto do_subi; | |
13436 | case M_SUBU_I: | |
13437 | s = "addiu"; | |
13438 | s2 = "subu"; | |
13439 | goto do_subi; | |
252b5132 RH |
13440 | case M_DSUB_I: |
13441 | dbl = 1; | |
df58fc94 RS |
13442 | s = "daddi"; |
13443 | s2 = "dsub"; | |
13444 | if (!mips_opts.micromips) | |
13445 | goto do_subi; | |
b0e6f033 | 13446 | if (imm_expr.X_add_number > -0x200 |
df58fc94 | 13447 | && imm_expr.X_add_number <= 0x200) |
252b5132 | 13448 | { |
b0e6f033 RS |
13449 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
13450 | (int) -imm_expr.X_add_number); | |
8fc2e39e | 13451 | break; |
252b5132 | 13452 | } |
df58fc94 | 13453 | goto do_subi_i; |
252b5132 RH |
13454 | case M_DSUBU_I: |
13455 | dbl = 1; | |
df58fc94 RS |
13456 | s = "daddiu"; |
13457 | s2 = "dsubu"; | |
13458 | do_subi: | |
b0e6f033 | 13459 | if (imm_expr.X_add_number > -0x8000 |
252b5132 RH |
13460 | && imm_expr.X_add_number <= 0x8000) |
13461 | { | |
13462 | imm_expr.X_add_number = -imm_expr.X_add_number; | |
c0ebe874 | 13463 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
8fc2e39e | 13464 | break; |
252b5132 | 13465 | } |
df58fc94 | 13466 | do_subi_i: |
8fc2e39e | 13467 | used_at = 1; |
67c0d1eb | 13468 | load_register (AT, &imm_expr, dbl); |
c0ebe874 | 13469 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
252b5132 RH |
13470 | break; |
13471 | ||
13472 | case M_TEQ_I: | |
13473 | s = "teq"; | |
13474 | goto trap; | |
13475 | case M_TGE_I: | |
13476 | s = "tge"; | |
13477 | goto trap; | |
13478 | case M_TGEU_I: | |
13479 | s = "tgeu"; | |
13480 | goto trap; | |
13481 | case M_TLT_I: | |
13482 | s = "tlt"; | |
13483 | goto trap; | |
13484 | case M_TLTU_I: | |
13485 | s = "tltu"; | |
13486 | goto trap; | |
13487 | case M_TNE_I: | |
13488 | s = "tne"; | |
13489 | trap: | |
8fc2e39e | 13490 | used_at = 1; |
bad1aba3 | 13491 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
c0ebe874 | 13492 | macro_build (NULL, s, "s,t", op[0], AT); |
252b5132 RH |
13493 | break; |
13494 | ||
252b5132 | 13495 | case M_TRUNCWS: |
43841e91 | 13496 | case M_TRUNCWD: |
df58fc94 | 13497 | gas_assert (!mips_opts.micromips); |
0aa27725 | 13498 | gas_assert (mips_opts.isa == ISA_MIPS1); |
8fc2e39e | 13499 | used_at = 1; |
252b5132 RH |
13500 | |
13501 | /* | |
13502 | * Is the double cfc1 instruction a bug in the mips assembler; | |
13503 | * or is there a reason for it? | |
13504 | */ | |
7d10b47d | 13505 | start_noreorder (); |
c0ebe874 RS |
13506 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
13507 | macro_build (NULL, "cfc1", "t,G", op[2], RA); | |
67c0d1eb | 13508 | macro_build (NULL, "nop", ""); |
252b5132 | 13509 | expr1.X_add_number = 3; |
c0ebe874 | 13510 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
252b5132 | 13511 | expr1.X_add_number = 2; |
67c0d1eb RS |
13512 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
13513 | macro_build (NULL, "ctc1", "t,G", AT, RA); | |
13514 | macro_build (NULL, "nop", ""); | |
13515 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", | |
c0ebe874 RS |
13516 | op[0], op[1]); |
13517 | macro_build (NULL, "ctc1", "t,G", op[2], RA); | |
67c0d1eb | 13518 | macro_build (NULL, "nop", ""); |
7d10b47d | 13519 | end_noreorder (); |
252b5132 RH |
13520 | break; |
13521 | ||
f2ae14a1 | 13522 | case M_ULH_AB: |
252b5132 | 13523 | s = "lb"; |
df58fc94 RS |
13524 | s2 = "lbu"; |
13525 | off = 1; | |
13526 | goto uld_st; | |
f2ae14a1 | 13527 | case M_ULHU_AB: |
252b5132 | 13528 | s = "lbu"; |
df58fc94 RS |
13529 | s2 = "lbu"; |
13530 | off = 1; | |
13531 | goto uld_st; | |
f2ae14a1 | 13532 | case M_ULW_AB: |
df58fc94 RS |
13533 | s = "lwl"; |
13534 | s2 = "lwr"; | |
7f3c4072 | 13535 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13536 | off = 3; |
13537 | goto uld_st; | |
f2ae14a1 | 13538 | case M_ULD_AB: |
252b5132 RH |
13539 | s = "ldl"; |
13540 | s2 = "ldr"; | |
7f3c4072 | 13541 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13542 | off = 7; |
df58fc94 | 13543 | goto uld_st; |
f2ae14a1 | 13544 | case M_USH_AB: |
df58fc94 RS |
13545 | s = "sb"; |
13546 | s2 = "sb"; | |
13547 | off = 1; | |
13548 | ust = 1; | |
13549 | goto uld_st; | |
f2ae14a1 | 13550 | case M_USW_AB: |
df58fc94 RS |
13551 | s = "swl"; |
13552 | s2 = "swr"; | |
7f3c4072 | 13553 | offbits = (mips_opts.micromips ? 12 : 16); |
252b5132 | 13554 | off = 3; |
df58fc94 RS |
13555 | ust = 1; |
13556 | goto uld_st; | |
f2ae14a1 | 13557 | case M_USD_AB: |
df58fc94 RS |
13558 | s = "sdl"; |
13559 | s2 = "sdr"; | |
7f3c4072 | 13560 | offbits = (mips_opts.micromips ? 12 : 16); |
df58fc94 RS |
13561 | off = 7; |
13562 | ust = 1; | |
13563 | ||
13564 | uld_st: | |
c0ebe874 | 13565 | breg = op[2]; |
f2ae14a1 | 13566 | large_offset = !small_offset_p (off, align, offbits); |
df58fc94 RS |
13567 | ep = &offset_expr; |
13568 | expr1.X_add_number = 0; | |
f2ae14a1 | 13569 | if (large_offset) |
df58fc94 RS |
13570 | { |
13571 | used_at = 1; | |
13572 | tempreg = AT; | |
f2ae14a1 RS |
13573 | if (small_offset_p (0, align, 16)) |
13574 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, | |
13575 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); | |
13576 | else | |
13577 | { | |
13578 | load_address (tempreg, ep, &used_at); | |
13579 | if (breg != 0) | |
13580 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", | |
13581 | tempreg, tempreg, breg); | |
13582 | } | |
13583 | offset_reloc[0] = BFD_RELOC_LO16; | |
13584 | offset_reloc[1] = BFD_RELOC_UNUSED; | |
13585 | offset_reloc[2] = BFD_RELOC_UNUSED; | |
df58fc94 | 13586 | breg = tempreg; |
c0ebe874 | 13587 | tempreg = op[0]; |
df58fc94 RS |
13588 | ep = &expr1; |
13589 | } | |
c0ebe874 | 13590 | else if (!ust && op[0] == breg) |
8fc2e39e TS |
13591 | { |
13592 | used_at = 1; | |
13593 | tempreg = AT; | |
13594 | } | |
252b5132 | 13595 | else |
c0ebe874 | 13596 | tempreg = op[0]; |
af22f5b2 | 13597 | |
df58fc94 RS |
13598 | if (off == 1) |
13599 | goto ulh_sh; | |
252b5132 | 13600 | |
90ecf173 | 13601 | if (!target_big_endian) |
df58fc94 | 13602 | ep->X_add_number += off; |
f2ae14a1 | 13603 | if (offbits == 12) |
c8276761 | 13604 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13605 | else |
13606 | macro_build (ep, s, "t,o(b)", tempreg, -1, | |
13607 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 | 13608 | |
90ecf173 | 13609 | if (!target_big_endian) |
df58fc94 | 13610 | ep->X_add_number -= off; |
252b5132 | 13611 | else |
df58fc94 | 13612 | ep->X_add_number += off; |
f2ae14a1 | 13613 | if (offbits == 12) |
df58fc94 | 13614 | macro_build (NULL, s2, "t,~(b)", |
c8276761 | 13615 | tempreg, (int) ep->X_add_number, breg); |
f2ae14a1 RS |
13616 | else |
13617 | macro_build (ep, s2, "t,o(b)", tempreg, -1, | |
13618 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13619 | |
df58fc94 | 13620 | /* If necessary, move the result in tempreg to the final destination. */ |
c0ebe874 | 13621 | if (!ust && op[0] != tempreg) |
df58fc94 RS |
13622 | { |
13623 | /* Protect second load's delay slot. */ | |
13624 | load_delay_nop (); | |
c0ebe874 | 13625 | move_register (op[0], tempreg); |
df58fc94 | 13626 | } |
8fc2e39e | 13627 | break; |
252b5132 | 13628 | |
df58fc94 | 13629 | ulh_sh: |
d6bc6245 | 13630 | used_at = 1; |
df58fc94 RS |
13631 | if (target_big_endian == ust) |
13632 | ep->X_add_number += off; | |
c0ebe874 | 13633 | tempreg = ust || large_offset ? op[0] : AT; |
f2ae14a1 RS |
13634 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
13635 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
df58fc94 RS |
13636 | |
13637 | /* For halfword transfers we need a temporary register to shuffle | |
13638 | bytes. Unfortunately for M_USH_A we have none available before | |
13639 | the next store as AT holds the base address. We deal with this | |
13640 | case by clobbering TREG and then restoring it as with ULH. */ | |
c0ebe874 | 13641 | tempreg = ust == large_offset ? op[0] : AT; |
df58fc94 | 13642 | if (ust) |
c0ebe874 | 13643 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
df58fc94 RS |
13644 | |
13645 | if (target_big_endian == ust) | |
13646 | ep->X_add_number -= off; | |
252b5132 | 13647 | else |
df58fc94 | 13648 | ep->X_add_number += off; |
f2ae14a1 RS |
13649 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
13650 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); | |
252b5132 | 13651 | |
df58fc94 | 13652 | /* For M_USH_A re-retrieve the LSB. */ |
f2ae14a1 | 13653 | if (ust && large_offset) |
df58fc94 RS |
13654 | { |
13655 | if (target_big_endian) | |
13656 | ep->X_add_number += off; | |
13657 | else | |
13658 | ep->X_add_number -= off; | |
f2ae14a1 RS |
13659 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
13660 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); | |
df58fc94 RS |
13661 | } |
13662 | /* For ULH and M_USH_A OR the LSB in. */ | |
f2ae14a1 | 13663 | if (!ust || large_offset) |
df58fc94 | 13664 | { |
c0ebe874 | 13665 | tempreg = !large_offset ? AT : op[0]; |
df58fc94 | 13666 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
c0ebe874 | 13667 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
df58fc94 | 13668 | } |
252b5132 RH |
13669 | break; |
13670 | ||
13671 | default: | |
13672 | /* FIXME: Check if this is one of the itbl macros, since they | |
bdaaa2e1 | 13673 | are added dynamically. */ |
1661c76c | 13674 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
252b5132 RH |
13675 | break; |
13676 | } | |
741fe287 | 13677 | if (!mips_opts.at && used_at) |
1661c76c | 13678 | as_bad (_("macro used $at after \".set noat\"")); |
252b5132 RH |
13679 | } |
13680 | ||
13681 | /* Implement macros in mips16 mode. */ | |
13682 | ||
13683 | static void | |
17a2f251 | 13684 | mips16_macro (struct mips_cl_insn *ip) |
252b5132 | 13685 | { |
c0ebe874 | 13686 | const struct mips_operand_array *operands; |
252b5132 | 13687 | int mask; |
c0ebe874 | 13688 | int tmp; |
252b5132 RH |
13689 | expressionS expr1; |
13690 | int dbl; | |
13691 | const char *s, *s2, *s3; | |
c0ebe874 RS |
13692 | unsigned int op[MAX_OPERANDS]; |
13693 | unsigned int i; | |
252b5132 RH |
13694 | |
13695 | mask = ip->insn_mo->mask; | |
13696 | ||
c0ebe874 RS |
13697 | operands = insn_operands (ip); |
13698 | for (i = 0; i < MAX_OPERANDS; i++) | |
13699 | if (operands->operand[i]) | |
13700 | op[i] = insn_extract_operand (ip, operands->operand[i]); | |
13701 | else | |
13702 | op[i] = -1; | |
252b5132 | 13703 | |
252b5132 RH |
13704 | expr1.X_op = O_constant; |
13705 | expr1.X_op_symbol = NULL; | |
13706 | expr1.X_add_symbol = NULL; | |
13707 | expr1.X_add_number = 1; | |
13708 | ||
13709 | dbl = 0; | |
13710 | ||
13711 | switch (mask) | |
13712 | { | |
13713 | default: | |
b37df7c4 | 13714 | abort (); |
252b5132 RH |
13715 | |
13716 | case M_DDIV_3: | |
13717 | dbl = 1; | |
1a0670f3 | 13718 | /* Fall through. */ |
252b5132 RH |
13719 | case M_DIV_3: |
13720 | s = "mflo"; | |
13721 | goto do_div3; | |
13722 | case M_DREM_3: | |
13723 | dbl = 1; | |
1a0670f3 | 13724 | /* Fall through. */ |
252b5132 RH |
13725 | case M_REM_3: |
13726 | s = "mfhi"; | |
13727 | do_div3: | |
7d10b47d | 13728 | start_noreorder (); |
d8722d76 | 13729 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
252b5132 | 13730 | expr1.X_add_number = 2; |
c0ebe874 | 13731 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13732 | macro_build (NULL, "break", "6", 7); |
bdaaa2e1 | 13733 | |
252b5132 RH |
13734 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
13735 | since that causes an overflow. We should do that as well, | |
13736 | but I don't see how to do the comparisons without a temporary | |
13737 | register. */ | |
7d10b47d | 13738 | end_noreorder (); |
c0ebe874 | 13739 | macro_build (NULL, s, "x", op[0]); |
252b5132 RH |
13740 | break; |
13741 | ||
13742 | case M_DIVU_3: | |
13743 | s = "divu"; | |
13744 | s2 = "mflo"; | |
13745 | goto do_divu3; | |
13746 | case M_REMU_3: | |
13747 | s = "divu"; | |
13748 | s2 = "mfhi"; | |
13749 | goto do_divu3; | |
13750 | case M_DDIVU_3: | |
13751 | s = "ddivu"; | |
13752 | s2 = "mflo"; | |
13753 | goto do_divu3; | |
13754 | case M_DREMU_3: | |
13755 | s = "ddivu"; | |
13756 | s2 = "mfhi"; | |
13757 | do_divu3: | |
7d10b47d | 13758 | start_noreorder (); |
d8722d76 | 13759 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
252b5132 | 13760 | expr1.X_add_number = 2; |
c0ebe874 | 13761 | macro_build (&expr1, "bnez", "x,p", op[2]); |
67c0d1eb | 13762 | macro_build (NULL, "break", "6", 7); |
7d10b47d | 13763 | end_noreorder (); |
c0ebe874 | 13764 | macro_build (NULL, s2, "x", op[0]); |
252b5132 RH |
13765 | break; |
13766 | ||
13767 | case M_DMUL: | |
13768 | dbl = 1; | |
1a0670f3 | 13769 | /* Fall through. */ |
252b5132 | 13770 | case M_MUL: |
c0ebe874 RS |
13771 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
13772 | macro_build (NULL, "mflo", "x", op[0]); | |
8fc2e39e | 13773 | break; |
252b5132 RH |
13774 | |
13775 | case M_DSUBU_I: | |
13776 | dbl = 1; | |
13777 | goto do_subu; | |
13778 | case M_SUBU_I: | |
13779 | do_subu: | |
252b5132 | 13780 | imm_expr.X_add_number = -imm_expr.X_add_number; |
d8722d76 | 13781 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
252b5132 RH |
13782 | break; |
13783 | ||
13784 | case M_SUBU_I_2: | |
252b5132 | 13785 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13786 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
252b5132 RH |
13787 | break; |
13788 | ||
13789 | case M_DSUBU_I_2: | |
252b5132 | 13790 | imm_expr.X_add_number = -imm_expr.X_add_number; |
c0ebe874 | 13791 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
252b5132 RH |
13792 | break; |
13793 | ||
13794 | case M_BEQ: | |
13795 | s = "cmp"; | |
13796 | s2 = "bteqz"; | |
13797 | goto do_branch; | |
13798 | case M_BNE: | |
13799 | s = "cmp"; | |
13800 | s2 = "btnez"; | |
13801 | goto do_branch; | |
13802 | case M_BLT: | |
13803 | s = "slt"; | |
13804 | s2 = "btnez"; | |
13805 | goto do_branch; | |
13806 | case M_BLTU: | |
13807 | s = "sltu"; | |
13808 | s2 = "btnez"; | |
13809 | goto do_branch; | |
13810 | case M_BLE: | |
13811 | s = "slt"; | |
13812 | s2 = "bteqz"; | |
13813 | goto do_reverse_branch; | |
13814 | case M_BLEU: | |
13815 | s = "sltu"; | |
13816 | s2 = "bteqz"; | |
13817 | goto do_reverse_branch; | |
13818 | case M_BGE: | |
13819 | s = "slt"; | |
13820 | s2 = "bteqz"; | |
13821 | goto do_branch; | |
13822 | case M_BGEU: | |
13823 | s = "sltu"; | |
13824 | s2 = "bteqz"; | |
13825 | goto do_branch; | |
13826 | case M_BGT: | |
13827 | s = "slt"; | |
13828 | s2 = "btnez"; | |
13829 | goto do_reverse_branch; | |
13830 | case M_BGTU: | |
13831 | s = "sltu"; | |
13832 | s2 = "btnez"; | |
13833 | ||
13834 | do_reverse_branch: | |
c0ebe874 RS |
13835 | tmp = op[1]; |
13836 | op[1] = op[0]; | |
13837 | op[0] = tmp; | |
252b5132 RH |
13838 | |
13839 | do_branch: | |
c0ebe874 | 13840 | macro_build (NULL, s, "x,y", op[0], op[1]); |
67c0d1eb | 13841 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13842 | break; |
13843 | ||
13844 | case M_BEQ_I: | |
13845 | s = "cmpi"; | |
13846 | s2 = "bteqz"; | |
13847 | s3 = "x,U"; | |
13848 | goto do_branch_i; | |
13849 | case M_BNE_I: | |
13850 | s = "cmpi"; | |
13851 | s2 = "btnez"; | |
13852 | s3 = "x,U"; | |
13853 | goto do_branch_i; | |
13854 | case M_BLT_I: | |
13855 | s = "slti"; | |
13856 | s2 = "btnez"; | |
13857 | s3 = "x,8"; | |
13858 | goto do_branch_i; | |
13859 | case M_BLTU_I: | |
13860 | s = "sltiu"; | |
13861 | s2 = "btnez"; | |
13862 | s3 = "x,8"; | |
13863 | goto do_branch_i; | |
13864 | case M_BLE_I: | |
13865 | s = "slti"; | |
13866 | s2 = "btnez"; | |
13867 | s3 = "x,8"; | |
13868 | goto do_addone_branch_i; | |
13869 | case M_BLEU_I: | |
13870 | s = "sltiu"; | |
13871 | s2 = "btnez"; | |
13872 | s3 = "x,8"; | |
13873 | goto do_addone_branch_i; | |
13874 | case M_BGE_I: | |
13875 | s = "slti"; | |
13876 | s2 = "bteqz"; | |
13877 | s3 = "x,8"; | |
13878 | goto do_branch_i; | |
13879 | case M_BGEU_I: | |
13880 | s = "sltiu"; | |
13881 | s2 = "bteqz"; | |
13882 | s3 = "x,8"; | |
13883 | goto do_branch_i; | |
13884 | case M_BGT_I: | |
13885 | s = "slti"; | |
13886 | s2 = "bteqz"; | |
13887 | s3 = "x,8"; | |
13888 | goto do_addone_branch_i; | |
13889 | case M_BGTU_I: | |
13890 | s = "sltiu"; | |
13891 | s2 = "bteqz"; | |
13892 | s3 = "x,8"; | |
13893 | ||
13894 | do_addone_branch_i: | |
252b5132 RH |
13895 | ++imm_expr.X_add_number; |
13896 | ||
13897 | do_branch_i: | |
c0ebe874 | 13898 | macro_build (&imm_expr, s, s3, op[0]); |
67c0d1eb | 13899 | macro_build (&offset_expr, s2, "p"); |
252b5132 RH |
13900 | break; |
13901 | ||
13902 | case M_ABS: | |
13903 | expr1.X_add_number = 0; | |
c0ebe874 RS |
13904 | macro_build (&expr1, "slti", "x,8", op[1]); |
13905 | if (op[0] != op[1]) | |
13906 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); | |
252b5132 | 13907 | expr1.X_add_number = 2; |
67c0d1eb | 13908 | macro_build (&expr1, "bteqz", "p"); |
c0ebe874 | 13909 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
0acfaea6 | 13910 | break; |
252b5132 RH |
13911 | } |
13912 | } | |
13913 | ||
14daeee3 RS |
13914 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
13915 | opcode bits in *OPCODE_EXTRA. */ | |
13916 | ||
13917 | static struct mips_opcode * | |
13918 | mips_lookup_insn (struct hash_control *hash, const char *start, | |
da8bca91 | 13919 | ssize_t length, unsigned int *opcode_extra) |
14daeee3 RS |
13920 | { |
13921 | char *name, *dot, *p; | |
13922 | unsigned int mask, suffix; | |
da8bca91 | 13923 | ssize_t opend; |
14daeee3 RS |
13924 | struct mips_opcode *insn; |
13925 | ||
13926 | /* Make a copy of the instruction so that we can fiddle with it. */ | |
4ec9d7d5 | 13927 | name = xstrndup (start, length); |
14daeee3 RS |
13928 | |
13929 | /* Look up the instruction as-is. */ | |
13930 | insn = (struct mips_opcode *) hash_find (hash, name); | |
ee5734f0 | 13931 | if (insn) |
e1fa0163 | 13932 | goto end; |
14daeee3 RS |
13933 | |
13934 | dot = strchr (name, '.'); | |
13935 | if (dot && dot[1]) | |
13936 | { | |
13937 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ | |
13938 | p = mips_parse_vu0_channels (dot + 1, &mask); | |
13939 | if (*p == 0 && mask != 0) | |
13940 | { | |
13941 | *dot = 0; | |
13942 | insn = (struct mips_opcode *) hash_find (hash, name); | |
13943 | *dot = '.'; | |
13944 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) | |
13945 | { | |
13946 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; | |
e1fa0163 | 13947 | goto end; |
14daeee3 RS |
13948 | } |
13949 | } | |
13950 | } | |
13951 | ||
13952 | if (mips_opts.micromips) | |
13953 | { | |
13954 | /* See if there's an instruction size override suffix, | |
13955 | either `16' or `32', at the end of the mnemonic proper, | |
13956 | that defines the operation, i.e. before the first `.' | |
13957 | character if any. Strip it and retry. */ | |
13958 | opend = dot != NULL ? dot - name : length; | |
13959 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') | |
13960 | suffix = 2; | |
13961 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') | |
13962 | suffix = 4; | |
13963 | else | |
13964 | suffix = 0; | |
13965 | if (suffix) | |
13966 | { | |
39334a61 | 13967 | memmove (name + opend - 2, name + opend, length - opend + 1); |
14daeee3 | 13968 | insn = (struct mips_opcode *) hash_find (hash, name); |
ee5734f0 | 13969 | if (insn) |
14daeee3 RS |
13970 | { |
13971 | forced_insn_length = suffix; | |
e1fa0163 | 13972 | goto end; |
14daeee3 RS |
13973 | } |
13974 | } | |
13975 | } | |
13976 | ||
e1fa0163 NC |
13977 | insn = NULL; |
13978 | end: | |
13979 | free (name); | |
13980 | return insn; | |
14daeee3 RS |
13981 | } |
13982 | ||
77bd4346 | 13983 | /* Assemble an instruction into its binary format. If the instruction |
e423441d RS |
13984 | is a macro, set imm_expr and offset_expr to the values associated |
13985 | with "I" and "A" operands respectively. Otherwise store the value | |
13986 | of the relocatable field (if any) in offset_expr. In both cases | |
13987 | set offset_reloc to the relocation operators applied to offset_expr. */ | |
252b5132 RH |
13988 | |
13989 | static void | |
60f20e8b | 13990 | mips_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 13991 | { |
60f20e8b | 13992 | const struct mips_opcode *first, *past; |
df58fc94 | 13993 | struct hash_control *hash; |
a92713e6 | 13994 | char format; |
14daeee3 | 13995 | size_t end; |
a92713e6 | 13996 | struct mips_operand_token *tokens; |
14daeee3 | 13997 | unsigned int opcode_extra; |
252b5132 | 13998 | |
df58fc94 RS |
13999 | if (mips_opts.micromips) |
14000 | { | |
14001 | hash = micromips_op_hash; | |
14002 | past = µmips_opcodes[bfd_micromips_num_opcodes]; | |
14003 | } | |
14004 | else | |
14005 | { | |
14006 | hash = op_hash; | |
14007 | past = &mips_opcodes[NUMOPCODES]; | |
14008 | } | |
14009 | forced_insn_length = 0; | |
14daeee3 | 14010 | opcode_extra = 0; |
252b5132 | 14011 | |
df58fc94 | 14012 | /* We first try to match an instruction up to a space or to the end. */ |
a40bc9dd RS |
14013 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
14014 | continue; | |
bdaaa2e1 | 14015 | |
60f20e8b RS |
14016 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
14017 | if (first == NULL) | |
252b5132 | 14018 | { |
1661c76c | 14019 | set_insn_error (0, _("unrecognized opcode")); |
a40bc9dd | 14020 | return; |
252b5132 RH |
14021 | } |
14022 | ||
60f20e8b | 14023 | if (strcmp (first->name, "li.s") == 0) |
a92713e6 | 14024 | format = 'f'; |
60f20e8b | 14025 | else if (strcmp (first->name, "li.d") == 0) |
a92713e6 RS |
14026 | format = 'd'; |
14027 | else | |
14028 | format = 0; | |
14029 | tokens = mips_parse_arguments (str + end, format); | |
14030 | if (!tokens) | |
14031 | return; | |
14032 | ||
60f20e8b RS |
14033 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
14034 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) | |
1661c76c | 14035 | set_insn_error (0, _("invalid operands")); |
df58fc94 | 14036 | |
e3de51ce | 14037 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14038 | } |
14039 | ||
77bd4346 RS |
14040 | /* As for mips_ip, but used when assembling MIPS16 code. |
14041 | Also set forced_insn_length to the resulting instruction size in | |
14042 | bytes if the user explicitly requested a small or extended instruction. */ | |
252b5132 RH |
14043 | |
14044 | static void | |
60f20e8b | 14045 | mips16_ip (char *str, struct mips_cl_insn *insn) |
252b5132 | 14046 | { |
1a00e612 | 14047 | char *end, *s, c; |
60f20e8b | 14048 | struct mips_opcode *first; |
a92713e6 | 14049 | struct mips_operand_token *tokens; |
3fb49709 | 14050 | unsigned int l; |
252b5132 | 14051 | |
25499ac7 | 14052 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
252b5132 | 14053 | ; |
1a00e612 RS |
14054 | end = s; |
14055 | c = *end; | |
3fb49709 MR |
14056 | |
14057 | l = 0; | |
1a00e612 | 14058 | switch (c) |
252b5132 RH |
14059 | { |
14060 | case '\0': | |
14061 | break; | |
14062 | ||
14063 | case ' ': | |
1a00e612 | 14064 | s++; |
252b5132 RH |
14065 | break; |
14066 | ||
14067 | case '.': | |
3fb49709 MR |
14068 | s++; |
14069 | if (*s == 't') | |
252b5132 | 14070 | { |
3fb49709 MR |
14071 | l = 2; |
14072 | s++; | |
252b5132 | 14073 | } |
3fb49709 | 14074 | else if (*s == 'e') |
252b5132 | 14075 | { |
3fb49709 MR |
14076 | l = 4; |
14077 | s++; | |
252b5132 | 14078 | } |
3fb49709 MR |
14079 | if (*s == '\0') |
14080 | break; | |
14081 | else if (*s++ == ' ') | |
14082 | break; | |
1661c76c | 14083 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14084 | return; |
14085 | } | |
3fb49709 | 14086 | forced_insn_length = l; |
252b5132 | 14087 | |
1a00e612 | 14088 | *end = 0; |
60f20e8b | 14089 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
1a00e612 RS |
14090 | *end = c; |
14091 | ||
60f20e8b | 14092 | if (!first) |
252b5132 | 14093 | { |
1661c76c | 14094 | set_insn_error (0, _("unrecognized opcode")); |
252b5132 RH |
14095 | return; |
14096 | } | |
14097 | ||
a92713e6 RS |
14098 | tokens = mips_parse_arguments (s, 0); |
14099 | if (!tokens) | |
14100 | return; | |
14101 | ||
60f20e8b | 14102 | if (!match_mips16_insns (insn, first, tokens)) |
1661c76c | 14103 | set_insn_error (0, _("invalid operands")); |
252b5132 | 14104 | |
e3de51ce | 14105 | obstack_free (&mips_operand_tokens, tokens); |
252b5132 RH |
14106 | } |
14107 | ||
b886a2ab RS |
14108 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
14109 | NBITS is the number of significant bits in VAL. */ | |
14110 | ||
14111 | static unsigned long | |
14112 | mips16_immed_extend (offsetT val, unsigned int nbits) | |
14113 | { | |
14114 | int extval; | |
25499ac7 MR |
14115 | |
14116 | extval = 0; | |
14117 | val &= (1U << nbits) - 1; | |
14118 | if (nbits == 16 || nbits == 9) | |
b886a2ab RS |
14119 | { |
14120 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); | |
14121 | val &= 0x1f; | |
14122 | } | |
14123 | else if (nbits == 15) | |
14124 | { | |
14125 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); | |
14126 | val &= 0xf; | |
14127 | } | |
25499ac7 | 14128 | else if (nbits == 6) |
b886a2ab RS |
14129 | { |
14130 | extval = ((val & 0x1f) << 6) | (val & 0x20); | |
14131 | val = 0; | |
14132 | } | |
14133 | return (extval << 16) | val; | |
14134 | } | |
14135 | ||
3ccad066 RS |
14136 | /* Like decode_mips16_operand, but require the operand to be defined and |
14137 | require it to be an integer. */ | |
14138 | ||
14139 | static const struct mips_int_operand * | |
14140 | mips16_immed_operand (int type, bfd_boolean extended_p) | |
14141 | { | |
14142 | const struct mips_operand *operand; | |
14143 | ||
14144 | operand = decode_mips16_operand (type, extended_p); | |
14145 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) | |
14146 | abort (); | |
14147 | return (const struct mips_int_operand *) operand; | |
14148 | } | |
14149 | ||
14150 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ | |
14151 | ||
14152 | static bfd_boolean | |
14153 | mips16_immed_in_range_p (const struct mips_int_operand *operand, | |
14154 | bfd_reloc_code_real_type reloc, offsetT sval) | |
14155 | { | |
14156 | int min_val, max_val; | |
14157 | ||
14158 | min_val = mips_int_operand_min (operand); | |
14159 | max_val = mips_int_operand_max (operand); | |
14160 | if (reloc != BFD_RELOC_UNUSED) | |
14161 | { | |
14162 | if (min_val < 0) | |
14163 | sval = SEXT_16BIT (sval); | |
14164 | else | |
14165 | sval &= 0xffff; | |
14166 | } | |
14167 | ||
14168 | return (sval >= min_val | |
14169 | && sval <= max_val | |
14170 | && (sval & ((1 << operand->shift) - 1)) == 0); | |
14171 | } | |
14172 | ||
5c04167a RS |
14173 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
14174 | extending it if necessary. The instruction in *INSN may | |
14175 | already be extended. | |
14176 | ||
43c0598f RS |
14177 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
14178 | if none. In the former case, VAL is a 16-bit number with no | |
14179 | defined signedness. | |
14180 | ||
14181 | TYPE is the type of the immediate field. USER_INSN_LENGTH | |
14182 | is the length that the user requested, or 0 if none. */ | |
252b5132 RH |
14183 | |
14184 | static void | |
3b4dbbbf | 14185 | mips16_immed (const char *file, unsigned int line, int type, |
43c0598f | 14186 | bfd_reloc_code_real_type reloc, offsetT val, |
5c04167a | 14187 | unsigned int user_insn_length, unsigned long *insn) |
252b5132 | 14188 | { |
3ccad066 RS |
14189 | const struct mips_int_operand *operand; |
14190 | unsigned int uval, length; | |
252b5132 | 14191 | |
3ccad066 RS |
14192 | operand = mips16_immed_operand (type, FALSE); |
14193 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
5c04167a RS |
14194 | { |
14195 | /* We need an extended instruction. */ | |
14196 | if (user_insn_length == 2) | |
14197 | as_bad_where (file, line, _("invalid unextended operand value")); | |
14198 | else | |
14199 | *insn |= MIPS16_EXTEND; | |
14200 | } | |
14201 | else if (user_insn_length == 4) | |
14202 | { | |
14203 | /* The operand doesn't force an unextended instruction to be extended. | |
14204 | Warn if the user wanted an extended instruction anyway. */ | |
14205 | *insn |= MIPS16_EXTEND; | |
14206 | as_warn_where (file, line, | |
14207 | _("extended operand requested but not required")); | |
14208 | } | |
252b5132 | 14209 | |
3ccad066 RS |
14210 | length = mips16_opcode_length (*insn); |
14211 | if (length == 4) | |
252b5132 | 14212 | { |
3ccad066 RS |
14213 | operand = mips16_immed_operand (type, TRUE); |
14214 | if (!mips16_immed_in_range_p (operand, reloc, val)) | |
14215 | as_bad_where (file, line, | |
14216 | _("operand value out of range for instruction")); | |
252b5132 | 14217 | } |
3ccad066 | 14218 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
bdd15286 | 14219 | if (length == 2 || operand->root.lsb != 0) |
3ccad066 | 14220 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
252b5132 | 14221 | else |
3ccad066 | 14222 | *insn |= mips16_immed_extend (uval, operand->root.size); |
252b5132 RH |
14223 | } |
14224 | \f | |
d6f16593 | 14225 | struct percent_op_match |
ad8d3bb3 | 14226 | { |
5e0116d5 RS |
14227 | const char *str; |
14228 | bfd_reloc_code_real_type reloc; | |
d6f16593 MR |
14229 | }; |
14230 | ||
14231 | static const struct percent_op_match mips_percent_op[] = | |
ad8d3bb3 | 14232 | { |
5e0116d5 | 14233 | {"%lo", BFD_RELOC_LO16}, |
5e0116d5 RS |
14234 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
14235 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, | |
14236 | {"%call16", BFD_RELOC_MIPS_CALL16}, | |
14237 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, | |
14238 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, | |
14239 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, | |
14240 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, | |
14241 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, | |
14242 | {"%got", BFD_RELOC_MIPS_GOT16}, | |
14243 | {"%gp_rel", BFD_RELOC_GPREL16}, | |
be3f1006 | 14244 | {"%gprel", BFD_RELOC_GPREL16}, |
5e0116d5 RS |
14245 | {"%half", BFD_RELOC_16}, |
14246 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, | |
14247 | {"%higher", BFD_RELOC_MIPS_HIGHER}, | |
14248 | {"%neg", BFD_RELOC_MIPS_SUB}, | |
3f98094e DJ |
14249 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
14250 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, | |
14251 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, | |
14252 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, | |
14253 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, | |
14254 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, | |
14255 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, | |
7361da2c AB |
14256 | {"%hi", BFD_RELOC_HI16_S}, |
14257 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, | |
14258 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} | |
ad8d3bb3 TS |
14259 | }; |
14260 | ||
d6f16593 MR |
14261 | static const struct percent_op_match mips16_percent_op[] = |
14262 | { | |
14263 | {"%lo", BFD_RELOC_MIPS16_LO16}, | |
be3f1006 | 14264 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
d6f16593 | 14265 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
738e5348 RS |
14266 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
14267 | {"%call16", BFD_RELOC_MIPS16_CALL16}, | |
d0f13682 CLT |
14268 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
14269 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, | |
14270 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, | |
14271 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, | |
14272 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, | |
14273 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, | |
14274 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, | |
14275 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} | |
d6f16593 MR |
14276 | }; |
14277 | ||
252b5132 | 14278 | |
5e0116d5 RS |
14279 | /* Return true if *STR points to a relocation operator. When returning true, |
14280 | move *STR over the operator and store its relocation code in *RELOC. | |
14281 | Leave both *STR and *RELOC alone when returning false. */ | |
14282 | ||
14283 | static bfd_boolean | |
17a2f251 | 14284 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
252b5132 | 14285 | { |
d6f16593 MR |
14286 | const struct percent_op_match *percent_op; |
14287 | size_t limit, i; | |
14288 | ||
14289 | if (mips_opts.mips16) | |
14290 | { | |
14291 | percent_op = mips16_percent_op; | |
14292 | limit = ARRAY_SIZE (mips16_percent_op); | |
14293 | } | |
14294 | else | |
14295 | { | |
14296 | percent_op = mips_percent_op; | |
14297 | limit = ARRAY_SIZE (mips_percent_op); | |
14298 | } | |
76b3015f | 14299 | |
d6f16593 | 14300 | for (i = 0; i < limit; i++) |
5e0116d5 | 14301 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
394f9b3a | 14302 | { |
3f98094e DJ |
14303 | int len = strlen (percent_op[i].str); |
14304 | ||
14305 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
14306 | continue; | |
14307 | ||
5e0116d5 RS |
14308 | *str += strlen (percent_op[i].str); |
14309 | *reloc = percent_op[i].reloc; | |
394f9b3a | 14310 | |
5e0116d5 RS |
14311 | /* Check whether the output BFD supports this relocation. |
14312 | If not, issue an error and fall back on something safe. */ | |
14313 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) | |
394f9b3a | 14314 | { |
20203fb9 | 14315 | as_bad (_("relocation %s isn't supported by the current ABI"), |
5e0116d5 | 14316 | percent_op[i].str); |
01a3f561 | 14317 | *reloc = BFD_RELOC_UNUSED; |
394f9b3a | 14318 | } |
5e0116d5 | 14319 | return TRUE; |
394f9b3a | 14320 | } |
5e0116d5 | 14321 | return FALSE; |
394f9b3a | 14322 | } |
ad8d3bb3 | 14323 | |
ad8d3bb3 | 14324 | |
5e0116d5 RS |
14325 | /* Parse string STR as a 16-bit relocatable operand. Store the |
14326 | expression in *EP and the relocations in the array starting | |
14327 | at RELOC. Return the number of relocation operators used. | |
ad8d3bb3 | 14328 | |
01a3f561 | 14329 | On exit, EXPR_END points to the first character after the expression. */ |
ad8d3bb3 | 14330 | |
5e0116d5 | 14331 | static size_t |
17a2f251 TS |
14332 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
14333 | char *str) | |
ad8d3bb3 | 14334 | { |
5e0116d5 RS |
14335 | bfd_reloc_code_real_type reversed_reloc[3]; |
14336 | size_t reloc_index, i; | |
09b8f35a RS |
14337 | int crux_depth, str_depth; |
14338 | char *crux; | |
5e0116d5 RS |
14339 | |
14340 | /* Search for the start of the main expression, recoding relocations | |
09b8f35a RS |
14341 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
14342 | of the main expression and with CRUX_DEPTH containing the number | |
14343 | of open brackets at that point. */ | |
14344 | reloc_index = -1; | |
14345 | str_depth = 0; | |
14346 | do | |
fb1b3232 | 14347 | { |
09b8f35a RS |
14348 | reloc_index++; |
14349 | crux = str; | |
14350 | crux_depth = str_depth; | |
14351 | ||
14352 | /* Skip over whitespace and brackets, keeping count of the number | |
14353 | of brackets. */ | |
14354 | while (*str == ' ' || *str == '\t' || *str == '(') | |
14355 | if (*str++ == '(') | |
14356 | str_depth++; | |
5e0116d5 | 14357 | } |
09b8f35a RS |
14358 | while (*str == '%' |
14359 | && reloc_index < (HAVE_NEWABI ? 3 : 1) | |
14360 | && parse_relocation (&str, &reversed_reloc[reloc_index])); | |
ad8d3bb3 | 14361 | |
09b8f35a | 14362 | my_getExpression (ep, crux); |
5e0116d5 | 14363 | str = expr_end; |
394f9b3a | 14364 | |
5e0116d5 | 14365 | /* Match every open bracket. */ |
09b8f35a | 14366 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
5e0116d5 | 14367 | if (*str++ == ')') |
09b8f35a | 14368 | crux_depth--; |
394f9b3a | 14369 | |
09b8f35a | 14370 | if (crux_depth > 0) |
20203fb9 | 14371 | as_bad (_("unclosed '('")); |
394f9b3a | 14372 | |
5e0116d5 | 14373 | expr_end = str; |
252b5132 | 14374 | |
01a3f561 | 14375 | if (reloc_index != 0) |
64bdfcaf RS |
14376 | { |
14377 | prev_reloc_op_frag = frag_now; | |
14378 | for (i = 0; i < reloc_index; i++) | |
14379 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; | |
14380 | } | |
fb1b3232 | 14381 | |
5e0116d5 | 14382 | return reloc_index; |
252b5132 RH |
14383 | } |
14384 | ||
14385 | static void | |
17a2f251 | 14386 | my_getExpression (expressionS *ep, char *str) |
252b5132 RH |
14387 | { |
14388 | char *save_in; | |
14389 | ||
14390 | save_in = input_line_pointer; | |
14391 | input_line_pointer = str; | |
14392 | expression (ep); | |
14393 | expr_end = input_line_pointer; | |
14394 | input_line_pointer = save_in; | |
252b5132 RH |
14395 | } |
14396 | ||
6d4af3c2 | 14397 | const char * |
17a2f251 | 14398 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 14399 | { |
499ac353 | 14400 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
252b5132 RH |
14401 | } |
14402 | ||
14403 | void | |
17a2f251 | 14404 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
14405 | { |
14406 | if (target_big_endian) | |
14407 | number_to_chars_bigendian (buf, val, n); | |
14408 | else | |
14409 | number_to_chars_littleendian (buf, val, n); | |
14410 | } | |
14411 | \f | |
e013f690 TS |
14412 | static int support_64bit_objects(void) |
14413 | { | |
14414 | const char **list, **l; | |
aa3d8fdf | 14415 | int yes; |
e013f690 TS |
14416 | |
14417 | list = bfd_target_list (); | |
14418 | for (l = list; *l != NULL; l++) | |
aeffff67 RS |
14419 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
14420 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) | |
e013f690 | 14421 | break; |
aa3d8fdf | 14422 | yes = (*l != NULL); |
e013f690 | 14423 | free (list); |
aa3d8fdf | 14424 | return yes; |
e013f690 TS |
14425 | } |
14426 | ||
316f5878 RS |
14427 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
14428 | NEW_VALUE. Warn if another value was already specified. Note: | |
14429 | we have to defer parsing the -march and -mtune arguments in order | |
14430 | to handle 'from-abi' correctly, since the ABI might be specified | |
14431 | in a later argument. */ | |
14432 | ||
14433 | static void | |
17a2f251 | 14434 | mips_set_option_string (const char **string_ptr, const char *new_value) |
316f5878 RS |
14435 | { |
14436 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) | |
1661c76c | 14437 | as_warn (_("a different %s was already specified, is now %s"), |
316f5878 RS |
14438 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
14439 | new_value); | |
14440 | ||
14441 | *string_ptr = new_value; | |
14442 | } | |
14443 | ||
252b5132 | 14444 | int |
17b9d67d | 14445 | md_parse_option (int c, const char *arg) |
252b5132 | 14446 | { |
c6278170 RS |
14447 | unsigned int i; |
14448 | ||
14449 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) | |
14450 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) | |
14451 | { | |
919731af | 14452 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
c6278170 RS |
14453 | c == mips_ases[i].option_on); |
14454 | return 1; | |
14455 | } | |
14456 | ||
252b5132 RH |
14457 | switch (c) |
14458 | { | |
119d663a NC |
14459 | case OPTION_CONSTRUCT_FLOATS: |
14460 | mips_disable_float_construction = 0; | |
14461 | break; | |
bdaaa2e1 | 14462 | |
119d663a NC |
14463 | case OPTION_NO_CONSTRUCT_FLOATS: |
14464 | mips_disable_float_construction = 1; | |
14465 | break; | |
bdaaa2e1 | 14466 | |
252b5132 RH |
14467 | case OPTION_TRAP: |
14468 | mips_trap = 1; | |
14469 | break; | |
14470 | ||
14471 | case OPTION_BREAK: | |
14472 | mips_trap = 0; | |
14473 | break; | |
14474 | ||
14475 | case OPTION_EB: | |
14476 | target_big_endian = 1; | |
14477 | break; | |
14478 | ||
14479 | case OPTION_EL: | |
14480 | target_big_endian = 0; | |
14481 | break; | |
14482 | ||
14483 | case 'O': | |
4ffff32f TS |
14484 | if (arg == NULL) |
14485 | mips_optimize = 1; | |
14486 | else if (arg[0] == '0') | |
14487 | mips_optimize = 0; | |
14488 | else if (arg[0] == '1') | |
252b5132 RH |
14489 | mips_optimize = 1; |
14490 | else | |
14491 | mips_optimize = 2; | |
14492 | break; | |
14493 | ||
14494 | case 'g': | |
14495 | if (arg == NULL) | |
14496 | mips_debug = 2; | |
14497 | else | |
14498 | mips_debug = atoi (arg); | |
252b5132 RH |
14499 | break; |
14500 | ||
14501 | case OPTION_MIPS1: | |
0b35dfee | 14502 | file_mips_opts.isa = ISA_MIPS1; |
252b5132 RH |
14503 | break; |
14504 | ||
14505 | case OPTION_MIPS2: | |
0b35dfee | 14506 | file_mips_opts.isa = ISA_MIPS2; |
252b5132 RH |
14507 | break; |
14508 | ||
14509 | case OPTION_MIPS3: | |
0b35dfee | 14510 | file_mips_opts.isa = ISA_MIPS3; |
252b5132 RH |
14511 | break; |
14512 | ||
14513 | case OPTION_MIPS4: | |
0b35dfee | 14514 | file_mips_opts.isa = ISA_MIPS4; |
e7af610e NC |
14515 | break; |
14516 | ||
84ea6cf2 | 14517 | case OPTION_MIPS5: |
0b35dfee | 14518 | file_mips_opts.isa = ISA_MIPS5; |
84ea6cf2 NC |
14519 | break; |
14520 | ||
e7af610e | 14521 | case OPTION_MIPS32: |
0b35dfee | 14522 | file_mips_opts.isa = ISA_MIPS32; |
252b5132 RH |
14523 | break; |
14524 | ||
af7ee8bf | 14525 | case OPTION_MIPS32R2: |
0b35dfee | 14526 | file_mips_opts.isa = ISA_MIPS32R2; |
af7ee8bf CD |
14527 | break; |
14528 | ||
ae52f483 | 14529 | case OPTION_MIPS32R3: |
0ae19f05 | 14530 | file_mips_opts.isa = ISA_MIPS32R3; |
ae52f483 AB |
14531 | break; |
14532 | ||
14533 | case OPTION_MIPS32R5: | |
0ae19f05 | 14534 | file_mips_opts.isa = ISA_MIPS32R5; |
ae52f483 AB |
14535 | break; |
14536 | ||
7361da2c AB |
14537 | case OPTION_MIPS32R6: |
14538 | file_mips_opts.isa = ISA_MIPS32R6; | |
14539 | break; | |
14540 | ||
5f74bc13 | 14541 | case OPTION_MIPS64R2: |
0b35dfee | 14542 | file_mips_opts.isa = ISA_MIPS64R2; |
5f74bc13 CD |
14543 | break; |
14544 | ||
ae52f483 | 14545 | case OPTION_MIPS64R3: |
0ae19f05 | 14546 | file_mips_opts.isa = ISA_MIPS64R3; |
ae52f483 AB |
14547 | break; |
14548 | ||
14549 | case OPTION_MIPS64R5: | |
0ae19f05 | 14550 | file_mips_opts.isa = ISA_MIPS64R5; |
ae52f483 AB |
14551 | break; |
14552 | ||
7361da2c AB |
14553 | case OPTION_MIPS64R6: |
14554 | file_mips_opts.isa = ISA_MIPS64R6; | |
14555 | break; | |
14556 | ||
84ea6cf2 | 14557 | case OPTION_MIPS64: |
0b35dfee | 14558 | file_mips_opts.isa = ISA_MIPS64; |
84ea6cf2 NC |
14559 | break; |
14560 | ||
ec68c924 | 14561 | case OPTION_MTUNE: |
316f5878 RS |
14562 | mips_set_option_string (&mips_tune_string, arg); |
14563 | break; | |
ec68c924 | 14564 | |
316f5878 RS |
14565 | case OPTION_MARCH: |
14566 | mips_set_option_string (&mips_arch_string, arg); | |
252b5132 RH |
14567 | break; |
14568 | ||
14569 | case OPTION_M4650: | |
316f5878 RS |
14570 | mips_set_option_string (&mips_arch_string, "4650"); |
14571 | mips_set_option_string (&mips_tune_string, "4650"); | |
252b5132 RH |
14572 | break; |
14573 | ||
14574 | case OPTION_NO_M4650: | |
14575 | break; | |
14576 | ||
14577 | case OPTION_M4010: | |
316f5878 RS |
14578 | mips_set_option_string (&mips_arch_string, "4010"); |
14579 | mips_set_option_string (&mips_tune_string, "4010"); | |
252b5132 RH |
14580 | break; |
14581 | ||
14582 | case OPTION_NO_M4010: | |
14583 | break; | |
14584 | ||
14585 | case OPTION_M4100: | |
316f5878 RS |
14586 | mips_set_option_string (&mips_arch_string, "4100"); |
14587 | mips_set_option_string (&mips_tune_string, "4100"); | |
252b5132 RH |
14588 | break; |
14589 | ||
14590 | case OPTION_NO_M4100: | |
14591 | break; | |
14592 | ||
252b5132 | 14593 | case OPTION_M3900: |
316f5878 RS |
14594 | mips_set_option_string (&mips_arch_string, "3900"); |
14595 | mips_set_option_string (&mips_tune_string, "3900"); | |
252b5132 | 14596 | break; |
bdaaa2e1 | 14597 | |
252b5132 RH |
14598 | case OPTION_NO_M3900: |
14599 | break; | |
14600 | ||
df58fc94 | 14601 | case OPTION_MICROMIPS: |
919731af | 14602 | if (file_mips_opts.mips16 == 1) |
df58fc94 RS |
14603 | { |
14604 | as_bad (_("-mmicromips cannot be used with -mips16")); | |
14605 | return 0; | |
14606 | } | |
919731af | 14607 | file_mips_opts.micromips = 1; |
df58fc94 RS |
14608 | mips_no_prev_insn (); |
14609 | break; | |
14610 | ||
14611 | case OPTION_NO_MICROMIPS: | |
919731af | 14612 | file_mips_opts.micromips = 0; |
df58fc94 RS |
14613 | mips_no_prev_insn (); |
14614 | break; | |
14615 | ||
252b5132 | 14616 | case OPTION_MIPS16: |
919731af | 14617 | if (file_mips_opts.micromips == 1) |
df58fc94 RS |
14618 | { |
14619 | as_bad (_("-mips16 cannot be used with -micromips")); | |
14620 | return 0; | |
14621 | } | |
919731af | 14622 | file_mips_opts.mips16 = 1; |
7d10b47d | 14623 | mips_no_prev_insn (); |
252b5132 RH |
14624 | break; |
14625 | ||
14626 | case OPTION_NO_MIPS16: | |
919731af | 14627 | file_mips_opts.mips16 = 0; |
7d10b47d | 14628 | mips_no_prev_insn (); |
252b5132 RH |
14629 | break; |
14630 | ||
6a32d874 CM |
14631 | case OPTION_FIX_24K: |
14632 | mips_fix_24k = 1; | |
14633 | break; | |
14634 | ||
14635 | case OPTION_NO_FIX_24K: | |
14636 | mips_fix_24k = 0; | |
14637 | break; | |
14638 | ||
a8d14a88 CM |
14639 | case OPTION_FIX_RM7000: |
14640 | mips_fix_rm7000 = 1; | |
14641 | break; | |
14642 | ||
14643 | case OPTION_NO_FIX_RM7000: | |
14644 | mips_fix_rm7000 = 0; | |
14645 | break; | |
14646 | ||
c67a084a NC |
14647 | case OPTION_FIX_LOONGSON2F_JUMP: |
14648 | mips_fix_loongson2f_jump = TRUE; | |
14649 | break; | |
14650 | ||
14651 | case OPTION_NO_FIX_LOONGSON2F_JUMP: | |
14652 | mips_fix_loongson2f_jump = FALSE; | |
14653 | break; | |
14654 | ||
14655 | case OPTION_FIX_LOONGSON2F_NOP: | |
14656 | mips_fix_loongson2f_nop = TRUE; | |
14657 | break; | |
14658 | ||
14659 | case OPTION_NO_FIX_LOONGSON2F_NOP: | |
14660 | mips_fix_loongson2f_nop = FALSE; | |
14661 | break; | |
14662 | ||
d766e8ec RS |
14663 | case OPTION_FIX_VR4120: |
14664 | mips_fix_vr4120 = 1; | |
60b63b72 RS |
14665 | break; |
14666 | ||
d766e8ec RS |
14667 | case OPTION_NO_FIX_VR4120: |
14668 | mips_fix_vr4120 = 0; | |
60b63b72 RS |
14669 | break; |
14670 | ||
7d8e00cf RS |
14671 | case OPTION_FIX_VR4130: |
14672 | mips_fix_vr4130 = 1; | |
14673 | break; | |
14674 | ||
14675 | case OPTION_NO_FIX_VR4130: | |
14676 | mips_fix_vr4130 = 0; | |
14677 | break; | |
14678 | ||
d954098f DD |
14679 | case OPTION_FIX_CN63XXP1: |
14680 | mips_fix_cn63xxp1 = TRUE; | |
14681 | break; | |
14682 | ||
14683 | case OPTION_NO_FIX_CN63XXP1: | |
14684 | mips_fix_cn63xxp1 = FALSE; | |
14685 | break; | |
14686 | ||
4a6a3df4 AO |
14687 | case OPTION_RELAX_BRANCH: |
14688 | mips_relax_branch = 1; | |
14689 | break; | |
14690 | ||
14691 | case OPTION_NO_RELAX_BRANCH: | |
14692 | mips_relax_branch = 0; | |
14693 | break; | |
14694 | ||
8b10b0b3 MR |
14695 | case OPTION_IGNORE_BRANCH_ISA: |
14696 | mips_ignore_branch_isa = TRUE; | |
14697 | break; | |
14698 | ||
14699 | case OPTION_NO_IGNORE_BRANCH_ISA: | |
14700 | mips_ignore_branch_isa = FALSE; | |
14701 | break; | |
14702 | ||
833794fc | 14703 | case OPTION_INSN32: |
919731af | 14704 | file_mips_opts.insn32 = TRUE; |
833794fc MR |
14705 | break; |
14706 | ||
14707 | case OPTION_NO_INSN32: | |
919731af | 14708 | file_mips_opts.insn32 = FALSE; |
833794fc MR |
14709 | break; |
14710 | ||
aa6975fb ILT |
14711 | case OPTION_MSHARED: |
14712 | mips_in_shared = TRUE; | |
14713 | break; | |
14714 | ||
14715 | case OPTION_MNO_SHARED: | |
14716 | mips_in_shared = FALSE; | |
14717 | break; | |
14718 | ||
aed1a261 | 14719 | case OPTION_MSYM32: |
919731af | 14720 | file_mips_opts.sym32 = TRUE; |
aed1a261 RS |
14721 | break; |
14722 | ||
14723 | case OPTION_MNO_SYM32: | |
919731af | 14724 | file_mips_opts.sym32 = FALSE; |
aed1a261 RS |
14725 | break; |
14726 | ||
252b5132 RH |
14727 | /* When generating ELF code, we permit -KPIC and -call_shared to |
14728 | select SVR4_PIC, and -non_shared to select no PIC. This is | |
14729 | intended to be compatible with Irix 5. */ | |
14730 | case OPTION_CALL_SHARED: | |
252b5132 | 14731 | mips_pic = SVR4_PIC; |
143d77c5 | 14732 | mips_abicalls = TRUE; |
252b5132 RH |
14733 | break; |
14734 | ||
861fb55a | 14735 | case OPTION_CALL_NONPIC: |
861fb55a DJ |
14736 | mips_pic = NO_PIC; |
14737 | mips_abicalls = TRUE; | |
14738 | break; | |
14739 | ||
252b5132 | 14740 | case OPTION_NON_SHARED: |
252b5132 | 14741 | mips_pic = NO_PIC; |
143d77c5 | 14742 | mips_abicalls = FALSE; |
252b5132 RH |
14743 | break; |
14744 | ||
44075ae2 TS |
14745 | /* The -xgot option tells the assembler to use 32 bit offsets |
14746 | when accessing the got in SVR4_PIC mode. It is for Irix | |
252b5132 RH |
14747 | compatibility. */ |
14748 | case OPTION_XGOT: | |
14749 | mips_big_got = 1; | |
14750 | break; | |
14751 | ||
14752 | case 'G': | |
6caf9ef4 TS |
14753 | g_switch_value = atoi (arg); |
14754 | g_switch_seen = 1; | |
252b5132 RH |
14755 | break; |
14756 | ||
34ba82a8 TS |
14757 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
14758 | and -mabi=64. */ | |
252b5132 | 14759 | case OPTION_32: |
f3ded42a | 14760 | mips_abi = O32_ABI; |
252b5132 RH |
14761 | break; |
14762 | ||
e013f690 | 14763 | case OPTION_N32: |
316f5878 | 14764 | mips_abi = N32_ABI; |
e013f690 | 14765 | break; |
252b5132 | 14766 | |
e013f690 | 14767 | case OPTION_64: |
316f5878 | 14768 | mips_abi = N64_ABI; |
f43abd2b | 14769 | if (!support_64bit_objects()) |
1661c76c | 14770 | as_fatal (_("no compiled in support for 64 bit object file format")); |
252b5132 RH |
14771 | break; |
14772 | ||
c97ef257 | 14773 | case OPTION_GP32: |
bad1aba3 | 14774 | file_mips_opts.gp = 32; |
c97ef257 AH |
14775 | break; |
14776 | ||
14777 | case OPTION_GP64: | |
bad1aba3 | 14778 | file_mips_opts.gp = 64; |
c97ef257 | 14779 | break; |
252b5132 | 14780 | |
ca4e0257 | 14781 | case OPTION_FP32: |
0b35dfee | 14782 | file_mips_opts.fp = 32; |
316f5878 RS |
14783 | break; |
14784 | ||
351cdf24 MF |
14785 | case OPTION_FPXX: |
14786 | file_mips_opts.fp = 0; | |
14787 | break; | |
14788 | ||
316f5878 | 14789 | case OPTION_FP64: |
0b35dfee | 14790 | file_mips_opts.fp = 64; |
ca4e0257 RS |
14791 | break; |
14792 | ||
351cdf24 MF |
14793 | case OPTION_ODD_SPREG: |
14794 | file_mips_opts.oddspreg = 1; | |
14795 | break; | |
14796 | ||
14797 | case OPTION_NO_ODD_SPREG: | |
14798 | file_mips_opts.oddspreg = 0; | |
14799 | break; | |
14800 | ||
037b32b9 | 14801 | case OPTION_SINGLE_FLOAT: |
0b35dfee | 14802 | file_mips_opts.single_float = 1; |
037b32b9 AN |
14803 | break; |
14804 | ||
14805 | case OPTION_DOUBLE_FLOAT: | |
0b35dfee | 14806 | file_mips_opts.single_float = 0; |
037b32b9 AN |
14807 | break; |
14808 | ||
14809 | case OPTION_SOFT_FLOAT: | |
0b35dfee | 14810 | file_mips_opts.soft_float = 1; |
037b32b9 AN |
14811 | break; |
14812 | ||
14813 | case OPTION_HARD_FLOAT: | |
0b35dfee | 14814 | file_mips_opts.soft_float = 0; |
037b32b9 AN |
14815 | break; |
14816 | ||
252b5132 | 14817 | case OPTION_MABI: |
e013f690 | 14818 | if (strcmp (arg, "32") == 0) |
316f5878 | 14819 | mips_abi = O32_ABI; |
e013f690 | 14820 | else if (strcmp (arg, "o64") == 0) |
316f5878 | 14821 | mips_abi = O64_ABI; |
e013f690 | 14822 | else if (strcmp (arg, "n32") == 0) |
316f5878 | 14823 | mips_abi = N32_ABI; |
e013f690 TS |
14824 | else if (strcmp (arg, "64") == 0) |
14825 | { | |
316f5878 | 14826 | mips_abi = N64_ABI; |
e013f690 | 14827 | if (! support_64bit_objects()) |
1661c76c | 14828 | as_fatal (_("no compiled in support for 64 bit object file " |
e013f690 TS |
14829 | "format")); |
14830 | } | |
14831 | else if (strcmp (arg, "eabi") == 0) | |
316f5878 | 14832 | mips_abi = EABI_ABI; |
e013f690 | 14833 | else |
da0e507f TS |
14834 | { |
14835 | as_fatal (_("invalid abi -mabi=%s"), arg); | |
14836 | return 0; | |
14837 | } | |
252b5132 RH |
14838 | break; |
14839 | ||
6b76fefe | 14840 | case OPTION_M7000_HILO_FIX: |
b34976b6 | 14841 | mips_7000_hilo_fix = TRUE; |
6b76fefe CM |
14842 | break; |
14843 | ||
9ee72ff1 | 14844 | case OPTION_MNO_7000_HILO_FIX: |
b34976b6 | 14845 | mips_7000_hilo_fix = FALSE; |
6b76fefe CM |
14846 | break; |
14847 | ||
ecb4347a | 14848 | case OPTION_MDEBUG: |
b34976b6 | 14849 | mips_flag_mdebug = TRUE; |
ecb4347a DJ |
14850 | break; |
14851 | ||
14852 | case OPTION_NO_MDEBUG: | |
b34976b6 | 14853 | mips_flag_mdebug = FALSE; |
ecb4347a | 14854 | break; |
dcd410fe RO |
14855 | |
14856 | case OPTION_PDR: | |
14857 | mips_flag_pdr = TRUE; | |
14858 | break; | |
14859 | ||
14860 | case OPTION_NO_PDR: | |
14861 | mips_flag_pdr = FALSE; | |
14862 | break; | |
0a44bf69 RS |
14863 | |
14864 | case OPTION_MVXWORKS_PIC: | |
14865 | mips_pic = VXWORKS_PIC; | |
14866 | break; | |
ecb4347a | 14867 | |
ba92f887 MR |
14868 | case OPTION_NAN: |
14869 | if (strcmp (arg, "2008") == 0) | |
7361da2c | 14870 | mips_nan2008 = 1; |
ba92f887 | 14871 | else if (strcmp (arg, "legacy") == 0) |
7361da2c | 14872 | mips_nan2008 = 0; |
ba92f887 MR |
14873 | else |
14874 | { | |
1661c76c | 14875 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
ba92f887 MR |
14876 | return 0; |
14877 | } | |
14878 | break; | |
14879 | ||
252b5132 RH |
14880 | default: |
14881 | return 0; | |
14882 | } | |
14883 | ||
c67a084a NC |
14884 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
14885 | ||
252b5132 RH |
14886 | return 1; |
14887 | } | |
316f5878 | 14888 | \f |
919731af | 14889 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
252b5132 | 14890 | |
316f5878 | 14891 | static void |
17a2f251 | 14892 | mips_set_tune (const struct mips_cpu_info *info) |
316f5878 RS |
14893 | { |
14894 | if (info != 0) | |
fef14a42 | 14895 | mips_tune = info->cpu; |
316f5878 | 14896 | } |
80cc45a5 | 14897 | |
34ba82a8 | 14898 | |
252b5132 | 14899 | void |
17a2f251 | 14900 | mips_after_parse_args (void) |
e9670677 | 14901 | { |
fef14a42 TS |
14902 | const struct mips_cpu_info *arch_info = 0; |
14903 | const struct mips_cpu_info *tune_info = 0; | |
14904 | ||
e9670677 | 14905 | /* GP relative stuff not working for PE */ |
6caf9ef4 | 14906 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
e9670677 | 14907 | { |
6caf9ef4 | 14908 | if (g_switch_seen && g_switch_value != 0) |
1661c76c | 14909 | as_bad (_("-G not supported in this configuration")); |
e9670677 MR |
14910 | g_switch_value = 0; |
14911 | } | |
14912 | ||
cac012d6 AO |
14913 | if (mips_abi == NO_ABI) |
14914 | mips_abi = MIPS_DEFAULT_ABI; | |
14915 | ||
919731af | 14916 | /* The following code determines the architecture. |
22923709 RS |
14917 | Similar code was added to GCC 3.3 (see override_options() in |
14918 | config/mips/mips.c). The GAS and GCC code should be kept in sync | |
14919 | as much as possible. */ | |
e9670677 | 14920 | |
316f5878 | 14921 | if (mips_arch_string != 0) |
fef14a42 | 14922 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
e9670677 | 14923 | |
0b35dfee | 14924 | if (file_mips_opts.isa != ISA_UNKNOWN) |
e9670677 | 14925 | { |
0b35dfee | 14926 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
fef14a42 | 14927 | ISA level specified by -mipsN, while arch_info->isa contains |
316f5878 | 14928 | the -march selection (if any). */ |
fef14a42 | 14929 | if (arch_info != 0) |
e9670677 | 14930 | { |
316f5878 RS |
14931 | /* -march takes precedence over -mipsN, since it is more descriptive. |
14932 | There's no harm in specifying both as long as the ISA levels | |
14933 | are the same. */ | |
0b35dfee | 14934 | if (file_mips_opts.isa != arch_info->isa) |
1661c76c RS |
14935 | as_bad (_("-%s conflicts with the other architecture options," |
14936 | " which imply -%s"), | |
0b35dfee | 14937 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
fef14a42 | 14938 | mips_cpu_info_from_isa (arch_info->isa)->name); |
e9670677 | 14939 | } |
316f5878 | 14940 | else |
0b35dfee | 14941 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
e9670677 MR |
14942 | } |
14943 | ||
fef14a42 | 14944 | if (arch_info == 0) |
95bfe26e MF |
14945 | { |
14946 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); | |
14947 | gas_assert (arch_info); | |
14948 | } | |
e9670677 | 14949 | |
fef14a42 | 14950 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
20203fb9 | 14951 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
fef14a42 TS |
14952 | arch_info->name); |
14953 | ||
919731af | 14954 | file_mips_opts.arch = arch_info->cpu; |
14955 | file_mips_opts.isa = arch_info->isa; | |
14956 | ||
14957 | /* Set up initial mips_opts state. */ | |
14958 | mips_opts = file_mips_opts; | |
14959 | ||
14960 | /* The register size inference code is now placed in | |
14961 | file_mips_check_options. */ | |
fef14a42 | 14962 | |
0b35dfee | 14963 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
14964 | processor. */ | |
fef14a42 TS |
14965 | if (mips_tune_string != 0) |
14966 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); | |
e9670677 | 14967 | |
fef14a42 TS |
14968 | if (tune_info == 0) |
14969 | mips_set_tune (arch_info); | |
14970 | else | |
14971 | mips_set_tune (tune_info); | |
e9670677 | 14972 | |
ecb4347a | 14973 | if (mips_flag_mdebug < 0) |
e8044f35 | 14974 | mips_flag_mdebug = 0; |
e9670677 MR |
14975 | } |
14976 | \f | |
14977 | void | |
17a2f251 | 14978 | mips_init_after_args (void) |
252b5132 RH |
14979 | { |
14980 | /* initialize opcodes */ | |
14981 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; | |
beae10d5 | 14982 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
252b5132 RH |
14983 | } |
14984 | ||
14985 | long | |
17a2f251 | 14986 | md_pcrel_from (fixS *fixP) |
252b5132 | 14987 | { |
a7ebbfdf TS |
14988 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
14989 | switch (fixP->fx_r_type) | |
14990 | { | |
df58fc94 RS |
14991 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
14992 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
14993 | /* Return the address of the delay slot. */ | |
14994 | return addr + 2; | |
14995 | ||
14996 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
14997 | case BFD_RELOC_MICROMIPS_JMP: | |
c9775dde | 14998 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
a7ebbfdf | 14999 | case BFD_RELOC_16_PCREL_S2: |
7361da2c AB |
15000 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15001 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
a7ebbfdf TS |
15002 | case BFD_RELOC_MIPS_JMP: |
15003 | /* Return the address of the delay slot. */ | |
15004 | return addr + 4; | |
df58fc94 | 15005 | |
51f6035b MR |
15006 | case BFD_RELOC_MIPS_18_PCREL_S3: |
15007 | /* Return the aligned address of the doubleword containing | |
15008 | the instruction. */ | |
15009 | return addr & ~7; | |
15010 | ||
a7ebbfdf TS |
15011 | default: |
15012 | return addr; | |
15013 | } | |
252b5132 RH |
15014 | } |
15015 | ||
252b5132 RH |
15016 | /* This is called before the symbol table is processed. In order to |
15017 | work with gcc when using mips-tfile, we must keep all local labels. | |
15018 | However, in other cases, we want to discard them. If we were | |
15019 | called with -g, but we didn't see any debugging information, it may | |
15020 | mean that gcc is smuggling debugging information through to | |
15021 | mips-tfile, in which case we must generate all local labels. */ | |
15022 | ||
15023 | void | |
17a2f251 | 15024 | mips_frob_file_before_adjust (void) |
252b5132 RH |
15025 | { |
15026 | #ifndef NO_ECOFF_DEBUGGING | |
15027 | if (ECOFF_DEBUGGING | |
15028 | && mips_debug != 0 | |
15029 | && ! ecoff_debugging_seen) | |
15030 | flag_keep_locals = 1; | |
15031 | #endif | |
15032 | } | |
15033 | ||
3b91255e | 15034 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
55cf6793 | 15035 | the corresponding LO16 reloc. This is called before md_apply_fix and |
3b91255e RS |
15036 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
15037 | relocation operators. | |
15038 | ||
15039 | For our purposes, a %lo() expression matches a %got() or %hi() | |
15040 | expression if: | |
15041 | ||
15042 | (a) it refers to the same symbol; and | |
15043 | (b) the offset applied in the %lo() expression is no lower than | |
15044 | the offset applied in the %got() or %hi(). | |
15045 | ||
15046 | (b) allows us to cope with code like: | |
15047 | ||
15048 | lui $4,%hi(foo) | |
15049 | lh $4,%lo(foo+2)($4) | |
15050 | ||
15051 | ...which is legal on RELA targets, and has a well-defined behaviour | |
15052 | if the user knows that adding 2 to "foo" will not induce a carry to | |
15053 | the high 16 bits. | |
15054 | ||
15055 | When several %lo()s match a particular %got() or %hi(), we use the | |
15056 | following rules to distinguish them: | |
15057 | ||
15058 | (1) %lo()s with smaller offsets are a better match than %lo()s with | |
15059 | higher offsets. | |
15060 | ||
15061 | (2) %lo()s with no matching %got() or %hi() are better than those | |
15062 | that already have a matching %got() or %hi(). | |
15063 | ||
15064 | (3) later %lo()s are better than earlier %lo()s. | |
15065 | ||
15066 | These rules are applied in order. | |
15067 | ||
15068 | (1) means, among other things, that %lo()s with identical offsets are | |
15069 | chosen if they exist. | |
15070 | ||
15071 | (2) means that we won't associate several high-part relocations with | |
15072 | the same low-part relocation unless there's no alternative. Having | |
15073 | several high parts for the same low part is a GNU extension; this rule | |
15074 | allows careful users to avoid it. | |
15075 | ||
15076 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, | |
15077 | with the last high-part relocation being at the front of the list. | |
15078 | It therefore makes sense to choose the last matching low-part | |
15079 | relocation, all other things being equal. It's also easier | |
15080 | to code that way. */ | |
252b5132 RH |
15081 | |
15082 | void | |
17a2f251 | 15083 | mips_frob_file (void) |
252b5132 RH |
15084 | { |
15085 | struct mips_hi_fixup *l; | |
35903be0 | 15086 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
252b5132 RH |
15087 | |
15088 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) | |
15089 | { | |
15090 | segment_info_type *seginfo; | |
3b91255e RS |
15091 | bfd_boolean matched_lo_p; |
15092 | fixS **hi_pos, **lo_pos, **pos; | |
252b5132 | 15093 | |
9c2799c2 | 15094 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
252b5132 | 15095 | |
5919d012 | 15096 | /* If a GOT16 relocation turns out to be against a global symbol, |
b886a2ab RS |
15097 | there isn't supposed to be a matching LO. Ignore %gots against |
15098 | constants; we'll report an error for those later. */ | |
738e5348 | 15099 | if (got16_reloc_p (l->fixp->fx_r_type) |
b886a2ab | 15100 | && !(l->fixp->fx_addsy |
9e009953 | 15101 | && pic_need_relax (l->fixp->fx_addsy))) |
5919d012 RS |
15102 | continue; |
15103 | ||
15104 | /* Check quickly whether the next fixup happens to be a matching %lo. */ | |
15105 | if (fixup_has_matching_lo_p (l->fixp)) | |
252b5132 RH |
15106 | continue; |
15107 | ||
252b5132 | 15108 | seginfo = seg_info (l->seg); |
252b5132 | 15109 | |
3b91255e RS |
15110 | /* Set HI_POS to the position of this relocation in the chain. |
15111 | Set LO_POS to the position of the chosen low-part relocation. | |
15112 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part | |
15113 | relocation that matches an immediately-preceding high-part | |
15114 | relocation. */ | |
15115 | hi_pos = NULL; | |
15116 | lo_pos = NULL; | |
15117 | matched_lo_p = FALSE; | |
738e5348 | 15118 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
35903be0 | 15119 | |
3b91255e RS |
15120 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
15121 | { | |
15122 | if (*pos == l->fixp) | |
15123 | hi_pos = pos; | |
15124 | ||
35903be0 | 15125 | if ((*pos)->fx_r_type == looking_for_rtype |
30cfc97a | 15126 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
3b91255e RS |
15127 | && (*pos)->fx_offset >= l->fixp->fx_offset |
15128 | && (lo_pos == NULL | |
15129 | || (*pos)->fx_offset < (*lo_pos)->fx_offset | |
15130 | || (!matched_lo_p | |
15131 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) | |
15132 | lo_pos = pos; | |
15133 | ||
15134 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) | |
15135 | && fixup_has_matching_lo_p (*pos)); | |
15136 | } | |
15137 | ||
15138 | /* If we found a match, remove the high-part relocation from its | |
15139 | current position and insert it before the low-part relocation. | |
15140 | Make the offsets match so that fixup_has_matching_lo_p() | |
15141 | will return true. | |
15142 | ||
15143 | We don't warn about unmatched high-part relocations since some | |
15144 | versions of gcc have been known to emit dead "lui ...%hi(...)" | |
15145 | instructions. */ | |
15146 | if (lo_pos != NULL) | |
15147 | { | |
15148 | l->fixp->fx_offset = (*lo_pos)->fx_offset; | |
15149 | if (l->fixp->fx_next != *lo_pos) | |
252b5132 | 15150 | { |
3b91255e RS |
15151 | *hi_pos = l->fixp->fx_next; |
15152 | l->fixp->fx_next = *lo_pos; | |
15153 | *lo_pos = l->fixp; | |
252b5132 | 15154 | } |
252b5132 RH |
15155 | } |
15156 | } | |
15157 | } | |
15158 | ||
252b5132 | 15159 | int |
17a2f251 | 15160 | mips_force_relocation (fixS *fixp) |
252b5132 | 15161 | { |
ae6063d4 | 15162 | if (generic_force_reloc (fixp)) |
252b5132 RH |
15163 | return 1; |
15164 | ||
df58fc94 RS |
15165 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
15166 | so that the linker relaxation can update targets. */ | |
15167 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 | |
15168 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
15169 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) | |
15170 | return 1; | |
15171 | ||
5caa2b07 MR |
15172 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
15173 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and | |
15174 | microMIPS symbols so that we can do cross-mode branch diagnostics | |
15175 | and BAL to JALX conversion by the linker. */ | |
15176 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 | |
9d862524 MR |
15177 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
15178 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) | |
15179 | && fixp->fx_addsy | |
15180 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) | |
15181 | return 1; | |
15182 | ||
7361da2c | 15183 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
912815f0 | 15184 | if (ISA_IS_R6 (file_mips_opts.isa) |
7361da2c AB |
15185 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
15186 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
15187 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
15188 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
15189 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
15190 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
15191 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) | |
15192 | return 1; | |
15193 | ||
3e722fb5 | 15194 | return 0; |
252b5132 RH |
15195 | } |
15196 | ||
b416ba9b MR |
15197 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
15198 | ||
15199 | bfd_boolean | |
15200 | mips_force_relocation_abs (fixS *fixp) | |
15201 | { | |
15202 | if (generic_force_reloc (fixp)) | |
15203 | return TRUE; | |
15204 | ||
15205 | /* These relocations do not have enough bits in the in-place addend | |
15206 | to hold an arbitrary absolute section's offset. */ | |
15207 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) | |
15208 | return TRUE; | |
15209 | ||
15210 | return FALSE; | |
15211 | } | |
15212 | ||
b886a2ab RS |
15213 | /* Read the instruction associated with RELOC from BUF. */ |
15214 | ||
15215 | static unsigned int | |
15216 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) | |
15217 | { | |
15218 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15219 | return read_compressed_insn (buf, 4); | |
15220 | else | |
15221 | return read_insn (buf); | |
15222 | } | |
15223 | ||
15224 | /* Write instruction INSN to BUF, given that it has been relocated | |
15225 | by RELOC. */ | |
15226 | ||
15227 | static void | |
15228 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, | |
15229 | unsigned long insn) | |
15230 | { | |
15231 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) | |
15232 | write_compressed_insn (buf, insn, 4); | |
15233 | else | |
15234 | write_insn (buf, insn); | |
15235 | } | |
15236 | ||
9d862524 MR |
15237 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
15238 | to a symbol in another ISA mode, which cannot be converted to JALX. */ | |
15239 | ||
15240 | static bfd_boolean | |
15241 | fix_bad_cross_mode_jump_p (fixS *fixP) | |
15242 | { | |
15243 | unsigned long opcode; | |
15244 | int other; | |
15245 | char *buf; | |
15246 | ||
15247 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15248 | return FALSE; | |
15249 | ||
15250 | other = S_GET_OTHER (fixP->fx_addsy); | |
15251 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15252 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15253 | switch (fixP->fx_r_type) | |
15254 | { | |
15255 | case BFD_RELOC_MIPS_JMP: | |
15256 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); | |
15257 | case BFD_RELOC_MICROMIPS_JMP: | |
15258 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); | |
15259 | default: | |
15260 | return FALSE; | |
15261 | } | |
15262 | } | |
15263 | ||
15264 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX | |
15265 | jump to a symbol in the same ISA mode. */ | |
15266 | ||
15267 | static bfd_boolean | |
15268 | fix_bad_same_mode_jalx_p (fixS *fixP) | |
15269 | { | |
15270 | unsigned long opcode; | |
15271 | int other; | |
15272 | char *buf; | |
15273 | ||
15274 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15275 | return FALSE; | |
15276 | ||
15277 | other = S_GET_OTHER (fixP->fx_addsy); | |
15278 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15279 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; | |
15280 | switch (fixP->fx_r_type) | |
15281 | { | |
15282 | case BFD_RELOC_MIPS_JMP: | |
15283 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); | |
15284 | case BFD_RELOC_MIPS16_JMP: | |
15285 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); | |
15286 | case BFD_RELOC_MICROMIPS_JMP: | |
15287 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); | |
15288 | default: | |
15289 | return FALSE; | |
15290 | } | |
15291 | } | |
15292 | ||
15293 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump | |
15294 | to a symbol whose value plus addend is not aligned according to the | |
15295 | ultimate (after linker relaxation) jump instruction's immediate field | |
15296 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to | |
15297 | regular MIPS code, to (1 << 2). */ | |
15298 | ||
15299 | static bfd_boolean | |
15300 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) | |
15301 | { | |
15302 | bfd_boolean micro_to_mips_p; | |
15303 | valueT val; | |
15304 | int other; | |
15305 | ||
15306 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15307 | return FALSE; | |
15308 | ||
15309 | other = S_GET_OTHER (fixP->fx_addsy); | |
15310 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); | |
15311 | val += fixP->fx_offset; | |
15312 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15313 | && !ELF_ST_IS_MICROMIPS (other)); | |
15314 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) | |
15315 | != ELF_ST_IS_COMPRESSED (other)); | |
15316 | } | |
15317 | ||
15318 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch | |
15319 | to a symbol whose annotation indicates another ISA mode. For absolute | |
a6ebf616 MR |
15320 | symbols check the ISA bit instead. |
15321 | ||
15322 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS | |
15323 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular | |
15324 | MIPS symbols and associated with BAL instructions as these instructions | |
de194d85 | 15325 | may be converted to JALX by the linker. */ |
9d862524 MR |
15326 | |
15327 | static bfd_boolean | |
15328 | fix_bad_cross_mode_branch_p (fixS *fixP) | |
15329 | { | |
15330 | bfd_boolean absolute_p; | |
15331 | unsigned long opcode; | |
15332 | asection *symsec; | |
15333 | valueT val; | |
15334 | int other; | |
15335 | char *buf; | |
15336 | ||
8b10b0b3 MR |
15337 | if (mips_ignore_branch_isa) |
15338 | return FALSE; | |
15339 | ||
9d862524 MR |
15340 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
15341 | return FALSE; | |
15342 | ||
15343 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15344 | absolute_p = bfd_is_abs_section (symsec); | |
15345 | ||
15346 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; | |
15347 | other = S_GET_OTHER (fixP->fx_addsy); | |
15348 | ||
15349 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; | |
15350 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; | |
15351 | switch (fixP->fx_r_type) | |
15352 | { | |
15353 | case BFD_RELOC_16_PCREL_S2: | |
a6ebf616 MR |
15354 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
15355 | && opcode != 0x0411); | |
15356 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15357 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) | |
15358 | && opcode != 0x4060); | |
9d862524 MR |
15359 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15360 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15361 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); | |
15362 | case BFD_RELOC_MIPS16_16_PCREL_S1: | |
15363 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); | |
15364 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: | |
15365 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
9d862524 MR |
15366 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
15367 | default: | |
15368 | abort (); | |
15369 | } | |
15370 | } | |
15371 | ||
15372 | /* Return TRUE if the symbol plus addend associated with a regular MIPS | |
15373 | branch instruction pointed to by FIXP is not aligned according to the | |
15374 | branch instruction's immediate field requirement. We need the addend | |
15375 | to preserve the ISA bit and also the sum must not have bit 2 set. We | |
15376 | must explicitly OR in the ISA bit from symbol annotation as the bit | |
15377 | won't be set in the symbol's value then. */ | |
15378 | ||
15379 | static bfd_boolean | |
15380 | fix_bad_misaligned_branch_p (fixS *fixP) | |
15381 | { | |
15382 | bfd_boolean absolute_p; | |
15383 | asection *symsec; | |
15384 | valueT isa_bit; | |
15385 | valueT val; | |
15386 | valueT off; | |
15387 | int other; | |
15388 | ||
15389 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) | |
15390 | return FALSE; | |
15391 | ||
15392 | symsec = S_GET_SEGMENT (fixP->fx_addsy); | |
15393 | absolute_p = bfd_is_abs_section (symsec); | |
15394 | ||
15395 | val = S_GET_VALUE (fixP->fx_addsy); | |
15396 | other = S_GET_OTHER (fixP->fx_addsy); | |
15397 | off = fixP->fx_offset; | |
15398 | ||
15399 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); | |
15400 | val |= ELF_ST_IS_COMPRESSED (other); | |
15401 | val += off; | |
15402 | return (val & 0x3) != isa_bit; | |
15403 | } | |
15404 | ||
15405 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP | |
15406 | and its calculated value VAL. */ | |
15407 | ||
15408 | static void | |
15409 | fix_validate_branch (fixS *fixP, valueT val) | |
15410 | { | |
15411 | if (fixP->fx_done && (val & 0x3) != 0) | |
15412 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15413 | _("branch to misaligned address (0x%lx)"), | |
15414 | (long) (val + md_pcrel_from (fixP))); | |
15415 | else if (fix_bad_cross_mode_branch_p (fixP)) | |
15416 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15417 | _("branch to a symbol in another ISA mode")); | |
15418 | else if (fix_bad_misaligned_branch_p (fixP)) | |
15419 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15420 | _("branch to misaligned address (0x%lx)"), | |
15421 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15422 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) | |
15423 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15424 | _("cannot encode misaligned addend " | |
15425 | "in the relocatable field (0x%lx)"), | |
15426 | (long) fixP->fx_offset); | |
15427 | } | |
15428 | ||
252b5132 RH |
15429 | /* Apply a fixup to the object file. */ |
15430 | ||
94f592af | 15431 | void |
55cf6793 | 15432 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 15433 | { |
4d68580a | 15434 | char *buf; |
b886a2ab | 15435 | unsigned long insn; |
a7ebbfdf | 15436 | reloc_howto_type *howto; |
252b5132 | 15437 | |
d56a8dda RS |
15438 | if (fixP->fx_pcrel) |
15439 | switch (fixP->fx_r_type) | |
15440 | { | |
15441 | case BFD_RELOC_16_PCREL_S2: | |
c9775dde | 15442 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
d56a8dda RS |
15443 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15444 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15445 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
15446 | case BFD_RELOC_32_PCREL: | |
7361da2c AB |
15447 | case BFD_RELOC_MIPS_21_PCREL_S2: |
15448 | case BFD_RELOC_MIPS_26_PCREL_S2: | |
15449 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
15450 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15451 | case BFD_RELOC_HI16_S_PCREL: | |
15452 | case BFD_RELOC_LO16_PCREL: | |
d56a8dda RS |
15453 | break; |
15454 | ||
15455 | case BFD_RELOC_32: | |
15456 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
15457 | break; | |
15458 | ||
15459 | default: | |
15460 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15461 | _("PC-relative reference to a different section")); | |
15462 | break; | |
15463 | } | |
15464 | ||
15465 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations | |
15466 | that have no MIPS ELF equivalent. */ | |
15467 | if (fixP->fx_r_type != BFD_RELOC_8) | |
15468 | { | |
15469 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); | |
15470 | if (!howto) | |
15471 | return; | |
15472 | } | |
65551fa4 | 15473 | |
df58fc94 RS |
15474 | gas_assert (fixP->fx_size == 2 |
15475 | || fixP->fx_size == 4 | |
d56a8dda | 15476 | || fixP->fx_r_type == BFD_RELOC_8 |
90ecf173 MR |
15477 | || fixP->fx_r_type == BFD_RELOC_16 |
15478 | || fixP->fx_r_type == BFD_RELOC_64 | |
15479 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
15480 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB | |
df58fc94 | 15481 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
90ecf173 MR |
15482 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
15483 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
2f0c68f2 CM |
15484 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
15485 | || fixP->fx_r_type == BFD_RELOC_NONE); | |
252b5132 | 15486 | |
4d68580a | 15487 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 15488 | |
b1dca8ee RS |
15489 | /* Don't treat parts of a composite relocation as done. There are two |
15490 | reasons for this: | |
15491 | ||
15492 | (1) The second and third parts will be against 0 (RSS_UNDEF) but | |
15493 | should nevertheless be emitted if the first part is. | |
15494 | ||
15495 | (2) In normal usage, composite relocations are never assembly-time | |
15496 | constants. The easiest way of dealing with the pathological | |
15497 | exceptions is to generate a relocation against STN_UNDEF and | |
15498 | leave everything up to the linker. */ | |
3994f87e | 15499 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
252b5132 RH |
15500 | fixP->fx_done = 1; |
15501 | ||
15502 | switch (fixP->fx_r_type) | |
15503 | { | |
3f98094e DJ |
15504 | case BFD_RELOC_MIPS_TLS_GD: |
15505 | case BFD_RELOC_MIPS_TLS_LDM: | |
741d6ea8 JM |
15506 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
15507 | case BFD_RELOC_MIPS_TLS_DTPREL64: | |
3f98094e DJ |
15508 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
15509 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: | |
15510 | case BFD_RELOC_MIPS_TLS_GOTTPREL: | |
d0f13682 CLT |
15511 | case BFD_RELOC_MIPS_TLS_TPREL32: |
15512 | case BFD_RELOC_MIPS_TLS_TPREL64: | |
3f98094e DJ |
15513 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
15514 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: | |
df58fc94 RS |
15515 | case BFD_RELOC_MICROMIPS_TLS_GD: |
15516 | case BFD_RELOC_MICROMIPS_TLS_LDM: | |
15517 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: | |
15518 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: | |
15519 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: | |
15520 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: | |
15521 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: | |
d0f13682 CLT |
15522 | case BFD_RELOC_MIPS16_TLS_GD: |
15523 | case BFD_RELOC_MIPS16_TLS_LDM: | |
15524 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: | |
15525 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: | |
15526 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: | |
15527 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: | |
15528 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: | |
4512dafa MR |
15529 | if (fixP->fx_addsy) |
15530 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
15531 | else | |
15532 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15533 | _("TLS relocation against a constant")); | |
15534 | break; | |
3f98094e | 15535 | |
252b5132 | 15536 | case BFD_RELOC_MIPS_JMP: |
9d862524 MR |
15537 | case BFD_RELOC_MIPS16_JMP: |
15538 | case BFD_RELOC_MICROMIPS_JMP: | |
15539 | { | |
15540 | int shift; | |
15541 | ||
15542 | gas_assert (!fixP->fx_done); | |
15543 | ||
15544 | /* Shift is 2, unusually, for microMIPS JALX. */ | |
15545 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
15546 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) | |
15547 | shift = 1; | |
15548 | else | |
15549 | shift = 2; | |
15550 | ||
15551 | if (fix_bad_cross_mode_jump_p (fixP)) | |
15552 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15553 | _("jump to a symbol in another ISA mode")); | |
15554 | else if (fix_bad_same_mode_jalx_p (fixP)) | |
15555 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15556 | _("JALX to a symbol in the same ISA mode")); | |
15557 | else if (fix_bad_misaligned_jump_p (fixP, shift)) | |
15558 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15559 | _("jump to misaligned address (0x%lx)"), | |
15560 | (long) (S_GET_VALUE (fixP->fx_addsy) | |
15561 | + fixP->fx_offset)); | |
15562 | else if (HAVE_IN_PLACE_ADDENDS | |
15563 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) | |
15564 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15565 | _("cannot encode misaligned addend " | |
15566 | "in the relocatable field (0x%lx)"), | |
15567 | (long) fixP->fx_offset); | |
15568 | } | |
15569 | /* Fall through. */ | |
15570 | ||
e369bcce TS |
15571 | case BFD_RELOC_MIPS_SHIFT5: |
15572 | case BFD_RELOC_MIPS_SHIFT6: | |
15573 | case BFD_RELOC_MIPS_GOT_DISP: | |
15574 | case BFD_RELOC_MIPS_GOT_PAGE: | |
15575 | case BFD_RELOC_MIPS_GOT_OFST: | |
15576 | case BFD_RELOC_MIPS_SUB: | |
15577 | case BFD_RELOC_MIPS_INSERT_A: | |
15578 | case BFD_RELOC_MIPS_INSERT_B: | |
15579 | case BFD_RELOC_MIPS_DELETE: | |
15580 | case BFD_RELOC_MIPS_HIGHEST: | |
15581 | case BFD_RELOC_MIPS_HIGHER: | |
15582 | case BFD_RELOC_MIPS_SCN_DISP: | |
15583 | case BFD_RELOC_MIPS_REL16: | |
15584 | case BFD_RELOC_MIPS_RELGOT: | |
15585 | case BFD_RELOC_MIPS_JALR: | |
252b5132 RH |
15586 | case BFD_RELOC_HI16: |
15587 | case BFD_RELOC_HI16_S: | |
b886a2ab | 15588 | case BFD_RELOC_LO16: |
cdf6fd85 | 15589 | case BFD_RELOC_GPREL16: |
252b5132 RH |
15590 | case BFD_RELOC_MIPS_LITERAL: |
15591 | case BFD_RELOC_MIPS_CALL16: | |
15592 | case BFD_RELOC_MIPS_GOT16: | |
cdf6fd85 | 15593 | case BFD_RELOC_GPREL32: |
252b5132 RH |
15594 | case BFD_RELOC_MIPS_GOT_HI16: |
15595 | case BFD_RELOC_MIPS_GOT_LO16: | |
15596 | case BFD_RELOC_MIPS_CALL_HI16: | |
15597 | case BFD_RELOC_MIPS_CALL_LO16: | |
41947d9e MR |
15598 | case BFD_RELOC_HI16_S_PCREL: |
15599 | case BFD_RELOC_LO16_PCREL: | |
252b5132 | 15600 | case BFD_RELOC_MIPS16_GPREL: |
738e5348 RS |
15601 | case BFD_RELOC_MIPS16_GOT16: |
15602 | case BFD_RELOC_MIPS16_CALL16: | |
d6f16593 MR |
15603 | case BFD_RELOC_MIPS16_HI16: |
15604 | case BFD_RELOC_MIPS16_HI16_S: | |
b886a2ab | 15605 | case BFD_RELOC_MIPS16_LO16: |
df58fc94 RS |
15606 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
15607 | case BFD_RELOC_MICROMIPS_GOT_PAGE: | |
15608 | case BFD_RELOC_MICROMIPS_GOT_OFST: | |
15609 | case BFD_RELOC_MICROMIPS_SUB: | |
15610 | case BFD_RELOC_MICROMIPS_HIGHEST: | |
15611 | case BFD_RELOC_MICROMIPS_HIGHER: | |
15612 | case BFD_RELOC_MICROMIPS_SCN_DISP: | |
15613 | case BFD_RELOC_MICROMIPS_JALR: | |
15614 | case BFD_RELOC_MICROMIPS_HI16: | |
15615 | case BFD_RELOC_MICROMIPS_HI16_S: | |
b886a2ab | 15616 | case BFD_RELOC_MICROMIPS_LO16: |
df58fc94 RS |
15617 | case BFD_RELOC_MICROMIPS_GPREL16: |
15618 | case BFD_RELOC_MICROMIPS_LITERAL: | |
15619 | case BFD_RELOC_MICROMIPS_CALL16: | |
15620 | case BFD_RELOC_MICROMIPS_GOT16: | |
15621 | case BFD_RELOC_MICROMIPS_GOT_HI16: | |
15622 | case BFD_RELOC_MICROMIPS_GOT_LO16: | |
15623 | case BFD_RELOC_MICROMIPS_CALL_HI16: | |
15624 | case BFD_RELOC_MICROMIPS_CALL_LO16: | |
067ec077 | 15625 | case BFD_RELOC_MIPS_EH: |
b886a2ab RS |
15626 | if (fixP->fx_done) |
15627 | { | |
15628 | offsetT value; | |
15629 | ||
15630 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) | |
15631 | { | |
15632 | insn = read_reloc_insn (buf, fixP->fx_r_type); | |
15633 | if (mips16_reloc_p (fixP->fx_r_type)) | |
15634 | insn |= mips16_immed_extend (value, 16); | |
15635 | else | |
15636 | insn |= (value & 0xffff); | |
15637 | write_reloc_insn (buf, fixP->fx_r_type, insn); | |
15638 | } | |
15639 | else | |
15640 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15641 | _("unsupported constant in relocation")); |
b886a2ab | 15642 | } |
252b5132 RH |
15643 | break; |
15644 | ||
252b5132 RH |
15645 | case BFD_RELOC_64: |
15646 | /* This is handled like BFD_RELOC_32, but we output a sign | |
15647 | extended value if we are only 32 bits. */ | |
3e722fb5 | 15648 | if (fixP->fx_done) |
252b5132 RH |
15649 | { |
15650 | if (8 <= sizeof (valueT)) | |
4d68580a | 15651 | md_number_to_chars (buf, *valP, 8); |
252b5132 RH |
15652 | else |
15653 | { | |
a7ebbfdf | 15654 | valueT hiv; |
252b5132 | 15655 | |
a7ebbfdf | 15656 | if ((*valP & 0x80000000) != 0) |
252b5132 RH |
15657 | hiv = 0xffffffff; |
15658 | else | |
15659 | hiv = 0; | |
4d68580a RS |
15660 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
15661 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); | |
252b5132 RH |
15662 | } |
15663 | } | |
15664 | break; | |
15665 | ||
056350c6 | 15666 | case BFD_RELOC_RVA: |
252b5132 | 15667 | case BFD_RELOC_32: |
b47468a6 | 15668 | case BFD_RELOC_32_PCREL: |
252b5132 | 15669 | case BFD_RELOC_16: |
d56a8dda | 15670 | case BFD_RELOC_8: |
252b5132 | 15671 | /* If we are deleting this reloc entry, we must fill in the |
54f4ddb3 TS |
15672 | value now. This can happen if we have a .word which is not |
15673 | resolved when it appears but is later defined. */ | |
252b5132 | 15674 | if (fixP->fx_done) |
4d68580a | 15675 | md_number_to_chars (buf, *valP, fixP->fx_size); |
252b5132 RH |
15676 | break; |
15677 | ||
7361da2c | 15678 | case BFD_RELOC_MIPS_21_PCREL_S2: |
9d862524 | 15679 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15680 | if (!fixP->fx_done) |
15681 | break; | |
15682 | ||
15683 | if (*valP + 0x400000 <= 0x7fffff) | |
15684 | { | |
15685 | insn = read_insn (buf); | |
15686 | insn |= (*valP >> 2) & 0x1fffff; | |
15687 | write_insn (buf, insn); | |
15688 | } | |
15689 | else | |
15690 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15691 | _("branch out of range")); | |
15692 | break; | |
15693 | ||
7361da2c | 15694 | case BFD_RELOC_MIPS_26_PCREL_S2: |
9d862524 | 15695 | fix_validate_branch (fixP, *valP); |
41947d9e MR |
15696 | if (!fixP->fx_done) |
15697 | break; | |
7361da2c | 15698 | |
41947d9e MR |
15699 | if (*valP + 0x8000000 <= 0xfffffff) |
15700 | { | |
15701 | insn = read_insn (buf); | |
15702 | insn |= (*valP >> 2) & 0x3ffffff; | |
15703 | write_insn (buf, insn); | |
15704 | } | |
15705 | else | |
15706 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15707 | _("branch out of range")); | |
7361da2c AB |
15708 | break; |
15709 | ||
15710 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
717ba204 | 15711 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
7361da2c | 15712 | as_bad_where (fixP->fx_file, fixP->fx_line, |
0866e94c MF |
15713 | _("PC-relative access using misaligned symbol (%lx)"), |
15714 | (long) S_GET_VALUE (fixP->fx_addsy)); | |
15715 | if ((fixP->fx_offset & 0x7) != 0) | |
15716 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15717 | _("PC-relative access using misaligned offset (%lx)"), | |
15718 | (long) fixP->fx_offset); | |
41947d9e MR |
15719 | if (!fixP->fx_done) |
15720 | break; | |
7361da2c | 15721 | |
41947d9e MR |
15722 | if (*valP + 0x100000 <= 0x1fffff) |
15723 | { | |
15724 | insn = read_insn (buf); | |
15725 | insn |= (*valP >> 3) & 0x3ffff; | |
15726 | write_insn (buf, insn); | |
15727 | } | |
15728 | else | |
15729 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15730 | _("PC-relative access out of range")); | |
7361da2c AB |
15731 | break; |
15732 | ||
15733 | case BFD_RELOC_MIPS_19_PCREL_S2: | |
15734 | if ((*valP & 0x3) != 0) | |
15735 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15736 | _("PC-relative access to misaligned address (%lx)"), | |
717ba204 | 15737 | (long) *valP); |
41947d9e MR |
15738 | if (!fixP->fx_done) |
15739 | break; | |
7361da2c | 15740 | |
41947d9e MR |
15741 | if (*valP + 0x100000 <= 0x1fffff) |
15742 | { | |
15743 | insn = read_insn (buf); | |
15744 | insn |= (*valP >> 2) & 0x7ffff; | |
15745 | write_insn (buf, insn); | |
15746 | } | |
15747 | else | |
15748 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15749 | _("PC-relative access out of range")); | |
7361da2c AB |
15750 | break; |
15751 | ||
252b5132 | 15752 | case BFD_RELOC_16_PCREL_S2: |
9d862524 | 15753 | fix_validate_branch (fixP, *valP); |
cb56d3d3 | 15754 | |
54f4ddb3 TS |
15755 | /* We need to save the bits in the instruction since fixup_segment() |
15756 | might be deleting the relocation entry (i.e., a branch within | |
15757 | the current segment). */ | |
a7ebbfdf | 15758 | if (! fixP->fx_done) |
bb2d6cd7 | 15759 | break; |
252b5132 | 15760 | |
54f4ddb3 | 15761 | /* Update old instruction data. */ |
4d68580a | 15762 | insn = read_insn (buf); |
252b5132 | 15763 | |
a7ebbfdf TS |
15764 | if (*valP + 0x20000 <= 0x3ffff) |
15765 | { | |
15766 | insn |= (*valP >> 2) & 0xffff; | |
4d68580a | 15767 | write_insn (buf, insn); |
a7ebbfdf | 15768 | } |
ce8ad872 | 15769 | else if (fixP->fx_tcbit2 |
a7ebbfdf TS |
15770 | && fixP->fx_done |
15771 | && fixP->fx_frag->fr_address >= text_section->vma | |
15772 | && (fixP->fx_frag->fr_address | |
587aac4e | 15773 | < text_section->vma + bfd_get_section_size (text_section)) |
a7ebbfdf TS |
15774 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
15775 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ | |
15776 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ | |
252b5132 RH |
15777 | { |
15778 | /* The branch offset is too large. If this is an | |
15779 | unconditional branch, and we are not generating PIC code, | |
15780 | we can convert it to an absolute jump instruction. */ | |
a7ebbfdf TS |
15781 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
15782 | insn = 0x0c000000; /* jal */ | |
252b5132 | 15783 | else |
a7ebbfdf TS |
15784 | insn = 0x08000000; /* j */ |
15785 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; | |
15786 | fixP->fx_done = 0; | |
15787 | fixP->fx_addsy = section_symbol (text_section); | |
15788 | *valP += md_pcrel_from (fixP); | |
4d68580a | 15789 | write_insn (buf, insn); |
a7ebbfdf TS |
15790 | } |
15791 | else | |
15792 | { | |
15793 | /* If we got here, we have branch-relaxation disabled, | |
15794 | and there's nothing we can do to fix this instruction | |
15795 | without turning it into a longer sequence. */ | |
15796 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1661c76c | 15797 | _("branch out of range")); |
252b5132 | 15798 | } |
252b5132 RH |
15799 | break; |
15800 | ||
c9775dde | 15801 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
df58fc94 RS |
15802 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
15803 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: | |
15804 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: | |
96e9ba5f | 15805 | gas_assert (!fixP->fx_done); |
9d862524 MR |
15806 | if (fix_bad_cross_mode_branch_p (fixP)) |
15807 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15808 | _("branch to a symbol in another ISA mode")); | |
15809 | else if (fixP->fx_addsy | |
15810 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) | |
15811 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) | |
15812 | && (fixP->fx_offset & 0x1) != 0) | |
15813 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15814 | _("branch to misaligned address (0x%lx)"), | |
15815 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); | |
15816 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) | |
15817 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
15818 | _("cannot encode misaligned addend " | |
15819 | "in the relocatable field (0x%lx)"), | |
15820 | (long) fixP->fx_offset); | |
df58fc94 RS |
15821 | break; |
15822 | ||
252b5132 RH |
15823 | case BFD_RELOC_VTABLE_INHERIT: |
15824 | fixP->fx_done = 0; | |
15825 | if (fixP->fx_addsy | |
15826 | && !S_IS_DEFINED (fixP->fx_addsy) | |
15827 | && !S_IS_WEAK (fixP->fx_addsy)) | |
15828 | S_SET_WEAK (fixP->fx_addsy); | |
15829 | break; | |
15830 | ||
2f0c68f2 | 15831 | case BFD_RELOC_NONE: |
252b5132 RH |
15832 | case BFD_RELOC_VTABLE_ENTRY: |
15833 | fixP->fx_done = 0; | |
15834 | break; | |
15835 | ||
15836 | default: | |
b37df7c4 | 15837 | abort (); |
252b5132 | 15838 | } |
a7ebbfdf TS |
15839 | |
15840 | /* Remember value for tc_gen_reloc. */ | |
15841 | fixP->fx_addnumber = *valP; | |
252b5132 RH |
15842 | } |
15843 | ||
252b5132 | 15844 | static symbolS * |
17a2f251 | 15845 | get_symbol (void) |
252b5132 RH |
15846 | { |
15847 | int c; | |
15848 | char *name; | |
15849 | symbolS *p; | |
15850 | ||
d02603dc | 15851 | c = get_symbol_name (&name); |
252b5132 | 15852 | p = (symbolS *) symbol_find_or_make (name); |
d02603dc | 15853 | (void) restore_line_pointer (c); |
252b5132 RH |
15854 | return p; |
15855 | } | |
15856 | ||
742a56fe RS |
15857 | /* Align the current frag to a given power of two. If a particular |
15858 | fill byte should be used, FILL points to an integer that contains | |
15859 | that byte, otherwise FILL is null. | |
15860 | ||
462427c4 RS |
15861 | This function used to have the comment: |
15862 | ||
15863 | The MIPS assembler also automatically adjusts any preceding label. | |
15864 | ||
15865 | The implementation therefore applied the adjustment to a maximum of | |
15866 | one label. However, other label adjustments are applied to batches | |
15867 | of labels, and adjusting just one caused problems when new labels | |
15868 | were added for the sake of debugging or unwind information. | |
15869 | We therefore adjust all preceding labels (given as LABELS) instead. */ | |
252b5132 RH |
15870 | |
15871 | static void | |
462427c4 | 15872 | mips_align (int to, int *fill, struct insn_label_list *labels) |
252b5132 | 15873 | { |
7d10b47d | 15874 | mips_emit_delays (); |
df58fc94 | 15875 | mips_record_compressed_mode (); |
742a56fe RS |
15876 | if (fill == NULL && subseg_text_p (now_seg)) |
15877 | frag_align_code (to, 0); | |
15878 | else | |
15879 | frag_align (to, fill ? *fill : 0, 0); | |
252b5132 | 15880 | record_alignment (now_seg, to); |
462427c4 | 15881 | mips_move_labels (labels, FALSE); |
252b5132 RH |
15882 | } |
15883 | ||
15884 | /* Align to a given power of two. .align 0 turns off the automatic | |
15885 | alignment used by the data creating pseudo-ops. */ | |
15886 | ||
15887 | static void | |
17a2f251 | 15888 | s_align (int x ATTRIBUTE_UNUSED) |
252b5132 | 15889 | { |
742a56fe | 15890 | int temp, fill_value, *fill_ptr; |
49954fb4 | 15891 | long max_alignment = 28; |
252b5132 | 15892 | |
54f4ddb3 | 15893 | /* o Note that the assembler pulls down any immediately preceding label |
252b5132 | 15894 | to the aligned address. |
54f4ddb3 | 15895 | o It's not documented but auto alignment is reinstated by |
252b5132 | 15896 | a .align pseudo instruction. |
54f4ddb3 | 15897 | o Note also that after auto alignment is turned off the mips assembler |
252b5132 | 15898 | issues an error on attempt to assemble an improperly aligned data item. |
54f4ddb3 | 15899 | We don't. */ |
252b5132 RH |
15900 | |
15901 | temp = get_absolute_expression (); | |
15902 | if (temp > max_alignment) | |
1661c76c | 15903 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
252b5132 RH |
15904 | else if (temp < 0) |
15905 | { | |
1661c76c | 15906 | as_warn (_("alignment negative, 0 assumed")); |
252b5132 RH |
15907 | temp = 0; |
15908 | } | |
15909 | if (*input_line_pointer == ',') | |
15910 | { | |
f9419b05 | 15911 | ++input_line_pointer; |
742a56fe RS |
15912 | fill_value = get_absolute_expression (); |
15913 | fill_ptr = &fill_value; | |
252b5132 RH |
15914 | } |
15915 | else | |
742a56fe | 15916 | fill_ptr = 0; |
252b5132 RH |
15917 | if (temp) |
15918 | { | |
a8dbcb85 TS |
15919 | segment_info_type *si = seg_info (now_seg); |
15920 | struct insn_label_list *l = si->label_list; | |
54f4ddb3 | 15921 | /* Auto alignment should be switched on by next section change. */ |
252b5132 | 15922 | auto_align = 1; |
462427c4 | 15923 | mips_align (temp, fill_ptr, l); |
252b5132 RH |
15924 | } |
15925 | else | |
15926 | { | |
15927 | auto_align = 0; | |
15928 | } | |
15929 | ||
15930 | demand_empty_rest_of_line (); | |
15931 | } | |
15932 | ||
252b5132 | 15933 | static void |
17a2f251 | 15934 | s_change_sec (int sec) |
252b5132 RH |
15935 | { |
15936 | segT seg; | |
15937 | ||
252b5132 RH |
15938 | /* The ELF backend needs to know that we are changing sections, so |
15939 | that .previous works correctly. We could do something like check | |
b6ff326e | 15940 | for an obj_section_change_hook macro, but that might be confusing |
252b5132 RH |
15941 | as it would not be appropriate to use it in the section changing |
15942 | functions in read.c, since obj-elf.c intercepts those. FIXME: | |
15943 | This should be cleaner, somehow. */ | |
f3ded42a | 15944 | obj_elf_section_change_hook (); |
252b5132 | 15945 | |
7d10b47d | 15946 | mips_emit_delays (); |
6a32d874 | 15947 | |
252b5132 RH |
15948 | switch (sec) |
15949 | { | |
15950 | case 't': | |
15951 | s_text (0); | |
15952 | break; | |
15953 | case 'd': | |
15954 | s_data (0); | |
15955 | break; | |
15956 | case 'b': | |
15957 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); | |
15958 | demand_empty_rest_of_line (); | |
15959 | break; | |
15960 | ||
15961 | case 'r': | |
4d0d148d TS |
15962 | seg = subseg_new (RDATA_SECTION_NAME, |
15963 | (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15964 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
15965 | | SEC_READONLY | SEC_RELOC | |
15966 | | SEC_DATA)); | |
15967 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15968 | record_alignment (seg, 4); | |
4d0d148d | 15969 | demand_empty_rest_of_line (); |
252b5132 RH |
15970 | break; |
15971 | ||
15972 | case 's': | |
4d0d148d | 15973 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
f3ded42a RS |
15974 | bfd_set_section_flags (stdoutput, seg, |
15975 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); | |
15976 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15977 | record_alignment (seg, 4); | |
4d0d148d TS |
15978 | demand_empty_rest_of_line (); |
15979 | break; | |
998b3c36 MR |
15980 | |
15981 | case 'B': | |
15982 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); | |
f3ded42a RS |
15983 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
15984 | if (strncmp (TARGET_OS, "elf", 3) != 0) | |
15985 | record_alignment (seg, 4); | |
998b3c36 MR |
15986 | demand_empty_rest_of_line (); |
15987 | break; | |
252b5132 RH |
15988 | } |
15989 | ||
15990 | auto_align = 1; | |
15991 | } | |
b34976b6 | 15992 | |
cca86cc8 | 15993 | void |
17a2f251 | 15994 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
cca86cc8 | 15995 | { |
d02603dc | 15996 | char *saved_ilp; |
cca86cc8 | 15997 | char *section_name; |
d02603dc | 15998 | char c, endc; |
684022ea | 15999 | char next_c = 0; |
cca86cc8 SC |
16000 | int section_type; |
16001 | int section_flag; | |
16002 | int section_entry_size; | |
16003 | int section_alignment; | |
b34976b6 | 16004 | |
d02603dc NC |
16005 | saved_ilp = input_line_pointer; |
16006 | endc = get_symbol_name (§ion_name); | |
16007 | c = (endc == '"' ? input_line_pointer[1] : endc); | |
a816d1ed | 16008 | if (c) |
d02603dc | 16009 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
cca86cc8 | 16010 | |
4cf0dd0d TS |
16011 | /* Do we have .section Name<,"flags">? */ |
16012 | if (c != ',' || (c == ',' && next_c == '"')) | |
cca86cc8 | 16013 | { |
d02603dc NC |
16014 | /* Just after name is now '\0'. */ |
16015 | (void) restore_line_pointer (endc); | |
16016 | input_line_pointer = saved_ilp; | |
cca86cc8 SC |
16017 | obj_elf_section (ignore); |
16018 | return; | |
16019 | } | |
d02603dc NC |
16020 | |
16021 | section_name = xstrdup (section_name); | |
16022 | c = restore_line_pointer (endc); | |
16023 | ||
cca86cc8 SC |
16024 | input_line_pointer++; |
16025 | ||
16026 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ | |
16027 | if (c == ',') | |
16028 | section_type = get_absolute_expression (); | |
16029 | else | |
16030 | section_type = 0; | |
d02603dc | 16031 | |
cca86cc8 SC |
16032 | if (*input_line_pointer++ == ',') |
16033 | section_flag = get_absolute_expression (); | |
16034 | else | |
16035 | section_flag = 0; | |
d02603dc | 16036 | |
cca86cc8 SC |
16037 | if (*input_line_pointer++ == ',') |
16038 | section_entry_size = get_absolute_expression (); | |
16039 | else | |
16040 | section_entry_size = 0; | |
d02603dc | 16041 | |
cca86cc8 SC |
16042 | if (*input_line_pointer++ == ',') |
16043 | section_alignment = get_absolute_expression (); | |
16044 | else | |
16045 | section_alignment = 0; | |
d02603dc | 16046 | |
87975d2a AM |
16047 | /* FIXME: really ignore? */ |
16048 | (void) section_alignment; | |
cca86cc8 | 16049 | |
8ab8a5c8 RS |
16050 | /* When using the generic form of .section (as implemented by obj-elf.c), |
16051 | there's no way to set the section type to SHT_MIPS_DWARF. Users have | |
16052 | traditionally had to fall back on the more common @progbits instead. | |
16053 | ||
16054 | There's nothing really harmful in this, since bfd will correct | |
16055 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it | |
708587a4 | 16056 | means that, for backwards compatibility, the special_section entries |
8ab8a5c8 RS |
16057 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
16058 | ||
16059 | Even so, we shouldn't force users of the MIPS .section syntax to | |
16060 | incorrectly label the sections as SHT_PROGBITS. The best compromise | |
16061 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the | |
16062 | generic type-checking code. */ | |
16063 | if (section_type == SHT_MIPS_DWARF) | |
16064 | section_type = SHT_PROGBITS; | |
16065 | ||
a91e1603 | 16066 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
cca86cc8 | 16067 | section_entry_size, 0, 0, 0); |
a816d1ed AO |
16068 | |
16069 | if (now_seg->name != section_name) | |
16070 | free (section_name); | |
cca86cc8 | 16071 | } |
252b5132 RH |
16072 | |
16073 | void | |
17a2f251 | 16074 | mips_enable_auto_align (void) |
252b5132 RH |
16075 | { |
16076 | auto_align = 1; | |
16077 | } | |
16078 | ||
16079 | static void | |
17a2f251 | 16080 | s_cons (int log_size) |
252b5132 | 16081 | { |
a8dbcb85 TS |
16082 | segment_info_type *si = seg_info (now_seg); |
16083 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16084 | |
7d10b47d | 16085 | mips_emit_delays (); |
252b5132 | 16086 | if (log_size > 0 && auto_align) |
462427c4 | 16087 | mips_align (log_size, 0, l); |
252b5132 | 16088 | cons (1 << log_size); |
a1facbec | 16089 | mips_clear_insn_labels (); |
252b5132 RH |
16090 | } |
16091 | ||
16092 | static void | |
17a2f251 | 16093 | s_float_cons (int type) |
252b5132 | 16094 | { |
a8dbcb85 TS |
16095 | segment_info_type *si = seg_info (now_seg); |
16096 | struct insn_label_list *l = si->label_list; | |
252b5132 | 16097 | |
7d10b47d | 16098 | mips_emit_delays (); |
252b5132 RH |
16099 | |
16100 | if (auto_align) | |
49309057 ILT |
16101 | { |
16102 | if (type == 'd') | |
462427c4 | 16103 | mips_align (3, 0, l); |
49309057 | 16104 | else |
462427c4 | 16105 | mips_align (2, 0, l); |
49309057 | 16106 | } |
252b5132 | 16107 | |
252b5132 | 16108 | float_cons (type); |
a1facbec | 16109 | mips_clear_insn_labels (); |
252b5132 RH |
16110 | } |
16111 | ||
16112 | /* Handle .globl. We need to override it because on Irix 5 you are | |
16113 | permitted to say | |
16114 | .globl foo .text | |
16115 | where foo is an undefined symbol, to mean that foo should be | |
16116 | considered to be the address of a function. */ | |
16117 | ||
16118 | static void | |
17a2f251 | 16119 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16120 | { |
16121 | char *name; | |
16122 | int c; | |
16123 | symbolS *symbolP; | |
16124 | flagword flag; | |
16125 | ||
8a06b769 | 16126 | do |
252b5132 | 16127 | { |
d02603dc | 16128 | c = get_symbol_name (&name); |
8a06b769 TS |
16129 | symbolP = symbol_find_or_make (name); |
16130 | S_SET_EXTERNAL (symbolP); | |
16131 | ||
252b5132 | 16132 | *input_line_pointer = c; |
d02603dc | 16133 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 | 16134 | |
8a06b769 TS |
16135 | /* On Irix 5, every global symbol that is not explicitly labelled as |
16136 | being a function is apparently labelled as being an object. */ | |
16137 | flag = BSF_OBJECT; | |
252b5132 | 16138 | |
8a06b769 TS |
16139 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
16140 | && (*input_line_pointer != ',')) | |
16141 | { | |
16142 | char *secname; | |
16143 | asection *sec; | |
16144 | ||
d02603dc | 16145 | c = get_symbol_name (&secname); |
8a06b769 TS |
16146 | sec = bfd_get_section_by_name (stdoutput, secname); |
16147 | if (sec == NULL) | |
16148 | as_bad (_("%s: no such section"), secname); | |
d02603dc | 16149 | (void) restore_line_pointer (c); |
8a06b769 TS |
16150 | |
16151 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) | |
16152 | flag = BSF_FUNCTION; | |
16153 | } | |
16154 | ||
16155 | symbol_get_bfdsym (symbolP)->flags |= flag; | |
16156 | ||
16157 | c = *input_line_pointer; | |
16158 | if (c == ',') | |
16159 | { | |
16160 | input_line_pointer++; | |
16161 | SKIP_WHITESPACE (); | |
16162 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
16163 | c = '\n'; | |
16164 | } | |
16165 | } | |
16166 | while (c == ','); | |
252b5132 | 16167 | |
252b5132 RH |
16168 | demand_empty_rest_of_line (); |
16169 | } | |
16170 | ||
16171 | static void | |
17a2f251 | 16172 | s_option (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
16173 | { |
16174 | char *opt; | |
16175 | char c; | |
16176 | ||
d02603dc | 16177 | c = get_symbol_name (&opt); |
252b5132 RH |
16178 | |
16179 | if (*opt == 'O') | |
16180 | { | |
16181 | /* FIXME: What does this mean? */ | |
16182 | } | |
41a1578e | 16183 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
252b5132 RH |
16184 | { |
16185 | int i; | |
16186 | ||
16187 | i = atoi (opt + 3); | |
668c5ebc MR |
16188 | if (i != 0 && i != 2) |
16189 | as_bad (_(".option pic%d not supported"), i); | |
16190 | else if (mips_pic == VXWORKS_PIC) | |
16191 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); | |
16192 | else if (i == 0) | |
252b5132 RH |
16193 | mips_pic = NO_PIC; |
16194 | else if (i == 2) | |
143d77c5 | 16195 | { |
8b828383 | 16196 | mips_pic = SVR4_PIC; |
143d77c5 EC |
16197 | mips_abicalls = TRUE; |
16198 | } | |
252b5132 | 16199 | |
4d0d148d | 16200 | if (mips_pic == SVR4_PIC) |
252b5132 RH |
16201 | { |
16202 | if (g_switch_seen && g_switch_value != 0) | |
16203 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16204 | g_switch_value = 0; | |
16205 | bfd_set_gp_size (stdoutput, 0); | |
16206 | } | |
16207 | } | |
16208 | else | |
1661c76c | 16209 | as_warn (_("unrecognized option \"%s\""), opt); |
252b5132 | 16210 | |
d02603dc | 16211 | (void) restore_line_pointer (c); |
252b5132 RH |
16212 | demand_empty_rest_of_line (); |
16213 | } | |
16214 | ||
16215 | /* This structure is used to hold a stack of .set values. */ | |
16216 | ||
e972090a NC |
16217 | struct mips_option_stack |
16218 | { | |
252b5132 RH |
16219 | struct mips_option_stack *next; |
16220 | struct mips_set_options options; | |
16221 | }; | |
16222 | ||
16223 | static struct mips_option_stack *mips_opts_stack; | |
16224 | ||
22522f88 MR |
16225 | /* Return status for .set/.module option handling. */ |
16226 | ||
16227 | enum code_option_type | |
16228 | { | |
16229 | /* Unrecognized option. */ | |
16230 | OPTION_TYPE_BAD = -1, | |
16231 | ||
16232 | /* Ordinary option. */ | |
16233 | OPTION_TYPE_NORMAL, | |
16234 | ||
16235 | /* ISA changing option. */ | |
16236 | OPTION_TYPE_ISA | |
16237 | }; | |
16238 | ||
16239 | /* Handle common .set/.module options. Return status indicating option | |
16240 | type. */ | |
16241 | ||
16242 | static enum code_option_type | |
919731af | 16243 | parse_code_option (char * name) |
252b5132 | 16244 | { |
22522f88 | 16245 | bfd_boolean isa_set = FALSE; |
c6278170 | 16246 | const struct mips_ase *ase; |
22522f88 | 16247 | |
919731af | 16248 | if (strncmp (name, "at=", 3) == 0) |
741fe287 MR |
16249 | { |
16250 | char *s = name + 3; | |
16251 | ||
16252 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) | |
1661c76c | 16253 | as_bad (_("unrecognized register name `%s'"), s); |
741fe287 | 16254 | } |
252b5132 | 16255 | else if (strcmp (name, "at") == 0) |
919731af | 16256 | mips_opts.at = ATREG; |
252b5132 | 16257 | else if (strcmp (name, "noat") == 0) |
919731af | 16258 | mips_opts.at = ZERO; |
252b5132 | 16259 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
919731af | 16260 | mips_opts.nomove = 0; |
252b5132 | 16261 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
919731af | 16262 | mips_opts.nomove = 1; |
252b5132 | 16263 | else if (strcmp (name, "bopt") == 0) |
919731af | 16264 | mips_opts.nobopt = 0; |
252b5132 | 16265 | else if (strcmp (name, "nobopt") == 0) |
919731af | 16266 | mips_opts.nobopt = 1; |
ad3fea08 | 16267 | else if (strcmp (name, "gp=32") == 0) |
bad1aba3 | 16268 | mips_opts.gp = 32; |
ad3fea08 | 16269 | else if (strcmp (name, "gp=64") == 0) |
919731af | 16270 | mips_opts.gp = 64; |
ad3fea08 | 16271 | else if (strcmp (name, "fp=32") == 0) |
0b35dfee | 16272 | mips_opts.fp = 32; |
351cdf24 MF |
16273 | else if (strcmp (name, "fp=xx") == 0) |
16274 | mips_opts.fp = 0; | |
ad3fea08 | 16275 | else if (strcmp (name, "fp=64") == 0) |
919731af | 16276 | mips_opts.fp = 64; |
037b32b9 AN |
16277 | else if (strcmp (name, "softfloat") == 0) |
16278 | mips_opts.soft_float = 1; | |
16279 | else if (strcmp (name, "hardfloat") == 0) | |
16280 | mips_opts.soft_float = 0; | |
16281 | else if (strcmp (name, "singlefloat") == 0) | |
16282 | mips_opts.single_float = 1; | |
16283 | else if (strcmp (name, "doublefloat") == 0) | |
16284 | mips_opts.single_float = 0; | |
351cdf24 MF |
16285 | else if (strcmp (name, "nooddspreg") == 0) |
16286 | mips_opts.oddspreg = 0; | |
16287 | else if (strcmp (name, "oddspreg") == 0) | |
16288 | mips_opts.oddspreg = 1; | |
252b5132 RH |
16289 | else if (strcmp (name, "mips16") == 0 |
16290 | || strcmp (name, "MIPS-16") == 0) | |
919731af | 16291 | mips_opts.mips16 = 1; |
252b5132 RH |
16292 | else if (strcmp (name, "nomips16") == 0 |
16293 | || strcmp (name, "noMIPS-16") == 0) | |
16294 | mips_opts.mips16 = 0; | |
df58fc94 | 16295 | else if (strcmp (name, "micromips") == 0) |
919731af | 16296 | mips_opts.micromips = 1; |
df58fc94 RS |
16297 | else if (strcmp (name, "nomicromips") == 0) |
16298 | mips_opts.micromips = 0; | |
c6278170 RS |
16299 | else if (name[0] == 'n' |
16300 | && name[1] == 'o' | |
16301 | && (ase = mips_lookup_ase (name + 2))) | |
919731af | 16302 | mips_set_ase (ase, &mips_opts, FALSE); |
c6278170 | 16303 | else if ((ase = mips_lookup_ase (name))) |
919731af | 16304 | mips_set_ase (ase, &mips_opts, TRUE); |
1a2c1fad | 16305 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
252b5132 | 16306 | { |
1a2c1fad CD |
16307 | /* Permit the user to change the ISA and architecture on the fly. |
16308 | Needless to say, misuse can cause serious problems. */ | |
919731af | 16309 | if (strncmp (name, "arch=", 5) == 0) |
1a2c1fad CD |
16310 | { |
16311 | const struct mips_cpu_info *p; | |
16312 | ||
919731af | 16313 | p = mips_parse_cpu ("internal use", name + 5); |
1a2c1fad CD |
16314 | if (!p) |
16315 | as_bad (_("unknown architecture %s"), name + 5); | |
16316 | else | |
16317 | { | |
16318 | mips_opts.arch = p->cpu; | |
16319 | mips_opts.isa = p->isa; | |
22522f88 | 16320 | isa_set = TRUE; |
1a2c1fad CD |
16321 | } |
16322 | } | |
81a21e38 TS |
16323 | else if (strncmp (name, "mips", 4) == 0) |
16324 | { | |
16325 | const struct mips_cpu_info *p; | |
16326 | ||
919731af | 16327 | p = mips_parse_cpu ("internal use", name); |
81a21e38 TS |
16328 | if (!p) |
16329 | as_bad (_("unknown ISA level %s"), name + 4); | |
16330 | else | |
16331 | { | |
16332 | mips_opts.arch = p->cpu; | |
16333 | mips_opts.isa = p->isa; | |
22522f88 | 16334 | isa_set = TRUE; |
81a21e38 TS |
16335 | } |
16336 | } | |
af7ee8bf | 16337 | else |
81a21e38 | 16338 | as_bad (_("unknown ISA or architecture %s"), name); |
252b5132 RH |
16339 | } |
16340 | else if (strcmp (name, "autoextend") == 0) | |
16341 | mips_opts.noautoextend = 0; | |
16342 | else if (strcmp (name, "noautoextend") == 0) | |
16343 | mips_opts.noautoextend = 1; | |
833794fc MR |
16344 | else if (strcmp (name, "insn32") == 0) |
16345 | mips_opts.insn32 = TRUE; | |
16346 | else if (strcmp (name, "noinsn32") == 0) | |
16347 | mips_opts.insn32 = FALSE; | |
919731af | 16348 | else if (strcmp (name, "sym32") == 0) |
16349 | mips_opts.sym32 = TRUE; | |
16350 | else if (strcmp (name, "nosym32") == 0) | |
16351 | mips_opts.sym32 = FALSE; | |
16352 | else | |
22522f88 MR |
16353 | return OPTION_TYPE_BAD; |
16354 | ||
16355 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; | |
919731af | 16356 | } |
16357 | ||
16358 | /* Handle the .set pseudo-op. */ | |
16359 | ||
16360 | static void | |
16361 | s_mipsset (int x ATTRIBUTE_UNUSED) | |
16362 | { | |
22522f88 | 16363 | enum code_option_type type = OPTION_TYPE_NORMAL; |
919731af | 16364 | char *name = input_line_pointer, ch; |
919731af | 16365 | |
16366 | file_mips_check_options (); | |
16367 | ||
16368 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16369 | ++input_line_pointer; | |
16370 | ch = *input_line_pointer; | |
16371 | *input_line_pointer = '\0'; | |
16372 | ||
16373 | if (strchr (name, ',')) | |
16374 | { | |
16375 | /* Generic ".set" directive; use the generic handler. */ | |
16376 | *input_line_pointer = ch; | |
16377 | input_line_pointer = name; | |
16378 | s_set (0); | |
16379 | return; | |
16380 | } | |
16381 | ||
16382 | if (strcmp (name, "reorder") == 0) | |
16383 | { | |
16384 | if (mips_opts.noreorder) | |
16385 | end_noreorder (); | |
16386 | } | |
16387 | else if (strcmp (name, "noreorder") == 0) | |
16388 | { | |
16389 | if (!mips_opts.noreorder) | |
16390 | start_noreorder (); | |
16391 | } | |
16392 | else if (strcmp (name, "macro") == 0) | |
16393 | mips_opts.warn_about_macros = 0; | |
16394 | else if (strcmp (name, "nomacro") == 0) | |
16395 | { | |
16396 | if (mips_opts.noreorder == 0) | |
16397 | as_bad (_("`noreorder' must be set before `nomacro'")); | |
16398 | mips_opts.warn_about_macros = 1; | |
16399 | } | |
16400 | else if (strcmp (name, "gp=default") == 0) | |
16401 | mips_opts.gp = file_mips_opts.gp; | |
16402 | else if (strcmp (name, "fp=default") == 0) | |
16403 | mips_opts.fp = file_mips_opts.fp; | |
16404 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) | |
16405 | { | |
16406 | mips_opts.isa = file_mips_opts.isa; | |
16407 | mips_opts.arch = file_mips_opts.arch; | |
16408 | mips_opts.gp = file_mips_opts.gp; | |
16409 | mips_opts.fp = file_mips_opts.fp; | |
16410 | } | |
252b5132 RH |
16411 | else if (strcmp (name, "push") == 0) |
16412 | { | |
16413 | struct mips_option_stack *s; | |
16414 | ||
325801bd | 16415 | s = XNEW (struct mips_option_stack); |
252b5132 RH |
16416 | s->next = mips_opts_stack; |
16417 | s->options = mips_opts; | |
16418 | mips_opts_stack = s; | |
16419 | } | |
16420 | else if (strcmp (name, "pop") == 0) | |
16421 | { | |
16422 | struct mips_option_stack *s; | |
16423 | ||
16424 | s = mips_opts_stack; | |
16425 | if (s == NULL) | |
16426 | as_bad (_(".set pop with no .set push")); | |
16427 | else | |
16428 | { | |
16429 | /* If we're changing the reorder mode we need to handle | |
16430 | delay slots correctly. */ | |
16431 | if (s->options.noreorder && ! mips_opts.noreorder) | |
7d10b47d | 16432 | start_noreorder (); |
252b5132 | 16433 | else if (! s->options.noreorder && mips_opts.noreorder) |
7d10b47d | 16434 | end_noreorder (); |
252b5132 RH |
16435 | |
16436 | mips_opts = s->options; | |
16437 | mips_opts_stack = s->next; | |
16438 | free (s); | |
16439 | } | |
16440 | } | |
22522f88 MR |
16441 | else |
16442 | { | |
16443 | type = parse_code_option (name); | |
16444 | if (type == OPTION_TYPE_BAD) | |
16445 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); | |
16446 | } | |
919731af | 16447 | |
16448 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp | |
16449 | registers based on what is supported by the arch/cpu. */ | |
22522f88 | 16450 | if (type == OPTION_TYPE_ISA) |
e6559e01 | 16451 | { |
919731af | 16452 | switch (mips_opts.isa) |
16453 | { | |
16454 | case 0: | |
16455 | break; | |
16456 | case ISA_MIPS1: | |
351cdf24 MF |
16457 | /* MIPS I cannot support FPXX. */ |
16458 | mips_opts.fp = 32; | |
16459 | /* fall-through. */ | |
919731af | 16460 | case ISA_MIPS2: |
16461 | case ISA_MIPS32: | |
16462 | case ISA_MIPS32R2: | |
16463 | case ISA_MIPS32R3: | |
16464 | case ISA_MIPS32R5: | |
16465 | mips_opts.gp = 32; | |
351cdf24 MF |
16466 | if (mips_opts.fp != 0) |
16467 | mips_opts.fp = 32; | |
919731af | 16468 | break; |
7361da2c AB |
16469 | case ISA_MIPS32R6: |
16470 | mips_opts.gp = 32; | |
16471 | mips_opts.fp = 64; | |
16472 | break; | |
919731af | 16473 | case ISA_MIPS3: |
16474 | case ISA_MIPS4: | |
16475 | case ISA_MIPS5: | |
16476 | case ISA_MIPS64: | |
16477 | case ISA_MIPS64R2: | |
16478 | case ISA_MIPS64R3: | |
16479 | case ISA_MIPS64R5: | |
7361da2c | 16480 | case ISA_MIPS64R6: |
919731af | 16481 | mips_opts.gp = 64; |
351cdf24 MF |
16482 | if (mips_opts.fp != 0) |
16483 | { | |
16484 | if (mips_opts.arch == CPU_R5900) | |
16485 | mips_opts.fp = 32; | |
16486 | else | |
16487 | mips_opts.fp = 64; | |
16488 | } | |
919731af | 16489 | break; |
16490 | default: | |
16491 | as_bad (_("unknown ISA level %s"), name + 4); | |
16492 | break; | |
16493 | } | |
e6559e01 | 16494 | } |
919731af | 16495 | |
16496 | mips_check_options (&mips_opts, FALSE); | |
16497 | ||
16498 | mips_check_isa_supports_ases (); | |
16499 | *input_line_pointer = ch; | |
16500 | demand_empty_rest_of_line (); | |
16501 | } | |
16502 | ||
16503 | /* Handle the .module pseudo-op. */ | |
16504 | ||
16505 | static void | |
16506 | s_module (int ignore ATTRIBUTE_UNUSED) | |
16507 | { | |
16508 | char *name = input_line_pointer, ch; | |
16509 | ||
16510 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
16511 | ++input_line_pointer; | |
16512 | ch = *input_line_pointer; | |
16513 | *input_line_pointer = '\0'; | |
16514 | ||
16515 | if (!file_mips_opts_checked) | |
252b5132 | 16516 | { |
22522f88 | 16517 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
919731af | 16518 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
16519 | ||
16520 | /* Update module level settings from mips_opts. */ | |
16521 | file_mips_opts = mips_opts; | |
252b5132 | 16522 | } |
919731af | 16523 | else |
16524 | as_bad (_(".module is not permitted after generating code")); | |
16525 | ||
252b5132 RH |
16526 | *input_line_pointer = ch; |
16527 | demand_empty_rest_of_line (); | |
16528 | } | |
16529 | ||
16530 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to | |
16531 | .option pic2. It means to generate SVR4 PIC calls. */ | |
16532 | ||
16533 | static void | |
17a2f251 | 16534 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16535 | { |
16536 | mips_pic = SVR4_PIC; | |
143d77c5 | 16537 | mips_abicalls = TRUE; |
4d0d148d TS |
16538 | |
16539 | if (g_switch_seen && g_switch_value != 0) | |
16540 | as_warn (_("-G may not be used with SVR4 PIC code")); | |
16541 | g_switch_value = 0; | |
16542 | ||
252b5132 RH |
16543 | bfd_set_gp_size (stdoutput, 0); |
16544 | demand_empty_rest_of_line (); | |
16545 | } | |
16546 | ||
16547 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 | |
16548 | PIC code. It sets the $gp register for the function based on the | |
16549 | function address, which is in the register named in the argument. | |
16550 | This uses a relocation against _gp_disp, which is handled specially | |
16551 | by the linker. The result is: | |
16552 | lui $gp,%hi(_gp_disp) | |
16553 | addiu $gp,$gp,%lo(_gp_disp) | |
16554 | addu $gp,$gp,.cpload argument | |
aa6975fb ILT |
16555 | The .cpload argument is normally $25 == $t9. |
16556 | ||
16557 | The -mno-shared option changes this to: | |
bbe506e8 TS |
16558 | lui $gp,%hi(__gnu_local_gp) |
16559 | addiu $gp,$gp,%lo(__gnu_local_gp) | |
aa6975fb ILT |
16560 | and the argument is ignored. This saves an instruction, but the |
16561 | resulting code is not position independent; it uses an absolute | |
bbe506e8 TS |
16562 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
16563 | can go into an ordinary executable, but not into a shared library. */ | |
252b5132 RH |
16564 | |
16565 | static void | |
17a2f251 | 16566 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16567 | { |
16568 | expressionS ex; | |
aa6975fb ILT |
16569 | int reg; |
16570 | int in_shared; | |
252b5132 | 16571 | |
919731af | 16572 | file_mips_check_options (); |
16573 | ||
6478892d TS |
16574 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
16575 | .cpload is ignored. */ | |
16576 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) | |
252b5132 RH |
16577 | { |
16578 | s_ignore (0); | |
16579 | return; | |
16580 | } | |
16581 | ||
a276b80c MR |
16582 | if (mips_opts.mips16) |
16583 | { | |
16584 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); | |
16585 | ignore_rest_of_line (); | |
16586 | return; | |
16587 | } | |
16588 | ||
d3ecfc59 | 16589 | /* .cpload should be in a .set noreorder section. */ |
252b5132 RH |
16590 | if (mips_opts.noreorder == 0) |
16591 | as_warn (_(".cpload not in noreorder section")); | |
16592 | ||
aa6975fb ILT |
16593 | reg = tc_get_register (0); |
16594 | ||
16595 | /* If we need to produce a 64-bit address, we are better off using | |
16596 | the default instruction sequence. */ | |
aed1a261 | 16597 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
aa6975fb | 16598 | |
252b5132 | 16599 | ex.X_op = O_symbol; |
bbe506e8 TS |
16600 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
16601 | "__gnu_local_gp"); | |
252b5132 RH |
16602 | ex.X_op_symbol = NULL; |
16603 | ex.X_add_number = 0; | |
16604 | ||
16605 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ | |
49309057 | 16606 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
252b5132 | 16607 | |
8a75745d MR |
16608 | mips_mark_labels (); |
16609 | mips_assembling_insn = TRUE; | |
16610 | ||
584892a6 | 16611 | macro_start (); |
67c0d1eb RS |
16612 | macro_build_lui (&ex, mips_gp_register); |
16613 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
17a2f251 | 16614 | mips_gp_register, BFD_RELOC_LO16); |
aa6975fb ILT |
16615 | if (in_shared) |
16616 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, | |
16617 | mips_gp_register, reg); | |
584892a6 | 16618 | macro_end (); |
252b5132 | 16619 | |
8a75745d | 16620 | mips_assembling_insn = FALSE; |
252b5132 RH |
16621 | demand_empty_rest_of_line (); |
16622 | } | |
16623 | ||
6478892d TS |
16624 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
16625 | .cpsetup $reg1, offset|$reg2, label | |
16626 | ||
16627 | If offset is given, this results in: | |
16628 | sd $gp, offset($sp) | |
956cd1d6 | 16629 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16630 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16631 | daddu $gp, $gp, $reg1 | |
6478892d TS |
16632 | |
16633 | If $reg2 is given, this results in: | |
40fc1451 | 16634 | or $reg2, $gp, $0 |
956cd1d6 | 16635 | lui $gp, %hi(%neg(%gp_rel(label))) |
698b7d9d TS |
16636 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
16637 | daddu $gp, $gp, $reg1 | |
aa6975fb ILT |
16638 | $reg1 is normally $25 == $t9. |
16639 | ||
16640 | The -mno-shared option replaces the last three instructions with | |
16641 | lui $gp,%hi(_gp) | |
54f4ddb3 | 16642 | addiu $gp,$gp,%lo(_gp) */ |
aa6975fb | 16643 | |
6478892d | 16644 | static void |
17a2f251 | 16645 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16646 | { |
16647 | expressionS ex_off; | |
16648 | expressionS ex_sym; | |
16649 | int reg1; | |
6478892d | 16650 | |
919731af | 16651 | file_mips_check_options (); |
16652 | ||
8586fc66 | 16653 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
6478892d TS |
16654 | We also need NewABI support. */ |
16655 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16656 | { | |
16657 | s_ignore (0); | |
16658 | return; | |
16659 | } | |
16660 | ||
a276b80c MR |
16661 | if (mips_opts.mips16) |
16662 | { | |
16663 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); | |
16664 | ignore_rest_of_line (); | |
16665 | return; | |
16666 | } | |
16667 | ||
6478892d TS |
16668 | reg1 = tc_get_register (0); |
16669 | SKIP_WHITESPACE (); | |
16670 | if (*input_line_pointer != ',') | |
16671 | { | |
16672 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16673 | return; | |
16674 | } | |
16675 | else | |
80245285 | 16676 | ++input_line_pointer; |
6478892d TS |
16677 | SKIP_WHITESPACE (); |
16678 | if (*input_line_pointer == '$') | |
80245285 TS |
16679 | { |
16680 | mips_cpreturn_register = tc_get_register (0); | |
16681 | mips_cpreturn_offset = -1; | |
16682 | } | |
6478892d | 16683 | else |
80245285 TS |
16684 | { |
16685 | mips_cpreturn_offset = get_absolute_expression (); | |
16686 | mips_cpreturn_register = -1; | |
16687 | } | |
6478892d TS |
16688 | SKIP_WHITESPACE (); |
16689 | if (*input_line_pointer != ',') | |
16690 | { | |
16691 | as_bad (_("missing argument separator ',' for .cpsetup")); | |
16692 | return; | |
16693 | } | |
16694 | else | |
f9419b05 | 16695 | ++input_line_pointer; |
6478892d | 16696 | SKIP_WHITESPACE (); |
f21f8242 | 16697 | expression (&ex_sym); |
6478892d | 16698 | |
8a75745d MR |
16699 | mips_mark_labels (); |
16700 | mips_assembling_insn = TRUE; | |
16701 | ||
584892a6 | 16702 | macro_start (); |
6478892d TS |
16703 | if (mips_cpreturn_register == -1) |
16704 | { | |
16705 | ex_off.X_op = O_constant; | |
16706 | ex_off.X_add_symbol = NULL; | |
16707 | ex_off.X_op_symbol = NULL; | |
16708 | ex_off.X_add_number = mips_cpreturn_offset; | |
16709 | ||
67c0d1eb | 16710 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
17a2f251 | 16711 | BFD_RELOC_LO16, SP); |
6478892d TS |
16712 | } |
16713 | else | |
40fc1451 | 16714 | move_register (mips_cpreturn_register, mips_gp_register); |
6478892d | 16715 | |
aed1a261 | 16716 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
aa6975fb | 16717 | { |
df58fc94 | 16718 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
aa6975fb ILT |
16719 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
16720 | BFD_RELOC_HI16_S); | |
16721 | ||
16722 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, | |
16723 | mips_gp_register, -1, BFD_RELOC_GPREL16, | |
16724 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); | |
16725 | ||
16726 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, | |
16727 | mips_gp_register, reg1); | |
16728 | } | |
16729 | else | |
16730 | { | |
16731 | expressionS ex; | |
16732 | ||
16733 | ex.X_op = O_symbol; | |
4184909a | 16734 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
aa6975fb ILT |
16735 | ex.X_op_symbol = NULL; |
16736 | ex.X_add_number = 0; | |
6e1304d8 | 16737 | |
aa6975fb ILT |
16738 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
16739 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; | |
16740 | ||
16741 | macro_build_lui (&ex, mips_gp_register); | |
16742 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, | |
16743 | mips_gp_register, BFD_RELOC_LO16); | |
16744 | } | |
f21f8242 | 16745 | |
584892a6 | 16746 | macro_end (); |
6478892d | 16747 | |
8a75745d | 16748 | mips_assembling_insn = FALSE; |
6478892d TS |
16749 | demand_empty_rest_of_line (); |
16750 | } | |
16751 | ||
16752 | static void | |
17a2f251 | 16753 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
6478892d | 16754 | { |
919731af | 16755 | file_mips_check_options (); |
16756 | ||
6478892d | 16757 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
54f4ddb3 | 16758 | .cplocal is ignored. */ |
6478892d TS |
16759 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
16760 | { | |
16761 | s_ignore (0); | |
16762 | return; | |
16763 | } | |
16764 | ||
a276b80c MR |
16765 | if (mips_opts.mips16) |
16766 | { | |
16767 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); | |
16768 | ignore_rest_of_line (); | |
16769 | return; | |
16770 | } | |
16771 | ||
6478892d | 16772 | mips_gp_register = tc_get_register (0); |
85b51719 | 16773 | demand_empty_rest_of_line (); |
6478892d TS |
16774 | } |
16775 | ||
252b5132 RH |
16776 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
16777 | offset from $sp. The offset is remembered, and after making a PIC | |
16778 | call $gp is restored from that location. */ | |
16779 | ||
16780 | static void | |
17a2f251 | 16781 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
16782 | { |
16783 | expressionS ex; | |
252b5132 | 16784 | |
919731af | 16785 | file_mips_check_options (); |
16786 | ||
6478892d | 16787 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
c9914766 | 16788 | .cprestore is ignored. */ |
6478892d | 16789 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
252b5132 RH |
16790 | { |
16791 | s_ignore (0); | |
16792 | return; | |
16793 | } | |
16794 | ||
a276b80c MR |
16795 | if (mips_opts.mips16) |
16796 | { | |
16797 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); | |
16798 | ignore_rest_of_line (); | |
16799 | return; | |
16800 | } | |
16801 | ||
252b5132 | 16802 | mips_cprestore_offset = get_absolute_expression (); |
7a621144 | 16803 | mips_cprestore_valid = 1; |
252b5132 RH |
16804 | |
16805 | ex.X_op = O_constant; | |
16806 | ex.X_add_symbol = NULL; | |
16807 | ex.X_op_symbol = NULL; | |
16808 | ex.X_add_number = mips_cprestore_offset; | |
16809 | ||
8a75745d MR |
16810 | mips_mark_labels (); |
16811 | mips_assembling_insn = TRUE; | |
16812 | ||
584892a6 | 16813 | macro_start (); |
67c0d1eb RS |
16814 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
16815 | SP, HAVE_64BIT_ADDRESSES); | |
584892a6 | 16816 | macro_end (); |
252b5132 | 16817 | |
8a75745d | 16818 | mips_assembling_insn = FALSE; |
252b5132 RH |
16819 | demand_empty_rest_of_line (); |
16820 | } | |
16821 | ||
6478892d | 16822 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
67c1ffbe | 16823 | was given in the preceding .cpsetup, it results in: |
6478892d | 16824 | ld $gp, offset($sp) |
76b3015f | 16825 | |
6478892d | 16826 | If a register $reg2 was given there, it results in: |
40fc1451 | 16827 | or $gp, $reg2, $0 */ |
54f4ddb3 | 16828 | |
6478892d | 16829 | static void |
17a2f251 | 16830 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16831 | { |
16832 | expressionS ex; | |
6478892d | 16833 | |
919731af | 16834 | file_mips_check_options (); |
16835 | ||
6478892d TS |
16836 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
16837 | We also need NewABI support. */ | |
16838 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16839 | { | |
16840 | s_ignore (0); | |
16841 | return; | |
16842 | } | |
16843 | ||
a276b80c MR |
16844 | if (mips_opts.mips16) |
16845 | { | |
16846 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); | |
16847 | ignore_rest_of_line (); | |
16848 | return; | |
16849 | } | |
16850 | ||
8a75745d MR |
16851 | mips_mark_labels (); |
16852 | mips_assembling_insn = TRUE; | |
16853 | ||
584892a6 | 16854 | macro_start (); |
6478892d TS |
16855 | if (mips_cpreturn_register == -1) |
16856 | { | |
16857 | ex.X_op = O_constant; | |
16858 | ex.X_add_symbol = NULL; | |
16859 | ex.X_op_symbol = NULL; | |
16860 | ex.X_add_number = mips_cpreturn_offset; | |
16861 | ||
67c0d1eb | 16862 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
6478892d TS |
16863 | } |
16864 | else | |
40fc1451 SD |
16865 | move_register (mips_gp_register, mips_cpreturn_register); |
16866 | ||
584892a6 | 16867 | macro_end (); |
6478892d | 16868 | |
8a75745d | 16869 | mips_assembling_insn = FALSE; |
6478892d TS |
16870 | demand_empty_rest_of_line (); |
16871 | } | |
16872 | ||
d0f13682 CLT |
16873 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
16874 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size | |
16875 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF | |
16876 | debug information or MIPS16 TLS. */ | |
741d6ea8 JM |
16877 | |
16878 | static void | |
d0f13682 CLT |
16879 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
16880 | bfd_reloc_code_real_type rtype) | |
741d6ea8 JM |
16881 | { |
16882 | expressionS ex; | |
16883 | char *p; | |
16884 | ||
16885 | expression (&ex); | |
16886 | ||
16887 | if (ex.X_op != O_symbol) | |
16888 | { | |
1661c76c | 16889 | as_bad (_("unsupported use of %s"), dirstr); |
741d6ea8 JM |
16890 | ignore_rest_of_line (); |
16891 | } | |
16892 | ||
16893 | p = frag_more (bytes); | |
16894 | md_number_to_chars (p, 0, bytes); | |
d0f13682 | 16895 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
741d6ea8 | 16896 | demand_empty_rest_of_line (); |
de64cffd | 16897 | mips_clear_insn_labels (); |
741d6ea8 JM |
16898 | } |
16899 | ||
16900 | /* Handle .dtprelword. */ | |
16901 | ||
16902 | static void | |
16903 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) | |
16904 | { | |
d0f13682 | 16905 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
741d6ea8 JM |
16906 | } |
16907 | ||
16908 | /* Handle .dtpreldword. */ | |
16909 | ||
16910 | static void | |
16911 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) | |
16912 | { | |
d0f13682 CLT |
16913 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
16914 | } | |
16915 | ||
16916 | /* Handle .tprelword. */ | |
16917 | ||
16918 | static void | |
16919 | s_tprelword (int ignore ATTRIBUTE_UNUSED) | |
16920 | { | |
16921 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); | |
16922 | } | |
16923 | ||
16924 | /* Handle .tpreldword. */ | |
16925 | ||
16926 | static void | |
16927 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) | |
16928 | { | |
16929 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); | |
741d6ea8 JM |
16930 | } |
16931 | ||
6478892d TS |
16932 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
16933 | code. It sets the offset to use in gp_rel relocations. */ | |
16934 | ||
16935 | static void | |
17a2f251 | 16936 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
6478892d TS |
16937 | { |
16938 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. | |
16939 | We also need NewABI support. */ | |
16940 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) | |
16941 | { | |
16942 | s_ignore (0); | |
16943 | return; | |
16944 | } | |
16945 | ||
def2e0dd | 16946 | mips_gprel_offset = get_absolute_expression (); |
6478892d TS |
16947 | |
16948 | demand_empty_rest_of_line (); | |
16949 | } | |
16950 | ||
252b5132 RH |
16951 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
16952 | code. It generates a 32 bit GP relative reloc. */ | |
16953 | ||
16954 | static void | |
17a2f251 | 16955 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 16956 | { |
a8dbcb85 TS |
16957 | segment_info_type *si; |
16958 | struct insn_label_list *l; | |
252b5132 RH |
16959 | expressionS ex; |
16960 | char *p; | |
16961 | ||
16962 | /* When not generating PIC code, this is treated as .word. */ | |
16963 | if (mips_pic != SVR4_PIC) | |
16964 | { | |
16965 | s_cons (2); | |
16966 | return; | |
16967 | } | |
16968 | ||
a8dbcb85 TS |
16969 | si = seg_info (now_seg); |
16970 | l = si->label_list; | |
7d10b47d | 16971 | mips_emit_delays (); |
252b5132 | 16972 | if (auto_align) |
462427c4 | 16973 | mips_align (2, 0, l); |
252b5132 RH |
16974 | |
16975 | expression (&ex); | |
a1facbec | 16976 | mips_clear_insn_labels (); |
252b5132 RH |
16977 | |
16978 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
16979 | { | |
1661c76c | 16980 | as_bad (_("unsupported use of .gpword")); |
252b5132 RH |
16981 | ignore_rest_of_line (); |
16982 | } | |
16983 | ||
16984 | p = frag_more (4); | |
17a2f251 | 16985 | md_number_to_chars (p, 0, 4); |
b34976b6 | 16986 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
cdf6fd85 | 16987 | BFD_RELOC_GPREL32); |
252b5132 RH |
16988 | |
16989 | demand_empty_rest_of_line (); | |
16990 | } | |
16991 | ||
10181a0d | 16992 | static void |
17a2f251 | 16993 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
10181a0d | 16994 | { |
a8dbcb85 TS |
16995 | segment_info_type *si; |
16996 | struct insn_label_list *l; | |
10181a0d AO |
16997 | expressionS ex; |
16998 | char *p; | |
16999 | ||
17000 | /* When not generating PIC code, this is treated as .dword. */ | |
17001 | if (mips_pic != SVR4_PIC) | |
17002 | { | |
17003 | s_cons (3); | |
17004 | return; | |
17005 | } | |
17006 | ||
a8dbcb85 TS |
17007 | si = seg_info (now_seg); |
17008 | l = si->label_list; | |
7d10b47d | 17009 | mips_emit_delays (); |
10181a0d | 17010 | if (auto_align) |
462427c4 | 17011 | mips_align (3, 0, l); |
10181a0d AO |
17012 | |
17013 | expression (&ex); | |
a1facbec | 17014 | mips_clear_insn_labels (); |
10181a0d AO |
17015 | |
17016 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17017 | { | |
1661c76c | 17018 | as_bad (_("unsupported use of .gpdword")); |
10181a0d AO |
17019 | ignore_rest_of_line (); |
17020 | } | |
17021 | ||
17022 | p = frag_more (8); | |
17a2f251 | 17023 | md_number_to_chars (p, 0, 8); |
a105a300 | 17024 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
6e1304d8 | 17025 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
10181a0d AO |
17026 | |
17027 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ | |
6e1304d8 RS |
17028 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
17029 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; | |
10181a0d AO |
17030 | |
17031 | demand_empty_rest_of_line (); | |
17032 | } | |
17033 | ||
a3f278e2 CM |
17034 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
17035 | tables. It generates a R_MIPS_EH reloc. */ | |
17036 | ||
17037 | static void | |
17038 | s_ehword (int ignore ATTRIBUTE_UNUSED) | |
17039 | { | |
17040 | expressionS ex; | |
17041 | char *p; | |
17042 | ||
17043 | mips_emit_delays (); | |
17044 | ||
17045 | expression (&ex); | |
17046 | mips_clear_insn_labels (); | |
17047 | ||
17048 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
17049 | { | |
1661c76c | 17050 | as_bad (_("unsupported use of .ehword")); |
a3f278e2 CM |
17051 | ignore_rest_of_line (); |
17052 | } | |
17053 | ||
17054 | p = frag_more (4); | |
17055 | md_number_to_chars (p, 0, 4); | |
17056 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, | |
2f0c68f2 | 17057 | BFD_RELOC_32_PCREL); |
a3f278e2 CM |
17058 | |
17059 | demand_empty_rest_of_line (); | |
17060 | } | |
17061 | ||
252b5132 RH |
17062 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
17063 | tables in SVR4 PIC code. */ | |
17064 | ||
17065 | static void | |
17a2f251 | 17066 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17067 | { |
252b5132 RH |
17068 | int reg; |
17069 | ||
919731af | 17070 | file_mips_check_options (); |
17071 | ||
10181a0d AO |
17072 | /* This is ignored when not generating SVR4 PIC code. */ |
17073 | if (mips_pic != SVR4_PIC) | |
252b5132 RH |
17074 | { |
17075 | s_ignore (0); | |
17076 | return; | |
17077 | } | |
17078 | ||
8a75745d MR |
17079 | mips_mark_labels (); |
17080 | mips_assembling_insn = TRUE; | |
17081 | ||
252b5132 | 17082 | /* Add $gp to the register named as an argument. */ |
584892a6 | 17083 | macro_start (); |
252b5132 | 17084 | reg = tc_get_register (0); |
67c0d1eb | 17085 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
584892a6 | 17086 | macro_end (); |
252b5132 | 17087 | |
8a75745d | 17088 | mips_assembling_insn = FALSE; |
bdaaa2e1 | 17089 | demand_empty_rest_of_line (); |
252b5132 RH |
17090 | } |
17091 | ||
17092 | /* Handle the .insn pseudo-op. This marks instruction labels in | |
df58fc94 | 17093 | mips16/micromips mode. This permits the linker to handle them specially, |
252b5132 RH |
17094 | such as generating jalx instructions when needed. We also make |
17095 | them odd for the duration of the assembly, in order to generate the | |
17096 | right sort of code. We will make them even in the adjust_symtab | |
17097 | routine, while leaving them marked. This is convenient for the | |
17098 | debugger and the disassembler. The linker knows to make them odd | |
17099 | again. */ | |
17100 | ||
17101 | static void | |
17a2f251 | 17102 | s_insn (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 17103 | { |
7bb01e2d MR |
17104 | file_mips_check_options (); |
17105 | file_ase_mips16 |= mips_opts.mips16; | |
17106 | file_ase_micromips |= mips_opts.micromips; | |
17107 | ||
df58fc94 | 17108 | mips_mark_labels (); |
252b5132 RH |
17109 | |
17110 | demand_empty_rest_of_line (); | |
17111 | } | |
17112 | ||
ba92f887 MR |
17113 | /* Handle the .nan pseudo-op. */ |
17114 | ||
17115 | static void | |
17116 | s_nan (int ignore ATTRIBUTE_UNUSED) | |
17117 | { | |
17118 | static const char str_legacy[] = "legacy"; | |
17119 | static const char str_2008[] = "2008"; | |
17120 | size_t i; | |
17121 | ||
17122 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); | |
17123 | ||
17124 | if (i == sizeof (str_2008) - 1 | |
17125 | && memcmp (input_line_pointer, str_2008, i) == 0) | |
7361da2c | 17126 | mips_nan2008 = 1; |
ba92f887 MR |
17127 | else if (i == sizeof (str_legacy) - 1 |
17128 | && memcmp (input_line_pointer, str_legacy, i) == 0) | |
7361da2c AB |
17129 | { |
17130 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) | |
17131 | mips_nan2008 = 0; | |
17132 | else | |
17133 | as_bad (_("`%s' does not support legacy NaN"), | |
17134 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); | |
17135 | } | |
ba92f887 | 17136 | else |
1661c76c | 17137 | as_bad (_("bad .nan directive")); |
ba92f887 MR |
17138 | |
17139 | input_line_pointer += i; | |
17140 | demand_empty_rest_of_line (); | |
17141 | } | |
17142 | ||
754e2bb9 RS |
17143 | /* Handle a .stab[snd] directive. Ideally these directives would be |
17144 | implemented in a transparent way, so that removing them would not | |
17145 | have any effect on the generated instructions. However, s_stab | |
17146 | internally changes the section, so in practice we need to decide | |
17147 | now whether the preceding label marks compressed code. We do not | |
17148 | support changing the compression mode of a label after a .stab* | |
17149 | directive, such as in: | |
17150 | ||
17151 | foo: | |
134c0c8b | 17152 | .stabs ... |
754e2bb9 RS |
17153 | .set mips16 |
17154 | ||
17155 | so the current mode wins. */ | |
252b5132 RH |
17156 | |
17157 | static void | |
17a2f251 | 17158 | s_mips_stab (int type) |
252b5132 | 17159 | { |
42c0794e | 17160 | file_mips_check_options (); |
754e2bb9 | 17161 | mips_mark_labels (); |
252b5132 RH |
17162 | s_stab (type); |
17163 | } | |
17164 | ||
54f4ddb3 | 17165 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
252b5132 RH |
17166 | |
17167 | static void | |
17a2f251 | 17168 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
17169 | { |
17170 | char *name; | |
17171 | int c; | |
17172 | symbolS *symbolP; | |
17173 | expressionS exp; | |
17174 | ||
d02603dc | 17175 | c = get_symbol_name (&name); |
252b5132 RH |
17176 | symbolP = symbol_find_or_make (name); |
17177 | S_SET_WEAK (symbolP); | |
17178 | *input_line_pointer = c; | |
17179 | ||
d02603dc | 17180 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
17181 | |
17182 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
17183 | { | |
17184 | if (S_IS_DEFINED (symbolP)) | |
17185 | { | |
20203fb9 | 17186 | as_bad (_("ignoring attempt to redefine symbol %s"), |
252b5132 RH |
17187 | S_GET_NAME (symbolP)); |
17188 | ignore_rest_of_line (); | |
17189 | return; | |
17190 | } | |
bdaaa2e1 | 17191 | |
252b5132 RH |
17192 | if (*input_line_pointer == ',') |
17193 | { | |
17194 | ++input_line_pointer; | |
17195 | SKIP_WHITESPACE (); | |
17196 | } | |
bdaaa2e1 | 17197 | |
252b5132 RH |
17198 | expression (&exp); |
17199 | if (exp.X_op != O_symbol) | |
17200 | { | |
20203fb9 | 17201 | as_bad (_("bad .weakext directive")); |
98d3f06f | 17202 | ignore_rest_of_line (); |
252b5132 RH |
17203 | return; |
17204 | } | |
49309057 | 17205 | symbol_set_value_expression (symbolP, &exp); |
252b5132 RH |
17206 | } |
17207 | ||
17208 | demand_empty_rest_of_line (); | |
17209 | } | |
17210 | ||
17211 | /* Parse a register string into a number. Called from the ECOFF code | |
17212 | to parse .frame. The argument is non-zero if this is the frame | |
17213 | register, so that we can record it in mips_frame_reg. */ | |
17214 | ||
17215 | int | |
17a2f251 | 17216 | tc_get_register (int frame) |
252b5132 | 17217 | { |
707bfff6 | 17218 | unsigned int reg; |
252b5132 RH |
17219 | |
17220 | SKIP_WHITESPACE (); | |
707bfff6 TS |
17221 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
17222 | reg = 0; | |
252b5132 | 17223 | if (frame) |
7a621144 DJ |
17224 | { |
17225 | mips_frame_reg = reg != 0 ? reg : SP; | |
17226 | mips_frame_reg_valid = 1; | |
17227 | mips_cprestore_valid = 0; | |
17228 | } | |
252b5132 RH |
17229 | return reg; |
17230 | } | |
17231 | ||
17232 | valueT | |
17a2f251 | 17233 | md_section_align (asection *seg, valueT addr) |
252b5132 RH |
17234 | { |
17235 | int align = bfd_get_section_alignment (stdoutput, seg); | |
17236 | ||
f3ded42a RS |
17237 | /* We don't need to align ELF sections to the full alignment. |
17238 | However, Irix 5 may prefer that we align them at least to a 16 | |
17239 | byte boundary. We don't bother to align the sections if we | |
17240 | are targeted for an embedded system. */ | |
17241 | if (strncmp (TARGET_OS, "elf", 3) == 0) | |
17242 | return addr; | |
17243 | if (align > 4) | |
17244 | align = 4; | |
252b5132 | 17245 | |
8d3842cd | 17246 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
17247 | } |
17248 | ||
17249 | /* Utility routine, called from above as well. If called while the | |
17250 | input file is still being read, it's only an approximation. (For | |
17251 | example, a symbol may later become defined which appeared to be | |
17252 | undefined earlier.) */ | |
17253 | ||
17254 | static int | |
17a2f251 | 17255 | nopic_need_relax (symbolS *sym, int before_relaxing) |
252b5132 RH |
17256 | { |
17257 | if (sym == 0) | |
17258 | return 0; | |
17259 | ||
4d0d148d | 17260 | if (g_switch_value > 0) |
252b5132 RH |
17261 | { |
17262 | const char *symname; | |
17263 | int change; | |
17264 | ||
c9914766 | 17265 | /* Find out whether this symbol can be referenced off the $gp |
252b5132 RH |
17266 | register. It can be if it is smaller than the -G size or if |
17267 | it is in the .sdata or .sbss section. Certain symbols can | |
c9914766 | 17268 | not be referenced off the $gp, although it appears as though |
252b5132 RH |
17269 | they can. */ |
17270 | symname = S_GET_NAME (sym); | |
17271 | if (symname != (const char *) NULL | |
17272 | && (strcmp (symname, "eprol") == 0 | |
17273 | || strcmp (symname, "etext") == 0 | |
17274 | || strcmp (symname, "_gp") == 0 | |
17275 | || strcmp (symname, "edata") == 0 | |
17276 | || strcmp (symname, "_fbss") == 0 | |
17277 | || strcmp (symname, "_fdata") == 0 | |
17278 | || strcmp (symname, "_ftext") == 0 | |
17279 | || strcmp (symname, "end") == 0 | |
17280 | || strcmp (symname, "_gp_disp") == 0)) | |
17281 | change = 1; | |
17282 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) | |
17283 | && (0 | |
17284 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 ILT |
17285 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
17286 | && (symbol_get_obj (sym)->ecoff_extern_size | |
17287 | <= g_switch_value)) | |
252b5132 RH |
17288 | #endif |
17289 | /* We must defer this decision until after the whole | |
17290 | file has been read, since there might be a .extern | |
17291 | after the first use of this symbol. */ | |
17292 | || (before_relaxing | |
17293 | #ifndef NO_ECOFF_DEBUGGING | |
49309057 | 17294 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
252b5132 RH |
17295 | #endif |
17296 | && S_GET_VALUE (sym) == 0) | |
17297 | || (S_GET_VALUE (sym) != 0 | |
17298 | && S_GET_VALUE (sym) <= g_switch_value))) | |
17299 | change = 0; | |
17300 | else | |
17301 | { | |
17302 | const char *segname; | |
17303 | ||
17304 | segname = segment_name (S_GET_SEGMENT (sym)); | |
9c2799c2 | 17305 | gas_assert (strcmp (segname, ".lit8") != 0 |
252b5132 RH |
17306 | && strcmp (segname, ".lit4") != 0); |
17307 | change = (strcmp (segname, ".sdata") != 0 | |
fba2b7f9 GK |
17308 | && strcmp (segname, ".sbss") != 0 |
17309 | && strncmp (segname, ".sdata.", 7) != 0 | |
d4dc2f22 TS |
17310 | && strncmp (segname, ".sbss.", 6) != 0 |
17311 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 | |
fba2b7f9 | 17312 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
252b5132 RH |
17313 | } |
17314 | return change; | |
17315 | } | |
17316 | else | |
c9914766 | 17317 | /* We are not optimizing for the $gp register. */ |
252b5132 RH |
17318 | return 1; |
17319 | } | |
17320 | ||
5919d012 RS |
17321 | |
17322 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ | |
17323 | ||
17324 | static bfd_boolean | |
9e009953 | 17325 | pic_need_relax (symbolS *sym) |
5919d012 RS |
17326 | { |
17327 | asection *symsec; | |
5919d012 RS |
17328 | |
17329 | /* Handle the case of a symbol equated to another symbol. */ | |
17330 | while (symbol_equated_reloc_p (sym)) | |
17331 | { | |
17332 | symbolS *n; | |
17333 | ||
5f0fe04b | 17334 | /* It's possible to get a loop here in a badly written program. */ |
5919d012 RS |
17335 | n = symbol_get_value_expression (sym)->X_add_symbol; |
17336 | if (n == sym) | |
17337 | break; | |
17338 | sym = n; | |
17339 | } | |
17340 | ||
df1f3cda DD |
17341 | if (symbol_section_p (sym)) |
17342 | return TRUE; | |
17343 | ||
5919d012 RS |
17344 | symsec = S_GET_SEGMENT (sym); |
17345 | ||
5919d012 | 17346 | /* This must duplicate the test in adjust_reloc_syms. */ |
45dfa85a AM |
17347 | return (!bfd_is_und_section (symsec) |
17348 | && !bfd_is_abs_section (symsec) | |
5f0fe04b | 17349 | && !bfd_is_com_section (symsec) |
5919d012 | 17350 | /* A global or weak symbol is treated as external. */ |
f3ded42a | 17351 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
5919d012 | 17352 | } |
14f72d45 MR |
17353 | \f |
17354 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP | |
17355 | convert a section-relative value VAL to the equivalent PC-relative | |
17356 | value. */ | |
17357 | ||
17358 | static offsetT | |
17359 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, | |
17360 | offsetT val, long stretch) | |
17361 | { | |
17362 | fragS *sym_frag; | |
17363 | addressT addr; | |
17364 | ||
17365 | gas_assert (pcrel_op->root.root.type == OP_PCREL); | |
17366 | ||
17367 | sym_frag = symbol_get_frag (fragp->fr_symbol); | |
17368 | ||
17369 | /* If the relax_marker of the symbol fragment differs from the | |
17370 | relax_marker of this fragment, we have not yet adjusted the | |
17371 | symbol fragment fr_address. We want to add in STRETCH in | |
17372 | order to get a better estimate of the address. This | |
17373 | particularly matters because of the shift bits. */ | |
17374 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) | |
17375 | { | |
17376 | fragS *f; | |
17377 | ||
17378 | /* Adjust stretch for any alignment frag. Note that if have | |
17379 | been expanding the earlier code, the symbol may be | |
17380 | defined in what appears to be an earlier frag. FIXME: | |
17381 | This doesn't handle the fr_subtype field, which specifies | |
17382 | a maximum number of bytes to skip when doing an | |
17383 | alignment. */ | |
17384 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) | |
17385 | { | |
17386 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) | |
17387 | { | |
17388 | if (stretch < 0) | |
17389 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); | |
17390 | else | |
17391 | stretch &= ~((1 << (int) f->fr_offset) - 1); | |
17392 | if (stretch == 0) | |
17393 | break; | |
17394 | } | |
17395 | } | |
17396 | if (f != NULL) | |
17397 | val += stretch; | |
17398 | } | |
17399 | ||
17400 | addr = fragp->fr_address + fragp->fr_fix; | |
17401 | ||
17402 | /* The base address rules are complicated. The base address of | |
17403 | a branch is the following instruction. The base address of a | |
17404 | PC relative load or add is the instruction itself, but if it | |
17405 | is in a delay slot (in which case it can not be extended) use | |
17406 | the address of the instruction whose delay slot it is in. */ | |
17407 | if (pcrel_op->include_isa_bit) | |
17408 | { | |
17409 | addr += 2; | |
17410 | ||
17411 | /* If we are currently assuming that this frag should be | |
17412 | extended, then the current address is two bytes higher. */ | |
17413 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
17414 | addr += 2; | |
17415 | ||
17416 | /* Ignore the low bit in the target, since it will be set | |
17417 | for a text label. */ | |
17418 | val &= -2; | |
17419 | } | |
17420 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) | |
17421 | addr -= 4; | |
17422 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
17423 | addr -= 2; | |
5919d012 | 17424 | |
14f72d45 MR |
17425 | val -= addr & -(1 << pcrel_op->align_log2); |
17426 | ||
17427 | return val; | |
17428 | } | |
5919d012 | 17429 | |
252b5132 RH |
17430 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
17431 | extended opcode. SEC is the section the frag is in. */ | |
17432 | ||
17433 | static int | |
17a2f251 | 17434 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
252b5132 | 17435 | { |
3ccad066 | 17436 | const struct mips_int_operand *operand; |
252b5132 | 17437 | offsetT val; |
252b5132 | 17438 | segT symsec; |
14f72d45 | 17439 | int type; |
252b5132 RH |
17440 | |
17441 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
17442 | return 0; | |
17443 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17444 | return 1; | |
17445 | ||
88a7ef16 | 17446 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
252b5132 | 17447 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
3ccad066 | 17448 | operand = mips16_immed_operand (type, FALSE); |
88a7ef16 MR |
17449 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
17450 | || (operand->root.type == OP_PCREL | |
17451 | ? sec != symsec | |
17452 | : !bfd_is_abs_section (symsec))) | |
17453 | return 1; | |
252b5132 | 17454 | |
88a7ef16 | 17455 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
252b5132 | 17456 | |
3ccad066 | 17457 | if (operand->root.type == OP_PCREL) |
252b5132 | 17458 | { |
3ccad066 | 17459 | const struct mips_pcrel_operand *pcrel_op; |
3ccad066 | 17460 | offsetT maxtiny; |
252b5132 | 17461 | |
1425c41d | 17462 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
88a7ef16 | 17463 | return 1; |
252b5132 | 17464 | |
88a7ef16 | 17465 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
14f72d45 | 17466 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
252b5132 RH |
17467 | |
17468 | /* If any of the shifted bits are set, we must use an extended | |
17469 | opcode. If the address depends on the size of this | |
17470 | instruction, this can lead to a loop, so we arrange to always | |
88a7ef16 MR |
17471 | use an extended opcode. */ |
17472 | if ((val & ((1 << operand->shift) - 1)) != 0) | |
252b5132 RH |
17473 | { |
17474 | fragp->fr_subtype = | |
1425c41d | 17475 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17476 | return 1; |
17477 | } | |
17478 | ||
17479 | /* If we are about to mark a frag as extended because the value | |
3ccad066 RS |
17480 | is precisely the next value above maxtiny, then there is a |
17481 | chance of an infinite loop as in the following code: | |
252b5132 RH |
17482 | la $4,foo |
17483 | .skip 1020 | |
17484 | .align 2 | |
17485 | foo: | |
17486 | In this case when the la is extended, foo is 0x3fc bytes | |
17487 | away, so the la can be shrunk, but then foo is 0x400 away, so | |
17488 | the la must be extended. To avoid this loop, we mark the | |
17489 | frag as extended if it was small, and is about to become | |
3ccad066 RS |
17490 | extended with the next value above maxtiny. */ |
17491 | maxtiny = mips_int_operand_max (operand); | |
17492 | if (val == maxtiny + (1 << operand->shift) | |
88a7ef16 | 17493 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
252b5132 RH |
17494 | { |
17495 | fragp->fr_subtype = | |
1425c41d | 17496 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
252b5132 RH |
17497 | return 1; |
17498 | } | |
17499 | } | |
252b5132 | 17500 | |
3ccad066 | 17501 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
252b5132 RH |
17502 | } |
17503 | ||
8507b6e7 MR |
17504 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
17505 | macro expansion. SEC is the section the frag is in. We only | |
17506 | support PC-relative instructions (LA, DLA, LW, LD) here, in | |
17507 | non-PIC code using 32-bit addressing. */ | |
17508 | ||
17509 | static int | |
17510 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) | |
17511 | { | |
17512 | const struct mips_pcrel_operand *pcrel_op; | |
17513 | const struct mips_int_operand *operand; | |
17514 | offsetT val; | |
17515 | segT symsec; | |
17516 | int type; | |
17517 | ||
17518 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); | |
17519 | ||
17520 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) | |
17521 | return 0; | |
17522 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) | |
17523 | return 0; | |
17524 | ||
17525 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
17526 | switch (type) | |
17527 | { | |
17528 | case 'A': | |
17529 | case 'B': | |
17530 | case 'E': | |
17531 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
17532 | if (bfd_is_abs_section (symsec)) | |
17533 | return 1; | |
17534 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) | |
17535 | return 0; | |
17536 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) | |
17537 | return 1; | |
17538 | ||
17539 | operand = mips16_immed_operand (type, TRUE); | |
17540 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17541 | pcrel_op = (const struct mips_pcrel_operand *) operand; | |
17542 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); | |
17543 | ||
17544 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); | |
17545 | ||
17546 | default: | |
17547 | return 0; | |
17548 | } | |
17549 | } | |
17550 | ||
4a6a3df4 AO |
17551 | /* Compute the length of a branch sequence, and adjust the |
17552 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the | |
17553 | worst-case length is computed, with UPDATE being used to indicate | |
17554 | whether an unconditional (-1), branch-likely (+1) or regular (0) | |
17555 | branch is to be computed. */ | |
17556 | static int | |
17a2f251 | 17557 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
4a6a3df4 | 17558 | { |
b34976b6 | 17559 | bfd_boolean toofar; |
4a6a3df4 AO |
17560 | int length; |
17561 | ||
17562 | if (fragp | |
17563 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17564 | && !S_IS_WEAK (fragp->fr_symbol) |
4a6a3df4 AO |
17565 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17566 | { | |
17567 | addressT addr; | |
17568 | offsetT val; | |
17569 | ||
17570 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17571 | ||
17572 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17573 | ||
17574 | val -= addr; | |
17575 | ||
17576 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); | |
17577 | } | |
4a6a3df4 | 17578 | else |
c1f61bd2 MR |
17579 | /* If the symbol is not defined or it's in a different segment, |
17580 | we emit the long sequence. */ | |
b34976b6 | 17581 | toofar = TRUE; |
4a6a3df4 AO |
17582 | |
17583 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) | |
17584 | fragp->fr_subtype | |
66b3e8da | 17585 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
ce8ad872 | 17586 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
66b3e8da | 17587 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
4a6a3df4 AO |
17588 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
17589 | RELAX_BRANCH_LINK (fragp->fr_subtype), | |
17590 | toofar); | |
17591 | ||
17592 | length = 4; | |
17593 | if (toofar) | |
17594 | { | |
17595 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) | |
17596 | length += 8; | |
17597 | ||
ce8ad872 | 17598 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
17599 | { |
17600 | /* Additional space for PIC loading of target address. */ | |
17601 | length += 8; | |
17602 | if (mips_opts.isa == ISA_MIPS1) | |
17603 | /* Additional space for $at-stabilizing nop. */ | |
17604 | length += 4; | |
17605 | } | |
17606 | ||
17607 | /* If branch is conditional. */ | |
17608 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) | |
17609 | length += 8; | |
17610 | } | |
b34976b6 | 17611 | |
4a6a3df4 AO |
17612 | return length; |
17613 | } | |
17614 | ||
7bd374a4 MR |
17615 | /* Get a FRAG's branch instruction delay slot size, either from the |
17616 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, | |
17617 | or SHORT_INSN_SIZE otherwise. */ | |
17618 | ||
17619 | static int | |
17620 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) | |
17621 | { | |
17622 | char *buf = fragp->fr_literal + fragp->fr_fix; | |
17623 | ||
17624 | if (al) | |
17625 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; | |
17626 | else | |
17627 | return short_insn_size; | |
17628 | } | |
17629 | ||
df58fc94 RS |
17630 | /* Compute the length of a branch sequence, and adjust the |
17631 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the | |
17632 | worst-case length is computed, with UPDATE being used to indicate | |
17633 | whether an unconditional (-1), or regular (0) branch is to be | |
17634 | computed. */ | |
17635 | ||
17636 | static int | |
17637 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) | |
17638 | { | |
7bd374a4 MR |
17639 | bfd_boolean insn32 = TRUE; |
17640 | bfd_boolean nods = TRUE; | |
ce8ad872 | 17641 | bfd_boolean pic = TRUE; |
7bd374a4 MR |
17642 | bfd_boolean al = TRUE; |
17643 | int short_insn_size; | |
df58fc94 RS |
17644 | bfd_boolean toofar; |
17645 | int length; | |
17646 | ||
7bd374a4 MR |
17647 | if (fragp) |
17648 | { | |
17649 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); | |
17650 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); | |
ce8ad872 | 17651 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
7bd374a4 MR |
17652 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
17653 | } | |
17654 | short_insn_size = insn32 ? 4 : 2; | |
17655 | ||
df58fc94 RS |
17656 | if (fragp |
17657 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17658 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17659 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17660 | { | |
17661 | addressT addr; | |
17662 | offsetT val; | |
17663 | ||
17664 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17665 | /* Ignore the low bit in the target, since it will be set | |
17666 | for a text label. */ | |
17667 | if ((val & 1) != 0) | |
17668 | --val; | |
17669 | ||
17670 | addr = fragp->fr_address + fragp->fr_fix + 4; | |
17671 | ||
17672 | val -= addr; | |
17673 | ||
17674 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); | |
17675 | } | |
df58fc94 | 17676 | else |
c1f61bd2 MR |
17677 | /* If the symbol is not defined or it's in a different segment, |
17678 | we emit the long sequence. */ | |
df58fc94 RS |
17679 | toofar = TRUE; |
17680 | ||
17681 | if (fragp && update | |
17682 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
17683 | fragp->fr_subtype = (toofar | |
17684 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) | |
17685 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); | |
17686 | ||
17687 | length = 4; | |
17688 | if (toofar) | |
17689 | { | |
17690 | bfd_boolean compact_known = fragp != NULL; | |
17691 | bfd_boolean compact = FALSE; | |
17692 | bfd_boolean uncond; | |
17693 | ||
df58fc94 | 17694 | if (fragp) |
8484fb75 MR |
17695 | { |
17696 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); | |
17697 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); | |
8484fb75 | 17698 | } |
df58fc94 RS |
17699 | else |
17700 | uncond = update < 0; | |
17701 | ||
17702 | /* If label is out of range, we turn branch <br>: | |
17703 | ||
17704 | <br> label # 4 bytes | |
17705 | 0: | |
17706 | ||
17707 | into: | |
17708 | ||
17709 | j label # 4 bytes | |
8484fb75 MR |
17710 | nop # 2/4 bytes if |
17711 | # compact && (!PIC || insn32) | |
df58fc94 RS |
17712 | 0: |
17713 | */ | |
ce8ad872 | 17714 | if ((!pic || insn32) && (!compact_known || compact)) |
8484fb75 | 17715 | length += short_insn_size; |
df58fc94 RS |
17716 | |
17717 | /* If assembling PIC code, we further turn: | |
17718 | ||
17719 | j label # 4 bytes | |
17720 | ||
17721 | into: | |
17722 | ||
17723 | lw/ld at, %got(label)(gp) # 4 bytes | |
17724 | d/addiu at, %lo(label) # 4 bytes | |
8484fb75 | 17725 | jr/c at # 2/4 bytes |
df58fc94 | 17726 | */ |
ce8ad872 | 17727 | if (pic) |
8484fb75 | 17728 | length += 4 + short_insn_size; |
df58fc94 | 17729 | |
7bd374a4 MR |
17730 | /* Add an extra nop if the jump has no compact form and we need |
17731 | to fill the delay slot. */ | |
ce8ad872 | 17732 | if ((!pic || al) && nods) |
7bd374a4 MR |
17733 | length += (fragp |
17734 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) | |
17735 | : short_insn_size); | |
17736 | ||
df58fc94 RS |
17737 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
17738 | ||
17739 | <brneg> 0f # 4 bytes | |
8484fb75 | 17740 | nop # 2/4 bytes if !compact |
df58fc94 RS |
17741 | */ |
17742 | if (!uncond) | |
8484fb75 | 17743 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
df58fc94 | 17744 | } |
7bd374a4 MR |
17745 | else if (nods) |
17746 | { | |
17747 | /* Add an extra nop to fill the delay slot. */ | |
17748 | gas_assert (fragp); | |
17749 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); | |
17750 | } | |
df58fc94 RS |
17751 | |
17752 | return length; | |
17753 | } | |
17754 | ||
17755 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 | |
17756 | bit accordingly. */ | |
17757 | ||
17758 | static int | |
17759 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) | |
17760 | { | |
17761 | bfd_boolean toofar; | |
17762 | ||
df58fc94 RS |
17763 | if (fragp |
17764 | && S_IS_DEFINED (fragp->fr_symbol) | |
991f40a9 | 17765 | && !S_IS_WEAK (fragp->fr_symbol) |
df58fc94 RS |
17766 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
17767 | { | |
17768 | addressT addr; | |
17769 | offsetT val; | |
17770 | int type; | |
17771 | ||
17772 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
17773 | /* Ignore the low bit in the target, since it will be set | |
17774 | for a text label. */ | |
17775 | if ((val & 1) != 0) | |
17776 | --val; | |
17777 | ||
17778 | /* Assume this is a 2-byte branch. */ | |
17779 | addr = fragp->fr_address + fragp->fr_fix + 2; | |
17780 | ||
17781 | /* We try to avoid the infinite loop by not adding 2 more bytes for | |
17782 | long branches. */ | |
17783 | ||
17784 | val -= addr; | |
17785 | ||
17786 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
17787 | if (type == 'D') | |
17788 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); | |
17789 | else if (type == 'E') | |
17790 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); | |
17791 | else | |
17792 | abort (); | |
17793 | } | |
17794 | else | |
17795 | /* If the symbol is not defined or it's in a different segment, | |
17796 | we emit a normal 32-bit branch. */ | |
17797 | toofar = TRUE; | |
17798 | ||
17799 | if (fragp && update | |
17800 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
17801 | fragp->fr_subtype | |
17802 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) | |
17803 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); | |
17804 | ||
17805 | if (toofar) | |
17806 | return 4; | |
17807 | ||
17808 | return 2; | |
17809 | } | |
17810 | ||
252b5132 RH |
17811 | /* Estimate the size of a frag before relaxing. Unless this is the |
17812 | mips16, we are not really relaxing here, and the final size is | |
17813 | encoded in the subtype information. For the mips16, we have to | |
17814 | decide whether we are using an extended opcode or not. */ | |
17815 | ||
252b5132 | 17816 | int |
17a2f251 | 17817 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
252b5132 | 17818 | { |
5919d012 | 17819 | int change; |
252b5132 | 17820 | |
4a6a3df4 AO |
17821 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
17822 | { | |
17823 | ||
b34976b6 AM |
17824 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
17825 | ||
4a6a3df4 AO |
17826 | return fragp->fr_var; |
17827 | } | |
17828 | ||
252b5132 | 17829 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
8507b6e7 MR |
17830 | { |
17831 | /* We don't want to modify the EXTENDED bit here; it might get us | |
17832 | into infinite loops. We change it only in mips_relax_frag(). */ | |
17833 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
25499ac7 | 17834 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
8507b6e7 MR |
17835 | else |
17836 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; | |
17837 | } | |
252b5132 | 17838 | |
df58fc94 RS |
17839 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
17840 | { | |
17841 | int length = 4; | |
17842 | ||
17843 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
17844 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); | |
17845 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
17846 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); | |
17847 | fragp->fr_var = length; | |
17848 | ||
17849 | return length; | |
17850 | } | |
17851 | ||
ce8ad872 | 17852 | if (mips_pic == VXWORKS_PIC) |
0a44bf69 RS |
17853 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
17854 | change = 0; | |
ce8ad872 MR |
17855 | else if (RELAX_PIC (fragp->fr_subtype)) |
17856 | change = pic_need_relax (fragp->fr_symbol); | |
252b5132 | 17857 | else |
ce8ad872 | 17858 | change = nopic_need_relax (fragp->fr_symbol, 0); |
252b5132 RH |
17859 | |
17860 | if (change) | |
17861 | { | |
4d7206a2 | 17862 | fragp->fr_subtype |= RELAX_USE_SECOND; |
4d7206a2 | 17863 | return -RELAX_FIRST (fragp->fr_subtype); |
252b5132 | 17864 | } |
4d7206a2 RS |
17865 | else |
17866 | return -RELAX_SECOND (fragp->fr_subtype); | |
252b5132 RH |
17867 | } |
17868 | ||
17869 | /* This is called to see whether a reloc against a defined symbol | |
de7e6852 | 17870 | should be converted into a reloc against a section. */ |
252b5132 RH |
17871 | |
17872 | int | |
17a2f251 | 17873 | mips_fix_adjustable (fixS *fixp) |
252b5132 | 17874 | { |
252b5132 RH |
17875 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
17876 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
17877 | return 0; | |
a161fe53 | 17878 | |
252b5132 RH |
17879 | if (fixp->fx_addsy == NULL) |
17880 | return 1; | |
a161fe53 | 17881 | |
2f0c68f2 CM |
17882 | /* Allow relocs used for EH tables. */ |
17883 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) | |
17884 | return 1; | |
17885 | ||
de7e6852 RS |
17886 | /* If symbol SYM is in a mergeable section, relocations of the form |
17887 | SYM + 0 can usually be made section-relative. The mergeable data | |
17888 | is then identified by the section offset rather than by the symbol. | |
17889 | ||
17890 | However, if we're generating REL LO16 relocations, the offset is split | |
33eaf5de | 17891 | between the LO16 and partnering high part relocation. The linker will |
de7e6852 RS |
17892 | need to recalculate the complete offset in order to correctly identify |
17893 | the merge data. | |
17894 | ||
33eaf5de | 17895 | The linker has traditionally not looked for the partnering high part |
de7e6852 RS |
17896 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
17897 | placed anywhere. Rather than break backwards compatibility by changing | |
17898 | this, it seems better not to force the issue, and instead keep the | |
17899 | original symbol. This will work with either linker behavior. */ | |
738e5348 | 17900 | if ((lo16_reloc_p (fixp->fx_r_type) |
704803a9 | 17901 | || reloc_needs_lo_p (fixp->fx_r_type)) |
de7e6852 RS |
17902 | && HAVE_IN_PLACE_ADDENDS |
17903 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) | |
17904 | return 0; | |
17905 | ||
97f50151 MR |
17906 | /* There is no place to store an in-place offset for JALR relocations. */ |
17907 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) | |
17908 | return 0; | |
17909 | ||
17910 | /* Likewise an in-range offset of limited PC-relative relocations may | |
2de39019 | 17911 | overflow the in-place relocatable field if recalculated against the |
7361da2c AB |
17912 | start address of the symbol's containing section. |
17913 | ||
17914 | Also, PC relative relocations for MIPS R6 need to be symbol rather than | |
17915 | section relative to allow linker relaxations to be performed later on. */ | |
97f50151 | 17916 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
912815f0 | 17917 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
1180b5a4 RS |
17918 | return 0; |
17919 | ||
b314ec0e RS |
17920 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
17921 | to a floating-point stub. The same is true for non-R_MIPS16_26 | |
17922 | relocations against MIPS16 functions; in this case, the stub becomes | |
17923 | the function's canonical address. | |
17924 | ||
17925 | Floating-point stubs are stored in unique .mips16.call.* or | |
17926 | .mips16.fn.* sections. If a stub T for function F is in section S, | |
17927 | the first relocation in section S must be against F; this is how the | |
17928 | linker determines the target function. All relocations that might | |
17929 | resolve to T must also be against F. We therefore have the following | |
17930 | restrictions, which are given in an intentionally-redundant way: | |
17931 | ||
17932 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 | |
17933 | symbols. | |
17934 | ||
17935 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols | |
17936 | if that stub might be used. | |
17937 | ||
17938 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 | |
17939 | symbols. | |
17940 | ||
17941 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if | |
17942 | that stub might be used. | |
17943 | ||
17944 | There is a further restriction: | |
17945 | ||
df58fc94 | 17946 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
0e9c5a5c | 17947 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
c9775dde MR |
17948 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
17949 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) | |
17950 | against MIPS16 or microMIPS symbols because we need to keep the | |
17951 | MIPS16 or microMIPS symbol for the purpose of mode mismatch | |
a6ebf616 MR |
17952 | detection and JAL or BAL to JALX instruction conversion in the |
17953 | linker. | |
b314ec0e | 17954 | |
df58fc94 | 17955 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
507dcb32 | 17956 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
0e9c5a5c | 17957 | alone any jump and branch relocations against a microMIPS symbol. |
b314ec0e RS |
17958 | |
17959 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 | |
17960 | relocation against some symbol R, no relocation against R may be | |
17961 | reduced. (Note that this deals with (2) as well as (1) because | |
17962 | relocations against global symbols will never be reduced on ELF | |
17963 | targets.) This approach is a little simpler than trying to detect | |
17964 | stub sections, and gives the "all or nothing" per-symbol consistency | |
17965 | that we have for MIPS16 symbols. */ | |
f3ded42a | 17966 | if (fixp->fx_subsy == NULL |
30c09090 | 17967 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
44d3da23 | 17968 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
0e9c5a5c MR |
17969 | && (jmp_reloc_p (fixp->fx_r_type) |
17970 | || b_reloc_p (fixp->fx_r_type))) | |
44d3da23 | 17971 | || *symbol_get_tc (fixp->fx_addsy))) |
252b5132 | 17972 | return 0; |
a161fe53 | 17973 | |
252b5132 RH |
17974 | return 1; |
17975 | } | |
17976 | ||
17977 | /* Translate internal representation of relocation info to BFD target | |
17978 | format. */ | |
17979 | ||
17980 | arelent ** | |
17a2f251 | 17981 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
17982 | { |
17983 | static arelent *retval[4]; | |
17984 | arelent *reloc; | |
17985 | bfd_reloc_code_real_type code; | |
17986 | ||
4b0cff4e | 17987 | memset (retval, 0, sizeof(retval)); |
325801bd TS |
17988 | reloc = retval[0] = XCNEW (arelent); |
17989 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 17990 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
17991 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
17992 | ||
bad36eac DJ |
17993 | if (fixp->fx_pcrel) |
17994 | { | |
df58fc94 | 17995 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
c9775dde | 17996 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
df58fc94 RS |
17997 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
17998 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 | |
b47468a6 | 17999 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
7361da2c AB |
18000 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
18001 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 | |
18002 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 | |
18003 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 | |
18004 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 | |
18005 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL | |
18006 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); | |
bad36eac DJ |
18007 | |
18008 | /* At this point, fx_addnumber is "symbol offset - pcrel address". | |
18009 | Relocations want only the symbol offset. */ | |
51f6035b MR |
18010 | switch (fixp->fx_r_type) |
18011 | { | |
18012 | case BFD_RELOC_MIPS_18_PCREL_S3: | |
18013 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); | |
18014 | break; | |
18015 | default: | |
18016 | reloc->addend = fixp->fx_addnumber + reloc->address; | |
18017 | break; | |
18018 | } | |
bad36eac | 18019 | } |
17c6c9d9 MR |
18020 | else if (HAVE_IN_PLACE_ADDENDS |
18021 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP | |
18022 | && (read_compressed_insn (fixp->fx_frag->fr_literal | |
18023 | + fixp->fx_where, 4) >> 26) == 0x3c) | |
18024 | { | |
18025 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place | |
18026 | addend accordingly. */ | |
18027 | reloc->addend = fixp->fx_addnumber >> 1; | |
18028 | } | |
bad36eac DJ |
18029 | else |
18030 | reloc->addend = fixp->fx_addnumber; | |
252b5132 | 18031 | |
438c16b8 TS |
18032 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
18033 | entry to be used in the relocation's section offset. */ | |
18034 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
252b5132 RH |
18035 | { |
18036 | reloc->address = reloc->addend; | |
18037 | reloc->addend = 0; | |
18038 | } | |
18039 | ||
252b5132 | 18040 | code = fixp->fx_r_type; |
252b5132 | 18041 | |
bad36eac | 18042 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
252b5132 RH |
18043 | if (reloc->howto == NULL) |
18044 | { | |
18045 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
1661c76c RS |
18046 | _("cannot represent %s relocation in this object file" |
18047 | " format"), | |
252b5132 RH |
18048 | bfd_get_reloc_code_name (code)); |
18049 | retval[0] = NULL; | |
18050 | } | |
18051 | ||
18052 | return retval; | |
18053 | } | |
18054 | ||
18055 | /* Relax a machine dependent frag. This returns the amount by which | |
18056 | the current size of the frag should change. */ | |
18057 | ||
18058 | int | |
17a2f251 | 18059 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
252b5132 | 18060 | { |
4a6a3df4 AO |
18061 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18062 | { | |
18063 | offsetT old_var = fragp->fr_var; | |
b34976b6 AM |
18064 | |
18065 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); | |
4a6a3df4 AO |
18066 | |
18067 | return fragp->fr_var - old_var; | |
18068 | } | |
18069 | ||
df58fc94 RS |
18070 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
18071 | { | |
18072 | offsetT old_var = fragp->fr_var; | |
18073 | offsetT new_var = 4; | |
18074 | ||
18075 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) | |
18076 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); | |
18077 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) | |
18078 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); | |
18079 | fragp->fr_var = new_var; | |
18080 | ||
18081 | return new_var - old_var; | |
18082 | } | |
18083 | ||
252b5132 RH |
18084 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
18085 | return 0; | |
18086 | ||
8507b6e7 | 18087 | if (!mips16_extended_frag (fragp, sec, stretch)) |
252b5132 | 18088 | { |
8507b6e7 MR |
18089 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
18090 | { | |
18091 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
25499ac7 | 18092 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
8507b6e7 MR |
18093 | } |
18094 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18095 | { | |
18096 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18097 | return -2; | |
18098 | } | |
18099 | else | |
18100 | return 0; | |
18101 | } | |
18102 | else if (!mips16_macro_frag (fragp, sec, stretch)) | |
18103 | { | |
18104 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) | |
18105 | { | |
18106 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); | |
18107 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
25499ac7 | 18108 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
8507b6e7 MR |
18109 | } |
18110 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) | |
18111 | { | |
18112 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); | |
18113 | return 2; | |
18114 | } | |
18115 | else | |
252b5132 | 18116 | return 0; |
252b5132 RH |
18117 | } |
18118 | else | |
18119 | { | |
8507b6e7 | 18120 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
252b5132 | 18121 | return 0; |
8507b6e7 MR |
18122 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
18123 | { | |
18124 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); | |
18125 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18126 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
8507b6e7 MR |
18127 | } |
18128 | else | |
18129 | { | |
18130 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); | |
25499ac7 | 18131 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
8507b6e7 | 18132 | } |
252b5132 RH |
18133 | } |
18134 | ||
18135 | return 0; | |
18136 | } | |
18137 | ||
18138 | /* Convert a machine dependent frag. */ | |
18139 | ||
18140 | void | |
17a2f251 | 18141 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
252b5132 | 18142 | { |
4a6a3df4 AO |
18143 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
18144 | { | |
4d68580a | 18145 | char *buf; |
4a6a3df4 | 18146 | unsigned long insn; |
4a6a3df4 | 18147 | fixS *fixp; |
b34976b6 | 18148 | |
4d68580a RS |
18149 | buf = fragp->fr_literal + fragp->fr_fix; |
18150 | insn = read_insn (buf); | |
b34976b6 | 18151 | |
4a6a3df4 AO |
18152 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
18153 | { | |
18154 | /* We generate a fixup instead of applying it right now | |
18155 | because, if there are linker relaxations, we're going to | |
18156 | need the relocations. */ | |
bbd27b76 MR |
18157 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18158 | fragp->fr_symbol, fragp->fr_offset, | |
18159 | TRUE, BFD_RELOC_16_PCREL_S2); | |
4a6a3df4 AO |
18160 | fixp->fx_file = fragp->fr_file; |
18161 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18162 | |
4d68580a | 18163 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18164 | } |
18165 | else | |
18166 | { | |
18167 | int i; | |
18168 | ||
18169 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18170 | _("relaxed out-of-range branch into a jump")); |
4a6a3df4 AO |
18171 | |
18172 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) | |
18173 | goto uncond; | |
18174 | ||
18175 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18176 | { | |
18177 | /* Reverse the branch. */ | |
18178 | switch ((insn >> 28) & 0xf) | |
18179 | { | |
18180 | case 4: | |
56d438b1 CF |
18181 | if ((insn & 0xff000000) == 0x47000000 |
18182 | || (insn & 0xff600000) == 0x45600000) | |
18183 | { | |
18184 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition | |
18185 | reversed by tweaking bit 23. */ | |
18186 | insn ^= 0x00800000; | |
18187 | } | |
18188 | else | |
18189 | { | |
18190 | /* bc[0-3][tf]l? instructions can have the condition | |
18191 | reversed by tweaking a single TF bit, and their | |
18192 | opcodes all have 0x4???????. */ | |
18193 | gas_assert ((insn & 0xf3e00000) == 0x41000000); | |
18194 | insn ^= 0x00010000; | |
18195 | } | |
4a6a3df4 AO |
18196 | break; |
18197 | ||
18198 | case 0: | |
18199 | /* bltz 0x04000000 bgez 0x04010000 | |
54f4ddb3 | 18200 | bltzal 0x04100000 bgezal 0x04110000 */ |
9c2799c2 | 18201 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
4a6a3df4 AO |
18202 | insn ^= 0x00010000; |
18203 | break; | |
b34976b6 | 18204 | |
4a6a3df4 AO |
18205 | case 1: |
18206 | /* beq 0x10000000 bne 0x14000000 | |
54f4ddb3 | 18207 | blez 0x18000000 bgtz 0x1c000000 */ |
4a6a3df4 AO |
18208 | insn ^= 0x04000000; |
18209 | break; | |
18210 | ||
18211 | default: | |
18212 | abort (); | |
18213 | } | |
18214 | } | |
18215 | ||
18216 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
18217 | { | |
18218 | /* Clear the and-link bit. */ | |
9c2799c2 | 18219 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
4a6a3df4 | 18220 | |
54f4ddb3 TS |
18221 | /* bltzal 0x04100000 bgezal 0x04110000 |
18222 | bltzall 0x04120000 bgezall 0x04130000 */ | |
4a6a3df4 AO |
18223 | insn &= ~0x00100000; |
18224 | } | |
18225 | ||
18226 | /* Branch over the branch (if the branch was likely) or the | |
18227 | full jump (not likely case). Compute the offset from the | |
18228 | current instruction to branch to. */ | |
18229 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18230 | i = 16; | |
18231 | else | |
18232 | { | |
18233 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18234 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18235 | /* How many bytes in instructions from here to the end? */ |
18236 | i = fragp->fr_var - i; | |
18237 | } | |
18238 | /* Convert to instruction count. */ | |
18239 | i >>= 2; | |
18240 | /* Branch counts from the next instruction. */ | |
b34976b6 | 18241 | i--; |
4a6a3df4 AO |
18242 | insn |= i; |
18243 | /* Branch over the jump. */ | |
4d68580a | 18244 | buf = write_insn (buf, insn); |
4a6a3df4 | 18245 | |
54f4ddb3 | 18246 | /* nop */ |
4d68580a | 18247 | buf = write_insn (buf, 0); |
4a6a3df4 AO |
18248 | |
18249 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) | |
18250 | { | |
18251 | /* beql $0, $0, 2f */ | |
18252 | insn = 0x50000000; | |
18253 | /* Compute the PC offset from the current instruction to | |
18254 | the end of the variable frag. */ | |
18255 | /* How many bytes in instructions we've already emitted? */ | |
4d68580a | 18256 | i = buf - fragp->fr_literal - fragp->fr_fix; |
4a6a3df4 AO |
18257 | /* How many bytes in instructions from here to the end? */ |
18258 | i = fragp->fr_var - i; | |
18259 | /* Convert to instruction count. */ | |
18260 | i >>= 2; | |
18261 | /* Don't decrement i, because we want to branch over the | |
18262 | delay slot. */ | |
4a6a3df4 | 18263 | insn |= i; |
4a6a3df4 | 18264 | |
4d68580a RS |
18265 | buf = write_insn (buf, insn); |
18266 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18267 | } |
18268 | ||
18269 | uncond: | |
ce8ad872 | 18270 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
4a6a3df4 AO |
18271 | { |
18272 | /* j or jal. */ | |
18273 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) | |
18274 | ? 0x0c000000 : 0x08000000); | |
4a6a3df4 | 18275 | |
bbd27b76 MR |
18276 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18277 | fragp->fr_symbol, fragp->fr_offset, | |
18278 | FALSE, BFD_RELOC_MIPS_JMP); | |
4a6a3df4 AO |
18279 | fixp->fx_file = fragp->fr_file; |
18280 | fixp->fx_line = fragp->fr_line; | |
18281 | ||
4d68580a | 18282 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18283 | } |
18284 | else | |
18285 | { | |
66b3e8da MR |
18286 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
18287 | ||
4a6a3df4 | 18288 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
66b3e8da MR |
18289 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
18290 | insn |= at << OP_SH_RT; | |
4a6a3df4 | 18291 | |
bbd27b76 MR |
18292 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18293 | fragp->fr_symbol, fragp->fr_offset, | |
18294 | FALSE, BFD_RELOC_MIPS_GOT16); | |
4a6a3df4 AO |
18295 | fixp->fx_file = fragp->fr_file; |
18296 | fixp->fx_line = fragp->fr_line; | |
18297 | ||
4d68580a | 18298 | buf = write_insn (buf, insn); |
b34976b6 | 18299 | |
4a6a3df4 | 18300 | if (mips_opts.isa == ISA_MIPS1) |
4d68580a RS |
18301 | /* nop */ |
18302 | buf = write_insn (buf, 0); | |
4a6a3df4 AO |
18303 | |
18304 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ | |
66b3e8da MR |
18305 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
18306 | insn |= at << OP_SH_RS | at << OP_SH_RT; | |
4a6a3df4 | 18307 | |
bbd27b76 MR |
18308 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18309 | fragp->fr_symbol, fragp->fr_offset, | |
18310 | FALSE, BFD_RELOC_LO16); | |
4a6a3df4 AO |
18311 | fixp->fx_file = fragp->fr_file; |
18312 | fixp->fx_line = fragp->fr_line; | |
b34976b6 | 18313 | |
4d68580a | 18314 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18315 | |
18316 | /* j(al)r $at. */ | |
18317 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) | |
66b3e8da | 18318 | insn = 0x0000f809; |
4a6a3df4 | 18319 | else |
66b3e8da MR |
18320 | insn = 0x00000008; |
18321 | insn |= at << OP_SH_RS; | |
4a6a3df4 | 18322 | |
4d68580a | 18323 | buf = write_insn (buf, insn); |
4a6a3df4 AO |
18324 | } |
18325 | } | |
18326 | ||
4a6a3df4 | 18327 | fragp->fr_fix += fragp->fr_var; |
4d68580a | 18328 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
4a6a3df4 AO |
18329 | return; |
18330 | } | |
18331 | ||
df58fc94 RS |
18332 | /* Relax microMIPS branches. */ |
18333 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) | |
18334 | { | |
4d68580a | 18335 | char *buf = fragp->fr_literal + fragp->fr_fix; |
df58fc94 | 18336 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
8484fb75 | 18337 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
7bd374a4 | 18338 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
ce8ad872 | 18339 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
df58fc94 RS |
18340 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
18341 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); | |
2309ddf2 | 18342 | bfd_boolean short_ds; |
df58fc94 | 18343 | unsigned long insn; |
df58fc94 RS |
18344 | fixS *fixp; |
18345 | ||
df58fc94 RS |
18346 | fragp->fr_fix += fragp->fr_var; |
18347 | ||
18348 | /* Handle 16-bit branches that fit or are forced to fit. */ | |
18349 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) | |
18350 | { | |
18351 | /* We generate a fixup instead of applying it right now, | |
18352 | because if there is linker relaxation, we're going to | |
18353 | need the relocations. */ | |
834a65aa MR |
18354 | switch (type) |
18355 | { | |
18356 | case 'D': | |
18357 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18358 | fragp->fr_symbol, fragp->fr_offset, | |
18359 | TRUE, BFD_RELOC_MICROMIPS_10_PCREL_S1); | |
18360 | break; | |
18361 | case 'E': | |
18362 | fixp = fix_new (fragp, buf - fragp->fr_literal, 2, | |
18363 | fragp->fr_symbol, fragp->fr_offset, | |
18364 | TRUE, BFD_RELOC_MICROMIPS_7_PCREL_S1); | |
18365 | break; | |
18366 | default: | |
18367 | abort (); | |
18368 | } | |
df58fc94 RS |
18369 | |
18370 | fixp->fx_file = fragp->fr_file; | |
18371 | fixp->fx_line = fragp->fr_line; | |
18372 | ||
18373 | /* These relocations can have an addend that won't fit in | |
18374 | 2 octets. */ | |
18375 | fixp->fx_no_overflow = 1; | |
18376 | ||
18377 | return; | |
18378 | } | |
18379 | ||
2309ddf2 | 18380 | /* Handle 32-bit branches that fit or are forced to fit. */ |
df58fc94 RS |
18381 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
18382 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18383 | { | |
18384 | /* We generate a fixup instead of applying it right now, | |
18385 | because if there is linker relaxation, we're going to | |
18386 | need the relocations. */ | |
bbd27b76 MR |
18387 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18388 | fragp->fr_symbol, fragp->fr_offset, | |
18389 | TRUE, BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18390 | fixp->fx_file = fragp->fr_file; |
18391 | fixp->fx_line = fragp->fr_line; | |
18392 | ||
18393 | if (type == 0) | |
7bd374a4 MR |
18394 | { |
18395 | insn = read_compressed_insn (buf, 4); | |
18396 | buf += 4; | |
18397 | ||
18398 | if (nods) | |
18399 | { | |
18400 | /* Check the short-delay-slot bit. */ | |
18401 | if (!al || (insn & 0x02000000) != 0) | |
18402 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18403 | else | |
18404 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18405 | } | |
18406 | ||
18407 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); | |
18408 | return; | |
18409 | } | |
df58fc94 RS |
18410 | } |
18411 | ||
18412 | /* Relax 16-bit branches to 32-bit branches. */ | |
18413 | if (type != 0) | |
18414 | { | |
4d68580a | 18415 | insn = read_compressed_insn (buf, 2); |
df58fc94 RS |
18416 | |
18417 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ | |
18418 | insn = 0x94000000; /* beq */ | |
18419 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ | |
18420 | { | |
18421 | unsigned long regno; | |
18422 | ||
18423 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; | |
18424 | regno = micromips_to_32_reg_d_map [regno]; | |
18425 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ | |
18426 | insn |= regno << MICROMIPSOP_SH_RS; | |
18427 | } | |
18428 | else | |
18429 | abort (); | |
18430 | ||
18431 | /* Nothing else to do, just write it out. */ | |
18432 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) | |
18433 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) | |
18434 | { | |
4d68580a | 18435 | buf = write_compressed_insn (buf, insn, 4); |
7bd374a4 MR |
18436 | if (nods) |
18437 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
4d68580a | 18438 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18439 | return; |
18440 | } | |
18441 | } | |
18442 | else | |
4d68580a | 18443 | insn = read_compressed_insn (buf, 4); |
df58fc94 RS |
18444 | |
18445 | /* Relax 32-bit branches to a sequence of instructions. */ | |
18446 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
1661c76c | 18447 | _("relaxed out-of-range branch into a jump")); |
df58fc94 | 18448 | |
2309ddf2 | 18449 | /* Set the short-delay-slot bit. */ |
7bd374a4 | 18450 | short_ds = !al || (insn & 0x02000000) != 0; |
df58fc94 RS |
18451 | |
18452 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) | |
18453 | { | |
18454 | symbolS *l; | |
18455 | ||
18456 | /* Reverse the branch. */ | |
18457 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ | |
18458 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ | |
18459 | insn ^= 0x20000000; | |
18460 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ | |
18461 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ | |
18462 | || (insn & 0xffe00000) == 0x40800000 /* blez */ | |
18463 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ | |
18464 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ | |
18465 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ | |
18466 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ | |
18467 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ | |
18468 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ | |
18469 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ | |
18470 | insn ^= 0x00400000; | |
18471 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ | |
18472 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ | |
18473 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ | |
18474 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ | |
18475 | insn ^= 0x00200000; | |
56d438b1 CF |
18476 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
18477 | BNZ.df */ | |
18478 | || (insn & 0xff600000) == 0x81600000) /* BZ.V | |
18479 | BNZ.V */ | |
18480 | insn ^= 0x00800000; | |
df58fc94 RS |
18481 | else |
18482 | abort (); | |
18483 | ||
18484 | if (al) | |
18485 | { | |
18486 | /* Clear the and-link and short-delay-slot bits. */ | |
18487 | gas_assert ((insn & 0xfda00000) == 0x40200000); | |
18488 | ||
18489 | /* bltzal 0x40200000 bgezal 0x40600000 */ | |
18490 | /* bltzals 0x42200000 bgezals 0x42600000 */ | |
18491 | insn &= ~0x02200000; | |
18492 | } | |
18493 | ||
18494 | /* Make a label at the end for use with the branch. */ | |
18495 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); | |
18496 | micromips_label_inc (); | |
f3ded42a | 18497 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
df58fc94 RS |
18498 | |
18499 | /* Refer to it. */ | |
4d68580a RS |
18500 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
18501 | BFD_RELOC_MICROMIPS_16_PCREL_S1); | |
df58fc94 RS |
18502 | fixp->fx_file = fragp->fr_file; |
18503 | fixp->fx_line = fragp->fr_line; | |
18504 | ||
18505 | /* Branch over the jump. */ | |
4d68580a | 18506 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18507 | |
df58fc94 | 18508 | if (!compact) |
8484fb75 MR |
18509 | { |
18510 | /* nop */ | |
18511 | if (insn32) | |
18512 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18513 | else | |
18514 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18515 | } | |
df58fc94 RS |
18516 | } |
18517 | ||
ce8ad872 | 18518 | if (!pic) |
df58fc94 | 18519 | { |
7bd374a4 MR |
18520 | unsigned long jal = (short_ds || nods |
18521 | ? 0x74000000 : 0xf4000000); /* jal/s */ | |
2309ddf2 | 18522 | |
df58fc94 RS |
18523 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
18524 | insn = al ? jal : 0xd4000000; | |
18525 | ||
bbd27b76 MR |
18526 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18527 | fragp->fr_symbol, fragp->fr_offset, | |
18528 | FALSE, BFD_RELOC_MICROMIPS_JMP); | |
df58fc94 RS |
18529 | fixp->fx_file = fragp->fr_file; |
18530 | fixp->fx_line = fragp->fr_line; | |
18531 | ||
4d68580a | 18532 | buf = write_compressed_insn (buf, insn, 4); |
8484fb75 | 18533 | |
7bd374a4 | 18534 | if (compact || nods) |
8484fb75 MR |
18535 | { |
18536 | /* nop */ | |
18537 | if (insn32) | |
18538 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18539 | else | |
18540 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18541 | } | |
df58fc94 RS |
18542 | } |
18543 | else | |
18544 | { | |
18545 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); | |
18546 | ||
18547 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ | |
18548 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; | |
18549 | insn |= at << MICROMIPSOP_SH_RT; | |
18550 | ||
bbd27b76 MR |
18551 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18552 | fragp->fr_symbol, fragp->fr_offset, | |
18553 | FALSE, BFD_RELOC_MICROMIPS_GOT16); | |
df58fc94 RS |
18554 | fixp->fx_file = fragp->fr_file; |
18555 | fixp->fx_line = fragp->fr_line; | |
18556 | ||
4d68580a | 18557 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 RS |
18558 | |
18559 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ | |
18560 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; | |
18561 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; | |
18562 | ||
bbd27b76 MR |
18563 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18564 | fragp->fr_symbol, fragp->fr_offset, | |
18565 | FALSE, BFD_RELOC_MICROMIPS_LO16); | |
df58fc94 RS |
18566 | fixp->fx_file = fragp->fr_file; |
18567 | fixp->fx_line = fragp->fr_line; | |
18568 | ||
4d68580a | 18569 | buf = write_compressed_insn (buf, insn, 4); |
df58fc94 | 18570 | |
8484fb75 MR |
18571 | if (insn32) |
18572 | { | |
18573 | /* jr/jalr $at */ | |
18574 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; | |
18575 | insn |= at << MICROMIPSOP_SH_RS; | |
18576 | ||
18577 | buf = write_compressed_insn (buf, insn, 4); | |
df58fc94 | 18578 | |
7bd374a4 | 18579 | if (compact || nods) |
8484fb75 MR |
18580 | /* nop */ |
18581 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18582 | } | |
18583 | else | |
18584 | { | |
18585 | /* jr/jrc/jalr/jalrs $at */ | |
18586 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ | |
7bd374a4 | 18587 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
8484fb75 MR |
18588 | |
18589 | insn = al ? jalr : jr; | |
18590 | insn |= at << MICROMIPSOP_SH_MJ; | |
18591 | ||
18592 | buf = write_compressed_insn (buf, insn, 2); | |
7bd374a4 MR |
18593 | if (al && nods) |
18594 | { | |
18595 | /* nop */ | |
18596 | if (short_ds) | |
18597 | buf = write_compressed_insn (buf, 0x0c00, 2); | |
18598 | else | |
18599 | buf = write_compressed_insn (buf, 0x00000000, 4); | |
18600 | } | |
8484fb75 | 18601 | } |
df58fc94 RS |
18602 | } |
18603 | ||
4d68580a | 18604 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
df58fc94 RS |
18605 | return; |
18606 | } | |
18607 | ||
252b5132 RH |
18608 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
18609 | { | |
18610 | int type; | |
3ccad066 | 18611 | const struct mips_int_operand *operand; |
252b5132 | 18612 | offsetT val; |
5c04167a | 18613 | char *buf; |
8507b6e7 | 18614 | unsigned int user_length; |
9d862524 | 18615 | bfd_boolean need_reloc; |
252b5132 | 18616 | unsigned long insn; |
8507b6e7 | 18617 | bfd_boolean mac; |
5c04167a | 18618 | bfd_boolean ext; |
88a7ef16 | 18619 | segT symsec; |
252b5132 RH |
18620 | |
18621 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); | |
3ccad066 | 18622 | operand = mips16_immed_operand (type, FALSE); |
252b5132 | 18623 | |
8507b6e7 | 18624 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
5c04167a | 18625 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
88a7ef16 | 18626 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
9d862524 MR |
18627 | |
18628 | symsec = S_GET_SEGMENT (fragp->fr_symbol); | |
18629 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) | |
8507b6e7 | 18630 | || (operand->root.type == OP_PCREL && !mac |
9d862524 MR |
18631 | ? asec != symsec |
18632 | : !bfd_is_abs_section (symsec))); | |
18633 | ||
8507b6e7 | 18634 | if (operand->root.type == OP_PCREL && !mac) |
252b5132 | 18635 | { |
3ccad066 | 18636 | const struct mips_pcrel_operand *pcrel_op; |
252b5132 | 18637 | |
3ccad066 | 18638 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
252b5132 | 18639 | |
14f72d45 | 18640 | if (pcrel_op->include_isa_bit && !need_reloc) |
252b5132 | 18641 | { |
37b2d327 MR |
18642 | if (!mips_ignore_branch_isa |
18643 | && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) | |
14f72d45 MR |
18644 | as_bad_where (fragp->fr_file, fragp->fr_line, |
18645 | _("branch to a symbol in another ISA mode")); | |
18646 | else if ((fragp->fr_offset & 0x1) != 0) | |
18647 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18648 | _("branch to misaligned address (0x%lx)"), | |
18649 | (long) val); | |
252b5132 | 18650 | } |
252b5132 | 18651 | |
14f72d45 | 18652 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
252b5132 RH |
18653 | |
18654 | /* Make sure the section winds up with the alignment we have | |
18655 | assumed. */ | |
3ccad066 RS |
18656 | if (operand->shift > 0) |
18657 | record_alignment (asec, operand->shift); | |
252b5132 RH |
18658 | } |
18659 | ||
8507b6e7 MR |
18660 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
18661 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) | |
18662 | { | |
18663 | if (mac) | |
18664 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18665 | _("macro instruction expanded into multiple " | |
18666 | "instructions in a branch delay slot")); | |
18667 | else if (ext) | |
18668 | as_warn_where (fragp->fr_file, fragp->fr_line, | |
18669 | _("extended instruction in a branch delay slot")); | |
18670 | } | |
18671 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) | |
252b5132 | 18672 | as_warn_where (fragp->fr_file, fragp->fr_line, |
8507b6e7 MR |
18673 | _("macro instruction expanded into multiple " |
18674 | "instructions")); | |
252b5132 | 18675 | |
5c04167a | 18676 | buf = fragp->fr_literal + fragp->fr_fix; |
252b5132 | 18677 | |
4d68580a | 18678 | insn = read_compressed_insn (buf, 2); |
5c04167a RS |
18679 | if (ext) |
18680 | insn |= MIPS16_EXTEND; | |
252b5132 | 18681 | |
5c04167a RS |
18682 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
18683 | user_length = 4; | |
18684 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) | |
18685 | user_length = 2; | |
18686 | else | |
18687 | user_length = 0; | |
18688 | ||
8507b6e7 | 18689 | if (mac) |
c9775dde | 18690 | { |
8507b6e7 MR |
18691 | unsigned long reg; |
18692 | unsigned long new; | |
18693 | unsigned long op; | |
25499ac7 | 18694 | bfd_boolean e2; |
8507b6e7 MR |
18695 | |
18696 | gas_assert (type == 'A' || type == 'B' || type == 'E'); | |
18697 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); | |
c9775dde | 18698 | |
25499ac7 MR |
18699 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
18700 | ||
8507b6e7 | 18701 | if (need_reloc) |
c9775dde | 18702 | { |
8507b6e7 MR |
18703 | fixS *fixp; |
18704 | ||
18705 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); | |
18706 | ||
18707 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, | |
18708 | fragp->fr_symbol, fragp->fr_offset, | |
18709 | FALSE, BFD_RELOC_MIPS16_HI16_S); | |
18710 | fixp->fx_file = fragp->fr_file; | |
18711 | fixp->fx_line = fragp->fr_line; | |
18712 | ||
25499ac7 | 18713 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
8507b6e7 MR |
18714 | fragp->fr_symbol, fragp->fr_offset, |
18715 | FALSE, BFD_RELOC_MIPS16_LO16); | |
18716 | fixp->fx_file = fragp->fr_file; | |
18717 | fixp->fx_line = fragp->fr_line; | |
18718 | ||
18719 | val = 0; | |
18720 | } | |
18721 | ||
18722 | switch (insn & 0xf800) | |
18723 | { | |
18724 | case 0x0800: /* ADDIU */ | |
18725 | reg = (insn >> 8) & 0x7; | |
18726 | op = 0xf0004800 | (reg << 8); | |
c9775dde | 18727 | break; |
8507b6e7 MR |
18728 | case 0xb000: /* LW */ |
18729 | reg = (insn >> 8) & 0x7; | |
18730 | op = 0xf0009800 | (reg << 8) | (reg << 5); | |
c9775dde | 18731 | break; |
8507b6e7 MR |
18732 | case 0xf800: /* I64 */ |
18733 | reg = (insn >> 5) & 0x7; | |
18734 | switch (insn & 0x0700) | |
18735 | { | |
18736 | case 0x0400: /* LD */ | |
18737 | op = 0xf0003800 | (reg << 8) | (reg << 5); | |
18738 | break; | |
18739 | case 0x0600: /* DADDIU */ | |
18740 | op = 0xf000fd00 | (reg << 5); | |
18741 | break; | |
18742 | default: | |
18743 | abort (); | |
18744 | } | |
18745 | break; | |
18746 | default: | |
18747 | abort (); | |
c9775dde | 18748 | } |
8507b6e7 | 18749 | |
25499ac7 | 18750 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
8507b6e7 MR |
18751 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
18752 | buf = write_compressed_insn (buf, new, 4); | |
25499ac7 MR |
18753 | if (!e2) |
18754 | { | |
18755 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ | |
18756 | buf = write_compressed_insn (buf, new, 4); | |
18757 | } | |
8507b6e7 MR |
18758 | op |= mips16_immed_extend (val, 16); |
18759 | buf = write_compressed_insn (buf, op, 4); | |
18760 | ||
25499ac7 | 18761 | fragp->fr_fix += e2 ? 8 : 12; |
8507b6e7 MR |
18762 | } |
18763 | else | |
18764 | { | |
18765 | unsigned int length = ext ? 4 : 2; | |
18766 | ||
18767 | if (need_reloc) | |
c9775dde | 18768 | { |
8507b6e7 | 18769 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
8507b6e7 | 18770 | fixS *fixp; |
c9775dde | 18771 | |
8507b6e7 MR |
18772 | switch (type) |
18773 | { | |
18774 | case 'p': | |
18775 | case 'q': | |
18776 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; | |
18777 | break; | |
18778 | default: | |
18779 | break; | |
18780 | } | |
18781 | if (mac || reloc == BFD_RELOC_NONE) | |
18782 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18783 | _("unsupported relocation")); | |
18784 | else if (ext) | |
18785 | { | |
bbd27b76 MR |
18786 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
18787 | fragp->fr_symbol, fragp->fr_offset, | |
18788 | TRUE, reloc); | |
8507b6e7 MR |
18789 | fixp->fx_file = fragp->fr_file; |
18790 | fixp->fx_line = fragp->fr_line; | |
18791 | } | |
18792 | else | |
18793 | as_bad_where (fragp->fr_file, fragp->fr_line, | |
18794 | _("invalid unextended operand value")); | |
c9775dde | 18795 | } |
eefc3365 | 18796 | else |
8507b6e7 MR |
18797 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
18798 | BFD_RELOC_UNUSED, val, user_length, &insn); | |
252b5132 | 18799 | |
8507b6e7 MR |
18800 | gas_assert (mips16_opcode_length (insn) == length); |
18801 | write_compressed_insn (buf, insn, length); | |
18802 | fragp->fr_fix += length; | |
18803 | } | |
252b5132 RH |
18804 | } |
18805 | else | |
18806 | { | |
df58fc94 RS |
18807 | relax_substateT subtype = fragp->fr_subtype; |
18808 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; | |
18809 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; | |
4d7206a2 RS |
18810 | int first, second; |
18811 | fixS *fixp; | |
252b5132 | 18812 | |
df58fc94 RS |
18813 | first = RELAX_FIRST (subtype); |
18814 | second = RELAX_SECOND (subtype); | |
4d7206a2 | 18815 | fixp = (fixS *) fragp->fr_opcode; |
252b5132 | 18816 | |
df58fc94 RS |
18817 | /* If the delay slot chosen does not match the size of the instruction, |
18818 | then emit a warning. */ | |
18819 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) | |
18820 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) | |
18821 | { | |
18822 | relax_substateT s; | |
18823 | const char *msg; | |
18824 | ||
18825 | s = subtype & (RELAX_DELAY_SLOT_16BIT | |
18826 | | RELAX_DELAY_SLOT_SIZE_FIRST | |
18827 | | RELAX_DELAY_SLOT_SIZE_SECOND); | |
18828 | msg = macro_warning (s); | |
18829 | if (msg != NULL) | |
db9b2be4 | 18830 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 RS |
18831 | subtype &= ~s; |
18832 | } | |
18833 | ||
584892a6 | 18834 | /* Possibly emit a warning if we've chosen the longer option. */ |
df58fc94 | 18835 | if (use_second == second_longer) |
584892a6 | 18836 | { |
df58fc94 RS |
18837 | relax_substateT s; |
18838 | const char *msg; | |
18839 | ||
18840 | s = (subtype | |
18841 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); | |
18842 | msg = macro_warning (s); | |
18843 | if (msg != NULL) | |
db9b2be4 | 18844 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
df58fc94 | 18845 | subtype &= ~s; |
584892a6 RS |
18846 | } |
18847 | ||
4d7206a2 RS |
18848 | /* Go through all the fixups for the first sequence. Disable them |
18849 | (by marking them as done) if we're going to use the second | |
18850 | sequence instead. */ | |
18851 | while (fixp | |
18852 | && fixp->fx_frag == fragp | |
18853 | && fixp->fx_where < fragp->fr_fix - second) | |
18854 | { | |
df58fc94 | 18855 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18856 | fixp->fx_done = 1; |
18857 | fixp = fixp->fx_next; | |
18858 | } | |
252b5132 | 18859 | |
4d7206a2 RS |
18860 | /* Go through the fixups for the second sequence. Disable them if |
18861 | we're going to use the first sequence, otherwise adjust their | |
18862 | addresses to account for the relaxation. */ | |
18863 | while (fixp && fixp->fx_frag == fragp) | |
18864 | { | |
df58fc94 | 18865 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18866 | fixp->fx_where -= first; |
18867 | else | |
18868 | fixp->fx_done = 1; | |
18869 | fixp = fixp->fx_next; | |
18870 | } | |
18871 | ||
18872 | /* Now modify the frag contents. */ | |
df58fc94 | 18873 | if (subtype & RELAX_USE_SECOND) |
4d7206a2 RS |
18874 | { |
18875 | char *start; | |
18876 | ||
18877 | start = fragp->fr_literal + fragp->fr_fix - first - second; | |
18878 | memmove (start, start + first, second); | |
18879 | fragp->fr_fix -= first; | |
18880 | } | |
18881 | else | |
18882 | fragp->fr_fix -= second; | |
252b5132 RH |
18883 | } |
18884 | } | |
18885 | ||
252b5132 RH |
18886 | /* This function is called after the relocs have been generated. |
18887 | We've been storing mips16 text labels as odd. Here we convert them | |
18888 | back to even for the convenience of the debugger. */ | |
18889 | ||
18890 | void | |
17a2f251 | 18891 | mips_frob_file_after_relocs (void) |
252b5132 RH |
18892 | { |
18893 | asymbol **syms; | |
18894 | unsigned int count, i; | |
18895 | ||
252b5132 RH |
18896 | syms = bfd_get_outsymbols (stdoutput); |
18897 | count = bfd_get_symcount (stdoutput); | |
18898 | for (i = 0; i < count; i++, syms++) | |
df58fc94 RS |
18899 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
18900 | && ((*syms)->value & 1) != 0) | |
18901 | { | |
18902 | (*syms)->value &= ~1; | |
18903 | /* If the symbol has an odd size, it was probably computed | |
18904 | incorrectly, so adjust that as well. */ | |
18905 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) | |
18906 | ++elf_symbol (*syms)->internal_elf_sym.st_size; | |
18907 | } | |
252b5132 RH |
18908 | } |
18909 | ||
a1facbec MR |
18910 | /* This function is called whenever a label is defined, including fake |
18911 | labels instantiated off the dot special symbol. It is used when | |
18912 | handling branch delays; if a branch has a label, we assume we cannot | |
18913 | move it. This also bumps the value of the symbol by 1 in compressed | |
18914 | code. */ | |
252b5132 | 18915 | |
e1b47bd5 | 18916 | static void |
a1facbec | 18917 | mips_record_label (symbolS *sym) |
252b5132 | 18918 | { |
a8dbcb85 | 18919 | segment_info_type *si = seg_info (now_seg); |
252b5132 RH |
18920 | struct insn_label_list *l; |
18921 | ||
18922 | if (free_insn_labels == NULL) | |
325801bd | 18923 | l = XNEW (struct insn_label_list); |
252b5132 RH |
18924 | else |
18925 | { | |
18926 | l = free_insn_labels; | |
18927 | free_insn_labels = l->next; | |
18928 | } | |
18929 | ||
18930 | l->label = sym; | |
a8dbcb85 TS |
18931 | l->next = si->label_list; |
18932 | si->label_list = l; | |
a1facbec | 18933 | } |
07a53e5c | 18934 | |
a1facbec MR |
18935 | /* This function is called as tc_frob_label() whenever a label is defined |
18936 | and adds a DWARF-2 record we only want for true labels. */ | |
18937 | ||
18938 | void | |
18939 | mips_define_label (symbolS *sym) | |
18940 | { | |
18941 | mips_record_label (sym); | |
07a53e5c | 18942 | dwarf2_emit_label (sym); |
252b5132 | 18943 | } |
e1b47bd5 RS |
18944 | |
18945 | /* This function is called by tc_new_dot_label whenever a new dot symbol | |
18946 | is defined. */ | |
18947 | ||
18948 | void | |
18949 | mips_add_dot_label (symbolS *sym) | |
18950 | { | |
18951 | mips_record_label (sym); | |
18952 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) | |
18953 | mips_compressed_mark_label (sym); | |
18954 | } | |
252b5132 | 18955 | \f |
351cdf24 MF |
18956 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
18957 | static unsigned int | |
18958 | mips_convert_ase_flags (int ase) | |
18959 | { | |
18960 | unsigned int ext_ases = 0; | |
18961 | ||
18962 | if (ase & ASE_DSP) | |
18963 | ext_ases |= AFL_ASE_DSP; | |
18964 | if (ase & ASE_DSPR2) | |
18965 | ext_ases |= AFL_ASE_DSPR2; | |
8f4f9071 MF |
18966 | if (ase & ASE_DSPR3) |
18967 | ext_ases |= AFL_ASE_DSPR3; | |
351cdf24 MF |
18968 | if (ase & ASE_EVA) |
18969 | ext_ases |= AFL_ASE_EVA; | |
18970 | if (ase & ASE_MCU) | |
18971 | ext_ases |= AFL_ASE_MCU; | |
18972 | if (ase & ASE_MDMX) | |
18973 | ext_ases |= AFL_ASE_MDMX; | |
18974 | if (ase & ASE_MIPS3D) | |
18975 | ext_ases |= AFL_ASE_MIPS3D; | |
18976 | if (ase & ASE_MT) | |
18977 | ext_ases |= AFL_ASE_MT; | |
18978 | if (ase & ASE_SMARTMIPS) | |
18979 | ext_ases |= AFL_ASE_SMARTMIPS; | |
18980 | if (ase & ASE_VIRT) | |
18981 | ext_ases |= AFL_ASE_VIRT; | |
18982 | if (ase & ASE_MSA) | |
18983 | ext_ases |= AFL_ASE_MSA; | |
18984 | if (ase & ASE_XPA) | |
18985 | ext_ases |= AFL_ASE_XPA; | |
25499ac7 MR |
18986 | if (ase & ASE_MIPS16E2) |
18987 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; | |
730c3174 SE |
18988 | if (ase & ASE_CRC) |
18989 | ext_ases |= AFL_ASE_CRC; | |
351cdf24 MF |
18990 | |
18991 | return ext_ases; | |
18992 | } | |
252b5132 RH |
18993 | /* Some special processing for a MIPS ELF file. */ |
18994 | ||
18995 | void | |
17a2f251 | 18996 | mips_elf_final_processing (void) |
252b5132 | 18997 | { |
351cdf24 MF |
18998 | int fpabi; |
18999 | Elf_Internal_ABIFlags_v0 flags; | |
19000 | ||
19001 | flags.version = 0; | |
19002 | flags.isa_rev = 0; | |
19003 | switch (file_mips_opts.isa) | |
19004 | { | |
19005 | case INSN_ISA1: | |
19006 | flags.isa_level = 1; | |
19007 | break; | |
19008 | case INSN_ISA2: | |
19009 | flags.isa_level = 2; | |
19010 | break; | |
19011 | case INSN_ISA3: | |
19012 | flags.isa_level = 3; | |
19013 | break; | |
19014 | case INSN_ISA4: | |
19015 | flags.isa_level = 4; | |
19016 | break; | |
19017 | case INSN_ISA5: | |
19018 | flags.isa_level = 5; | |
19019 | break; | |
19020 | case INSN_ISA32: | |
19021 | flags.isa_level = 32; | |
19022 | flags.isa_rev = 1; | |
19023 | break; | |
19024 | case INSN_ISA32R2: | |
19025 | flags.isa_level = 32; | |
19026 | flags.isa_rev = 2; | |
19027 | break; | |
19028 | case INSN_ISA32R3: | |
19029 | flags.isa_level = 32; | |
19030 | flags.isa_rev = 3; | |
19031 | break; | |
19032 | case INSN_ISA32R5: | |
19033 | flags.isa_level = 32; | |
19034 | flags.isa_rev = 5; | |
19035 | break; | |
09c14161 MF |
19036 | case INSN_ISA32R6: |
19037 | flags.isa_level = 32; | |
19038 | flags.isa_rev = 6; | |
19039 | break; | |
351cdf24 MF |
19040 | case INSN_ISA64: |
19041 | flags.isa_level = 64; | |
19042 | flags.isa_rev = 1; | |
19043 | break; | |
19044 | case INSN_ISA64R2: | |
19045 | flags.isa_level = 64; | |
19046 | flags.isa_rev = 2; | |
19047 | break; | |
19048 | case INSN_ISA64R3: | |
19049 | flags.isa_level = 64; | |
19050 | flags.isa_rev = 3; | |
19051 | break; | |
19052 | case INSN_ISA64R5: | |
19053 | flags.isa_level = 64; | |
19054 | flags.isa_rev = 5; | |
19055 | break; | |
09c14161 MF |
19056 | case INSN_ISA64R6: |
19057 | flags.isa_level = 64; | |
19058 | flags.isa_rev = 6; | |
19059 | break; | |
351cdf24 MF |
19060 | } |
19061 | ||
19062 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; | |
19063 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE | |
19064 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 | |
19065 | : (file_mips_opts.fp == 64) ? AFL_REG_64 | |
19066 | : AFL_REG_32; | |
19067 | flags.cpr2_size = AFL_REG_NONE; | |
19068 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
19069 | Tag_GNU_MIPS_ABI_FP); | |
19070 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); | |
19071 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); | |
19072 | if (file_ase_mips16) | |
19073 | flags.ases |= AFL_ASE_MIPS16; | |
19074 | if (file_ase_micromips) | |
19075 | flags.ases |= AFL_ASE_MICROMIPS; | |
19076 | flags.flags1 = 0; | |
19077 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) | |
19078 | || file_mips_opts.fp == 64) | |
19079 | && file_mips_opts.oddspreg) | |
19080 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; | |
19081 | flags.flags2 = 0; | |
19082 | ||
19083 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, | |
19084 | ((Elf_External_ABIFlags_v0 *) | |
19085 | mips_flags_frag)); | |
19086 | ||
252b5132 | 19087 | /* Write out the register information. */ |
316f5878 | 19088 | if (mips_abi != N64_ABI) |
252b5132 RH |
19089 | { |
19090 | Elf32_RegInfo s; | |
19091 | ||
19092 | s.ri_gprmask = mips_gprmask; | |
19093 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19094 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19095 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19096 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19097 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19098 | ||
19099 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, | |
19100 | ((Elf32_External_RegInfo *) | |
19101 | mips_regmask_frag)); | |
19102 | } | |
19103 | else | |
19104 | { | |
19105 | Elf64_Internal_RegInfo s; | |
19106 | ||
19107 | s.ri_gprmask = mips_gprmask; | |
19108 | s.ri_pad = 0; | |
19109 | s.ri_cprmask[0] = mips_cprmask[0]; | |
19110 | s.ri_cprmask[1] = mips_cprmask[1]; | |
19111 | s.ri_cprmask[2] = mips_cprmask[2]; | |
19112 | s.ri_cprmask[3] = mips_cprmask[3]; | |
19113 | /* The gp_value field is set by the MIPS ELF backend. */ | |
19114 | ||
19115 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, | |
19116 | ((Elf64_External_RegInfo *) | |
19117 | mips_regmask_frag)); | |
19118 | } | |
19119 | ||
19120 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some | |
19121 | sort of BFD interface for this. */ | |
19122 | if (mips_any_noreorder) | |
19123 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; | |
19124 | if (mips_pic != NO_PIC) | |
143d77c5 | 19125 | { |
8b828383 | 19126 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
143d77c5 EC |
19127 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
19128 | } | |
19129 | if (mips_abicalls) | |
19130 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; | |
252b5132 | 19131 | |
b015e599 AP |
19132 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
19133 | defined at present; this might need to change in future. */ | |
a4672219 TS |
19134 | if (file_ase_mips16) |
19135 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; | |
df58fc94 RS |
19136 | if (file_ase_micromips) |
19137 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; | |
919731af | 19138 | if (file_mips_opts.ase & ASE_MDMX) |
deec1734 | 19139 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
1f25f5d3 | 19140 | |
bdaaa2e1 | 19141 | /* Set the MIPS ELF ABI flags. */ |
316f5878 | 19142 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
252b5132 | 19143 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
316f5878 | 19144 | else if (mips_abi == O64_ABI) |
252b5132 | 19145 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
316f5878 | 19146 | else if (mips_abi == EABI_ABI) |
252b5132 | 19147 | { |
bad1aba3 | 19148 | if (file_mips_opts.gp == 64) |
252b5132 RH |
19149 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
19150 | else | |
19151 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; | |
19152 | } | |
be00bddd | 19153 | |
defc8e2b | 19154 | /* Nothing to do for N32_ABI or N64_ABI. */ |
252b5132 RH |
19155 | |
19156 | if (mips_32bitmode) | |
19157 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; | |
ad3fea08 | 19158 | |
7361da2c | 19159 | if (mips_nan2008 == 1) |
ba92f887 MR |
19160 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
19161 | ||
ad3fea08 | 19162 | /* 32 bit code with 64 bit FP registers. */ |
351cdf24 MF |
19163 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
19164 | Tag_GNU_MIPS_ABI_FP); | |
19165 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) | |
f1c38003 | 19166 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
252b5132 | 19167 | } |
252b5132 | 19168 | \f |
beae10d5 | 19169 | typedef struct proc { |
9b2f1d35 EC |
19170 | symbolS *func_sym; |
19171 | symbolS *func_end_sym; | |
beae10d5 KH |
19172 | unsigned long reg_mask; |
19173 | unsigned long reg_offset; | |
19174 | unsigned long fpreg_mask; | |
19175 | unsigned long fpreg_offset; | |
19176 | unsigned long frame_offset; | |
19177 | unsigned long frame_reg; | |
19178 | unsigned long pc_reg; | |
19179 | } procS; | |
252b5132 RH |
19180 | |
19181 | static procS cur_proc; | |
19182 | static procS *cur_proc_ptr; | |
19183 | static int numprocs; | |
19184 | ||
df58fc94 RS |
19185 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
19186 | as "2", and a normal nop as "0". */ | |
19187 | ||
19188 | #define NOP_OPCODE_MIPS 0 | |
19189 | #define NOP_OPCODE_MIPS16 1 | |
19190 | #define NOP_OPCODE_MICROMIPS 2 | |
742a56fe RS |
19191 | |
19192 | char | |
19193 | mips_nop_opcode (void) | |
19194 | { | |
df58fc94 RS |
19195 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
19196 | return NOP_OPCODE_MICROMIPS; | |
19197 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) | |
19198 | return NOP_OPCODE_MIPS16; | |
19199 | else | |
19200 | return NOP_OPCODE_MIPS; | |
742a56fe RS |
19201 | } |
19202 | ||
df58fc94 RS |
19203 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
19204 | 32-bit microMIPS NOPs here (if applicable). */ | |
a19d8eb0 | 19205 | |
0a9ef439 | 19206 | void |
17a2f251 | 19207 | mips_handle_align (fragS *fragp) |
a19d8eb0 | 19208 | { |
df58fc94 | 19209 | char nop_opcode; |
742a56fe | 19210 | char *p; |
c67a084a NC |
19211 | int bytes, size, excess; |
19212 | valueT opcode; | |
742a56fe | 19213 | |
0a9ef439 RH |
19214 | if (fragp->fr_type != rs_align_code) |
19215 | return; | |
19216 | ||
742a56fe | 19217 | p = fragp->fr_literal + fragp->fr_fix; |
df58fc94 RS |
19218 | nop_opcode = *p; |
19219 | switch (nop_opcode) | |
a19d8eb0 | 19220 | { |
df58fc94 RS |
19221 | case NOP_OPCODE_MICROMIPS: |
19222 | opcode = micromips_nop32_insn.insn_opcode; | |
19223 | size = 4; | |
19224 | break; | |
19225 | case NOP_OPCODE_MIPS16: | |
c67a084a NC |
19226 | opcode = mips16_nop_insn.insn_opcode; |
19227 | size = 2; | |
df58fc94 RS |
19228 | break; |
19229 | case NOP_OPCODE_MIPS: | |
19230 | default: | |
c67a084a NC |
19231 | opcode = nop_insn.insn_opcode; |
19232 | size = 4; | |
df58fc94 | 19233 | break; |
c67a084a | 19234 | } |
a19d8eb0 | 19235 | |
c67a084a NC |
19236 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
19237 | excess = bytes % size; | |
df58fc94 RS |
19238 | |
19239 | /* Handle the leading part if we're not inserting a whole number of | |
19240 | instructions, and make it the end of the fixed part of the frag. | |
19241 | Try to fit in a short microMIPS NOP if applicable and possible, | |
19242 | and use zeroes otherwise. */ | |
19243 | gas_assert (excess < 4); | |
19244 | fragp->fr_fix += excess; | |
19245 | switch (excess) | |
c67a084a | 19246 | { |
df58fc94 RS |
19247 | case 3: |
19248 | *p++ = '\0'; | |
19249 | /* Fall through. */ | |
19250 | case 2: | |
833794fc | 19251 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
df58fc94 | 19252 | { |
4d68580a | 19253 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
df58fc94 RS |
19254 | break; |
19255 | } | |
19256 | *p++ = '\0'; | |
19257 | /* Fall through. */ | |
19258 | case 1: | |
19259 | *p++ = '\0'; | |
19260 | /* Fall through. */ | |
19261 | case 0: | |
19262 | break; | |
a19d8eb0 | 19263 | } |
c67a084a NC |
19264 | |
19265 | md_number_to_chars (p, opcode, size); | |
19266 | fragp->fr_var = size; | |
a19d8eb0 CP |
19267 | } |
19268 | ||
252b5132 | 19269 | static long |
17a2f251 | 19270 | get_number (void) |
252b5132 RH |
19271 | { |
19272 | int negative = 0; | |
19273 | long val = 0; | |
19274 | ||
19275 | if (*input_line_pointer == '-') | |
19276 | { | |
19277 | ++input_line_pointer; | |
19278 | negative = 1; | |
19279 | } | |
3882b010 | 19280 | if (!ISDIGIT (*input_line_pointer)) |
956cd1d6 | 19281 | as_bad (_("expected simple number")); |
252b5132 RH |
19282 | if (input_line_pointer[0] == '0') |
19283 | { | |
19284 | if (input_line_pointer[1] == 'x') | |
19285 | { | |
19286 | input_line_pointer += 2; | |
3882b010 | 19287 | while (ISXDIGIT (*input_line_pointer)) |
252b5132 RH |
19288 | { |
19289 | val <<= 4; | |
19290 | val |= hex_value (*input_line_pointer++); | |
19291 | } | |
19292 | return negative ? -val : val; | |
19293 | } | |
19294 | else | |
19295 | { | |
19296 | ++input_line_pointer; | |
3882b010 | 19297 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19298 | { |
19299 | val <<= 3; | |
19300 | val |= *input_line_pointer++ - '0'; | |
19301 | } | |
19302 | return negative ? -val : val; | |
19303 | } | |
19304 | } | |
3882b010 | 19305 | if (!ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19306 | { |
19307 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), | |
19308 | *input_line_pointer, *input_line_pointer); | |
956cd1d6 | 19309 | as_warn (_("invalid number")); |
252b5132 RH |
19310 | return -1; |
19311 | } | |
3882b010 | 19312 | while (ISDIGIT (*input_line_pointer)) |
252b5132 RH |
19313 | { |
19314 | val *= 10; | |
19315 | val += *input_line_pointer++ - '0'; | |
19316 | } | |
19317 | return negative ? -val : val; | |
19318 | } | |
19319 | ||
19320 | /* The .file directive; just like the usual .file directive, but there | |
c5dd6aab DJ |
19321 | is an initial number which is the ECOFF file index. In the non-ECOFF |
19322 | case .file implies DWARF-2. */ | |
19323 | ||
19324 | static void | |
17a2f251 | 19325 | s_mips_file (int x ATTRIBUTE_UNUSED) |
c5dd6aab | 19326 | { |
ecb4347a DJ |
19327 | static int first_file_directive = 0; |
19328 | ||
c5dd6aab DJ |
19329 | if (ECOFF_DEBUGGING) |
19330 | { | |
19331 | get_number (); | |
19332 | s_app_file (0); | |
19333 | } | |
19334 | else | |
ecb4347a DJ |
19335 | { |
19336 | char *filename; | |
19337 | ||
68d20676 | 19338 | filename = dwarf2_directive_filename (); |
ecb4347a DJ |
19339 | |
19340 | /* Versions of GCC up to 3.1 start files with a ".file" | |
19341 | directive even for stabs output. Make sure that this | |
19342 | ".file" is handled. Note that you need a version of GCC | |
19343 | after 3.1 in order to support DWARF-2 on MIPS. */ | |
19344 | if (filename != NULL && ! first_file_directive) | |
19345 | { | |
19346 | (void) new_logical_line (filename, -1); | |
c04f5787 | 19347 | s_app_file_string (filename, 0); |
ecb4347a DJ |
19348 | } |
19349 | first_file_directive = 1; | |
19350 | } | |
c5dd6aab DJ |
19351 | } |
19352 | ||
19353 | /* The .loc directive, implying DWARF-2. */ | |
252b5132 RH |
19354 | |
19355 | static void | |
17a2f251 | 19356 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
252b5132 | 19357 | { |
c5dd6aab DJ |
19358 | if (!ECOFF_DEBUGGING) |
19359 | dwarf2_directive_loc (0); | |
252b5132 RH |
19360 | } |
19361 | ||
252b5132 RH |
19362 | /* The .end directive. */ |
19363 | ||
19364 | static void | |
17a2f251 | 19365 | s_mips_end (int x ATTRIBUTE_UNUSED) |
252b5132 RH |
19366 | { |
19367 | symbolS *p; | |
252b5132 | 19368 | |
7a621144 DJ |
19369 | /* Following functions need their own .frame and .cprestore directives. */ |
19370 | mips_frame_reg_valid = 0; | |
19371 | mips_cprestore_valid = 0; | |
19372 | ||
252b5132 RH |
19373 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
19374 | { | |
19375 | p = get_symbol (); | |
19376 | demand_empty_rest_of_line (); | |
19377 | } | |
19378 | else | |
19379 | p = NULL; | |
19380 | ||
14949570 | 19381 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
252b5132 RH |
19382 | as_warn (_(".end not in text section")); |
19383 | ||
19384 | if (!cur_proc_ptr) | |
19385 | { | |
1661c76c | 19386 | as_warn (_(".end directive without a preceding .ent directive")); |
252b5132 RH |
19387 | demand_empty_rest_of_line (); |
19388 | return; | |
19389 | } | |
19390 | ||
19391 | if (p != NULL) | |
19392 | { | |
9c2799c2 | 19393 | gas_assert (S_GET_NAME (p)); |
9b2f1d35 | 19394 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
1661c76c | 19395 | as_warn (_(".end symbol does not match .ent symbol")); |
ecb4347a DJ |
19396 | |
19397 | if (debug_type == DEBUG_STABS) | |
19398 | stabs_generate_asm_endfunc (S_GET_NAME (p), | |
19399 | S_GET_NAME (p)); | |
252b5132 RH |
19400 | } |
19401 | else | |
19402 | as_warn (_(".end directive missing or unknown symbol")); | |
19403 | ||
9b2f1d35 EC |
19404 | /* Create an expression to calculate the size of the function. */ |
19405 | if (p && cur_proc_ptr) | |
19406 | { | |
19407 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); | |
325801bd | 19408 | expressionS *exp = XNEW (expressionS); |
9b2f1d35 EC |
19409 | |
19410 | obj->size = exp; | |
19411 | exp->X_op = O_subtract; | |
19412 | exp->X_add_symbol = symbol_temp_new_now (); | |
19413 | exp->X_op_symbol = p; | |
19414 | exp->X_add_number = 0; | |
19415 | ||
19416 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; | |
19417 | } | |
19418 | ||
5ff6a06c MR |
19419 | #ifdef md_flush_pending_output |
19420 | md_flush_pending_output (); | |
19421 | #endif | |
19422 | ||
ecb4347a | 19423 | /* Generate a .pdr section. */ |
f3ded42a | 19424 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
ecb4347a DJ |
19425 | { |
19426 | segT saved_seg = now_seg; | |
19427 | subsegT saved_subseg = now_subseg; | |
ecb4347a DJ |
19428 | expressionS exp; |
19429 | char *fragp; | |
252b5132 | 19430 | |
9c2799c2 | 19431 | gas_assert (pdr_seg); |
ecb4347a | 19432 | subseg_set (pdr_seg, 0); |
252b5132 | 19433 | |
ecb4347a DJ |
19434 | /* Write the symbol. */ |
19435 | exp.X_op = O_symbol; | |
19436 | exp.X_add_symbol = p; | |
19437 | exp.X_add_number = 0; | |
19438 | emit_expr (&exp, 4); | |
252b5132 | 19439 | |
ecb4347a | 19440 | fragp = frag_more (7 * 4); |
252b5132 | 19441 | |
17a2f251 TS |
19442 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
19443 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); | |
19444 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); | |
19445 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); | |
19446 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); | |
19447 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); | |
19448 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); | |
252b5132 | 19449 | |
ecb4347a DJ |
19450 | subseg_set (saved_seg, saved_subseg); |
19451 | } | |
252b5132 RH |
19452 | |
19453 | cur_proc_ptr = NULL; | |
19454 | } | |
19455 | ||
19456 | /* The .aent and .ent directives. */ | |
19457 | ||
19458 | static void | |
17a2f251 | 19459 | s_mips_ent (int aent) |
252b5132 | 19460 | { |
252b5132 | 19461 | symbolS *symbolP; |
252b5132 RH |
19462 | |
19463 | symbolP = get_symbol (); | |
19464 | if (*input_line_pointer == ',') | |
f9419b05 | 19465 | ++input_line_pointer; |
252b5132 | 19466 | SKIP_WHITESPACE (); |
3882b010 | 19467 | if (ISDIGIT (*input_line_pointer) |
d9a62219 | 19468 | || *input_line_pointer == '-') |
874e8986 | 19469 | get_number (); |
252b5132 | 19470 | |
14949570 | 19471 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
1661c76c | 19472 | as_warn (_(".ent or .aent not in text section")); |
252b5132 RH |
19473 | |
19474 | if (!aent && cur_proc_ptr) | |
9a41af64 | 19475 | as_warn (_("missing .end")); |
252b5132 RH |
19476 | |
19477 | if (!aent) | |
19478 | { | |
7a621144 DJ |
19479 | /* This function needs its own .frame and .cprestore directives. */ |
19480 | mips_frame_reg_valid = 0; | |
19481 | mips_cprestore_valid = 0; | |
19482 | ||
252b5132 RH |
19483 | cur_proc_ptr = &cur_proc; |
19484 | memset (cur_proc_ptr, '\0', sizeof (procS)); | |
19485 | ||
9b2f1d35 | 19486 | cur_proc_ptr->func_sym = symbolP; |
252b5132 | 19487 | |
f9419b05 | 19488 | ++numprocs; |
ecb4347a DJ |
19489 | |
19490 | if (debug_type == DEBUG_STABS) | |
19491 | stabs_generate_asm_func (S_GET_NAME (symbolP), | |
19492 | S_GET_NAME (symbolP)); | |
252b5132 RH |
19493 | } |
19494 | ||
7c0fc524 MR |
19495 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
19496 | ||
252b5132 RH |
19497 | demand_empty_rest_of_line (); |
19498 | } | |
19499 | ||
19500 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) | |
bdaaa2e1 | 19501 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
252b5132 | 19502 | s_mips_frame is used so that we can set the PDR information correctly. |
bdaaa2e1 | 19503 | We can't use the ecoff routines because they make reference to the ecoff |
252b5132 RH |
19504 | symbol table (in the mdebug section). */ |
19505 | ||
19506 | static void | |
17a2f251 | 19507 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 19508 | { |
f3ded42a RS |
19509 | if (ECOFF_DEBUGGING) |
19510 | s_ignore (ignore); | |
19511 | else | |
ecb4347a DJ |
19512 | { |
19513 | long val; | |
252b5132 | 19514 | |
ecb4347a DJ |
19515 | if (cur_proc_ptr == (procS *) NULL) |
19516 | { | |
19517 | as_warn (_(".frame outside of .ent")); | |
19518 | demand_empty_rest_of_line (); | |
19519 | return; | |
19520 | } | |
252b5132 | 19521 | |
ecb4347a DJ |
19522 | cur_proc_ptr->frame_reg = tc_get_register (1); |
19523 | ||
19524 | SKIP_WHITESPACE (); | |
19525 | if (*input_line_pointer++ != ',' | |
19526 | || get_absolute_expression_and_terminator (&val) != ',') | |
19527 | { | |
1661c76c | 19528 | as_warn (_("bad .frame directive")); |
ecb4347a DJ |
19529 | --input_line_pointer; |
19530 | demand_empty_rest_of_line (); | |
19531 | return; | |
19532 | } | |
252b5132 | 19533 | |
ecb4347a DJ |
19534 | cur_proc_ptr->frame_offset = val; |
19535 | cur_proc_ptr->pc_reg = tc_get_register (0); | |
252b5132 | 19536 | |
252b5132 | 19537 | demand_empty_rest_of_line (); |
252b5132 | 19538 | } |
252b5132 RH |
19539 | } |
19540 | ||
bdaaa2e1 KH |
19541 | /* The .fmask and .mask directives. If the mdebug section is present |
19542 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For | |
252b5132 | 19543 | embedded targets, s_mips_mask is used so that we can set the PDR |
bdaaa2e1 | 19544 | information correctly. We can't use the ecoff routines because they |
252b5132 RH |
19545 | make reference to the ecoff symbol table (in the mdebug section). */ |
19546 | ||
19547 | static void | |
17a2f251 | 19548 | s_mips_mask (int reg_type) |
252b5132 | 19549 | { |
f3ded42a RS |
19550 | if (ECOFF_DEBUGGING) |
19551 | s_ignore (reg_type); | |
19552 | else | |
252b5132 | 19553 | { |
ecb4347a | 19554 | long mask, off; |
252b5132 | 19555 | |
ecb4347a DJ |
19556 | if (cur_proc_ptr == (procS *) NULL) |
19557 | { | |
19558 | as_warn (_(".mask/.fmask outside of .ent")); | |
19559 | demand_empty_rest_of_line (); | |
19560 | return; | |
19561 | } | |
252b5132 | 19562 | |
ecb4347a DJ |
19563 | if (get_absolute_expression_and_terminator (&mask) != ',') |
19564 | { | |
1661c76c | 19565 | as_warn (_("bad .mask/.fmask directive")); |
ecb4347a DJ |
19566 | --input_line_pointer; |
19567 | demand_empty_rest_of_line (); | |
19568 | return; | |
19569 | } | |
252b5132 | 19570 | |
ecb4347a DJ |
19571 | off = get_absolute_expression (); |
19572 | ||
19573 | if (reg_type == 'F') | |
19574 | { | |
19575 | cur_proc_ptr->fpreg_mask = mask; | |
19576 | cur_proc_ptr->fpreg_offset = off; | |
19577 | } | |
19578 | else | |
19579 | { | |
19580 | cur_proc_ptr->reg_mask = mask; | |
19581 | cur_proc_ptr->reg_offset = off; | |
19582 | } | |
19583 | ||
19584 | demand_empty_rest_of_line (); | |
252b5132 | 19585 | } |
252b5132 RH |
19586 | } |
19587 | ||
316f5878 RS |
19588 | /* A table describing all the processors gas knows about. Names are |
19589 | matched in the order listed. | |
e7af610e | 19590 | |
316f5878 RS |
19591 | To ease comparison, please keep this table in the same order as |
19592 | gcc's mips_cpu_info_table[]. */ | |
e972090a NC |
19593 | static const struct mips_cpu_info mips_cpu_info_table[] = |
19594 | { | |
316f5878 | 19595 | /* Entries for generic ISAs */ |
d16afab6 RS |
19596 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
19597 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, | |
19598 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, | |
19599 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, | |
19600 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, | |
19601 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19602 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
ae52f483 AB |
19603 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
19604 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
7361da2c | 19605 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
d16afab6 RS |
19606 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
19607 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, | |
ae52f483 AB |
19608 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
19609 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, | |
7361da2c | 19610 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
316f5878 RS |
19611 | |
19612 | /* MIPS I */ | |
d16afab6 RS |
19613 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
19614 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, | |
19615 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, | |
316f5878 RS |
19616 | |
19617 | /* MIPS II */ | |
d16afab6 | 19618 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
316f5878 RS |
19619 | |
19620 | /* MIPS III */ | |
d16afab6 RS |
19621 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
19622 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, | |
19623 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, | |
19624 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19625 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19626 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, | |
19627 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, | |
19628 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, | |
19629 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, | |
19630 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19631 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, | |
19632 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, | |
19633 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, | |
b15591bb | 19634 | /* ST Microelectronics Loongson 2E and 2F cores */ |
d16afab6 RS |
19635 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
19636 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, | |
316f5878 RS |
19637 | |
19638 | /* MIPS IV */ | |
d16afab6 RS |
19639 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
19640 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, | |
19641 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, | |
19642 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, | |
19643 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, | |
19644 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19645 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, | |
19646 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, | |
19647 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19648 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19649 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19650 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19651 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, | |
19652 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, | |
19653 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, | |
316f5878 RS |
19654 | |
19655 | /* MIPS 32 */ | |
d16afab6 RS |
19656 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
19657 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19658 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, | |
19659 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, | |
ad3fea08 TS |
19660 | |
19661 | /* MIPS 32 Release 2 */ | |
d16afab6 RS |
19662 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19663 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19664 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19665 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19666 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19667 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19668 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19669 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19670 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19671 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19672 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, | |
19673 | ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19674 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19675 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19676 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19677 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19678 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19679 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19680 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19681 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
d16afab6 RS |
19682 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19683 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19684 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19685 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19686 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19687 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19688 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
01fd108f | 19689 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
d16afab6 RS |
19690 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19691 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19692 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19693 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19694 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19695 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19696 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
711eefe4 | 19697 | /* 34Kn is a 34kc without DSP. */ |
d16afab6 | 19698 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
01fd108f | 19699 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
d16afab6 RS |
19700 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19701 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19702 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19703 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19704 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
0fdf1951 | 19705 | /* Deprecated forms of the above. */ |
d16afab6 RS |
19706 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19707 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
30f8113a | 19708 | /* 1004K cores are multiprocessor versions of the 34K. */ |
d16afab6 RS |
19709 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
19710 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19711 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
19712 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
77403ce9 RS |
19713 | /* interaptiv is the new name for 1004kf */ |
19714 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, | |
38bf472a MR |
19715 | { "interaptiv-mr2", 0, |
19716 | ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT, | |
19717 | ISA_MIPS32R3, CPU_INTERAPTIV_MR2 }, | |
c6e5c03a RS |
19718 | /* M5100 family */ |
19719 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
19720 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, | |
bbaa46c0 | 19721 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
134c0c8b | 19722 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
32b26a03 | 19723 | |
316f5878 | 19724 | /* MIPS 64 */ |
d16afab6 RS |
19725 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
19726 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, | |
19727 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
19728 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, | |
ad3fea08 | 19729 | |
c7a23324 | 19730 | /* Broadcom SB-1 CPU core */ |
d16afab6 | 19731 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
1e85aad8 | 19732 | /* Broadcom SB-1A CPU core */ |
d16afab6 | 19733 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
3739860c | 19734 | |
4ba154f5 | 19735 | { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, |
e7af610e | 19736 | |
ed163775 MR |
19737 | /* MIPS 64 Release 2 */ |
19738 | ||
967344c6 | 19739 | /* Cavium Networks Octeon CPU core */ |
d16afab6 RS |
19740 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
19741 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, | |
19742 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, | |
2c629856 | 19743 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
967344c6 | 19744 | |
52b6b6b9 | 19745 | /* RMI Xlr */ |
d16afab6 | 19746 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
52b6b6b9 | 19747 | |
55a36193 MK |
19748 | /* Broadcom XLP. |
19749 | XLP is mostly like XLR, with the prominent exception that it is | |
19750 | MIPS64R2 rather than MIPS64. */ | |
d16afab6 | 19751 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
55a36193 | 19752 | |
a4968f42 | 19753 | /* MIPS 64 Release 6 */ |
7ef0d297 | 19754 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
a4968f42 | 19755 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
7ef0d297 | 19756 | |
316f5878 | 19757 | /* End marker */ |
d16afab6 | 19758 | { NULL, 0, 0, 0, 0 } |
316f5878 | 19759 | }; |
e7af610e | 19760 | |
84ea6cf2 | 19761 | |
316f5878 RS |
19762 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
19763 | with a final "000" replaced by "k". Ignore case. | |
e7af610e | 19764 | |
316f5878 | 19765 | Note: this function is shared between GCC and GAS. */ |
c6c98b38 | 19766 | |
b34976b6 | 19767 | static bfd_boolean |
17a2f251 | 19768 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19769 | { |
19770 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) | |
19771 | given++, canonical++; | |
19772 | ||
19773 | return ((*given == 0 && *canonical == 0) | |
19774 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
19775 | } | |
19776 | ||
19777 | ||
19778 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied | |
19779 | CPU name. We've traditionally allowed a lot of variation here. | |
19780 | ||
19781 | Note: this function is shared between GCC and GAS. */ | |
19782 | ||
b34976b6 | 19783 | static bfd_boolean |
17a2f251 | 19784 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
316f5878 RS |
19785 | { |
19786 | /* First see if the name matches exactly, or with a final "000" | |
19787 | turned into "k". */ | |
19788 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
b34976b6 | 19789 | return TRUE; |
316f5878 RS |
19790 | |
19791 | /* If not, try comparing based on numerical designation alone. | |
19792 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
19793 | if (TOLOWER (*given) == 'r') | |
19794 | given++; | |
19795 | if (!ISDIGIT (*given)) | |
b34976b6 | 19796 | return FALSE; |
316f5878 RS |
19797 | |
19798 | /* Skip over some well-known prefixes in the canonical name, | |
19799 | hoping to find a number there too. */ | |
19800 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
19801 | canonical += 2; | |
19802 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
19803 | canonical += 2; | |
19804 | else if (TOLOWER (canonical[0]) == 'r') | |
19805 | canonical += 1; | |
19806 | ||
19807 | return mips_strict_matching_cpu_name_p (canonical, given); | |
19808 | } | |
19809 | ||
19810 | ||
19811 | /* Parse an option that takes the name of a processor as its argument. | |
19812 | OPTION is the name of the option and CPU_STRING is the argument. | |
19813 | Return the corresponding processor enumeration if the CPU_STRING is | |
19814 | recognized, otherwise report an error and return null. | |
19815 | ||
19816 | A similar function exists in GCC. */ | |
e7af610e NC |
19817 | |
19818 | static const struct mips_cpu_info * | |
17a2f251 | 19819 | mips_parse_cpu (const char *option, const char *cpu_string) |
e7af610e | 19820 | { |
316f5878 | 19821 | const struct mips_cpu_info *p; |
e7af610e | 19822 | |
316f5878 RS |
19823 | /* 'from-abi' selects the most compatible architecture for the given |
19824 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
19825 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
19826 | version. Look first at the -mgp options, if given, otherwise base | |
19827 | the choice on MIPS_DEFAULT_64BIT. | |
e7af610e | 19828 | |
316f5878 RS |
19829 | Treat NO_ABI like the EABIs. One reason to do this is that the |
19830 | plain 'mips' and 'mips64' configs have 'from-abi' as their default | |
19831 | architecture. This code picks MIPS I for 'mips' and MIPS III for | |
19832 | 'mips64', just as we did in the days before 'from-abi'. */ | |
19833 | if (strcasecmp (cpu_string, "from-abi") == 0) | |
19834 | { | |
19835 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) | |
19836 | return mips_cpu_info_from_isa (ISA_MIPS1); | |
19837 | ||
19838 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) | |
19839 | return mips_cpu_info_from_isa (ISA_MIPS3); | |
19840 | ||
bad1aba3 | 19841 | if (file_mips_opts.gp >= 0) |
19842 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 | |
0b35dfee | 19843 | ? ISA_MIPS1 : ISA_MIPS3); |
316f5878 RS |
19844 | |
19845 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT | |
19846 | ? ISA_MIPS3 | |
19847 | : ISA_MIPS1); | |
19848 | } | |
19849 | ||
19850 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
19851 | if (strcasecmp (cpu_string, "default") == 0) | |
19852 | return 0; | |
19853 | ||
19854 | for (p = mips_cpu_info_table; p->name != 0; p++) | |
19855 | if (mips_matching_cpu_name_p (p->name, cpu_string)) | |
19856 | return p; | |
19857 | ||
1661c76c | 19858 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
316f5878 | 19859 | return 0; |
e7af610e NC |
19860 | } |
19861 | ||
316f5878 RS |
19862 | /* Return the canonical processor information for ISA (a member of the |
19863 | ISA_MIPS* enumeration). */ | |
19864 | ||
e7af610e | 19865 | static const struct mips_cpu_info * |
17a2f251 | 19866 | mips_cpu_info_from_isa (int isa) |
e7af610e NC |
19867 | { |
19868 | int i; | |
19869 | ||
19870 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
ad3fea08 | 19871 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
316f5878 | 19872 | && isa == mips_cpu_info_table[i].isa) |
e7af610e NC |
19873 | return (&mips_cpu_info_table[i]); |
19874 | ||
e972090a | 19875 | return NULL; |
e7af610e | 19876 | } |
fef14a42 TS |
19877 | |
19878 | static const struct mips_cpu_info * | |
17a2f251 | 19879 | mips_cpu_info_from_arch (int arch) |
fef14a42 TS |
19880 | { |
19881 | int i; | |
19882 | ||
19883 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
19884 | if (arch == mips_cpu_info_table[i].cpu) | |
19885 | return (&mips_cpu_info_table[i]); | |
19886 | ||
19887 | return NULL; | |
19888 | } | |
316f5878 RS |
19889 | \f |
19890 | static void | |
17a2f251 | 19891 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
316f5878 RS |
19892 | { |
19893 | if (*first_p) | |
19894 | { | |
19895 | fprintf (stream, "%24s", ""); | |
19896 | *col_p = 24; | |
19897 | } | |
19898 | else | |
19899 | { | |
19900 | fprintf (stream, ", "); | |
19901 | *col_p += 2; | |
19902 | } | |
e7af610e | 19903 | |
316f5878 RS |
19904 | if (*col_p + strlen (string) > 72) |
19905 | { | |
19906 | fprintf (stream, "\n%24s", ""); | |
19907 | *col_p = 24; | |
19908 | } | |
19909 | ||
19910 | fprintf (stream, "%s", string); | |
19911 | *col_p += strlen (string); | |
19912 | ||
19913 | *first_p = 0; | |
19914 | } | |
19915 | ||
19916 | void | |
17a2f251 | 19917 | md_show_usage (FILE *stream) |
e7af610e | 19918 | { |
316f5878 RS |
19919 | int column, first; |
19920 | size_t i; | |
19921 | ||
19922 | fprintf (stream, _("\ | |
19923 | MIPS options:\n\ | |
316f5878 RS |
19924 | -EB generate big endian output\n\ |
19925 | -EL generate little endian output\n\ | |
19926 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ | |
19927 | -G NUM allow referencing objects up to NUM bytes\n\ | |
19928 | implicitly with the gp register [default 8]\n")); | |
19929 | fprintf (stream, _("\ | |
19930 | -mips1 generate MIPS ISA I instructions\n\ | |
19931 | -mips2 generate MIPS ISA II instructions\n\ | |
19932 | -mips3 generate MIPS ISA III instructions\n\ | |
19933 | -mips4 generate MIPS ISA IV instructions\n\ | |
19934 | -mips5 generate MIPS ISA V instructions\n\ | |
19935 | -mips32 generate MIPS32 ISA instructions\n\ | |
af7ee8bf | 19936 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
ae52f483 AB |
19937 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
19938 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ | |
7361da2c | 19939 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
316f5878 | 19940 | -mips64 generate MIPS64 ISA instructions\n\ |
5f74bc13 | 19941 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
ae52f483 AB |
19942 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
19943 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ | |
7361da2c | 19944 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
316f5878 RS |
19945 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
19946 | ||
19947 | first = 1; | |
e7af610e NC |
19948 | |
19949 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) | |
316f5878 RS |
19950 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
19951 | show (stream, "from-abi", &column, &first); | |
19952 | fputc ('\n', stream); | |
e7af610e | 19953 | |
316f5878 RS |
19954 | fprintf (stream, _("\ |
19955 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ | |
19956 | -no-mCPU don't generate code specific to CPU.\n\ | |
19957 | For -mCPU and -no-mCPU, CPU must be one of:\n")); | |
19958 | ||
19959 | first = 1; | |
19960 | ||
19961 | show (stream, "3900", &column, &first); | |
19962 | show (stream, "4010", &column, &first); | |
19963 | show (stream, "4100", &column, &first); | |
19964 | show (stream, "4650", &column, &first); | |
19965 | fputc ('\n', stream); | |
19966 | ||
19967 | fprintf (stream, _("\ | |
19968 | -mips16 generate mips16 instructions\n\ | |
19969 | -no-mips16 do not generate mips16 instructions\n")); | |
19970 | fprintf (stream, _("\ | |
f866b262 MR |
19971 | -mmips16e2 generate MIPS16e2 instructions\n\ |
19972 | -mno-mips16e2 do not generate MIPS16e2 instructions\n")); | |
19973 | fprintf (stream, _("\ | |
df58fc94 RS |
19974 | -mmicromips generate microMIPS instructions\n\ |
19975 | -mno-micromips do not generate microMIPS instructions\n")); | |
19976 | fprintf (stream, _("\ | |
e16bfa71 | 19977 | -msmartmips generate smartmips instructions\n\ |
3739860c | 19978 | -mno-smartmips do not generate smartmips instructions\n")); |
e16bfa71 | 19979 | fprintf (stream, _("\ |
74cd071d CF |
19980 | -mdsp generate DSP instructions\n\ |
19981 | -mno-dsp do not generate DSP instructions\n")); | |
19982 | fprintf (stream, _("\ | |
8b082fb1 TS |
19983 | -mdspr2 generate DSP R2 instructions\n\ |
19984 | -mno-dspr2 do not generate DSP R2 instructions\n")); | |
19985 | fprintf (stream, _("\ | |
8f4f9071 MF |
19986 | -mdspr3 generate DSP R3 instructions\n\ |
19987 | -mno-dspr3 do not generate DSP R3 instructions\n")); | |
19988 | fprintf (stream, _("\ | |
ef2e4d86 CF |
19989 | -mmt generate MT instructions\n\ |
19990 | -mno-mt do not generate MT instructions\n")); | |
19991 | fprintf (stream, _("\ | |
dec0624d MR |
19992 | -mmcu generate MCU instructions\n\ |
19993 | -mno-mcu do not generate MCU instructions\n")); | |
19994 | fprintf (stream, _("\ | |
56d438b1 CF |
19995 | -mmsa generate MSA instructions\n\ |
19996 | -mno-msa do not generate MSA instructions\n")); | |
19997 | fprintf (stream, _("\ | |
7d64c587 AB |
19998 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
19999 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); | |
20000 | fprintf (stream, _("\ | |
b015e599 AP |
20001 | -mvirt generate Virtualization instructions\n\ |
20002 | -mno-virt do not generate Virtualization instructions\n")); | |
20003 | fprintf (stream, _("\ | |
730c3174 SE |
20004 | -mcrc generate CRC instructions\n\ |
20005 | -mno-crc do not generate CRC instructions\n")); | |
20006 | fprintf (stream, _("\ | |
833794fc MR |
20007 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
20008 | -mno-insn32 generate all microMIPS instructions\n")); | |
20009 | fprintf (stream, _("\ | |
c67a084a NC |
20010 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
20011 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ | |
d766e8ec | 20012 | -mfix-vr4120 work around certain VR4120 errata\n\ |
7d8e00cf | 20013 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
6a32d874 | 20014 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
d954098f | 20015 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
316f5878 RS |
20016 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
20017 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ | |
aed1a261 | 20018 | -msym32 assume all symbols have 32-bit values\n\ |
092a534f MR |
20019 | -O0 do not remove unneeded NOPs, do not swap branches\n\ |
20020 | -O, -O1 remove unneeded NOPs, do not swap branches\n\ | |
20021 | -O2 remove unneeded NOPs and swap branches\n\ | |
316f5878 RS |
20022 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
20023 | --break, --no-trap break exception on div by 0 and mult overflow\n")); | |
037b32b9 AN |
20024 | fprintf (stream, _("\ |
20025 | -mhard-float allow floating-point instructions\n\ | |
20026 | -msoft-float do not allow floating-point instructions\n\ | |
20027 | -msingle-float only allow 32-bit floating-point operations\n\ | |
20028 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ | |
3bf0dbfb | 20029 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
ba92f887 | 20030 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
8b10b0b3 MR |
20031 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
20032 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ | |
ba92f887 MR |
20033 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
20034 | ||
20035 | first = 1; | |
20036 | ||
20037 | show (stream, "legacy", &column, &first); | |
20038 | show (stream, "2008", &column, &first); | |
20039 | ||
20040 | fputc ('\n', stream); | |
20041 | ||
316f5878 RS |
20042 | fprintf (stream, _("\ |
20043 | -KPIC, -call_shared generate SVR4 position independent code\n\ | |
861fb55a | 20044 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
0c000745 | 20045 | -mvxworks-pic generate VxWorks position independent code\n\ |
861fb55a | 20046 | -non_shared do not generate code that can operate with DSOs\n\ |
316f5878 | 20047 | -xgot assume a 32 bit GOT\n\ |
dcd410fe | 20048 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
bbe506e8 | 20049 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
d821e36b | 20050 | position dependent (non shared) code\n\ |
316f5878 RS |
20051 | -mabi=ABI create ABI conformant object file for:\n")); |
20052 | ||
20053 | first = 1; | |
20054 | ||
20055 | show (stream, "32", &column, &first); | |
20056 | show (stream, "o64", &column, &first); | |
20057 | show (stream, "n32", &column, &first); | |
20058 | show (stream, "64", &column, &first); | |
20059 | show (stream, "eabi", &column, &first); | |
20060 | ||
20061 | fputc ('\n', stream); | |
20062 | ||
20063 | fprintf (stream, _("\ | |
b4f6242e MR |
20064 | -32 create o32 ABI object file%s\n"), |
20065 | MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : ""); | |
20066 | fprintf (stream, _("\ | |
20067 | -n32 create n32 ABI object file%s\n"), | |
20068 | MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : ""); | |
20069 | fprintf (stream, _("\ | |
20070 | -64 create 64 ABI object file%s\n"), | |
20071 | MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : ""); | |
e7af610e | 20072 | } |
14e777e0 | 20073 | |
1575952e | 20074 | #ifdef TE_IRIX |
14e777e0 | 20075 | enum dwarf2_format |
413a266c | 20076 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
14e777e0 | 20077 | { |
369943fe | 20078 | if (HAVE_64BIT_SYMBOLS) |
1575952e | 20079 | return dwarf2_format_64bit_irix; |
14e777e0 KB |
20080 | else |
20081 | return dwarf2_format_32bit; | |
20082 | } | |
1575952e | 20083 | #endif |
73369e65 EC |
20084 | |
20085 | int | |
20086 | mips_dwarf2_addr_size (void) | |
20087 | { | |
6b6b3450 | 20088 | if (HAVE_64BIT_OBJECTS) |
73369e65 | 20089 | return 8; |
73369e65 EC |
20090 | else |
20091 | return 4; | |
20092 | } | |
5862107c EC |
20093 | |
20094 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
20095 | void | |
20096 | mips_cfi_frame_initial_instructions (void) | |
20097 | { | |
20098 | cfi_add_CFA_def_cfa_register (SP); | |
20099 | } | |
20100 | ||
707bfff6 TS |
20101 | int |
20102 | tc_mips_regname_to_dw2regnum (char *regname) | |
20103 | { | |
20104 | unsigned int regnum = -1; | |
20105 | unsigned int reg; | |
20106 | ||
20107 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) | |
20108 | regnum = reg; | |
20109 | ||
20110 | return regnum; | |
20111 | } | |
263b2574 | 20112 | |
20113 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. | |
20114 | Given a symbolic attribute NAME, return the proper integer value. | |
20115 | Returns -1 if the attribute is not known. */ | |
20116 | ||
20117 | int | |
20118 | mips_convert_symbolic_attribute (const char *name) | |
20119 | { | |
20120 | static const struct | |
20121 | { | |
20122 | const char * name; | |
20123 | const int tag; | |
20124 | } | |
20125 | attribute_table[] = | |
20126 | { | |
20127 | #define T(tag) {#tag, tag} | |
20128 | T (Tag_GNU_MIPS_ABI_FP), | |
20129 | T (Tag_GNU_MIPS_ABI_MSA), | |
20130 | #undef T | |
20131 | }; | |
20132 | unsigned int i; | |
20133 | ||
20134 | if (name == NULL) | |
20135 | return -1; | |
20136 | ||
20137 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) | |
20138 | if (streq (name, attribute_table[i].name)) | |
20139 | return attribute_table[i].tag; | |
20140 | ||
20141 | return -1; | |
20142 | } | |
fd5c94ab RS |
20143 | |
20144 | void | |
20145 | md_mips_end (void) | |
20146 | { | |
351cdf24 MF |
20147 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
20148 | ||
fd5c94ab RS |
20149 | mips_emit_delays (); |
20150 | if (cur_proc_ptr) | |
20151 | as_warn (_("missing .end at end of assembly")); | |
919731af | 20152 | |
20153 | /* Just in case no code was emitted, do the consistency check. */ | |
20154 | file_mips_check_options (); | |
351cdf24 MF |
20155 | |
20156 | /* Set a floating-point ABI if the user did not. */ | |
20157 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) | |
20158 | { | |
20159 | /* Perform consistency checks on the floating-point ABI. */ | |
20160 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20161 | Tag_GNU_MIPS_ABI_FP); | |
20162 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) | |
20163 | check_fpabi (fpabi); | |
20164 | } | |
20165 | else | |
20166 | { | |
20167 | /* Soft-float gets precedence over single-float, the two options should | |
20168 | not be used together so this should not matter. */ | |
20169 | if (file_mips_opts.soft_float == 1) | |
20170 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; | |
20171 | /* Single-float gets precedence over all double_float cases. */ | |
20172 | else if (file_mips_opts.single_float == 1) | |
20173 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; | |
20174 | else | |
20175 | { | |
20176 | switch (file_mips_opts.fp) | |
20177 | { | |
20178 | case 32: | |
20179 | if (file_mips_opts.gp == 32) | |
20180 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20181 | break; | |
20182 | case 0: | |
20183 | fpabi = Val_GNU_MIPS_ABI_FP_XX; | |
20184 | break; | |
20185 | case 64: | |
20186 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) | |
20187 | fpabi = Val_GNU_MIPS_ABI_FP_64A; | |
20188 | else if (file_mips_opts.gp == 32) | |
20189 | fpabi = Val_GNU_MIPS_ABI_FP_64; | |
20190 | else | |
20191 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; | |
20192 | break; | |
20193 | } | |
20194 | } | |
20195 | ||
20196 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, | |
20197 | Tag_GNU_MIPS_ABI_FP, fpabi); | |
20198 | } | |
fd5c94ab | 20199 | } |
2f0c68f2 CM |
20200 | |
20201 | /* Returns the relocation type required for a particular CFI encoding. */ | |
20202 | ||
20203 | bfd_reloc_code_real_type | |
20204 | mips_cfi_reloc_for_encoding (int encoding) | |
20205 | { | |
20206 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) | |
20207 | return BFD_RELOC_32_PCREL; | |
20208 | else return BFD_RELOC_NONE; | |
20209 | } |