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RISC-V: PR25212, Report errors for invalid march and mabi combinations.
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
CommitLineData
e23eba97 1/* tc-riscv.c -- RISC-V assembler
250d07de 2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97
NC		 3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
3d73d29e 32#include "bfd/cpu-riscv.h"
1080bf78 33#include "bfd/elfxx-riscv.h"
e23eba97
NC		 34#include "elf/riscv.h"
35#include "opcode/riscv.h"
36
37#include <stdint.h>
38
39/* Information about an instruction, including its format, operands
40 and fixups. */
41struct riscv_cl_insn
42{
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode *insn_mo;
45
46 /* The encoded instruction bits. */
47 insn_t insn_opcode;
48
49 /* The frag that contains the instruction. */
50 struct frag *frag;
51
52 /* The offset into FRAG of the first instruction byte. */
53 long where;
54
55 /* The relocs associated with the instruction, if any. */
56 fixS *fixp;
57};
58
3d73d29e
NC		 59/* All RISC-V CSR belong to one of these classes. */
60enum riscv_csr_class
61{
62 CSR_CLASS_NONE,
63
64 CSR_CLASS_I,
65 CSR_CLASS_I_32, /* rv32 only */
66 CSR_CLASS_F, /* f-ext only */
67 CSR_CLASS_DEBUG /* debug CSR */
68};
69
70/* This structure holds all restricted conditions for a CSR. */
71struct riscv_csr_extra
72{
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class;
76
77 /* CSR may have differnet numbers in the previous priv spec. */
78 unsigned address;
79
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version;
82
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version;
86
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra *next;
89};
90
91/* All standard/Z* extensions defined in all supported ISA spec. */
92struct riscv_ext_version
93{
94 const char *name;
95 enum riscv_spec_class isa_spec_class;
96 int major_version;
97 int minor_version;
98};
99
100static const struct riscv_ext_version ext_version_table[] =
101{
102 {"e", ISA_SPEC_CLASS_20191213, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2, 1, 9},
105
106 {"i", ISA_SPEC_CLASS_20191213, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2, 2, 0},
109
110 {"m", ISA_SPEC_CLASS_20191213, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2, 2, 0},
113
114 {"a", ISA_SPEC_CLASS_20191213, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2, 2, 0},
117
118 {"f", ISA_SPEC_CLASS_20191213, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2, 2, 0},
121
122 {"d", ISA_SPEC_CLASS_20191213, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2, 2, 0},
125
126 {"q", ISA_SPEC_CLASS_20191213, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2, 2, 0},
129
130 {"c", ISA_SPEC_CLASS_20191213, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2, 2, 0},
133
134 {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
136
137 {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
139
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
141
80d49d6a
KLC		 142 {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
143 {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
144 {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
145
3d73d29e
NC		 146 /* Terminate the list. */
147 {NULL, 0, 0, 0}
148};
149
e23eba97
NC		 150#ifndef DEFAULT_ARCH
151#define DEFAULT_ARCH "riscv64"
152#endif
153
2dc8dd17
JW		 154#ifndef DEFAULT_RISCV_ATTR
155#define DEFAULT_RISCV_ATTR 0
156#endif
157
8f595e9b 158/* Let riscv_after_parse_args set the default value according to xlen. */
8f595e9b
NC		 159#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
160#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
161#endif
162
dcd709e0 163/* Need to sync the version with RISC-V compiler. */
8f595e9b
NC		 164#ifndef DEFAULT_RISCV_ISA_SPEC
165#define DEFAULT_RISCV_ISA_SPEC "2.2"
166#endif
167
168#ifndef DEFAULT_RISCV_PRIV_SPEC
169#define DEFAULT_RISCV_PRIV_SPEC "1.11"
170#endif
171
e23eba97 172static const char default_arch[] = DEFAULT_ARCH;
8f595e9b 173static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
3d73d29e
NC		 174static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
175static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
e23eba97 176
dcd709e0
NC		 177static unsigned xlen = 0; /* The width of an x-register. */
178static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
5b7c81bd 179static bool rve_abi = false;
1942a048
NC		 180enum float_abi
181{
6e1605e4
NC		 182 FLOAT_ABI_DEFAULT = -1,
183 FLOAT_ABI_SOFT,
184 FLOAT_ABI_SINGLE,
185 FLOAT_ABI_DOUBLE,
186 FLOAT_ABI_QUAD
187};
188static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
e23eba97 189
2922d21d 190#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
e23eba97
NC		 191#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
192
193static unsigned elf_flags = 0;
194
dcd709e0
NC		 195/* Set the default_isa_spec. Return 0 if the spec isn't supported.
196 Otherwise, return 1. */
8f595e9b
NC		 197
198static int
199riscv_set_default_isa_spec (const char *s)
200{
3d73d29e
NC		 201 enum riscv_spec_class class = ISA_SPEC_CLASS_NONE;
202 RISCV_GET_ISA_SPEC_CLASS (s, class);
203 if (class == ISA_SPEC_CLASS_NONE)
8f595e9b 204 {
b800637e
NC		 205 as_bad ("unknown default ISA spec `%s' set by "
206 "-misa-spec or --with-isa-spec", s);
8f595e9b
NC		 207 return 0;
208 }
209 else
210 default_isa_spec = class;
211 return 1;
212}
213
dcd709e0
NC		 214/* Set the default_priv_spec. Find the privileged elf attributes when
215 the input string is NULL. Return 0 if the spec isn't supported.
216 Otherwise, return 1. */
8f595e9b
NC		 217
218static int
219riscv_set_default_priv_spec (const char *s)
220{
3d73d29e 221 enum riscv_spec_class class = PRIV_SPEC_CLASS_NONE;
8f595e9b
NC		 222 unsigned major, minor, revision;
223 obj_attribute *attr;
8f595e9b 224
3d73d29e
NC		 225 RISCV_GET_PRIV_SPEC_CLASS (s, class);
226 if (class != PRIV_SPEC_CLASS_NONE)
8f595e9b
NC		 227 {
228 default_priv_spec = class;
229 return 1;
230 }
231
232 if (s != NULL)
233 {
b800637e
NC		 234 as_bad (_("unknown default privileged spec `%s' set by "
235 "-mpriv-spec or --with-priv-spec"), s);
8f595e9b
NC		 236 return 0;
237 }
238
dcd709e0 239 /* Set the default_priv_spec by the privileged elf attributes. */
8f595e9b
NC		 240 attr = elf_known_obj_attributes_proc (stdoutput);
241 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
242 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
243 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
3d73d29e
NC		 244 /* Version 0.0.0 is the default value and meningless. */
245 if (major == 0 && minor == 0 && revision == 0)
246 return 1;
8f595e9b 247
3d73d29e
NC		 248 riscv_get_priv_spec_class_from_numbers (major, minor, revision, &class);
249 if (class != PRIV_SPEC_CLASS_NONE)
250 {
8f595e9b 251 default_priv_spec = class;
8f595e9b
NC		 252 return 1;
253 }
254
dcd709e0 255 /* Still can not find the privileged spec class. */
b800637e
NC		 256 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
257 "privileged elf attributes"), major, minor, revision);
8f595e9b
NC		 258 return 0;
259}
260
e23eba97 261/* This is the set of options which the .option pseudo-op may modify. */
e23eba97
NC		 262struct riscv_set_options
263{
264 int pic; /* Generate position-independent code. */
265 int rvc; /* Generate RVC code. */
7f999549 266 int rve; /* Generate RVE code. */
45f76423 267 int relax; /* Emit relocs the linker is allowed to relax. */
dcd709e0 268 int arch_attr; /* Emit architecture and privileged elf attributes. */
2ca89224 269 int csr_check; /* Enable the CSR checking. */
e23eba97
NC		 270};
271
272static struct riscv_set_options riscv_opts =
273{
dcd709e0
NC		 274 0, /* pic */
275 0, /* rvc */
276 0, /* rve */
277 1, /* relax */
2dc8dd17 278 DEFAULT_RISCV_ATTR, /* arch_attr */
dcd709e0 279 0, /* csr_check */
e23eba97
NC		 280};
281
282static void
5b7c81bd 283riscv_set_rvc (bool rvc_value)
e23eba97
NC		 284{
285 if (rvc_value)
286 elf_flags |= EF_RISCV_RVC;
287
288 riscv_opts.rvc = rvc_value;
289}
290
7f999549 291static void
5b7c81bd 292riscv_set_rve (bool rve_value)
7f999549
JW		 293{
294 riscv_opts.rve = rve_value;
295}
296
1080bf78 297static riscv_subset_list_t riscv_subsets;
e23eba97 298
5b7c81bd 299static bool
1080bf78 300riscv_subset_supports (const char *feature)
e23eba97 301{
dfe92496
NC		 302 struct riscv_subset_t *subset;
303
1080bf78 304 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
5b7c81bd 305 return true;
e23eba97 306
dfe92496 307 return riscv_lookup_subset (&riscv_subsets, feature, &subset);
e23eba97
NC		 308}
309
5b7c81bd 310static bool
7e9ad3a3 311riscv_multi_subset_supports (enum riscv_insn_class insn_class)
43135d3b 312{
7e9ad3a3
JW		 313 switch (insn_class)
314 {
315 case INSN_CLASS_I: return riscv_subset_supports ("i");
316 case INSN_CLASS_C: return riscv_subset_supports ("c");
317 case INSN_CLASS_A: return riscv_subset_supports ("a");
318 case INSN_CLASS_M: return riscv_subset_supports ("m");
319 case INSN_CLASS_F: return riscv_subset_supports ("f");
320 case INSN_CLASS_D: return riscv_subset_supports ("d");
729a5353 321 case INSN_CLASS_Q: return riscv_subset_supports ("q");
7e9ad3a3
JW		 322
323 case INSN_CLASS_F_AND_C:
729a5353
NC		 324 return (riscv_subset_supports ("f")
325 && riscv_subset_supports ("c"));
326 case INSN_CLASS_D_AND_C:
327 return (riscv_subset_supports ("d")
328 && riscv_subset_supports ("c"));
43135d3b 329
729a5353
NC		 330 case INSN_CLASS_ZICSR:
331 return riscv_subset_supports ("zicsr");
332 case INSN_CLASS_ZIFENCEI:
333 return riscv_subset_supports ("zifencei");
aa881ecd
PT		 334 case INSN_CLASS_ZIHINTPAUSE:
335 return riscv_subset_supports ("zihintpause");
43135d3b 336
80d49d6a
KLC		 337 case INSN_CLASS_ZBB:
338 return riscv_subset_supports ("zbb");
339
340 case INSN_CLASS_ZBA:
341 return riscv_subset_supports ("zba");
342
343 case INSN_CLASS_ZBC:
344 return riscv_subset_supports ("zbc");
345
7e9ad3a3 346 default:
b800637e 347 as_fatal ("internal: unreachable");
5b7c81bd 348 return false;
7e9ad3a3 349 }
43135d3b
JW		 350}
351
8f595e9b 352/* Handle of the extension with version hash table. */
629310ab 353static htab_t ext_version_hash = NULL;
8f595e9b 354
629310ab 355static htab_t
3d73d29e 356init_ext_version_hash (void)
8f595e9b 357{
3d73d29e 358 const struct riscv_ext_version *table = ext_version_table;
629310ab 359 htab_t hash = str_htab_create ();
3d73d29e 360 int i = 0;
8f595e9b
NC		 361
362 while (table[i].name)
363 {
364 const char *name = table[i].name;
fe0e921f 365 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
b800637e 366 as_fatal (_("internal: duplicate %s"), name);
8f595e9b
NC		 367
368 i++;
369 while (table[i].name
1942a048 370 && strcmp (table[i].name, name) == 0)
8f595e9b
NC		 371 i++;
372 }
373
374 return hash;
375}
376
377static void
378riscv_get_default_ext_version (const char *name,
7ef19aa6
NC		 379 int *major_version,
380 int *minor_version)
8f595e9b
NC		 381{
382 struct riscv_ext_version *ext;
383
8f595e9b
NC		 384 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
385 return;
386
629310ab 387 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
8f595e9b 388 while (ext
7ef19aa6
NC		 389 && ext->name
390 && strcmp (ext->name, name) == 0)
8f595e9b 391 {
2652cfad
CXW		 392 if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
393 || ext->isa_spec_class == default_isa_spec)
7ef19aa6
NC		 394 {
395 *major_version = ext->major_version;
396 *minor_version = ext->minor_version;
397 return;
398 }
8f595e9b
NC		 399 ext++;
400 }
401}
402
2922d21d 403/* Set which ISA and extensions are available. */
e23eba97 404
e23eba97 405static void
2922d21d 406riscv_set_arch (const char *s)
e23eba97 407{
1080bf78
JW		 408 riscv_parse_subset_t rps;
409 rps.subset_list = &riscv_subsets;
7ef19aa6 410 rps.error_handler = as_bad;
1080bf78 411 rps.xlen = &xlen;
8f595e9b
NC		 412 rps.get_default_version = riscv_get_default_ext_version;
413
414 if (s == NULL)
415 return;
7f999549 416
1080bf78
JW		 417 riscv_release_subset_list (&riscv_subsets);
418 riscv_parse_subset (&rps, s);
e23eba97
NC		 419}
420
dcd709e0 421/* Indicate -mabi option is explictly set. */
5b7c81bd 422static bool explicit_mabi = false;
6e1605e4
NC		 423
424static void
5b7c81bd 425riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve)
6e1605e4
NC		 426{
427 abi_xlen = new_xlen;
428 float_abi = new_float_abi;
429 rve_abi = rve;
430}
431
dcd709e0
NC		 432/* If the -mabi option isn't set, then set the abi according to the
433 ISA string. Otherwise, check if there is any conflict. */
6e1605e4
NC		 434
435static void
436riscv_set_abi_by_arch (void)
437{
438 if (!explicit_mabi)
439 {
440 if (riscv_subset_supports ("q"))
5b7c81bd 441 riscv_set_abi (xlen, FLOAT_ABI_QUAD, false);
6e1605e4 442 else if (riscv_subset_supports ("d"))
5b7c81bd 443 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false);
5d0ed830
NC		 444 else if (riscv_subset_supports ("e"))
445 riscv_set_abi (xlen, FLOAT_ABI_SOFT, true);
6e1605e4 446 else
5b7c81bd 447 riscv_set_abi (xlen, FLOAT_ABI_SOFT, false);
6e1605e4
NC		 448 }
449 else
450 {
451 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
452 if (abi_xlen > xlen)
453 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
454 else if (abi_xlen < xlen)
455 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
5d0ed830
NC		 456
457 if (riscv_subset_supports ("e") && !rve_abi)
458 as_bad ("only the ilp32e ABI is supported for e extension");
459
460 if (float_abi == FLOAT_ABI_SINGLE
461 && !riscv_subset_supports ("f"))
462 as_bad ("ilp32f/lp64f ABI can't be used when f extension "
463 "isn't supported");
464 else if (float_abi == FLOAT_ABI_DOUBLE
465 && !riscv_subset_supports ("d"))
466 as_bad ("ilp32d/lp64d ABI can't be used when d extension "
467 "isn't supported");
468 else if (float_abi == FLOAT_ABI_QUAD
469 && !riscv_subset_supports ("q"))
470 as_bad ("ilp32q/lp64q ABI can't be used when q extension "
471 "isn't supported");
6e1605e4
NC		 472 }
473
474 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
475 elf_flags &= ~EF_RISCV_FLOAT_ABI;
476 elf_flags |= float_abi << 1;
477
478 if (rve_abi)
479 elf_flags |= EF_RISCV_RVE;
480}
481
e23eba97 482/* Handle of the OPCODE hash table. */
629310ab 483static htab_t op_hash = NULL;
e23eba97 484
0e35537d 485/* Handle of the type of .insn hash table. */
629310ab 486static htab_t insn_type_hash = NULL;
0e35537d 487
e23eba97 488/* This array holds the chars that always start a comment. If the
dcd709e0 489 pre-processor is disabled, these aren't very useful. */
e23eba97
NC		 490const char comment_chars[] = "#";
491
492/* This array holds the chars that only start a comment at the beginning of
493 a line. If the line seems to have the form '# 123 filename'
dcd709e0
NC		 494 .line and .file directives will appear in the pre-processed output
495
496 Note that input_file.c hand checks for '#' at the beginning of the
e23eba97 497 first line of the input file. This is because the compiler outputs
dcd709e0
NC		 498 #NO_APP at the beginning of its output.
499
500 Also note that C style comments are always supported. */
e23eba97
NC		 501const char line_comment_chars[] = "#";
502
503/* This array holds machine specific line separator characters. */
504const char line_separator_chars[] = ";";
505
dcd709e0 506/* Chars that can be used to separate mant from exp in floating point nums. */
e23eba97
NC		 507const char EXP_CHARS[] = "eE";
508
dcd709e0
NC		 509/* Chars that mean this number is a floating point constant.
510 As in 0f12.456 or 0d1.2345e12. */
e23eba97
NC		 511const char FLT_CHARS[] = "rRsSfFdDxXpP";
512
2dc8dd17 513/* Indicate we are already assemble any instructions or not. */
5b7c81bd 514static bool start_assemble = false;
2dc8dd17 515
f9a6a8f0 516/* Indicate ELF attributes are explicitly set. */
5b7c81bd 517static bool explicit_attr = false;
2dc8dd17 518
f9a6a8f0 519/* Indicate CSR or priv instructions are explicitly used. */
5b7c81bd 520static bool explicit_priv_attr = false;
3fc6c3dc 521
e23eba97
NC		 522/* Macros for encoding relaxation state for RVC branches and far jumps. */
523#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
524 ((relax_substateT) \
525 (0xc0000000 \
526 | ((uncond) ? 1 : 0) \
527 | ((rvc) ? 2 : 0) \
528 | ((length) << 2)))
529#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
530#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
531#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
532#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
533
534/* Is the given value a sign-extended 32-bit value? */
535#define IS_SEXT_32BIT_NUM(x) \
536 (((x) &~ (offsetT) 0x7fffffff) == 0 \
537 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
538
539/* Is the given value a zero-extended 32-bit value? Or a negated one? */
540#define IS_ZEXT_32BIT_NUM(x) \
541 (((x) &~ (offsetT) 0xffffffff) == 0 \
542 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
543
544/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
545 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
546#define INSERT_OPERAND(FIELD, INSN, VALUE) \
547 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
548
549/* Determine if an instruction matches an opcode. */
550#define OPCODE_MATCHES(OPCODE, OP) \
551 (((OPCODE) & MASK_##OP) == MATCH_##OP)
552
553static char *expr_end;
554
555/* The default target format to use. */
556
557const char *
558riscv_target_format (void)
559{
fbc09e7a
MC		 560 if (target_big_endian)
561 return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
562 else
563 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
e23eba97
NC		 564}
565
566/* Return the length of instruction INSN. */
567
568static inline unsigned int
569insn_length (const struct riscv_cl_insn *insn)
570{
571 return riscv_insn_length (insn->insn_opcode);
572}
573
574/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
575
576static void
577create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
578{
579 insn->insn_mo = mo;
580 insn->insn_opcode = mo->match;
581 insn->frag = NULL;
582 insn->where = 0;
583 insn->fixp = NULL;
584}
585
586/* Install INSN at the location specified by its "frag" and "where" fields. */
587
588static void
589install_insn (const struct riscv_cl_insn *insn)
590{
591 char *f = insn->frag->fr_literal + insn->where;
fbc09e7a 592 number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
e23eba97
NC		 593}
594
595/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
596 and install the opcode in the new location. */
597
598static void
599move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
600{
601 insn->frag = frag;
602 insn->where = where;
603 if (insn->fixp != NULL)
604 {
605 insn->fixp->fx_frag = frag;
606 insn->fixp->fx_where = where;
607 }
608 install_insn (insn);
609}
610
611/* Add INSN to the end of the output. */
612
613static void
614add_fixed_insn (struct riscv_cl_insn *insn)
615{
616 char *f = frag_more (insn_length (insn));
617 move_insn (insn, frag_now, f - frag_now->fr_literal);
618}
619
620static void
621add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
622 relax_substateT subtype, symbolS *symbol, offsetT offset)
623{
624 frag_grow (max_chars);
625 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
626 frag_var (rs_machine_dependent, max_chars, var,
627 subtype, symbol, offset, NULL);
628}
629
630/* Compute the length of a branch sequence, and adjust the stored length
631 accordingly. If FRAGP is NULL, the worst-case length is returned. */
632
633static unsigned
634relaxed_branch_length (fragS *fragp, asection *sec, int update)
635{
636 int jump, rvc, length = 8;
637
638 if (!fragp)
639 return length;
640
641 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
642 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
643 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
644
645 /* Assume jumps are in range; the linker will catch any that aren't. */
646 length = jump ? 4 : 8;
647
648 if (fragp->fr_symbol != NULL
649 && S_IS_DEFINED (fragp->fr_symbol)
01156111 650 && !S_IS_WEAK (fragp->fr_symbol)
e23eba97
NC		 651 && sec == S_GET_SEGMENT (fragp->fr_symbol))
652 {
653 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
654 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
655 val -= fragp->fr_address + fragp->fr_fix;
656
657 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
658 length = 2;
659 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
660 length = 4;
661 else if (!jump && rvc)
662 length = 6;
663 }
664
665 if (update)
666 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
667
668 return length;
669}
670
0e35537d
JW		 671/* Information about an opcode name, mnemonics and its value. */
672struct opcode_name_t
673{
674 const char *name;
675 unsigned int val;
676};
677
678/* List for all supported opcode name. */
679static const struct opcode_name_t opcode_name_list[] =
680{
681 {"C0", 0x0},
682 {"C1", 0x1},
683 {"C2", 0x2},
684
685 {"LOAD", 0x03},
686 {"LOAD_FP", 0x07},
687 {"CUSTOM_0", 0x0b},
688 {"MISC_MEM", 0x0f},
689 {"OP_IMM", 0x13},
690 {"AUIPC", 0x17},
691 {"OP_IMM_32", 0x1b},
692 /* 48b 0x1f. */
693
694 {"STORE", 0x23},
695 {"STORE_FP", 0x27},
696 {"CUSTOM_1", 0x2b},
697 {"AMO", 0x2f},
698 {"OP", 0x33},
699 {"LUI", 0x37},
700 {"OP_32", 0x3b},
701 /* 64b 0x3f. */
702
703 {"MADD", 0x43},
704 {"MSUB", 0x47},
705 {"NMADD", 0x4f},
706 {"NMSUB", 0x4b},
707 {"OP_FP", 0x53},
708 /*reserved 0x57. */
709 {"CUSTOM_2", 0x5b},
710 /* 48b 0x5f. */
711
712 {"BRANCH", 0x63},
713 {"JALR", 0x67},
714 /*reserved 0x5b. */
715 {"JAL", 0x6f},
716 {"SYSTEM", 0x73},
717 /*reserved 0x77. */
718 {"CUSTOM_3", 0x7b},
719 /* >80b 0x7f. */
720
721 {NULL, 0}
722};
723
724/* Hash table for lookup opcode name. */
629310ab 725static htab_t opcode_names_hash = NULL;
0e35537d
JW		 726
727/* Initialization for hash table of opcode name. */
dcd709e0 728
0e35537d
JW		 729static void
730init_opcode_names_hash (void)
731{
0e35537d
JW		 732 const struct opcode_name_t *opcode;
733
734 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
fe0e921f 735 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
b800637e 736 as_fatal (_("internal: duplicate %s"), opcode->name);
0e35537d
JW		 737}
738
dcd709e0
NC		 739/* Find `s` is a valid opcode name or not, return the opcode name info
740 if found. */
741
0e35537d
JW		 742static const struct opcode_name_t *
743opcode_name_lookup (char **s)
744{
745 char *e;
746 char save_c;
747 struct opcode_name_t *o;
748
749 /* Find end of name. */
750 e = *s;
751 if (is_name_beginner (*e))
752 ++e;
753 while (is_part_of_name (*e))
754 ++e;
755
756 /* Terminate name. */
757 save_c = *e;
758 *e = '\0';
759
629310ab 760 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
0e35537d
JW		 761
762 /* Advance to next token if one was recognized. */
763 if (o)
764 *s = e;
765
766 *e = save_c;
767 expr_end = e;
768
769 return o;
770}
771
e23eba97
NC		 772enum reg_class
773{
774 RCLASS_GPR,
775 RCLASS_FPR,
8f595e9b
NC		 776 RCLASS_MAX,
777
778 RCLASS_CSR
e23eba97
NC		 779};
780
629310ab
ML		 781static htab_t reg_names_hash = NULL;
782static htab_t csr_extra_hash = NULL;
e23eba97
NC		 783
784#define ENCODE_REG_HASH(cls, n) \
785 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
786#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
787#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
788
789static void
790hash_reg_name (enum reg_class class, const char *name, unsigned n)
791{
792 void *hash = ENCODE_REG_HASH (class, n);
fe0e921f 793 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
b800637e 794 as_fatal (_("internal: duplicate %s"), name);
e23eba97
NC		 795}
796
797static void
798hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
799{
800 unsigned i;
801
802 for (i = 0; i < n; i++)
803 hash_reg_name (class, names[i], i);
804}
805
8f595e9b 806/* Init hash table csr_extra_hash to handle CSR. */
dcd709e0 807
8f595e9b
NC		 808static void
809riscv_init_csr_hash (const char *name,
3d73d29e
NC		 810 unsigned address,
811 enum riscv_csr_class class,
812 enum riscv_spec_class define_version,
813 enum riscv_spec_class abort_version)
8f595e9b
NC		 814{
815 struct riscv_csr_extra *entry, *pre_entry;
5b7c81bd 816 bool need_enrty = true;
8f595e9b
NC		 817
818 pre_entry = NULL;
629310ab 819 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
8f595e9b
NC		 820 while (need_enrty && entry != NULL)
821 {
822 if (entry->csr_class == class
1942a048
NC		 823 && entry->address == address
824 && entry->define_version == define_version
825 && entry->abort_version == abort_version)
5b7c81bd 826 need_enrty = false;
8f595e9b
NC		 827 pre_entry = entry;
828 entry = entry->next;
829 }
1942a048 830
dcd709e0 831 /* Duplicate CSR. */
8f595e9b
NC		 832 if (!need_enrty)
833 return;
bd0cf5a6 834
8f595e9b
NC		 835 entry = XNEW (struct riscv_csr_extra);
836 entry->csr_class = class;
837 entry->address = address;
838 entry->define_version = define_version;
839 entry->abort_version = abort_version;
5c505568 840 entry->next = NULL;
8f595e9b 841
8f595e9b 842 if (pre_entry == NULL)
fe0e921f 843 str_hash_insert (csr_extra_hash, name, entry, 0);
8f595e9b
NC		 844 else
845 pre_entry->next = entry;
846}
bd0cf5a6 847
dcd709e0
NC		 848/* Return the CSR address after checking the ISA dependency and
849 the privileged spec version.
850
851 There are one warning and two errors for CSR,
852
853 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
854 or the privileged spec, report warning only if -mcsr-check is set.
855 Unknown CSR: the CSR has never been defined, report error.
856 Improper CSR: the CSR number over the range (> 0xfff), report error. */
bd0cf5a6 857
08ccfccf
NC		 858static unsigned int
859riscv_csr_address (const char *csr_name,
860 struct riscv_csr_extra *entry)
bd0cf5a6 861{
08ccfccf
NC		 862 struct riscv_csr_extra *saved_entry = entry;
863 enum riscv_csr_class csr_class = entry->csr_class;
5b7c81bd
AM		 864 bool need_check_version = true;
865 bool result = true;
8f595e9b 866
8f595e9b 867 switch (csr_class)
bd0cf5a6 868 {
8f595e9b
NC		 869 case CSR_CLASS_I:
870 result = riscv_subset_supports ("i");
871 break;
08ccfccf
NC		 872 case CSR_CLASS_I_32:
873 result = (xlen == 32 && riscv_subset_supports ("i"));
874 break;
8f595e9b
NC		 875 case CSR_CLASS_F:
876 result = riscv_subset_supports ("f");
5b7c81bd 877 need_check_version = false;
8f595e9b 878 break;
08ccfccf 879 case CSR_CLASS_DEBUG:
5b7c81bd 880 need_check_version = false;
8f595e9b
NC		 881 break;
882 default:
883 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
bd0cf5a6
NC		 884 }
885
08ccfccf 886 if (riscv_opts.csr_check && !result)
b800637e 887 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name);
8f595e9b
NC		 888
889 while (entry != NULL)
bd0cf5a6 890 {
08ccfccf
NC		 891 if (!need_check_version
892 || (default_priv_spec >= entry->define_version
893 && default_priv_spec < entry->abort_version))
8f595e9b 894 {
dcd709e0 895 /* Find the CSR according to the specific version. */
08ccfccf 896 return entry->address;
8f595e9b
NC		 897 }
898 entry = entry->next;
899 }
bd0cf5a6 900
dcd709e0
NC		 901 /* Can not find the CSR address from the chosen privileged version,
902 so use the newly defined value. */
8f595e9b
NC		 903 if (riscv_opts.csr_check)
904 {
3d73d29e
NC		 905 const char *priv_name = NULL;
906 RISCV_GET_PRIV_SPEC_NAME (priv_name, default_priv_spec);
8f595e9b 907 if (priv_name != NULL)
b800637e 908 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
8f595e9b 909 csr_name, priv_name);
bd0cf5a6 910 }
08ccfccf
NC		 911
912 return saved_entry->address;
bd0cf5a6
NC		 913}
914
dcd709e0
NC		 915/* Return -1 if the CSR has never been defined. Otherwise, return
916 the address. */
bd0cf5a6 917
8f595e9b 918static unsigned int
bd0cf5a6
NC		 919reg_csr_lookup_internal (const char *s)
920{
921 struct riscv_csr_extra *r =
629310ab 922 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
bd0cf5a6
NC		 923
924 if (r == NULL)
8f595e9b 925 return -1U;
bd0cf5a6 926
08ccfccf 927 return riscv_csr_address (s, r);
bd0cf5a6
NC		 928}
929
e23eba97
NC		 930static unsigned int
931reg_lookup_internal (const char *s, enum reg_class class)
932{
8f595e9b
NC		 933 void *r;
934
935 if (class == RCLASS_CSR)
936 return reg_csr_lookup_internal (s);
e23eba97 937
629310ab 938 r = str_hash_find (reg_names_hash, s);
e23eba97
NC		 939 if (r == NULL || DECODE_REG_CLASS (r) != class)
940 return -1;
7f999549
JW		 941
942 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
943 return -1;
944
e23eba97
NC		 945 return DECODE_REG_NUM (r);
946}
947
5b7c81bd 948static bool
e23eba97
NC		 949reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
950{
951 char *e;
952 char save_c;
953 int reg = -1;
954
955 /* Find end of name. */
956 e = *s;
957 if (is_name_beginner (*e))
958 ++e;
959 while (is_part_of_name (*e))
960 ++e;
961
962 /* Terminate name. */
963 save_c = *e;
964 *e = '\0';
965
966 /* Look for the register. Advance to next token if one was recognized. */
967 if ((reg = reg_lookup_internal (*s, class)) >= 0)
968 *s = e;
969
970 *e = save_c;
971 if (regnop)
972 *regnop = reg;
973 return reg >= 0;
974}
975
5b7c81bd 976static bool
e23eba97
NC		 977arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
978{
979 const char *p = strchr (*s, ',');
980 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
981
bfb218e3 982 if (len == 0)
5b7c81bd 983 return false;
bfb218e3 984
e23eba97
NC		 985 for (i = 0; i < size; i++)
986 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
987 {
988 *regnop = i;
989 *s += len;
5b7c81bd 990 return true;
e23eba97
NC		 991 }
992
5b7c81bd 993 return false;
e23eba97
NC		 994}
995
996/* For consistency checking, verify that all bits are specified either
997 by the match/mask part of the instruction definition, or by the
dcd709e0 998 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
0e35537d 999
5b7c81bd 1000static bool
0e35537d 1001validate_riscv_insn (const struct riscv_opcode *opc, int length)
e23eba97
NC		 1002{
1003 const char *p = opc->args;
1004 char c;
1005 insn_t used_bits = opc->mask;
0e35537d
JW		 1006 int insn_width;
1007 insn_t required_bits;
1008
1009 if (length == 0)
1010 insn_width = 8 * riscv_insn_length (opc->match);
1011 else
1012 insn_width = 8 * length;
1013
1014 required_bits = ~0ULL >> (64 - insn_width);
e23eba97
NC		 1015
1016 if ((used_bits & opc->match) != (opc->match & required_bits))
1017 {
1018 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1019 opc->name, opc->args);
5b7c81bd 1020 return false;
e23eba97
NC		 1021 }
1022
1023#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1024 while (*p)
1025 switch (c = *p++)
1026 {
1027 case 'C': /* RVC */
1028 switch (c = *p++)
1029 {
5a9f5403
NC		 1030 case 'U': break; /* CRS1, constrained to equal RD. */
1031 case 'c': break; /* CRS1, constrained to equal sp. */
1032 case 'T': /* CRS2, floating point. */
1033 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1034 case 'S': /* CRS1S, floating point. */
e23eba97 1035 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
5a9f5403
NC		 1036 case 'w': break; /* CRS1S, constrained to equal RD. */
1037 case 'D': /* CRS2S, floating point. */
e23eba97 1038 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
5a9f5403
NC		 1039 case 'x': break; /* CRS2S, constrained to equal RD. */
1040 case 'z': break; /* CRS2S, constrained to be x0. */
1041 case '>': /* CITYPE immediate, compressed shift. */
1042 case 'u': /* CITYPE immediate, compressed lui. */
1043 case 'v': /* CITYPE immediate, li to compressed lui. */
1044 case 'o': /* CITYPE immediate, allow zero. */
1045 case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break;
1046 case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1047 case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1048 case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1049 case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break;
1050 case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1051 case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1052 case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break;
1053 case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1054 /* CLTYPE and CSTYPE have the same immediate encoding. */
1055 case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break;
1056 case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break;
1057 case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break;
1058 case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break;
1059 case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break;
1060 case 'F': /* Compressed funct for .insn directive. */
0e35537d
JW		 1061 switch (c = *p++)
1062 {
4765cd61 1063 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
0e35537d
JW		 1064 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
1065 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
4765cd61 1066 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
0e35537d 1067 default:
b800637e
NC		 1068 as_bad (_("internal: bad RISC-V opcode "
1069 "(unknown operand type `CF%c'): %s %s"),
0e35537d 1070 c, opc->name, opc->args);
5b7c81bd 1071 return false;
0e35537d
JW		 1072 }
1073 break;
e23eba97 1074 default:
b800637e
NC		 1075 as_bad (_("internal: bad RISC-V opcode "
1076 "(unknown operand type `C%c'): %s %s"),
e23eba97 1077 c, opc->name, opc->args);
5b7c81bd 1078 return false;
e23eba97
NC		 1079 }
1080 break;
1081 case ',': break;
1082 case '(': break;
1083 case ')': break;
1942a048
NC		 1084 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
1085 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
5a9f5403
NC		 1086 case 'A': break; /* Macro operand, must be symbol. */
1087 case 'B': break; /* Macro operand, must be symbol or constant. */
1088 case 'I': break; /* Macro operand, must be constant. */
1089 case 'D': /* RD, floating point. */
1942a048 1090 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
5a9f5403
NC		 1091 case 'Z': /* RS1, CSR number. */
1092 case 'S': /* RS1, floating point. */
1942a048 1093 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
5a9f5403
NC		 1094 case 'U': /* RS1 and RS2 are the same, floating point. */
1095 USE_BITS (OP_MASK_RS1, OP_SH_RS1);
1096 /* Fall through. */
1097 case 'T': /* RS2, floating point. */
1942a048 1098 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
5a9f5403
NC		 1099 case 'R': /* RS3, floating point. */
1100 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
1101 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
1102 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
1942a048
NC		 1103 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
1104 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
5a9f5403 1105 case 'o': /* ITYPE immediate, load displacement. */
1d65abb5 1106 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
5a9f5403
NC		 1107 case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
1108 case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
1942a048
NC		 1109 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
1110 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
5a9f5403
NC		 1111 case 'z': break; /* Zero immediate. */
1112 case '[': break; /* Unused operand. */
1113 case ']': break; /* Unused operand. */
1114 case '0': break; /* AMO displacement, must to zero. */
1115 case '1': break; /* Relaxation operand. */
dcd709e0 1116 case 'F': /* Funct for .insn directive. */
0e35537d
JW		 1117 switch (c = *p++)
1118 {
1119 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
1120 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
1121 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
1122 default:
b800637e
NC		 1123 as_bad (_("internal: bad RISC-V opcode "
1124 "(unknown operand type `F%c'): %s %s"),
0e35537d 1125 c, opc->name, opc->args);
5b7c81bd 1126 return false;
0e35537d
JW		 1127 }
1128 break;
dcd709e0 1129 case 'O': /* Opcode for .insn directive. */
0e35537d
JW		 1130 switch (c = *p++)
1131 {
1132 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1133 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1134 default:
b800637e
NC		 1135 as_bad (_("internal: bad RISC-V opcode "
1136 "(unknown operand type `F%c'): %s %s"),
0e35537d 1137 c, opc->name, opc->args);
5b7c81bd 1138 return false;
0e35537d
JW		 1139 }
1140 break;
e23eba97
NC		 1141 default:
1142 as_bad (_("internal: bad RISC-V opcode "
1143 "(unknown operand type `%c'): %s %s"),
1144 c, opc->name, opc->args);
5b7c81bd 1145 return false;
e23eba97
NC		 1146 }
1147#undef USE_BITS
1148 if (used_bits != required_bits)
1149 {
b800637e
NC		 1150 as_bad (_("internal: bad RISC-V opcode "
1151 "(bits 0x%lx undefined): %s %s"),
e23eba97
NC		 1152 ~(unsigned long)(used_bits & required_bits),
1153 opc->name, opc->args);
5b7c81bd 1154 return false;
e23eba97 1155 }
5b7c81bd 1156 return true;
e23eba97
NC		 1157}
1158
1159struct percent_op_match
1160{
1161 const char *str;
1162 bfd_reloc_code_real_type reloc;
1163};
1164
dcd709e0
NC		 1165/* Common hash table initialization function for instruction and .insn
1166 directive. */
1167
629310ab 1168static htab_t
0e35537d 1169init_opcode_hash (const struct riscv_opcode *opcodes,
5b7c81bd 1170 bool insn_directive_p)
e23eba97
NC		 1171{
1172 int i = 0;
0e35537d 1173 int length;
629310ab 1174 htab_t hash = str_htab_create ();
0e35537d 1175 while (opcodes[i].name)
e23eba97 1176 {
0e35537d 1177 const char *name = opcodes[i].name;
fe0e921f 1178 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
b800637e 1179 as_fatal (_("internal: duplicate %s"), name);
e23eba97
NC		 1180
1181 do
1182 {
0e35537d 1183 if (opcodes[i].pinfo != INSN_MACRO)
e23eba97 1184 {
0e35537d
JW		 1185 if (insn_directive_p)
1186 length = ((name[0] == 'c') ? 2 : 4);
1187 else
dcd709e0 1188 length = 0; /* Let assembler determine the length. */
0e35537d 1189 if (!validate_riscv_insn (&opcodes[i], length))
b800637e
NC		 1190 as_fatal (_("internal: broken assembler. "
1191 "No assembly attempted"));
e23eba97 1192 }
0e35537d
JW		 1193 else
1194 gas_assert (!insn_directive_p);
e23eba97
NC		 1195 ++i;
1196 }
0e35537d 1197 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
e23eba97
NC		 1198 }
1199
0e35537d
JW		 1200 return hash;
1201}
1202
1203/* This function is called once, at assembler startup time. It should set up
1204 all the tables, etc. that the MD part of the assembler will need. */
1205
1206void
1207md_begin (void)
1208{
1209 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1210
1211 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
b800637e 1212 as_warn (_("could not set architecture and machine"));
0e35537d 1213
5b7c81bd
AM		 1214 op_hash = init_opcode_hash (riscv_opcodes, false);
1215 insn_type_hash = init_opcode_hash (riscv_insn_types, true);
0e35537d 1216
629310ab 1217 reg_names_hash = str_htab_create ();
e23eba97
NC		 1218 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1219 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1220 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1221 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
b9c04e5a
JW		 1222 /* Add "fp" as an alias for "s0". */
1223 hash_reg_name (RCLASS_GPR, "fp", 8);
1224
bd0cf5a6 1225 /* Create and insert CSR hash tables. */
629310ab 1226 csr_extra_hash = str_htab_create ();
8f595e9b
NC		 1227#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1228 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1229#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1230 DECLARE_CSR(name, num, class, define_version, abort_version);
e23eba97
NC		 1231#include "opcode/riscv-opc.h"
1232#undef DECLARE_CSR
1233
629310ab 1234 opcode_names_hash = str_htab_create ();
bd0cf5a6
NC		 1235 init_opcode_names_hash ();
1236
e23eba97
NC		 1237 /* Set the default alignment for the text section. */
1238 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1239}
1240
45f76423
AW		 1241static insn_t
1242riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1243{
1244 switch (reloc_type)
1245 {
1246 case BFD_RELOC_32:
1247 return value;
1248
1249 case BFD_RELOC_RISCV_HI20:
1250 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1251
1252 case BFD_RELOC_RISCV_LO12_S:
1253 return ENCODE_STYPE_IMM (value);
1254
1255 case BFD_RELOC_RISCV_LO12_I:
1256 return ENCODE_ITYPE_IMM (value);
1257
1258 default:
1259 abort ();
1260 }
1261}
1262
e23eba97
NC		 1263/* Output an instruction. IP is the instruction information.
1264 ADDRESS_EXPR is an operand of the instruction to be used with
1265 RELOC_TYPE. */
1266
1267static void
1268append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1269 bfd_reloc_code_real_type reloc_type)
1270{
1271 dwarf2_emit_insn (0);
1272
1273 if (reloc_type != BFD_RELOC_UNUSED)
1274 {
1275 reloc_howto_type *howto;
1276
1d65abb5 1277 gas_assert (address_expr);
e23eba97
NC		 1278 if (reloc_type == BFD_RELOC_12_PCREL
1279 || reloc_type == BFD_RELOC_RISCV_JMP)
1280 {
1281 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1282 int best_case = riscv_insn_length (ip->insn_opcode);
1283 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
743f5cfc
JW		 1284
1285 if (now_seg == absolute_section)
1286 {
1287 as_bad (_("relaxable branches not supported in absolute section"));
1288 return;
1289 }
1290
e23eba97
NC		 1291 add_relaxed_insn (ip, worst_case, best_case,
1292 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1293 address_expr->X_add_symbol,
1294 address_expr->X_add_number);
1295 return;
1296 }
45f76423 1297 else
e23eba97 1298 {
45f76423
AW		 1299 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1300 if (howto == NULL)
b800637e
NC		 1301 as_bad (_("internal: usupported RISC-V relocation number %d"),
1302 reloc_type);
e23eba97 1303
45f76423
AW		 1304 ip->fixp = fix_new_exp (ip->frag, ip->where,
1305 bfd_get_reloc_size (howto),
5b7c81bd 1306 address_expr, false, reloc_type);
e23eba97 1307
45f76423 1308 ip->fixp->fx_tcbit = riscv_opts.relax;
e23eba97 1309 }
e23eba97
NC		 1310 }
1311
e23eba97
NC		 1312 add_fixed_insn (ip);
1313 install_insn (ip);
f77bb6c5
JW		 1314
1315 /* We need to start a new frag after any instruction that can be
1316 optimized away or compressed by the linker during relaxation, to prevent
1317 the assembler from computing static offsets across such an instruction.
1318 This is necessary to get correct EH info. */
b1b11e92 1319 if (reloc_type == BFD_RELOC_RISCV_HI20
f77bb6c5
JW		 1320 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1321 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1322 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1323 {
1324 frag_wane (frag_now);
1325 frag_new (0);
1326 }
e23eba97
NC		 1327}
1328
1329/* Build an instruction created by a macro expansion. This is passed
dcd709e0
NC		 1330 a pointer to the count of instructions created so far, an expression,
1331 the name of the instruction to build, an operand format string, and
1332 corresponding arguments. */
e23eba97
NC		 1333
1334static void
1335macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1336{
1337 const struct riscv_opcode *mo;
1338 struct riscv_cl_insn insn;
1339 bfd_reloc_code_real_type r;
1340 va_list args;
1341
1342 va_start (args, fmt);
1343
1344 r = BFD_RELOC_UNUSED;
629310ab 1345 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
e23eba97
NC		 1346 gas_assert (mo);
1347
1348 /* Find a non-RVC variant of the instruction. append_insn will compress
1349 it if possible. */
1350 while (riscv_insn_length (mo->match) < 4)
1351 mo++;
1352 gas_assert (strcmp (name, mo->name) == 0);
1353
1354 create_insn (&insn, mo);
1355 for (;;)
1356 {
1357 switch (*fmt++)
1358 {
1359 case 'd':
1360 INSERT_OPERAND (RD, insn, va_arg (args, int));
1361 continue;
1362
1363 case 's':
1364 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1365 continue;
1366
1367 case 't':
1368 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1369 continue;
1370
e23eba97
NC		 1371 case 'j':
1372 case 'u':
1373 case 'q':
1374 gas_assert (ep != NULL);
1375 r = va_arg (args, int);
1376 continue;
1377
1378 case '\0':
1379 break;
1380 case ',':
1381 continue;
1382 default:
b800637e 1383 as_fatal (_("internal: invalid macro"));
e23eba97
NC		 1384 }
1385 break;
1386 }
1387 va_end (args);
1388 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1389
1390 append_insn (&insn, ep, r);
1391}
1392
db3b6ecc
KC		 1393/* Build an instruction created by a macro expansion. Like md_assemble but
1394 accept a printf-style format string and arguments. */
1395
1396static void
1397md_assemblef (const char *format, ...)
1398{
1399 char *buf = NULL;
1400 va_list ap;
1401 int r;
1402
1403 va_start (ap, format);
1404
1405 r = vasprintf (&buf, format, ap);
1406
1407 if (r < 0)
b800637e 1408 as_fatal (_("internal: vasprintf failed"));
db3b6ecc
KC		 1409
1410 md_assemble (buf);
1411 free(buf);
1412
1413 va_end (ap);
1414}
1415
e23eba97
NC		 1416/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1417 unset. */
dcd709e0 1418
e23eba97
NC		 1419static void
1420normalize_constant_expr (expressionS *ex)
1421{
1422 if (xlen > 32)
1423 return;
1424 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1425 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1426 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1427 - 0x80000000);
1428}
1429
ca2fd32c
JW		 1430/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1431 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
e23eba97
NC		 1432
1433static void
ca2fd32c 1434check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
5b7c81bd 1435 bool maybe_csr)
e23eba97
NC		 1436{
1437 if (ex->X_op == O_big)
1438 as_bad (_("unsupported large constant"));
ca2fd32c
JW		 1439 else if (maybe_csr && ex->X_op == O_symbol)
1440 as_bad (_("unknown CSR `%s'"),
1441 S_GET_NAME (ex->X_add_symbol));
e23eba97 1442 else if (ex->X_op != O_constant)
b800637e 1443 as_bad (_("instruction %s requires absolute expression"),
e23eba97
NC		 1444 ip->insn_mo->name);
1445 normalize_constant_expr (ex);
1446}
1447
1448static symbolS *
1449make_internal_label (void)
1450{
e01e1cee
AM		 1451 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1452 frag_now_fix ());
e23eba97
NC		 1453}
1454
1455/* Load an entry from the GOT. */
dcd709e0 1456
e23eba97
NC		 1457static void
1458pcrel_access (int destreg, int tempreg, expressionS *ep,
1459 const char *lo_insn, const char *lo_pattern,
1460 bfd_reloc_code_real_type hi_reloc,
1461 bfd_reloc_code_real_type lo_reloc)
1462{
1463 expressionS ep2;
1464 ep2.X_op = O_symbol;
1465 ep2.X_add_symbol = make_internal_label ();
1466 ep2.X_add_number = 0;
1467
1468 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1469 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1470}
1471
1472static void
1473pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1474 bfd_reloc_code_real_type hi_reloc,
1475 bfd_reloc_code_real_type lo_reloc)
1476{
1477 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1478}
1479
1480static void
1481pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1482 bfd_reloc_code_real_type hi_reloc,
1483 bfd_reloc_code_real_type lo_reloc)
1484{
1485 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1486}
1487
1488/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
dcd709e0 1489
e23eba97
NC		 1490static void
1491riscv_call (int destreg, int tempreg, expressionS *ep,
1492 bfd_reloc_code_real_type reloc)
1493{
b1b11e92
AM		 1494 /* Ensure the jalr is emitted to the same frag as the auipc. */
1495 frag_grow (8);
e23eba97
NC		 1496 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1497 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
b1b11e92
AM		 1498 /* See comment at end of append_insn. */
1499 frag_wane (frag_now);
1500 frag_new (0);
e23eba97
NC		 1501}
1502
1503/* Load an integer constant into a register. */
1504
1505static void
1506load_const (int reg, expressionS *ep)
1507{
1508 int shift = RISCV_IMM_BITS;
4f7cc141 1509 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
e23eba97 1510 expressionS upper = *ep, lower = *ep;
4f7cc141 1511 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
e23eba97
NC		 1512 upper.X_add_number -= lower.X_add_number;
1513
1514 if (ep->X_op != O_constant)
1515 {
1516 as_bad (_("unsupported large constant"));
1517 return;
1518 }
1519
1d65abb5 1520 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
e23eba97
NC		 1521 {
1522 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1523 while (((upper.X_add_number >> shift) & 1) == 0)
1524 shift++;
1525
1526 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1d65abb5 1527 load_const (reg, &upper);
e23eba97 1528
db3b6ecc 1529 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
e23eba97 1530 if (lower.X_add_number != 0)
db3b6ecc
KC		 1531 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1532 lower.X_add_number);
e23eba97
NC		 1533 }
1534 else
1535 {
1536 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1537 int hi_reg = 0;
1538
1539 if (upper.X_add_number != 0)
1540 {
db3b6ecc
KC		 1541 /* Discard low part and zero-extend upper immediate. */
1542 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1543
1544 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
e23eba97
NC		 1545 hi_reg = reg;
1546 }
1547
1548 if (lower.X_add_number != 0 || hi_reg == 0)
db3b6ecc
KC		 1549 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1550 lower.X_add_number);
e23eba97
NC		 1551 }
1552}
1553
c2137f55
NC		 1554/* Zero extend and sign extend byte/half-word/word. */
1555
1556static void
5b7c81bd 1557riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
c2137f55
NC		 1558{
1559 if (sign)
1560 {
1561 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1562 md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
1563 }
1564 else
1565 {
1566 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1567 md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
1568 }
1569}
1570
e23eba97 1571/* Expand RISC-V assembly macros into one or more instructions. */
2652cfad 1572
e23eba97
NC		 1573static void
1574macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1575 bfd_reloc_code_real_type *imm_reloc)
1576{
1577 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1578 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1579 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1580 int mask = ip->insn_mo->mask;
1581
1582 switch (mask)
1583 {
1584 case M_LI:
1585 load_const (rd, imm_expr);
1586 break;
1587
1588 case M_LA:
1589 case M_LLA:
1590 /* Load the address of a symbol into a register. */
1591 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1592 as_bad (_("offset too large"));
1593
1594 if (imm_expr->X_op == O_constant)
1595 load_const (rd, imm_expr);
dcd709e0 1596 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol. */
e23eba97
NC		 1597 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1598 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
dcd709e0 1599 else /* Local PIC symbol, or any non-PIC symbol. */
e23eba97
NC		 1600 pcrel_load (rd, rd, imm_expr, "addi",
1601 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1602 break;
1603
1604 case M_LA_TLS_GD:
1605 pcrel_load (rd, rd, imm_expr, "addi",
1606 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1607 break;
1608
1609 case M_LA_TLS_IE:
1610 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1611 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1612 break;
1613
1614 case M_LB:
1615 pcrel_load (rd, rd, imm_expr, "lb",
1616 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1617 break;
1618
1619 case M_LBU:
1620 pcrel_load (rd, rd, imm_expr, "lbu",
1621 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1622 break;
1623
1624 case M_LH:
1625 pcrel_load (rd, rd, imm_expr, "lh",
1626 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1627 break;
1628
1629 case M_LHU:
1630 pcrel_load (rd, rd, imm_expr, "lhu",
1631 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1632 break;
1633
1634 case M_LW:
1635 pcrel_load (rd, rd, imm_expr, "lw",
1636 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1637 break;
1638
1639 case M_LWU:
1640 pcrel_load (rd, rd, imm_expr, "lwu",
1641 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1642 break;
1643
1644 case M_LD:
1645 pcrel_load (rd, rd, imm_expr, "ld",
1646 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1647 break;
1648
1649 case M_FLW:
1650 pcrel_load (rd, rs1, imm_expr, "flw",
1651 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1652 break;
1653
1654 case M_FLD:
1655 pcrel_load (rd, rs1, imm_expr, "fld",
1656 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1657 break;
1658
1659 case M_SB:
1660 pcrel_store (rs2, rs1, imm_expr, "sb",
1661 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1662 break;
1663
1664 case M_SH:
1665 pcrel_store (rs2, rs1, imm_expr, "sh",
1666 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1667 break;
1668
1669 case M_SW:
1670 pcrel_store (rs2, rs1, imm_expr, "sw",
1671 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1672 break;
1673
1674 case M_SD:
1675 pcrel_store (rs2, rs1, imm_expr, "sd",
1676 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1677 break;
1678
1679 case M_FSW:
1680 pcrel_store (rs2, rs1, imm_expr, "fsw",
1681 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1682 break;
1683
1684 case M_FSD:
1685 pcrel_store (rs2, rs1, imm_expr, "fsd",
1686 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1687 break;
1688
1689 case M_CALL:
1690 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1691 break;
1692
c2137f55 1693 case M_ZEXTH:
5b7c81bd 1694 riscv_ext (rd, rs1, xlen - 16, false);
c2137f55
NC		 1695 break;
1696
1697 case M_ZEXTW:
5b7c81bd 1698 riscv_ext (rd, rs1, xlen - 32, false);
c2137f55
NC		 1699 break;
1700
1701 case M_SEXTB:
5b7c81bd 1702 riscv_ext (rd, rs1, xlen - 8, true);
c2137f55
NC		 1703 break;
1704
1705 case M_SEXTH:
5b7c81bd 1706 riscv_ext (rd, rs1, xlen - 16, true);
c2137f55
NC		 1707 break;
1708
e23eba97 1709 default:
b800637e 1710 as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
e23eba97
NC		 1711 break;
1712 }
1713}
1714
1715static const struct percent_op_match percent_op_utype[] =
1716{
1717 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1718 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
dee35d02 1719 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
e23eba97
NC		 1720 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1721 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1722 {"%hi", BFD_RELOC_RISCV_HI20},
1723 {0, 0}
1724};
1725
1726static const struct percent_op_match percent_op_itype[] =
1727{
1728 {"%lo", BFD_RELOC_RISCV_LO12_I},
1729 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1730 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1731 {0, 0}
1732};
1733
1734static const struct percent_op_match percent_op_stype[] =
1735{
1736 {"%lo", BFD_RELOC_RISCV_LO12_S},
1737 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1738 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1739 {0, 0}
1740};
1741
1742static const struct percent_op_match percent_op_rtype[] =
1743{
1744 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1745 {0, 0}
1746};
1747
f50fabe4
JW		 1748static const struct percent_op_match percent_op_null[] =
1749{
1750 {0, 0}
1751};
1752
e23eba97
NC		 1753/* Return true if *STR points to a relocation operator. When returning true,
1754 move *STR over the operator and store its relocation code in *RELOC.
1755 Leave both *STR and *RELOC alone when returning false. */
1756
5b7c81bd 1757static bool
e23eba97
NC		 1758parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1759 const struct percent_op_match *percent_op)
1760{
1761 for ( ; percent_op->str; percent_op++)
1762 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1763 {
1764 int len = strlen (percent_op->str);
1765
1766 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1767 continue;
1768
1769 *str += strlen (percent_op->str);
1770 *reloc = percent_op->reloc;
1771
1772 /* Check whether the output BFD supports this relocation.
1773 If not, issue an error and fall back on something safe. */
45f76423
AW		 1774 if (*reloc != BFD_RELOC_UNUSED
1775 && !bfd_reloc_type_lookup (stdoutput, *reloc))
e23eba97 1776 {
b800637e
NC		 1777 as_bad ("internal: relocation %s isn't supported by the "
1778 "current ABI", percent_op->str);
e23eba97
NC		 1779 *reloc = BFD_RELOC_UNUSED;
1780 }
5b7c81bd 1781 return true;
e23eba97 1782 }
5b7c81bd 1783 return false;
e23eba97
NC		 1784}
1785
1786static void
1787my_getExpression (expressionS *ep, char *str)
1788{
1789 char *save_in;
1790
1791 save_in = input_line_pointer;
1792 input_line_pointer = str;
1793 expression (ep);
1794 expr_end = input_line_pointer;
1795 input_line_pointer = save_in;
1796}
1797
1798/* Parse string STR as a 16-bit relocatable operand. Store the
1799 expression in *EP and the relocation, if any, in RELOC.
1800 Return the number of relocation operators used (0 or 1).
1801
1802 On exit, EXPR_END points to the first character after the expression. */
1803
1804static size_t
1805my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1806 char *str, const struct percent_op_match *percent_op)
1807{
1808 size_t reloc_index;
1809 unsigned crux_depth, str_depth, regno;
1810 char *crux;
1811
8970c022
JW		 1812 /* First, check for integer registers. No callers can accept a reg, but
1813 we need to avoid accidentally creating a useless undefined symbol below,
1814 if this is an instruction pattern that can't match. A glibc build fails
1815 if this is removed. */
e23eba97
NC		 1816 if (reg_lookup (&str, RCLASS_GPR, &regno))
1817 {
1818 ep->X_op = O_register;
1819 ep->X_add_number = regno;
8970c022 1820 expr_end = str;
e23eba97
NC		 1821 return 0;
1822 }
1823
1824 /* Search for the start of the main expression.
dcd709e0
NC		 1825
1826 End the loop with CRUX pointing to the start of the main expression and
1827 with CRUX_DEPTH containing the number of open brackets at that point. */
e23eba97
NC		 1828 reloc_index = -1;
1829 str_depth = 0;
1830 do
1831 {
1832 reloc_index++;
1833 crux = str;
1834 crux_depth = str_depth;
1835
1836 /* Skip over whitespace and brackets, keeping count of the number
1837 of brackets. */
1838 while (*str == ' ' || *str == '\t' || *str == '(')
1839 if (*str++ == '(')
1840 str_depth++;
1841 }
1842 while (*str == '%'
1843 && reloc_index < 1
1844 && parse_relocation (&str, reloc, percent_op));
1845
1846 my_getExpression (ep, crux);
1847 str = expr_end;
1848
1849 /* Match every open bracket. */
1850 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1851 if (*str++ == ')')
1852 crux_depth--;
1853
1854 if (crux_depth > 0)
1855 as_bad ("unclosed '('");
1856
1857 expr_end = str;
1858
1859 return reloc_index;
1860}
1861
0e35537d 1862/* Parse opcode name, could be an mnemonics or number. */
dcd709e0 1863
0e35537d
JW		 1864static size_t
1865my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1866 char *str, const struct percent_op_match *percent_op)
1867{
1868 const struct opcode_name_t *o = opcode_name_lookup (&str);
1869
1870 if (o != NULL)
1871 {
1872 ep->X_op = O_constant;
1873 ep->X_add_number = o->val;
1874 return 0;
1875 }
1876
1877 return my_getSmallExpression (ep, reloc, str, percent_op);
1878}
1879
f0531ed6
JW		 1880/* Detect and handle implicitly zero load-store offsets. For example,
1881 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1882 an implicit offset was detected. */
1883
5b7c81bd 1884static bool
89424b1d 1885riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
f0531ed6
JW		 1886{
1887 /* Check whether there is only a single bracketed expression left.
1888 If so, it must be the base register and the constant must be zero. */
1889 if (*s == '(' && strchr (s + 1, '(') == 0)
1890 {
89424b1d
MR		 1891 ep->X_op = O_constant;
1892 ep->X_add_number = 0;
5b7c81bd 1893 return true;
f0531ed6
JW		 1894 }
1895
5b7c81bd 1896 return false;
f0531ed6
JW		 1897}
1898
54b2aec1 1899/* All RISC-V CSR instructions belong to one of these classes. */
54b2aec1
NC		 1900enum csr_insn_type
1901{
1902 INSN_NOT_CSR,
1903 INSN_CSRRW,
1904 INSN_CSRRS,
1905 INSN_CSRRC
1906};
1907
1908/* Return which CSR instruction is checking. */
1909
1910static enum csr_insn_type
1911riscv_csr_insn_type (insn_t insn)
1912{
1913 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1914 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1915 return INSN_CSRRW;
1916 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1917 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1918 return INSN_CSRRS;
1919 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1920 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1921 return INSN_CSRRC;
1922 else
1923 return INSN_NOT_CSR;
1924}
1925
1926/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1927 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1928 CSR address is 0x3. */
1929
5b7c81bd 1930static bool
54b2aec1
NC		 1931riscv_csr_read_only_check (insn_t insn)
1932{
1933 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1934 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1935 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1936 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1937
1938 if (readonly
1939 && (((csr_insn == INSN_CSRRS
1940 || csr_insn == INSN_CSRRC)
1941 && rs1 != 0)
1942 || csr_insn == INSN_CSRRW))
5b7c81bd 1943 return false;
54b2aec1 1944
5b7c81bd 1945 return true;
54b2aec1
NC		 1946}
1947
1a79004f
NC		 1948/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1949
1950 uret is actually a N-ext instruction. So it is better to regard it as
1951 an user instruction rather than the priv instruction.
1952
1953 hret is used to return from traps in H-mode. H-mode is removed since
1954 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1955 Therefore, hret should be controlled by the hypervisor spec rather than
1956 priv spec in the future.
1957
1958 dret is defined in the debug spec, so it should be checked in the future,
1959 too. */
1960
5b7c81bd 1961static bool
1a79004f
NC		 1962riscv_is_priv_insn (insn_t insn)
1963{
1964 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1965 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1966 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1967 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1968 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
dcd709e0 1969 check it here to keep the compatible. */
1a79004f
NC		 1970 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1971}
1972
e23eba97
NC		 1973/* This routine assembles an instruction into its binary format. As a
1974 side effect, it sets the global variable imm_reloc to the type of
1975 relocation to do if one of the operands is an address expression. */
1976
1977static const char *
1978riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
629310ab 1979 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
e23eba97
NC		 1980{
1981 char *s;
1982 const char *args;
1983 char c = 0;
1984 struct riscv_opcode *insn;
1985 char *argsStart;
1986 unsigned int regno;
1987 char save_c = 0;
1988 int argnum;
1989 const struct percent_op_match *p;
1990 const char *error = "unrecognized opcode";
54b2aec1 1991 /* Indicate we are assembling instruction with CSR. */
5b7c81bd 1992 bool insn_with_csr = false;
e23eba97
NC		 1993
1994 /* Parse the name of the instruction. Terminate the string if whitespace
629310ab 1995 is found so that str_hash_find only sees the name part of the string. */
e23eba97
NC		 1996 for (s = str; *s != '\0'; ++s)
1997 if (ISSPACE (*s))
1998 {
1999 save_c = *s;
2000 *s++ = '\0';
2001 break;
2002 }
2003
629310ab 2004 insn = (struct riscv_opcode *) str_hash_find (hash, str);
e23eba97
NC		 2005
2006 argsStart = s;
2007 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
2008 {
1080bf78
JW		 2009 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
2010 continue;
2011
7e9ad3a3 2012 if (!riscv_multi_subset_supports (insn->insn_class))
e23eba97
NC		 2013 continue;
2014
2015 create_insn (ip, insn);
2016 argnum = 1;
2017
2018 imm_expr->X_op = O_absent;
2019 *imm_reloc = BFD_RELOC_UNUSED;
2020 p = percent_op_itype;
2021
2022 for (args = insn->args;; ++args)
2023 {
2024 s += strspn (s, " \t");
2025 switch (*args)
2026 {
dcd709e0 2027 case '\0': /* End of args. */
e23eba97
NC		 2028 if (insn->pinfo != INSN_MACRO)
2029 {
2030 if (!insn->match_func (insn, ip->insn_opcode))
2031 break;
0e35537d
JW		 2032
2033 /* For .insn, insn->match and insn->mask are 0. */
2034 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
2035 ? ip->insn_opcode
2036 : insn->match) == 2
2037 && !riscv_opts.rvc)
e23eba97 2038 break;
54b2aec1 2039
1a79004f 2040 if (riscv_is_priv_insn (ip->insn_opcode))
5b7c81bd 2041 explicit_priv_attr = true;
1a79004f 2042
54b2aec1
NC		 2043 /* Check if we write a read-only CSR by the CSR
2044 instruction. */
2045 if (insn_with_csr
2046 && riscv_opts.csr_check
2047 && !riscv_csr_read_only_check (ip->insn_opcode))
2048 {
2049 /* Restore the character in advance, since we want to
2050 report the detailed warning message here. */
2051 if (save_c)
2052 *(argsStart - 1) = save_c;
b800637e 2053 as_warn (_("read-only CSR is written `%s'"), str);
5b7c81bd 2054 insn_with_csr = false;
54b2aec1 2055 }
e23eba97
NC		 2056 }
2057 if (*s != '\0')
2058 break;
2059 /* Successful assembly. */
2060 error = NULL;
5b7c81bd 2061 insn_with_csr = false;
e23eba97
NC		 2062 goto out;
2063
2064 case 'C': /* RVC */
2065 switch (*++args)
2066 {
dcd709e0 2067 case 's': /* RS1 x8-x15. */
e23eba97
NC		 2068 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2069 || !(regno >= 8 && regno <= 15))
2070 break;
2071 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2072 continue;
2073 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2074 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2075 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
2076 break;
2077 continue;
dcd709e0 2078 case 't': /* RS2 x8-x15. */
e23eba97
NC		 2079 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2080 || !(regno >= 8 && regno <= 15))
2081 break;
2082 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2083 continue;
2084 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2085 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2086 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
2087 break;
2088 continue;
2089 case 'U': /* RS1, constrained to equal RD. */
2090 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2091 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
2092 break;
2093 continue;
2094 case 'V': /* RS2 */
2095 if (!reg_lookup (&s, RCLASS_GPR, &regno))
2096 break;
2097 INSERT_OPERAND (CRS2, *ip, regno);
2098 continue;
2099 case 'c': /* RS1, constrained to equal sp. */
2100 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2101 || regno != X_SP)
2102 break;
2103 continue;
dcd709e0 2104 case 'z': /* RS2, constrained to equal x0. */
ca0bc150
JW		 2105 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2106 || regno != 0)
2107 break;
2108 continue;
768589d1 2109 case '>': /* Shift amount, 0 - (XLEN-1). */
e23eba97
NC		 2110 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2111 || imm_expr->X_op != O_constant
768589d1 2112 || (unsigned long) imm_expr->X_add_number >= xlen)
e23eba97 2113 break;
5a9f5403 2114 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
dc1e8a47 2115 rvc_imm_done:
e23eba97
NC		 2116 s = expr_end;
2117 imm_expr->X_op = O_absent;
2118 continue;
5a9f5403 2119 case '5':
e23eba97
NC		 2120 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2121 || imm_expr->X_op != O_constant
5a9f5403 2122 || imm_expr->X_add_number < 0
169ec512 2123 || imm_expr->X_add_number >= 32
5a9f5403 2124 || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2125 break;
0257c2ff 2126 ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number);
e23eba97 2127 goto rvc_imm_done;
5a9f5403 2128 case '6':
0e35537d
JW		 2129 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2130 || imm_expr->X_op != O_constant
0e35537d 2131 || imm_expr->X_add_number < 0
5a9f5403
NC		 2132 || imm_expr->X_add_number >= 64
2133 || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number))
0e35537d 2134 break;
0257c2ff 2135 ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number);
0e35537d 2136 goto rvc_imm_done;
5a9f5403 2137 case '8':
e23eba97
NC		 2138 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2139 || imm_expr->X_op != O_constant
5a9f5403
NC		 2140 || imm_expr->X_add_number < 0
2141 || imm_expr->X_add_number >= 256
2142 || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2143 break;
0257c2ff 2144 ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2145 goto rvc_imm_done;
2146 case 'j':
2147 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2148 || imm_expr->X_op != O_constant
2149 || imm_expr->X_add_number == 0
5a9f5403 2150 || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2151 break;
5a9f5403 2152 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2153 goto rvc_imm_done;
2154 case 'k':
f0531ed6
JW		 2155 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2156 continue;
e23eba97
NC		 2157 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2158 || imm_expr->X_op != O_constant
5a9f5403 2159 || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2160 break;
5a9f5403 2161 ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number);
e23eba97
NC		 2162 goto rvc_imm_done;
2163 case 'l':
f0531ed6
JW		 2164 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2165 continue;
e23eba97
NC		 2166 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2167 || imm_expr->X_op != O_constant
5a9f5403 2168 || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number))
e23eba97 2169 break;
5a9f5403 2170 ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number);
e23eba97
NC		 2171 goto rvc_imm_done;
2172 case 'm':
f0531ed6
JW		 2173 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2174 continue;
e23eba97
NC		 2175 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2176 || imm_expr->X_op != O_constant
5a9f5403 2177 || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2178 break;
2179 ip->insn_opcode |=
5a9f5403 2180 ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2181 goto rvc_imm_done;
2182 case 'n':
f0531ed6
JW		 2183 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2184 continue;
e23eba97
NC		 2185 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2186 || imm_expr->X_op != O_constant
5a9f5403 2187 || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2188 break;
2189 ip->insn_opcode |=
5a9f5403 2190 ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number);
e23eba97 2191 goto rvc_imm_done;
b416fe87
KC		 2192 case 'o':
2193 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2194 || imm_expr->X_op != O_constant
21a186f2
JW		 2195 /* C.addiw, c.li, and c.andi allow zero immediate.
2196 C.addi allows zero immediate as hint. Otherwise this
2197 is same as 'j'. */
5a9f5403 2198 || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
b416fe87 2199 break;
5a9f5403 2200 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
b416fe87 2201 goto rvc_imm_done;
e23eba97
NC		 2202 case 'K':
2203 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2204 || imm_expr->X_op != O_constant
169ec512 2205 || imm_expr->X_add_number == 0
5a9f5403 2206 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2207 break;
2208 ip->insn_opcode |=
5a9f5403 2209 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number);
e23eba97
NC		 2210 goto rvc_imm_done;
2211 case 'L':
2212 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2213 || imm_expr->X_op != O_constant
5a9f5403 2214 || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2215 break;
2216 ip->insn_opcode |=
5a9f5403 2217 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2218 goto rvc_imm_done;
2219 case 'M':
f0531ed6
JW		 2220 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2221 continue;
e23eba97
NC		 2222 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2223 || imm_expr->X_op != O_constant
5a9f5403 2224 || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2225 break;
2226 ip->insn_opcode |=
5a9f5403 2227 ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2228 goto rvc_imm_done;
2229 case 'N':
f0531ed6
JW		 2230 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2231 continue;
e23eba97
NC		 2232 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2233 || imm_expr->X_op != O_constant
5a9f5403 2234 || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number))
e23eba97
NC		 2235 break;
2236 ip->insn_opcode |=
5a9f5403 2237 ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number);
e23eba97
NC		 2238 goto rvc_imm_done;
2239 case 'u':
2240 p = percent_op_utype;
2241 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2242 break;
dc1e8a47 2243 rvc_lui:
e23eba97
NC		 2244 if (imm_expr->X_op != O_constant
2245 || imm_expr->X_add_number <= 0
2246 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2247 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2248 && (imm_expr->X_add_number <
2249 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2250 break;
5a9f5403 2251 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
e23eba97
NC		 2252 goto rvc_imm_done;
2253 case 'v':
2254 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2255 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2256 || ((int32_t)imm_expr->X_add_number
2257 != imm_expr->X_add_number))
2258 break;
2259 imm_expr->X_add_number =
2260 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2261 goto rvc_lui;
2262 case 'p':
2263 goto branch;
2264 case 'a':
2265 goto jump;
0e35537d
JW		 2266 case 'S': /* Floating-point RS1 x8-x15. */
2267 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2268 || !(regno >= 8 && regno <= 15))
2269 break;
2270 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2271 continue;
e23eba97
NC		 2272 case 'D': /* Floating-point RS2 x8-x15. */
2273 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2274 || !(regno >= 8 && regno <= 15))
2275 break;
2276 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2277 continue;
2278 case 'T': /* Floating-point RS2. */
2279 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2280 break;
2281 INSERT_OPERAND (CRS2, *ip, regno);
2282 continue;
0e35537d
JW		 2283 case 'F':
2284 switch (*++args)
2285 {
4765cd61
JW		 2286 case '6':
2287 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2288 || imm_expr->X_op != O_constant
2289 || imm_expr->X_add_number < 0
2290 || imm_expr->X_add_number >= 64)
2291 {
b800637e
NC		 2292 as_bad (_("bad value for compressed funct6 "
2293 "field, value must be 0...64"));
4765cd61
JW		 2294 break;
2295 }
4765cd61
JW		 2296 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2297 imm_expr->X_op = O_absent;
2298 s = expr_end;
2299 continue;
1942a048 2300
0e35537d
JW		 2301 case '4':
2302 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2303 || imm_expr->X_op != O_constant
2304 || imm_expr->X_add_number < 0
2305 || imm_expr->X_add_number >= 16)
2306 {
b800637e
NC		 2307 as_bad (_("bad value for compressed funct4 "
2308 "field, value must be 0...15"));
0e35537d
JW		 2309 break;
2310 }
0e35537d
JW		 2311 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2312 imm_expr->X_op = O_absent;
2313 s = expr_end;
2314 continue;
1942a048 2315
0e35537d
JW		 2316 case '3':
2317 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2318 || imm_expr->X_op != O_constant
2319 || imm_expr->X_add_number < 0
2320 || imm_expr->X_add_number >= 8)
2321 {
b800637e
NC		 2322 as_bad (_("bad value for compressed funct3 "
2323 "field, value must be 0...7"));
0e35537d
JW		 2324 break;
2325 }
2326 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2327 imm_expr->X_op = O_absent;
2328 s = expr_end;
2329 continue;
1942a048 2330
4765cd61
JW		 2331 case '2':
2332 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2333 || imm_expr->X_op != O_constant
2334 || imm_expr->X_add_number < 0
2335 || imm_expr->X_add_number >= 4)
2336 {
b800637e
NC		 2337 as_bad (_("bad value for compressed funct2 "
2338 "field, value must be 0...3"));
4765cd61
JW		 2339 break;
2340 }
2341 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2342 imm_expr->X_op = O_absent;
2343 s = expr_end;
2344 continue;
1942a048 2345
0e35537d 2346 default:
b800637e
NC		 2347 as_bad (_("internal: unknown compressed funct "
2348 "field specifier `CF%c'"), *args);
0e35537d
JW		 2349 }
2350 break;
2351
e23eba97 2352 default:
b800637e
NC		 2353 as_bad (_("internal: unknown compressed field "
2354 "specifier `C%c'"), *args);
e23eba97
NC		 2355 }
2356 break;
2357
2358 case ',':
2359 ++argnum;
2360 if (*s++ == *args)
2361 continue;
2362 s--;
2363 break;
2364
2365 case '(':
2366 case ')':
2367 case '[':
2368 case ']':
2369 if (*s++ == *args)
2370 continue;
2371 break;
2372
dcd709e0 2373 case '<': /* Shift amount, 0 - 31. */
e23eba97 2374 my_getExpression (imm_expr, s);
5b7c81bd 2375 check_absolute_expr (ip, imm_expr, false);
e23eba97 2376 if ((unsigned long) imm_expr->X_add_number > 31)
b800637e 2377 as_bad (_("improper shift amount (%lu)"),
94f78a77 2378 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2379 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2380 imm_expr->X_op = O_absent;
2381 s = expr_end;
2382 continue;
2383
dcd709e0 2384 case '>': /* Shift amount, 0 - (XLEN-1). */
e23eba97 2385 my_getExpression (imm_expr, s);
5b7c81bd 2386 check_absolute_expr (ip, imm_expr, false);
e23eba97 2387 if ((unsigned long) imm_expr->X_add_number >= xlen)
b800637e 2388 as_bad (_("improper shift amount (%lu)"),
94f78a77 2389 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2390 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2391 imm_expr->X_op = O_absent;
2392 s = expr_end;
2393 continue;
2394
dcd709e0 2395 case 'Z': /* CSRRxI immediate. */
e23eba97 2396 my_getExpression (imm_expr, s);
5b7c81bd 2397 check_absolute_expr (ip, imm_expr, false);
e23eba97 2398 if ((unsigned long) imm_expr->X_add_number > 31)
b800637e 2399 as_bad (_("improper CSRxI immediate (%lu)"),
94f78a77 2400 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2401 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2402 imm_expr->X_op = O_absent;
2403 s = expr_end;
2404 continue;
2405
dcd709e0 2406 case 'E': /* Control register. */
5b7c81bd
AM		 2407 insn_with_csr = true;
2408 explicit_priv_attr = true;
e23eba97
NC		 2409 if (reg_lookup (&s, RCLASS_CSR, &regno))
2410 INSERT_OPERAND (CSR, *ip, regno);
2411 else
2412 {
2413 my_getExpression (imm_expr, s);
5b7c81bd 2414 check_absolute_expr (ip, imm_expr, true);
e23eba97 2415 if ((unsigned long) imm_expr->X_add_number > 0xfff)
b800637e 2416 as_bad (_("improper CSR address (%lu)"),
94f78a77 2417 (unsigned long) imm_expr->X_add_number);
e23eba97
NC		 2418 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2419 imm_expr->X_op = O_absent;
2420 s = expr_end;
2421 }
2422 continue;
2423
dcd709e0 2424 case 'm': /* Rounding mode. */
e23eba97
NC		 2425 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2426 {
2427 INSERT_OPERAND (RM, *ip, regno);
2428 continue;
2429 }
2430 break;
2431
2432 case 'P':
dcd709e0 2433 case 'Q': /* Fence predecessor/successor. */
e23eba97
NC		 2434 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2435 &regno))
2436 {
2437 if (*args == 'P')
2438 INSERT_OPERAND (PRED, *ip, regno);
2439 else
2440 INSERT_OPERAND (SUCC, *ip, regno);
2441 continue;
2442 }
2443 break;
2444
dcd709e0
NC		 2445 case 'd': /* Destination register. */
2446 case 's': /* Source register. */
2447 case 't': /* Target register. */
2448 case 'r': /* RS3 */
e23eba97
NC		 2449 if (reg_lookup (&s, RCLASS_GPR, &regno))
2450 {
2451 c = *args;
2452 if (*s == ' ')
2453 ++s;
2454
2455 /* Now that we have assembled one operand, we use the args
2456 string to figure out where it goes in the instruction. */
2457 switch (c)
2458 {
2459 case 's':
2460 INSERT_OPERAND (RS1, *ip, regno);
2461 break;
2462 case 'd':
2463 INSERT_OPERAND (RD, *ip, regno);
2464 break;
2465 case 't':
2466 INSERT_OPERAND (RS2, *ip, regno);
2467 break;
0e35537d
JW		 2468 case 'r':
2469 INSERT_OPERAND (RS3, *ip, regno);
2470 break;
e23eba97
NC		 2471 }
2472 continue;
2473 }
2474 break;
2475
dcd709e0
NC		 2476 case 'D': /* Floating point RD. */
2477 case 'S': /* Floating point RS1. */
2478 case 'T': /* Floating point RS2. */
2479 case 'U': /* Floating point RS1 and RS2. */
2480 case 'R': /* Floating point RS3. */
e23eba97
NC		 2481 if (reg_lookup (&s, RCLASS_FPR, &regno))
2482 {
2483 c = *args;
2484 if (*s == ' ')
2485 ++s;
2486 switch (c)
2487 {
2488 case 'D':
2489 INSERT_OPERAND (RD, *ip, regno);
2490 break;
2491 case 'S':
2492 INSERT_OPERAND (RS1, *ip, regno);
2493 break;
2494 case 'U':
2495 INSERT_OPERAND (RS1, *ip, regno);
dcd709e0 2496 /* Fall through. */
e23eba97
NC		 2497 case 'T':
2498 INSERT_OPERAND (RS2, *ip, regno);
2499 break;
2500 case 'R':
2501 INSERT_OPERAND (RS3, *ip, regno);
2502 break;
2503 }
2504 continue;
2505 }
e23eba97
NC		 2506 break;
2507
2508 case 'I':
2509 my_getExpression (imm_expr, s);
2510 if (imm_expr->X_op != O_big
2511 && imm_expr->X_op != O_constant)
2512 break;
2513 normalize_constant_expr (imm_expr);
2514 s = expr_end;
2515 continue;
2516
2517 case 'A':
2518 my_getExpression (imm_expr, s);
2519 normalize_constant_expr (imm_expr);
2520 /* The 'A' format specifier must be a symbol. */
2521 if (imm_expr->X_op != O_symbol)
2522 break;
2523 *imm_reloc = BFD_RELOC_32;
2524 s = expr_end;
2525 continue;
2526
160d1b3d
SH		 2527 case 'B':
2528 my_getExpression (imm_expr, s);
2529 normalize_constant_expr (imm_expr);
2530 /* The 'B' format specifier must be a symbol or a constant. */
2531 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2532 break;
2533 if (imm_expr->X_op == O_symbol)
2534 *imm_reloc = BFD_RELOC_32;
2535 s = expr_end;
2536 continue;
2537
e23eba97 2538 case 'j': /* Sign-extended immediate. */
e23eba97 2539 p = percent_op_itype;
f50fabe4 2540 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
e23eba97
NC		 2541 goto alu_op;
2542 case 'q': /* Store displacement. */
2543 p = percent_op_stype;
2544 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2545 goto load_store;
2546 case 'o': /* Load displacement. */
2547 p = percent_op_itype;
2548 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2549 goto load_store;
dcd709e0
NC		 2550 case '1':
2551 /* This is used for TLS, where the fourth operand is
2552 %tprel_add, to get a relocation applied to an add
2553 instruction, for relaxation to use. */
e23eba97 2554 p = percent_op_rtype;
f50fabe4 2555 goto alu_op;
dcd709e0 2556 case '0': /* AMO displacement, which must be zero. */
f50fabe4 2557 p = percent_op_null;
dc1e8a47 2558 load_store:
f0531ed6 2559 if (riscv_handle_implicit_zero_offset (imm_expr, s))
e23eba97 2560 continue;
dc1e8a47 2561 alu_op:
e23eba97
NC		 2562 /* If this value won't fit into a 16 bit offset, then go
2563 find a macro that will generate the 32 bit offset
2564 code pattern. */
2565 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2566 {
2567 normalize_constant_expr (imm_expr);
2568 if (imm_expr->X_op != O_constant
2569 || (*args == '0' && imm_expr->X_add_number != 0)
f50fabe4 2570 || (*args == '1')
e23eba97
NC		 2571 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2572 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2573 break;
2574 }
e23eba97
NC		 2575 s = expr_end;
2576 continue;
2577
dcd709e0 2578 case 'p': /* PC-relative offset. */
dc1e8a47 2579 branch:
e23eba97
NC		 2580 *imm_reloc = BFD_RELOC_12_PCREL;
2581 my_getExpression (imm_expr, s);
2582 s = expr_end;
2583 continue;
2584
dcd709e0 2585 case 'u': /* Upper 20 bits. */
e23eba97 2586 p = percent_op_utype;
4288405d 2587 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
e23eba97 2588 {
4288405d
JW		 2589 if (imm_expr->X_op != O_constant)
2590 break;
2591
e23eba97
NC		 2592 if (imm_expr->X_add_number < 0
2593 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2594 as_bad (_("lui expression not in range 0..1048575"));
2595
2596 *imm_reloc = BFD_RELOC_RISCV_HI20;
2597 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2598 }
2599 s = expr_end;
2600 continue;
2601
dcd709e0 2602 case 'a': /* 20-bit PC-relative offset. */
dc1e8a47 2603 jump:
e23eba97
NC		 2604 my_getExpression (imm_expr, s);
2605 s = expr_end;
2606 *imm_reloc = BFD_RELOC_RISCV_JMP;
2607 continue;
2608
2609 case 'c':
2610 my_getExpression (imm_expr, s);
2611 s = expr_end;
2612 if (strcmp (s, "@plt") == 0)
2613 {
2614 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2615 s += 4;
2616 }
2617 else
2618 *imm_reloc = BFD_RELOC_RISCV_CALL;
2619 continue;
1942a048 2620
0e35537d
JW		 2621 case 'O':
2622 switch (*++args)
2623 {
2624 case '4':
2625 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2626 || imm_expr->X_op != O_constant
2627 || imm_expr->X_add_number < 0
2628 || imm_expr->X_add_number >= 128
2629 || (imm_expr->X_add_number & 0x3) != 3)
2630 {
2631 as_bad (_("bad value for opcode field, "
2632 "value must be 0...127 and "
2633 "lower 2 bits must be 0x3"));
2634 break;
2635 }
0e35537d
JW		 2636 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2637 imm_expr->X_op = O_absent;
2638 s = expr_end;
2639 continue;
1942a048 2640
0e35537d
JW		 2641 case '2':
2642 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2643 || imm_expr->X_op != O_constant
2644 || imm_expr->X_add_number < 0
2645 || imm_expr->X_add_number >= 3)
2646 {
2647 as_bad (_("bad value for opcode field, "
2648 "value must be 0...2"));
2649 break;
2650 }
0e35537d
JW		 2651 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2652 imm_expr->X_op = O_absent;
2653 s = expr_end;
2654 continue;
1942a048 2655
0e35537d 2656 default:
b800637e
NC		 2657 as_bad (_("internal: unknown opcode field "
2658 "specifier `O%c'"), *args);
0e35537d
JW		 2659 }
2660 break;
2661
2662 case 'F':
2663 switch (*++args)
2664 {
2665 case '7':
2666 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2667 || imm_expr->X_op != O_constant
2668 || imm_expr->X_add_number < 0
2669 || imm_expr->X_add_number >= 128)
2670 {
2671 as_bad (_("bad value for funct7 field, "
2672 "value must be 0...127"));
2673 break;
2674 }
0e35537d
JW		 2675 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2676 imm_expr->X_op = O_absent;
2677 s = expr_end;
2678 continue;
1942a048 2679
0e35537d
JW		 2680 case '3':
2681 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2682 || imm_expr->X_op != O_constant
2683 || imm_expr->X_add_number < 0
2684 || imm_expr->X_add_number >= 8)
2685 {
2686 as_bad (_("bad value for funct3 field, "
2687 "value must be 0...7"));
2688 break;
2689 }
0e35537d
JW		 2690 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2691 imm_expr->X_op = O_absent;
2692 s = expr_end;
2693 continue;
1942a048 2694
0e35537d
JW		 2695 case '2':
2696 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2697 || imm_expr->X_op != O_constant
2698 || imm_expr->X_add_number < 0
2699 || imm_expr->X_add_number >= 4)
2700 {
2701 as_bad (_("bad value for funct2 field, "
2702 "value must be 0...3"));
2703 break;
2704 }
0e35537d
JW		 2705 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2706 imm_expr->X_op = O_absent;
2707 s = expr_end;
2708 continue;
2709
2710 default:
b800637e
NC		 2711 as_bad (_("internal: unknown funct field "
2712 "specifier `F%c'\n"), *args);
0e35537d
JW		 2713 }
2714 break;
e23eba97 2715
e925c834
JW		 2716 case 'z':
2717 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2718 || imm_expr->X_op != O_constant
2719 || imm_expr->X_add_number != 0)
2720 break;
2721 s = expr_end;
2722 imm_expr->X_op = O_absent;
2723 continue;
2724
e23eba97 2725 default:
b800637e 2726 as_fatal (_("internal: unknown argument type `%c'"), *args);
e23eba97
NC		 2727 }
2728 break;
2729 }
2730 s = argsStart;
2731 error = _("illegal operands");
5b7c81bd 2732 insn_with_csr = false;
e23eba97
NC		 2733 }
2734
dc1e8a47 2735 out:
e23eba97
NC		 2736 /* Restore the character we might have clobbered above. */
2737 if (save_c)
2738 *(argsStart - 1) = save_c;
2739
2740 return error;
2741}
2742
2743void
2744md_assemble (char *str)
2745{
2746 struct riscv_cl_insn insn;
2747 expressionS imm_expr;
2748 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2749
dcd709e0
NC		 2750 /* The architecture and privileged elf attributes should be set
2751 before assembling. */
8f595e9b
NC		 2752 if (!start_assemble)
2753 {
5b7c81bd 2754 start_assemble = true;
e23eba97 2755
dcd709e0 2756 riscv_set_abi_by_arch ();
8f595e9b
NC		 2757 if (!riscv_set_default_priv_spec (NULL))
2758 return;
2759 }
2760
2761 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2dc8dd17 2762
e23eba97
NC		 2763 if (error)
2764 {
2765 as_bad ("%s `%s'", error, str);
2766 return;
2767 }
2768
2769 if (insn.insn_mo->pinfo == INSN_MACRO)
2770 macro (&insn, &imm_expr, &imm_reloc);
2771 else
2772 append_insn (&insn, &imm_expr, imm_reloc);
2773}
2774
2775const char *
2776md_atof (int type, char *litP, int *sizeP)
2777{
2778 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2779}
2780
2781void
2782md_number_to_chars (char *buf, valueT val, int n)
2783{
fbc09e7a
MC		 2784 if (target_big_endian)
2785 number_to_chars_bigendian (buf, val, n);
2786 else
2787 number_to_chars_littleendian (buf, val, n);
e23eba97
NC		 2788}
2789
2790const char *md_shortopts = "O::g::G:";
2791
2792enum options
2793{
2922d21d 2794 OPTION_MARCH = OPTION_MD_BASE,
e23eba97
NC		 2795 OPTION_PIC,
2796 OPTION_NO_PIC,
2922d21d 2797 OPTION_MABI,
71060565
JW		 2798 OPTION_RELAX,
2799 OPTION_NO_RELAX,
2dc8dd17
JW		 2800 OPTION_ARCH_ATTR,
2801 OPTION_NO_ARCH_ATTR,
2ca89224
NC		 2802 OPTION_CSR_CHECK,
2803 OPTION_NO_CSR_CHECK,
8f595e9b
NC		 2804 OPTION_MISA_SPEC,
2805 OPTION_MPRIV_SPEC,
fbc09e7a
MC		 2806 OPTION_BIG_ENDIAN,
2807 OPTION_LITTLE_ENDIAN,
e23eba97
NC		 2808 OPTION_END_OF_ENUM
2809};
2810
2811struct option md_longopts[] =
2812{
e23eba97
NC		 2813 {"march", required_argument, NULL, OPTION_MARCH},
2814 {"fPIC", no_argument, NULL, OPTION_PIC},
2815 {"fpic", no_argument, NULL, OPTION_PIC},
2816 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2922d21d 2817 {"mabi", required_argument, NULL, OPTION_MABI},
71060565
JW		 2818 {"mrelax", no_argument, NULL, OPTION_RELAX},
2819 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2dc8dd17
JW		 2820 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2821 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2ca89224
NC		 2822 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2823 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
8f595e9b
NC		 2824 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2825 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
fbc09e7a
MC		 2826 {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
2827 {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
e23eba97
NC		 2828
2829 {NULL, no_argument, NULL, 0}
2830};
2831size_t md_longopts_size = sizeof (md_longopts);
2832
e23eba97
NC		 2833int
2834md_parse_option (int c, const char *arg)
2835{
2836 switch (c)
2837 {
e23eba97 2838 case OPTION_MARCH:
8f595e9b 2839 default_arch_with_ext = arg;
e23eba97
NC		 2840 break;
2841
2842 case OPTION_NO_PIC:
5b7c81bd 2843 riscv_opts.pic = false;
e23eba97
NC		 2844 break;
2845
2846 case OPTION_PIC:
5b7c81bd 2847 riscv_opts.pic = true;
e23eba97
NC		 2848 break;
2849
2922d21d
AW		 2850 case OPTION_MABI:
2851 if (strcmp (arg, "ilp32") == 0)
5b7c81bd 2852 riscv_set_abi (32, FLOAT_ABI_SOFT, false);
7f999549 2853 else if (strcmp (arg, "ilp32e") == 0)
5b7c81bd 2854 riscv_set_abi (32, FLOAT_ABI_SOFT, true);
2922d21d 2855 else if (strcmp (arg, "ilp32f") == 0)
5b7c81bd 2856 riscv_set_abi (32, FLOAT_ABI_SINGLE, false);
2922d21d 2857 else if (strcmp (arg, "ilp32d") == 0)
5b7c81bd 2858 riscv_set_abi (32, FLOAT_ABI_DOUBLE, false);
2922d21d 2859 else if (strcmp (arg, "ilp32q") == 0)
5b7c81bd 2860 riscv_set_abi (32, FLOAT_ABI_QUAD, false);
2922d21d 2861 else if (strcmp (arg, "lp64") == 0)
5b7c81bd 2862 riscv_set_abi (64, FLOAT_ABI_SOFT, false);
2922d21d 2863 else if (strcmp (arg, "lp64f") == 0)
5b7c81bd 2864 riscv_set_abi (64, FLOAT_ABI_SINGLE, false);
2922d21d 2865 else if (strcmp (arg, "lp64d") == 0)
5b7c81bd 2866 riscv_set_abi (64, FLOAT_ABI_DOUBLE, false);
2922d21d 2867 else if (strcmp (arg, "lp64q") == 0)
5b7c81bd 2868 riscv_set_abi (64, FLOAT_ABI_QUAD, false);
2922d21d
AW		 2869 else
2870 return 0;
5b7c81bd 2871 explicit_mabi = true;
2922d21d
AW		 2872 break;
2873
71060565 2874 case OPTION_RELAX:
5b7c81bd 2875 riscv_opts.relax = true;
71060565
JW		 2876 break;
2877
2878 case OPTION_NO_RELAX:
5b7c81bd 2879 riscv_opts.relax = false;
71060565
JW		 2880 break;
2881
2dc8dd17 2882 case OPTION_ARCH_ATTR:
5b7c81bd 2883 riscv_opts.arch_attr = true;
2dc8dd17
JW		 2884 break;
2885
2886 case OPTION_NO_ARCH_ATTR:
5b7c81bd 2887 riscv_opts.arch_attr = false;
2dc8dd17
JW		 2888 break;
2889
2ca89224 2890 case OPTION_CSR_CHECK:
5b7c81bd 2891 riscv_opts.csr_check = true;
2ca89224
NC		 2892 break;
2893
2894 case OPTION_NO_CSR_CHECK:
5b7c81bd 2895 riscv_opts.csr_check = false;
2ca89224
NC		 2896 break;
2897
8f595e9b
NC		 2898 case OPTION_MISA_SPEC:
2899 return riscv_set_default_isa_spec (arg);
2900
2901 case OPTION_MPRIV_SPEC:
2902 return riscv_set_default_priv_spec (arg);
2903
fbc09e7a
MC		 2904 case OPTION_BIG_ENDIAN:
2905 target_big_endian = 1;
2906 break;
2907
2908 case OPTION_LITTLE_ENDIAN:
2909 target_big_endian = 0;
2910 break;
2911
e23eba97
NC		 2912 default:
2913 return 0;
2914 }
2915
2916 return 1;
2917}
2918
2919void
2920riscv_after_parse_args (void)
2921{
dcd709e0
NC		 2922 /* The --with-arch is optional for now, so we still need to set the xlen
2923 according to the default_arch, which is set by the --target. */
e23eba97
NC		 2924 if (xlen == 0)
2925 {
2926 if (strcmp (default_arch, "riscv32") == 0)
2927 xlen = 32;
2928 else if (strcmp (default_arch, "riscv64") == 0)
2929 xlen = 64;
2930 else
2931 as_bad ("unknown default architecture `%s'", default_arch);
2932 }
8f595e9b
NC		 2933 if (default_arch_with_ext == NULL)
2934 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2935
2936 /* Initialize the hash table for extensions with default version. */
3d73d29e 2937 ext_version_hash = init_ext_version_hash ();
8f595e9b 2938
dcd709e0 2939 /* Set default specs. */
8f595e9b
NC		 2940 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2941 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
dcd709e0
NC		 2942 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2943 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2922d21d 2944
8f595e9b 2945 riscv_set_arch (default_arch_with_ext);
2922d21d
AW		 2946
2947 /* Add the RVC extension, regardless of -march, to support .option rvc. */
5b7c81bd 2948 riscv_set_rvc (false);
1080bf78 2949 if (riscv_subset_supports ("c"))
5b7c81bd 2950 riscv_set_rvc (true);
2922d21d 2951
7f999549 2952 /* Enable RVE if specified by the -march option. */
5b7c81bd 2953 riscv_set_rve (false);
1080bf78 2954 if (riscv_subset_supports ("e"))
5b7c81bd 2955 riscv_set_rve (true);
7f999549 2956
0ac2b354
AB		 2957 /* If the CIE to be produced has not been overridden on the command line,
2958 then produce version 3 by default. This allows us to use the full
2959 range of registers in a .cfi_return_column directive. */
2960 if (flag_dwarf_cie_version == -1)
2961 flag_dwarf_cie_version = 3;
e23eba97
NC		 2962}
2963
2964long
2965md_pcrel_from (fixS *fixP)
2966{
2967 return fixP->fx_where + fixP->fx_frag->fr_address;
2968}
2969
2970/* Apply a fixup to the object file. */
2971
2972void
2973md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2974{
45f76423 2975 unsigned int subtype;
e23eba97 2976 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
5b7c81bd 2977 bool relaxable = false;
c1b465c9 2978 offsetT loc;
a6cbf936 2979 segT sub_segment;
e23eba97
NC		 2980
2981 /* Remember value for tc_gen_reloc. */
2982 fixP->fx_addnumber = *valP;
2983
2984 switch (fixP->fx_r_type)
2985 {
e23eba97
NC		 2986 case BFD_RELOC_RISCV_HI20:
2987 case BFD_RELOC_RISCV_LO12_I:
2988 case BFD_RELOC_RISCV_LO12_S:
45f76423
AW		 2989 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2990 | bfd_getl32 (buf), buf);
a5ec5e3f 2991 if (fixP->fx_addsy == NULL)
5b7c81bd
AM		 2992 fixP->fx_done = true;
2993 relaxable = true;
45f76423
AW		 2994 break;
2995
2996 case BFD_RELOC_RISCV_GOT_HI20:
e23eba97
NC		 2997 case BFD_RELOC_RISCV_ADD8:
2998 case BFD_RELOC_RISCV_ADD16:
2999 case BFD_RELOC_RISCV_ADD32:
3000 case BFD_RELOC_RISCV_ADD64:
45f76423 3001 case BFD_RELOC_RISCV_SUB6:
e23eba97
NC		 3002 case BFD_RELOC_RISCV_SUB8:
3003 case BFD_RELOC_RISCV_SUB16:
3004 case BFD_RELOC_RISCV_SUB32:
3005 case BFD_RELOC_RISCV_SUB64:
45f76423
AW		 3006 case BFD_RELOC_RISCV_RELAX:
3007 break;
3008
3009 case BFD_RELOC_RISCV_TPREL_HI20:
3010 case BFD_RELOC_RISCV_TPREL_LO12_I:
3011 case BFD_RELOC_RISCV_TPREL_LO12_S:
3012 case BFD_RELOC_RISCV_TPREL_ADD:
5b7c81bd 3013 relaxable = true;
45f76423
AW		 3014 /* Fall through. */
3015
3016 case BFD_RELOC_RISCV_TLS_GOT_HI20:
3017 case BFD_RELOC_RISCV_TLS_GD_HI20:
3018 case BFD_RELOC_RISCV_TLS_DTPREL32:
3019 case BFD_RELOC_RISCV_TLS_DTPREL64:
e294484e
AW		 3020 if (fixP->fx_addsy != NULL)
3021 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3022 else
3023 as_bad_where (fixP->fx_file, fixP->fx_line,
3024 _("TLS relocation against a constant"));
e23eba97
NC		 3025 break;
3026
e23eba97 3027 case BFD_RELOC_32:
a6cbf936
KLC		 3028 /* Use pc-relative relocation for FDE initial location.
3029 The symbol address in .eh_frame may be adjusted in
3030 _bfd_elf_discard_section_eh_frame, and the content of
3031 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3032 Therefore, we cannot insert a relocation whose addend symbol is
dcd709e0 3033 in .eh_frame. Othrewise, the value may be adjusted twice. */
a6cbf936
KLC		 3034 if (fixP->fx_addsy && fixP->fx_subsy
3035 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
3036 && strcmp (sub_segment->name, ".eh_frame") == 0
3037 && S_GET_VALUE (fixP->fx_subsy)
3038 == fixP->fx_frag->fr_address + fixP->fx_where)
3039 {
3040 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
3041 fixP->fx_subsy = NULL;
3042 break;
3043 }
3044 /* Fall through. */
3045 case BFD_RELOC_64:
e23eba97
NC		 3046 case BFD_RELOC_16:
3047 case BFD_RELOC_8:
45f76423 3048 case BFD_RELOC_RISCV_CFA:
e23eba97
NC		 3049 if (fixP->fx_addsy && fixP->fx_subsy)
3050 {
3051 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3052 fixP->fx_next->fx_addsy = fixP->fx_subsy;
3053 fixP->fx_next->fx_subsy = NULL;
3054 fixP->fx_next->fx_offset = 0;
3055 fixP->fx_subsy = NULL;
3056
3057 switch (fixP->fx_r_type)
3058 {
3059 case BFD_RELOC_64:
3060 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
3061 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
3062 break;
3063
3064 case BFD_RELOC_32:
3065 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
3066 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3067 break;
3068
3069 case BFD_RELOC_16:
3070 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
3071 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
3072 break;
3073
3074 case BFD_RELOC_8:
3075 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
3076 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
073808ed 3077 break;
e23eba97 3078
45f76423
AW		 3079 case BFD_RELOC_RISCV_CFA:
3080 /* Load the byte to get the subtype. */
c1b465c9
KLC		 3081 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
3082 loc = fixP->fx_frag->fr_fix - (subtype & 7);
45f76423
AW		 3083 switch (subtype)
3084 {
3085 case DW_CFA_advance_loc1:
c1b465c9
KLC		 3086 fixP->fx_where = loc + 1;
3087 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 3088 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
3089 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
3090 break;
3091
3092 case DW_CFA_advance_loc2:
3093 fixP->fx_size = 2;
45f76423 3094 fixP->fx_next->fx_size = 2;
c1b465c9
KLC		 3095 fixP->fx_where = loc + 1;
3096 fixP->fx_next->fx_where = loc + 1;
45f76423
AW		 3097 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
3098 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
3099 break;
3100
3101 case DW_CFA_advance_loc4:
3102 fixP->fx_size = 4;
45f76423 3103 fixP->fx_next->fx_size = 4;
c1b465c9
KLC		 3104 fixP->fx_where = loc;
3105 fixP->fx_next->fx_where = loc;
45f76423
AW		 3106 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
3107 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3108 break;
3109
3110 default:
3111 if (subtype < 0x80 && (subtype & 0x40))
3112 {
3113 /* DW_CFA_advance_loc */
2aece2ba
KLC		 3114 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
3115 fixP->fx_next->fx_frag = fixP->fx_frag;
45f76423
AW		 3116 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
3117 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
3118 }
3119 else
b800637e 3120 as_fatal (_("internal: bad CFA value #%d"), subtype);
45f76423
AW		 3121 break;
3122 }
3123 break;
3124
e23eba97
NC		 3125 default:
3126 /* This case is unreachable. */
3127 abort ();
3128 }
3129 }
3130 /* Fall through. */
3131
3132 case BFD_RELOC_RVA:
3133 /* If we are deleting this reloc entry, we must fill in the
3134 value now. This can happen if we have a .word which is not
3135 resolved when it appears but is later defined. */
3136 if (fixP->fx_addsy == NULL)
3137 {
3138 gas_assert (fixP->fx_size <= sizeof (valueT));
3139 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
3140 fixP->fx_done = 1;
3141 }
3142 break;
3143
3144 case BFD_RELOC_RISCV_JMP:
3145 if (fixP->fx_addsy)
3146 {
3147 /* Fill in a tentative value to improve objdump readability. */
3148 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3149 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3150 bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf);
e23eba97
NC		 3151 }
3152 break;
3153
3154 case BFD_RELOC_12_PCREL:
3155 if (fixP->fx_addsy)
3156 {
3157 /* Fill in a tentative value to improve objdump readability. */
3158 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3159 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3160 bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf);
e23eba97
NC		 3161 }
3162 break;
3163
3164 case BFD_RELOC_RISCV_RVC_BRANCH:
3165 if (fixP->fx_addsy)
3166 {
3167 /* Fill in a tentative value to improve objdump readability. */
3168 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3169 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3170 bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf);
e23eba97
NC		 3171 }
3172 break;
3173
3174 case BFD_RELOC_RISCV_RVC_JUMP:
3175 if (fixP->fx_addsy)
3176 {
3177 /* Fill in a tentative value to improve objdump readability. */
3178 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3179 bfd_vma delta = target - md_pcrel_from (fixP);
5a9f5403 3180 bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf);
e23eba97
NC		 3181 }
3182 break;
3183
e23eba97
NC		 3184 case BFD_RELOC_RISCV_CALL:
3185 case BFD_RELOC_RISCV_CALL_PLT:
5b7c81bd 3186 relaxable = true;
45f76423
AW		 3187 break;
3188
9d06997a 3189 case BFD_RELOC_RISCV_PCREL_HI20:
45f76423
AW		 3190 case BFD_RELOC_RISCV_PCREL_LO12_S:
3191 case BFD_RELOC_RISCV_PCREL_LO12_I:
9d06997a
PD		 3192 relaxable = riscv_opts.relax;
3193 break;
3194
e23eba97
NC		 3195 case BFD_RELOC_RISCV_ALIGN:
3196 break;
3197
3198 default:
3199 /* We ignore generic BFD relocations we don't know about. */
3200 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
b800637e 3201 as_fatal (_("internal: bad relocation #%d"), fixP->fx_r_type);
e23eba97 3202 }
45f76423 3203
e294484e
AW		 3204 if (fixP->fx_subsy != NULL)
3205 as_bad_where (fixP->fx_file, fixP->fx_line,
3206 _("unsupported symbol subtraction"));
3207
45f76423
AW		 3208 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3209 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3210 {
3211 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3212 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3213 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
b1b11e92 3214 fixP->fx_next->fx_size = 0;
45f76423
AW		 3215 }
3216}
3217
3218/* Because the value of .cfi_remember_state may changed after relaxation,
3219 we insert a fix to relocate it again in link-time. */
3220
3221void
3222riscv_pre_output_hook (void)
3223{
3224 const frchainS *frch;
72393fd1
JW		 3225 segT s;
3226
3227 /* Save the current segment info. */
3228 segT seg = now_seg;
3229 subsegT subseg = now_subseg;
45f76423
AW		 3230
3231 for (s = stdoutput->sections; s; s = s->next)
3232 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3233 {
7cb7b948 3234 fragS *frag;
45f76423
AW		 3235
3236 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3237 {
3238 if (frag->fr_type == rs_cfa)
3239 {
45f76423 3240 expressionS exp;
8d1015a8 3241 expressionS *symval;
45f76423 3242
8d1015a8 3243 symval = symbol_get_value_expression (frag->fr_symbol);
45f76423 3244 exp.X_op = O_subtract;
8d1015a8 3245 exp.X_add_symbol = symval->X_add_symbol;
45f76423 3246 exp.X_add_number = 0;
8d1015a8 3247 exp.X_op_symbol = symval->X_op_symbol;
45f76423 3248
72393fd1
JW		 3249 /* We must set the segment before creating a frag after all
3250 frag chains have been chained together. */
3251 subseg_set (s, frch->frch_subseg);
3252
c1b465c9 3253 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
45f76423
AW		 3254 BFD_RELOC_RISCV_CFA);
3255 }
3256 }
3257 }
72393fd1
JW		 3258
3259 /* Restore the original segment info. */
3260 subseg_set (seg, subseg);
e23eba97
NC		 3261}
3262
3263/* This structure is used to hold a stack of .option values. */
e23eba97
NC		 3264struct riscv_option_stack
3265{
3266 struct riscv_option_stack *next;
3267 struct riscv_set_options options;
3268};
3269
3270static struct riscv_option_stack *riscv_opts_stack;
3271
3272/* Handle the .option pseudo-op. */
3273
3274static void
3275s_riscv_option (int x ATTRIBUTE_UNUSED)
3276{
3277 char *name = input_line_pointer, ch;
3278
3279 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3280 ++input_line_pointer;
3281 ch = *input_line_pointer;
3282 *input_line_pointer = '\0';
3283
3284 if (strcmp (name, "rvc") == 0)
5b7c81bd 3285 riscv_set_rvc (true);
e23eba97 3286 else if (strcmp (name, "norvc") == 0)
5b7c81bd 3287 riscv_set_rvc (false);
e23eba97 3288 else if (strcmp (name, "pic") == 0)
5b7c81bd 3289 riscv_opts.pic = true;
e23eba97 3290 else if (strcmp (name, "nopic") == 0)
5b7c81bd 3291 riscv_opts.pic = false;
45f76423 3292 else if (strcmp (name, "relax") == 0)
5b7c81bd 3293 riscv_opts.relax = true;
45f76423 3294 else if (strcmp (name, "norelax") == 0)
5b7c81bd 3295 riscv_opts.relax = false;
2ca89224 3296 else if (strcmp (name, "csr-check") == 0)
5b7c81bd 3297 riscv_opts.csr_check = true;
2ca89224 3298 else if (strcmp (name, "no-csr-check") == 0)
5b7c81bd 3299 riscv_opts.csr_check = false;
e23eba97
NC		 3300 else if (strcmp (name, "push") == 0)
3301 {
3302 struct riscv_option_stack *s;
3303
3304 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3305 s->next = riscv_opts_stack;
3306 s->options = riscv_opts;
3307 riscv_opts_stack = s;
3308 }
3309 else if (strcmp (name, "pop") == 0)
3310 {
3311 struct riscv_option_stack *s;
3312
3313 s = riscv_opts_stack;
3314 if (s == NULL)
3315 as_bad (_(".option pop with no .option push"));
3316 else
3317 {
3318 riscv_opts = s->options;
3319 riscv_opts_stack = s->next;
3320 free (s);
3321 }
3322 }
3323 else
3324 {
b800637e 3325 as_warn (_("unrecognized .option directive: %s\n"), name);
e23eba97
NC		 3326 }
3327 *input_line_pointer = ch;
3328 demand_empty_rest_of_line ();
3329}
3330
3331/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3332 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3333 use in DWARF debug information. */
3334
3335static void
3336s_dtprel (int bytes)
3337{
3338 expressionS ex;
3339 char *p;
3340
3341 expression (&ex);
3342
3343 if (ex.X_op != O_symbol)
3344 {
b800637e 3345 as_bad (_("unsupported use of %s"), (bytes == 8
e23eba97
NC		 3346 ? ".dtpreldword"
3347 : ".dtprelword"));
3348 ignore_rest_of_line ();
3349 }
3350
3351 p = frag_more (bytes);
3352 md_number_to_chars (p, 0, bytes);
5b7c81bd 3353 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false,
e23eba97
NC		 3354 (bytes == 8
3355 ? BFD_RELOC_RISCV_TLS_DTPREL64
3356 : BFD_RELOC_RISCV_TLS_DTPREL32));
3357
3358 demand_empty_rest_of_line ();
3359}
3360
3361/* Handle the .bss pseudo-op. */
3362
3363static void
3364s_bss (int ignore ATTRIBUTE_UNUSED)
3365{
3366 subseg_set (bss_section, 0);
3367 demand_empty_rest_of_line ();
3368}
3369
e23eba97 3370static void
d115ab8e 3371riscv_make_nops (char *buf, bfd_vma bytes)
e23eba97 3372{
d115ab8e 3373 bfd_vma i = 0;
e23eba97 3374
e5b737de
AW		 3375 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3376 means we are not within a valid instruction sequence. It is thus safe
3377 to use a zero byte, even though that is not a valid instruction. */
3378 if (bytes % 2 == 1)
3379 buf[i++] = 0;
3380
3381 /* Use at most one 2-byte NOP. */
3382 if ((bytes - i) % 4 == 2)
e23eba97 3383 {
fbc09e7a 3384 number_to_chars_littleendian (buf + i, RVC_NOP, 2);
d115ab8e 3385 i += 2;
e23eba97
NC		 3386 }
3387
e5b737de 3388 /* Fill the remainder with 4-byte NOPs. */
d115ab8e 3389 for ( ; i < bytes; i += 4)
fbc09e7a 3390 number_to_chars_littleendian (buf + i, RISCV_NOP, 4);
d115ab8e 3391}
e23eba97 3392
d115ab8e
AW		 3393/* Called from md_do_align. Used to create an alignment frag in a
3394 code section by emitting a worst-case NOP sequence that the linker
3395 will later relax to the correct number of NOPs. We can't compute
3396 the correct alignment now because of other linker relaxations. */
3397
5b7c81bd 3398bool
d115ab8e
AW		 3399riscv_frag_align_code (int n)
3400{
e5b737de 3401 bfd_vma bytes = (bfd_vma) 1 << n;
36877bfb
JW		 3402 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3403 bfd_vma worst_case_bytes = bytes - insn_alignment;
3404 char *nops;
ed0816bd 3405 expressionS ex;
d115ab8e 3406
36877bfb
JW		 3407 /* If we are moving to a smaller alignment than the instruction size, then no
3408 alignment is required. */
3409 if (bytes <= insn_alignment)
5b7c81bd 3410 return true;
36877bfb 3411
d115ab8e
AW		 3412 /* When not relaxing, riscv_handle_align handles code alignment. */
3413 if (!riscv_opts.relax)
5b7c81bd 3414 return false;
e23eba97 3415
e80ae190
JW		 3416 nops = frag_more (worst_case_bytes);
3417
ed0816bd
PD		 3418 ex.X_op = O_constant;
3419 ex.X_add_number = worst_case_bytes;
d115ab8e 3420
ed0816bd 3421 riscv_make_nops (nops, worst_case_bytes);
e23eba97 3422
ed0816bd 3423 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
5b7c81bd 3424 &ex, false, BFD_RELOC_RISCV_ALIGN);
e23eba97 3425
5b7c81bd 3426 return true;
d115ab8e 3427}
e23eba97 3428
d115ab8e
AW		 3429/* Implement HANDLE_ALIGN. */
3430
3431void
3432riscv_handle_align (fragS *fragP)
3433{
3434 switch (fragP->fr_type)
3435 {
3436 case rs_align_code:
3437 /* When relaxing, riscv_frag_align_code handles code alignment. */
3438 if (!riscv_opts.relax)
3439 {
e80ae190
JW		 3440 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3441 - fragP->fr_address - fragP->fr_fix);
3442 /* We have 4 byte uncompressed nops. */
3443 bfd_signed_vma size = 4;
3444 bfd_signed_vma excess = bytes % size;
3445 char *p = fragP->fr_literal + fragP->fr_fix;
3446
3447 if (bytes <= 0)
d115ab8e
AW		 3448 break;
3449
e80ae190
JW		 3450 /* Insert zeros or compressed nops to get 4 byte alignment. */
3451 if (excess)
3452 {
3453 riscv_make_nops (p, excess);
3454 fragP->fr_fix += excess;
3455 p += excess;
3456 }
3457
3458 /* Insert variable number of 4 byte uncompressed nops. */
3459 riscv_make_nops (p, size);
3460 fragP->fr_var = size;
d115ab8e
AW		 3461 }
3462 break;
3463
3464 default:
3465 break;
3466 }
e23eba97
NC		 3467}
3468
3469int
3470md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3471{
5b7c81bd 3472 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false));
e23eba97
NC		 3473}
3474
3475/* Translate internal representation of relocation info to BFD target
3476 format. */
3477
3478arelent *
3479tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3480{
3481 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3482
3483 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3484 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3485 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3486 reloc->addend = fixp->fx_addnumber;
3487
3488 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3489 if (reloc->howto == NULL)
3490 {
3491 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3492 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3493 {
3494 /* We don't have R_RISCV_8/16, but for this special case,
3495 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3496 return reloc;
3497 }
3498
3499 as_bad_where (fixp->fx_file, fixp->fx_line,
3500 _("cannot represent %s relocation in object file"),
3501 bfd_get_reloc_code_name (fixp->fx_r_type));
3502 return NULL;
3503 }
3504
3505 return reloc;
3506}
3507
3508int
3509riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3510{
3511 if (RELAX_BRANCH_P (fragp->fr_subtype))
3512 {
3513 offsetT old_var = fragp->fr_var;
5b7c81bd 3514 fragp->fr_var = relaxed_branch_length (fragp, sec, true);
e23eba97
NC		 3515 return fragp->fr_var - old_var;
3516 }
3517
3518 return 0;
3519}
3520
3521/* Expand far branches to multi-instruction sequences. */
3522
3523static void
3524md_convert_frag_branch (fragS *fragp)
3525{
3526 bfd_byte *buf;
3527 expressionS exp;
3528 fixS *fixp;
3529 insn_t insn;
3530 int rs1, reloc;
3531
3532 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3533
3534 exp.X_op = O_symbol;
3535 exp.X_add_symbol = fragp->fr_symbol;
3536 exp.X_add_number = fragp->fr_offset;
3537
3538 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3539
3540 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3541 {
3542 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3543 {
3544 case 8:
3545 case 4:
3546 /* Expand the RVC branch into a RISC-V one. */
3547 insn = bfd_getl16 (buf);
3548 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3549 if ((insn & MASK_C_J) == MATCH_C_J)
3550 insn = MATCH_JAL;
3551 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3552 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3553 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3554 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3555 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3556 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3557 else
3558 abort ();
3559 bfd_putl32 (insn, buf);
3560 break;
3561
3562 case 6:
3563 /* Invert the branch condition. Branch over the jump. */
3564 insn = bfd_getl16 (buf);
3565 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
5a9f5403 3566 insn |= ENCODE_CBTYPE_IMM (6);
e23eba97
NC		 3567 bfd_putl16 (insn, buf);
3568 buf += 2;
3569 goto jump;
3570
3571 case 2:
3572 /* Just keep the RVC branch. */
3573 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3574 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3575 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
5b7c81bd 3576 2, &exp, false, reloc);
e23eba97
NC		 3577 buf += 2;
3578 goto done;
3579
3580 default:
1d65abb5 3581 abort ();
e23eba97
NC		 3582 }
3583 }
3584
3585 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3586 {
3587 case 8:
3588 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3589
3590 /* Invert the branch condition. Branch over the jump. */
3591 insn = bfd_getl32 (buf);
3592 insn ^= MATCH_BEQ ^ MATCH_BNE;
5a9f5403 3593 insn |= ENCODE_BTYPE_IMM (8);
fbc09e7a 3594 bfd_putl32 (insn, buf);
e23eba97
NC		 3595 buf += 4;
3596
dc1e8a47 3597 jump:
e23eba97
NC		 3598 /* Jump to the target. */
3599 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
5b7c81bd 3600 4, &exp, false, BFD_RELOC_RISCV_JMP);
fbc09e7a 3601 bfd_putl32 (MATCH_JAL, buf);
e23eba97
NC		 3602 buf += 4;
3603 break;
3604
3605 case 4:
3606 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3607 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3608 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
5b7c81bd 3609 4, &exp, false, reloc);
e23eba97
NC		 3610 buf += 4;
3611 break;
3612
3613 default:
3614 abort ();
3615 }
3616
dc1e8a47 3617 done:
e23eba97
NC		 3618 fixp->fx_file = fragp->fr_file;
3619 fixp->fx_line = fragp->fr_line;
3620
3621 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3622 + fragp->fr_fix + fragp->fr_var);
3623
3624 fragp->fr_fix += fragp->fr_var;
3625}
3626
3627/* Relax a machine dependent frag. This returns the amount by which
3628 the current size of the frag should change. */
3629
3630void
3631md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3632 fragS *fragp)
3633{
3634 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3635 md_convert_frag_branch (fragp);
3636}
3637
3638void
3639md_show_usage (FILE *stream)
3640{
3641 fprintf (stream, _("\
3642RISC-V options:\n\
8f595e9b
NC		 3643 -fpic generate position-independent code\n\
3644 -fno-pic don't generate position-independent code (default)\n\
3645 -march=ISA set the RISC-V architecture\n\
3646 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3647 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3648 -mabi=ABI set the RISC-V ABI\n\
3649 -mrelax enable relax (default)\n\
3650 -mno-relax disable relax\n\
3651 -march-attr generate RISC-V arch attribute\n\
3652 -mno-arch-attr don't generate RISC-V arch attribute\n\
e23eba97
NC		 3653"));
3654}
3655
3656/* Standard calling conventions leave the CFA at SP on entry. */
dcd709e0 3657
e23eba97
NC		 3658void
3659riscv_cfi_frame_initial_instructions (void)
3660{
3661 cfi_add_CFA_def_cfa_register (X_SP);
3662}
3663
3664int
3665tc_riscv_regname_to_dw2regnum (char *regname)
3666{
3667 int reg;
3668
3669 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3670 return reg;
3671
3672 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3673 return reg + 32;
3674
4762fe62
AB		 3675 /* CSRs are numbered 4096 -> 8191. */
3676 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3677 return reg + 4096;
3678
e23eba97
NC		 3679 as_bad (_("unknown register `%s'"), regname);
3680 return -1;
3681}
3682
3683void
3684riscv_elf_final_processing (void)
3685{
6e1605e4 3686 riscv_set_abi_by_arch ();
e23eba97 3687 elf_elfheader (stdoutput)->e_flags |= elf_flags;
e23eba97
NC		 3688}
3689
3690/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3691 since these directives break relaxation when used with symbol deltas. */
3692
3693static void
3694s_riscv_leb128 (int sign)
3695{
3696 expressionS exp;
3697 char *save_in = input_line_pointer;
3698
3699 expression (&exp);
3700 if (exp.X_op != O_constant)
3701 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3702 demand_empty_rest_of_line ();
3703
3704 input_line_pointer = save_in;
3705 return s_leb128 (sign);
3706}
3707
0e35537d
JW		 3708/* Parse the .insn directive. */
3709
3710static void
3711s_riscv_insn (int x ATTRIBUTE_UNUSED)
3712{
3713 char *str = input_line_pointer;
3714 struct riscv_cl_insn insn;
3715 expressionS imm_expr;
3716 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3717 char save_c;
3718
3719 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3720 ++input_line_pointer;
3721
3722 save_c = *input_line_pointer;
3723 *input_line_pointer = '\0';
3724
3725 const char *error = riscv_ip (str, &insn, &imm_expr,
3726 &imm_reloc, insn_type_hash);
3727
3728 if (error)
3729 {
3730 as_bad ("%s `%s'", error, str);
3731 }
3732 else
3733 {
3734 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3735 append_insn (&insn, &imm_expr, imm_reloc);
3736 }
3737
3738 *input_line_pointer = save_c;
3739 demand_empty_rest_of_line ();
3740}
3741
dcd709e0
NC		 3742/* Update architecture and privileged elf attributes. If we don't set
3743 them, then try to output the default ones. */
2dc8dd17
JW		 3744
3745static void
8f595e9b 3746riscv_write_out_attrs (void)
2dc8dd17 3747{
8f595e9b 3748 const char *arch_str, *priv_str, *p;
dcd709e0
NC		 3749 /* versions[0]: major version.
3750 versions[1]: minor version.
3751 versions[2]: revision version. */
8f595e9b
NC		 3752 unsigned versions[3] = {0}, number = 0;
3753 unsigned int i;
2dc8dd17 3754
dcd709e0 3755 /* Re-write architecture elf attribute. */
8f595e9b 3756 arch_str = riscv_arch_str (xlen, &riscv_subsets);
2dc8dd17 3757 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
1942a048 3758 xfree ((void *) arch_str);
8f595e9b
NC		 3759
3760 /* For the file without any instruction, we don't set the default_priv_spec
dcd709e0
NC		 3761 according to the privileged elf attributes since the md_assemble isn't
3762 called. */
8f595e9b
NC		 3763 if (!start_assemble
3764 && !riscv_set_default_priv_spec (NULL))
3765 return;
3766
dcd709e0
NC		 3767 /* If we already have set privileged elf attributes, then no need to do
3768 anything. Otherwise, don't generate or update them when no CSR and
3769 privileged instructions are used. */
1a79004f 3770 if (!explicit_priv_attr)
3fc6c3dc
NC		 3771 return;
3772
3d73d29e 3773 RISCV_GET_PRIV_SPEC_NAME (priv_str, default_priv_spec);
8f595e9b
NC		 3774 p = priv_str;
3775 for (i = 0; *p; ++p)
3776 {
3777 if (*p == '.' && i < 3)
3778 {
3779 versions[i++] = number;
3780 number = 0;
3781 }
3782 else if (ISDIGIT (*p))
3783 number = (number * 10) + (*p - '0');
3784 else
3785 {
b800637e 3786 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str);
8f595e9b
NC		 3787 return;
3788 }
3789 }
3790 versions[i] = number;
3791
dcd709e0 3792 /* Re-write privileged elf attributes. */
8f595e9b
NC		 3793 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3794 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3795 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
2dc8dd17
JW		 3796}
3797
dcd709e0 3798/* Add the default contents for the .riscv.attributes section. */
2dc8dd17
JW		 3799
3800static void
3801riscv_set_public_attributes (void)
3802{
8f595e9b
NC		 3803 if (riscv_opts.arch_attr || explicit_attr)
3804 riscv_write_out_attrs ();
2dc8dd17
JW		 3805}
3806
3807/* Called after all assembly has been done. */
3808
3809void
3810riscv_md_end (void)
3811{
3812 riscv_set_public_attributes ();
3813}
3814
3815/* Given a symbolic attribute NAME, return the proper integer value.
3816 Returns -1 if the attribute is not known. */
3817
3818int
3819riscv_convert_symbolic_attribute (const char *name)
3820{
3821 static const struct
3822 {
1942a048
NC		 3823 const char *name;
3824 const int tag;
2dc8dd17
JW		 3825 }
3826 attribute_table[] =
1942a048
NC		 3827 {
3828 /* When you modify this table you should
3829 also modify the list in doc/c-riscv.texi. */
3830#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3831 T(arch),
3832 T(priv_spec),
3833 T(priv_spec_minor),
3834 T(priv_spec_revision),
3835 T(unaligned_access),
3836 T(stack_align),
2dc8dd17 3837#undef T
1942a048 3838 };
2dc8dd17
JW		 3839
3840 if (name == NULL)
3841 return -1;
3842
1942a048 3843 unsigned int i;
2dc8dd17
JW		 3844 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3845 if (strcmp (name, attribute_table[i].name) == 0)
3846 return attribute_table[i].tag;
3847
3848 return -1;
3849}
3850
3851/* Parse a .attribute directive. */
3852
3853static void
3854s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3855{
3856 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
8f595e9b
NC		 3857 unsigned old_xlen;
3858 obj_attribute *attr;
2dc8dd17 3859
5b7c81bd 3860 explicit_attr = true;
8f595e9b 3861 switch (tag)
2dc8dd17 3862 {
8f595e9b
NC		 3863 case Tag_RISCV_arch:
3864 old_xlen = xlen;
2dc8dd17
JW		 3865 attr = elf_known_obj_attributes_proc (stdoutput);
3866 if (!start_assemble)
3867 riscv_set_arch (attr[Tag_RISCV_arch].s);
3868 else
b800637e
NC		 3869 as_fatal (_("architecture elf attributes must set before "
3870 "any instructions"));
2dc8dd17
JW		 3871
3872 if (old_xlen != xlen)
3873 {
3874 /* We must re-init bfd again if xlen is changed. */
3875 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3876 bfd_find_target (riscv_target_format (), stdoutput);
3877
3878 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
b800637e 3879 as_warn (_("could not set architecture and machine"));
2dc8dd17 3880 }
8f595e9b
NC		 3881 break;
3882
3883 case Tag_RISCV_priv_spec:
3884 case Tag_RISCV_priv_spec_minor:
3885 case Tag_RISCV_priv_spec_revision:
3886 if (start_assemble)
b800637e
NC		 3887 as_fatal (_("privileged elf attributes must set before "
3888 "any instructions"));
8f595e9b
NC		 3889 break;
3890
3891 default:
3892 break;
2dc8dd17
JW		 3893 }
3894}
3895
dcd709e0 3896/* RISC-V pseudo-ops table. */
e23eba97
NC		 3897static const pseudo_typeS riscv_pseudo_table[] =
3898{
e23eba97
NC		 3899 {"option", s_riscv_option, 0},
3900 {"half", cons, 2},
3901 {"word", cons, 4},
3902 {"dword", cons, 8},
3903 {"dtprelword", s_dtprel, 4},
3904 {"dtpreldword", s_dtprel, 8},
3905 {"bss", s_bss, 0},
e23eba97
NC		 3906 {"uleb128", s_riscv_leb128, 0},
3907 {"sleb128", s_riscv_leb128, 1},
0e35537d 3908 {"insn", s_riscv_insn, 0},
2dc8dd17 3909 {"attribute", s_riscv_attribute, 0},
e23eba97
NC		 3910
3911 { NULL, NULL, 0 },
3912};
3913
3914void
3915riscv_pop_insert (void)
3916{
3917 extern void pop_insert (const pseudo_typeS *);
3918
3919 pop_insert (riscv_pseudo_table);
3920}
GDB Binutils - Deliverables
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