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1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000 |
2 | @c Free Software Foundation, Inc. | |
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3 | @c This is part of the GAS manual. |
4 | @c For copying conditions, see the file as.texinfo. | |
5 | @ifset GENERIC | |
6 | @page | |
7 | @node MIPS-Dependent | |
8 | @chapter MIPS Dependent Features | |
9 | @end ifset | |
10 | @ifclear GENERIC | |
11 | @node Machine Dependencies | |
12 | @chapter MIPS Dependent Features | |
13 | @end ifclear | |
14 | ||
15 | @cindex MIPS processor | |
16 | @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several | |
84ea6cf2 | 17 | different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, |
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18 | and MIPS64. For information about the @sc{mips} instruction set, see |
19 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). | |
20 | For an overview of @sc{mips} assembly conventions, see ``Appendix D: | |
21 | Assembly Language Programming'' in the same work. | |
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22 | |
23 | @menu | |
24 | * MIPS Opts:: Assembler options | |
25 | * MIPS Object:: ECOFF object code | |
26 | * MIPS Stabs:: Directives for debugging information | |
27 | * MIPS ISA:: Directives to override the ISA level | |
28 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions | |
29 | * MIPS insn:: Directive to mark data as an instruction | |
30 | * MIPS option stack:: Directives to save and restore options | |
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31 | * MIPS ASE instruction generation overrides:: Directives to control |
32 | generation of MIPS ASE instructions | |
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33 | @end menu |
34 | ||
35 | @node MIPS Opts | |
36 | @section Assembler options | |
37 | ||
38 | The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these | |
39 | special options: | |
40 | ||
41 | @table @code | |
42 | @cindex @code{-G} option (MIPS) | |
43 | @item -G @var{num} | |
44 | This option sets the largest size of an object that can be referenced | |
45 | implicitly with the @code{gp} register. It is only accepted for targets | |
46 | that use @sc{ecoff} format. The default value is 8. | |
47 | ||
48 | @cindex @code{-EB} option (MIPS) | |
49 | @cindex @code{-EL} option (MIPS) | |
50 | @cindex MIPS big-endian output | |
51 | @cindex MIPS little-endian output | |
52 | @cindex big-endian output, MIPS | |
53 | @cindex little-endian output, MIPS | |
54 | @item -EB | |
55 | @itemx -EL | |
56 | Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or | |
57 | little-endian output at run time (unlike the other @sc{gnu} development | |
58 | tools, which must be configured for one or the other). Use @samp{-EB} | |
59 | to select big-endian output, and @samp{-EL} for little-endian. | |
60 | ||
61 | @cindex MIPS architecture options | |
62 | @item -mips1 | |
63 | @itemx -mips2 | |
64 | @itemx -mips3 | |
65 | @itemx -mips4 | |
84ea6cf2 | 66 | @itemx -mips5 |
e7af610e | 67 | @itemx -mips32 |
84ea6cf2 | 68 | @itemx -mips64 |
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69 | Generate code for a particular MIPS Instruction Set Architecture level. |
70 | @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, | |
71 | @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the | |
84ea6cf2 | 72 | @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and |
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73 | @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, and |
74 | @samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and | |
75 | @sc{MIPS64} ISA processors, respectively. You can also switch | |
76 | instruction sets during the assembly; see @ref{MIPS ISA, Directives to | |
ec68c924 | 77 | override the ISA level}. |
252b5132 | 78 | |
6349b5f4 | 79 | @item -mgp32 |
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80 | @itemx -mfp32 |
81 | Some macros have different expansions for 32-bit and 64-bit registers. | |
82 | The register sizes are normally inferred from the ISA and ABI, but these | |
83 | flags force a certain group of registers to be treated as 32 bits wide at | |
84 | all times. @samp{-mgp32} controls the size of general-purpose registers | |
85 | and @samp{-mfp32} controls the size of floating-point registers. | |
86 | ||
87 | On some MIPS variants there is a 32-bit mode flag; when this flag is | |
88 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only | |
89 | save the 32-bit registers on a context switch, so it is essential never | |
90 | to use the 64-bit registers. | |
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91 | |
92 | @item -mgp64 | |
93 | Assume that 64-bit general purpose registers are available. This is | |
94 | provided in the interests of symmetry with -gp32. | |
95 | ||
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96 | @item -mips16 |
97 | @itemx -no-mips16 | |
98 | Generate code for the MIPS 16 processor. This is equivalent to putting | |
99 | @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} | |
100 | turns off this option. | |
101 | ||
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102 | @item -mips3d |
103 | @itemx -no-mips3d | |
104 | Generate code for the MIPS-3D Application Specific Extension. | |
105 | This tells the assembler to accept MIPS-3D instructions. | |
106 | @samp{-no-mips3d} turns off this option. | |
107 | ||
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108 | @item -mfix7000 |
109 | @itemx -no-mfix7000 | |
110 | Cause nops to be inserted if the read of the destination register | |
111 | of an mfhi or mflo instruction occurs in the following two instructions. | |
112 | ||
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113 | @item -m4010 |
114 | @itemx -no-m4010 | |
115 | Generate code for the LSI @sc{r4010} chip. This tells the assembler to | |
116 | accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, | |
117 | etc.), and to not schedule @samp{nop} instructions around accesses to | |
118 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this | |
119 | option. | |
120 | ||
121 | @item -m4650 | |
122 | @itemx -no-m4650 | |
123 | Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept | |
124 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} | |
125 | instructions around accesses to the @samp{HI} and @samp{LO} registers. | |
126 | @samp{-no-m4650} turns off this option. | |
127 | ||
128 | @itemx -m3900 | |
129 | @itemx -no-m3900 | |
130 | @itemx -m4100 | |
131 | @itemx -no-m4100 | |
132 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS | |
133 | @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions | |
134 | specific to that chip, and to schedule for that chip's hazards. | |
135 | ||
ec68c924 | 136 | @item -march=@var{cpu} |
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137 | Generate code for a particular MIPS cpu. It is exactly equivalent to |
138 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} | |
139 | understood. Valid @var{cpu} value are: | |
140 | ||
141 | @quotation | |
142 | 2000, | |
143 | 3000, | |
144 | 3900, | |
145 | 4000, | |
146 | 4010, | |
147 | 4100, | |
148 | 4111, | |
149 | 4300, | |
150 | 4400, | |
151 | 4600, | |
152 | 4650, | |
153 | 5000, | |
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154 | rm5200, |
155 | rm5230, | |
156 | rm5231, | |
157 | rm5261, | |
158 | rm5721, | |
252b5132 | 159 | 6000, |
b946ec34 | 160 | rm7000, |
252b5132 | 161 | 8000, |
e7af610e | 162 | 10000, |
18ae5d72 | 163 | 12000, |
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164 | mips32-4k, |
165 | sb1 | |
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166 | @end quotation |
167 | ||
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168 | @item -mtune=@var{cpu} |
169 | Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are | |
170 | identical to @samp{-march=@var{cpu}}. | |
171 | ||
172 | @item -mcpu=@var{cpu} | |
173 | Generate code and schedule for a particular MIPS cpu. This is exactly | |
174 | equivalent to @samp{-march=@var{cpu}} and @samp{-mtune=@var{cpu}}. Valid | |
175 | @var{cpu} values are identical to @samp{-march=@var{cpu}}. | |
176 | Use of this option is discouraged. | |
177 | ||
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178 | |
179 | @cindex @code{-nocpp} ignored (MIPS) | |
180 | @item -nocpp | |
181 | This option is ignored. It is accepted for command-line compatibility with | |
182 | other assemblers, which use it to turn off C style preprocessing. With | |
183 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the | |
184 | @sc{gnu} assembler itself never runs the C preprocessor. | |
185 | ||
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186 | @item --construct-floats |
187 | @itemx --no-construct-floats | |
188 | @cindex --construct-floats | |
189 | @cindex --no-construct-floats | |
190 | The @code{--no-construct-floats} option disables the construction of | |
191 | double width floating point constants by loading the two halves of the | |
192 | value into the two single width floating point registers that make up | |
193 | the double width register. This feature is useful if the processor | |
194 | support the FR bit in its status register, and this bit is known (by | |
195 | the programmer) to be set. This bit prevents the aliasing of the double | |
196 | width register by the single width registers. | |
197 | ||
63bf5651 | 198 | By default @code{--construct-floats} is selected, allowing construction |
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199 | of these floating point constants. |
200 | ||
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201 | @item --trap |
202 | @itemx --no-break | |
203 | @c FIXME! (1) reflect these options (next item too) in option summaries; | |
204 | @c (2) stop teasing, say _which_ instructions expanded _how_. | |
205 | @code{@value{AS}} automatically macro expands certain division and | |
206 | multiplication instructions to check for overflow and division by zero. This | |
207 | option causes @code{@value{AS}} to generate code to take a trap exception | |
208 | rather than a break exception when an error is detected. The trap instructions | |
209 | are only supported at Instruction Set Architecture level 2 and higher. | |
210 | ||
211 | @item --break | |
212 | @itemx --no-trap | |
213 | Generate code to take a break exception rather than a trap exception when an | |
214 | error is detected. This is the default. | |
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215 | |
216 | @item -n | |
217 | When this option is used, @code{@value{AS}} will issue a warning every | |
218 | time it generates a nop instruction from a macro. | |
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219 | @end table |
220 | ||
221 | @node MIPS Object | |
222 | @section MIPS ECOFF object code | |
223 | ||
224 | @cindex ECOFF sections | |
225 | @cindex MIPS ECOFF sections | |
226 | Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections | |
227 | besides the usual @code{.text}, @code{.data} and @code{.bss}. The | |
228 | additional sections are @code{.rdata}, used for read-only data, | |
229 | @code{.sdata}, used for small data, and @code{.sbss}, used for small | |
230 | common objects. | |
231 | ||
232 | @cindex small objects, MIPS ECOFF | |
233 | @cindex @code{gp} register, MIPS | |
234 | When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) | |
235 | register to form the address of a ``small object''. Any object in the | |
236 | @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. | |
237 | For external objects, or for objects in the @code{.bss} section, you can use | |
238 | the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via | |
239 | @code{$gp}; the default value is 8, meaning that a reference to any object | |
240 | eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to | |
241 | @code{@value{AS}} prevents it from using the @code{$gp} register on the basis | |
242 | of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} | |
243 | or @code{sbss} in any case). The size of an object in the @code{.bss} section | |
244 | is set by the @code{.comm} or @code{.lcomm} directive that defines it. The | |
245 | size of an external object may be set with the @code{.extern} directive. For | |
246 | example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes | |
247 | in length, whie leaving @code{sym} otherwise undefined. | |
248 | ||
249 | Using small @sc{ecoff} objects requires linker support, and assumes that the | |
250 | @code{$gp} register is correctly initialized (normally done automatically by | |
251 | the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the | |
252 | @code{$gp} register. | |
253 | ||
254 | @node MIPS Stabs | |
255 | @section Directives for debugging information | |
256 | ||
257 | @cindex MIPS debugging directives | |
258 | @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for | |
259 | generating debugging information which are not support by traditional @sc{mips} | |
260 | assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, | |
261 | @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, | |
262 | @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information | |
263 | generated by the three @code{.stab} directives can only be read by @sc{gdb}, | |
264 | not by traditional @sc{mips} debuggers (this enhancement is required to fully | |
265 | support C++ debugging). These directives are primarily used by compilers, not | |
266 | assembly language programmers! | |
267 | ||
268 | @node MIPS ISA | |
269 | @section Directives to override the ISA level | |
270 | ||
271 | @cindex MIPS ISA override | |
272 | @kindex @code{.set mips@var{n}} | |
273 | @sc{gnu} @code{@value{AS}} supports an additional directive to change | |
274 | the @sc{mips} Instruction Set Architecture level on the fly: @code{.set | |
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275 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64. |
276 | The values 1 to 5, 32, and 64 make the assembler accept instructions | |
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277 | for the corresponding @sc{isa} level, from that point on in the |
278 | assembly. @code{.set mips@var{n}} affects not only which instructions | |
279 | are permitted, but also how certain macros are expanded. @code{.set | |
280 | mips0} restores the @sc{isa} level to its original level: either the | |
281 | level you selected with command line options, or the default for your | |
282 | configuration. You can use this feature to permit specific @sc{r4000} | |
283 | instructions while assembling in 32 bit mode. Use this directive with | |
ec68c924 | 284 | care! |
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285 | |
286 | The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, | |
287 | in which it will assemble instructions for the MIPS 16 processor. Use | |
288 | @samp{.set nomips16} to return to normal 32 bit mode. | |
289 | ||
ec68c924 | 290 | Traditional @sc{mips} assemblers do not support this directive. |
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291 | |
292 | @node MIPS autoextend | |
293 | @section Directives for extending MIPS 16 bit instructions | |
294 | ||
295 | @kindex @code{.set autoextend} | |
296 | @kindex @code{.set noautoextend} | |
297 | By default, MIPS 16 instructions are automatically extended to 32 bits | |
298 | when necessary. The directive @samp{.set noautoextend} will turn this | |
299 | off. When @samp{.set noautoextend} is in effect, any 32 bit instruction | |
300 | must be explicitly extended with the @samp{.e} modifier (e.g., | |
301 | @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used | |
302 | to once again automatically extend instructions when necessary. | |
303 | ||
304 | This directive is only meaningful when in MIPS 16 mode. Traditional | |
305 | @sc{mips} assemblers do not support this directive. | |
306 | ||
307 | @node MIPS insn | |
308 | @section Directive to mark data as an instruction | |
309 | ||
310 | @kindex @code{.insn} | |
311 | The @code{.insn} directive tells @code{@value{AS}} that the following | |
312 | data is actually instructions. This makes a difference in MIPS 16 mode: | |
313 | when loading the address of a label which precedes instructions, | |
314 | @code{@value{AS}} automatically adds 1 to the value, so that jumping to | |
315 | the loaded address will do the right thing. | |
316 | ||
317 | @node MIPS option stack | |
318 | @section Directives to save and restore options | |
319 | ||
320 | @cindex MIPS option stack | |
321 | @kindex @code{.set push} | |
322 | @kindex @code{.set pop} | |
323 | The directives @code{.set push} and @code{.set pop} may be used to save | |
324 | and restore the current settings for all the options which are | |
325 | controlled by @code{.set}. The @code{.set push} directive saves the | |
326 | current settings on a stack. The @code{.set pop} directive pops the | |
327 | stack and restores the settings. | |
328 | ||
329 | These directives can be useful inside an macro which must change an | |
330 | option such as the ISA level or instruction reordering but does not want | |
331 | to change the state of the code which invoked the macro. | |
332 | ||
333 | Traditional @sc{mips} assemblers do not support these directives. | |
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334 | |
335 | @node MIPS ASE instruction generation overrides | |
336 | @section Directives to control generation of MIPS ASE instructions | |
337 | ||
338 | @cindex MIPS MIPS-3D instruction generation override | |
339 | @kindex @code{.set mips3d} | |
340 | @kindex @code{.set nomips3d} | |
341 | The directive @code{.set mips3d} makes the assembler accept instructions | |
342 | from the MIPS-3D Application Specific Extension from that point on | |
343 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D | |
344 | instructions from being accepted. | |
345 | ||
346 | Traditional @sc{mips} assemblers do not support these directives. |