x86: improve handling of insns with ambiguous operand sizes
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / sse-noavx.s
CommitLineData
9ba52a26
L
1# Check SSE instructions without AVX equivalent
2
3 .text
4_start:
5 crc32 %cl,%ebx
cbc80391
L
6 cvtpd2pi %xmm3,%mm2
7 cvtpi2pd %mm3,%xmm2
9ba52a26
L
8 cvtpi2ps %mm3,%xmm2
9 cvtps2pi %xmm7,%mm6
cbc80391 10 cvttpd2pi %xmm4,%mm3
9ba52a26 11 cvttps2pi %xmm4,%mm3
8e2495f2
L
12 fisttps (%eax)
13 fisttpl (%eax)
9ba52a26 14 fisttpll (%eax)
c1ec1875 15 lfence
9ba52a26 16 maskmovq %mm7,%mm0
c1ec1875 17 mfence
9ba52a26 18 monitor
d9479f2d 19 movdq2q %xmm0, %mm1
c1ec1875 20 movnti %eax, (%eax)
9ba52a26 21 movntq %mm2,(%eax)
d9479f2d 22 movq2dq %mm0, %xmm1
9ba52a26
L
23 mwait
24 pabsb %mm1,%mm0
25 pabsd %mm1,%mm0
26 pabsw %mm1,%mm0
27 paddq %mm1,%mm0
28 palignr $0x2,%mm1,%mm0
29 pavgb %mm1,%mm0
30 pavgw %mm3,%mm2
31 pextrw $0x0,%mm1,%eax
32 phaddd %mm1,%mm0
33 phaddsw %mm1,%mm0
34 phaddw %mm1,%mm0
35 phsubd %mm1,%mm0
36 phsubsw %mm1,%mm0
37 phsubw %mm1,%mm0
38 pinsrw $0x2,%edx,%mm2
39 pmaddubsw %mm1,%mm0
40 pmaxsw %mm1,%mm0
41 pmaxub %mm2,%mm2
42 pminsw %mm5,%mm4
43 pminub %mm7,%mm6
44 pmovmskb %mm5,%eax
45 pmulhrsw %mm1,%mm0
46 pmulhuw %mm5,%mm4
47 pmuludq %mm0, %mm1
48 popcnt %ebx,%ecx
49 prefetchnta (%eax)
50 prefetcht0 (%eax)
51 prefetcht1 (%eax)
52 prefetcht2 (%eax)
53 psadbw %mm7,%mm6
54 pshufb %mm1,%mm0
55 pshufw $0x1,%mm2,%mm3
56 psignb %mm1,%mm0
57 psignd %mm1,%mm0
58 psignw %mm1,%mm0
59 psubq %mm1,%mm0
60 sfence
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