x86: improve handling of insns with ambiguous operand sizes
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-ptwrite-intel.d
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6b40c462
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1#as:
2#objdump: -dw -Mintel
3#name: x86_64 PTWRITE insns (Intel disassembly)
4#source: x86-64-ptwrite.s
5
6.*: +file format .*
7
8
9Disassembly of section \.text:
10
110+ <_start>:
12 +[a-f0-9]+: f3 0f ae e1 ptwrite ecx
13 +[a-f0-9]+: f3 0f ae e1 ptwrite ecx
14 +[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
15 +[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
16 +[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[rcx\]
6b40c462
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17 +[a-f0-9]+: f3 48 0f ae 21 ptwrite QWORD PTR \[rcx\]
18 +[a-f0-9]+: f3 0f ae e1 ptwrite ecx
19 +[a-f0-9]+: f3 48 0f ae e1 ptwrite rcx
20 +[a-f0-9]+: f3 0f ae 21 ptwrite DWORD PTR \[rcx\]
21 +[a-f0-9]+: f3 48 0f ae 21 ptwrite QWORD PTR \[rcx\]
22#pass
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