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[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c
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07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
e2882c85 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
24#include "inferior.h"
25#include "gdbcmd.h"
26#include "gdbcore.h"
07b287a0
MS		 27#include "dis-asm.h"
28#include "regcache.h"
29#include "reggroups.h"
07b287a0
MS		 30#include "value.h"
31#include "arch-utils.h"
32#include "osabi.h"
33#include "frame-unwind.h"
34#include "frame-base.h"
35#include "trad-frame.h"
36#include "objfiles.h"
37#include "dwarf2-frame.h"
38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
41#include "user-regs.h"
42#include "language.h"
43#include "infcall.h"
ea873d8e
PL		 44#include "ax.h"
45#include "ax-gdb.h"
4d9a9006 46#include "selftest.h"
07b287a0
MS		 47
48#include "aarch64-tdep.h"
49
50#include "elf-bfd.h"
51#include "elf/aarch64.h"
52
07b287a0
MS		 53#include "vec.h"
54
99afc88b
OJ		 55#include "record.h"
56#include "record-full.h"
787749ea
PL		 57#include "arch/aarch64-insn.h"
58
f77ee802 59#include "opcode/aarch64.h"
325fac50 60#include <algorithm>
f77ee802
YQ		 61
62#define submask(x) ((1L << ((x) + 1)) - 1)
63#define bit(obj,st) (((obj) >> (st)) & 1)
64#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
65
07b287a0
MS		 66/* Pseudo register base numbers. */
67#define AARCH64_Q0_REGNUM 0
187f5d00 68#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
07b287a0
MS		 69#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
70#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
71#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
72
73/* The standard register names, and all the valid aliases for them. */
74static const struct
75{
76 const char *const name;
77 int regnum;
78} aarch64_register_aliases[] =
79{
80 /* 64-bit register names. */
81 {"fp", AARCH64_FP_REGNUM},
82 {"lr", AARCH64_LR_REGNUM},
83 {"sp", AARCH64_SP_REGNUM},
84
85 /* 32-bit register names. */
86 {"w0", AARCH64_X0_REGNUM + 0},
87 {"w1", AARCH64_X0_REGNUM + 1},
88 {"w2", AARCH64_X0_REGNUM + 2},
89 {"w3", AARCH64_X0_REGNUM + 3},
90 {"w4", AARCH64_X0_REGNUM + 4},
91 {"w5", AARCH64_X0_REGNUM + 5},
92 {"w6", AARCH64_X0_REGNUM + 6},
93 {"w7", AARCH64_X0_REGNUM + 7},
94 {"w8", AARCH64_X0_REGNUM + 8},
95 {"w9", AARCH64_X0_REGNUM + 9},
96 {"w10", AARCH64_X0_REGNUM + 10},
97 {"w11", AARCH64_X0_REGNUM + 11},
98 {"w12", AARCH64_X0_REGNUM + 12},
99 {"w13", AARCH64_X0_REGNUM + 13},
100 {"w14", AARCH64_X0_REGNUM + 14},
101 {"w15", AARCH64_X0_REGNUM + 15},
102 {"w16", AARCH64_X0_REGNUM + 16},
103 {"w17", AARCH64_X0_REGNUM + 17},
104 {"w18", AARCH64_X0_REGNUM + 18},
105 {"w19", AARCH64_X0_REGNUM + 19},
106 {"w20", AARCH64_X0_REGNUM + 20},
107 {"w21", AARCH64_X0_REGNUM + 21},
108 {"w22", AARCH64_X0_REGNUM + 22},
109 {"w23", AARCH64_X0_REGNUM + 23},
110 {"w24", AARCH64_X0_REGNUM + 24},
111 {"w25", AARCH64_X0_REGNUM + 25},
112 {"w26", AARCH64_X0_REGNUM + 26},
113 {"w27", AARCH64_X0_REGNUM + 27},
114 {"w28", AARCH64_X0_REGNUM + 28},
115 {"w29", AARCH64_X0_REGNUM + 29},
116 {"w30", AARCH64_X0_REGNUM + 30},
117
118 /* specials */
119 {"ip0", AARCH64_X0_REGNUM + 16},
120 {"ip1", AARCH64_X0_REGNUM + 17}
121};
122
123/* The required core 'R' registers. */
124static const char *const aarch64_r_register_names[] =
125{
126 /* These registers must appear in consecutive RAW register number
127 order and they must begin with AARCH64_X0_REGNUM! */
128 "x0", "x1", "x2", "x3",
129 "x4", "x5", "x6", "x7",
130 "x8", "x9", "x10", "x11",
131 "x12", "x13", "x14", "x15",
132 "x16", "x17", "x18", "x19",
133 "x20", "x21", "x22", "x23",
134 "x24", "x25", "x26", "x27",
135 "x28", "x29", "x30", "sp",
136 "pc", "cpsr"
137};
138
139/* The FP/SIMD 'V' registers. */
140static const char *const aarch64_v_register_names[] =
141{
142 /* These registers must appear in consecutive RAW register number
143 order and they must begin with AARCH64_V0_REGNUM! */
144 "v0", "v1", "v2", "v3",
145 "v4", "v5", "v6", "v7",
146 "v8", "v9", "v10", "v11",
147 "v12", "v13", "v14", "v15",
148 "v16", "v17", "v18", "v19",
149 "v20", "v21", "v22", "v23",
150 "v24", "v25", "v26", "v27",
151 "v28", "v29", "v30", "v31",
152 "fpsr",
153 "fpcr"
154};
155
156/* AArch64 prologue cache structure. */
157struct aarch64_prologue_cache
158{
db634143
PL		 159 /* The program counter at the start of the function. It is used to
160 identify this frame as a prologue frame. */
161 CORE_ADDR func;
162
163 /* The program counter at the time this frame was created; i.e. where
164 this function was called from. It is used to identify this frame as a
165 stub frame. */
166 CORE_ADDR prev_pc;
167
07b287a0
MS		 168 /* The stack pointer at the time this frame was created; i.e. the
169 caller's stack pointer when this function was called. It is used
170 to identify this frame. */
171 CORE_ADDR prev_sp;
172
7dfa3edc
PL		 173 /* Is the target available to read from? */
174 int available_p;
175
07b287a0
MS		 176 /* The frame base for this frame is just prev_sp - frame size.
177 FRAMESIZE is the distance from the frame pointer to the
178 initial stack pointer. */
179 int framesize;
180
181 /* The register used to hold the frame pointer for this frame. */
182 int framereg;
183
184 /* Saved register offsets. */
185 struct trad_frame_saved_reg *saved_regs;
186};
187
07b287a0
MS		 188static void
189show_aarch64_debug (struct ui_file *file, int from_tty,
190 struct cmd_list_element *c, const char *value)
191{
192 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
193}
194
ffdbe864
YQ		 195namespace {
196
4d9a9006
YQ		 197/* Abstract instruction reader. */
198
199class abstract_instruction_reader
200{
201public:
202 /* Read in one instruction. */
203 virtual ULONGEST read (CORE_ADDR memaddr, int len,
204 enum bfd_endian byte_order) = 0;
205};
206
207/* Instruction reader from real target. */
208
209class instruction_reader : public abstract_instruction_reader
210{
211 public:
212 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 213 override
4d9a9006 214 {
fc2f703e 215 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 216 }
217};
218
ffdbe864
YQ		 219} // namespace
220
07b287a0
MS		 221/* Analyze a prologue, looking for a recognizable stack frame
222 and frame pointer. Scan until we encounter a store that could
223 clobber the stack frame unexpectedly, or an unknown instruction. */
224
225static CORE_ADDR
226aarch64_analyze_prologue (struct gdbarch *gdbarch,
227 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 228 struct aarch64_prologue_cache *cache,
229 abstract_instruction_reader& reader)
07b287a0
MS		 230{
231 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
232 int i;
187f5d00
YQ		 233 /* Track X registers and D registers in prologue. */
234 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 235
187f5d00 236 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 237 regs[i] = pv_register (i, 0);
f7b7ed97 238 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 239
240 for (; start < limit; start += 4)
241 {
242 uint32_t insn;
d9ebcbce 243 aarch64_inst inst;
07b287a0 244
4d9a9006 245 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 246
d9ebcbce
YQ		 247 if (aarch64_decode_insn (insn, &inst, 1) != 0)
248 break;
249
250 if (inst.opcode->iclass == addsub_imm
251 && (inst.opcode->op == OP_ADD
252 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 253 {
d9ebcbce
YQ		 254 unsigned rd = inst.operands[0].reg.regno;
255 unsigned rn = inst.operands[1].reg.regno;
256
257 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
258 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
259 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
260 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
261
262 if (inst.opcode->op == OP_ADD)
263 {
264 regs[rd] = pv_add_constant (regs[rn],
265 inst.operands[2].imm.value);
266 }
267 else
268 {
269 regs[rd] = pv_add_constant (regs[rn],
270 -inst.operands[2].imm.value);
271 }
272 }
273 else if (inst.opcode->iclass == pcreladdr
274 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
275 {
276 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
277 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
278
279 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 280 }
d9ebcbce 281 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 282 {
283 /* Stop analysis on branch. */
284 break;
285 }
d9ebcbce 286 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 287 {
288 /* Stop analysis on branch. */
289 break;
290 }
d9ebcbce 291 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 292 {
293 /* Stop analysis on branch. */
294 break;
295 }
d9ebcbce 296 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 297 {
298 /* Stop analysis on branch. */
299 break;
300 }
d9ebcbce
YQ		 301 else if (inst.opcode->op == OP_MOVZ)
302 {
303 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
304 regs[inst.operands[0].reg.regno] = pv_unknown ();
305 }
306 else if (inst.opcode->iclass == log_shift
307 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 308 {
d9ebcbce
YQ		 309 unsigned rd = inst.operands[0].reg.regno;
310 unsigned rn = inst.operands[1].reg.regno;
311 unsigned rm = inst.operands[2].reg.regno;
312
313 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
314 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
315 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
316
317 if (inst.operands[2].shifter.amount == 0
318 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 319 regs[rd] = regs[rm];
320 else
321 {
322 if (aarch64_debug)
b277c936
PL		 323 {
324 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 325 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 326 core_addr_to_string_nz (start), insn);
327 }
07b287a0
MS		 328 break;
329 }
330 }
d9ebcbce 331 else if (inst.opcode->op == OP_STUR)
07b287a0 332 {
d9ebcbce
YQ		 333 unsigned rt = inst.operands[0].reg.regno;
334 unsigned rn = inst.operands[1].addr.base_regno;
335 int is64
336 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
337
338 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
339 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
340 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
341 gdb_assert (!inst.operands[1].addr.offset.is_reg);
342
f7b7ed97
TT		 343 stack.store (pv_add_constant (regs[rn],
344 inst.operands[1].addr.offset.imm),
345 is64 ? 8 : 4, regs[rt]);
07b287a0 346 }
d9ebcbce 347 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 348 || (inst.opcode->iclass == ldstpair_indexed
349 && inst.operands[2].addr.preind))
d9ebcbce 350 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 351 {
03bcd739 352 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 353 unsigned rt1;
354 unsigned rt2;
d9ebcbce
YQ		 355 unsigned rn = inst.operands[2].addr.base_regno;
356 int32_t imm = inst.operands[2].addr.offset.imm;
357
187f5d00
YQ		 358 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
359 || inst.operands[0].type == AARCH64_OPND_Ft);
360 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
361 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 362 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
363 gdb_assert (!inst.operands[2].addr.offset.is_reg);
364
07b287a0
MS		 365 /* If recording this store would invalidate the store area
366 (perhaps because rn is not known) then we should abandon
367 further prologue analysis. */
f7b7ed97 368 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 369 break;
370
f7b7ed97 371 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 372 break;
373
187f5d00
YQ		 374 rt1 = inst.operands[0].reg.regno;
375 rt2 = inst.operands[1].reg.regno;
376 if (inst.operands[0].type == AARCH64_OPND_Ft)
377 {
378 /* Only bottom 64-bit of each V register (D register) need
379 to be preserved. */
380 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
381 rt1 += AARCH64_X_REGISTER_COUNT;
382 rt2 += AARCH64_X_REGISTER_COUNT;
383 }
384
f7b7ed97
TT		 385 stack.store (pv_add_constant (regs[rn], imm), 8,
386 regs[rt1]);
387 stack.store (pv_add_constant (regs[rn], imm + 8), 8,
388 regs[rt2]);
14ac654f 389
d9ebcbce 390 if (inst.operands[2].addr.writeback)
93d96012 391 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 392
07b287a0 393 }
432ec081
YQ		 394 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
395 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
396 && (inst.opcode->op == OP_STR_POS
397 || inst.opcode->op == OP_STRF_POS)))
398 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
399 && strcmp ("str", inst.opcode->name) == 0)
400 {
401 /* STR (immediate) */
402 unsigned int rt = inst.operands[0].reg.regno;
403 int32_t imm = inst.operands[1].addr.offset.imm;
404 unsigned int rn = inst.operands[1].addr.base_regno;
405 bool is64
406 = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
407 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
408 || inst.operands[0].type == AARCH64_OPND_Ft);
409
410 if (inst.operands[0].type == AARCH64_OPND_Ft)
411 {
412 /* Only bottom 64-bit of each V register (D register) need
413 to be preserved. */
414 gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
415 rt += AARCH64_X_REGISTER_COUNT;
416 }
417
f7b7ed97
TT		 418 stack.store (pv_add_constant (regs[rn], imm),
419 is64 ? 8 : 4, regs[rt]);
432ec081
YQ		 420 if (inst.operands[1].addr.writeback)
421 regs[rn] = pv_add_constant (regs[rn], imm);
422 }
d9ebcbce 423 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 424 {
425 /* Stop analysis on branch. */
426 break;
427 }
428 else
429 {
430 if (aarch64_debug)
b277c936 431 {
0a0da556 432 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 433 " opcode=0x%x\n",
434 core_addr_to_string_nz (start), insn);
435 }
07b287a0
MS		 436 break;
437 }
438 }
439
440 if (cache == NULL)
f7b7ed97 441 return start;
07b287a0
MS		 442
443 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
444 {
445 /* Frame pointer is fp. Frame size is constant. */
446 cache->framereg = AARCH64_FP_REGNUM;
447 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
448 }
449 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
450 {
451 /* Try the stack pointer. */
452 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
453 cache->framereg = AARCH64_SP_REGNUM;
454 }
455 else
456 {
457 /* We're just out of luck. We don't know where the frame is. */
458 cache->framereg = -1;
459 cache->framesize = 0;
460 }
461
462 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
463 {
464 CORE_ADDR offset;
465
f7b7ed97 466 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 467 cache->saved_regs[i].addr = offset;
468 }
469
187f5d00
YQ		 470 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
471 {
472 int regnum = gdbarch_num_regs (gdbarch);
473 CORE_ADDR offset;
474
f7b7ed97
TT		 475 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
476 &offset))
187f5d00
YQ		 477 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
478 }
479
07b287a0
MS		 480 return start;
481}
482
4d9a9006
YQ		 483static CORE_ADDR
484aarch64_analyze_prologue (struct gdbarch *gdbarch,
485 CORE_ADDR start, CORE_ADDR limit,
486 struct aarch64_prologue_cache *cache)
487{
488 instruction_reader reader;
489
490 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
491 reader);
492}
493
494#if GDB_SELF_TEST
495
496namespace selftests {
497
498/* Instruction reader from manually cooked instruction sequences. */
499
500class instruction_reader_test : public abstract_instruction_reader
501{
502public:
503 template<size_t SIZE>
504 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
505 : m_insns (insns), m_insns_size (SIZE)
506 {}
507
508 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 509 override
4d9a9006
YQ		 510 {
511 SELF_CHECK (len == 4);
512 SELF_CHECK (memaddr % 4 == 0);
513 SELF_CHECK (memaddr / 4 < m_insns_size);
514
515 return m_insns[memaddr / 4];
516 }
517
518private:
519 const uint32_t *m_insns;
520 size_t m_insns_size;
521};
522
523static void
524aarch64_analyze_prologue_test (void)
525{
526 struct gdbarch_info info;
527
528 gdbarch_info_init (&info);
529 info.bfd_arch_info = bfd_scan_arch ("aarch64");
530
531 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
532 SELF_CHECK (gdbarch != NULL);
533
534 /* Test the simple prologue in which frame pointer is used. */
535 {
536 struct aarch64_prologue_cache cache;
537 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
538
539 static const uint32_t insns[] = {
540 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
541 0x910003fd, /* mov x29, sp */
542 0x97ffffe6, /* bl 0x400580 */
543 };
544 instruction_reader_test reader (insns);
545
546 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
547 SELF_CHECK (end == 4 * 2);
548
549 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
550 SELF_CHECK (cache.framesize == 272);
551
552 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
553 {
554 if (i == AARCH64_FP_REGNUM)
555 SELF_CHECK (cache.saved_regs[i].addr == -272);
556 else if (i == AARCH64_LR_REGNUM)
557 SELF_CHECK (cache.saved_regs[i].addr == -264);
558 else
559 SELF_CHECK (cache.saved_regs[i].addr == -1);
560 }
561
562 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
563 {
564 int regnum = gdbarch_num_regs (gdbarch);
565
566 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
567 == -1);
568 }
569 }
432ec081
YQ		 570
571 /* Test a prologue in which STR is used and frame pointer is not
572 used. */
573 {
574 struct aarch64_prologue_cache cache;
575 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
576
577 static const uint32_t insns[] = {
578 0xf81d0ff3, /* str x19, [sp, #-48]! */
579 0xb9002fe0, /* str w0, [sp, #44] */
580 0xf90013e1, /* str x1, [sp, #32]*/
581 0xfd000fe0, /* str d0, [sp, #24] */
582 0xaa0203f3, /* mov x19, x2 */
583 0xf94013e0, /* ldr x0, [sp, #32] */
584 };
585 instruction_reader_test reader (insns);
586
587 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
588
589 SELF_CHECK (end == 4 * 5);
590
591 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
592 SELF_CHECK (cache.framesize == 48);
593
594 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
595 {
596 if (i == 1)
597 SELF_CHECK (cache.saved_regs[i].addr == -16);
598 else if (i == 19)
599 SELF_CHECK (cache.saved_regs[i].addr == -48);
600 else
601 SELF_CHECK (cache.saved_regs[i].addr == -1);
602 }
603
604 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
605 {
606 int regnum = gdbarch_num_regs (gdbarch);
607
608 if (i == 0)
609 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
610 == -24);
611 else
612 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
613 == -1);
614 }
615 }
4d9a9006
YQ		 616}
617} // namespace selftests
618#endif /* GDB_SELF_TEST */
619
07b287a0
MS		 620/* Implement the "skip_prologue" gdbarch method. */
621
622static CORE_ADDR
623aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
624{
07b287a0 625 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 626
627 /* See if we can determine the end of the prologue via the symbol
628 table. If so, then return either PC, or the PC after the
629 prologue, whichever is greater. */
630 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
631 {
632 CORE_ADDR post_prologue_pc
633 = skip_prologue_using_sal (gdbarch, func_addr);
634
635 if (post_prologue_pc != 0)
325fac50 636 return std::max (pc, post_prologue_pc);
07b287a0
MS		 637 }
638
639 /* Can't determine prologue from the symbol table, need to examine
640 instructions. */
641
642 /* Find an upper limit on the function prologue using the debug
643 information. If the debug information could not be used to
644 provide that bound, then use an arbitrary large number as the
645 upper bound. */
646 limit_pc = skip_prologue_using_sal (gdbarch, pc);
647 if (limit_pc == 0)
648 limit_pc = pc + 128; /* Magic. */
649
650 /* Try disassembling prologue. */
651 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
652}
653
654/* Scan the function prologue for THIS_FRAME and populate the prologue
655 cache CACHE. */
656
657static void
658aarch64_scan_prologue (struct frame_info *this_frame,
659 struct aarch64_prologue_cache *cache)
660{
661 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
662 CORE_ADDR prologue_start;
663 CORE_ADDR prologue_end;
664 CORE_ADDR prev_pc = get_frame_pc (this_frame);
665 struct gdbarch *gdbarch = get_frame_arch (this_frame);
666
db634143
PL		 667 cache->prev_pc = prev_pc;
668
07b287a0
MS		 669 /* Assume we do not find a frame. */
670 cache->framereg = -1;
671 cache->framesize = 0;
672
673 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
674 &prologue_end))
675 {
676 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
677
678 if (sal.line == 0)
679 {
680 /* No line info so use the current PC. */
681 prologue_end = prev_pc;
682 }
683 else if (sal.end < prologue_end)
684 {
685 /* The next line begins after the function end. */
686 prologue_end = sal.end;
687 }
688
325fac50 689 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 690 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
691 }
692 else
693 {
694 CORE_ADDR frame_loc;
07b287a0
MS		 695
696 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
697 if (frame_loc == 0)
698 return;
699
700 cache->framereg = AARCH64_FP_REGNUM;
701 cache->framesize = 16;
702 cache->saved_regs[29].addr = 0;
703 cache->saved_regs[30].addr = 8;
704 }
705}
706
7dfa3edc
PL		 707/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
708 function may throw an exception if the inferior's registers or memory is
709 not available. */
07b287a0 710
7dfa3edc
PL		 711static void
712aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
713 struct aarch64_prologue_cache *cache)
07b287a0 714{
07b287a0
MS		 715 CORE_ADDR unwound_fp;
716 int reg;
717
07b287a0
MS		 718 aarch64_scan_prologue (this_frame, cache);
719
720 if (cache->framereg == -1)
7dfa3edc 721 return;
07b287a0
MS		 722
723 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
724 if (unwound_fp == 0)
7dfa3edc 725 return;
07b287a0
MS		 726
727 cache->prev_sp = unwound_fp + cache->framesize;
728
729 /* Calculate actual addresses of saved registers using offsets
730 determined by aarch64_analyze_prologue. */
731 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
732 if (trad_frame_addr_p (cache->saved_regs, reg))
733 cache->saved_regs[reg].addr += cache->prev_sp;
734
db634143
PL		 735 cache->func = get_frame_func (this_frame);
736
7dfa3edc
PL		 737 cache->available_p = 1;
738}
739
740/* Allocate and fill in *THIS_CACHE with information about the prologue of
741 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
742 Return a pointer to the current aarch64_prologue_cache in
743 *THIS_CACHE. */
744
745static struct aarch64_prologue_cache *
746aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
747{
748 struct aarch64_prologue_cache *cache;
749
750 if (*this_cache != NULL)
9a3c8263 751 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 752
753 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
754 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
755 *this_cache = cache;
756
757 TRY
758 {
759 aarch64_make_prologue_cache_1 (this_frame, cache);
760 }
761 CATCH (ex, RETURN_MASK_ERROR)
762 {
763 if (ex.error != NOT_AVAILABLE_ERROR)
764 throw_exception (ex);
765 }
766 END_CATCH
767
07b287a0
MS		 768 return cache;
769}
770
7dfa3edc
PL		 771/* Implement the "stop_reason" frame_unwind method. */
772
773static enum unwind_stop_reason
774aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
775 void **this_cache)
776{
777 struct aarch64_prologue_cache *cache
778 = aarch64_make_prologue_cache (this_frame, this_cache);
779
780 if (!cache->available_p)
781 return UNWIND_UNAVAILABLE;
782
783 /* Halt the backtrace at "_start". */
784 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
785 return UNWIND_OUTERMOST;
786
787 /* We've hit a wall, stop. */
788 if (cache->prev_sp == 0)
789 return UNWIND_OUTERMOST;
790
791 return UNWIND_NO_REASON;
792}
793
07b287a0
MS		 794/* Our frame ID for a normal frame is the current function's starting
795 PC and the caller's SP when we were called. */
796
797static void
798aarch64_prologue_this_id (struct frame_info *this_frame,
799 void **this_cache, struct frame_id *this_id)
800{
7c8edfae
PL		 801 struct aarch64_prologue_cache *cache
802 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 803
7dfa3edc
PL		 804 if (!cache->available_p)
805 *this_id = frame_id_build_unavailable_stack (cache->func);
806 else
807 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 808}
809
810/* Implement the "prev_register" frame_unwind method. */
811
812static struct value *
813aarch64_prologue_prev_register (struct frame_info *this_frame,
814 void **this_cache, int prev_regnum)
815{
7c8edfae
PL		 816 struct aarch64_prologue_cache *cache
817 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 818
819 /* If we are asked to unwind the PC, then we need to return the LR
820 instead. The prologue may save PC, but it will point into this
821 frame's prologue, not the next frame's resume location. */
822 if (prev_regnum == AARCH64_PC_REGNUM)
823 {
824 CORE_ADDR lr;
825
826 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
827 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
828 }
829
830 /* SP is generally not saved to the stack, but this frame is
831 identified by the next frame's stack pointer at the time of the
832 call. The value was already reconstructed into PREV_SP. */
833 /*
834 +----------+ ^
835 | saved lr | |
836 +->| saved fp |--+
837 | | |
838 | | | <- Previous SP
839 | +----------+
840 | | saved lr |
841 +--| saved fp |<- FP
842 | |
843 | |<- SP
844 +----------+ */
845 if (prev_regnum == AARCH64_SP_REGNUM)
846 return frame_unwind_got_constant (this_frame, prev_regnum,
847 cache->prev_sp);
848
849 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
850 prev_regnum);
851}
852
853/* AArch64 prologue unwinder. */
854struct frame_unwind aarch64_prologue_unwind =
855{
856 NORMAL_FRAME,
7dfa3edc 857 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 858 aarch64_prologue_this_id,
859 aarch64_prologue_prev_register,
860 NULL,
861 default_frame_sniffer
862};
863
8b61f75d
PL		 864/* Allocate and fill in *THIS_CACHE with information about the prologue of
865 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
866 Return a pointer to the current aarch64_prologue_cache in
867 *THIS_CACHE. */
07b287a0
MS		 868
869static struct aarch64_prologue_cache *
8b61f75d 870aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 871{
07b287a0 872 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 873
874 if (*this_cache != NULL)
9a3c8263 875 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 876
877 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
878 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 879 *this_cache = cache;
07b287a0 880
02a2a705
PL		 881 TRY
882 {
883 cache->prev_sp = get_frame_register_unsigned (this_frame,
884 AARCH64_SP_REGNUM);
885 cache->prev_pc = get_frame_pc (this_frame);
886 cache->available_p = 1;
887 }
888 CATCH (ex, RETURN_MASK_ERROR)
889 {
890 if (ex.error != NOT_AVAILABLE_ERROR)
891 throw_exception (ex);
892 }
893 END_CATCH
07b287a0
MS		 894
895 return cache;
896}
897
02a2a705
PL		 898/* Implement the "stop_reason" frame_unwind method. */
899
900static enum unwind_stop_reason
901aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
902 void **this_cache)
903{
904 struct aarch64_prologue_cache *cache
905 = aarch64_make_stub_cache (this_frame, this_cache);
906
907 if (!cache->available_p)
908 return UNWIND_UNAVAILABLE;
909
910 return UNWIND_NO_REASON;
911}
912
07b287a0
MS		 913/* Our frame ID for a stub frame is the current SP and LR. */
914
915static void
916aarch64_stub_this_id (struct frame_info *this_frame,
917 void **this_cache, struct frame_id *this_id)
918{
8b61f75d
PL		 919 struct aarch64_prologue_cache *cache
920 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 921
02a2a705
PL		 922 if (cache->available_p)
923 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
924 else
925 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 926}
927
928/* Implement the "sniffer" frame_unwind method. */
929
930static int
931aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
932 struct frame_info *this_frame,
933 void **this_prologue_cache)
934{
935 CORE_ADDR addr_in_block;
936 gdb_byte dummy[4];
937
938 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 939 if (in_plt_section (addr_in_block)
07b287a0
MS		 940 /* We also use the stub winder if the target memory is unreadable
941 to avoid having the prologue unwinder trying to read it. */
942 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
943 return 1;
944
945 return 0;
946}
947
948/* AArch64 stub unwinder. */
949struct frame_unwind aarch64_stub_unwind =
950{
951 NORMAL_FRAME,
02a2a705 952 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 953 aarch64_stub_this_id,
954 aarch64_prologue_prev_register,
955 NULL,
956 aarch64_stub_unwind_sniffer
957};
958
959/* Return the frame base address of *THIS_FRAME. */
960
961static CORE_ADDR
962aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
963{
7c8edfae
PL		 964 struct aarch64_prologue_cache *cache
965 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 966
967 return cache->prev_sp - cache->framesize;
968}
969
970/* AArch64 default frame base information. */
971struct frame_base aarch64_normal_base =
972{
973 &aarch64_prologue_unwind,
974 aarch64_normal_frame_base,
975 aarch64_normal_frame_base,
976 aarch64_normal_frame_base
977};
978
979/* Assuming THIS_FRAME is a dummy, return the frame ID of that
980 dummy frame. The frame ID's base needs to match the TOS value
981 saved by save_dummy_frame_tos () and returned from
982 aarch64_push_dummy_call, and the PC needs to match the dummy
983 frame's breakpoint. */
984
985static struct frame_id
986aarch64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
987{
988 return frame_id_build (get_frame_register_unsigned (this_frame,
989 AARCH64_SP_REGNUM),
990 get_frame_pc (this_frame));
991}
992
993/* Implement the "unwind_pc" gdbarch method. */
994
995static CORE_ADDR
996aarch64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
997{
998 CORE_ADDR pc
999 = frame_unwind_register_unsigned (this_frame, AARCH64_PC_REGNUM);
1000
1001 return pc;
1002}
1003
1004/* Implement the "unwind_sp" gdbarch method. */
1005
1006static CORE_ADDR
1007aarch64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1008{
1009 return frame_unwind_register_unsigned (this_frame, AARCH64_SP_REGNUM);
1010}
1011
1012/* Return the value of the REGNUM register in the previous frame of
1013 *THIS_FRAME. */
1014
1015static struct value *
1016aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1017 void **this_cache, int regnum)
1018{
07b287a0
MS		 1019 CORE_ADDR lr;
1020
1021 switch (regnum)
1022 {
1023 case AARCH64_PC_REGNUM:
1024 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
1025 return frame_unwind_got_constant (this_frame, regnum, lr);
1026
1027 default:
1028 internal_error (__FILE__, __LINE__,
1029 _("Unexpected register %d"), regnum);
1030 }
1031}
1032
1033/* Implement the "init_reg" dwarf2_frame_ops method. */
1034
1035static void
1036aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1037 struct dwarf2_frame_state_reg *reg,
1038 struct frame_info *this_frame)
1039{
1040 switch (regnum)
1041 {
1042 case AARCH64_PC_REGNUM:
1043 reg->how = DWARF2_FRAME_REG_FN;
1044 reg->loc.fn = aarch64_dwarf2_prev_register;
1045 break;
1046 case AARCH64_SP_REGNUM:
1047 reg->how = DWARF2_FRAME_REG_CFA;
1048 break;
1049 }
1050}
1051
1052/* When arguments must be pushed onto the stack, they go on in reverse
1053 order. The code below implements a FILO (stack) to do this. */
1054
1055typedef struct
1056{
c3c87445
YQ		 1057 /* Value to pass on stack. It can be NULL if this item is for stack
1058 padding. */
7c543f7b 1059 const gdb_byte *data;
07b287a0
MS		 1060
1061 /* Size in bytes of value to pass on stack. */
1062 int len;
1063} stack_item_t;
1064
1065DEF_VEC_O (stack_item_t);
1066
1067/* Return the alignment (in bytes) of the given type. */
1068
1069static int
1070aarch64_type_align (struct type *t)
1071{
1072 int n;
1073 int align;
1074 int falign;
1075
1076 t = check_typedef (t);
1077 switch (TYPE_CODE (t))
1078 {
1079 default:
1080 /* Should never happen. */
1081 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1082 return 4;
1083
1084 case TYPE_CODE_PTR:
1085 case TYPE_CODE_ENUM:
1086 case TYPE_CODE_INT:
1087 case TYPE_CODE_FLT:
1088 case TYPE_CODE_SET:
1089 case TYPE_CODE_RANGE:
1090 case TYPE_CODE_BITSTRING:
1091 case TYPE_CODE_REF:
aa006118 1092 case TYPE_CODE_RVALUE_REF:
07b287a0
MS		 1093 case TYPE_CODE_CHAR:
1094 case TYPE_CODE_BOOL:
1095 return TYPE_LENGTH (t);
1096
1097 case TYPE_CODE_ARRAY:
238f2452
YQ		 1098 if (TYPE_VECTOR (t))
1099 {
1100 /* Use the natural alignment for vector types (the same for
1101 scalar type), but the maximum alignment is 128-bit. */
1102 if (TYPE_LENGTH (t) > 16)
1103 return 16;
1104 else
1105 return TYPE_LENGTH (t);
1106 }
1107 else
1108 return aarch64_type_align (TYPE_TARGET_TYPE (t));
07b287a0
MS		 1109 case TYPE_CODE_COMPLEX:
1110 return aarch64_type_align (TYPE_TARGET_TYPE (t));
1111
1112 case TYPE_CODE_STRUCT:
1113 case TYPE_CODE_UNION:
1114 align = 1;
1115 for (n = 0; n < TYPE_NFIELDS (t); n++)
1116 {
1117 falign = aarch64_type_align (TYPE_FIELD_TYPE (t, n));
1118 if (falign > align)
1119 align = falign;
1120 }
1121 return align;
1122 }
1123}
1124
cd635f74
YQ		 1125/* Return 1 if *TY is a homogeneous floating-point aggregate or
1126 homogeneous short-vector aggregate as defined in the AAPCS64 ABI
1127 document; otherwise return 0. */
07b287a0
MS		 1128
1129static int
cd635f74 1130is_hfa_or_hva (struct type *ty)
07b287a0
MS		 1131{
1132 switch (TYPE_CODE (ty))
1133 {
1134 case TYPE_CODE_ARRAY:
1135 {
1136 struct type *target_ty = TYPE_TARGET_TYPE (ty);
238f2452
YQ		 1137
1138 if (TYPE_VECTOR (ty))
1139 return 0;
1140
cd635f74
YQ		 1141 if (TYPE_LENGTH (ty) <= 4 /* HFA or HVA has at most 4 members. */
1142 && (TYPE_CODE (target_ty) == TYPE_CODE_FLT /* HFA */
1143 || (TYPE_CODE (target_ty) == TYPE_CODE_ARRAY /* HVA */
1144 && TYPE_VECTOR (target_ty))))
07b287a0
MS		 1145 return 1;
1146 break;
1147 }
1148
1149 case TYPE_CODE_UNION:
1150 case TYPE_CODE_STRUCT:
1151 {
cd635f74 1152 /* HFA or HVA has at most four members. */
07b287a0
MS		 1153 if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4)
1154 {
1155 struct type *member0_type;
1156
1157 member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0));
cd635f74
YQ		 1158 if (TYPE_CODE (member0_type) == TYPE_CODE_FLT
1159 || (TYPE_CODE (member0_type) == TYPE_CODE_ARRAY
1160 && TYPE_VECTOR (member0_type)))
07b287a0
MS		 1161 {
1162 int i;
1163
1164 for (i = 0; i < TYPE_NFIELDS (ty); i++)
1165 {
1166 struct type *member1_type;
1167
1168 member1_type = check_typedef (TYPE_FIELD_TYPE (ty, i));
1169 if (TYPE_CODE (member0_type) != TYPE_CODE (member1_type)
1170 || (TYPE_LENGTH (member0_type)
1171 != TYPE_LENGTH (member1_type)))
1172 return 0;
1173 }
1174 return 1;
1175 }
1176 }
1177 return 0;
1178 }
1179
1180 default:
1181 break;
1182 }
1183
1184 return 0;
1185}
1186
1187/* AArch64 function call information structure. */
1188struct aarch64_call_info
1189{
1190 /* the current argument number. */
1191 unsigned argnum;
1192
1193 /* The next general purpose register number, equivalent to NGRN as
1194 described in the AArch64 Procedure Call Standard. */
1195 unsigned ngrn;
1196
1197 /* The next SIMD and floating point register number, equivalent to
1198 NSRN as described in the AArch64 Procedure Call Standard. */
1199 unsigned nsrn;
1200
1201 /* The next stacked argument address, equivalent to NSAA as
1202 described in the AArch64 Procedure Call Standard. */
1203 unsigned nsaa;
1204
1205 /* Stack item vector. */
1206 VEC(stack_item_t) *si;
1207};
1208
1209/* Pass a value in a sequence of consecutive X registers. The caller
1210 is responsbile for ensuring sufficient registers are available. */
1211
1212static void
1213pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1214 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1215 struct value *arg)
07b287a0
MS		 1216{
1217 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1218 int len = TYPE_LENGTH (type);
1219 enum type_code typecode = TYPE_CODE (type);
1220 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1221 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1222
1223 info->argnum++;
1224
1225 while (len > 0)
1226 {
1227 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1228 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1229 byte_order);
1230
1231
1232 /* Adjust sub-word struct/union args when big-endian. */
1233 if (byte_order == BFD_ENDIAN_BIG
1234 && partial_len < X_REGISTER_SIZE
1235 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1236 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1237
1238 if (aarch64_debug)
b277c936
PL		 1239 {
1240 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1241 gdbarch_register_name (gdbarch, regnum),
1242 phex (regval, X_REGISTER_SIZE));
1243 }
07b287a0
MS		 1244 regcache_cooked_write_unsigned (regcache, regnum, regval);
1245 len -= partial_len;
1246 buf += partial_len;
1247 regnum++;
1248 }
1249}
1250
1251/* Attempt to marshall a value in a V register. Return 1 if
1252 successful, or 0 if insufficient registers are available. This
1253 function, unlike the equivalent pass_in_x() function does not
1254 handle arguments spread across multiple registers. */
1255
1256static int
1257pass_in_v (struct gdbarch *gdbarch,
1258 struct regcache *regcache,
1259 struct aarch64_call_info *info,
0735fddd 1260 int len, const bfd_byte *buf)
07b287a0
MS		 1261{
1262 if (info->nsrn < 8)
1263 {
07b287a0 1264 int regnum = AARCH64_V0_REGNUM + info->nsrn;
0735fddd 1265 gdb_byte reg[V_REGISTER_SIZE];
07b287a0
MS		 1266
1267 info->argnum++;
1268 info->nsrn++;
1269
0735fddd
YQ		 1270 memset (reg, 0, sizeof (reg));
1271 /* PCS C.1, the argument is allocated to the least significant
1272 bits of V register. */
1273 memcpy (reg, buf, len);
1274 regcache_cooked_write (regcache, regnum, reg);
1275
07b287a0 1276 if (aarch64_debug)
b277c936
PL		 1277 {
1278 debug_printf ("arg %d in %s\n", info->argnum,
1279 gdbarch_register_name (gdbarch, regnum));
1280 }
07b287a0
MS		 1281 return 1;
1282 }
1283 info->nsrn = 8;
1284 return 0;
1285}
1286
1287/* Marshall an argument onto the stack. */
1288
1289static void
1290pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1291 struct value *arg)
07b287a0 1292{
8e80f9d1 1293 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1294 int len = TYPE_LENGTH (type);
1295 int align;
1296 stack_item_t item;
1297
1298 info->argnum++;
1299
1300 align = aarch64_type_align (type);
1301
1302 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1303 Natural alignment of the argument's type. */
1304 align = align_up (align, 8);
1305
1306 /* The AArch64 PCS requires at most doubleword alignment. */
1307 if (align > 16)
1308 align = 16;
1309
1310 if (aarch64_debug)
b277c936
PL		 1311 {
1312 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1313 info->nsaa);
1314 }
07b287a0
MS		 1315
1316 item.len = len;
1317 item.data = buf;
1318 VEC_safe_push (stack_item_t, info->si, &item);
1319
1320 info->nsaa += len;
1321 if (info->nsaa & (align - 1))
1322 {
1323 /* Push stack alignment padding. */
1324 int pad = align - (info->nsaa & (align - 1));
1325
1326 item.len = pad;
c3c87445 1327 item.data = NULL;
07b287a0
MS		 1328
1329 VEC_safe_push (stack_item_t, info->si, &item);
1330 info->nsaa += pad;
1331 }
1332}
1333
1334/* Marshall an argument into a sequence of one or more consecutive X
1335 registers or, if insufficient X registers are available then onto
1336 the stack. */
1337
1338static void
1339pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1340 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1341 struct value *arg)
07b287a0
MS		 1342{
1343 int len = TYPE_LENGTH (type);
1344 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1345
1346 /* PCS C.13 - Pass in registers if we have enough spare */
1347 if (info->ngrn + nregs <= 8)
1348 {
8e80f9d1 1349 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1350 info->ngrn += nregs;
1351 }
1352 else
1353 {
1354 info->ngrn = 8;
8e80f9d1 1355 pass_on_stack (info, type, arg);
07b287a0
MS		 1356 }
1357}
1358
1359/* Pass a value in a V register, or on the stack if insufficient are
1360 available. */
1361
1362static void
1363pass_in_v_or_stack (struct gdbarch *gdbarch,
1364 struct regcache *regcache,
1365 struct aarch64_call_info *info,
1366 struct type *type,
8e80f9d1 1367 struct value *arg)
07b287a0 1368{
0735fddd
YQ		 1369 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (type),
1370 value_contents (arg)))
8e80f9d1 1371 pass_on_stack (info, type, arg);
07b287a0
MS		 1372}
1373
1374/* Implement the "push_dummy_call" gdbarch method. */
1375
1376static CORE_ADDR
1377aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1378 struct regcache *regcache, CORE_ADDR bp_addr,
1379 int nargs,
1380 struct value **args, CORE_ADDR sp, int struct_return,
1381 CORE_ADDR struct_addr)
1382{
07b287a0 1383 int argnum;
07b287a0
MS		 1384 struct aarch64_call_info info;
1385 struct type *func_type;
1386 struct type *return_type;
1387 int lang_struct_return;
1388
1389 memset (&info, 0, sizeof (info));
1390
1391 /* We need to know what the type of the called function is in order
1392 to determine the number of named/anonymous arguments for the
1393 actual argument placement, and the return type in order to handle
1394 return value correctly.
1395
1396 The generic code above us views the decision of return in memory
1397 or return in registers as a two stage processes. The language
1398 handler is consulted first and may decide to return in memory (eg
1399 class with copy constructor returned by value), this will cause
1400 the generic code to allocate space AND insert an initial leading
1401 argument.
1402
1403 If the language code does not decide to pass in memory then the
1404 target code is consulted.
1405
1406 If the language code decides to pass in memory we want to move
1407 the pointer inserted as the initial argument from the argument
1408 list and into X8, the conventional AArch64 struct return pointer
1409 register.
1410
1411 This is slightly awkward, ideally the flag "lang_struct_return"
1412 would be passed to the targets implementation of push_dummy_call.
1413 Rather that change the target interface we call the language code
1414 directly ourselves. */
1415
1416 func_type = check_typedef (value_type (function));
1417
1418 /* Dereference function pointer types. */
1419 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1420 func_type = TYPE_TARGET_TYPE (func_type);
1421
1422 gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1423 || TYPE_CODE (func_type) == TYPE_CODE_METHOD);
1424
1425 /* If language_pass_by_reference () returned true we will have been
1426 given an additional initial argument, a hidden pointer to the
1427 return slot in memory. */
1428 return_type = TYPE_TARGET_TYPE (func_type);
1429 lang_struct_return = language_pass_by_reference (return_type);
1430
1431 /* Set the return address. For the AArch64, the return breakpoint
1432 is always at BP_ADDR. */
1433 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1434
1435 /* If we were given an initial argument for the return slot because
1436 lang_struct_return was true, lose it. */
1437 if (lang_struct_return)
1438 {
1439 args++;
1440 nargs--;
1441 }
1442
1443 /* The struct_return pointer occupies X8. */
1444 if (struct_return || lang_struct_return)
1445 {
1446 if (aarch64_debug)
b277c936
PL		 1447 {
1448 debug_printf ("struct return in %s = 0x%s\n",
1449 gdbarch_register_name (gdbarch,
1450 AARCH64_STRUCT_RETURN_REGNUM),
1451 paddress (gdbarch, struct_addr));
1452 }
07b287a0
MS		 1453 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1454 struct_addr);
1455 }
1456
1457 for (argnum = 0; argnum < nargs; argnum++)
1458 {
1459 struct value *arg = args[argnum];
1460 struct type *arg_type;
1461 int len;
1462
1463 arg_type = check_typedef (value_type (arg));
1464 len = TYPE_LENGTH (arg_type);
1465
1466 switch (TYPE_CODE (arg_type))
1467 {
1468 case TYPE_CODE_INT:
1469 case TYPE_CODE_BOOL:
1470 case TYPE_CODE_CHAR:
1471 case TYPE_CODE_RANGE:
1472 case TYPE_CODE_ENUM:
1473 if (len < 4)
1474 {
1475 /* Promote to 32 bit integer. */
1476 if (TYPE_UNSIGNED (arg_type))
1477 arg_type = builtin_type (gdbarch)->builtin_uint32;
1478 else
1479 arg_type = builtin_type (gdbarch)->builtin_int32;
1480 arg = value_cast (arg_type, arg);
1481 }
8e80f9d1 1482 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1483 break;
1484
1485 case TYPE_CODE_COMPLEX:
1486 if (info.nsrn <= 6)
1487 {
1488 const bfd_byte *buf = value_contents (arg);
1489 struct type *target_type =
1490 check_typedef (TYPE_TARGET_TYPE (arg_type));
1491
07b287a0 1492 pass_in_v (gdbarch, regcache, &info,
0735fddd
YQ		 1493 TYPE_LENGTH (target_type), buf);
1494 pass_in_v (gdbarch, regcache, &info,
1495 TYPE_LENGTH (target_type),
07b287a0
MS		 1496 buf + TYPE_LENGTH (target_type));
1497 }
1498 else
1499 {
1500 info.nsrn = 8;
8e80f9d1 1501 pass_on_stack (&info, arg_type, arg);
07b287a0
MS		 1502 }
1503 break;
1504 case TYPE_CODE_FLT:
8e80f9d1 1505 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1506 break;
1507
1508 case TYPE_CODE_STRUCT:
1509 case TYPE_CODE_ARRAY:
1510 case TYPE_CODE_UNION:
cd635f74 1511 if (is_hfa_or_hva (arg_type))
07b287a0
MS		 1512 {
1513 int elements = TYPE_NFIELDS (arg_type);
1514
1515 /* Homogeneous Aggregates */
1516 if (info.nsrn + elements < 8)
1517 {
1518 int i;
1519
1520 for (i = 0; i < elements; i++)
1521 {
1522 /* We know that we have sufficient registers
1523 available therefore this will never fallback
1524 to the stack. */
1525 struct value *field =
1526 value_primitive_field (arg, 0, i, arg_type);
1527 struct type *field_type =
1528 check_typedef (value_type (field));
1529
8e80f9d1
YQ		 1530 pass_in_v_or_stack (gdbarch, regcache, &info,
1531 field_type, field);
07b287a0
MS		 1532 }
1533 }
1534 else
1535 {
1536 info.nsrn = 8;
8e80f9d1 1537 pass_on_stack (&info, arg_type, arg);
07b287a0
MS		 1538 }
1539 }
238f2452
YQ		 1540 else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
1541 && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
1542 {
1543 /* Short vector types are passed in V registers. */
1544 pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
1545 }
07b287a0
MS		 1546 else if (len > 16)
1547 {
1548 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1549 invisible reference. */
1550
1551 /* Allocate aligned storage. */
1552 sp = align_down (sp - len, 16);
1553
1554 /* Write the real data into the stack. */
1555 write_memory (sp, value_contents (arg), len);
1556
1557 /* Construct the indirection. */
1558 arg_type = lookup_pointer_type (arg_type);
1559 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1560 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1561 }
1562 else
1563 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1564 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1565 break;
1566
1567 default:
8e80f9d1 1568 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1569 break;
1570 }
1571 }
1572
1573 /* Make sure stack retains 16 byte alignment. */
1574 if (info.nsaa & 15)
1575 sp -= 16 - (info.nsaa & 15);
1576
1577 while (!VEC_empty (stack_item_t, info.si))
1578 {
1579 stack_item_t *si = VEC_last (stack_item_t, info.si);
1580
1581 sp -= si->len;
c3c87445
YQ		 1582 if (si->data != NULL)
1583 write_memory (sp, si->data, si->len);
07b287a0
MS		 1584 VEC_pop (stack_item_t, info.si);
1585 }
1586
1587 VEC_free (stack_item_t, info.si);
1588
1589 /* Finally, update the SP register. */
1590 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1591
1592 return sp;
1593}
1594
1595/* Implement the "frame_align" gdbarch method. */
1596
1597static CORE_ADDR
1598aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1599{
1600 /* Align the stack to sixteen bytes. */
1601 return sp & ~(CORE_ADDR) 15;
1602}
1603
1604/* Return the type for an AdvSISD Q register. */
1605
1606static struct type *
1607aarch64_vnq_type (struct gdbarch *gdbarch)
1608{
1609 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1610
1611 if (tdep->vnq_type == NULL)
1612 {
1613 struct type *t;
1614 struct type *elem;
1615
1616 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1617 TYPE_CODE_UNION);
1618
1619 elem = builtin_type (gdbarch)->builtin_uint128;
1620 append_composite_type_field (t, "u", elem);
1621
1622 elem = builtin_type (gdbarch)->builtin_int128;
1623 append_composite_type_field (t, "s", elem);
1624
1625 tdep->vnq_type = t;
1626 }
1627
1628 return tdep->vnq_type;
1629}
1630
1631/* Return the type for an AdvSISD D register. */
1632
1633static struct type *
1634aarch64_vnd_type (struct gdbarch *gdbarch)
1635{
1636 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1637
1638 if (tdep->vnd_type == NULL)
1639 {
1640 struct type *t;
1641 struct type *elem;
1642
1643 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1644 TYPE_CODE_UNION);
1645
1646 elem = builtin_type (gdbarch)->builtin_double;
1647 append_composite_type_field (t, "f", elem);
1648
1649 elem = builtin_type (gdbarch)->builtin_uint64;
1650 append_composite_type_field (t, "u", elem);
1651
1652 elem = builtin_type (gdbarch)->builtin_int64;
1653 append_composite_type_field (t, "s", elem);
1654
1655 tdep->vnd_type = t;
1656 }
1657
1658 return tdep->vnd_type;
1659}
1660
1661/* Return the type for an AdvSISD S register. */
1662
1663static struct type *
1664aarch64_vns_type (struct gdbarch *gdbarch)
1665{
1666 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1667
1668 if (tdep->vns_type == NULL)
1669 {
1670 struct type *t;
1671 struct type *elem;
1672
1673 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1674 TYPE_CODE_UNION);
1675
1676 elem = builtin_type (gdbarch)->builtin_float;
1677 append_composite_type_field (t, "f", elem);
1678
1679 elem = builtin_type (gdbarch)->builtin_uint32;
1680 append_composite_type_field (t, "u", elem);
1681
1682 elem = builtin_type (gdbarch)->builtin_int32;
1683 append_composite_type_field (t, "s", elem);
1684
1685 tdep->vns_type = t;
1686 }
1687
1688 return tdep->vns_type;
1689}
1690
1691/* Return the type for an AdvSISD H register. */
1692
1693static struct type *
1694aarch64_vnh_type (struct gdbarch *gdbarch)
1695{
1696 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1697
1698 if (tdep->vnh_type == NULL)
1699 {
1700 struct type *t;
1701 struct type *elem;
1702
1703 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1704 TYPE_CODE_UNION);
1705
1706 elem = builtin_type (gdbarch)->builtin_uint16;
1707 append_composite_type_field (t, "u", elem);
1708
1709 elem = builtin_type (gdbarch)->builtin_int16;
1710 append_composite_type_field (t, "s", elem);
1711
1712 tdep->vnh_type = t;
1713 }
1714
1715 return tdep->vnh_type;
1716}
1717
1718/* Return the type for an AdvSISD B register. */
1719
1720static struct type *
1721aarch64_vnb_type (struct gdbarch *gdbarch)
1722{
1723 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1724
1725 if (tdep->vnb_type == NULL)
1726 {
1727 struct type *t;
1728 struct type *elem;
1729
1730 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1731 TYPE_CODE_UNION);
1732
1733 elem = builtin_type (gdbarch)->builtin_uint8;
1734 append_composite_type_field (t, "u", elem);
1735
1736 elem = builtin_type (gdbarch)->builtin_int8;
1737 append_composite_type_field (t, "s", elem);
1738
1739 tdep->vnb_type = t;
1740 }
1741
1742 return tdep->vnb_type;
1743}
1744
1745/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1746
1747static int
1748aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1749{
1750 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
1751 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
1752
1753 if (reg == AARCH64_DWARF_SP)
1754 return AARCH64_SP_REGNUM;
1755
1756 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
1757 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
1758
1759 return -1;
1760}
1761\f
1762
1763/* Implement the "print_insn" gdbarch method. */
1764
1765static int
1766aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
1767{
1768 info->symbols = NULL;
6394c606 1769 return default_print_insn (memaddr, info);
07b287a0
MS		 1770}
1771
1772/* AArch64 BRK software debug mode instruction.
1773 Note that AArch64 code is always little-endian.
1774 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 1775constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 1776
04180708 1777typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 1778
1779/* Extract from an array REGS containing the (raw) register state a
1780 function return value of type TYPE, and copy that, in virtual
1781 format, into VALBUF. */
1782
1783static void
1784aarch64_extract_return_value (struct type *type, struct regcache *regs,
1785 gdb_byte *valbuf)
1786{
ac7936df 1787 struct gdbarch *gdbarch = regs->arch ();
07b287a0
MS		 1788 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1789
1790 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1791 {
1792 bfd_byte buf[V_REGISTER_SIZE];
1793 int len = TYPE_LENGTH (type);
1794
1795 regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
1796 memcpy (valbuf, buf, len);
1797 }
1798 else if (TYPE_CODE (type) == TYPE_CODE_INT
1799 || TYPE_CODE (type) == TYPE_CODE_CHAR
1800 || TYPE_CODE (type) == TYPE_CODE_BOOL
1801 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 1802 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 1803 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1804 {
1805 /* If the the type is a plain integer, then the access is
1806 straight-forward. Otherwise we have to play around a bit
1807 more. */
1808 int len = TYPE_LENGTH (type);
1809 int regno = AARCH64_X0_REGNUM;
1810 ULONGEST tmp;
1811
1812 while (len > 0)
1813 {
1814 /* By using store_unsigned_integer we avoid having to do
1815 anything special for small big-endian values. */
1816 regcache_cooked_read_unsigned (regs, regno++, &tmp);
1817 store_unsigned_integer (valbuf,
1818 (len > X_REGISTER_SIZE
1819 ? X_REGISTER_SIZE : len), byte_order, tmp);
1820 len -= X_REGISTER_SIZE;
1821 valbuf += X_REGISTER_SIZE;
1822 }
1823 }
1824 else if (TYPE_CODE (type) == TYPE_CODE_COMPLEX)
1825 {
1826 int regno = AARCH64_V0_REGNUM;
1827 bfd_byte buf[V_REGISTER_SIZE];
1828 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1829 int len = TYPE_LENGTH (target_type);
1830
1831 regcache_cooked_read (regs, regno, buf);
1832 memcpy (valbuf, buf, len);
1833 valbuf += len;
1834 regcache_cooked_read (regs, regno + 1, buf);
1835 memcpy (valbuf, buf, len);
1836 valbuf += len;
1837 }
cd635f74 1838 else if (is_hfa_or_hva (type))
07b287a0
MS		 1839 {
1840 int elements = TYPE_NFIELDS (type);
1841 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1842 int len = TYPE_LENGTH (member_type);
1843 int i;
1844
1845 for (i = 0; i < elements; i++)
1846 {
1847 int regno = AARCH64_V0_REGNUM + i;
db3516bb 1848 bfd_byte buf[V_REGISTER_SIZE];
07b287a0
MS		 1849
1850 if (aarch64_debug)
b277c936 1851 {
cd635f74 1852 debug_printf ("read HFA or HVA return value element %d from %s\n",
b277c936
PL		 1853 i + 1,
1854 gdbarch_register_name (gdbarch, regno));
1855 }
07b287a0
MS		 1856 regcache_cooked_read (regs, regno, buf);
1857
1858 memcpy (valbuf, buf, len);
1859 valbuf += len;
1860 }
1861 }
238f2452
YQ		 1862 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1863 && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8))
1864 {
1865 /* Short vector is returned in V register. */
1866 gdb_byte buf[V_REGISTER_SIZE];
1867
1868 regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
1869 memcpy (valbuf, buf, TYPE_LENGTH (type));
1870 }
07b287a0
MS		 1871 else
1872 {
1873 /* For a structure or union the behaviour is as if the value had
1874 been stored to word-aligned memory and then loaded into
1875 registers with 64-bit load instruction(s). */
1876 int len = TYPE_LENGTH (type);
1877 int regno = AARCH64_X0_REGNUM;
1878 bfd_byte buf[X_REGISTER_SIZE];
1879
1880 while (len > 0)
1881 {
1882 regcache_cooked_read (regs, regno++, buf);
1883 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
1884 len -= X_REGISTER_SIZE;
1885 valbuf += X_REGISTER_SIZE;
1886 }
1887 }
1888}
1889
1890
1891/* Will a function return an aggregate type in memory or in a
1892 register? Return 0 if an aggregate type can be returned in a
1893 register, 1 if it must be returned in memory. */
1894
1895static int
1896aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
1897{
f168693b 1898 type = check_typedef (type);
07b287a0 1899
cd635f74 1900 if (is_hfa_or_hva (type))
07b287a0 1901 {
cd635f74
YQ		 1902 /* v0-v7 are used to return values and one register is allocated
1903 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 1904 return 0;
1905 }
1906
1907 if (TYPE_LENGTH (type) > 16)
1908 {
1909 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1910 invisible reference. */
1911
1912 return 1;
1913 }
1914
1915 return 0;
1916}
1917
1918/* Write into appropriate registers a function return value of type
1919 TYPE, given in virtual format. */
1920
1921static void
1922aarch64_store_return_value (struct type *type, struct regcache *regs,
1923 const gdb_byte *valbuf)
1924{
ac7936df 1925 struct gdbarch *gdbarch = regs->arch ();
07b287a0
MS		 1926 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1927
1928 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1929 {
1930 bfd_byte buf[V_REGISTER_SIZE];
1931 int len = TYPE_LENGTH (type);
1932
1933 memcpy (buf, valbuf, len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
1934 regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
1935 }
1936 else if (TYPE_CODE (type) == TYPE_CODE_INT
1937 || TYPE_CODE (type) == TYPE_CODE_CHAR
1938 || TYPE_CODE (type) == TYPE_CODE_BOOL
1939 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 1940 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 1941 || TYPE_CODE (type) == TYPE_CODE_ENUM)
1942 {
1943 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
1944 {
1945 /* Values of one word or less are zero/sign-extended and
1946 returned in r0. */
1947 bfd_byte tmpbuf[X_REGISTER_SIZE];
1948 LONGEST val = unpack_long (type, valbuf);
1949
1950 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
1951 regcache_cooked_write (regs, AARCH64_X0_REGNUM, tmpbuf);
1952 }
1953 else
1954 {
1955 /* Integral values greater than one word are stored in
1956 consecutive registers starting with r0. This will always
1957 be a multiple of the regiser size. */
1958 int len = TYPE_LENGTH (type);
1959 int regno = AARCH64_X0_REGNUM;
1960
1961 while (len > 0)
1962 {
1963 regcache_cooked_write (regs, regno++, valbuf);
1964 len -= X_REGISTER_SIZE;
1965 valbuf += X_REGISTER_SIZE;
1966 }
1967 }
1968 }
cd635f74 1969 else if (is_hfa_or_hva (type))
07b287a0
MS		 1970 {
1971 int elements = TYPE_NFIELDS (type);
1972 struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
1973 int len = TYPE_LENGTH (member_type);
1974 int i;
1975
1976 for (i = 0; i < elements; i++)
1977 {
1978 int regno = AARCH64_V0_REGNUM + i;
d1be909e 1979 bfd_byte tmpbuf[V_REGISTER_SIZE];
07b287a0
MS		 1980
1981 if (aarch64_debug)
b277c936 1982 {
cd635f74 1983 debug_printf ("write HFA or HVA return value element %d to %s\n",
b277c936
PL		 1984 i + 1,
1985 gdbarch_register_name (gdbarch, regno));
1986 }
07b287a0
MS		 1987
1988 memcpy (tmpbuf, valbuf, len);
1989 regcache_cooked_write (regs, regno, tmpbuf);
1990 valbuf += len;
1991 }
1992 }
238f2452
YQ		 1993 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
1994 && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16))
1995 {
1996 /* Short vector. */
1997 gdb_byte buf[V_REGISTER_SIZE];
1998
1999 memcpy (buf, valbuf, TYPE_LENGTH (type));
2000 regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
2001 }
07b287a0
MS		 2002 else
2003 {
2004 /* For a structure or union the behaviour is as if the value had
2005 been stored to word-aligned memory and then loaded into
2006 registers with 64-bit load instruction(s). */
2007 int len = TYPE_LENGTH (type);
2008 int regno = AARCH64_X0_REGNUM;
2009 bfd_byte tmpbuf[X_REGISTER_SIZE];
2010
2011 while (len > 0)
2012 {
2013 memcpy (tmpbuf, valbuf,
2014 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2015 regcache_cooked_write (regs, regno++, tmpbuf);
2016 len -= X_REGISTER_SIZE;
2017 valbuf += X_REGISTER_SIZE;
2018 }
2019 }
2020}
2021
2022/* Implement the "return_value" gdbarch method. */
2023
2024static enum return_value_convention
2025aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2026 struct type *valtype, struct regcache *regcache,
2027 gdb_byte *readbuf, const gdb_byte *writebuf)
2028{
07b287a0
MS		 2029
2030 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2031 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2032 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2033 {
2034 if (aarch64_return_in_memory (gdbarch, valtype))
2035 {
2036 if (aarch64_debug)
b277c936 2037 debug_printf ("return value in memory\n");
07b287a0
MS		 2038 return RETURN_VALUE_STRUCT_CONVENTION;
2039 }
2040 }
2041
2042 if (writebuf)
2043 aarch64_store_return_value (valtype, regcache, writebuf);
2044
2045 if (readbuf)
2046 aarch64_extract_return_value (valtype, regcache, readbuf);
2047
2048 if (aarch64_debug)
b277c936 2049 debug_printf ("return value in registers\n");
07b287a0
MS		 2050
2051 return RETURN_VALUE_REGISTER_CONVENTION;
2052}
2053
2054/* Implement the "get_longjmp_target" gdbarch method. */
2055
2056static int
2057aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2058{
2059 CORE_ADDR jb_addr;
2060 gdb_byte buf[X_REGISTER_SIZE];
2061 struct gdbarch *gdbarch = get_frame_arch (frame);
2062 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2063 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2064
2065 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2066
2067 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2068 X_REGISTER_SIZE))
2069 return 0;
2070
2071 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2072 return 1;
2073}
ea873d8e
PL		 2074
2075/* Implement the "gen_return_address" gdbarch method. */
2076
2077static void
2078aarch64_gen_return_address (struct gdbarch *gdbarch,
2079 struct agent_expr *ax, struct axs_value *value,
2080 CORE_ADDR scope)
2081{
2082 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2083 value->kind = axs_lvalue_register;
2084 value->u.reg = AARCH64_LR_REGNUM;
2085}
07b287a0
MS		 2086\f
2087
2088/* Return the pseudo register name corresponding to register regnum. */
2089
2090static const char *
2091aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2092{
2093 static const char *const q_name[] =
2094 {
2095 "q0", "q1", "q2", "q3",
2096 "q4", "q5", "q6", "q7",
2097 "q8", "q9", "q10", "q11",
2098 "q12", "q13", "q14", "q15",
2099 "q16", "q17", "q18", "q19",
2100 "q20", "q21", "q22", "q23",
2101 "q24", "q25", "q26", "q27",
2102 "q28", "q29", "q30", "q31",
2103 };
2104
2105 static const char *const d_name[] =
2106 {
2107 "d0", "d1", "d2", "d3",
2108 "d4", "d5", "d6", "d7",
2109 "d8", "d9", "d10", "d11",
2110 "d12", "d13", "d14", "d15",
2111 "d16", "d17", "d18", "d19",
2112 "d20", "d21", "d22", "d23",
2113 "d24", "d25", "d26", "d27",
2114 "d28", "d29", "d30", "d31",
2115 };
2116
2117 static const char *const s_name[] =
2118 {
2119 "s0", "s1", "s2", "s3",
2120 "s4", "s5", "s6", "s7",
2121 "s8", "s9", "s10", "s11",
2122 "s12", "s13", "s14", "s15",
2123 "s16", "s17", "s18", "s19",
2124 "s20", "s21", "s22", "s23",
2125 "s24", "s25", "s26", "s27",
2126 "s28", "s29", "s30", "s31",
2127 };
2128
2129 static const char *const h_name[] =
2130 {
2131 "h0", "h1", "h2", "h3",
2132 "h4", "h5", "h6", "h7",
2133 "h8", "h9", "h10", "h11",
2134 "h12", "h13", "h14", "h15",
2135 "h16", "h17", "h18", "h19",
2136 "h20", "h21", "h22", "h23",
2137 "h24", "h25", "h26", "h27",
2138 "h28", "h29", "h30", "h31",
2139 };
2140
2141 static const char *const b_name[] =
2142 {
2143 "b0", "b1", "b2", "b3",
2144 "b4", "b5", "b6", "b7",
2145 "b8", "b9", "b10", "b11",
2146 "b12", "b13", "b14", "b15",
2147 "b16", "b17", "b18", "b19",
2148 "b20", "b21", "b22", "b23",
2149 "b24", "b25", "b26", "b27",
2150 "b28", "b29", "b30", "b31",
2151 };
2152
2153 regnum -= gdbarch_num_regs (gdbarch);
2154
2155 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2156 return q_name[regnum - AARCH64_Q0_REGNUM];
2157
2158 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2159 return d_name[regnum - AARCH64_D0_REGNUM];
2160
2161 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2162 return s_name[regnum - AARCH64_S0_REGNUM];
2163
2164 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2165 return h_name[regnum - AARCH64_H0_REGNUM];
2166
2167 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2168 return b_name[regnum - AARCH64_B0_REGNUM];
2169
2170 internal_error (__FILE__, __LINE__,
2171 _("aarch64_pseudo_register_name: bad register number %d"),
2172 regnum);
2173}
2174
2175/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2176
2177static struct type *
2178aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2179{
2180 regnum -= gdbarch_num_regs (gdbarch);
2181
2182 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2183 return aarch64_vnq_type (gdbarch);
2184
2185 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2186 return aarch64_vnd_type (gdbarch);
2187
2188 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2189 return aarch64_vns_type (gdbarch);
2190
2191 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2192 return aarch64_vnh_type (gdbarch);
2193
2194 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2195 return aarch64_vnb_type (gdbarch);
2196
2197 internal_error (__FILE__, __LINE__,
2198 _("aarch64_pseudo_register_type: bad register number %d"),
2199 regnum);
2200}
2201
2202/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2203
2204static int
2205aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2206 struct reggroup *group)
2207{
2208 regnum -= gdbarch_num_regs (gdbarch);
2209
2210 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2211 return group == all_reggroup || group == vector_reggroup;
2212 else if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2213 return (group == all_reggroup || group == vector_reggroup
2214 || group == float_reggroup);
2215 else if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2216 return (group == all_reggroup || group == vector_reggroup
2217 || group == float_reggroup);
2218 else if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2219 return group == all_reggroup || group == vector_reggroup;
2220 else if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2221 return group == all_reggroup || group == vector_reggroup;
2222
2223 return group == all_reggroup;
2224}
2225
2226/* Implement the "pseudo_register_read_value" gdbarch method. */
2227
2228static struct value *
2229aarch64_pseudo_read_value (struct gdbarch *gdbarch,
849d0ba8 2230 readable_regcache *regcache,
07b287a0
MS		 2231 int regnum)
2232{
d1be909e 2233 gdb_byte reg_buf[V_REGISTER_SIZE];
07b287a0
MS		 2234 struct value *result_value;
2235 gdb_byte *buf;
2236
2237 result_value = allocate_value (register_type (gdbarch, regnum));
2238 VALUE_LVAL (result_value) = lval_register;
2239 VALUE_REGNUM (result_value) = regnum;
2240 buf = value_contents_raw (result_value);
2241
2242 regnum -= gdbarch_num_regs (gdbarch);
2243
2244 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2245 {
2246 enum register_status status;
2247 unsigned v_regnum;
2248
2249 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
03f50fc8 2250 status = regcache->raw_read (v_regnum, reg_buf);
07b287a0
MS		 2251 if (status != REG_VALID)
2252 mark_value_bytes_unavailable (result_value, 0,
2253 TYPE_LENGTH (value_type (result_value)));
2254 else
2255 memcpy (buf, reg_buf, Q_REGISTER_SIZE);
2256 return result_value;
2257 }
2258
2259 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2260 {
2261 enum register_status status;
2262 unsigned v_regnum;
2263
2264 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
03f50fc8 2265 status = regcache->raw_read (v_regnum, reg_buf);
07b287a0
MS		 2266 if (status != REG_VALID)
2267 mark_value_bytes_unavailable (result_value, 0,
2268 TYPE_LENGTH (value_type (result_value)));
2269 else
2270 memcpy (buf, reg_buf, D_REGISTER_SIZE);
2271 return result_value;
2272 }
2273
2274 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2275 {
2276 enum register_status status;
2277 unsigned v_regnum;
2278
2279 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
03f50fc8 2280 status = regcache->raw_read (v_regnum, reg_buf);
4bcddace
PL		 2281 if (status != REG_VALID)
2282 mark_value_bytes_unavailable (result_value, 0,
2283 TYPE_LENGTH (value_type (result_value)));
2284 else
2285 memcpy (buf, reg_buf, S_REGISTER_SIZE);
07b287a0
MS		 2286 return result_value;
2287 }
2288
2289 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2290 {
2291 enum register_status status;
2292 unsigned v_regnum;
2293
2294 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
03f50fc8 2295 status = regcache->raw_read (v_regnum, reg_buf);
07b287a0
MS		 2296 if (status != REG_VALID)
2297 mark_value_bytes_unavailable (result_value, 0,
2298 TYPE_LENGTH (value_type (result_value)));
2299 else
2300 memcpy (buf, reg_buf, H_REGISTER_SIZE);
2301 return result_value;
2302 }
2303
2304 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2305 {
2306 enum register_status status;
2307 unsigned v_regnum;
2308
2309 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
03f50fc8 2310 status = regcache->raw_read (v_regnum, reg_buf);
07b287a0
MS		 2311 if (status != REG_VALID)
2312 mark_value_bytes_unavailable (result_value, 0,
2313 TYPE_LENGTH (value_type (result_value)));
2314 else
2315 memcpy (buf, reg_buf, B_REGISTER_SIZE);
2316 return result_value;
2317 }
2318
2319 gdb_assert_not_reached ("regnum out of bound");
2320}
2321
2322/* Implement the "pseudo_register_write" gdbarch method. */
2323
2324static void
2325aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2326 int regnum, const gdb_byte *buf)
2327{
d1be909e 2328 gdb_byte reg_buf[V_REGISTER_SIZE];
07b287a0
MS		 2329
2330 /* Ensure the register buffer is zero, we want gdb writes of the
2331 various 'scalar' pseudo registers to behavior like architectural
2332 writes, register width bytes are written the remainder are set to
2333 zero. */
2334 memset (reg_buf, 0, sizeof (reg_buf));
2335
2336 regnum -= gdbarch_num_regs (gdbarch);
2337
2338 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
2339 {
2340 /* pseudo Q registers */
2341 unsigned v_regnum;
2342
2343 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_Q0_REGNUM;
2344 memcpy (reg_buf, buf, Q_REGISTER_SIZE);
2345 regcache_raw_write (regcache, v_regnum, reg_buf);
2346 return;
2347 }
2348
2349 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
2350 {
2351 /* pseudo D registers */
2352 unsigned v_regnum;
2353
2354 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_D0_REGNUM;
2355 memcpy (reg_buf, buf, D_REGISTER_SIZE);
2356 regcache_raw_write (regcache, v_regnum, reg_buf);
2357 return;
2358 }
2359
2360 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
2361 {
2362 unsigned v_regnum;
2363
2364 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_S0_REGNUM;
2365 memcpy (reg_buf, buf, S_REGISTER_SIZE);
2366 regcache_raw_write (regcache, v_regnum, reg_buf);
2367 return;
2368 }
2369
2370 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
2371 {
2372 /* pseudo H registers */
2373 unsigned v_regnum;
2374
2375 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_H0_REGNUM;
2376 memcpy (reg_buf, buf, H_REGISTER_SIZE);
2377 regcache_raw_write (regcache, v_regnum, reg_buf);
2378 return;
2379 }
2380
2381 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
2382 {
2383 /* pseudo B registers */
2384 unsigned v_regnum;
2385
2386 v_regnum = AARCH64_V0_REGNUM + regnum - AARCH64_B0_REGNUM;
2387 memcpy (reg_buf, buf, B_REGISTER_SIZE);
2388 regcache_raw_write (regcache, v_regnum, reg_buf);
2389 return;
2390 }
2391
2392 gdb_assert_not_reached ("regnum out of bound");
2393}
2394
07b287a0
MS		 2395/* Callback function for user_reg_add. */
2396
2397static struct value *
2398value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2399{
9a3c8263 2400 const int *reg_p = (const int *) baton;
07b287a0
MS		 2401
2402 return value_of_register (*reg_p, frame);
2403}
2404\f
2405
9404b58f
KM		 2406/* Implement the "software_single_step" gdbarch method, needed to
2407 single step through atomic sequences on AArch64. */
2408
a0ff9e1a 2409static std::vector<CORE_ADDR>
f5ea389a 2410aarch64_software_single_step (struct regcache *regcache)
9404b58f 2411{
ac7936df 2412 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2413 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2414 const int insn_size = 4;
2415 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2416 CORE_ADDR pc = regcache_read_pc (regcache);
9404b58f
KM		 2417 CORE_ADDR breaks[2] = { -1, -1 };
2418 CORE_ADDR loc = pc;
2419 CORE_ADDR closing_insn = 0;
2420 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2421 byte_order_for_code);
2422 int index;
2423 int insn_count;
2424 int bc_insn_count = 0; /* Conditional branch instruction count. */
2425 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2426 aarch64_inst inst;
2427
43cdf5ae 2428 if (aarch64_decode_insn (insn, &inst, 1) != 0)
a0ff9e1a 2429 return {};
9404b58f
KM		 2430
2431 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2432 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2433 return {};
9404b58f
KM		 2434
2435 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2436 {
9404b58f
KM		 2437 loc += insn_size;
2438 insn = read_memory_unsigned_integer (loc, insn_size,
2439 byte_order_for_code);
2440
43cdf5ae 2441 if (aarch64_decode_insn (insn, &inst, 1) != 0)
a0ff9e1a 2442 return {};
9404b58f 2443 /* Check if the instruction is a conditional branch. */
f77ee802 2444 if (inst.opcode->iclass == condbranch)
9404b58f 2445 {
f77ee802
YQ		 2446 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2447
9404b58f 2448 if (bc_insn_count >= 1)
a0ff9e1a 2449 return {};
9404b58f
KM		 2450
2451 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2452 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2453
2454 bc_insn_count++;
2455 last_breakpoint++;
2456 }
2457
2458 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2459 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2460 {
2461 closing_insn = loc;
2462 break;
2463 }
2464 }
2465
2466 /* We didn't find a closing Store Exclusive instruction, fall back. */
2467 if (!closing_insn)
a0ff9e1a 2468 return {};
9404b58f
KM		 2469
2470 /* Insert breakpoint after the end of the atomic sequence. */
2471 breaks[0] = loc + insn_size;
2472
2473 /* Check for duplicated breakpoints, and also check that the second
2474 breakpoint is not within the atomic sequence. */
2475 if (last_breakpoint
2476 && (breaks[1] == breaks[0]
2477 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2478 last_breakpoint = 0;
2479
a0ff9e1a
SM		 2480 std::vector<CORE_ADDR> next_pcs;
2481
9404b58f
KM		 2482 /* Insert the breakpoint at the end of the sequence, and one at the
2483 destination of the conditional branch, if it exists. */
2484 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2485 next_pcs.push_back (breaks[index]);
9404b58f 2486
93f9a11f 2487 return next_pcs;
9404b58f
KM		 2488}
2489
cfba9872 2490struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2491{
2492 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2493 is being displaced stepping. */
cfba9872 2494 int cond = 0;
b6542f81
YQ		 2495
2496 /* PC adjustment offset after displaced stepping. */
cfba9872 2497 int32_t pc_adjust = 0;
b6542f81
YQ		 2498};
2499
2500/* Data when visiting instructions for displaced stepping. */
2501
2502struct aarch64_displaced_step_data
2503{
2504 struct aarch64_insn_data base;
2505
2506 /* The address where the instruction will be executed at. */
2507 CORE_ADDR new_addr;
2508 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2509 uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
2510 /* Number of instructions in INSN_BUF. */
2511 unsigned insn_count;
2512 /* Registers when doing displaced stepping. */
2513 struct regcache *regs;
2514
cfba9872 2515 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2516};
2517
2518/* Implementation of aarch64_insn_visitor method "b". */
2519
2520static void
2521aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2522 struct aarch64_insn_data *data)
2523{
2524 struct aarch64_displaced_step_data *dsd
2525 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2526 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2527
2528 if (can_encode_int32 (new_offset, 28))
2529 {
2530 /* Emit B rather than BL, because executing BL on a new address
2531 will get the wrong address into LR. In order to avoid this,
2532 we emit B, and update LR if the instruction is BL. */
2533 emit_b (dsd->insn_buf, 0, new_offset);
2534 dsd->insn_count++;
2535 }
2536 else
2537 {
2538 /* Write NOP. */
2539 emit_nop (dsd->insn_buf);
2540 dsd->insn_count++;
2541 dsd->dsc->pc_adjust = offset;
2542 }
2543
2544 if (is_bl)
2545 {
2546 /* Update LR. */
2547 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2548 data->insn_addr + 4);
2549 }
2550}
2551
2552/* Implementation of aarch64_insn_visitor method "b_cond". */
2553
2554static void
2555aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2556 struct aarch64_insn_data *data)
2557{
2558 struct aarch64_displaced_step_data *dsd
2559 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2560
2561 /* GDB has to fix up PC after displaced step this instruction
2562 differently according to the condition is true or false. Instead
2563 of checking COND against conditional flags, we can use
2564 the following instructions, and GDB can tell how to fix up PC
2565 according to the PC value.
2566
2567 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2568 INSN1 ;
2569 TAKEN:
2570 INSN2
2571 */
2572
2573 emit_bcond (dsd->insn_buf, cond, 8);
2574 dsd->dsc->cond = 1;
2575 dsd->dsc->pc_adjust = offset;
2576 dsd->insn_count = 1;
2577}
2578
2579/* Dynamically allocate a new register. If we know the register
2580 statically, we should make it a global as above instead of using this
2581 helper function. */
2582
2583static struct aarch64_register
2584aarch64_register (unsigned num, int is64)
2585{
2586 return (struct aarch64_register) { num, is64 };
2587}
2588
2589/* Implementation of aarch64_insn_visitor method "cb". */
2590
2591static void
2592aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2593 const unsigned rn, int is64,
2594 struct aarch64_insn_data *data)
2595{
2596 struct aarch64_displaced_step_data *dsd
2597 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2598
2599 /* The offset is out of range for a compare and branch
2600 instruction. We can use the following instructions instead:
2601
2602 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2603 INSN1 ;
2604 TAKEN:
2605 INSN2
2606 */
2607 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2608 dsd->insn_count = 1;
2609 dsd->dsc->cond = 1;
2610 dsd->dsc->pc_adjust = offset;
2611}
2612
2613/* Implementation of aarch64_insn_visitor method "tb". */
2614
2615static void
2616aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2617 const unsigned rt, unsigned bit,
2618 struct aarch64_insn_data *data)
2619{
2620 struct aarch64_displaced_step_data *dsd
2621 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2622
2623 /* The offset is out of range for a test bit and branch
2624 instruction We can use the following instructions instead:
2625
2626 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2627 INSN1 ;
2628 TAKEN:
2629 INSN2
2630
2631 */
2632 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2633 dsd->insn_count = 1;
2634 dsd->dsc->cond = 1;
2635 dsd->dsc->pc_adjust = offset;
2636}
2637
2638/* Implementation of aarch64_insn_visitor method "adr". */
2639
2640static void
2641aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2642 const int is_adrp, struct aarch64_insn_data *data)
2643{
2644 struct aarch64_displaced_step_data *dsd
2645 = (struct aarch64_displaced_step_data *) data;
2646 /* We know exactly the address the ADR{P,} instruction will compute.
2647 We can just write it to the destination register. */
2648 CORE_ADDR address = data->insn_addr + offset;
2649
2650 if (is_adrp)
2651 {
2652 /* Clear the lower 12 bits of the offset to get the 4K page. */
2653 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2654 address & ~0xfff);
2655 }
2656 else
2657 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2658 address);
2659
2660 dsd->dsc->pc_adjust = 4;
2661 emit_nop (dsd->insn_buf);
2662 dsd->insn_count = 1;
2663}
2664
2665/* Implementation of aarch64_insn_visitor method "ldr_literal". */
2666
2667static void
2668aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2669 const unsigned rt, const int is64,
2670 struct aarch64_insn_data *data)
2671{
2672 struct aarch64_displaced_step_data *dsd
2673 = (struct aarch64_displaced_step_data *) data;
2674 CORE_ADDR address = data->insn_addr + offset;
2675 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2676
2677 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2678 address);
2679
2680 if (is_sw)
2681 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2682 aarch64_register (rt, 1), zero);
2683 else
2684 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2685 aarch64_register (rt, 1), zero);
2686
2687 dsd->dsc->pc_adjust = 4;
2688}
2689
2690/* Implementation of aarch64_insn_visitor method "others". */
2691
2692static void
2693aarch64_displaced_step_others (const uint32_t insn,
2694 struct aarch64_insn_data *data)
2695{
2696 struct aarch64_displaced_step_data *dsd
2697 = (struct aarch64_displaced_step_data *) data;
2698
e1c587c3 2699 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 2700 dsd->insn_count = 1;
2701
2702 if ((insn & 0xfffffc1f) == 0xd65f0000)
2703 {
2704 /* RET */
2705 dsd->dsc->pc_adjust = 0;
2706 }
2707 else
2708 dsd->dsc->pc_adjust = 4;
2709}
2710
2711static const struct aarch64_insn_visitor visitor =
2712{
2713 aarch64_displaced_step_b,
2714 aarch64_displaced_step_b_cond,
2715 aarch64_displaced_step_cb,
2716 aarch64_displaced_step_tb,
2717 aarch64_displaced_step_adr,
2718 aarch64_displaced_step_ldr_literal,
2719 aarch64_displaced_step_others,
2720};
2721
2722/* Implement the "displaced_step_copy_insn" gdbarch method. */
2723
2724struct displaced_step_closure *
2725aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2726 CORE_ADDR from, CORE_ADDR to,
2727 struct regcache *regs)
2728{
b6542f81
YQ		 2729 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2730 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2731 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 2732 aarch64_inst inst;
2733
2734 if (aarch64_decode_insn (insn, &inst, 1) != 0)
2735 return NULL;
b6542f81
YQ		 2736
2737 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 2738 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 2739 {
2740 /* We can't displaced step atomic sequences. */
2741 return NULL;
2742 }
2743
cfba9872
SM		 2744 std::unique_ptr<aarch64_displaced_step_closure> dsc
2745 (new aarch64_displaced_step_closure);
b6542f81
YQ		 2746 dsd.base.insn_addr = from;
2747 dsd.new_addr = to;
2748 dsd.regs = regs;
cfba9872 2749 dsd.dsc = dsc.get ();
034f1a81 2750 dsd.insn_count = 0;
b6542f81
YQ		 2751 aarch64_relocate_instruction (insn, &visitor,
2752 (struct aarch64_insn_data *) &dsd);
2753 gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
2754
2755 if (dsd.insn_count != 0)
2756 {
2757 int i;
2758
2759 /* Instruction can be relocated to scratch pad. Copy
2760 relocated instruction(s) there. */
2761 for (i = 0; i < dsd.insn_count; i++)
2762 {
2763 if (debug_displaced)
2764 {
2765 debug_printf ("displaced: writing insn ");
2766 debug_printf ("%.8x", dsd.insn_buf[i]);
2767 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
2768 }
2769 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
2770 (ULONGEST) dsd.insn_buf[i]);
2771 }
2772 }
2773 else
2774 {
b6542f81
YQ		 2775 dsc = NULL;
2776 }
2777
cfba9872 2778 return dsc.release ();
b6542f81
YQ		 2779}
2780
2781/* Implement the "displaced_step_fixup" gdbarch method. */
2782
2783void
2784aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 2785 struct displaced_step_closure *dsc_,
b6542f81
YQ		 2786 CORE_ADDR from, CORE_ADDR to,
2787 struct regcache *regs)
2788{
cfba9872
SM		 2789 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
2790
b6542f81
YQ		 2791 if (dsc->cond)
2792 {
2793 ULONGEST pc;
2794
2795 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
2796 if (pc - to == 8)
2797 {
2798 /* Condition is true. */
2799 }
2800 else if (pc - to == 4)
2801 {
2802 /* Condition is false. */
2803 dsc->pc_adjust = 4;
2804 }
2805 else
2806 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2807 }
2808
2809 if (dsc->pc_adjust != 0)
2810 {
2811 if (debug_displaced)
2812 {
2813 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2814 paddress (gdbarch, from), dsc->pc_adjust);
2815 }
2816 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
2817 from + dsc->pc_adjust);
2818 }
2819}
2820
2821/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2822
2823int
2824aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
2825 struct displaced_step_closure *closure)
2826{
2827 return 1;
2828}
2829
da434ccb
AH		 2830/* Get the correct target description. */
2831
2832const target_desc *
2833aarch64_read_description ()
2834{
2835 static target_desc *aarch64_tdesc = NULL;
2836 target_desc **tdesc = &aarch64_tdesc;
2837
2838 if (*tdesc == NULL)
2839 *tdesc = aarch64_create_target_description ();
2840
2841 return *tdesc;
2842}
2843
07b287a0
MS		 2844/* Initialize the current architecture based on INFO. If possible,
2845 re-use an architecture from ARCHES, which is a list of
2846 architectures already created during this debugging session.
2847
2848 Called e.g. at program startup, when reading a core file, and when
2849 reading a binary file. */
2850
2851static struct gdbarch *
2852aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2853{
2854 struct gdbarch_tdep *tdep;
2855 struct gdbarch *gdbarch;
2856 struct gdbarch_list *best_arch;
2857 struct tdesc_arch_data *tdesc_data = NULL;
2858 const struct target_desc *tdesc = info.target_desc;
2859 int i;
07b287a0
MS		 2860 int valid_p = 1;
2861 const struct tdesc_feature *feature;
2862 int num_regs = 0;
2863 int num_pseudo_regs = 0;
2864
2865 /* Ensure we always have a target descriptor. */
2866 if (!tdesc_has_registers (tdesc))
da434ccb 2867 tdesc = aarch64_read_description ();
07b287a0
MS		 2868
2869 gdb_assert (tdesc);
2870
2871 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.core");
2872
2873 if (feature == NULL)
2874 return NULL;
2875
2876 tdesc_data = tdesc_data_alloc ();
2877
2878 /* Validate the descriptor provides the mandatory core R registers
2879 and allocate their numbers. */
2880 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
2881 valid_p &=
2882 tdesc_numbered_register (feature, tdesc_data, AARCH64_X0_REGNUM + i,
2883 aarch64_r_register_names[i]);
2884
2885 num_regs = AARCH64_X0_REGNUM + i;
2886
2887 /* Look for the V registers. */
2888 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
2889 if (feature)
2890 {
2891 /* Validate the descriptor provides the mandatory V registers
2892 and allocate their numbers. */
2893 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
2894 valid_p &=
2895 tdesc_numbered_register (feature, tdesc_data, AARCH64_V0_REGNUM + i,
2896 aarch64_v_register_names[i]);
2897
2898 num_regs = AARCH64_V0_REGNUM + i;
2899
2900 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
2901 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
2902 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
2903 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
2904 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
2905 }
2906
2907 if (!valid_p)
2908 {
2909 tdesc_data_cleanup (tdesc_data);
2910 return NULL;
2911 }
2912
2913 /* AArch64 code is always little-endian. */
2914 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
2915
2916 /* If there is already a candidate, use it. */
2917 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2918 best_arch != NULL;
2919 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2920 {
2921 /* Found a match. */
2922 break;
2923 }
2924
2925 if (best_arch != NULL)
2926 {
2927 if (tdesc_data != NULL)
2928 tdesc_data_cleanup (tdesc_data);
2929 return best_arch->gdbarch;
2930 }
2931
8d749320 2932 tdep = XCNEW (struct gdbarch_tdep);
07b287a0
MS		 2933 gdbarch = gdbarch_alloc (&info, tdep);
2934
2935 /* This should be low enough for everything. */
2936 tdep->lowest_pc = 0x20;
2937 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2938 tdep->jb_elt_size = 8;
2939
2940 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
2941 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
2942
07b287a0
MS		 2943 /* Frame handling. */
2944 set_gdbarch_dummy_id (gdbarch, aarch64_dummy_id);
2945 set_gdbarch_unwind_pc (gdbarch, aarch64_unwind_pc);
2946 set_gdbarch_unwind_sp (gdbarch, aarch64_unwind_sp);
2947
2948 /* Advance PC across function entry code. */
2949 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
2950
2951 /* The stack grows downward. */
2952 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2953
2954 /* Breakpoint manipulation. */
04180708
YQ		 2955 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
2956 aarch64_breakpoint::kind_from_pc);
2957 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
2958 aarch64_breakpoint::bp_from_kind);
07b287a0 2959 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 2960 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 2961
2962 /* Information about registers, etc. */
2963 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
2964 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
2965 set_gdbarch_num_regs (gdbarch, num_regs);
2966
2967 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
2968 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
2969 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
2970 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
2971 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
2972 set_tdesc_pseudo_register_reggroup_p (gdbarch,
2973 aarch64_pseudo_register_reggroup_p);
2974
a738ea1d
YQ		 2975 /* The top byte of an address is known as the "tag" and is
2976 ignored by the kernel, the hardware, etc. and can be regarded
2977 as additional data associated with the address. */
2978 set_gdbarch_significant_addr_bit (gdbarch, 56);
2979
07b287a0
MS		 2980 /* ABI */
2981 set_gdbarch_short_bit (gdbarch, 16);
2982 set_gdbarch_int_bit (gdbarch, 32);
2983 set_gdbarch_float_bit (gdbarch, 32);
2984 set_gdbarch_double_bit (gdbarch, 64);
2985 set_gdbarch_long_double_bit (gdbarch, 128);
2986 set_gdbarch_long_bit (gdbarch, 64);
2987 set_gdbarch_long_long_bit (gdbarch, 64);
2988 set_gdbarch_ptr_bit (gdbarch, 64);
2989 set_gdbarch_char_signed (gdbarch, 0);
53375380 2990 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 2991 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2992 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2993 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2994
2995 /* Internal <-> external register number maps. */
2996 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
2997
2998 /* Returning results. */
2999 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3000
3001 /* Disassembly. */
3002 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3003
3004 /* Virtual tables. */
3005 set_gdbarch_vbit_in_delta (gdbarch, 1);
3006
3007 /* Hook in the ABI-specific overrides, if they have been registered. */
3008 info.target_desc = tdesc;
0dba2a6c 3009 info.tdesc_data = tdesc_data;
07b287a0
MS		 3010 gdbarch_init_osabi (info, gdbarch);
3011
3012 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
3013
3014 /* Add some default predicates. */
3015 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3016 dwarf2_append_unwinders (gdbarch);
3017 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3018
3019 frame_base_set_default (gdbarch, &aarch64_normal_base);
3020
3021 /* Now we have tuned the configuration, set a few final things,
3022 based on what the OS ABI has told us. */
3023
3024 if (tdep->jb_pc >= 0)
3025 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3026
ea873d8e
PL		 3027 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3028
07b287a0
MS		 3029 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3030
3031 /* Add standard register aliases. */
3032 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3033 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3034 value_of_aarch64_user_reg,
3035 &aarch64_register_aliases[i].regnum);
3036
3037 return gdbarch;
3038}
3039
3040static void
3041aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3042{
3043 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3044
3045 if (tdep == NULL)
3046 return;
3047
3048 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3049 paddress (gdbarch, tdep->lowest_pc));
3050}
3051
0d4c07af 3052#if GDB_SELF_TEST
1e2b521d
YQ		 3053namespace selftests
3054{
3055static void aarch64_process_record_test (void);
3056}
0d4c07af 3057#endif
1e2b521d 3058
07b287a0
MS		 3059void
3060_initialize_aarch64_tdep (void)
3061{
3062 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3063 aarch64_dump_tdep);
3064
07b287a0
MS		 3065 /* Debug this file's internals. */
3066 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3067Set AArch64 debugging."), _("\
3068Show AArch64 debugging."), _("\
3069When on, AArch64 specific debugging is enabled."),
3070 NULL,
3071 show_aarch64_debug,
3072 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3073
3074#if GDB_SELF_TEST
1526853e
SM		 3075 selftests::register_test ("aarch64-analyze-prologue",
3076 selftests::aarch64_analyze_prologue_test);
3077 selftests::register_test ("aarch64-process-record",
3078 selftests::aarch64_process_record_test);
6654d750
AH		 3079 selftests::record_xml_tdesc ("aarch64.xml",
3080 aarch64_create_target_description ());
4d9a9006 3081#endif
07b287a0 3082}
99afc88b
OJ		 3083
3084/* AArch64 process record-replay related structures, defines etc. */
3085
99afc88b
OJ		 3086#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3087 do \
3088 { \
3089 unsigned int reg_len = LENGTH; \
3090 if (reg_len) \
3091 { \
3092 REGS = XNEWVEC (uint32_t, reg_len); \
3093 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3094 } \
3095 } \
3096 while (0)
3097
3098#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3099 do \
3100 { \
3101 unsigned int mem_len = LENGTH; \
3102 if (mem_len) \
3103 { \
3104 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3105 memcpy(&MEMS->len, &RECORD_BUF[0], \
3106 sizeof(struct aarch64_mem_r) * LENGTH); \
3107 } \
3108 } \
3109 while (0)
3110
3111/* AArch64 record/replay structures and enumerations. */
3112
3113struct aarch64_mem_r
3114{
3115 uint64_t len; /* Record length. */
3116 uint64_t addr; /* Memory address. */
3117};
3118
3119enum aarch64_record_result
3120{
3121 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3122 AARCH64_RECORD_UNSUPPORTED,
3123 AARCH64_RECORD_UNKNOWN
3124};
3125
3126typedef struct insn_decode_record_t
3127{
3128 struct gdbarch *gdbarch;
3129 struct regcache *regcache;
3130 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3131 uint32_t aarch64_insn; /* Insn to be recorded. */
3132 uint32_t mem_rec_count; /* Count of memory records. */
3133 uint32_t reg_rec_count; /* Count of register records. */
3134 uint32_t *aarch64_regs; /* Registers to be recorded. */
3135 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3136} insn_decode_record;
3137
3138/* Record handler for data processing - register instructions. */
3139
3140static unsigned int
3141aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3142{
3143 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3144 uint32_t record_buf[4];
3145
3146 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3147 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3148 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3149
3150 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3151 {
3152 uint8_t setflags;
3153
3154 /* Logical (shifted register). */
3155 if (insn_bits24_27 == 0x0a)
3156 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3157 /* Add/subtract. */
3158 else if (insn_bits24_27 == 0x0b)
3159 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3160 else
3161 return AARCH64_RECORD_UNKNOWN;
3162
3163 record_buf[0] = reg_rd;
3164 aarch64_insn_r->reg_rec_count = 1;
3165 if (setflags)
3166 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3167 }
3168 else
3169 {
3170 if (insn_bits24_27 == 0x0b)
3171 {
3172 /* Data-processing (3 source). */
3173 record_buf[0] = reg_rd;
3174 aarch64_insn_r->reg_rec_count = 1;
3175 }
3176 else if (insn_bits24_27 == 0x0a)
3177 {
3178 if (insn_bits21_23 == 0x00)
3179 {
3180 /* Add/subtract (with carry). */
3181 record_buf[0] = reg_rd;
3182 aarch64_insn_r->reg_rec_count = 1;
3183 if (bit (aarch64_insn_r->aarch64_insn, 29))
3184 {
3185 record_buf[1] = AARCH64_CPSR_REGNUM;
3186 aarch64_insn_r->reg_rec_count = 2;
3187 }
3188 }
3189 else if (insn_bits21_23 == 0x02)
3190 {
3191 /* Conditional compare (register) and conditional compare
3192 (immediate) instructions. */
3193 record_buf[0] = AARCH64_CPSR_REGNUM;
3194 aarch64_insn_r->reg_rec_count = 1;
3195 }
3196 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3197 {
3198 /* CConditional select. */
3199 /* Data-processing (2 source). */
3200 /* Data-processing (1 source). */
3201 record_buf[0] = reg_rd;
3202 aarch64_insn_r->reg_rec_count = 1;
3203 }
3204 else
3205 return AARCH64_RECORD_UNKNOWN;
3206 }
3207 }
3208
3209 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3210 record_buf);
3211 return AARCH64_RECORD_SUCCESS;
3212}
3213
3214/* Record handler for data processing - immediate instructions. */
3215
3216static unsigned int
3217aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3218{
78cc6c2d 3219 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3220 uint32_t record_buf[4];
3221
3222 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3223 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3224 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3225
3226 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3227 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3228 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3229 {
3230 record_buf[0] = reg_rd;
3231 aarch64_insn_r->reg_rec_count = 1;
3232 }
3233 else if (insn_bits24_27 == 0x01)
3234 {
3235 /* Add/Subtract (immediate). */
3236 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3237 record_buf[0] = reg_rd;
3238 aarch64_insn_r->reg_rec_count = 1;
3239 if (setflags)
3240 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3241 }
3242 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3243 {
3244 /* Logical (immediate). */
3245 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3246 record_buf[0] = reg_rd;
3247 aarch64_insn_r->reg_rec_count = 1;
3248 if (setflags)
3249 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3250 }
3251 else
3252 return AARCH64_RECORD_UNKNOWN;
3253
3254 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3255 record_buf);
3256 return AARCH64_RECORD_SUCCESS;
3257}
3258
3259/* Record handler for branch, exception generation and system instructions. */
3260
3261static unsigned int
3262aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3263{
3264 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3265 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3266 uint32_t record_buf[4];
3267
3268 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3269 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3270 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3271
3272 if (insn_bits28_31 == 0x0d)
3273 {
3274 /* Exception generation instructions. */
3275 if (insn_bits24_27 == 0x04)
3276 {
5d98d3cd
YQ		 3277 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3278 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3279 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3280 {
3281 ULONGEST svc_number;
3282
3283 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3284 &svc_number);
3285 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3286 svc_number);
3287 }
3288 else
3289 return AARCH64_RECORD_UNSUPPORTED;
3290 }
3291 /* System instructions. */
3292 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3293 {
3294 uint32_t reg_rt, reg_crn;
3295
3296 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3297 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3298
3299 /* Record rt in case of sysl and mrs instructions. */
3300 if (bit (aarch64_insn_r->aarch64_insn, 21))
3301 {
3302 record_buf[0] = reg_rt;
3303 aarch64_insn_r->reg_rec_count = 1;
3304 }
3305 /* Record cpsr for hint and msr(immediate) instructions. */
3306 else if (reg_crn == 0x02 || reg_crn == 0x04)
3307 {
3308 record_buf[0] = AARCH64_CPSR_REGNUM;
3309 aarch64_insn_r->reg_rec_count = 1;
3310 }
3311 }
3312 /* Unconditional branch (register). */
3313 else if((insn_bits24_27 & 0x0e) == 0x06)
3314 {
3315 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3316 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3317 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3318 }
3319 else
3320 return AARCH64_RECORD_UNKNOWN;
3321 }
3322 /* Unconditional branch (immediate). */
3323 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3324 {
3325 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3326 if (bit (aarch64_insn_r->aarch64_insn, 31))
3327 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3328 }
3329 else
3330 /* Compare & branch (immediate), Test & branch (immediate) and
3331 Conditional branch (immediate). */
3332 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3333
3334 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3335 record_buf);
3336 return AARCH64_RECORD_SUCCESS;
3337}
3338
3339/* Record handler for advanced SIMD load and store instructions. */
3340
3341static unsigned int
3342aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3343{
3344 CORE_ADDR address;
3345 uint64_t addr_offset = 0;
3346 uint32_t record_buf[24];
3347 uint64_t record_buf_mem[24];
3348 uint32_t reg_rn, reg_rt;
3349 uint32_t reg_index = 0, mem_index = 0;
3350 uint8_t opcode_bits, size_bits;
3351
3352 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3353 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3354 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3355 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3356 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3357
3358 if (record_debug)
b277c936 3359 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3360
3361 /* Load/store single structure. */
3362 if (bit (aarch64_insn_r->aarch64_insn, 24))
3363 {
3364 uint8_t sindex, scale, selem, esize, replicate = 0;
3365 scale = opcode_bits >> 2;
3366 selem = ((opcode_bits & 0x02) |
3367 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3368 switch (scale)
3369 {
3370 case 1:
3371 if (size_bits & 0x01)
3372 return AARCH64_RECORD_UNKNOWN;
3373 break;
3374 case 2:
3375 if ((size_bits >> 1) & 0x01)
3376 return AARCH64_RECORD_UNKNOWN;
3377 if (size_bits & 0x01)
3378 {
3379 if (!((opcode_bits >> 1) & 0x01))
3380 scale = 3;
3381 else
3382 return AARCH64_RECORD_UNKNOWN;
3383 }
3384 break;
3385 case 3:
3386 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3387 {
3388 scale = size_bits;
3389 replicate = 1;
3390 break;
3391 }
3392 else
3393 return AARCH64_RECORD_UNKNOWN;
3394 default:
3395 break;
3396 }
3397 esize = 8 << scale;
3398 if (replicate)
3399 for (sindex = 0; sindex < selem; sindex++)
3400 {
3401 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3402 reg_rt = (reg_rt + 1) % 32;
3403 }
3404 else
3405 {
3406 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3407 {
3408 if (bit (aarch64_insn_r->aarch64_insn, 22))
3409 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3410 else
3411 {
3412 record_buf_mem[mem_index++] = esize / 8;
3413 record_buf_mem[mem_index++] = address + addr_offset;
3414 }
3415 addr_offset = addr_offset + (esize / 8);
3416 reg_rt = (reg_rt + 1) % 32;
3417 }
99afc88b
OJ		 3418 }
3419 }
3420 /* Load/store multiple structure. */
3421 else
3422 {
3423 uint8_t selem, esize, rpt, elements;
3424 uint8_t eindex, rindex;
3425
3426 esize = 8 << size_bits;
3427 if (bit (aarch64_insn_r->aarch64_insn, 30))
3428 elements = 128 / esize;
3429 else
3430 elements = 64 / esize;
3431
3432 switch (opcode_bits)
3433 {
3434 /*LD/ST4 (4 Registers). */
3435 case 0:
3436 rpt = 1;
3437 selem = 4;
3438 break;
3439 /*LD/ST1 (4 Registers). */
3440 case 2:
3441 rpt = 4;
3442 selem = 1;
3443 break;
3444 /*LD/ST3 (3 Registers). */
3445 case 4:
3446 rpt = 1;
3447 selem = 3;
3448 break;
3449 /*LD/ST1 (3 Registers). */
3450 case 6:
3451 rpt = 3;
3452 selem = 1;
3453 break;
3454 /*LD/ST1 (1 Register). */
3455 case 7:
3456 rpt = 1;
3457 selem = 1;
3458 break;
3459 /*LD/ST2 (2 Registers). */
3460 case 8:
3461 rpt = 1;
3462 selem = 2;
3463 break;
3464 /*LD/ST1 (2 Registers). */
3465 case 10:
3466 rpt = 2;
3467 selem = 1;
3468 break;
3469 default:
3470 return AARCH64_RECORD_UNSUPPORTED;
3471 break;
3472 }
3473 for (rindex = 0; rindex < rpt; rindex++)
3474 for (eindex = 0; eindex < elements; eindex++)
3475 {
3476 uint8_t reg_tt, sindex;
3477 reg_tt = (reg_rt + rindex) % 32;
3478 for (sindex = 0; sindex < selem; sindex++)
3479 {
3480 if (bit (aarch64_insn_r->aarch64_insn, 22))
3481 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3482 else
3483 {
3484 record_buf_mem[mem_index++] = esize / 8;
3485 record_buf_mem[mem_index++] = address + addr_offset;
3486 }
3487 addr_offset = addr_offset + (esize / 8);
3488 reg_tt = (reg_tt + 1) % 32;
3489 }
3490 }
3491 }
3492
3493 if (bit (aarch64_insn_r->aarch64_insn, 23))
3494 record_buf[reg_index++] = reg_rn;
3495
3496 aarch64_insn_r->reg_rec_count = reg_index;
3497 aarch64_insn_r->mem_rec_count = mem_index / 2;
3498 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3499 record_buf_mem);
3500 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3501 record_buf);
3502 return AARCH64_RECORD_SUCCESS;
3503}
3504
3505/* Record handler for load and store instructions. */
3506
3507static unsigned int
3508aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3509{
3510 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3511 uint8_t insn_bit23, insn_bit21;
3512 uint8_t opc, size_bits, ld_flag, vector_flag;
3513 uint32_t reg_rn, reg_rt, reg_rt2;
3514 uint64_t datasize, offset;
3515 uint32_t record_buf[8];
3516 uint64_t record_buf_mem[8];
3517 CORE_ADDR address;
3518
3519 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3520 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3521 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3522 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3523 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3524 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3525 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3526 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3527 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3528 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3529 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3530
3531 /* Load/store exclusive. */
3532 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3533 {
3534 if (record_debug)
b277c936 3535 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 3536
3537 if (ld_flag)
3538 {
3539 record_buf[0] = reg_rt;
3540 aarch64_insn_r->reg_rec_count = 1;
3541 if (insn_bit21)
3542 {
3543 record_buf[1] = reg_rt2;
3544 aarch64_insn_r->reg_rec_count = 2;
3545 }
3546 }
3547 else
3548 {
3549 if (insn_bit21)
3550 datasize = (8 << size_bits) * 2;
3551 else
3552 datasize = (8 << size_bits);
3553 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3554 &address);
3555 record_buf_mem[0] = datasize / 8;
3556 record_buf_mem[1] = address;
3557 aarch64_insn_r->mem_rec_count = 1;
3558 if (!insn_bit23)
3559 {
3560 /* Save register rs. */
3561 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3562 aarch64_insn_r->reg_rec_count = 1;
3563 }
3564 }
3565 }
3566 /* Load register (literal) instructions decoding. */
3567 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3568 {
3569 if (record_debug)
b277c936 3570 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 3571 if (vector_flag)
3572 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3573 else
3574 record_buf[0] = reg_rt;
3575 aarch64_insn_r->reg_rec_count = 1;
3576 }
3577 /* All types of load/store pair instructions decoding. */
3578 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3579 {
3580 if (record_debug)
b277c936 3581 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 3582
3583 if (ld_flag)
3584 {
3585 if (vector_flag)
3586 {
3587 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3588 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3589 }
3590 else
3591 {
3592 record_buf[0] = reg_rt;
3593 record_buf[1] = reg_rt2;
3594 }
3595 aarch64_insn_r->reg_rec_count = 2;
3596 }
3597 else
3598 {
3599 uint16_t imm7_off;
3600 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3601 if (!vector_flag)
3602 size_bits = size_bits >> 1;
3603 datasize = 8 << (2 + size_bits);
3604 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3605 offset = offset << (2 + size_bits);
3606 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3607 &address);
3608 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3609 {
3610 if (imm7_off & 0x40)
3611 address = address - offset;
3612 else
3613 address = address + offset;
3614 }
3615
3616 record_buf_mem[0] = datasize / 8;
3617 record_buf_mem[1] = address;
3618 record_buf_mem[2] = datasize / 8;
3619 record_buf_mem[3] = address + (datasize / 8);
3620 aarch64_insn_r->mem_rec_count = 2;
3621 }
3622 if (bit (aarch64_insn_r->aarch64_insn, 23))
3623 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3624 }
3625 /* Load/store register (unsigned immediate) instructions. */
3626 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3627 {
3628 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3629 if (!(opc >> 1))
33877125
YQ		 3630 {
3631 if (opc & 0x01)
3632 ld_flag = 0x01;
3633 else
3634 ld_flag = 0x0;
3635 }
99afc88b 3636 else
33877125 3637 {
1e2b521d
YQ		 3638 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3639 {
3640 /* PRFM (immediate) */
3641 return AARCH64_RECORD_SUCCESS;
3642 }
3643 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3644 {
3645 /* LDRSW (immediate) */
3646 ld_flag = 0x1;
3647 }
33877125 3648 else
1e2b521d
YQ		 3649 {
3650 if (opc & 0x01)
3651 ld_flag = 0x01;
3652 else
3653 ld_flag = 0x0;
3654 }
33877125 3655 }
99afc88b
OJ		 3656
3657 if (record_debug)
3658 {
b277c936
PL		 3659 debug_printf ("Process record: load/store (unsigned immediate):"
3660 " size %x V %d opc %x\n", size_bits, vector_flag,
3661 opc);
99afc88b
OJ		 3662 }
3663
3664 if (!ld_flag)
3665 {
3666 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
3667 datasize = 8 << size_bits;
3668 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3669 &address);
3670 offset = offset << size_bits;
3671 address = address + offset;
3672
3673 record_buf_mem[0] = datasize >> 3;
3674 record_buf_mem[1] = address;
3675 aarch64_insn_r->mem_rec_count = 1;
3676 }
3677 else
3678 {
3679 if (vector_flag)
3680 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3681 else
3682 record_buf[0] = reg_rt;
3683 aarch64_insn_r->reg_rec_count = 1;
3684 }
3685 }
3686 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 3687 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3688 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 3689 {
3690 if (record_debug)
b277c936 3691 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 3692 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3693 if (!(opc >> 1))
3694 if (opc & 0x01)
3695 ld_flag = 0x01;
3696 else
3697 ld_flag = 0x0;
3698 else
3699 if (size_bits != 0x03)
3700 ld_flag = 0x01;
3701 else
3702 return AARCH64_RECORD_UNKNOWN;
3703
3704 if (!ld_flag)
3705 {
d9436c7c
PA		 3706 ULONGEST reg_rm_val;
3707
99afc88b
OJ		 3708 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
3709 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
3710 if (bit (aarch64_insn_r->aarch64_insn, 12))
3711 offset = reg_rm_val << size_bits;
3712 else
3713 offset = reg_rm_val;
3714 datasize = 8 << size_bits;
3715 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3716 &address);
3717 address = address + offset;
3718 record_buf_mem[0] = datasize >> 3;
3719 record_buf_mem[1] = address;
3720 aarch64_insn_r->mem_rec_count = 1;
3721 }
3722 else
3723 {
3724 if (vector_flag)
3725 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3726 else
3727 record_buf[0] = reg_rt;
3728 aarch64_insn_r->reg_rec_count = 1;
3729 }
3730 }
3731 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 3732 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
3733 && !insn_bit21)
99afc88b
OJ		 3734 {
3735 if (record_debug)
3736 {
b277c936
PL		 3737 debug_printf ("Process record: load/store "
3738 "(immediate and unprivileged)\n");
99afc88b
OJ		 3739 }
3740 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3741 if (!(opc >> 1))
3742 if (opc & 0x01)
3743 ld_flag = 0x01;
3744 else
3745 ld_flag = 0x0;
3746 else
3747 if (size_bits != 0x03)
3748 ld_flag = 0x01;
3749 else
3750 return AARCH64_RECORD_UNKNOWN;
3751
3752 if (!ld_flag)
3753 {
3754 uint16_t imm9_off;
3755 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
3756 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
3757 datasize = 8 << size_bits;
3758 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3759 &address);
3760 if (insn_bits10_11 != 0x01)
3761 {
3762 if (imm9_off & 0x0100)
3763 address = address - offset;
3764 else
3765 address = address + offset;
3766 }
3767 record_buf_mem[0] = datasize >> 3;
3768 record_buf_mem[1] = address;
3769 aarch64_insn_r->mem_rec_count = 1;
3770 }
3771 else
3772 {
3773 if (vector_flag)
3774 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3775 else
3776 record_buf[0] = reg_rt;
3777 aarch64_insn_r->reg_rec_count = 1;
3778 }
3779 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
3780 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3781 }
3782 /* Advanced SIMD load/store instructions. */
3783 else
3784 return aarch64_record_asimd_load_store (aarch64_insn_r);
3785
3786 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3787 record_buf_mem);
3788 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3789 record_buf);
3790 return AARCH64_RECORD_SUCCESS;
3791}
3792
3793/* Record handler for data processing SIMD and floating point instructions. */
3794
3795static unsigned int
3796aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
3797{
3798 uint8_t insn_bit21, opcode, rmode, reg_rd;
3799 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
3800 uint8_t insn_bits11_14;
3801 uint32_t record_buf[2];
3802
3803 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3804 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3805 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3806 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3807 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
3808 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
3809 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
3810 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3811 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3812
3813 if (record_debug)
b277c936 3814 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 3815
3816 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
3817 {
3818 /* Floating point - fixed point conversion instructions. */
3819 if (!insn_bit21)
3820 {
3821 if (record_debug)
b277c936 3822 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 3823
3824 if ((opcode >> 1) == 0x0 && rmode == 0x03)
3825 record_buf[0] = reg_rd;
3826 else
3827 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3828 }
3829 /* Floating point - conditional compare instructions. */
3830 else if (insn_bits10_11 == 0x01)
3831 {
3832 if (record_debug)
b277c936 3833 debug_printf ("FP - conditional compare");
99afc88b
OJ		 3834
3835 record_buf[0] = AARCH64_CPSR_REGNUM;
3836 }
3837 /* Floating point - data processing (2-source) and
3838 conditional select instructions. */
3839 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
3840 {
3841 if (record_debug)
b277c936 3842 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 3843
3844 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3845 }
3846 else if (insn_bits10_11 == 0x00)
3847 {
3848 /* Floating point - immediate instructions. */
3849 if ((insn_bits12_15 & 0x01) == 0x01
3850 || (insn_bits12_15 & 0x07) == 0x04)
3851 {
3852 if (record_debug)
b277c936 3853 debug_printf ("FP - immediate");
99afc88b
OJ		 3854 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3855 }
3856 /* Floating point - compare instructions. */
3857 else if ((insn_bits12_15 & 0x03) == 0x02)
3858 {
3859 if (record_debug)
b277c936 3860 debug_printf ("FP - immediate");
99afc88b
OJ		 3861 record_buf[0] = AARCH64_CPSR_REGNUM;
3862 }
3863 /* Floating point - integer conversions instructions. */
f62fce35 3864 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 3865 {
3866 /* Convert float to integer instruction. */
3867 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
3868 {
3869 if (record_debug)
b277c936 3870 debug_printf ("float to int conversion");
99afc88b
OJ		 3871
3872 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3873 }
3874 /* Convert integer to float instruction. */
3875 else if ((opcode >> 1) == 0x01 && !rmode)
3876 {
3877 if (record_debug)
b277c936 3878 debug_printf ("int to float conversion");
99afc88b
OJ		 3879
3880 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3881 }
3882 /* Move float to integer instruction. */
3883 else if ((opcode >> 1) == 0x03)
3884 {
3885 if (record_debug)
b277c936 3886 debug_printf ("move float to int");
99afc88b
OJ		 3887
3888 if (!(opcode & 0x01))
3889 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3890 else
3891 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3892 }
f62fce35
YQ		 3893 else
3894 return AARCH64_RECORD_UNKNOWN;
99afc88b 3895 }
f62fce35
YQ		 3896 else
3897 return AARCH64_RECORD_UNKNOWN;
99afc88b 3898 }
f62fce35
YQ		 3899 else
3900 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 3901 }
3902 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
3903 {
3904 if (record_debug)
b277c936 3905 debug_printf ("SIMD copy");
99afc88b
OJ		 3906
3907 /* Advanced SIMD copy instructions. */
3908 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
3909 && !bit (aarch64_insn_r->aarch64_insn, 15)
3910 && bit (aarch64_insn_r->aarch64_insn, 10))
3911 {
3912 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
3913 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
3914 else
3915 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3916 }
3917 else
3918 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3919 }
3920 /* All remaining floating point or advanced SIMD instructions. */
3921 else
3922 {
3923 if (record_debug)
b277c936 3924 debug_printf ("all remain");
99afc88b
OJ		 3925
3926 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
3927 }
3928
3929 if (record_debug)
b277c936 3930 debug_printf ("\n");
99afc88b
OJ		 3931
3932 aarch64_insn_r->reg_rec_count++;
3933 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
3934 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3935 record_buf);
3936 return AARCH64_RECORD_SUCCESS;
3937}
3938
3939/* Decodes insns type and invokes its record handler. */
3940
3941static unsigned int
3942aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
3943{
3944 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
3945
3946 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
3947 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
3948 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
3949 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
3950
3951 /* Data processing - immediate instructions. */
3952 if (!ins_bit26 && !ins_bit27 && ins_bit28)
3953 return aarch64_record_data_proc_imm (aarch64_insn_r);
3954
3955 /* Branch, exception generation and system instructions. */
3956 if (ins_bit26 && !ins_bit27 && ins_bit28)
3957 return aarch64_record_branch_except_sys (aarch64_insn_r);
3958
3959 /* Load and store instructions. */
3960 if (!ins_bit25 && ins_bit27)
3961 return aarch64_record_load_store (aarch64_insn_r);
3962
3963 /* Data processing - register instructions. */
3964 if (ins_bit25 && !ins_bit26 && ins_bit27)
3965 return aarch64_record_data_proc_reg (aarch64_insn_r);
3966
3967 /* Data processing - SIMD and floating point instructions. */
3968 if (ins_bit25 && ins_bit26 && ins_bit27)
3969 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
3970
3971 return AARCH64_RECORD_UNSUPPORTED;
3972}
3973
3974/* Cleans up local record registers and memory allocations. */
3975
3976static void
3977deallocate_reg_mem (insn_decode_record *record)
3978{
3979 xfree (record->aarch64_regs);
3980 xfree (record->aarch64_mems);
3981}
3982
1e2b521d
YQ		 3983#if GDB_SELF_TEST
3984namespace selftests {
3985
3986static void
3987aarch64_process_record_test (void)
3988{
3989 struct gdbarch_info info;
3990 uint32_t ret;
3991
3992 gdbarch_info_init (&info);
3993 info.bfd_arch_info = bfd_scan_arch ("aarch64");
3994
3995 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
3996 SELF_CHECK (gdbarch != NULL);
3997
3998 insn_decode_record aarch64_record;
3999
4000 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4001 aarch64_record.regcache = NULL;
4002 aarch64_record.this_addr = 0;
4003 aarch64_record.gdbarch = gdbarch;
4004
4005 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4006 aarch64_record.aarch64_insn = 0xf9800020;
4007 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4008 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4009 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4010 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4011
4012 deallocate_reg_mem (&aarch64_record);
4013}
4014
4015} // namespace selftests
4016#endif /* GDB_SELF_TEST */
4017
99afc88b
OJ		 4018/* Parse the current instruction and record the values of the registers and
4019 memory that will be changed in current instruction to record_arch_list
4020 return -1 if something is wrong. */
4021
4022int
4023aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4024 CORE_ADDR insn_addr)
4025{
4026 uint32_t rec_no = 0;
4027 uint8_t insn_size = 4;
4028 uint32_t ret = 0;
99afc88b
OJ		 4029 gdb_byte buf[insn_size];
4030 insn_decode_record aarch64_record;
4031
4032 memset (&buf[0], 0, insn_size);
4033 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4034 target_read_memory (insn_addr, &buf[0], insn_size);
4035 aarch64_record.aarch64_insn
4036 = (uint32_t) extract_unsigned_integer (&buf[0],
4037 insn_size,
4038 gdbarch_byte_order (gdbarch));
4039 aarch64_record.regcache = regcache;
4040 aarch64_record.this_addr = insn_addr;
4041 aarch64_record.gdbarch = gdbarch;
4042
4043 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4044 if (ret == AARCH64_RECORD_UNSUPPORTED)
4045 {
4046 printf_unfiltered (_("Process record does not support instruction "
4047 "0x%0x at address %s.\n"),
4048 aarch64_record.aarch64_insn,
4049 paddress (gdbarch, insn_addr));
4050 ret = -1;
4051 }
4052
4053 if (0 == ret)
4054 {
4055 /* Record registers. */
4056 record_full_arch_list_add_reg (aarch64_record.regcache,
4057 AARCH64_PC_REGNUM);
4058 /* Always record register CPSR. */
4059 record_full_arch_list_add_reg (aarch64_record.regcache,
4060 AARCH64_CPSR_REGNUM);
4061 if (aarch64_record.aarch64_regs)
4062 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4063 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4064 aarch64_record.aarch64_regs[rec_no]))
4065 ret = -1;
4066
4067 /* Record memories. */
4068 if (aarch64_record.aarch64_mems)
4069 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4070 if (record_full_arch_list_add_mem
4071 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4072 aarch64_record.aarch64_mems[rec_no].len))
4073 ret = -1;
4074
4075 if (record_full_arch_list_add_end ())
4076 ret = -1;
4077 }
4078
4079 deallocate_reg_mem (&aarch64_record);
4080 return ret;
4081}
GDB Binutils - Deliverables
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