2007-10-08 Markus Deuling <deuling@de.ibm.com>
[deliverable/binutils-gdb.git] / gdb / amd64-nat.c
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1/* Native-dependent code for AMD64.
2
6aba47ca 3 Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
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4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
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10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
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19
20#include "defs.h"
21#include "gdbarch.h"
22#include "regcache.h"
23
24#include "gdb_assert.h"
041bd74b 25#include "gdb_string.h"
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26
27#include "i386-tdep.h"
85be1ca6 28#include "amd64-tdep.h"
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29
30/* The following bits of code help with implementing debugging 32-bit
31 code natively on AMD64. The idea is to define two mappings between
32 the register number as used by GDB and the register set used by the
33 host to represent the general-purpose registers; one for 32-bit
34 code and one for 64-bit code. The mappings are specified by the
35 follwing variables and consist of an array of offsets within the
36 register set indexed by register number, and the number of
37 registers supported by the mapping. We don't need mappings for the
38 floating-point and SSE registers, since the difference between
39 64-bit and 32-bit variants are negligable. The difference in the
40 number of SSE registers is already handled by the target code. */
41
42/* General-purpose register mapping for native 32-bit code. */
43int *amd64_native_gregset32_reg_offset;
44int amd64_native_gregset32_num_regs = I386_NUM_GREGS;
45
46/* General-purpose register mapping for native 64-bit code. */
47int *amd64_native_gregset64_reg_offset;
90f90721 48int amd64_native_gregset64_num_regs = AMD64_NUM_GREGS;
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49
50/* Return the offset of REGNUM within the appropriate native
51 general-purpose register set. */
52
53static int
54amd64_native_gregset_reg_offset (int regnum)
55{
56 int *reg_offset = amd64_native_gregset64_reg_offset;
57 int num_regs = amd64_native_gregset64_num_regs;
58
59 gdb_assert (regnum >= 0);
60
61 if (gdbarch_ptr_bit (current_gdbarch) == 32)
62 {
63 reg_offset = amd64_native_gregset32_reg_offset;
64 num_regs = amd64_native_gregset32_num_regs;
65 }
66
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67 if (num_regs > gdbarch_num_regs (current_gdbarch))
68 num_regs = gdbarch_num_regs (current_gdbarch);
2a6d284d 69
f57d151a 70 if (regnum < num_regs && regnum < gdbarch_num_regs (current_gdbarch))
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71 return reg_offset[regnum];
72
73 return -1;
74}
75
76/* Return whether the native general-purpose register set supplies
77 register REGNUM. */
78
79int
80amd64_native_gregset_supplies_p (int regnum)
81{
82 return (amd64_native_gregset_reg_offset (regnum) != -1);
83}
84
85
ecba89de 86/* Supply register REGNUM, whose contents are stored in GREGS, to
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87 REGCACHE. If REGNUM is -1, supply all appropriate registers. */
88
89void
90amd64_supply_native_gregset (struct regcache *regcache,
91 const void *gregs, int regnum)
92{
93 const char *regs = gregs;
b053aceb 94 struct gdbarch *gdbarch = get_regcache_arch (regcache);
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95 int num_regs = amd64_native_gregset64_num_regs;
96 int i;
97
b053aceb 98 if (gdbarch_ptr_bit (gdbarch) == 32)
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99 num_regs = amd64_native_gregset32_num_regs;
100
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101 if (num_regs > gdbarch_num_regs (current_gdbarch))
102 num_regs = gdbarch_num_regs (current_gdbarch);
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103
104 for (i = 0; i < num_regs; i++)
105 {
106 if (regnum == -1 || regnum == i)
107 {
108 int offset = amd64_native_gregset_reg_offset (i);
109
110 if (offset != -1)
b053aceb 111 regcache_raw_supply (regcache, i, regs + offset);
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112 }
113 }
114}
115
116/* Collect register REGNUM from REGCACHE and store its contents in
117 GREGS. If REGNUM is -1, collect and store all appropriate
118 registers. */
119
120void
121amd64_collect_native_gregset (const struct regcache *regcache,
122 void *gregs, int regnum)
123{
124 char *regs = gregs;
b053aceb 125 struct gdbarch *gdbarch = get_regcache_arch (regcache);
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126 int num_regs = amd64_native_gregset64_num_regs;
127 int i;
128
b053aceb 129 if (gdbarch_ptr_bit (gdbarch) == 32)
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130 {
131 num_regs = amd64_native_gregset32_num_regs;
132
133 /* Make sure %eax, %ebx, %ecx, %edx, %esi, %edi, %ebp, %esp and
134 %eip get zero-extended to 64 bits. */
135 for (i = 0; i <= I386_EIP_REGNUM; i++)
136 {
137 if (regnum == -1 || regnum == i)
138 memset (regs + amd64_native_gregset_reg_offset (i), 0, 8);
139 }
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140 /* Ditto for %cs, %ss, %ds, %es, %fs, and %gs. */
141 for (i = I386_CS_REGNUM; i <= I386_GS_REGNUM; i++)
142 {
143 if (regnum == -1 || regnum == i)
144 memset (regs + amd64_native_gregset_reg_offset (i), 0, 8);
145 }
041bd74b 146 }
2a6d284d 147
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148 if (num_regs > gdbarch_num_regs (current_gdbarch))
149 num_regs = gdbarch_num_regs (current_gdbarch);
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150
151 for (i = 0; i < num_regs; i++)
152 {
153 if (regnum == -1 || regnum == i)
154 {
155 int offset = amd64_native_gregset_reg_offset (i);
156
157 if (offset != -1)
b053aceb 158 regcache_raw_collect (regcache, i, regs + offset);
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159 }
160 }
161}
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