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[deliverable/binutils-gdb.git] / gdb / amd64-tdep.c
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e53bef9f 1/* Target-dependent code for AMD64.
ce0eebec 2
e2882c85 3 Copyright (C) 2001-2018 Free Software Foundation, Inc.
5ae96ec1
MK		 4
5 Contributed by Jiri Smid, SuSE Labs.
53e95fcf
JS		 6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
53e95fcf
JS		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
53e95fcf
JS		 21
22#include "defs.h"
35669430
DE		 23#include "opcode/i386.h"
24#include "dis-asm.h"
c4f35dd8
MK		 25#include "arch-utils.h"
26#include "block.h"
27#include "dummy-frame.h"
28#include "frame.h"
29#include "frame-base.h"
30#include "frame-unwind.h"
53e95fcf 31#include "inferior.h"
45741a9c 32#include "infrun.h"
53e95fcf 33#include "gdbcmd.h"
c4f35dd8
MK		 34#include "gdbcore.h"
35#include "objfiles.h"
53e95fcf 36#include "regcache.h"
2c261fae 37#include "regset.h"
53e95fcf 38#include "symfile.h"
eda5a4d7 39#include "disasm.h"
9c1488cb 40#include "amd64-tdep.h"
c4f35dd8 41#include "i387-tdep.h"
97de3545 42#include "x86-xstate.h"
325fac50 43#include <algorithm>
22916b07
YQ		 44#include "target-descriptions.h"
45#include "arch/amd64.h"
b32b108a 46#include "producer.h"
6710bf39
SS		 47#include "ax.h"
48#include "ax-gdb.h"
cfba9872 49#include "common/byte-vector.h"
c912f608 50#include "osabi.h"
6710bf39 51
e53bef9f
MK		 52/* Note that the AMD64 architecture was previously known as x86-64.
53 The latter is (forever) engraved into the canonical system name as
90f90721 54 returned by config.guess, and used as the name for the AMD64 port
e53bef9f
MK		 55 of GNU/Linux. The BSD's have renamed their ports to amd64; they
56 don't like to shout. For GDB we prefer the amd64_-prefix over the
57 x86_64_-prefix since it's so much easier to type. */
58
402ecd56 59/* Register information. */
c4f35dd8 60
6707b003 61static const char *amd64_register_names[] =
de220d0f 62{
6707b003 63 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
c4f35dd8
MK		 64
65 /* %r8 is indeed register number 8. */
6707b003
UW		 66 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
67 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
c4f35dd8 68
af233647 69 /* %st0 is register number 24. */
6707b003
UW		 70 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
71 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
c4f35dd8 72
af233647 73 /* %xmm0 is register number 40. */
6707b003
UW		 74 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
75 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
76 "mxcsr",
0e04a514
ML		 77};
78
a055a187
L		 79static const char *amd64_ymm_names[] =
80{
81 "ymm0", "ymm1", "ymm2", "ymm3",
82 "ymm4", "ymm5", "ymm6", "ymm7",
83 "ymm8", "ymm9", "ymm10", "ymm11",
84 "ymm12", "ymm13", "ymm14", "ymm15"
85};
86
01f9f808
MS		 87static const char *amd64_ymm_avx512_names[] =
88{
89 "ymm16", "ymm17", "ymm18", "ymm19",
90 "ymm20", "ymm21", "ymm22", "ymm23",
91 "ymm24", "ymm25", "ymm26", "ymm27",
92 "ymm28", "ymm29", "ymm30", "ymm31"
93};
94
a055a187
L		 95static const char *amd64_ymmh_names[] =
96{
97 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
98 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
99 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
100 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
101};
de220d0f 102
01f9f808
MS		 103static const char *amd64_ymmh_avx512_names[] =
104{
105 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
106 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
107 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
108 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
109};
110
e43e105e
WT		 111static const char *amd64_mpx_names[] =
112{
113 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
114};
115
01f9f808
MS		 116static const char *amd64_k_names[] =
117{
118 "k0", "k1", "k2", "k3",
119 "k4", "k5", "k6", "k7"
120};
121
122static const char *amd64_zmmh_names[] =
123{
124 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
125 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
126 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
127 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
128 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
129 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
130 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
131 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
132};
133
134static const char *amd64_zmm_names[] =
135{
136 "zmm0", "zmm1", "zmm2", "zmm3",
137 "zmm4", "zmm5", "zmm6", "zmm7",
138 "zmm8", "zmm9", "zmm10", "zmm11",
139 "zmm12", "zmm13", "zmm14", "zmm15",
140 "zmm16", "zmm17", "zmm18", "zmm19",
141 "zmm20", "zmm21", "zmm22", "zmm23",
142 "zmm24", "zmm25", "zmm26", "zmm27",
143 "zmm28", "zmm29", "zmm30", "zmm31"
144};
145
146static const char *amd64_xmm_avx512_names[] = {
147 "xmm16", "xmm17", "xmm18", "xmm19",
148 "xmm20", "xmm21", "xmm22", "xmm23",
149 "xmm24", "xmm25", "xmm26", "xmm27",
150 "xmm28", "xmm29", "xmm30", "xmm31"
151};
152
51547df6
MS		 153static const char *amd64_pkeys_names[] = {
154 "pkru"
155};
156
c4f35dd8
MK		 157/* DWARF Register Number Mapping as defined in the System V psABI,
158 section 3.6. */
53e95fcf 159
e53bef9f 160static int amd64_dwarf_regmap[] =
0e04a514 161{
c4f35dd8 162 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
90f90721
MK		 163 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
164 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
165 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
c4f35dd8
MK		 166
167 /* Frame Pointer Register RBP. */
90f90721 168 AMD64_RBP_REGNUM,
c4f35dd8
MK		 169
170 /* Stack Pointer Register RSP. */
90f90721 171 AMD64_RSP_REGNUM,
c4f35dd8
MK		 172
173 /* Extended Integer Registers 8 - 15. */
5b856f36
PM		 174 AMD64_R8_REGNUM, /* %r8 */
175 AMD64_R9_REGNUM, /* %r9 */
176 AMD64_R10_REGNUM, /* %r10 */
177 AMD64_R11_REGNUM, /* %r11 */
178 AMD64_R12_REGNUM, /* %r12 */
179 AMD64_R13_REGNUM, /* %r13 */
180 AMD64_R14_REGNUM, /* %r14 */
181 AMD64_R15_REGNUM, /* %r15 */
c4f35dd8 182
59207364 183 /* Return Address RA. Mapped to RIP. */
90f90721 184 AMD64_RIP_REGNUM,
c4f35dd8
MK		 185
186 /* SSE Registers 0 - 7. */
90f90721
MK		 187 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
188 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
189 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
190 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
c4f35dd8
MK		 191
192 /* Extended SSE Registers 8 - 15. */
90f90721
MK		 193 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
194 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
195 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
196 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
c4f35dd8
MK		 197
198 /* Floating Point Registers 0-7. */
90f90721
MK		 199 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
200 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
201 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
c6f4c129 202 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
f7ca3fcf
PM		 203
204 /* MMX Registers 0 - 7.
205 We have to handle those registers specifically, as their register
206 number within GDB depends on the target (or they may even not be
207 available at all). */
208 -1, -1, -1, -1, -1, -1, -1, -1,
209
c6f4c129
JB		 210 /* Control and Status Flags Register. */
211 AMD64_EFLAGS_REGNUM,
212
213 /* Selector Registers. */
214 AMD64_ES_REGNUM,
215 AMD64_CS_REGNUM,
216 AMD64_SS_REGNUM,
217 AMD64_DS_REGNUM,
218 AMD64_FS_REGNUM,
219 AMD64_GS_REGNUM,
220 -1,
221 -1,
222
223 /* Segment Base Address Registers. */
224 -1,
225 -1,
226 -1,
227 -1,
228
229 /* Special Selector Registers. */
230 -1,
231 -1,
232
233 /* Floating Point Control Registers. */
234 AMD64_MXCSR_REGNUM,
235 AMD64_FCTRL_REGNUM,
236 AMD64_FSTAT_REGNUM
c4f35dd8 237};
0e04a514 238
e53bef9f
MK		 239static const int amd64_dwarf_regmap_len =
240 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
0e04a514 241
c4f35dd8
MK		 242/* Convert DWARF register number REG to the appropriate register
243 number used by GDB. */
26abbdc4 244
c4f35dd8 245static int
d3f73121 246amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
53e95fcf 247{
a055a187
L		 248 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
249 int ymm0_regnum = tdep->ymm0_regnum;
c4f35dd8 250 int regnum = -1;
53e95fcf 251
16aff9a6 252 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
e53bef9f 253 regnum = amd64_dwarf_regmap[reg];
53e95fcf 254
0fde2c53 255 if (ymm0_regnum >= 0
a055a187
L		 256 && i386_xmm_regnum_p (gdbarch, regnum))
257 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
c4f35dd8
MK		 258
259 return regnum;
53e95fcf 260}
d532c08f 261
35669430
DE		 262/* Map architectural register numbers to gdb register numbers. */
263
264static const int amd64_arch_regmap[16] =
265{
266 AMD64_RAX_REGNUM, /* %rax */
267 AMD64_RCX_REGNUM, /* %rcx */
268 AMD64_RDX_REGNUM, /* %rdx */
269 AMD64_RBX_REGNUM, /* %rbx */
270 AMD64_RSP_REGNUM, /* %rsp */
271 AMD64_RBP_REGNUM, /* %rbp */
272 AMD64_RSI_REGNUM, /* %rsi */
273 AMD64_RDI_REGNUM, /* %rdi */
274 AMD64_R8_REGNUM, /* %r8 */
275 AMD64_R9_REGNUM, /* %r9 */
276 AMD64_R10_REGNUM, /* %r10 */
277 AMD64_R11_REGNUM, /* %r11 */
278 AMD64_R12_REGNUM, /* %r12 */
279 AMD64_R13_REGNUM, /* %r13 */
280 AMD64_R14_REGNUM, /* %r14 */
281 AMD64_R15_REGNUM /* %r15 */
282};
283
284static const int amd64_arch_regmap_len =
285 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
286
287/* Convert architectural register number REG to the appropriate register
288 number used by GDB. */
289
290static int
291amd64_arch_reg_to_regnum (int reg)
292{
293 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
294
295 return amd64_arch_regmap[reg];
296}
297
1ba53b71
L		 298/* Register names for byte pseudo-registers. */
299
300static const char *amd64_byte_names[] =
301{
302 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
fe01d668
L		 303 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
304 "ah", "bh", "ch", "dh"
1ba53b71
L		 305};
306
fe01d668
L		 307/* Number of lower byte registers. */
308#define AMD64_NUM_LOWER_BYTE_REGS 16
309
1ba53b71
L		 310/* Register names for word pseudo-registers. */
311
312static const char *amd64_word_names[] =
313{
9cad29ac 314 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
1ba53b71
L		 315 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
316};
317
318/* Register names for dword pseudo-registers. */
319
320static const char *amd64_dword_names[] =
321{
322 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
fff4548b
MK		 323 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
324 "eip"
1ba53b71
L		 325};
326
327/* Return the name of register REGNUM. */
328
329static const char *
330amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
331{
332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
333 if (i386_byte_regnum_p (gdbarch, regnum))
334 return amd64_byte_names[regnum - tdep->al_regnum];
01f9f808
MS		 335 else if (i386_zmm_regnum_p (gdbarch, regnum))
336 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
a055a187
L		 337 else if (i386_ymm_regnum_p (gdbarch, regnum))
338 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
01f9f808
MS		 339 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
340 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
1ba53b71
L		 341 else if (i386_word_regnum_p (gdbarch, regnum))
342 return amd64_word_names[regnum - tdep->ax_regnum];
343 else if (i386_dword_regnum_p (gdbarch, regnum))
344 return amd64_dword_names[regnum - tdep->eax_regnum];
345 else
346 return i386_pseudo_register_name (gdbarch, regnum);
347}
348
3543a589
TT		 349static struct value *
350amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
849d0ba8 351 readable_regcache *regcache,
3543a589 352 int regnum)
1ba53b71 353{
9890e433 354 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
1ba53b71 355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
05d1431c 356 enum register_status status;
3543a589
TT		 357 struct value *result_value;
358 gdb_byte *buf;
359
360 result_value = allocate_value (register_type (gdbarch, regnum));
361 VALUE_LVAL (result_value) = lval_register;
362 VALUE_REGNUM (result_value) = regnum;
363 buf = value_contents_raw (result_value);
1ba53b71
L		 364
365 if (i386_byte_regnum_p (gdbarch, regnum))
366 {
367 int gpnum = regnum - tdep->al_regnum;
368
369 /* Extract (always little endian). */
fe01d668
L		 370 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
371 {
372 /* Special handling for AH, BH, CH, DH. */
03f50fc8
YQ		 373 status = regcache->raw_read (gpnum - AMD64_NUM_LOWER_BYTE_REGS,
374 raw_buf);
05d1431c
PA		 375 if (status == REG_VALID)
376 memcpy (buf, raw_buf + 1, 1);
3543a589
TT		 377 else
378 mark_value_bytes_unavailable (result_value, 0,
379 TYPE_LENGTH (value_type (result_value)));
fe01d668
L		 380 }
381 else
382 {
03f50fc8 383 status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 384 if (status == REG_VALID)
385 memcpy (buf, raw_buf, 1);
3543a589
TT		 386 else
387 mark_value_bytes_unavailable (result_value, 0,
388 TYPE_LENGTH (value_type (result_value)));
fe01d668 389 }
1ba53b71
L		 390 }
391 else if (i386_dword_regnum_p (gdbarch, regnum))
392 {
393 int gpnum = regnum - tdep->eax_regnum;
394 /* Extract (always little endian). */
03f50fc8 395 status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 396 if (status == REG_VALID)
397 memcpy (buf, raw_buf, 4);
3543a589
TT		 398 else
399 mark_value_bytes_unavailable (result_value, 0,
400 TYPE_LENGTH (value_type (result_value)));
1ba53b71
L		 401 }
402 else
3543a589
TT		 403 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
404 result_value);
405
406 return result_value;
1ba53b71
L		 407}
408
409static void
410amd64_pseudo_register_write (struct gdbarch *gdbarch,
411 struct regcache *regcache,
412 int regnum, const gdb_byte *buf)
413{
9890e433 414 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
1ba53b71
L		 415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416
417 if (i386_byte_regnum_p (gdbarch, regnum))
418 {
419 int gpnum = regnum - tdep->al_regnum;
420
fe01d668
L		 421 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
422 {
423 /* Read ... AH, BH, CH, DH. */
424 regcache_raw_read (regcache,
425 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
426 /* ... Modify ... (always little endian). */
427 memcpy (raw_buf + 1, buf, 1);
428 /* ... Write. */
429 regcache_raw_write (regcache,
430 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
431 }
432 else
433 {
434 /* Read ... */
435 regcache_raw_read (regcache, gpnum, raw_buf);
436 /* ... Modify ... (always little endian). */
437 memcpy (raw_buf, buf, 1);
438 /* ... Write. */
439 regcache_raw_write (regcache, gpnum, raw_buf);
440 }
1ba53b71
L		 441 }
442 else if (i386_dword_regnum_p (gdbarch, regnum))
443 {
444 int gpnum = regnum - tdep->eax_regnum;
445
446 /* Read ... */
447 regcache_raw_read (regcache, gpnum, raw_buf);
448 /* ... Modify ... (always little endian). */
449 memcpy (raw_buf, buf, 4);
450 /* ... Write. */
451 regcache_raw_write (regcache, gpnum, raw_buf);
452 }
453 else
454 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
455}
456
62e5fd57
MK		 457/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
458
459static int
460amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
461 struct agent_expr *ax, int regnum)
462{
463 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
464
465 if (i386_byte_regnum_p (gdbarch, regnum))
466 {
467 int gpnum = regnum - tdep->al_regnum;
468
469 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
470 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
471 else
472 ax_reg_mask (ax, gpnum);
473 return 0;
474 }
475 else if (i386_dword_regnum_p (gdbarch, regnum))
476 {
477 int gpnum = regnum - tdep->eax_regnum;
478
479 ax_reg_mask (ax, gpnum);
480 return 0;
481 }
482 else
483 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
484}
485
53e95fcf
JS		 486\f
487
bf4d6c1c
JB		 488/* Register classes as defined in the psABI. */
489
490enum amd64_reg_class
491{
492 AMD64_INTEGER,
493 AMD64_SSE,
494 AMD64_SSEUP,
495 AMD64_X87,
496 AMD64_X87UP,
497 AMD64_COMPLEX_X87,
498 AMD64_NO_CLASS,
499 AMD64_MEMORY
500};
501
efb1c01c
MK		 502/* Return the union class of CLASS1 and CLASS2. See the psABI for
503 details. */
504
505static enum amd64_reg_class
506amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
507{
508 /* Rule (a): If both classes are equal, this is the resulting class. */
509 if (class1 == class2)
510 return class1;
511
512 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
513 is the other class. */
514 if (class1 == AMD64_NO_CLASS)
515 return class2;
516 if (class2 == AMD64_NO_CLASS)
517 return class1;
518
519 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
520 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
521 return AMD64_MEMORY;
522
523 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
524 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
525 return AMD64_INTEGER;
526
527 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
528 MEMORY is used as class. */
529 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
530 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
531 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
532 return AMD64_MEMORY;
533
534 /* Rule (f): Otherwise class SSE is used. */
535 return AMD64_SSE;
536}
537
fe978cb0 538static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
bf4d6c1c 539
79b1ab3d
MK		 540/* Return non-zero if TYPE is a non-POD structure or union type. */
541
542static int
543amd64_non_pod_p (struct type *type)
544{
545 /* ??? A class with a base class certainly isn't POD, but does this
546 catch all non-POD structure types? */
547 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
548 return 1;
549
550 return 0;
551}
552
efb1c01c
MK		 553/* Classify TYPE according to the rules for aggregate (structures and
554 arrays) and union types, and store the result in CLASS. */
c4f35dd8
MK		 555
556static void
fe978cb0 557amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
53e95fcf 558{
efb1c01c
MK		 559 /* 1. If the size of an object is larger than two eightbytes, or in
560 C++, is a non-POD structure or union type, or contains
561 unaligned fields, it has class memory. */
744a8059 562 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
53e95fcf 563 {
fe978cb0 564 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 565 return;
53e95fcf 566 }
efb1c01c
MK		 567
568 /* 2. Both eightbytes get initialized to class NO_CLASS. */
fe978cb0 569 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 570
571 /* 3. Each field of an object is classified recursively so that
572 always two fields are considered. The resulting class is
573 calculated according to the classes of the fields in the
574 eightbyte: */
575
576 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
8ffd9b1b 577 {
efb1c01c
MK		 578 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
579
580 /* All fields in an array have the same type. */
fe978cb0
PA		 581 amd64_classify (subtype, theclass);
582 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
583 theclass[1] = theclass[0];
8ffd9b1b 584 }
53e95fcf
JS		 585 else
586 {
efb1c01c 587 int i;
53e95fcf 588
efb1c01c
MK		 589 /* Structure or union. */
590 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
591 || TYPE_CODE (type) == TYPE_CODE_UNION);
592
593 for (i = 0; i < TYPE_NFIELDS (type); i++)
53e95fcf 594 {
efb1c01c
MK		 595 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
596 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
597 enum amd64_reg_class subclass[2];
e4e2711a
JB		 598 int bitsize = TYPE_FIELD_BITSIZE (type, i);
599 int endpos;
600
601 if (bitsize == 0)
602 bitsize = TYPE_LENGTH (subtype) * 8;
603 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
efb1c01c 604
5dc43913
AB		 605 /* Ignore static fields, or empty fields, for example nested
606 empty structures.*/
607 if (field_is_static (&TYPE_FIELD (type, i)) || bitsize == 0)
562c50c2
MK		 608 continue;
609
efb1c01c
MK		 610 gdb_assert (pos == 0 || pos == 1);
611
612 amd64_classify (subtype, subclass);
fe978cb0 613 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
e4e2711a
JB		 614 if (bitsize <= 64 && pos == 0 && endpos == 1)
615 /* This is a bit of an odd case: We have a field that would
616 normally fit in one of the two eightbytes, except that
617 it is placed in a way that this field straddles them.
618 This has been seen with a structure containing an array.
619
620 The ABI is a bit unclear in this case, but we assume that
621 this field's class (stored in subclass[0]) must also be merged
622 into class[1]. In other words, our field has a piece stored
623 in the second eight-byte, and thus its class applies to
624 the second eight-byte as well.
625
626 In the case where the field length exceeds 8 bytes,
627 it should not be necessary to merge the field class
628 into class[1]. As LEN > 8, subclass[1] is necessarily
629 different from AMD64_NO_CLASS. If subclass[1] is equal
630 to subclass[0], then the normal class[1]/subclass[1]
631 merging will take care of everything. For subclass[1]
632 to be different from subclass[0], I can only see the case
633 where we have a SSE/SSEUP or X87/X87UP pair, which both
634 use up all 16 bytes of the aggregate, and are already
635 handled just fine (because each portion sits on its own
636 8-byte). */
fe978cb0 637 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
efb1c01c 638 if (pos == 0)
fe978cb0 639 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
53e95fcf 640 }
53e95fcf 641 }
efb1c01c
MK		 642
643 /* 4. Then a post merger cleanup is done: */
644
645 /* Rule (a): If one of the classes is MEMORY, the whole argument is
646 passed in memory. */
fe978cb0
PA		 647 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
648 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 649
177b42fe 650 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
efb1c01c 651 SSE. */
fe978cb0
PA		 652 if (theclass[0] == AMD64_SSEUP)
653 theclass[0] = AMD64_SSE;
654 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
655 theclass[1] = AMD64_SSE;
efb1c01c
MK		 656}
657
658/* Classify TYPE, and store the result in CLASS. */
659
bf4d6c1c 660static void
fe978cb0 661amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
efb1c01c
MK		 662{
663 enum type_code code = TYPE_CODE (type);
664 int len = TYPE_LENGTH (type);
665
fe978cb0 666 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 667
668 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
5a7225ed
JB		 669 long, long long, and pointers are in the INTEGER class. Similarly,
670 range types, used by languages such as Ada, are also in the INTEGER
671 class. */
efb1c01c 672 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
b929c77f 673 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
9db13498 674 || code == TYPE_CODE_CHAR
aa006118 675 || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
efb1c01c 676 && (len == 1 || len == 2 || len == 4 || len == 8))
fe978cb0 677 theclass[0] = AMD64_INTEGER;
efb1c01c 678
5daa78cc
TJB		 679 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
680 are in class SSE. */
681 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
682 && (len == 4 || len == 8))
efb1c01c 683 /* FIXME: __m64 . */
fe978cb0 684 theclass[0] = AMD64_SSE;
efb1c01c 685
5daa78cc
TJB		 686 /* Arguments of types __float128, _Decimal128 and __m128 are split into
687 two halves. The least significant ones belong to class SSE, the most
efb1c01c 688 significant one to class SSEUP. */
5daa78cc
TJB		 689 else if (code == TYPE_CODE_DECFLOAT && len == 16)
690 /* FIXME: __float128, __m128. */
fe978cb0 691 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
efb1c01c
MK		 692
693 /* The 64-bit mantissa of arguments of type long double belongs to
694 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
695 class X87UP. */
696 else if (code == TYPE_CODE_FLT && len == 16)
697 /* Class X87 and X87UP. */
fe978cb0 698 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
efb1c01c 699
7f7930dd
MK		 700 /* Arguments of complex T where T is one of the types float or
701 double get treated as if they are implemented as:
702
703 struct complexT {
704 T real;
705 T imag;
5f52445b
YQ		 706 };
707
708 */
7f7930dd 709 else if (code == TYPE_CODE_COMPLEX && len == 8)
fe978cb0 710 theclass[0] = AMD64_SSE;
7f7930dd 711 else if (code == TYPE_CODE_COMPLEX && len == 16)
fe978cb0 712 theclass[0] = theclass[1] = AMD64_SSE;
7f7930dd
MK		 713
714 /* A variable of type complex long double is classified as type
715 COMPLEX_X87. */
716 else if (code == TYPE_CODE_COMPLEX && len == 32)
fe978cb0 717 theclass[0] = AMD64_COMPLEX_X87;
7f7930dd 718
efb1c01c
MK		 719 /* Aggregates. */
720 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
721 || code == TYPE_CODE_UNION)
fe978cb0 722 amd64_classify_aggregate (type, theclass);
efb1c01c
MK		 723}
724
725static enum return_value_convention
6a3a010b 726amd64_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101 727 struct type *type, struct regcache *regcache,
42835c2b 728 gdb_byte *readbuf, const gdb_byte *writebuf)
efb1c01c 729{
fe978cb0 730 enum amd64_reg_class theclass[2];
efb1c01c 731 int len = TYPE_LENGTH (type);
90f90721
MK		 732 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
733 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
efb1c01c
MK		 734 int integer_reg = 0;
735 int sse_reg = 0;
736 int i;
737
738 gdb_assert (!(readbuf && writebuf));
739
740 /* 1. Classify the return type with the classification algorithm. */
fe978cb0 741 amd64_classify (type, theclass);
efb1c01c
MK		 742
743 /* 2. If the type has class MEMORY, then the caller provides space
6fa57a7d 744 for the return value and passes the address of this storage in
0963b4bd 745 %rdi as if it were the first argument to the function. In effect,
6fa57a7d
MK		 746 this address becomes a hidden first argument.
747
748 On return %rax will contain the address that has been passed in
749 by the caller in %rdi. */
fe978cb0 750 if (theclass[0] == AMD64_MEMORY)
6fa57a7d
MK		 751 {
752 /* As indicated by the comment above, the ABI guarantees that we
753 can always find the return value just after the function has
754 returned. */
755
756 if (readbuf)
757 {
758 ULONGEST addr;
759
760 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
761 read_memory (addr, readbuf, TYPE_LENGTH (type));
762 }
763
764 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
765 }
efb1c01c 766
7f7930dd
MK		 767 /* 8. If the class is COMPLEX_X87, the real part of the value is
768 returned in %st0 and the imaginary part in %st1. */
fe978cb0 769 if (theclass[0] == AMD64_COMPLEX_X87)
7f7930dd
MK		 770 {
771 if (readbuf)
772 {
773 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
774 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
775 }
776
777 if (writebuf)
778 {
779 i387_return_value (gdbarch, regcache);
780 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
781 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
782
783 /* Fix up the tag word such that both %st(0) and %st(1) are
784 marked as valid. */
785 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
786 }
787
788 return RETURN_VALUE_REGISTER_CONVENTION;
789 }
790
fe978cb0 791 gdb_assert (theclass[1] != AMD64_MEMORY);
bad43aa5 792 gdb_assert (len <= 16);
efb1c01c
MK		 793
794 for (i = 0; len > 0; i++, len -= 8)
795 {
796 int regnum = -1;
797 int offset = 0;
798
fe978cb0 799 switch (theclass[i])
efb1c01c
MK		 800 {
801 case AMD64_INTEGER:
802 /* 3. If the class is INTEGER, the next available register
803 of the sequence %rax, %rdx is used. */
804 regnum = integer_regnum[integer_reg++];
805 break;
806
807 case AMD64_SSE:
808 /* 4. If the class is SSE, the next available SSE register
809 of the sequence %xmm0, %xmm1 is used. */
810 regnum = sse_regnum[sse_reg++];
811 break;
812
813 case AMD64_SSEUP:
814 /* 5. If the class is SSEUP, the eightbyte is passed in the
815 upper half of the last used SSE register. */
816 gdb_assert (sse_reg > 0);
817 regnum = sse_regnum[sse_reg - 1];
818 offset = 8;
819 break;
820
821 case AMD64_X87:
822 /* 6. If the class is X87, the value is returned on the X87
823 stack in %st0 as 80-bit x87 number. */
90f90721 824 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 825 if (writebuf)
826 i387_return_value (gdbarch, regcache);
827 break;
828
829 case AMD64_X87UP:
830 /* 7. If the class is X87UP, the value is returned together
831 with the previous X87 value in %st0. */
fe978cb0 832 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
90f90721 833 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 834 offset = 8;
835 len = 2;
836 break;
837
838 case AMD64_NO_CLASS:
839 continue;
840
841 default:
842 gdb_assert (!"Unexpected register class.");
843 }
844
845 gdb_assert (regnum != -1);
846
847 if (readbuf)
325fac50 848 regcache_raw_read_part (regcache, regnum, offset, std::min (len, 8),
42835c2b 849 readbuf + i * 8);
efb1c01c 850 if (writebuf)
325fac50 851 regcache_raw_write_part (regcache, regnum, offset, std::min (len, 8),
42835c2b 852 writebuf + i * 8);
efb1c01c
MK		 853 }
854
855 return RETURN_VALUE_REGISTER_CONVENTION;
53e95fcf
JS		 856}
857\f
858
720aa428
MK		 859static CORE_ADDR
860amd64_push_arguments (struct regcache *regcache, int nargs,
6470d250 861 struct value **args, CORE_ADDR sp, int struct_return)
720aa428 862{
bf4d6c1c
JB		 863 static int integer_regnum[] =
864 {
865 AMD64_RDI_REGNUM, /* %rdi */
866 AMD64_RSI_REGNUM, /* %rsi */
867 AMD64_RDX_REGNUM, /* %rdx */
868 AMD64_RCX_REGNUM, /* %rcx */
5b856f36
PM		 869 AMD64_R8_REGNUM, /* %r8 */
870 AMD64_R9_REGNUM /* %r9 */
bf4d6c1c 871 };
720aa428
MK		 872 static int sse_regnum[] =
873 {
874 /* %xmm0 ... %xmm7 */
90f90721
MK		 875 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
876 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
877 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
878 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
720aa428 879 };
224c3ddb 880 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
720aa428
MK		 881 int num_stack_args = 0;
882 int num_elements = 0;
883 int element = 0;
884 int integer_reg = 0;
885 int sse_reg = 0;
886 int i;
887
6470d250
MK		 888 /* Reserve a register for the "hidden" argument. */
889 if (struct_return)
890 integer_reg++;
891
720aa428
MK		 892 for (i = 0; i < nargs; i++)
893 {
4991999e 894 struct type *type = value_type (args[i]);
720aa428 895 int len = TYPE_LENGTH (type);
fe978cb0 896 enum amd64_reg_class theclass[2];
720aa428
MK		 897 int needed_integer_regs = 0;
898 int needed_sse_regs = 0;
899 int j;
900
901 /* Classify argument. */
fe978cb0 902 amd64_classify (type, theclass);
720aa428
MK		 903
904 /* Calculate the number of integer and SSE registers needed for
905 this argument. */
906 for (j = 0; j < 2; j++)
907 {
fe978cb0 908 if (theclass[j] == AMD64_INTEGER)
720aa428 909 needed_integer_regs++;
fe978cb0 910 else if (theclass[j] == AMD64_SSE)
720aa428
MK		 911 needed_sse_regs++;
912 }
913
914 /* Check whether enough registers are available, and if the
915 argument should be passed in registers at all. */
bf4d6c1c 916 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
720aa428
MK		 917 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
918 || (needed_integer_regs == 0 && needed_sse_regs == 0))
919 {
920 /* The argument will be passed on the stack. */
921 num_elements += ((len + 7) / 8);
849e9755 922 stack_args[num_stack_args++] = args[i];
720aa428
MK		 923 }
924 else
925 {
926 /* The argument will be passed in registers. */
d8de1ef7
MK		 927 const gdb_byte *valbuf = value_contents (args[i]);
928 gdb_byte buf[8];
720aa428
MK		 929
930 gdb_assert (len <= 16);
931
932 for (j = 0; len > 0; j++, len -= 8)
933 {
934 int regnum = -1;
935 int offset = 0;
936
fe978cb0 937 switch (theclass[j])
720aa428
MK		 938 {
939 case AMD64_INTEGER:
bf4d6c1c 940 regnum = integer_regnum[integer_reg++];
720aa428
MK		 941 break;
942
943 case AMD64_SSE:
944 regnum = sse_regnum[sse_reg++];
945 break;
946
947 case AMD64_SSEUP:
948 gdb_assert (sse_reg > 0);
949 regnum = sse_regnum[sse_reg - 1];
950 offset = 8;
951 break;
952
953 default:
954 gdb_assert (!"Unexpected register class.");
955 }
956
957 gdb_assert (regnum != -1);
958 memset (buf, 0, sizeof buf);
325fac50 959 memcpy (buf, valbuf + j * 8, std::min (len, 8));
720aa428
MK		 960 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
961 }
962 }
963 }
964
965 /* Allocate space for the arguments on the stack. */
966 sp -= num_elements * 8;
967
968 /* The psABI says that "The end of the input argument area shall be
969 aligned on a 16 byte boundary." */
970 sp &= ~0xf;
971
972 /* Write out the arguments to the stack. */
973 for (i = 0; i < num_stack_args; i++)
974 {
4991999e 975 struct type *type = value_type (stack_args[i]);
d8de1ef7 976 const gdb_byte *valbuf = value_contents (stack_args[i]);
849e9755
JB		 977 int len = TYPE_LENGTH (type);
978
979 write_memory (sp + element * 8, valbuf, len);
980 element += ((len + 7) / 8);
720aa428
MK		 981 }
982
983 /* The psABI says that "For calls that may call functions that use
984 varargs or stdargs (prototype-less calls or calls to functions
985 containing ellipsis (...) in the declaration) %al is used as
986 hidden argument to specify the number of SSE registers used. */
90f90721 987 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
720aa428
MK		 988 return sp;
989}
990
c4f35dd8 991static CORE_ADDR
7d9b040b 992amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
e53bef9f
MK		 993 struct regcache *regcache, CORE_ADDR bp_addr,
994 int nargs, struct value **args, CORE_ADDR sp,
995 int struct_return, CORE_ADDR struct_addr)
53e95fcf 996{
e17a4113 997 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 998 gdb_byte buf[8];
c4f35dd8 999
4a612d6f
WT		 1000 /* BND registers can be in arbitrary values at the moment of the
1001 inferior call. This can cause boundary violations that are not
1002 due to a real bug or even desired by the user. The best to be done
1003 is set the BND registers to allow access to the whole memory, INIT
1004 state, before pushing the inferior call. */
1005 i387_reset_bnd_regs (gdbarch, regcache);
1006
c4f35dd8 1007 /* Pass arguments. */
6470d250 1008 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
c4f35dd8
MK		 1009
1010 /* Pass "hidden" argument". */
1011 if (struct_return)
1012 {
e17a4113 1013 store_unsigned_integer (buf, 8, byte_order, struct_addr);
bf4d6c1c 1014 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
c4f35dd8
MK		 1015 }
1016
1017 /* Store return address. */
1018 sp -= 8;
e17a4113 1019 store_unsigned_integer (buf, 8, byte_order, bp_addr);
c4f35dd8
MK		 1020 write_memory (sp, buf, 8);
1021
1022 /* Finally, update the stack pointer... */
e17a4113 1023 store_unsigned_integer (buf, 8, byte_order, sp);
90f90721 1024 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
c4f35dd8
MK		 1025
1026 /* ...and fake a frame pointer. */
90f90721 1027 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
c4f35dd8 1028
3e210248 1029 return sp + 16;
53e95fcf 1030}
c4f35dd8 1031\f
35669430
DE		 1032/* Displaced instruction handling. */
1033
1034/* A partially decoded instruction.
1035 This contains enough details for displaced stepping purposes. */
1036
1037struct amd64_insn
1038{
1039 /* The number of opcode bytes. */
1040 int opcode_len;
50a1fdd5
PA		 1041 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1042 not present. */
1043 int enc_prefix_offset;
35669430
DE		 1044 /* The offset to the first opcode byte. */
1045 int opcode_offset;
1046 /* The offset to the modrm byte or -1 if not present. */
1047 int modrm_offset;
1048
1049 /* The raw instruction. */
1050 gdb_byte *raw_insn;
1051};
1052
cfba9872 1053struct amd64_displaced_step_closure : public displaced_step_closure
35669430 1054{
cfba9872
SM		 1055 amd64_displaced_step_closure (int insn_buf_len)
1056 : insn_buf (insn_buf_len, 0)
1057 {}
1058
35669430 1059 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
cfba9872 1060 int tmp_used = 0;
35669430
DE		 1061 int tmp_regno;
1062 ULONGEST tmp_save;
1063
1064 /* Details of the instruction. */
1065 struct amd64_insn insn_details;
1066
cfba9872
SM		 1067 /* The possibly modified insn. */
1068 gdb::byte_vector insn_buf;
35669430
DE		 1069};
1070
1071/* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1072 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1073 at which point delete these in favor of libopcodes' versions). */
1074
1075static const unsigned char onebyte_has_modrm[256] = {
1076 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1077 /* ------------------------------- */
1078 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1079 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1080 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1081 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1082 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1083 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1084 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1085 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1086 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1087 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1088 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1089 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1090 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1091 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1092 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1093 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1094 /* ------------------------------- */
1095 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1096};
1097
1098static const unsigned char twobyte_has_modrm[256] = {
1099 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1100 /* ------------------------------- */
1101 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1102 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1103 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1104 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1105 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1106 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1107 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1108 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1109 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1110 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1111 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1112 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1113 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1114 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1115 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1116 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1117 /* ------------------------------- */
1118 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1119};
1120
1121static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1122
1123static int
1124rex_prefix_p (gdb_byte pfx)
1125{
1126 return REX_PREFIX_P (pfx);
1127}
1128
50a1fdd5
PA		 1129/* True if PFX is the start of the 2-byte VEX prefix. */
1130
1131static bool
1132vex2_prefix_p (gdb_byte pfx)
1133{
1134 return pfx == 0xc5;
1135}
1136
1137/* True if PFX is the start of the 3-byte VEX prefix. */
1138
1139static bool
1140vex3_prefix_p (gdb_byte pfx)
1141{
1142 return pfx == 0xc4;
1143}
1144
35669430
DE		 1145/* Skip the legacy instruction prefixes in INSN.
1146 We assume INSN is properly sentineled so we don't have to worry
1147 about falling off the end of the buffer. */
1148
1149static gdb_byte *
1903f0e6 1150amd64_skip_prefixes (gdb_byte *insn)
35669430
DE		 1151{
1152 while (1)
1153 {
1154 switch (*insn)
1155 {
1156 case DATA_PREFIX_OPCODE:
1157 case ADDR_PREFIX_OPCODE:
1158 case CS_PREFIX_OPCODE:
1159 case DS_PREFIX_OPCODE:
1160 case ES_PREFIX_OPCODE:
1161 case FS_PREFIX_OPCODE:
1162 case GS_PREFIX_OPCODE:
1163 case SS_PREFIX_OPCODE:
1164 case LOCK_PREFIX_OPCODE:
1165 case REPE_PREFIX_OPCODE:
1166 case REPNE_PREFIX_OPCODE:
1167 ++insn;
1168 continue;
1169 default:
1170 break;
1171 }
1172 break;
1173 }
1174
1175 return insn;
1176}
1177
35669430
DE		 1178/* Return an integer register (other than RSP) that is unused as an input
1179 operand in INSN.
1180 In order to not require adding a rex prefix if the insn doesn't already
1181 have one, the result is restricted to RAX ... RDI, sans RSP.
1182 The register numbering of the result follows architecture ordering,
1183 e.g. RDI = 7. */
1184
1185static int
1186amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1187{
1188 /* 1 bit for each reg */
1189 int used_regs_mask = 0;
1190
1191 /* There can be at most 3 int regs used as inputs in an insn, and we have
1192 7 to choose from (RAX ... RDI, sans RSP).
1193 This allows us to take a conservative approach and keep things simple.
1194 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1195 that implicitly specify RAX. */
1196
1197 /* Avoid RAX. */
1198 used_regs_mask |= 1 << EAX_REG_NUM;
1199 /* Similarily avoid RDX, implicit operand in divides. */
1200 used_regs_mask |= 1 << EDX_REG_NUM;
1201 /* Avoid RSP. */
1202 used_regs_mask |= 1 << ESP_REG_NUM;
1203
1204 /* If the opcode is one byte long and there's no ModRM byte,
1205 assume the opcode specifies a register. */
1206 if (details->opcode_len == 1 && details->modrm_offset == -1)
1207 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1208
1209 /* Mark used regs in the modrm/sib bytes. */
1210 if (details->modrm_offset != -1)
1211 {
1212 int modrm = details->raw_insn[details->modrm_offset];
1213 int mod = MODRM_MOD_FIELD (modrm);
1214 int reg = MODRM_REG_FIELD (modrm);
1215 int rm = MODRM_RM_FIELD (modrm);
1216 int have_sib = mod != 3 && rm == 4;
1217
1218 /* Assume the reg field of the modrm byte specifies a register. */
1219 used_regs_mask |= 1 << reg;
1220
1221 if (have_sib)
1222 {
1223 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
d48ebb5b 1224 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
35669430 1225 used_regs_mask |= 1 << base;
d48ebb5b 1226 used_regs_mask |= 1 << idx;
35669430
DE		 1227 }
1228 else
1229 {
1230 used_regs_mask |= 1 << rm;
1231 }
1232 }
1233
1234 gdb_assert (used_regs_mask < 256);
1235 gdb_assert (used_regs_mask != 255);
1236
1237 /* Finally, find a free reg. */
1238 {
1239 int i;
1240
1241 for (i = 0; i < 8; ++i)
1242 {
1243 if (! (used_regs_mask & (1 << i)))
1244 return i;
1245 }
1246
1247 /* We shouldn't get here. */
1248 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1249 }
1250}
1251
1252/* Extract the details of INSN that we need. */
1253
1254static void
1255amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1256{
1257 gdb_byte *start = insn;
1258 int need_modrm;
1259
1260 details->raw_insn = insn;
1261
1262 details->opcode_len = -1;
50a1fdd5 1263 details->enc_prefix_offset = -1;
35669430
DE		 1264 details->opcode_offset = -1;
1265 details->modrm_offset = -1;
1266
1267 /* Skip legacy instruction prefixes. */
1903f0e6 1268 insn = amd64_skip_prefixes (insn);
35669430 1269
50a1fdd5 1270 /* Skip REX/VEX instruction encoding prefixes. */
35669430
DE		 1271 if (rex_prefix_p (*insn))
1272 {
50a1fdd5 1273 details->enc_prefix_offset = insn - start;
35669430
DE		 1274 ++insn;
1275 }
50a1fdd5
PA		 1276 else if (vex2_prefix_p (*insn))
1277 {
1278 /* Don't record the offset in this case because this prefix has
1279 no REX.B equivalent. */
1280 insn += 2;
1281 }
1282 else if (vex3_prefix_p (*insn))
1283 {
1284 details->enc_prefix_offset = insn - start;
1285 insn += 3;
1286 }
35669430
DE		 1287
1288 details->opcode_offset = insn - start;
1289
1290 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1291 {
1292 /* Two or three-byte opcode. */
1293 ++insn;
1294 need_modrm = twobyte_has_modrm[*insn];
1295
1296 /* Check for three-byte opcode. */
1903f0e6 1297 switch (*insn)
35669430 1298 {
1903f0e6
DE		 1299 case 0x24:
1300 case 0x25:
1301 case 0x38:
1302 case 0x3a:
1303 case 0x7a:
1304 case 0x7b:
35669430
DE		 1305 ++insn;
1306 details->opcode_len = 3;
1903f0e6
DE		 1307 break;
1308 default:
1309 details->opcode_len = 2;
1310 break;
35669430 1311 }
35669430
DE		 1312 }
1313 else
1314 {
1315 /* One-byte opcode. */
1316 need_modrm = onebyte_has_modrm[*insn];
1317 details->opcode_len = 1;
1318 }
1319
1320 if (need_modrm)
1321 {
1322 ++insn;
1323 details->modrm_offset = insn - start;
1324 }
1325}
1326
1327/* Update %rip-relative addressing in INSN.
1328
1329 %rip-relative addressing only uses a 32-bit displacement.
1330 32 bits is not enough to be guaranteed to cover the distance between where
1331 the real instruction is and where its copy is.
1332 Convert the insn to use base+disp addressing.
1333 We set base = pc + insn_length so we can leave disp unchanged. */
c4f35dd8 1334
35669430 1335static void
cfba9872 1336fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc,
35669430
DE		 1337 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1338{
1339 const struct amd64_insn *insn_details = &dsc->insn_details;
1340 int modrm_offset = insn_details->modrm_offset;
1341 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1342 CORE_ADDR rip_base;
35669430
DE		 1343 int insn_length;
1344 int arch_tmp_regno, tmp_regno;
1345 ULONGEST orig_value;
1346
1347 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1348 ++insn;
1349
1350 /* Compute the rip-relative address. */
cfba9872
SM		 1351 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (),
1352 dsc->insn_buf.size (), from);
35669430
DE		 1353 rip_base = from + insn_length;
1354
1355 /* We need a register to hold the address.
1356 Pick one not used in the insn.
1357 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1358 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1359 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1360
50a1fdd5
PA		 1361 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1362 static constexpr gdb_byte VEX3_NOT_B = 0x20;
1363
1364 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1365 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1366 is not r8-r15. */
1367 if (insn_details->enc_prefix_offset != -1)
1368 {
1369 gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset];
1370 if (rex_prefix_p (pfx[0]))
1371 pfx[0] &= ~REX_B;
1372 else if (vex3_prefix_p (pfx[0]))
1373 pfx[1] |= VEX3_NOT_B;
1374 else
1375 gdb_assert_not_reached ("unhandled prefix");
1376 }
35669430
DE		 1377
1378 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1379 dsc->tmp_regno = tmp_regno;
1380 dsc->tmp_save = orig_value;
1381 dsc->tmp_used = 1;
1382
1383 /* Convert the ModRM field to be base+disp. */
1384 dsc->insn_buf[modrm_offset] &= ~0xc7;
1385 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1386
1387 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1388
1389 if (debug_displaced)
1390 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
5af949e3
UW		 1391 "displaced: using temp reg %d, old value %s, new value %s\n",
1392 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1393 paddress (gdbarch, rip_base));
35669430
DE		 1394}
1395
1396static void
1397fixup_displaced_copy (struct gdbarch *gdbarch,
cfba9872 1398 amd64_displaced_step_closure *dsc,
35669430
DE		 1399 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1400{
1401 const struct amd64_insn *details = &dsc->insn_details;
1402
1403 if (details->modrm_offset != -1)
1404 {
1405 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1406
1407 if ((modrm & 0xc7) == 0x05)
1408 {
1409 /* The insn uses rip-relative addressing.
1410 Deal with it. */
1411 fixup_riprel (gdbarch, dsc, from, to, regs);
1412 }
1413 }
1414}
1415
1416struct displaced_step_closure *
1417amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1418 CORE_ADDR from, CORE_ADDR to,
1419 struct regcache *regs)
1420{
1421 int len = gdbarch_max_insn_length (gdbarch);
741e63d7 1422 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
35669430
DE		 1423 continually watch for running off the end of the buffer. */
1424 int fixup_sentinel_space = len;
cfba9872
SM		 1425 amd64_displaced_step_closure *dsc
1426 = new amd64_displaced_step_closure (len + fixup_sentinel_space);
35669430
DE		 1427 gdb_byte *buf = &dsc->insn_buf[0];
1428 struct amd64_insn *details = &dsc->insn_details;
1429
35669430
DE		 1430 read_memory (from, buf, len);
1431
1432 /* Set up the sentinel space so we don't have to worry about running
1433 off the end of the buffer. An excessive number of leading prefixes
1434 could otherwise cause this. */
1435 memset (buf + len, 0, fixup_sentinel_space);
1436
1437 amd64_get_insn_details (buf, details);
1438
1439 /* GDB may get control back after the insn after the syscall.
1440 Presumably this is a kernel bug.
1441 If this is a syscall, make sure there's a nop afterwards. */
1442 {
1443 int syscall_length;
1444
1445 if (amd64_syscall_p (details, &syscall_length))
1446 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1447 }
1448
1449 /* Modify the insn to cope with the address where it will be executed from.
1450 In particular, handle any rip-relative addressing. */
1451 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1452
1453 write_memory (to, buf, len);
1454
1455 if (debug_displaced)
1456 {
5af949e3
UW		 1457 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1458 paddress (gdbarch, from), paddress (gdbarch, to));
35669430
DE		 1459 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1460 }
1461
1462 return dsc;
1463}
1464
1465static int
1466amd64_absolute_jmp_p (const struct amd64_insn *details)
1467{
1468 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1469
1470 if (insn[0] == 0xff)
1471 {
1472 /* jump near, absolute indirect (/4) */
1473 if ((insn[1] & 0x38) == 0x20)
1474 return 1;
1475
1476 /* jump far, absolute indirect (/5) */
1477 if ((insn[1] & 0x38) == 0x28)
1478 return 1;
1479 }
1480
1481 return 0;
1482}
1483
c2170eef
MM		 1484/* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1485
1486static int
1487amd64_jmp_p (const struct amd64_insn *details)
1488{
1489 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1490
1491 /* jump short, relative. */
1492 if (insn[0] == 0xeb)
1493 return 1;
1494
1495 /* jump near, relative. */
1496 if (insn[0] == 0xe9)
1497 return 1;
1498
1499 return amd64_absolute_jmp_p (details);
1500}
1501
35669430
DE		 1502static int
1503amd64_absolute_call_p (const struct amd64_insn *details)
1504{
1505 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1506
1507 if (insn[0] == 0xff)
1508 {
1509 /* Call near, absolute indirect (/2) */
1510 if ((insn[1] & 0x38) == 0x10)
1511 return 1;
1512
1513 /* Call far, absolute indirect (/3) */
1514 if ((insn[1] & 0x38) == 0x18)
1515 return 1;
1516 }
1517
1518 return 0;
1519}
1520
1521static int
1522amd64_ret_p (const struct amd64_insn *details)
1523{
1524 /* NOTE: gcc can emit "repz ; ret". */
1525 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1526
1527 switch (insn[0])
1528 {
1529 case 0xc2: /* ret near, pop N bytes */
1530 case 0xc3: /* ret near */
1531 case 0xca: /* ret far, pop N bytes */
1532 case 0xcb: /* ret far */
1533 case 0xcf: /* iret */
1534 return 1;
1535
1536 default:
1537 return 0;
1538 }
1539}
1540
1541static int
1542amd64_call_p (const struct amd64_insn *details)
1543{
1544 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1545
1546 if (amd64_absolute_call_p (details))
1547 return 1;
1548
1549 /* call near, relative */
1550 if (insn[0] == 0xe8)
1551 return 1;
1552
1553 return 0;
1554}
1555
35669430
DE		 1556/* Return non-zero if INSN is a system call, and set *LENGTHP to its
1557 length in bytes. Otherwise, return zero. */
1558
1559static int
1560amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1561{
1562 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1563
1564 if (insn[0] == 0x0f && insn[1] == 0x05)
1565 {
1566 *lengthp = 2;
1567 return 1;
1568 }
1569
1570 return 0;
1571}
1572
c2170eef
MM		 1573/* Classify the instruction at ADDR using PRED.
1574 Throw an error if the memory can't be read. */
1575
1576static int
1577amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1578 int (*pred) (const struct amd64_insn *))
1579{
1580 struct amd64_insn details;
1581 gdb_byte *buf;
1582 int len, classification;
1583
1584 len = gdbarch_max_insn_length (gdbarch);
224c3ddb 1585 buf = (gdb_byte *) alloca (len);
c2170eef
MM		 1586
1587 read_code (addr, buf, len);
1588 amd64_get_insn_details (buf, &details);
1589
1590 classification = pred (&details);
1591
1592 return classification;
1593}
1594
1595/* The gdbarch insn_is_call method. */
1596
1597static int
1598amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1599{
1600 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1601}
1602
1603/* The gdbarch insn_is_ret method. */
1604
1605static int
1606amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1607{
1608 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1609}
1610
1611/* The gdbarch insn_is_jump method. */
1612
1613static int
1614amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1615{
1616 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1617}
1618
35669430
DE		 1619/* Fix up the state of registers and memory after having single-stepped
1620 a displaced instruction. */
1621
1622void
1623amd64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 1624 struct displaced_step_closure *dsc_,
35669430
DE		 1625 CORE_ADDR from, CORE_ADDR to,
1626 struct regcache *regs)
1627{
cfba9872 1628 amd64_displaced_step_closure *dsc = (amd64_displaced_step_closure *) dsc_;
e17a4113 1629 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
35669430
DE		 1630 /* The offset we applied to the instruction's address. */
1631 ULONGEST insn_offset = to - from;
cfba9872 1632 gdb_byte *insn = dsc->insn_buf.data ();
35669430
DE		 1633 const struct amd64_insn *insn_details = &dsc->insn_details;
1634
1635 if (debug_displaced)
1636 fprintf_unfiltered (gdb_stdlog,
5af949e3 1637 "displaced: fixup (%s, %s), "
35669430 1638 "insn = 0x%02x 0x%02x ...\n",
5af949e3
UW		 1639 paddress (gdbarch, from), paddress (gdbarch, to),
1640 insn[0], insn[1]);
35669430
DE		 1641
1642 /* If we used a tmp reg, restore it. */
1643
1644 if (dsc->tmp_used)
1645 {
1646 if (debug_displaced)
5af949e3
UW		 1647 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1648 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
35669430
DE		 1649 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1650 }
1651
1652 /* The list of issues to contend with here is taken from
1653 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1654 Yay for Free Software! */
1655
1656 /* Relocate the %rip back to the program's instruction stream,
1657 if necessary. */
1658
1659 /* Except in the case of absolute or indirect jump or call
1660 instructions, or a return instruction, the new rip is relative to
1661 the displaced instruction; make it relative to the original insn.
1662 Well, signal handler returns don't need relocation either, but we use the
1663 value of %rip to recognize those; see below. */
1664 if (! amd64_absolute_jmp_p (insn_details)
1665 && ! amd64_absolute_call_p (insn_details)
1666 && ! amd64_ret_p (insn_details))
1667 {
1668 ULONGEST orig_rip;
1669 int insn_len;
1670
1671 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1672
1673 /* A signal trampoline system call changes the %rip, resuming
1674 execution of the main program after the signal handler has
1675 returned. That makes them like 'return' instructions; we
1676 shouldn't relocate %rip.
1677
1678 But most system calls don't, and we do need to relocate %rip.
1679
1680 Our heuristic for distinguishing these cases: if stepping
1681 over the system call instruction left control directly after
1682 the instruction, the we relocate --- control almost certainly
1683 doesn't belong in the displaced copy. Otherwise, we assume
1684 the instruction has put control where it belongs, and leave
1685 it unrelocated. Goodness help us if there are PC-relative
1686 system calls. */
1687 if (amd64_syscall_p (insn_details, &insn_len)
1688 && orig_rip != to + insn_len
1689 /* GDB can get control back after the insn after the syscall.
1690 Presumably this is a kernel bug.
1691 Fixup ensures its a nop, we add one to the length for it. */
1692 && orig_rip != to + insn_len + 1)
1693 {
1694 if (debug_displaced)
1695 fprintf_unfiltered (gdb_stdlog,
1696 "displaced: syscall changed %%rip; "
1697 "not relocating\n");
1698 }
1699 else
1700 {
1701 ULONGEST rip = orig_rip - insn_offset;
1702
1903f0e6
DE		 1703 /* If we just stepped over a breakpoint insn, we don't backup
1704 the pc on purpose; this is to match behaviour without
1705 stepping. */
35669430
DE		 1706
1707 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1708
1709 if (debug_displaced)
1710 fprintf_unfiltered (gdb_stdlog,
1711 "displaced: "
5af949e3
UW		 1712 "relocated %%rip from %s to %s\n",
1713 paddress (gdbarch, orig_rip),
1714 paddress (gdbarch, rip));
35669430
DE		 1715 }
1716 }
1717
1718 /* If the instruction was PUSHFL, then the TF bit will be set in the
1719 pushed value, and should be cleared. We'll leave this for later,
1720 since GDB already messes up the TF flag when stepping over a
1721 pushfl. */
1722
1723 /* If the instruction was a call, the return address now atop the
1724 stack is the address following the copied instruction. We need
1725 to make it the address following the original instruction. */
1726 if (amd64_call_p (insn_details))
1727 {
1728 ULONGEST rsp;
1729 ULONGEST retaddr;
1730 const ULONGEST retaddr_len = 8;
1731
1732 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
e17a4113 1733 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
4dafcdeb 1734 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
e17a4113 1735 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
35669430
DE		 1736
1737 if (debug_displaced)
1738 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1739 "displaced: relocated return addr at %s "
1740 "to %s\n",
1741 paddress (gdbarch, rsp),
1742 paddress (gdbarch, retaddr));
35669430
DE		 1743 }
1744}
dde08ee1
PA		 1745
1746/* If the instruction INSN uses RIP-relative addressing, return the
1747 offset into the raw INSN where the displacement to be adjusted is
1748 found. Returns 0 if the instruction doesn't use RIP-relative
1749 addressing. */
1750
1751static int
1752rip_relative_offset (struct amd64_insn *insn)
1753{
1754 if (insn->modrm_offset != -1)
1755 {
1756 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1757
1758 if ((modrm & 0xc7) == 0x05)
1759 {
1760 /* The displacement is found right after the ModRM byte. */
1761 return insn->modrm_offset + 1;
1762 }
1763 }
1764
1765 return 0;
1766}
1767
1768static void
1769append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1770{
1771 target_write_memory (*to, buf, len);
1772 *to += len;
1773}
1774
60965737 1775static void
dde08ee1
PA		 1776amd64_relocate_instruction (struct gdbarch *gdbarch,
1777 CORE_ADDR *to, CORE_ADDR oldloc)
1778{
1779 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1780 int len = gdbarch_max_insn_length (gdbarch);
1781 /* Extra space for sentinels. */
1782 int fixup_sentinel_space = len;
224c3ddb 1783 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
dde08ee1
PA		 1784 struct amd64_insn insn_details;
1785 int offset = 0;
1786 LONGEST rel32, newrel;
1787 gdb_byte *insn;
1788 int insn_length;
1789
1790 read_memory (oldloc, buf, len);
1791
1792 /* Set up the sentinel space so we don't have to worry about running
1793 off the end of the buffer. An excessive number of leading prefixes
1794 could otherwise cause this. */
1795 memset (buf + len, 0, fixup_sentinel_space);
1796
1797 insn = buf;
1798 amd64_get_insn_details (insn, &insn_details);
1799
1800 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1801
1802 /* Skip legacy instruction prefixes. */
1803 insn = amd64_skip_prefixes (insn);
1804
1805 /* Adjust calls with 32-bit relative addresses as push/jump, with
1806 the address pushed being the location where the original call in
1807 the user program would return to. */
1808 if (insn[0] == 0xe8)
1809 {
f077e978
PA		 1810 gdb_byte push_buf[32];
1811 CORE_ADDR ret_addr;
1812 int i = 0;
dde08ee1
PA		 1813
1814 /* Where "ret" in the original code will return to. */
1815 ret_addr = oldloc + insn_length;
f077e978
PA		 1816
1817 /* If pushing an address higher than or equal to 0x80000000,
1818 avoid 'pushq', as that sign extends its 32-bit operand, which
1819 would be incorrect. */
1820 if (ret_addr <= 0x7fffffff)
1821 {
1822 push_buf[0] = 0x68; /* pushq $... */
1823 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1824 i = 5;
1825 }
1826 else
1827 {
1828 push_buf[i++] = 0x48; /* sub $0x8,%rsp */
1829 push_buf[i++] = 0x83;
1830 push_buf[i++] = 0xec;
1831 push_buf[i++] = 0x08;
1832
1833 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */
1834 push_buf[i++] = 0x04;
1835 push_buf[i++] = 0x24;
1836 store_unsigned_integer (&push_buf[i], 4, byte_order,
1837 ret_addr & 0xffffffff);
1838 i += 4;
1839
1840 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */
1841 push_buf[i++] = 0x44;
1842 push_buf[i++] = 0x24;
1843 push_buf[i++] = 0x04;
1844 store_unsigned_integer (&push_buf[i], 4, byte_order,
1845 ret_addr >> 32);
1846 i += 4;
1847 }
1848 gdb_assert (i <= sizeof (push_buf));
dde08ee1 1849 /* Push the push. */
f077e978 1850 append_insns (to, i, push_buf);
dde08ee1
PA		 1851
1852 /* Convert the relative call to a relative jump. */
1853 insn[0] = 0xe9;
1854
1855 /* Adjust the destination offset. */
1856 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1857 newrel = (oldloc - *to) + rel32;
f4a1794a
KY		 1858 store_signed_integer (insn + 1, 4, byte_order, newrel);
1859
1860 if (debug_displaced)
1861 fprintf_unfiltered (gdb_stdlog,
1862 "Adjusted insn rel32=%s at %s to"
1863 " rel32=%s at %s\n",
1864 hex_string (rel32), paddress (gdbarch, oldloc),
1865 hex_string (newrel), paddress (gdbarch, *to));
dde08ee1
PA		 1866
1867 /* Write the adjusted jump into its displaced location. */
1868 append_insns (to, 5, insn);
1869 return;
1870 }
1871
1872 offset = rip_relative_offset (&insn_details);
1873 if (!offset)
1874 {
1875 /* Adjust jumps with 32-bit relative addresses. Calls are
1876 already handled above. */
1877 if (insn[0] == 0xe9)
1878 offset = 1;
1879 /* Adjust conditional jumps. */
1880 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1881 offset = 2;
1882 }
1883
1884 if (offset)
1885 {
1886 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1887 newrel = (oldloc - *to) + rel32;
f4a1794a 1888 store_signed_integer (insn + offset, 4, byte_order, newrel);
dde08ee1
PA		 1889 if (debug_displaced)
1890 fprintf_unfiltered (gdb_stdlog,
f4a1794a
KY		 1891 "Adjusted insn rel32=%s at %s to"
1892 " rel32=%s at %s\n",
dde08ee1
PA		 1893 hex_string (rel32), paddress (gdbarch, oldloc),
1894 hex_string (newrel), paddress (gdbarch, *to));
1895 }
1896
1897 /* Write the adjusted instruction into its displaced location. */
1898 append_insns (to, insn_length, buf);
1899}
1900
35669430 1901\f
c4f35dd8 1902/* The maximum number of saved registers. This should include %rip. */
90f90721 1903#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
c4f35dd8 1904
e53bef9f 1905struct amd64_frame_cache
c4f35dd8
MK		 1906{
1907 /* Base address. */
1908 CORE_ADDR base;
8fbca658 1909 int base_p;
c4f35dd8
MK		 1910 CORE_ADDR sp_offset;
1911 CORE_ADDR pc;
1912
1913 /* Saved registers. */
e53bef9f 1914 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
c4f35dd8 1915 CORE_ADDR saved_sp;
e0c62198 1916 int saved_sp_reg;
c4f35dd8
MK		 1917
1918 /* Do we have a frame? */
1919 int frameless_p;
1920};
8dda9770 1921
d2449ee8 1922/* Initialize a frame cache. */
c4f35dd8 1923
d2449ee8
DJ		 1924static void
1925amd64_init_frame_cache (struct amd64_frame_cache *cache)
8dda9770 1926{
c4f35dd8
MK		 1927 int i;
1928
c4f35dd8
MK		 1929 /* Base address. */
1930 cache->base = 0;
8fbca658 1931 cache->base_p = 0;
c4f35dd8
MK		 1932 cache->sp_offset = -8;
1933 cache->pc = 0;
1934
1935 /* Saved registers. We initialize these to -1 since zero is a valid
bba66b87
DE		 1936 offset (that's where %rbp is supposed to be stored).
1937 The values start out as being offsets, and are later converted to
1938 addresses (at which point -1 is interpreted as an address, still meaning
1939 "invalid"). */
e53bef9f 1940 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 1941 cache->saved_regs[i] = -1;
1942 cache->saved_sp = 0;
e0c62198 1943 cache->saved_sp_reg = -1;
c4f35dd8
MK		 1944
1945 /* Frameless until proven otherwise. */
1946 cache->frameless_p = 1;
d2449ee8 1947}
c4f35dd8 1948
d2449ee8
DJ		 1949/* Allocate and initialize a frame cache. */
1950
1951static struct amd64_frame_cache *
1952amd64_alloc_frame_cache (void)
1953{
1954 struct amd64_frame_cache *cache;
1955
1956 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1957 amd64_init_frame_cache (cache);
c4f35dd8 1958 return cache;
8dda9770 1959}
53e95fcf 1960
e0c62198
L		 1961/* GCC 4.4 and later, can put code in the prologue to realign the
1962 stack pointer. Check whether PC points to such code, and update
1963 CACHE accordingly. Return the first instruction after the code
1964 sequence or CURRENT_PC, whichever is smaller. If we don't
1965 recognize the code, return PC. */
1966
1967static CORE_ADDR
1968amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1969 struct amd64_frame_cache *cache)
1970{
1971 /* There are 2 code sequences to re-align stack before the frame
1972 gets set up:
1973
1974 1. Use a caller-saved saved register:
1975
1976 leaq 8(%rsp), %reg
1977 andq $-XXX, %rsp
1978 pushq -8(%reg)
1979
1980 2. Use a callee-saved saved register:
1981
1982 pushq %reg
1983 leaq 16(%rsp), %reg
1984 andq $-XXX, %rsp
1985 pushq -8(%reg)
1986
1987 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1988
1989 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1990 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1991 */
1992
1993 gdb_byte buf[18];
1994 int reg, r;
1995 int offset, offset_and;
e0c62198 1996
bae8a07a 1997 if (target_read_code (pc, buf, sizeof buf))
e0c62198
L		 1998 return pc;
1999
2000 /* Check caller-saved saved register. The first instruction has
2001 to be "leaq 8(%rsp), %reg". */
2002 if ((buf[0] & 0xfb) == 0x48
2003 && buf[1] == 0x8d
2004 && buf[3] == 0x24
2005 && buf[4] == 0x8)
2006 {
2007 /* MOD must be binary 10 and R/M must be binary 100. */
2008 if ((buf[2] & 0xc7) != 0x44)
2009 return pc;
2010
2011 /* REG has register number. */
2012 reg = (buf[2] >> 3) & 7;
2013
2014 /* Check the REX.R bit. */
2015 if (buf[0] == 0x4c)
2016 reg += 8;
2017
2018 offset = 5;
2019 }
2020 else
2021 {
2022 /* Check callee-saved saved register. The first instruction
2023 has to be "pushq %reg". */
2024 reg = 0;
2025 if ((buf[0] & 0xf8) == 0x50)
2026 offset = 0;
2027 else if ((buf[0] & 0xf6) == 0x40
2028 && (buf[1] & 0xf8) == 0x50)
2029 {
2030 /* Check the REX.B bit. */
2031 if ((buf[0] & 1) != 0)
2032 reg = 8;
2033
2034 offset = 1;
2035 }
2036 else
2037 return pc;
2038
2039 /* Get register. */
2040 reg += buf[offset] & 0x7;
2041
2042 offset++;
2043
2044 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2045 if ((buf[offset] & 0xfb) != 0x48
2046 || buf[offset + 1] != 0x8d
2047 || buf[offset + 3] != 0x24
2048 || buf[offset + 4] != 0x10)
2049 return pc;
2050
2051 /* MOD must be binary 10 and R/M must be binary 100. */
2052 if ((buf[offset + 2] & 0xc7) != 0x44)
2053 return pc;
2054
2055 /* REG has register number. */
2056 r = (buf[offset + 2] >> 3) & 7;
2057
2058 /* Check the REX.R bit. */
2059 if (buf[offset] == 0x4c)
2060 r += 8;
2061
2062 /* Registers in pushq and leaq have to be the same. */
2063 if (reg != r)
2064 return pc;
2065
2066 offset += 5;
2067 }
2068
2069 /* Rigister can't be %rsp nor %rbp. */
2070 if (reg == 4 || reg == 5)
2071 return pc;
2072
2073 /* The next instruction has to be "andq $-XXX, %rsp". */
2074 if (buf[offset] != 0x48
2075 || buf[offset + 2] != 0xe4
2076 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2077 return pc;
2078
2079 offset_and = offset;
2080 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2081
2082 /* The next instruction has to be "pushq -8(%reg)". */
2083 r = 0;
2084 if (buf[offset] == 0xff)
2085 offset++;
2086 else if ((buf[offset] & 0xf6) == 0x40
2087 && buf[offset + 1] == 0xff)
2088 {
2089 /* Check the REX.B bit. */
2090 if ((buf[offset] & 0x1) != 0)
2091 r = 8;
2092 offset += 2;
2093 }
2094 else
2095 return pc;
2096
2097 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2098 01. */
2099 if (buf[offset + 1] != 0xf8
2100 || (buf[offset] & 0xf8) != 0x70)
2101 return pc;
2102
2103 /* R/M has register. */
2104 r += buf[offset] & 7;
2105
2106 /* Registers in leaq and pushq have to be the same. */
2107 if (reg != r)
2108 return pc;
2109
2110 if (current_pc > pc + offset_and)
35669430 2111 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
e0c62198 2112
325fac50 2113 return std::min (pc + offset + 2, current_pc);
e0c62198
L		 2114}
2115
ac142d96
L		 2116/* Similar to amd64_analyze_stack_align for x32. */
2117
2118static CORE_ADDR
2119amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2120 struct amd64_frame_cache *cache)
2121{
2122 /* There are 2 code sequences to re-align stack before the frame
2123 gets set up:
2124
2125 1. Use a caller-saved saved register:
2126
2127 leaq 8(%rsp), %reg
2128 andq $-XXX, %rsp
2129 pushq -8(%reg)
2130
2131 or
2132
2133 [addr32] leal 8(%rsp), %reg
2134 andl $-XXX, %esp
2135 [addr32] pushq -8(%reg)
2136
2137 2. Use a callee-saved saved register:
2138
2139 pushq %reg
2140 leaq 16(%rsp), %reg
2141 andq $-XXX, %rsp
2142 pushq -8(%reg)
2143
2144 or
2145
2146 pushq %reg
2147 [addr32] leal 16(%rsp), %reg
2148 andl $-XXX, %esp
2149 [addr32] pushq -8(%reg)
2150
2151 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2152
2153 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2154 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2155
2156 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2157
2158 0x83 0xe4 0xf0 andl $-16, %esp
2159 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2160 */
2161
2162 gdb_byte buf[19];
2163 int reg, r;
2164 int offset, offset_and;
2165
2166 if (target_read_memory (pc, buf, sizeof buf))
2167 return pc;
2168
2169 /* Skip optional addr32 prefix. */
2170 offset = buf[0] == 0x67 ? 1 : 0;
2171
2172 /* Check caller-saved saved register. The first instruction has
2173 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2174 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2175 && buf[offset + 1] == 0x8d
2176 && buf[offset + 3] == 0x24
2177 && buf[offset + 4] == 0x8)
2178 {
2179 /* MOD must be binary 10 and R/M must be binary 100. */
2180 if ((buf[offset + 2] & 0xc7) != 0x44)
2181 return pc;
2182
2183 /* REG has register number. */
2184 reg = (buf[offset + 2] >> 3) & 7;
2185
2186 /* Check the REX.R bit. */
2187 if ((buf[offset] & 0x4) != 0)
2188 reg += 8;
2189
2190 offset += 5;
2191 }
2192 else
2193 {
2194 /* Check callee-saved saved register. The first instruction
2195 has to be "pushq %reg". */
2196 reg = 0;
2197 if ((buf[offset] & 0xf6) == 0x40
2198 && (buf[offset + 1] & 0xf8) == 0x50)
2199 {
2200 /* Check the REX.B bit. */
2201 if ((buf[offset] & 1) != 0)
2202 reg = 8;
2203
2204 offset += 1;
2205 }
2206 else if ((buf[offset] & 0xf8) != 0x50)
2207 return pc;
2208
2209 /* Get register. */
2210 reg += buf[offset] & 0x7;
2211
2212 offset++;
2213
2214 /* Skip optional addr32 prefix. */
2215 if (buf[offset] == 0x67)
2216 offset++;
2217
2218 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2219 "leal 16(%rsp), %reg". */
2220 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2221 || buf[offset + 1] != 0x8d
2222 || buf[offset + 3] != 0x24
2223 || buf[offset + 4] != 0x10)
2224 return pc;
2225
2226 /* MOD must be binary 10 and R/M must be binary 100. */
2227 if ((buf[offset + 2] & 0xc7) != 0x44)
2228 return pc;
2229
2230 /* REG has register number. */
2231 r = (buf[offset + 2] >> 3) & 7;
2232
2233 /* Check the REX.R bit. */
2234 if ((buf[offset] & 0x4) != 0)
2235 r += 8;
2236
2237 /* Registers in pushq and leaq have to be the same. */
2238 if (reg != r)
2239 return pc;
2240
2241 offset += 5;
2242 }
2243
2244 /* Rigister can't be %rsp nor %rbp. */
2245 if (reg == 4 || reg == 5)
2246 return pc;
2247
2248 /* The next instruction may be "andq $-XXX, %rsp" or
2249 "andl $-XXX, %esp". */
2250 if (buf[offset] != 0x48)
2251 offset--;
2252
2253 if (buf[offset + 2] != 0xe4
2254 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2255 return pc;
2256
2257 offset_and = offset;
2258 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2259
2260 /* Skip optional addr32 prefix. */
2261 if (buf[offset] == 0x67)
2262 offset++;
2263
2264 /* The next instruction has to be "pushq -8(%reg)". */
2265 r = 0;
2266 if (buf[offset] == 0xff)
2267 offset++;
2268 else if ((buf[offset] & 0xf6) == 0x40
2269 && buf[offset + 1] == 0xff)
2270 {
2271 /* Check the REX.B bit. */
2272 if ((buf[offset] & 0x1) != 0)
2273 r = 8;
2274 offset += 2;
2275 }
2276 else
2277 return pc;
2278
2279 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2280 01. */
2281 if (buf[offset + 1] != 0xf8
2282 || (buf[offset] & 0xf8) != 0x70)
2283 return pc;
2284
2285 /* R/M has register. */
2286 r += buf[offset] & 7;
2287
2288 /* Registers in leaq and pushq have to be the same. */
2289 if (reg != r)
2290 return pc;
2291
2292 if (current_pc > pc + offset_and)
2293 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2294
325fac50 2295 return std::min (pc + offset + 2, current_pc);
ac142d96
L		 2296}
2297
c4f35dd8
MK		 2298/* Do a limited analysis of the prologue at PC and update CACHE
2299 accordingly. Bail out early if CURRENT_PC is reached. Return the
2300 address where the analysis stopped.
2301
2302 We will handle only functions beginning with:
2303
2304 pushq %rbp 0x55
50f1ae7b 2305 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
c4f35dd8 2306
649e6d92
MK		 2307 or (for the X32 ABI):
2308
2309 pushq %rbp 0x55
2310 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2311
2312 Any function that doesn't start with one of these sequences will be
2313 assumed to have no prologue and thus no valid frame pointer in
2314 %rbp. */
c4f35dd8
MK		 2315
2316static CORE_ADDR
e17a4113
UW		 2317amd64_analyze_prologue (struct gdbarch *gdbarch,
2318 CORE_ADDR pc, CORE_ADDR current_pc,
e53bef9f 2319 struct amd64_frame_cache *cache)
53e95fcf 2320{
e17a4113 2321 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
50f1ae7b
DE		 2322 /* There are two variations of movq %rsp, %rbp. */
2323 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2324 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
649e6d92
MK		 2325 /* Ditto for movl %esp, %ebp. */
2326 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2327 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2328
d8de1ef7
MK		 2329 gdb_byte buf[3];
2330 gdb_byte op;
c4f35dd8
MK		 2331
2332 if (current_pc <= pc)
2333 return current_pc;
2334
ac142d96
L		 2335 if (gdbarch_ptr_bit (gdbarch) == 32)
2336 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2337 else
2338 pc = amd64_analyze_stack_align (pc, current_pc, cache);
e0c62198 2339
bae8a07a 2340 op = read_code_unsigned_integer (pc, 1, byte_order);
c4f35dd8
MK		 2341
2342 if (op == 0x55) /* pushq %rbp */
2343 {
2344 /* Take into account that we've executed the `pushq %rbp' that
2345 starts this instruction sequence. */
90f90721 2346 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
c4f35dd8
MK		 2347 cache->sp_offset += 8;
2348
2349 /* If that's all, return now. */
2350 if (current_pc <= pc + 1)
2351 return current_pc;
2352
bae8a07a 2353 read_code (pc + 1, buf, 3);
c4f35dd8 2354
649e6d92
MK		 2355 /* Check for `movq %rsp, %rbp'. */
2356 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2357 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2358 {
2359 /* OK, we actually have a frame. */
2360 cache->frameless_p = 0;
2361 return pc + 4;
2362 }
2363
2364 /* For X32, also check for `movq %esp, %ebp'. */
2365 if (gdbarch_ptr_bit (gdbarch) == 32)
2366 {
2367 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2368 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2369 {
2370 /* OK, we actually have a frame. */
2371 cache->frameless_p = 0;
2372 return pc + 3;
2373 }
2374 }
2375
2376 return pc + 1;
c4f35dd8
MK		 2377 }
2378
2379 return pc;
53e95fcf
JS		 2380}
2381
df15bd07
JK		 2382/* Work around false termination of prologue - GCC PR debug/48827.
2383
2384 START_PC is the first instruction of a function, PC is its minimal already
2385 determined advanced address. Function returns PC if it has nothing to do.
2386
2387 84 c0 test %al,%al
2388 74 23 je after
2389 <-- here is 0 lines advance - the false prologue end marker.
2390 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2391 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2392 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2393 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2394 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2395 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2396 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2397 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2398 after: */
c4f35dd8
MK		 2399
2400static CORE_ADDR
df15bd07 2401amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
53e95fcf 2402{
08711b9a
JK		 2403 struct symtab_and_line start_pc_sal, next_sal;
2404 gdb_byte buf[4 + 8 * 7];
2405 int offset, xmmreg;
c4f35dd8 2406
08711b9a
JK		 2407 if (pc == start_pc)
2408 return pc;
2409
2410 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2411 if (start_pc_sal.symtab == NULL
43f3e411
DE		 2412 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2413 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
08711b9a
JK		 2414 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2415 return pc;
2416
2417 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2418 if (next_sal.line != start_pc_sal.line)
2419 return pc;
2420
2421 /* START_PC can be from overlayed memory, ignored here. */
bae8a07a 2422 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
08711b9a
JK		 2423 return pc;
2424
2425 /* test %al,%al */
2426 if (buf[0] != 0x84 || buf[1] != 0xc0)
2427 return pc;
2428 /* je AFTER */
2429 if (buf[2] != 0x74)
2430 return pc;
2431
2432 offset = 4;
2433 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2434 {
bede5f5f 2435 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
08711b9a 2436 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
bede5f5f 2437 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
08711b9a
JK		 2438 return pc;
2439
bede5f5f
JK		 2440 /* 0b01?????? */
2441 if ((buf[offset + 2] & 0xc0) == 0x40)
08711b9a
JK		 2442 {
2443 /* 8-bit displacement. */
2444 offset += 4;
2445 }
bede5f5f
JK		 2446 /* 0b10?????? */
2447 else if ((buf[offset + 2] & 0xc0) == 0x80)
08711b9a
JK		 2448 {
2449 /* 32-bit displacement. */
2450 offset += 7;
2451 }
2452 else
2453 return pc;
2454 }
2455
2456 /* je AFTER */
2457 if (offset - 4 != buf[3])
2458 return pc;
2459
2460 return next_sal.end;
53e95fcf 2461}
df15bd07
JK		 2462
2463/* Return PC of first real instruction. */
2464
2465static CORE_ADDR
2466amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2467{
2468 struct amd64_frame_cache cache;
2469 CORE_ADDR pc;
56bf0743
KB		 2470 CORE_ADDR func_addr;
2471
2472 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2473 {
2474 CORE_ADDR post_prologue_pc
2475 = skip_prologue_using_sal (gdbarch, func_addr);
43f3e411 2476 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
56bf0743
KB		 2477
2478 /* Clang always emits a line note before the prologue and another
2479 one after. We trust clang to emit usable line notes. */
2480 if (post_prologue_pc
43f3e411
DE		 2481 && (cust != NULL
2482 && COMPUNIT_PRODUCER (cust) != NULL
61012eef 2483 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
325fac50 2484 return std::max (start_pc, post_prologue_pc);
56bf0743 2485 }
df15bd07
JK		 2486
2487 amd64_init_frame_cache (&cache);
2488 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2489 &cache);
2490 if (cache.frameless_p)
2491 return start_pc;
2492
2493 return amd64_skip_xmm_prologue (pc, start_pc);
2494}
c4f35dd8 2495\f
53e95fcf 2496
c4f35dd8
MK		 2497/* Normal frames. */
2498
8fbca658
PA		 2499static void
2500amd64_frame_cache_1 (struct frame_info *this_frame,
2501 struct amd64_frame_cache *cache)
6d686a84 2502{
e17a4113
UW		 2503 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2504 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 2505 gdb_byte buf[8];
6d686a84 2506 int i;
6d686a84 2507
10458914 2508 cache->pc = get_frame_func (this_frame);
c4f35dd8 2509 if (cache->pc != 0)
e17a4113
UW		 2510 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2511 cache);
c4f35dd8
MK		 2512
2513 if (cache->frameless_p)
2514 {
4a28816e
MK		 2515 /* We didn't find a valid frame. If we're at the start of a
2516 function, or somewhere half-way its prologue, the function's
2517 frame probably hasn't been fully setup yet. Try to
2518 reconstruct the base address for the stack frame by looking
2519 at the stack pointer. For truly "frameless" functions this
2520 might work too. */
c4f35dd8 2521
e0c62198
L		 2522 if (cache->saved_sp_reg != -1)
2523 {
8fbca658
PA		 2524 /* Stack pointer has been saved. */
2525 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2526 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2527
e0c62198
L		 2528 /* We're halfway aligning the stack. */
2529 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2530 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2531
2532 /* This will be added back below. */
2533 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2534 }
2535 else
2536 {
2537 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
e17a4113
UW		 2538 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2539 + cache->sp_offset;
e0c62198 2540 }
c4f35dd8 2541 }
35883a3f
MK		 2542 else
2543 {
10458914 2544 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
e17a4113 2545 cache->base = extract_unsigned_integer (buf, 8, byte_order);
35883a3f 2546 }
c4f35dd8
MK		 2547
2548 /* Now that we have the base address for the stack frame we can
2549 calculate the value of %rsp in the calling frame. */
2550 cache->saved_sp = cache->base + 16;
2551
35883a3f
MK		 2552 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2553 frame we find it at the same offset from the reconstructed base
e0c62198
L		 2554 address. If we're halfway aligning the stack, %rip is handled
2555 differently (see above). */
2556 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2557 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
35883a3f 2558
c4f35dd8
MK		 2559 /* Adjust all the saved registers such that they contain addresses
2560 instead of offsets. */
e53bef9f 2561 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 2562 if (cache->saved_regs[i] != -1)
2563 cache->saved_regs[i] += cache->base;
2564
8fbca658
PA		 2565 cache->base_p = 1;
2566}
2567
2568static struct amd64_frame_cache *
2569amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2570{
8fbca658
PA		 2571 struct amd64_frame_cache *cache;
2572
2573 if (*this_cache)
9a3c8263 2574 return (struct amd64_frame_cache *) *this_cache;
8fbca658
PA		 2575
2576 cache = amd64_alloc_frame_cache ();
2577 *this_cache = cache;
2578
492d29ea 2579 TRY
8fbca658
PA		 2580 {
2581 amd64_frame_cache_1 (this_frame, cache);
2582 }
492d29ea 2583 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2584 {
2585 if (ex.error != NOT_AVAILABLE_ERROR)
2586 throw_exception (ex);
2587 }
492d29ea 2588 END_CATCH
8fbca658 2589
c4f35dd8 2590 return cache;
6d686a84
ML		 2591}
2592
8fbca658
PA		 2593static enum unwind_stop_reason
2594amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2595 void **this_cache)
2596{
2597 struct amd64_frame_cache *cache =
2598 amd64_frame_cache (this_frame, this_cache);
2599
2600 if (!cache->base_p)
2601 return UNWIND_UNAVAILABLE;
2602
2603 /* This marks the outermost frame. */
2604 if (cache->base == 0)
2605 return UNWIND_OUTERMOST;
2606
2607 return UNWIND_NO_REASON;
2608}
2609
c4f35dd8 2610static void
10458914 2611amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
e53bef9f 2612 struct frame_id *this_id)
c4f35dd8 2613{
e53bef9f 2614 struct amd64_frame_cache *cache =
10458914 2615 amd64_frame_cache (this_frame, this_cache);
c4f35dd8 2616
8fbca658 2617 if (!cache->base_p)
5ce0145d
PA		 2618 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2619 else if (cache->base == 0)
2620 {
2621 /* This marks the outermost frame. */
2622 return;
2623 }
2624 else
2625 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
c4f35dd8 2626}
e76e1718 2627
10458914
DJ		 2628static struct value *
2629amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2630 int regnum)
53e95fcf 2631{
10458914 2632 struct gdbarch *gdbarch = get_frame_arch (this_frame);
e53bef9f 2633 struct amd64_frame_cache *cache =
10458914 2634 amd64_frame_cache (this_frame, this_cache);
e76e1718 2635
c4f35dd8 2636 gdb_assert (regnum >= 0);
b1ab997b 2637
2ae02b47 2638 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
10458914 2639 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
e76e1718 2640
e53bef9f 2641 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
10458914
DJ		 2642 return frame_unwind_got_memory (this_frame, regnum,
2643 cache->saved_regs[regnum]);
e76e1718 2644
10458914 2645 return frame_unwind_got_register (this_frame, regnum, regnum);
c4f35dd8 2646}
e76e1718 2647
e53bef9f 2648static const struct frame_unwind amd64_frame_unwind =
c4f35dd8
MK		 2649{
2650 NORMAL_FRAME,
8fbca658 2651 amd64_frame_unwind_stop_reason,
e53bef9f 2652 amd64_frame_this_id,
10458914
DJ		 2653 amd64_frame_prev_register,
2654 NULL,
2655 default_frame_sniffer
c4f35dd8 2656};
c4f35dd8 2657\f
6710bf39
SS		 2658/* Generate a bytecode expression to get the value of the saved PC. */
2659
2660static void
2661amd64_gen_return_address (struct gdbarch *gdbarch,
2662 struct agent_expr *ax, struct axs_value *value,
2663 CORE_ADDR scope)
2664{
2665 /* The following sequence assumes the traditional use of the base
2666 register. */
2667 ax_reg (ax, AMD64_RBP_REGNUM);
2668 ax_const_l (ax, 8);
2669 ax_simple (ax, aop_add);
2670 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2671 value->kind = axs_lvalue_memory;
2672}
2673\f
e76e1718 2674
c4f35dd8
MK		 2675/* Signal trampolines. */
2676
2677/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2678 64-bit variants. This would require using identical frame caches
2679 on both platforms. */
2680
e53bef9f 2681static struct amd64_frame_cache *
10458914 2682amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2683{
e17a4113
UW		 2684 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2685 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2686 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e53bef9f 2687 struct amd64_frame_cache *cache;
c4f35dd8 2688 CORE_ADDR addr;
d8de1ef7 2689 gdb_byte buf[8];
2b5e0749 2690 int i;
c4f35dd8
MK		 2691
2692 if (*this_cache)
9a3c8263 2693 return (struct amd64_frame_cache *) *this_cache;
c4f35dd8 2694
e53bef9f 2695 cache = amd64_alloc_frame_cache ();
c4f35dd8 2696
492d29ea 2697 TRY
8fbca658
PA		 2698 {
2699 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2700 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2701
2702 addr = tdep->sigcontext_addr (this_frame);
2703 gdb_assert (tdep->sc_reg_offset);
2704 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2705 for (i = 0; i < tdep->sc_num_regs; i++)
2706 if (tdep->sc_reg_offset[i] != -1)
2707 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
c4f35dd8 2708
8fbca658
PA		 2709 cache->base_p = 1;
2710 }
492d29ea 2711 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2712 {
2713 if (ex.error != NOT_AVAILABLE_ERROR)
2714 throw_exception (ex);
2715 }
492d29ea 2716 END_CATCH
c4f35dd8
MK		 2717
2718 *this_cache = cache;
2719 return cache;
53e95fcf
JS		 2720}
2721
8fbca658
PA		 2722static enum unwind_stop_reason
2723amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2724 void **this_cache)
2725{
2726 struct amd64_frame_cache *cache =
2727 amd64_sigtramp_frame_cache (this_frame, this_cache);
2728
2729 if (!cache->base_p)
2730 return UNWIND_UNAVAILABLE;
2731
2732 return UNWIND_NO_REASON;
2733}
2734
c4f35dd8 2735static void
10458914 2736amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
e53bef9f 2737 void **this_cache, struct frame_id *this_id)
c4f35dd8 2738{
e53bef9f 2739 struct amd64_frame_cache *cache =
10458914 2740 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2741
8fbca658 2742 if (!cache->base_p)
5ce0145d
PA		 2743 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2744 else if (cache->base == 0)
2745 {
2746 /* This marks the outermost frame. */
2747 return;
2748 }
2749 else
2750 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
c4f35dd8
MK		 2751}
2752
10458914
DJ		 2753static struct value *
2754amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2755 void **this_cache, int regnum)
c4f35dd8
MK		 2756{
2757 /* Make sure we've initialized the cache. */
10458914 2758 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2759
10458914 2760 return amd64_frame_prev_register (this_frame, this_cache, regnum);
c4f35dd8
MK		 2761}
2762
10458914
DJ		 2763static int
2764amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2765 struct frame_info *this_frame,
2766 void **this_cache)
c4f35dd8 2767{
10458914 2768 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
911bc6ee
MK		 2769
2770 /* We shouldn't even bother if we don't have a sigcontext_addr
2771 handler. */
2772 if (tdep->sigcontext_addr == NULL)
10458914 2773 return 0;
911bc6ee
MK		 2774
2775 if (tdep->sigtramp_p != NULL)
2776 {
10458914
DJ		 2777 if (tdep->sigtramp_p (this_frame))
2778 return 1;
911bc6ee 2779 }
c4f35dd8 2780
911bc6ee 2781 if (tdep->sigtramp_start != 0)
1c3545ae 2782 {
10458914 2783 CORE_ADDR pc = get_frame_pc (this_frame);
1c3545ae 2784
911bc6ee
MK		 2785 gdb_assert (tdep->sigtramp_end != 0);
2786 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
10458914 2787 return 1;
1c3545ae 2788 }
c4f35dd8 2789
10458914 2790 return 0;
c4f35dd8 2791}
10458914
DJ		 2792
2793static const struct frame_unwind amd64_sigtramp_frame_unwind =
2794{
2795 SIGTRAMP_FRAME,
8fbca658 2796 amd64_sigtramp_frame_unwind_stop_reason,
10458914
DJ		 2797 amd64_sigtramp_frame_this_id,
2798 amd64_sigtramp_frame_prev_register,
2799 NULL,
2800 amd64_sigtramp_frame_sniffer
2801};
c4f35dd8
MK		 2802\f
2803
2804static CORE_ADDR
10458914 2805amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2806{
e53bef9f 2807 struct amd64_frame_cache *cache =
10458914 2808 amd64_frame_cache (this_frame, this_cache);
c4f35dd8
MK		 2809
2810 return cache->base;
2811}
2812
e53bef9f 2813static const struct frame_base amd64_frame_base =
c4f35dd8 2814{
e53bef9f
MK		 2815 &amd64_frame_unwind,
2816 amd64_frame_base_address,
2817 amd64_frame_base_address,
2818 amd64_frame_base_address
c4f35dd8
MK		 2819};
2820
872761f4
MS		 2821/* Normal frames, but in a function epilogue. */
2822
c9cf6e20
MG		 2823/* Implement the stack_frame_destroyed_p gdbarch method.
2824
2825 The epilogue is defined here as the 'ret' instruction, which will
872761f4
MS		 2826 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2827 the function's stack frame. */
2828
2829static int
c9cf6e20 2830amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
872761f4
MS		 2831{
2832 gdb_byte insn;
43f3e411 2833 struct compunit_symtab *cust;
e0d00bc7 2834
43f3e411
DE		 2835 cust = find_pc_compunit_symtab (pc);
2836 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
e0d00bc7 2837 return 0;
872761f4
MS		 2838
2839 if (target_read_memory (pc, &insn, 1))
2840 return 0; /* Can't read memory at pc. */
2841
2842 if (insn != 0xc3) /* 'ret' instruction. */
2843 return 0;
2844
2845 return 1;
2846}
2847
2848static int
2849amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2850 struct frame_info *this_frame,
2851 void **this_prologue_cache)
2852{
2853 if (frame_relative_level (this_frame) == 0)
c9cf6e20
MG		 2854 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2855 get_frame_pc (this_frame));
872761f4
MS		 2856 else
2857 return 0;
2858}
2859
2860static struct amd64_frame_cache *
2861amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2862{
2863 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2864 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2865 struct amd64_frame_cache *cache;
6c10c06b 2866 gdb_byte buf[8];
872761f4
MS		 2867
2868 if (*this_cache)
9a3c8263 2869 return (struct amd64_frame_cache *) *this_cache;
872761f4
MS		 2870
2871 cache = amd64_alloc_frame_cache ();
2872 *this_cache = cache;
2873
492d29ea 2874 TRY
8fbca658
PA		 2875 {
2876 /* Cache base will be %esp plus cache->sp_offset (-8). */
2877 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2878 cache->base = extract_unsigned_integer (buf, 8,
2879 byte_order) + cache->sp_offset;
2880
2881 /* Cache pc will be the frame func. */
2882 cache->pc = get_frame_pc (this_frame);
872761f4 2883
8fbca658
PA		 2884 /* The saved %esp will be at cache->base plus 16. */
2885 cache->saved_sp = cache->base + 16;
872761f4 2886
8fbca658
PA		 2887 /* The saved %eip will be at cache->base plus 8. */
2888 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
872761f4 2889
8fbca658
PA		 2890 cache->base_p = 1;
2891 }
492d29ea 2892 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2893 {
2894 if (ex.error != NOT_AVAILABLE_ERROR)
2895 throw_exception (ex);
2896 }
492d29ea 2897 END_CATCH
872761f4
MS		 2898
2899 return cache;
2900}
2901
8fbca658
PA		 2902static enum unwind_stop_reason
2903amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2904 void **this_cache)
2905{
2906 struct amd64_frame_cache *cache
2907 = amd64_epilogue_frame_cache (this_frame, this_cache);
2908
2909 if (!cache->base_p)
2910 return UNWIND_UNAVAILABLE;
2911
2912 return UNWIND_NO_REASON;
2913}
2914
872761f4
MS		 2915static void
2916amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2917 void **this_cache,
2918 struct frame_id *this_id)
2919{
2920 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2921 this_cache);
2922
8fbca658 2923 if (!cache->base_p)
5ce0145d
PA		 2924 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2925 else
2926 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
872761f4
MS		 2927}
2928
2929static const struct frame_unwind amd64_epilogue_frame_unwind =
2930{
2931 NORMAL_FRAME,
8fbca658 2932 amd64_epilogue_frame_unwind_stop_reason,
872761f4
MS		 2933 amd64_epilogue_frame_this_id,
2934 amd64_frame_prev_register,
2935 NULL,
2936 amd64_epilogue_frame_sniffer
2937};
2938
166f4c7b 2939static struct frame_id
10458914 2940amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
166f4c7b 2941{
c4f35dd8
MK		 2942 CORE_ADDR fp;
2943
10458914 2944 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
c4f35dd8 2945
10458914 2946 return frame_id_build (fp + 16, get_frame_pc (this_frame));
166f4c7b
ML		 2947}
2948
8b148df9
AC		 2949/* 16 byte align the SP per frame requirements. */
2950
2951static CORE_ADDR
e53bef9f 2952amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
8b148df9
AC		 2953{
2954 return sp & -(CORE_ADDR)16;
2955}
473f17b0
MK		 2956\f
2957
593adc23
MK		 2958/* Supply register REGNUM from the buffer specified by FPREGS and LEN
2959 in the floating-point register set REGSET to register cache
2960 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
473f17b0
MK		 2961
2962static void
e53bef9f
MK		 2963amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2964 int regnum, const void *fpregs, size_t len)
473f17b0 2965{
ac7936df 2966 struct gdbarch *gdbarch = regcache->arch ();
09424cff 2967 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
473f17b0 2968
1528345d 2969 gdb_assert (len >= tdep->sizeof_fpregset);
90f90721 2970 amd64_supply_fxsave (regcache, regnum, fpregs);
473f17b0 2971}
8b148df9 2972
593adc23
MK		 2973/* Collect register REGNUM from the register cache REGCACHE and store
2974 it in the buffer specified by FPREGS and LEN as described by the
2975 floating-point register set REGSET. If REGNUM is -1, do this for
2976 all registers in REGSET. */
2977
2978static void
2979amd64_collect_fpregset (const struct regset *regset,
2980 const struct regcache *regcache,
2981 int regnum, void *fpregs, size_t len)
2982{
ac7936df 2983 struct gdbarch *gdbarch = regcache->arch ();
09424cff 2984 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
593adc23 2985
1528345d 2986 gdb_assert (len >= tdep->sizeof_fpregset);
593adc23
MK		 2987 amd64_collect_fxsave (regcache, regnum, fpregs);
2988}
2989
8f0435f7 2990const struct regset amd64_fpregset =
ecc37a5a
AA		 2991 {
2992 NULL, amd64_supply_fpregset, amd64_collect_fpregset
2993 };
c6b33596
MK		 2994\f
2995
436675d3
PA		 2996/* Figure out where the longjmp will land. Slurp the jmp_buf out of
2997 %rdi. We expect its value to be a pointer to the jmp_buf structure
2998 from which we extract the address that we will land at. This
2999 address is copied into PC. This routine returns non-zero on
3000 success. */
3001
3002static int
3003amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
3004{
3005 gdb_byte buf[8];
3006 CORE_ADDR jb_addr;
3007 struct gdbarch *gdbarch = get_frame_arch (frame);
3008 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
0dfff4cb 3009 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 3010
3011 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3012 longjmp will land. */
3013 if (jb_pc_offset == -1)
3014 return 0;
3015
3016 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
0dfff4cb
UW		 3017 jb_addr= extract_typed_address
3018 (buf, builtin_type (gdbarch)->builtin_data_ptr);
436675d3
PA		 3019 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
3020 return 0;
3021
0dfff4cb 3022 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 3023
3024 return 1;
3025}
3026
cf648174
HZ		 3027static const int amd64_record_regmap[] =
3028{
3029 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
3030 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
3031 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
3032 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
3033 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
3034 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
3035};
3036
2213a65d 3037void
c55a47e7 3038amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
a04b5337 3039 const target_desc *default_tdesc)
53e95fcf 3040{
0c1a73d6 3041 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
90884b2b 3042 const struct target_desc *tdesc = info.target_desc;
05c0465e
SDJ		 3043 static const char *const stap_integer_prefixes[] = { "$", NULL };
3044 static const char *const stap_register_prefixes[] = { "%", NULL };
3045 static const char *const stap_register_indirection_prefixes[] = { "(",
3046 NULL };
3047 static const char *const stap_register_indirection_suffixes[] = { ")",
3048 NULL };
53e95fcf 3049
473f17b0
MK		 3050 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3051 floating-point registers. */
3052 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
8f0435f7 3053 tdep->fpregset = &amd64_fpregset;
473f17b0 3054
90884b2b 3055 if (! tdesc_has_registers (tdesc))
c55a47e7 3056 tdesc = default_tdesc;
90884b2b
L		 3057 tdep->tdesc = tdesc;
3058
3059 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
3060 tdep->register_names = amd64_register_names;
3061
01f9f808
MS		 3062 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
3063 {
3064 tdep->zmmh_register_names = amd64_zmmh_names;
3065 tdep->k_register_names = amd64_k_names;
3066 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
3067 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
3068
3069 tdep->num_zmm_regs = 32;
3070 tdep->num_xmm_avx512_regs = 16;
3071 tdep->num_ymm_avx512_regs = 16;
3072
3073 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
3074 tdep->k0_regnum = AMD64_K0_REGNUM;
3075 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3076 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3077 }
3078
a055a187
L		 3079 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3080 {
3081 tdep->ymmh_register_names = amd64_ymmh_names;
3082 tdep->num_ymm_regs = 16;
3083 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3084 }
3085
e43e105e
WT		 3086 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3087 {
3088 tdep->mpx_register_names = amd64_mpx_names;
3089 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3090 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3091 }
3092
2735833d
WT		 3093 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL)
3094 {
3095 const struct tdesc_feature *feature =
3096 tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments");
3097 struct tdesc_arch_data *tdesc_data_segments =
3098 (struct tdesc_arch_data *) info.tdep_info;
3099
3100 tdesc_numbered_register (feature, tdesc_data_segments,
3101 AMD64_FSBASE_REGNUM, "fs_base");
3102 tdesc_numbered_register (feature, tdesc_data_segments,
3103 AMD64_GSBASE_REGNUM, "gs_base");
3104 }
3105
51547df6
MS		 3106 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
3107 {
3108 tdep->pkeys_register_names = amd64_pkeys_names;
3109 tdep->pkru_regnum = AMD64_PKRU_REGNUM;
3110 tdep->num_pkeys_regs = 1;
3111 }
3112
fe01d668 3113 tdep->num_byte_regs = 20;
1ba53b71
L		 3114 tdep->num_word_regs = 16;
3115 tdep->num_dword_regs = 16;
3116 /* Avoid wiring in the MMX registers for now. */
3117 tdep->num_mmx_regs = 0;
3118
3543a589
TT		 3119 set_gdbarch_pseudo_register_read_value (gdbarch,
3120 amd64_pseudo_register_read_value);
1ba53b71
L		 3121 set_gdbarch_pseudo_register_write (gdbarch,
3122 amd64_pseudo_register_write);
62e5fd57
MK		 3123 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3124 amd64_ax_pseudo_register_collect);
1ba53b71
L		 3125
3126 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3127
5716833c 3128 /* AMD64 has an FPU and 16 SSE registers. */
90f90721 3129 tdep->st0_regnum = AMD64_ST0_REGNUM;
0c1a73d6 3130 tdep->num_xmm_regs = 16;
53e95fcf 3131
0c1a73d6 3132 /* This is what all the fuss is about. */
53e95fcf
JS		 3133 set_gdbarch_long_bit (gdbarch, 64);
3134 set_gdbarch_long_long_bit (gdbarch, 64);
3135 set_gdbarch_ptr_bit (gdbarch, 64);
3136
e53bef9f
MK		 3137 /* In contrast to the i386, on AMD64 a `long double' actually takes
3138 up 128 bits, even though it's still based on the i387 extended
3139 floating-point format which has only 80 significant bits. */
b83b026c
MK		 3140 set_gdbarch_long_double_bit (gdbarch, 128);
3141
e53bef9f 3142 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
b83b026c
MK		 3143
3144 /* Register numbers of various important registers. */
90f90721
MK		 3145 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3146 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3147 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3148 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
b83b026c 3149
e53bef9f
MK		 3150 /* The "default" register numbering scheme for AMD64 is referred to
3151 as the "DWARF Register Number Mapping" in the System V psABI.
3152 The preferred debugging format for all known AMD64 targets is
3153 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3154 DWARF-1), but we provide the same mapping just in case. This
3155 mapping is also used for stabs, which GCC does support. */
3156 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
e53bef9f 3157 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
de220d0f 3158
c4f35dd8 3159 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
e53bef9f 3160 be in use on any of the supported AMD64 targets. */
53e95fcf 3161
c4f35dd8 3162 /* Call dummy code. */
e53bef9f
MK		 3163 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3164 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
8b148df9 3165 set_gdbarch_frame_red_zone_size (gdbarch, 128);
53e95fcf 3166
83acabca 3167 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
d532c08f
MK		 3168 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3169 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3170
efb1c01c 3171 set_gdbarch_return_value (gdbarch, amd64_return_value);
53e95fcf 3172
e53bef9f 3173 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
53e95fcf 3174
cf648174
HZ		 3175 tdep->record_regmap = amd64_record_regmap;
3176
10458914 3177 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
53e95fcf 3178
872761f4
MS		 3179 /* Hook the function epilogue frame unwinder. This unwinder is
3180 appended to the list first, so that it supercedes the other
3181 unwinders in function epilogues. */
3182 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3183
3184 /* Hook the prologue-based frame unwinders. */
10458914
DJ		 3185 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3186 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
e53bef9f 3187 frame_base_set_default (gdbarch, &amd64_frame_base);
c6b33596 3188
436675d3 3189 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
dde08ee1
PA		 3190
3191 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
6710bf39
SS		 3192
3193 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
55aa24fb
SDJ		 3194
3195 /* SystemTap variables and functions. */
05c0465e
SDJ		 3196 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3197 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3198 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3199 stap_register_indirection_prefixes);
3200 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3201 stap_register_indirection_suffixes);
55aa24fb
SDJ		 3202 set_gdbarch_stap_is_single_operand (gdbarch,
3203 i386_stap_is_single_operand);
3204 set_gdbarch_stap_parse_special_token (gdbarch,
3205 i386_stap_parse_special_token);
c2170eef
MM		 3206 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3207 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3208 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
c4f35dd8 3209}
c912f608
SM		 3210
3211/* Initialize ARCH for x86-64, no osabi. */
3212
3213static void
3214amd64_none_init_abi (gdbarch_info info, gdbarch *arch)
3215{
3216 amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK));
3217}
fff4548b
MK		 3218
3219static struct type *
3220amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3221{
3222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3223
3224 switch (regnum - tdep->eax_regnum)
3225 {
3226 case AMD64_RBP_REGNUM: /* %ebp */
3227 case AMD64_RSP_REGNUM: /* %esp */
3228 return builtin_type (gdbarch)->builtin_data_ptr;
3229 case AMD64_RIP_REGNUM: /* %eip */
3230 return builtin_type (gdbarch)->builtin_func_ptr;
3231 }
3232
3233 return i386_pseudo_register_type (gdbarch, regnum);
3234}
3235
3236void
c55a47e7 3237amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
a04b5337 3238 const target_desc *default_tdesc)
fff4548b
MK		 3239{
3240 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
fff4548b 3241
c55a47e7 3242 amd64_init_abi (info, gdbarch, default_tdesc);
fff4548b
MK		 3243
3244 tdep->num_dword_regs = 17;
3245 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3246
3247 set_gdbarch_long_bit (gdbarch, 32);
3248 set_gdbarch_ptr_bit (gdbarch, 32);
3249}
90884b2b 3250
c912f608
SM		 3251/* Initialize ARCH for x64-32, no osabi. */
3252
3253static void
3254amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch)
3255{
3256 amd64_x32_init_abi (info, arch,
3257 amd64_target_description (X86_XSTATE_SSE_MASK));
3258}
3259
97de3545
JB		 3260/* Return the target description for a specified XSAVE feature mask. */
3261
3262const struct target_desc *
3263amd64_target_description (uint64_t xcr0)
3264{
22916b07
YQ		 3265 static target_desc *amd64_tdescs \
3266 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
3267 target_desc **tdesc;
3268
3269 tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
3270 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
3271 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
3272 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0];
3273
3274 if (*tdesc == NULL)
3275 *tdesc = amd64_create_target_description (xcr0, false, false);
3276
3277 return *tdesc;
97de3545
JB		 3278}
3279
90884b2b
L		 3280void
3281_initialize_amd64_tdep (void)
3282{
c912f608
SM		 3283 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NONE,
3284 amd64_none_init_abi);
3285 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE,
3286 amd64_x32_none_init_abi);
3287
22916b07
YQ		 3288#if GDB_SELF_TEST
3289 struct
3290 {
3291 const char *xml;
3292 uint64_t mask;
3293 } xml_masks[] = {
3294 { "i386/amd64.xml", X86_XSTATE_SSE_MASK },
3295 { "i386/amd64-avx.xml", X86_XSTATE_AVX_MASK },
3296 { "i386/amd64-mpx.xml", X86_XSTATE_MPX_MASK },
3297 { "i386/amd64-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK },
3298 { "i386/amd64-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK },
3299 { "i386/amd64-avx-mpx-avx512-pku.xml",
3300 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK },
3301 };
3302
3303 for (auto &a : xml_masks)
3304 {
3305 auto tdesc = amd64_target_description (a.mask);
3306
3307 selftests::record_xml_tdesc (a.xml, tdesc);
3308 }
3309#endif /* GDB_SELF_TEST */
90884b2b 3310}
c4f35dd8
MK		 3311\f
3312
41d041d6
MK		 3313/* The 64-bit FXSAVE format differs from the 32-bit format in the
3314 sense that the instruction pointer and data pointer are simply
3315 64-bit offsets into the code segment and the data segment instead
3316 of a selector offset pair. The functions below store the upper 32
3317 bits of these pointers (instead of just the 16-bits of the segment
3318 selector). */
3319
3320/* Fill register REGNUM in REGCACHE with the appropriate
0485f6ad
MK		 3321 floating-point or SSE register value from *FXSAVE. If REGNUM is
3322 -1, do this for all registers. This function masks off any of the
3323 reserved bits in *FXSAVE. */
c4f35dd8
MK		 3324
3325void
90f90721 3326amd64_supply_fxsave (struct regcache *regcache, int regnum,
20a6ec49 3327 const void *fxsave)
c4f35dd8 3328{
ac7936df 3329 struct gdbarch *gdbarch = regcache->arch ();
20a6ec49
MD		 3330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3331
41d041d6 3332 i387_supply_fxsave (regcache, regnum, fxsave);
c4f35dd8 3333
233dfcf0
L		 3334 if (fxsave
3335 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
c4f35dd8 3336 {
9a3c8263 3337 const gdb_byte *regs = (const gdb_byte *) fxsave;
41d041d6 3338
20a6ec49
MD		 3339 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3340 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3341 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3342 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
c4f35dd8 3343 }
0c1a73d6
MK		 3344}
3345
a055a187
L		 3346/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3347
3348void
3349amd64_supply_xsave (struct regcache *regcache, int regnum,
3350 const void *xsave)
3351{
ac7936df 3352 struct gdbarch *gdbarch = regcache->arch ();
a055a187
L		 3353 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3354
3355 i387_supply_xsave (regcache, regnum, xsave);
3356
233dfcf0
L		 3357 if (xsave
3358 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187 3359 {
9a3c8263 3360 const gdb_byte *regs = (const gdb_byte *) xsave;
a055a187
L		 3361
3362 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3363 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3364 regs + 12);
3365 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3366 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3367 regs + 20);
3368 }
3369}
3370
3c017e40
MK		 3371/* Fill register REGNUM (if it is a floating-point or SSE register) in
3372 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3373 all registers. This function doesn't touch any of the reserved
3374 bits in *FXSAVE. */
3375
3376void
3377amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3378 void *fxsave)
3379{
ac7936df 3380 struct gdbarch *gdbarch = regcache->arch ();
20a6ec49 3381 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3382 gdb_byte *regs = (gdb_byte *) fxsave;
3c017e40
MK		 3383
3384 i387_collect_fxsave (regcache, regnum, fxsave);
3385
233dfcf0 3386 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
f0ef85a5 3387 {
20a6ec49
MD		 3388 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3389 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3390 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3391 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
f0ef85a5 3392 }
3c017e40 3393}
a055a187 3394
7a9dd1b2 3395/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
a055a187
L		 3396
3397void
3398amd64_collect_xsave (const struct regcache *regcache, int regnum,
3399 void *xsave, int gcore)
3400{
ac7936df 3401 struct gdbarch *gdbarch = regcache->arch ();
a055a187 3402 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3403 gdb_byte *regs = (gdb_byte *) xsave;
a055a187
L		 3404
3405 i387_collect_xsave (regcache, regnum, xsave, gcore);
3406
233dfcf0 3407 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187
L		 3408 {
3409 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3410 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3411 regs + 12);
3412 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3413 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),
3414 regs + 20);
3415 }
3416}
GDB Binutils - Deliverables
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