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amd64: simplify addition of new general registers.
[deliverable/binutils-gdb.git] / gdb / amd64-tdep.c
CommitLineData
e53bef9f 1/* Target-dependent code for AMD64.
ce0eebec 2
61baf725 3 Copyright (C) 2001-2017 Free Software Foundation, Inc.
5ae96ec1
MK		 4
5 Contributed by Jiri Smid, SuSE Labs.
53e95fcf
JS		 6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
53e95fcf
JS		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
53e95fcf
JS		 21
22#include "defs.h"
35669430
DE		 23#include "opcode/i386.h"
24#include "dis-asm.h"
c4f35dd8
MK		 25#include "arch-utils.h"
26#include "block.h"
27#include "dummy-frame.h"
28#include "frame.h"
29#include "frame-base.h"
30#include "frame-unwind.h"
53e95fcf 31#include "inferior.h"
45741a9c 32#include "infrun.h"
53e95fcf 33#include "gdbcmd.h"
c4f35dd8
MK		 34#include "gdbcore.h"
35#include "objfiles.h"
53e95fcf 36#include "regcache.h"
2c261fae 37#include "regset.h"
53e95fcf 38#include "symfile.h"
eda5a4d7 39#include "disasm.h"
9c1488cb 40#include "amd64-tdep.h"
c4f35dd8 41#include "i387-tdep.h"
97de3545 42#include "x86-xstate.h"
325fac50 43#include <algorithm>
53e95fcf 44
90884b2b 45#include "features/i386/amd64.c"
a055a187 46#include "features/i386/amd64-avx.c"
e43e105e 47#include "features/i386/amd64-mpx.c"
2b863f51 48#include "features/i386/amd64-avx-mpx.c"
01f9f808
MS		 49#include "features/i386/amd64-avx512.c"
50
ac1438b5
L		 51#include "features/i386/x32.c"
52#include "features/i386/x32-avx.c"
01f9f808 53#include "features/i386/x32-avx512.c"
90884b2b 54
6710bf39
SS		 55#include "ax.h"
56#include "ax-gdb.h"
57
e53bef9f
MK		 58/* Note that the AMD64 architecture was previously known as x86-64.
59 The latter is (forever) engraved into the canonical system name as
90f90721 60 returned by config.guess, and used as the name for the AMD64 port
e53bef9f
MK		 61 of GNU/Linux. The BSD's have renamed their ports to amd64; they
62 don't like to shout. For GDB we prefer the amd64_-prefix over the
63 x86_64_-prefix since it's so much easier to type. */
64
402ecd56 65/* Register information. */
c4f35dd8 66
6707b003 67static const char *amd64_register_names[] =
de220d0f 68{
6707b003 69 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
c4f35dd8
MK		 70
71 /* %r8 is indeed register number 8. */
6707b003
UW		 72 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
73 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
c4f35dd8 74
af233647 75 /* %st0 is register number 24. */
6707b003
UW		 76 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
77 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
c4f35dd8 78
af233647 79 /* %xmm0 is register number 40. */
6707b003
UW		 80 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
81 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
82 "mxcsr",
0e04a514
ML		 83};
84
a055a187
L		 85static const char *amd64_ymm_names[] =
86{
87 "ymm0", "ymm1", "ymm2", "ymm3",
88 "ymm4", "ymm5", "ymm6", "ymm7",
89 "ymm8", "ymm9", "ymm10", "ymm11",
90 "ymm12", "ymm13", "ymm14", "ymm15"
91};
92
01f9f808
MS		 93static const char *amd64_ymm_avx512_names[] =
94{
95 "ymm16", "ymm17", "ymm18", "ymm19",
96 "ymm20", "ymm21", "ymm22", "ymm23",
97 "ymm24", "ymm25", "ymm26", "ymm27",
98 "ymm28", "ymm29", "ymm30", "ymm31"
99};
100
a055a187
L		 101static const char *amd64_ymmh_names[] =
102{
103 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
104 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
105 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
106 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
107};
de220d0f 108
01f9f808
MS		 109static const char *amd64_ymmh_avx512_names[] =
110{
111 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
112 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
113 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
114 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
115};
116
e43e105e
WT		 117static const char *amd64_mpx_names[] =
118{
119 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
120};
121
01f9f808
MS		 122static const char *amd64_k_names[] =
123{
124 "k0", "k1", "k2", "k3",
125 "k4", "k5", "k6", "k7"
126};
127
128static const char *amd64_zmmh_names[] =
129{
130 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
131 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
132 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
133 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
134 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
135 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
136 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
137 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
138};
139
140static const char *amd64_zmm_names[] =
141{
142 "zmm0", "zmm1", "zmm2", "zmm3",
143 "zmm4", "zmm5", "zmm6", "zmm7",
144 "zmm8", "zmm9", "zmm10", "zmm11",
145 "zmm12", "zmm13", "zmm14", "zmm15",
146 "zmm16", "zmm17", "zmm18", "zmm19",
147 "zmm20", "zmm21", "zmm22", "zmm23",
148 "zmm24", "zmm25", "zmm26", "zmm27",
149 "zmm28", "zmm29", "zmm30", "zmm31"
150};
151
152static const char *amd64_xmm_avx512_names[] = {
153 "xmm16", "xmm17", "xmm18", "xmm19",
154 "xmm20", "xmm21", "xmm22", "xmm23",
155 "xmm24", "xmm25", "xmm26", "xmm27",
156 "xmm28", "xmm29", "xmm30", "xmm31"
157};
158
c4f35dd8
MK		 159/* DWARF Register Number Mapping as defined in the System V psABI,
160 section 3.6. */
53e95fcf 161
e53bef9f 162static int amd64_dwarf_regmap[] =
0e04a514 163{
c4f35dd8 164 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
90f90721
MK		 165 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
166 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
167 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
c4f35dd8
MK		 168
169 /* Frame Pointer Register RBP. */
90f90721 170 AMD64_RBP_REGNUM,
c4f35dd8
MK		 171
172 /* Stack Pointer Register RSP. */
90f90721 173 AMD64_RSP_REGNUM,
c4f35dd8
MK		 174
175 /* Extended Integer Registers 8 - 15. */
5b856f36
PM		 176 AMD64_R8_REGNUM, /* %r8 */
177 AMD64_R9_REGNUM, /* %r9 */
178 AMD64_R10_REGNUM, /* %r10 */
179 AMD64_R11_REGNUM, /* %r11 */
180 AMD64_R12_REGNUM, /* %r12 */
181 AMD64_R13_REGNUM, /* %r13 */
182 AMD64_R14_REGNUM, /* %r14 */
183 AMD64_R15_REGNUM, /* %r15 */
c4f35dd8 184
59207364 185 /* Return Address RA. Mapped to RIP. */
90f90721 186 AMD64_RIP_REGNUM,
c4f35dd8
MK		 187
188 /* SSE Registers 0 - 7. */
90f90721
MK		 189 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
190 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
191 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
192 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
c4f35dd8
MK		 193
194 /* Extended SSE Registers 8 - 15. */
90f90721
MK		 195 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
196 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
197 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
198 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
c4f35dd8
MK		 199
200 /* Floating Point Registers 0-7. */
90f90721
MK		 201 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
202 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
203 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
c6f4c129 204 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
f7ca3fcf
PM		 205
206 /* MMX Registers 0 - 7.
207 We have to handle those registers specifically, as their register
208 number within GDB depends on the target (or they may even not be
209 available at all). */
210 -1, -1, -1, -1, -1, -1, -1, -1,
211
c6f4c129
JB		 212 /* Control and Status Flags Register. */
213 AMD64_EFLAGS_REGNUM,
214
215 /* Selector Registers. */
216 AMD64_ES_REGNUM,
217 AMD64_CS_REGNUM,
218 AMD64_SS_REGNUM,
219 AMD64_DS_REGNUM,
220 AMD64_FS_REGNUM,
221 AMD64_GS_REGNUM,
222 -1,
223 -1,
224
225 /* Segment Base Address Registers. */
226 -1,
227 -1,
228 -1,
229 -1,
230
231 /* Special Selector Registers. */
232 -1,
233 -1,
234
235 /* Floating Point Control Registers. */
236 AMD64_MXCSR_REGNUM,
237 AMD64_FCTRL_REGNUM,
238 AMD64_FSTAT_REGNUM
c4f35dd8 239};
0e04a514 240
e53bef9f
MK		 241static const int amd64_dwarf_regmap_len =
242 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
0e04a514 243
c4f35dd8
MK		 244/* Convert DWARF register number REG to the appropriate register
245 number used by GDB. */
26abbdc4 246
c4f35dd8 247static int
d3f73121 248amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
53e95fcf 249{
a055a187
L		 250 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
251 int ymm0_regnum = tdep->ymm0_regnum;
c4f35dd8 252 int regnum = -1;
53e95fcf 253
16aff9a6 254 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
e53bef9f 255 regnum = amd64_dwarf_regmap[reg];
53e95fcf 256
0fde2c53 257 if (ymm0_regnum >= 0
a055a187
L		 258 && i386_xmm_regnum_p (gdbarch, regnum))
259 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
c4f35dd8
MK		 260
261 return regnum;
53e95fcf 262}
d532c08f 263
35669430
DE		 264/* Map architectural register numbers to gdb register numbers. */
265
266static const int amd64_arch_regmap[16] =
267{
268 AMD64_RAX_REGNUM, /* %rax */
269 AMD64_RCX_REGNUM, /* %rcx */
270 AMD64_RDX_REGNUM, /* %rdx */
271 AMD64_RBX_REGNUM, /* %rbx */
272 AMD64_RSP_REGNUM, /* %rsp */
273 AMD64_RBP_REGNUM, /* %rbp */
274 AMD64_RSI_REGNUM, /* %rsi */
275 AMD64_RDI_REGNUM, /* %rdi */
276 AMD64_R8_REGNUM, /* %r8 */
277 AMD64_R9_REGNUM, /* %r9 */
278 AMD64_R10_REGNUM, /* %r10 */
279 AMD64_R11_REGNUM, /* %r11 */
280 AMD64_R12_REGNUM, /* %r12 */
281 AMD64_R13_REGNUM, /* %r13 */
282 AMD64_R14_REGNUM, /* %r14 */
283 AMD64_R15_REGNUM /* %r15 */
284};
285
286static const int amd64_arch_regmap_len =
287 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
288
289/* Convert architectural register number REG to the appropriate register
290 number used by GDB. */
291
292static int
293amd64_arch_reg_to_regnum (int reg)
294{
295 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
296
297 return amd64_arch_regmap[reg];
298}
299
1ba53b71
L		 300/* Register names for byte pseudo-registers. */
301
302static const char *amd64_byte_names[] =
303{
304 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
fe01d668
L		 305 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
306 "ah", "bh", "ch", "dh"
1ba53b71
L		 307};
308
fe01d668
L		 309/* Number of lower byte registers. */
310#define AMD64_NUM_LOWER_BYTE_REGS 16
311
1ba53b71
L		 312/* Register names for word pseudo-registers. */
313
314static const char *amd64_word_names[] =
315{
9cad29ac 316 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
1ba53b71
L		 317 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
318};
319
320/* Register names for dword pseudo-registers. */
321
322static const char *amd64_dword_names[] =
323{
324 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
fff4548b
MK		 325 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
326 "eip"
1ba53b71
L		 327};
328
329/* Return the name of register REGNUM. */
330
331static const char *
332amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
333{
334 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
335 if (i386_byte_regnum_p (gdbarch, regnum))
336 return amd64_byte_names[regnum - tdep->al_regnum];
01f9f808
MS		 337 else if (i386_zmm_regnum_p (gdbarch, regnum))
338 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
a055a187
L		 339 else if (i386_ymm_regnum_p (gdbarch, regnum))
340 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
01f9f808
MS		 341 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
342 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
1ba53b71
L		 343 else if (i386_word_regnum_p (gdbarch, regnum))
344 return amd64_word_names[regnum - tdep->ax_regnum];
345 else if (i386_dword_regnum_p (gdbarch, regnum))
346 return amd64_dword_names[regnum - tdep->eax_regnum];
347 else
348 return i386_pseudo_register_name (gdbarch, regnum);
349}
350
3543a589
TT		 351static struct value *
352amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
353 struct regcache *regcache,
354 int regnum)
1ba53b71 355{
9890e433 356 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
1ba53b71 357 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
05d1431c 358 enum register_status status;
3543a589
TT		 359 struct value *result_value;
360 gdb_byte *buf;
361
362 result_value = allocate_value (register_type (gdbarch, regnum));
363 VALUE_LVAL (result_value) = lval_register;
364 VALUE_REGNUM (result_value) = regnum;
365 buf = value_contents_raw (result_value);
1ba53b71
L		 366
367 if (i386_byte_regnum_p (gdbarch, regnum))
368 {
369 int gpnum = regnum - tdep->al_regnum;
370
371 /* Extract (always little endian). */
fe01d668
L		 372 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
373 {
374 /* Special handling for AH, BH, CH, DH. */
05d1431c
PA		 375 status = regcache_raw_read (regcache,
376 gpnum - AMD64_NUM_LOWER_BYTE_REGS,
377 raw_buf);
378 if (status == REG_VALID)
379 memcpy (buf, raw_buf + 1, 1);
3543a589
TT		 380 else
381 mark_value_bytes_unavailable (result_value, 0,
382 TYPE_LENGTH (value_type (result_value)));
fe01d668
L		 383 }
384 else
385 {
05d1431c
PA		 386 status = regcache_raw_read (regcache, gpnum, raw_buf);
387 if (status == REG_VALID)
388 memcpy (buf, raw_buf, 1);
3543a589
TT		 389 else
390 mark_value_bytes_unavailable (result_value, 0,
391 TYPE_LENGTH (value_type (result_value)));
fe01d668 392 }
1ba53b71
L		 393 }
394 else if (i386_dword_regnum_p (gdbarch, regnum))
395 {
396 int gpnum = regnum - tdep->eax_regnum;
397 /* Extract (always little endian). */
05d1431c
PA		 398 status = regcache_raw_read (regcache, gpnum, raw_buf);
399 if (status == REG_VALID)
400 memcpy (buf, raw_buf, 4);
3543a589
TT		 401 else
402 mark_value_bytes_unavailable (result_value, 0,
403 TYPE_LENGTH (value_type (result_value)));
1ba53b71
L		 404 }
405 else
3543a589
TT		 406 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
407 result_value);
408
409 return result_value;
1ba53b71
L		 410}
411
412static void
413amd64_pseudo_register_write (struct gdbarch *gdbarch,
414 struct regcache *regcache,
415 int regnum, const gdb_byte *buf)
416{
9890e433 417 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
1ba53b71
L		 418 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
419
420 if (i386_byte_regnum_p (gdbarch, regnum))
421 {
422 int gpnum = regnum - tdep->al_regnum;
423
fe01d668
L		 424 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
425 {
426 /* Read ... AH, BH, CH, DH. */
427 regcache_raw_read (regcache,
428 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
429 /* ... Modify ... (always little endian). */
430 memcpy (raw_buf + 1, buf, 1);
431 /* ... Write. */
432 regcache_raw_write (regcache,
433 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf);
434 }
435 else
436 {
437 /* Read ... */
438 regcache_raw_read (regcache, gpnum, raw_buf);
439 /* ... Modify ... (always little endian). */
440 memcpy (raw_buf, buf, 1);
441 /* ... Write. */
442 regcache_raw_write (regcache, gpnum, raw_buf);
443 }
1ba53b71
L		 444 }
445 else if (i386_dword_regnum_p (gdbarch, regnum))
446 {
447 int gpnum = regnum - tdep->eax_regnum;
448
449 /* Read ... */
450 regcache_raw_read (regcache, gpnum, raw_buf);
451 /* ... Modify ... (always little endian). */
452 memcpy (raw_buf, buf, 4);
453 /* ... Write. */
454 regcache_raw_write (regcache, gpnum, raw_buf);
455 }
456 else
457 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
458}
459
62e5fd57
MK		 460/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
461
462static int
463amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
464 struct agent_expr *ax, int regnum)
465{
466 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
467
468 if (i386_byte_regnum_p (gdbarch, regnum))
469 {
470 int gpnum = regnum - tdep->al_regnum;
471
472 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
473 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
474 else
475 ax_reg_mask (ax, gpnum);
476 return 0;
477 }
478 else if (i386_dword_regnum_p (gdbarch, regnum))
479 {
480 int gpnum = regnum - tdep->eax_regnum;
481
482 ax_reg_mask (ax, gpnum);
483 return 0;
484 }
485 else
486 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
487}
488
53e95fcf
JS		 489\f
490
bf4d6c1c
JB		 491/* Register classes as defined in the psABI. */
492
493enum amd64_reg_class
494{
495 AMD64_INTEGER,
496 AMD64_SSE,
497 AMD64_SSEUP,
498 AMD64_X87,
499 AMD64_X87UP,
500 AMD64_COMPLEX_X87,
501 AMD64_NO_CLASS,
502 AMD64_MEMORY
503};
504
efb1c01c
MK		 505/* Return the union class of CLASS1 and CLASS2. See the psABI for
506 details. */
507
508static enum amd64_reg_class
509amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
510{
511 /* Rule (a): If both classes are equal, this is the resulting class. */
512 if (class1 == class2)
513 return class1;
514
515 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
516 is the other class. */
517 if (class1 == AMD64_NO_CLASS)
518 return class2;
519 if (class2 == AMD64_NO_CLASS)
520 return class1;
521
522 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
523 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
524 return AMD64_MEMORY;
525
526 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
527 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
528 return AMD64_INTEGER;
529
530 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
531 MEMORY is used as class. */
532 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
533 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
534 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
535 return AMD64_MEMORY;
536
537 /* Rule (f): Otherwise class SSE is used. */
538 return AMD64_SSE;
539}
540
fe978cb0 541static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
bf4d6c1c 542
79b1ab3d
MK		 543/* Return non-zero if TYPE is a non-POD structure or union type. */
544
545static int
546amd64_non_pod_p (struct type *type)
547{
548 /* ??? A class with a base class certainly isn't POD, but does this
549 catch all non-POD structure types? */
550 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
551 return 1;
552
553 return 0;
554}
555
efb1c01c
MK		 556/* Classify TYPE according to the rules for aggregate (structures and
557 arrays) and union types, and store the result in CLASS. */
c4f35dd8
MK		 558
559static void
fe978cb0 560amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
53e95fcf 561{
efb1c01c
MK		 562 /* 1. If the size of an object is larger than two eightbytes, or in
563 C++, is a non-POD structure or union type, or contains
564 unaligned fields, it has class memory. */
744a8059 565 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type))
53e95fcf 566 {
fe978cb0 567 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 568 return;
53e95fcf 569 }
efb1c01c
MK		 570
571 /* 2. Both eightbytes get initialized to class NO_CLASS. */
fe978cb0 572 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 573
574 /* 3. Each field of an object is classified recursively so that
575 always two fields are considered. The resulting class is
576 calculated according to the classes of the fields in the
577 eightbyte: */
578
579 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
8ffd9b1b 580 {
efb1c01c
MK		 581 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
582
583 /* All fields in an array have the same type. */
fe978cb0
PA		 584 amd64_classify (subtype, theclass);
585 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
586 theclass[1] = theclass[0];
8ffd9b1b 587 }
53e95fcf
JS		 588 else
589 {
efb1c01c 590 int i;
53e95fcf 591
efb1c01c
MK		 592 /* Structure or union. */
593 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
594 || TYPE_CODE (type) == TYPE_CODE_UNION);
595
596 for (i = 0; i < TYPE_NFIELDS (type); i++)
53e95fcf 597 {
efb1c01c
MK		 598 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
599 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
600 enum amd64_reg_class subclass[2];
e4e2711a
JB		 601 int bitsize = TYPE_FIELD_BITSIZE (type, i);
602 int endpos;
603
604 if (bitsize == 0)
605 bitsize = TYPE_LENGTH (subtype) * 8;
606 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64;
efb1c01c 607
562c50c2 608 /* Ignore static fields. */
d6a843b5 609 if (field_is_static (&TYPE_FIELD (type, i)))
562c50c2
MK		 610 continue;
611
efb1c01c
MK		 612 gdb_assert (pos == 0 || pos == 1);
613
614 amd64_classify (subtype, subclass);
fe978cb0 615 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
e4e2711a
JB		 616 if (bitsize <= 64 && pos == 0 && endpos == 1)
617 /* This is a bit of an odd case: We have a field that would
618 normally fit in one of the two eightbytes, except that
619 it is placed in a way that this field straddles them.
620 This has been seen with a structure containing an array.
621
622 The ABI is a bit unclear in this case, but we assume that
623 this field's class (stored in subclass[0]) must also be merged
624 into class[1]. In other words, our field has a piece stored
625 in the second eight-byte, and thus its class applies to
626 the second eight-byte as well.
627
628 In the case where the field length exceeds 8 bytes,
629 it should not be necessary to merge the field class
630 into class[1]. As LEN > 8, subclass[1] is necessarily
631 different from AMD64_NO_CLASS. If subclass[1] is equal
632 to subclass[0], then the normal class[1]/subclass[1]
633 merging will take care of everything. For subclass[1]
634 to be different from subclass[0], I can only see the case
635 where we have a SSE/SSEUP or X87/X87UP pair, which both
636 use up all 16 bytes of the aggregate, and are already
637 handled just fine (because each portion sits on its own
638 8-byte). */
fe978cb0 639 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
efb1c01c 640 if (pos == 0)
fe978cb0 641 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
53e95fcf 642 }
53e95fcf 643 }
efb1c01c
MK		 644
645 /* 4. Then a post merger cleanup is done: */
646
647 /* Rule (a): If one of the classes is MEMORY, the whole argument is
648 passed in memory. */
fe978cb0
PA		 649 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
650 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 651
177b42fe 652 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
efb1c01c 653 SSE. */
fe978cb0
PA		 654 if (theclass[0] == AMD64_SSEUP)
655 theclass[0] = AMD64_SSE;
656 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
657 theclass[1] = AMD64_SSE;
efb1c01c
MK		 658}
659
660/* Classify TYPE, and store the result in CLASS. */
661
bf4d6c1c 662static void
fe978cb0 663amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
efb1c01c
MK		 664{
665 enum type_code code = TYPE_CODE (type);
666 int len = TYPE_LENGTH (type);
667
fe978cb0 668 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 669
670 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
5a7225ed
JB		 671 long, long long, and pointers are in the INTEGER class. Similarly,
672 range types, used by languages such as Ada, are also in the INTEGER
673 class. */
efb1c01c 674 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
b929c77f 675 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
9db13498 676 || code == TYPE_CODE_CHAR
efb1c01c
MK		 677 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
678 && (len == 1 || len == 2 || len == 4 || len == 8))
fe978cb0 679 theclass[0] = AMD64_INTEGER;
efb1c01c 680
5daa78cc
TJB		 681 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
682 are in class SSE. */
683 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
684 && (len == 4 || len == 8))
efb1c01c 685 /* FIXME: __m64 . */
fe978cb0 686 theclass[0] = AMD64_SSE;
efb1c01c 687
5daa78cc
TJB		 688 /* Arguments of types __float128, _Decimal128 and __m128 are split into
689 two halves. The least significant ones belong to class SSE, the most
efb1c01c 690 significant one to class SSEUP. */
5daa78cc
TJB		 691 else if (code == TYPE_CODE_DECFLOAT && len == 16)
692 /* FIXME: __float128, __m128. */
fe978cb0 693 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
efb1c01c
MK		 694
695 /* The 64-bit mantissa of arguments of type long double belongs to
696 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
697 class X87UP. */
698 else if (code == TYPE_CODE_FLT && len == 16)
699 /* Class X87 and X87UP. */
fe978cb0 700 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
efb1c01c 701
7f7930dd
MK		 702 /* Arguments of complex T where T is one of the types float or
703 double get treated as if they are implemented as:
704
705 struct complexT {
706 T real;
707 T imag;
5f52445b
YQ		 708 };
709
710 */
7f7930dd 711 else if (code == TYPE_CODE_COMPLEX && len == 8)
fe978cb0 712 theclass[0] = AMD64_SSE;
7f7930dd 713 else if (code == TYPE_CODE_COMPLEX && len == 16)
fe978cb0 714 theclass[0] = theclass[1] = AMD64_SSE;
7f7930dd
MK		 715
716 /* A variable of type complex long double is classified as type
717 COMPLEX_X87. */
718 else if (code == TYPE_CODE_COMPLEX && len == 32)
fe978cb0 719 theclass[0] = AMD64_COMPLEX_X87;
7f7930dd 720
efb1c01c
MK		 721 /* Aggregates. */
722 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
723 || code == TYPE_CODE_UNION)
fe978cb0 724 amd64_classify_aggregate (type, theclass);
efb1c01c
MK		 725}
726
727static enum return_value_convention
6a3a010b 728amd64_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101 729 struct type *type, struct regcache *regcache,
42835c2b 730 gdb_byte *readbuf, const gdb_byte *writebuf)
efb1c01c 731{
fe978cb0 732 enum amd64_reg_class theclass[2];
efb1c01c 733 int len = TYPE_LENGTH (type);
90f90721
MK		 734 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
735 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
efb1c01c
MK		 736 int integer_reg = 0;
737 int sse_reg = 0;
738 int i;
739
740 gdb_assert (!(readbuf && writebuf));
741
742 /* 1. Classify the return type with the classification algorithm. */
fe978cb0 743 amd64_classify (type, theclass);
efb1c01c
MK		 744
745 /* 2. If the type has class MEMORY, then the caller provides space
6fa57a7d 746 for the return value and passes the address of this storage in
0963b4bd 747 %rdi as if it were the first argument to the function. In effect,
6fa57a7d
MK		 748 this address becomes a hidden first argument.
749
750 On return %rax will contain the address that has been passed in
751 by the caller in %rdi. */
fe978cb0 752 if (theclass[0] == AMD64_MEMORY)
6fa57a7d
MK		 753 {
754 /* As indicated by the comment above, the ABI guarantees that we
755 can always find the return value just after the function has
756 returned. */
757
758 if (readbuf)
759 {
760 ULONGEST addr;
761
762 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
763 read_memory (addr, readbuf, TYPE_LENGTH (type));
764 }
765
766 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
767 }
efb1c01c 768
7f7930dd
MK		 769 /* 8. If the class is COMPLEX_X87, the real part of the value is
770 returned in %st0 and the imaginary part in %st1. */
fe978cb0 771 if (theclass[0] == AMD64_COMPLEX_X87)
7f7930dd
MK		 772 {
773 if (readbuf)
774 {
775 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf);
776 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16);
777 }
778
779 if (writebuf)
780 {
781 i387_return_value (gdbarch, regcache);
782 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf);
783 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16);
784
785 /* Fix up the tag word such that both %st(0) and %st(1) are
786 marked as valid. */
787 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
788 }
789
790 return RETURN_VALUE_REGISTER_CONVENTION;
791 }
792
fe978cb0 793 gdb_assert (theclass[1] != AMD64_MEMORY);
bad43aa5 794 gdb_assert (len <= 16);
efb1c01c
MK		 795
796 for (i = 0; len > 0; i++, len -= 8)
797 {
798 int regnum = -1;
799 int offset = 0;
800
fe978cb0 801 switch (theclass[i])
efb1c01c
MK		 802 {
803 case AMD64_INTEGER:
804 /* 3. If the class is INTEGER, the next available register
805 of the sequence %rax, %rdx is used. */
806 regnum = integer_regnum[integer_reg++];
807 break;
808
809 case AMD64_SSE:
810 /* 4. If the class is SSE, the next available SSE register
811 of the sequence %xmm0, %xmm1 is used. */
812 regnum = sse_regnum[sse_reg++];
813 break;
814
815 case AMD64_SSEUP:
816 /* 5. If the class is SSEUP, the eightbyte is passed in the
817 upper half of the last used SSE register. */
818 gdb_assert (sse_reg > 0);
819 regnum = sse_regnum[sse_reg - 1];
820 offset = 8;
821 break;
822
823 case AMD64_X87:
824 /* 6. If the class is X87, the value is returned on the X87
825 stack in %st0 as 80-bit x87 number. */
90f90721 826 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 827 if (writebuf)
828 i387_return_value (gdbarch, regcache);
829 break;
830
831 case AMD64_X87UP:
832 /* 7. If the class is X87UP, the value is returned together
833 with the previous X87 value in %st0. */
fe978cb0 834 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
90f90721 835 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 836 offset = 8;
837 len = 2;
838 break;
839
840 case AMD64_NO_CLASS:
841 continue;
842
843 default:
844 gdb_assert (!"Unexpected register class.");
845 }
846
847 gdb_assert (regnum != -1);
848
849 if (readbuf)
325fac50 850 regcache_raw_read_part (regcache, regnum, offset, std::min (len, 8),
42835c2b 851 readbuf + i * 8);
efb1c01c 852 if (writebuf)
325fac50 853 regcache_raw_write_part (regcache, regnum, offset, std::min (len, 8),
42835c2b 854 writebuf + i * 8);
efb1c01c
MK		 855 }
856
857 return RETURN_VALUE_REGISTER_CONVENTION;
53e95fcf
JS		 858}
859\f
860
720aa428
MK		 861static CORE_ADDR
862amd64_push_arguments (struct regcache *regcache, int nargs,
6470d250 863 struct value **args, CORE_ADDR sp, int struct_return)
720aa428 864{
bf4d6c1c
JB		 865 static int integer_regnum[] =
866 {
867 AMD64_RDI_REGNUM, /* %rdi */
868 AMD64_RSI_REGNUM, /* %rsi */
869 AMD64_RDX_REGNUM, /* %rdx */
870 AMD64_RCX_REGNUM, /* %rcx */
5b856f36
PM		 871 AMD64_R8_REGNUM, /* %r8 */
872 AMD64_R9_REGNUM /* %r9 */
bf4d6c1c 873 };
720aa428
MK		 874 static int sse_regnum[] =
875 {
876 /* %xmm0 ... %xmm7 */
90f90721
MK		 877 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
878 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
879 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
880 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
720aa428 881 };
224c3ddb 882 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
720aa428
MK		 883 int num_stack_args = 0;
884 int num_elements = 0;
885 int element = 0;
886 int integer_reg = 0;
887 int sse_reg = 0;
888 int i;
889
6470d250
MK		 890 /* Reserve a register for the "hidden" argument. */
891 if (struct_return)
892 integer_reg++;
893
720aa428
MK		 894 for (i = 0; i < nargs; i++)
895 {
4991999e 896 struct type *type = value_type (args[i]);
720aa428 897 int len = TYPE_LENGTH (type);
fe978cb0 898 enum amd64_reg_class theclass[2];
720aa428
MK		 899 int needed_integer_regs = 0;
900 int needed_sse_regs = 0;
901 int j;
902
903 /* Classify argument. */
fe978cb0 904 amd64_classify (type, theclass);
720aa428
MK		 905
906 /* Calculate the number of integer and SSE registers needed for
907 this argument. */
908 for (j = 0; j < 2; j++)
909 {
fe978cb0 910 if (theclass[j] == AMD64_INTEGER)
720aa428 911 needed_integer_regs++;
fe978cb0 912 else if (theclass[j] == AMD64_SSE)
720aa428
MK		 913 needed_sse_regs++;
914 }
915
916 /* Check whether enough registers are available, and if the
917 argument should be passed in registers at all. */
bf4d6c1c 918 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
720aa428
MK		 919 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
920 || (needed_integer_regs == 0 && needed_sse_regs == 0))
921 {
922 /* The argument will be passed on the stack. */
923 num_elements += ((len + 7) / 8);
849e9755 924 stack_args[num_stack_args++] = args[i];
720aa428
MK		 925 }
926 else
927 {
928 /* The argument will be passed in registers. */
d8de1ef7
MK		 929 const gdb_byte *valbuf = value_contents (args[i]);
930 gdb_byte buf[8];
720aa428
MK		 931
932 gdb_assert (len <= 16);
933
934 for (j = 0; len > 0; j++, len -= 8)
935 {
936 int regnum = -1;
937 int offset = 0;
938
fe978cb0 939 switch (theclass[j])
720aa428
MK		 940 {
941 case AMD64_INTEGER:
bf4d6c1c 942 regnum = integer_regnum[integer_reg++];
720aa428
MK		 943 break;
944
945 case AMD64_SSE:
946 regnum = sse_regnum[sse_reg++];
947 break;
948
949 case AMD64_SSEUP:
950 gdb_assert (sse_reg > 0);
951 regnum = sse_regnum[sse_reg - 1];
952 offset = 8;
953 break;
954
955 default:
956 gdb_assert (!"Unexpected register class.");
957 }
958
959 gdb_assert (regnum != -1);
960 memset (buf, 0, sizeof buf);
325fac50 961 memcpy (buf, valbuf + j * 8, std::min (len, 8));
720aa428
MK		 962 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
963 }
964 }
965 }
966
967 /* Allocate space for the arguments on the stack. */
968 sp -= num_elements * 8;
969
970 /* The psABI says that "The end of the input argument area shall be
971 aligned on a 16 byte boundary." */
972 sp &= ~0xf;
973
974 /* Write out the arguments to the stack. */
975 for (i = 0; i < num_stack_args; i++)
976 {
4991999e 977 struct type *type = value_type (stack_args[i]);
d8de1ef7 978 const gdb_byte *valbuf = value_contents (stack_args[i]);
849e9755
JB		 979 int len = TYPE_LENGTH (type);
980
981 write_memory (sp + element * 8, valbuf, len);
982 element += ((len + 7) / 8);
720aa428
MK		 983 }
984
985 /* The psABI says that "For calls that may call functions that use
986 varargs or stdargs (prototype-less calls or calls to functions
987 containing ellipsis (...) in the declaration) %al is used as
988 hidden argument to specify the number of SSE registers used. */
90f90721 989 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
720aa428
MK		 990 return sp;
991}
992
c4f35dd8 993static CORE_ADDR
7d9b040b 994amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
e53bef9f
MK		 995 struct regcache *regcache, CORE_ADDR bp_addr,
996 int nargs, struct value **args, CORE_ADDR sp,
997 int struct_return, CORE_ADDR struct_addr)
53e95fcf 998{
e17a4113 999 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 1000 gdb_byte buf[8];
c4f35dd8
MK		 1001
1002 /* Pass arguments. */
6470d250 1003 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
c4f35dd8
MK		 1004
1005 /* Pass "hidden" argument". */
1006 if (struct_return)
1007 {
e17a4113 1008 store_unsigned_integer (buf, 8, byte_order, struct_addr);
bf4d6c1c 1009 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
c4f35dd8
MK		 1010 }
1011
1012 /* Store return address. */
1013 sp -= 8;
e17a4113 1014 store_unsigned_integer (buf, 8, byte_order, bp_addr);
c4f35dd8
MK		 1015 write_memory (sp, buf, 8);
1016
1017 /* Finally, update the stack pointer... */
e17a4113 1018 store_unsigned_integer (buf, 8, byte_order, sp);
90f90721 1019 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
c4f35dd8
MK		 1020
1021 /* ...and fake a frame pointer. */
90f90721 1022 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
c4f35dd8 1023
3e210248 1024 return sp + 16;
53e95fcf 1025}
c4f35dd8 1026\f
35669430
DE		 1027/* Displaced instruction handling. */
1028
1029/* A partially decoded instruction.
1030 This contains enough details for displaced stepping purposes. */
1031
1032struct amd64_insn
1033{
1034 /* The number of opcode bytes. */
1035 int opcode_len;
1036 /* The offset of the rex prefix or -1 if not present. */
1037 int rex_offset;
1038 /* The offset to the first opcode byte. */
1039 int opcode_offset;
1040 /* The offset to the modrm byte or -1 if not present. */
1041 int modrm_offset;
1042
1043 /* The raw instruction. */
1044 gdb_byte *raw_insn;
1045};
1046
1047struct displaced_step_closure
1048{
1049 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1050 int tmp_used;
1051 int tmp_regno;
1052 ULONGEST tmp_save;
1053
1054 /* Details of the instruction. */
1055 struct amd64_insn insn_details;
1056
1057 /* Amount of space allocated to insn_buf. */
1058 int max_len;
1059
1060 /* The possibly modified insn.
1061 This is a variable-length field. */
1062 gdb_byte insn_buf[1];
1063};
1064
1065/* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1066 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1067 at which point delete these in favor of libopcodes' versions). */
1068
1069static const unsigned char onebyte_has_modrm[256] = {
1070 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1071 /* ------------------------------- */
1072 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1073 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1074 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1075 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1076 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1077 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1078 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1079 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1080 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1081 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1082 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1083 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1084 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1085 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1086 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1087 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1088 /* ------------------------------- */
1089 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1090};
1091
1092static const unsigned char twobyte_has_modrm[256] = {
1093 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1094 /* ------------------------------- */
1095 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1096 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1097 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1098 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1099 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1100 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1101 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1102 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1103 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1104 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1105 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1106 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1107 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1108 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1109 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1110 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1111 /* ------------------------------- */
1112 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1113};
1114
1115static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1116
1117static int
1118rex_prefix_p (gdb_byte pfx)
1119{
1120 return REX_PREFIX_P (pfx);
1121}
1122
1123/* Skip the legacy instruction prefixes in INSN.
1124 We assume INSN is properly sentineled so we don't have to worry
1125 about falling off the end of the buffer. */
1126
1127static gdb_byte *
1903f0e6 1128amd64_skip_prefixes (gdb_byte *insn)
35669430
DE		 1129{
1130 while (1)
1131 {
1132 switch (*insn)
1133 {
1134 case DATA_PREFIX_OPCODE:
1135 case ADDR_PREFIX_OPCODE:
1136 case CS_PREFIX_OPCODE:
1137 case DS_PREFIX_OPCODE:
1138 case ES_PREFIX_OPCODE:
1139 case FS_PREFIX_OPCODE:
1140 case GS_PREFIX_OPCODE:
1141 case SS_PREFIX_OPCODE:
1142 case LOCK_PREFIX_OPCODE:
1143 case REPE_PREFIX_OPCODE:
1144 case REPNE_PREFIX_OPCODE:
1145 ++insn;
1146 continue;
1147 default:
1148 break;
1149 }
1150 break;
1151 }
1152
1153 return insn;
1154}
1155
35669430
DE		 1156/* Return an integer register (other than RSP) that is unused as an input
1157 operand in INSN.
1158 In order to not require adding a rex prefix if the insn doesn't already
1159 have one, the result is restricted to RAX ... RDI, sans RSP.
1160 The register numbering of the result follows architecture ordering,
1161 e.g. RDI = 7. */
1162
1163static int
1164amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1165{
1166 /* 1 bit for each reg */
1167 int used_regs_mask = 0;
1168
1169 /* There can be at most 3 int regs used as inputs in an insn, and we have
1170 7 to choose from (RAX ... RDI, sans RSP).
1171 This allows us to take a conservative approach and keep things simple.
1172 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1173 that implicitly specify RAX. */
1174
1175 /* Avoid RAX. */
1176 used_regs_mask |= 1 << EAX_REG_NUM;
1177 /* Similarily avoid RDX, implicit operand in divides. */
1178 used_regs_mask |= 1 << EDX_REG_NUM;
1179 /* Avoid RSP. */
1180 used_regs_mask |= 1 << ESP_REG_NUM;
1181
1182 /* If the opcode is one byte long and there's no ModRM byte,
1183 assume the opcode specifies a register. */
1184 if (details->opcode_len == 1 && details->modrm_offset == -1)
1185 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1186
1187 /* Mark used regs in the modrm/sib bytes. */
1188 if (details->modrm_offset != -1)
1189 {
1190 int modrm = details->raw_insn[details->modrm_offset];
1191 int mod = MODRM_MOD_FIELD (modrm);
1192 int reg = MODRM_REG_FIELD (modrm);
1193 int rm = MODRM_RM_FIELD (modrm);
1194 int have_sib = mod != 3 && rm == 4;
1195
1196 /* Assume the reg field of the modrm byte specifies a register. */
1197 used_regs_mask |= 1 << reg;
1198
1199 if (have_sib)
1200 {
1201 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
d48ebb5b 1202 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
35669430 1203 used_regs_mask |= 1 << base;
d48ebb5b 1204 used_regs_mask |= 1 << idx;
35669430
DE		 1205 }
1206 else
1207 {
1208 used_regs_mask |= 1 << rm;
1209 }
1210 }
1211
1212 gdb_assert (used_regs_mask < 256);
1213 gdb_assert (used_regs_mask != 255);
1214
1215 /* Finally, find a free reg. */
1216 {
1217 int i;
1218
1219 for (i = 0; i < 8; ++i)
1220 {
1221 if (! (used_regs_mask & (1 << i)))
1222 return i;
1223 }
1224
1225 /* We shouldn't get here. */
1226 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1227 }
1228}
1229
1230/* Extract the details of INSN that we need. */
1231
1232static void
1233amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1234{
1235 gdb_byte *start = insn;
1236 int need_modrm;
1237
1238 details->raw_insn = insn;
1239
1240 details->opcode_len = -1;
1241 details->rex_offset = -1;
1242 details->opcode_offset = -1;
1243 details->modrm_offset = -1;
1244
1245 /* Skip legacy instruction prefixes. */
1903f0e6 1246 insn = amd64_skip_prefixes (insn);
35669430
DE		 1247
1248 /* Skip REX instruction prefix. */
1249 if (rex_prefix_p (*insn))
1250 {
1251 details->rex_offset = insn - start;
1252 ++insn;
1253 }
1254
1255 details->opcode_offset = insn - start;
1256
1257 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1258 {
1259 /* Two or three-byte opcode. */
1260 ++insn;
1261 need_modrm = twobyte_has_modrm[*insn];
1262
1263 /* Check for three-byte opcode. */
1903f0e6 1264 switch (*insn)
35669430 1265 {
1903f0e6
DE		 1266 case 0x24:
1267 case 0x25:
1268 case 0x38:
1269 case 0x3a:
1270 case 0x7a:
1271 case 0x7b:
35669430
DE		 1272 ++insn;
1273 details->opcode_len = 3;
1903f0e6
DE		 1274 break;
1275 default:
1276 details->opcode_len = 2;
1277 break;
35669430 1278 }
35669430
DE		 1279 }
1280 else
1281 {
1282 /* One-byte opcode. */
1283 need_modrm = onebyte_has_modrm[*insn];
1284 details->opcode_len = 1;
1285 }
1286
1287 if (need_modrm)
1288 {
1289 ++insn;
1290 details->modrm_offset = insn - start;
1291 }
1292}
1293
1294/* Update %rip-relative addressing in INSN.
1295
1296 %rip-relative addressing only uses a 32-bit displacement.
1297 32 bits is not enough to be guaranteed to cover the distance between where
1298 the real instruction is and where its copy is.
1299 Convert the insn to use base+disp addressing.
1300 We set base = pc + insn_length so we can leave disp unchanged. */
c4f35dd8 1301
35669430
DE		 1302static void
1303fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc,
1304 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1305{
1306 const struct amd64_insn *insn_details = &dsc->insn_details;
1307 int modrm_offset = insn_details->modrm_offset;
1308 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1309 CORE_ADDR rip_base;
35669430
DE		 1310 int insn_length;
1311 int arch_tmp_regno, tmp_regno;
1312 ULONGEST orig_value;
1313
1314 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1315 ++insn;
1316
1317 /* Compute the rip-relative address. */
eda5a4d7
PA		 1318 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf,
1319 dsc->max_len, from);
35669430
DE		 1320 rip_base = from + insn_length;
1321
1322 /* We need a register to hold the address.
1323 Pick one not used in the insn.
1324 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1325 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1326 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1327
1328 /* REX.B should be unset as we were using rip-relative addressing,
1329 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1330 if (insn_details->rex_offset != -1)
1331 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B;
1332
1333 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1334 dsc->tmp_regno = tmp_regno;
1335 dsc->tmp_save = orig_value;
1336 dsc->tmp_used = 1;
1337
1338 /* Convert the ModRM field to be base+disp. */
1339 dsc->insn_buf[modrm_offset] &= ~0xc7;
1340 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1341
1342 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1343
1344 if (debug_displaced)
1345 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
5af949e3
UW		 1346 "displaced: using temp reg %d, old value %s, new value %s\n",
1347 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1348 paddress (gdbarch, rip_base));
35669430
DE		 1349}
1350
1351static void
1352fixup_displaced_copy (struct gdbarch *gdbarch,
1353 struct displaced_step_closure *dsc,
1354 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1355{
1356 const struct amd64_insn *details = &dsc->insn_details;
1357
1358 if (details->modrm_offset != -1)
1359 {
1360 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1361
1362 if ((modrm & 0xc7) == 0x05)
1363 {
1364 /* The insn uses rip-relative addressing.
1365 Deal with it. */
1366 fixup_riprel (gdbarch, dsc, from, to, regs);
1367 }
1368 }
1369}
1370
1371struct displaced_step_closure *
1372amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1373 CORE_ADDR from, CORE_ADDR to,
1374 struct regcache *regs)
1375{
1376 int len = gdbarch_max_insn_length (gdbarch);
741e63d7 1377 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
35669430
DE		 1378 continually watch for running off the end of the buffer. */
1379 int fixup_sentinel_space = len;
224c3ddb
SM		 1380 struct displaced_step_closure *dsc
1381 = ((struct displaced_step_closure *)
1382 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space));
35669430
DE		 1383 gdb_byte *buf = &dsc->insn_buf[0];
1384 struct amd64_insn *details = &dsc->insn_details;
1385
1386 dsc->tmp_used = 0;
1387 dsc->max_len = len + fixup_sentinel_space;
1388
1389 read_memory (from, buf, len);
1390
1391 /* Set up the sentinel space so we don't have to worry about running
1392 off the end of the buffer. An excessive number of leading prefixes
1393 could otherwise cause this. */
1394 memset (buf + len, 0, fixup_sentinel_space);
1395
1396 amd64_get_insn_details (buf, details);
1397
1398 /* GDB may get control back after the insn after the syscall.
1399 Presumably this is a kernel bug.
1400 If this is a syscall, make sure there's a nop afterwards. */
1401 {
1402 int syscall_length;
1403
1404 if (amd64_syscall_p (details, &syscall_length))
1405 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1406 }
1407
1408 /* Modify the insn to cope with the address where it will be executed from.
1409 In particular, handle any rip-relative addressing. */
1410 fixup_displaced_copy (gdbarch, dsc, from, to, regs);
1411
1412 write_memory (to, buf, len);
1413
1414 if (debug_displaced)
1415 {
5af949e3
UW		 1416 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1417 paddress (gdbarch, from), paddress (gdbarch, to));
35669430
DE		 1418 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1419 }
1420
1421 return dsc;
1422}
1423
1424static int
1425amd64_absolute_jmp_p (const struct amd64_insn *details)
1426{
1427 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1428
1429 if (insn[0] == 0xff)
1430 {
1431 /* jump near, absolute indirect (/4) */
1432 if ((insn[1] & 0x38) == 0x20)
1433 return 1;
1434
1435 /* jump far, absolute indirect (/5) */
1436 if ((insn[1] & 0x38) == 0x28)
1437 return 1;
1438 }
1439
1440 return 0;
1441}
1442
c2170eef
MM		 1443/* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1444
1445static int
1446amd64_jmp_p (const struct amd64_insn *details)
1447{
1448 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1449
1450 /* jump short, relative. */
1451 if (insn[0] == 0xeb)
1452 return 1;
1453
1454 /* jump near, relative. */
1455 if (insn[0] == 0xe9)
1456 return 1;
1457
1458 return amd64_absolute_jmp_p (details);
1459}
1460
35669430
DE		 1461static int
1462amd64_absolute_call_p (const struct amd64_insn *details)
1463{
1464 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1465
1466 if (insn[0] == 0xff)
1467 {
1468 /* Call near, absolute indirect (/2) */
1469 if ((insn[1] & 0x38) == 0x10)
1470 return 1;
1471
1472 /* Call far, absolute indirect (/3) */
1473 if ((insn[1] & 0x38) == 0x18)
1474 return 1;
1475 }
1476
1477 return 0;
1478}
1479
1480static int
1481amd64_ret_p (const struct amd64_insn *details)
1482{
1483 /* NOTE: gcc can emit "repz ; ret". */
1484 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1485
1486 switch (insn[0])
1487 {
1488 case 0xc2: /* ret near, pop N bytes */
1489 case 0xc3: /* ret near */
1490 case 0xca: /* ret far, pop N bytes */
1491 case 0xcb: /* ret far */
1492 case 0xcf: /* iret */
1493 return 1;
1494
1495 default:
1496 return 0;
1497 }
1498}
1499
1500static int
1501amd64_call_p (const struct amd64_insn *details)
1502{
1503 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1504
1505 if (amd64_absolute_call_p (details))
1506 return 1;
1507
1508 /* call near, relative */
1509 if (insn[0] == 0xe8)
1510 return 1;
1511
1512 return 0;
1513}
1514
35669430
DE		 1515/* Return non-zero if INSN is a system call, and set *LENGTHP to its
1516 length in bytes. Otherwise, return zero. */
1517
1518static int
1519amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1520{
1521 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1522
1523 if (insn[0] == 0x0f && insn[1] == 0x05)
1524 {
1525 *lengthp = 2;
1526 return 1;
1527 }
1528
1529 return 0;
1530}
1531
c2170eef
MM		 1532/* Classify the instruction at ADDR using PRED.
1533 Throw an error if the memory can't be read. */
1534
1535static int
1536amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1537 int (*pred) (const struct amd64_insn *))
1538{
1539 struct amd64_insn details;
1540 gdb_byte *buf;
1541 int len, classification;
1542
1543 len = gdbarch_max_insn_length (gdbarch);
224c3ddb 1544 buf = (gdb_byte *) alloca (len);
c2170eef
MM		 1545
1546 read_code (addr, buf, len);
1547 amd64_get_insn_details (buf, &details);
1548
1549 classification = pred (&details);
1550
1551 return classification;
1552}
1553
1554/* The gdbarch insn_is_call method. */
1555
1556static int
1557amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1558{
1559 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1560}
1561
1562/* The gdbarch insn_is_ret method. */
1563
1564static int
1565amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1566{
1567 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1568}
1569
1570/* The gdbarch insn_is_jump method. */
1571
1572static int
1573amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1574{
1575 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1576}
1577
35669430
DE		 1578/* Fix up the state of registers and memory after having single-stepped
1579 a displaced instruction. */
1580
1581void
1582amd64_displaced_step_fixup (struct gdbarch *gdbarch,
1583 struct displaced_step_closure *dsc,
1584 CORE_ADDR from, CORE_ADDR to,
1585 struct regcache *regs)
1586{
e17a4113 1587 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
35669430
DE		 1588 /* The offset we applied to the instruction's address. */
1589 ULONGEST insn_offset = to - from;
1590 gdb_byte *insn = dsc->insn_buf;
1591 const struct amd64_insn *insn_details = &dsc->insn_details;
1592
1593 if (debug_displaced)
1594 fprintf_unfiltered (gdb_stdlog,
5af949e3 1595 "displaced: fixup (%s, %s), "
35669430 1596 "insn = 0x%02x 0x%02x ...\n",
5af949e3
UW		 1597 paddress (gdbarch, from), paddress (gdbarch, to),
1598 insn[0], insn[1]);
35669430
DE		 1599
1600 /* If we used a tmp reg, restore it. */
1601
1602 if (dsc->tmp_used)
1603 {
1604 if (debug_displaced)
5af949e3
UW		 1605 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1606 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
35669430
DE		 1607 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1608 }
1609
1610 /* The list of issues to contend with here is taken from
1611 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1612 Yay for Free Software! */
1613
1614 /* Relocate the %rip back to the program's instruction stream,
1615 if necessary. */
1616
1617 /* Except in the case of absolute or indirect jump or call
1618 instructions, or a return instruction, the new rip is relative to
1619 the displaced instruction; make it relative to the original insn.
1620 Well, signal handler returns don't need relocation either, but we use the
1621 value of %rip to recognize those; see below. */
1622 if (! amd64_absolute_jmp_p (insn_details)
1623 && ! amd64_absolute_call_p (insn_details)
1624 && ! amd64_ret_p (insn_details))
1625 {
1626 ULONGEST orig_rip;
1627 int insn_len;
1628
1629 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1630
1631 /* A signal trampoline system call changes the %rip, resuming
1632 execution of the main program after the signal handler has
1633 returned. That makes them like 'return' instructions; we
1634 shouldn't relocate %rip.
1635
1636 But most system calls don't, and we do need to relocate %rip.
1637
1638 Our heuristic for distinguishing these cases: if stepping
1639 over the system call instruction left control directly after
1640 the instruction, the we relocate --- control almost certainly
1641 doesn't belong in the displaced copy. Otherwise, we assume
1642 the instruction has put control where it belongs, and leave
1643 it unrelocated. Goodness help us if there are PC-relative
1644 system calls. */
1645 if (amd64_syscall_p (insn_details, &insn_len)
1646 && orig_rip != to + insn_len
1647 /* GDB can get control back after the insn after the syscall.
1648 Presumably this is a kernel bug.
1649 Fixup ensures its a nop, we add one to the length for it. */
1650 && orig_rip != to + insn_len + 1)
1651 {
1652 if (debug_displaced)
1653 fprintf_unfiltered (gdb_stdlog,
1654 "displaced: syscall changed %%rip; "
1655 "not relocating\n");
1656 }
1657 else
1658 {
1659 ULONGEST rip = orig_rip - insn_offset;
1660
1903f0e6
DE		 1661 /* If we just stepped over a breakpoint insn, we don't backup
1662 the pc on purpose; this is to match behaviour without
1663 stepping. */
35669430
DE		 1664
1665 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1666
1667 if (debug_displaced)
1668 fprintf_unfiltered (gdb_stdlog,
1669 "displaced: "
5af949e3
UW		 1670 "relocated %%rip from %s to %s\n",
1671 paddress (gdbarch, orig_rip),
1672 paddress (gdbarch, rip));
35669430
DE		 1673 }
1674 }
1675
1676 /* If the instruction was PUSHFL, then the TF bit will be set in the
1677 pushed value, and should be cleared. We'll leave this for later,
1678 since GDB already messes up the TF flag when stepping over a
1679 pushfl. */
1680
1681 /* If the instruction was a call, the return address now atop the
1682 stack is the address following the copied instruction. We need
1683 to make it the address following the original instruction. */
1684 if (amd64_call_p (insn_details))
1685 {
1686 ULONGEST rsp;
1687 ULONGEST retaddr;
1688 const ULONGEST retaddr_len = 8;
1689
1690 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
e17a4113 1691 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
4dafcdeb 1692 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
e17a4113 1693 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
35669430
DE		 1694
1695 if (debug_displaced)
1696 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1697 "displaced: relocated return addr at %s "
1698 "to %s\n",
1699 paddress (gdbarch, rsp),
1700 paddress (gdbarch, retaddr));
35669430
DE		 1701 }
1702}
dde08ee1
PA		 1703
1704/* If the instruction INSN uses RIP-relative addressing, return the
1705 offset into the raw INSN where the displacement to be adjusted is
1706 found. Returns 0 if the instruction doesn't use RIP-relative
1707 addressing. */
1708
1709static int
1710rip_relative_offset (struct amd64_insn *insn)
1711{
1712 if (insn->modrm_offset != -1)
1713 {
1714 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1715
1716 if ((modrm & 0xc7) == 0x05)
1717 {
1718 /* The displacement is found right after the ModRM byte. */
1719 return insn->modrm_offset + 1;
1720 }
1721 }
1722
1723 return 0;
1724}
1725
1726static void
1727append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1728{
1729 target_write_memory (*to, buf, len);
1730 *to += len;
1731}
1732
60965737 1733static void
dde08ee1
PA		 1734amd64_relocate_instruction (struct gdbarch *gdbarch,
1735 CORE_ADDR *to, CORE_ADDR oldloc)
1736{
1737 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1738 int len = gdbarch_max_insn_length (gdbarch);
1739 /* Extra space for sentinels. */
1740 int fixup_sentinel_space = len;
224c3ddb 1741 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
dde08ee1
PA		 1742 struct amd64_insn insn_details;
1743 int offset = 0;
1744 LONGEST rel32, newrel;
1745 gdb_byte *insn;
1746 int insn_length;
1747
1748 read_memory (oldloc, buf, len);
1749
1750 /* Set up the sentinel space so we don't have to worry about running
1751 off the end of the buffer. An excessive number of leading prefixes
1752 could otherwise cause this. */
1753 memset (buf + len, 0, fixup_sentinel_space);
1754
1755 insn = buf;
1756 amd64_get_insn_details (insn, &insn_details);
1757
1758 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1759
1760 /* Skip legacy instruction prefixes. */
1761 insn = amd64_skip_prefixes (insn);
1762
1763 /* Adjust calls with 32-bit relative addresses as push/jump, with
1764 the address pushed being the location where the original call in
1765 the user program would return to. */
1766 if (insn[0] == 0xe8)
1767 {
f077e978
PA		 1768 gdb_byte push_buf[32];
1769 CORE_ADDR ret_addr;
1770 int i = 0;
dde08ee1
PA		 1771
1772 /* Where "ret" in the original code will return to. */
1773 ret_addr = oldloc + insn_length;
f077e978
PA		 1774
1775 /* If pushing an address higher than or equal to 0x80000000,
1776 avoid 'pushq', as that sign extends its 32-bit operand, which
1777 would be incorrect. */
1778 if (ret_addr <= 0x7fffffff)
1779 {
1780 push_buf[0] = 0x68; /* pushq $... */
1781 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1782 i = 5;
1783 }
1784 else
1785 {
1786 push_buf[i++] = 0x48; /* sub $0x8,%rsp */
1787 push_buf[i++] = 0x83;
1788 push_buf[i++] = 0xec;
1789 push_buf[i++] = 0x08;
1790
1791 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */
1792 push_buf[i++] = 0x04;
1793 push_buf[i++] = 0x24;
1794 store_unsigned_integer (&push_buf[i], 4, byte_order,
1795 ret_addr & 0xffffffff);
1796 i += 4;
1797
1798 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */
1799 push_buf[i++] = 0x44;
1800 push_buf[i++] = 0x24;
1801 push_buf[i++] = 0x04;
1802 store_unsigned_integer (&push_buf[i], 4, byte_order,
1803 ret_addr >> 32);
1804 i += 4;
1805 }
1806 gdb_assert (i <= sizeof (push_buf));
dde08ee1 1807 /* Push the push. */
f077e978 1808 append_insns (to, i, push_buf);
dde08ee1
PA		 1809
1810 /* Convert the relative call to a relative jump. */
1811 insn[0] = 0xe9;
1812
1813 /* Adjust the destination offset. */
1814 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1815 newrel = (oldloc - *to) + rel32;
f4a1794a
KY		 1816 store_signed_integer (insn + 1, 4, byte_order, newrel);
1817
1818 if (debug_displaced)
1819 fprintf_unfiltered (gdb_stdlog,
1820 "Adjusted insn rel32=%s at %s to"
1821 " rel32=%s at %s\n",
1822 hex_string (rel32), paddress (gdbarch, oldloc),
1823 hex_string (newrel), paddress (gdbarch, *to));
dde08ee1
PA		 1824
1825 /* Write the adjusted jump into its displaced location. */
1826 append_insns (to, 5, insn);
1827 return;
1828 }
1829
1830 offset = rip_relative_offset (&insn_details);
1831 if (!offset)
1832 {
1833 /* Adjust jumps with 32-bit relative addresses. Calls are
1834 already handled above. */
1835 if (insn[0] == 0xe9)
1836 offset = 1;
1837 /* Adjust conditional jumps. */
1838 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1839 offset = 2;
1840 }
1841
1842 if (offset)
1843 {
1844 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1845 newrel = (oldloc - *to) + rel32;
f4a1794a 1846 store_signed_integer (insn + offset, 4, byte_order, newrel);
dde08ee1
PA		 1847 if (debug_displaced)
1848 fprintf_unfiltered (gdb_stdlog,
f4a1794a
KY		 1849 "Adjusted insn rel32=%s at %s to"
1850 " rel32=%s at %s\n",
dde08ee1
PA		 1851 hex_string (rel32), paddress (gdbarch, oldloc),
1852 hex_string (newrel), paddress (gdbarch, *to));
1853 }
1854
1855 /* Write the adjusted instruction into its displaced location. */
1856 append_insns (to, insn_length, buf);
1857}
1858
35669430 1859\f
c4f35dd8 1860/* The maximum number of saved registers. This should include %rip. */
90f90721 1861#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
c4f35dd8 1862
e53bef9f 1863struct amd64_frame_cache
c4f35dd8
MK		 1864{
1865 /* Base address. */
1866 CORE_ADDR base;
8fbca658 1867 int base_p;
c4f35dd8
MK		 1868 CORE_ADDR sp_offset;
1869 CORE_ADDR pc;
1870
1871 /* Saved registers. */
e53bef9f 1872 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
c4f35dd8 1873 CORE_ADDR saved_sp;
e0c62198 1874 int saved_sp_reg;
c4f35dd8
MK		 1875
1876 /* Do we have a frame? */
1877 int frameless_p;
1878};
8dda9770 1879
d2449ee8 1880/* Initialize a frame cache. */
c4f35dd8 1881
d2449ee8
DJ		 1882static void
1883amd64_init_frame_cache (struct amd64_frame_cache *cache)
8dda9770 1884{
c4f35dd8
MK		 1885 int i;
1886
c4f35dd8
MK		 1887 /* Base address. */
1888 cache->base = 0;
8fbca658 1889 cache->base_p = 0;
c4f35dd8
MK		 1890 cache->sp_offset = -8;
1891 cache->pc = 0;
1892
1893 /* Saved registers. We initialize these to -1 since zero is a valid
bba66b87
DE		 1894 offset (that's where %rbp is supposed to be stored).
1895 The values start out as being offsets, and are later converted to
1896 addresses (at which point -1 is interpreted as an address, still meaning
1897 "invalid"). */
e53bef9f 1898 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 1899 cache->saved_regs[i] = -1;
1900 cache->saved_sp = 0;
e0c62198 1901 cache->saved_sp_reg = -1;
c4f35dd8
MK		 1902
1903 /* Frameless until proven otherwise. */
1904 cache->frameless_p = 1;
d2449ee8 1905}
c4f35dd8 1906
d2449ee8
DJ		 1907/* Allocate and initialize a frame cache. */
1908
1909static struct amd64_frame_cache *
1910amd64_alloc_frame_cache (void)
1911{
1912 struct amd64_frame_cache *cache;
1913
1914 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
1915 amd64_init_frame_cache (cache);
c4f35dd8 1916 return cache;
8dda9770 1917}
53e95fcf 1918
e0c62198
L		 1919/* GCC 4.4 and later, can put code in the prologue to realign the
1920 stack pointer. Check whether PC points to such code, and update
1921 CACHE accordingly. Return the first instruction after the code
1922 sequence or CURRENT_PC, whichever is smaller. If we don't
1923 recognize the code, return PC. */
1924
1925static CORE_ADDR
1926amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
1927 struct amd64_frame_cache *cache)
1928{
1929 /* There are 2 code sequences to re-align stack before the frame
1930 gets set up:
1931
1932 1. Use a caller-saved saved register:
1933
1934 leaq 8(%rsp), %reg
1935 andq $-XXX, %rsp
1936 pushq -8(%reg)
1937
1938 2. Use a callee-saved saved register:
1939
1940 pushq %reg
1941 leaq 16(%rsp), %reg
1942 andq $-XXX, %rsp
1943 pushq -8(%reg)
1944
1945 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1946
1947 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1948 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1949 */
1950
1951 gdb_byte buf[18];
1952 int reg, r;
1953 int offset, offset_and;
e0c62198 1954
bae8a07a 1955 if (target_read_code (pc, buf, sizeof buf))
e0c62198
L		 1956 return pc;
1957
1958 /* Check caller-saved saved register. The first instruction has
1959 to be "leaq 8(%rsp), %reg". */
1960 if ((buf[0] & 0xfb) == 0x48
1961 && buf[1] == 0x8d
1962 && buf[3] == 0x24
1963 && buf[4] == 0x8)
1964 {
1965 /* MOD must be binary 10 and R/M must be binary 100. */
1966 if ((buf[2] & 0xc7) != 0x44)
1967 return pc;
1968
1969 /* REG has register number. */
1970 reg = (buf[2] >> 3) & 7;
1971
1972 /* Check the REX.R bit. */
1973 if (buf[0] == 0x4c)
1974 reg += 8;
1975
1976 offset = 5;
1977 }
1978 else
1979 {
1980 /* Check callee-saved saved register. The first instruction
1981 has to be "pushq %reg". */
1982 reg = 0;
1983 if ((buf[0] & 0xf8) == 0x50)
1984 offset = 0;
1985 else if ((buf[0] & 0xf6) == 0x40
1986 && (buf[1] & 0xf8) == 0x50)
1987 {
1988 /* Check the REX.B bit. */
1989 if ((buf[0] & 1) != 0)
1990 reg = 8;
1991
1992 offset = 1;
1993 }
1994 else
1995 return pc;
1996
1997 /* Get register. */
1998 reg += buf[offset] & 0x7;
1999
2000 offset++;
2001
2002 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2003 if ((buf[offset] & 0xfb) != 0x48
2004 || buf[offset + 1] != 0x8d
2005 || buf[offset + 3] != 0x24
2006 || buf[offset + 4] != 0x10)
2007 return pc;
2008
2009 /* MOD must be binary 10 and R/M must be binary 100. */
2010 if ((buf[offset + 2] & 0xc7) != 0x44)
2011 return pc;
2012
2013 /* REG has register number. */
2014 r = (buf[offset + 2] >> 3) & 7;
2015
2016 /* Check the REX.R bit. */
2017 if (buf[offset] == 0x4c)
2018 r += 8;
2019
2020 /* Registers in pushq and leaq have to be the same. */
2021 if (reg != r)
2022 return pc;
2023
2024 offset += 5;
2025 }
2026
2027 /* Rigister can't be %rsp nor %rbp. */
2028 if (reg == 4 || reg == 5)
2029 return pc;
2030
2031 /* The next instruction has to be "andq $-XXX, %rsp". */
2032 if (buf[offset] != 0x48
2033 || buf[offset + 2] != 0xe4
2034 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2035 return pc;
2036
2037 offset_and = offset;
2038 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2039
2040 /* The next instruction has to be "pushq -8(%reg)". */
2041 r = 0;
2042 if (buf[offset] == 0xff)
2043 offset++;
2044 else if ((buf[offset] & 0xf6) == 0x40
2045 && buf[offset + 1] == 0xff)
2046 {
2047 /* Check the REX.B bit. */
2048 if ((buf[offset] & 0x1) != 0)
2049 r = 8;
2050 offset += 2;
2051 }
2052 else
2053 return pc;
2054
2055 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2056 01. */
2057 if (buf[offset + 1] != 0xf8
2058 || (buf[offset] & 0xf8) != 0x70)
2059 return pc;
2060
2061 /* R/M has register. */
2062 r += buf[offset] & 7;
2063
2064 /* Registers in leaq and pushq have to be the same. */
2065 if (reg != r)
2066 return pc;
2067
2068 if (current_pc > pc + offset_and)
35669430 2069 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
e0c62198 2070
325fac50 2071 return std::min (pc + offset + 2, current_pc);
e0c62198
L		 2072}
2073
ac142d96
L		 2074/* Similar to amd64_analyze_stack_align for x32. */
2075
2076static CORE_ADDR
2077amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2078 struct amd64_frame_cache *cache)
2079{
2080 /* There are 2 code sequences to re-align stack before the frame
2081 gets set up:
2082
2083 1. Use a caller-saved saved register:
2084
2085 leaq 8(%rsp), %reg
2086 andq $-XXX, %rsp
2087 pushq -8(%reg)
2088
2089 or
2090
2091 [addr32] leal 8(%rsp), %reg
2092 andl $-XXX, %esp
2093 [addr32] pushq -8(%reg)
2094
2095 2. Use a callee-saved saved register:
2096
2097 pushq %reg
2098 leaq 16(%rsp), %reg
2099 andq $-XXX, %rsp
2100 pushq -8(%reg)
2101
2102 or
2103
2104 pushq %reg
2105 [addr32] leal 16(%rsp), %reg
2106 andl $-XXX, %esp
2107 [addr32] pushq -8(%reg)
2108
2109 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2110
2111 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2112 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2113
2114 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2115
2116 0x83 0xe4 0xf0 andl $-16, %esp
2117 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2118 */
2119
2120 gdb_byte buf[19];
2121 int reg, r;
2122 int offset, offset_and;
2123
2124 if (target_read_memory (pc, buf, sizeof buf))
2125 return pc;
2126
2127 /* Skip optional addr32 prefix. */
2128 offset = buf[0] == 0x67 ? 1 : 0;
2129
2130 /* Check caller-saved saved register. The first instruction has
2131 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2132 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2133 && buf[offset + 1] == 0x8d
2134 && buf[offset + 3] == 0x24
2135 && buf[offset + 4] == 0x8)
2136 {
2137 /* MOD must be binary 10 and R/M must be binary 100. */
2138 if ((buf[offset + 2] & 0xc7) != 0x44)
2139 return pc;
2140
2141 /* REG has register number. */
2142 reg = (buf[offset + 2] >> 3) & 7;
2143
2144 /* Check the REX.R bit. */
2145 if ((buf[offset] & 0x4) != 0)
2146 reg += 8;
2147
2148 offset += 5;
2149 }
2150 else
2151 {
2152 /* Check callee-saved saved register. The first instruction
2153 has to be "pushq %reg". */
2154 reg = 0;
2155 if ((buf[offset] & 0xf6) == 0x40
2156 && (buf[offset + 1] & 0xf8) == 0x50)
2157 {
2158 /* Check the REX.B bit. */
2159 if ((buf[offset] & 1) != 0)
2160 reg = 8;
2161
2162 offset += 1;
2163 }
2164 else if ((buf[offset] & 0xf8) != 0x50)
2165 return pc;
2166
2167 /* Get register. */
2168 reg += buf[offset] & 0x7;
2169
2170 offset++;
2171
2172 /* Skip optional addr32 prefix. */
2173 if (buf[offset] == 0x67)
2174 offset++;
2175
2176 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2177 "leal 16(%rsp), %reg". */
2178 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2179 || buf[offset + 1] != 0x8d
2180 || buf[offset + 3] != 0x24
2181 || buf[offset + 4] != 0x10)
2182 return pc;
2183
2184 /* MOD must be binary 10 and R/M must be binary 100. */
2185 if ((buf[offset + 2] & 0xc7) != 0x44)
2186 return pc;
2187
2188 /* REG has register number. */
2189 r = (buf[offset + 2] >> 3) & 7;
2190
2191 /* Check the REX.R bit. */
2192 if ((buf[offset] & 0x4) != 0)
2193 r += 8;
2194
2195 /* Registers in pushq and leaq have to be the same. */
2196 if (reg != r)
2197 return pc;
2198
2199 offset += 5;
2200 }
2201
2202 /* Rigister can't be %rsp nor %rbp. */
2203 if (reg == 4 || reg == 5)
2204 return pc;
2205
2206 /* The next instruction may be "andq $-XXX, %rsp" or
2207 "andl $-XXX, %esp". */
2208 if (buf[offset] != 0x48)
2209 offset--;
2210
2211 if (buf[offset + 2] != 0xe4
2212 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2213 return pc;
2214
2215 offset_and = offset;
2216 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2217
2218 /* Skip optional addr32 prefix. */
2219 if (buf[offset] == 0x67)
2220 offset++;
2221
2222 /* The next instruction has to be "pushq -8(%reg)". */
2223 r = 0;
2224 if (buf[offset] == 0xff)
2225 offset++;
2226 else if ((buf[offset] & 0xf6) == 0x40
2227 && buf[offset + 1] == 0xff)
2228 {
2229 /* Check the REX.B bit. */
2230 if ((buf[offset] & 0x1) != 0)
2231 r = 8;
2232 offset += 2;
2233 }
2234 else
2235 return pc;
2236
2237 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2238 01. */
2239 if (buf[offset + 1] != 0xf8
2240 || (buf[offset] & 0xf8) != 0x70)
2241 return pc;
2242
2243 /* R/M has register. */
2244 r += buf[offset] & 7;
2245
2246 /* Registers in leaq and pushq have to be the same. */
2247 if (reg != r)
2248 return pc;
2249
2250 if (current_pc > pc + offset_and)
2251 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2252
325fac50 2253 return std::min (pc + offset + 2, current_pc);
ac142d96
L		 2254}
2255
c4f35dd8
MK		 2256/* Do a limited analysis of the prologue at PC and update CACHE
2257 accordingly. Bail out early if CURRENT_PC is reached. Return the
2258 address where the analysis stopped.
2259
2260 We will handle only functions beginning with:
2261
2262 pushq %rbp 0x55
50f1ae7b 2263 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
c4f35dd8 2264
649e6d92
MK		 2265 or (for the X32 ABI):
2266
2267 pushq %rbp 0x55
2268 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2269
2270 Any function that doesn't start with one of these sequences will be
2271 assumed to have no prologue and thus no valid frame pointer in
2272 %rbp. */
c4f35dd8
MK		 2273
2274static CORE_ADDR
e17a4113
UW		 2275amd64_analyze_prologue (struct gdbarch *gdbarch,
2276 CORE_ADDR pc, CORE_ADDR current_pc,
e53bef9f 2277 struct amd64_frame_cache *cache)
53e95fcf 2278{
e17a4113 2279 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
50f1ae7b
DE		 2280 /* There are two variations of movq %rsp, %rbp. */
2281 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2282 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
649e6d92
MK		 2283 /* Ditto for movl %esp, %ebp. */
2284 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2285 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2286
d8de1ef7
MK		 2287 gdb_byte buf[3];
2288 gdb_byte op;
c4f35dd8
MK		 2289
2290 if (current_pc <= pc)
2291 return current_pc;
2292
ac142d96
L		 2293 if (gdbarch_ptr_bit (gdbarch) == 32)
2294 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2295 else
2296 pc = amd64_analyze_stack_align (pc, current_pc, cache);
e0c62198 2297
bae8a07a 2298 op = read_code_unsigned_integer (pc, 1, byte_order);
c4f35dd8
MK		 2299
2300 if (op == 0x55) /* pushq %rbp */
2301 {
2302 /* Take into account that we've executed the `pushq %rbp' that
2303 starts this instruction sequence. */
90f90721 2304 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
c4f35dd8
MK		 2305 cache->sp_offset += 8;
2306
2307 /* If that's all, return now. */
2308 if (current_pc <= pc + 1)
2309 return current_pc;
2310
bae8a07a 2311 read_code (pc + 1, buf, 3);
c4f35dd8 2312
649e6d92
MK		 2313 /* Check for `movq %rsp, %rbp'. */
2314 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2315 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2316 {
2317 /* OK, we actually have a frame. */
2318 cache->frameless_p = 0;
2319 return pc + 4;
2320 }
2321
2322 /* For X32, also check for `movq %esp, %ebp'. */
2323 if (gdbarch_ptr_bit (gdbarch) == 32)
2324 {
2325 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2326 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2327 {
2328 /* OK, we actually have a frame. */
2329 cache->frameless_p = 0;
2330 return pc + 3;
2331 }
2332 }
2333
2334 return pc + 1;
c4f35dd8
MK		 2335 }
2336
2337 return pc;
53e95fcf
JS		 2338}
2339
df15bd07
JK		 2340/* Work around false termination of prologue - GCC PR debug/48827.
2341
2342 START_PC is the first instruction of a function, PC is its minimal already
2343 determined advanced address. Function returns PC if it has nothing to do.
2344
2345 84 c0 test %al,%al
2346 74 23 je after
2347 <-- here is 0 lines advance - the false prologue end marker.
2348 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2349 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2350 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2351 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2352 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2353 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2354 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2355 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2356 after: */
c4f35dd8
MK		 2357
2358static CORE_ADDR
df15bd07 2359amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
53e95fcf 2360{
08711b9a
JK		 2361 struct symtab_and_line start_pc_sal, next_sal;
2362 gdb_byte buf[4 + 8 * 7];
2363 int offset, xmmreg;
c4f35dd8 2364
08711b9a
JK		 2365 if (pc == start_pc)
2366 return pc;
2367
2368 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2369 if (start_pc_sal.symtab == NULL
43f3e411
DE		 2370 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2371 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
08711b9a
JK		 2372 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2373 return pc;
2374
2375 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2376 if (next_sal.line != start_pc_sal.line)
2377 return pc;
2378
2379 /* START_PC can be from overlayed memory, ignored here. */
bae8a07a 2380 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
08711b9a
JK		 2381 return pc;
2382
2383 /* test %al,%al */
2384 if (buf[0] != 0x84 || buf[1] != 0xc0)
2385 return pc;
2386 /* je AFTER */
2387 if (buf[2] != 0x74)
2388 return pc;
2389
2390 offset = 4;
2391 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2392 {
bede5f5f 2393 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
08711b9a 2394 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
bede5f5f 2395 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
08711b9a
JK		 2396 return pc;
2397
bede5f5f
JK		 2398 /* 0b01?????? */
2399 if ((buf[offset + 2] & 0xc0) == 0x40)
08711b9a
JK		 2400 {
2401 /* 8-bit displacement. */
2402 offset += 4;
2403 }
bede5f5f
JK		 2404 /* 0b10?????? */
2405 else if ((buf[offset + 2] & 0xc0) == 0x80)
08711b9a
JK		 2406 {
2407 /* 32-bit displacement. */
2408 offset += 7;
2409 }
2410 else
2411 return pc;
2412 }
2413
2414 /* je AFTER */
2415 if (offset - 4 != buf[3])
2416 return pc;
2417
2418 return next_sal.end;
53e95fcf 2419}
df15bd07
JK		 2420
2421/* Return PC of first real instruction. */
2422
2423static CORE_ADDR
2424amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2425{
2426 struct amd64_frame_cache cache;
2427 CORE_ADDR pc;
56bf0743
KB		 2428 CORE_ADDR func_addr;
2429
2430 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2431 {
2432 CORE_ADDR post_prologue_pc
2433 = skip_prologue_using_sal (gdbarch, func_addr);
43f3e411 2434 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
56bf0743
KB		 2435
2436 /* Clang always emits a line note before the prologue and another
2437 one after. We trust clang to emit usable line notes. */
2438 if (post_prologue_pc
43f3e411
DE		 2439 && (cust != NULL
2440 && COMPUNIT_PRODUCER (cust) != NULL
61012eef 2441 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
325fac50 2442 return std::max (start_pc, post_prologue_pc);
56bf0743 2443 }
df15bd07
JK		 2444
2445 amd64_init_frame_cache (&cache);
2446 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2447 &cache);
2448 if (cache.frameless_p)
2449 return start_pc;
2450
2451 return amd64_skip_xmm_prologue (pc, start_pc);
2452}
c4f35dd8 2453\f
53e95fcf 2454
c4f35dd8
MK		 2455/* Normal frames. */
2456
8fbca658
PA		 2457static void
2458amd64_frame_cache_1 (struct frame_info *this_frame,
2459 struct amd64_frame_cache *cache)
6d686a84 2460{
e17a4113
UW		 2461 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2462 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 2463 gdb_byte buf[8];
6d686a84 2464 int i;
6d686a84 2465
10458914 2466 cache->pc = get_frame_func (this_frame);
c4f35dd8 2467 if (cache->pc != 0)
e17a4113
UW		 2468 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2469 cache);
c4f35dd8
MK		 2470
2471 if (cache->frameless_p)
2472 {
4a28816e
MK		 2473 /* We didn't find a valid frame. If we're at the start of a
2474 function, or somewhere half-way its prologue, the function's
2475 frame probably hasn't been fully setup yet. Try to
2476 reconstruct the base address for the stack frame by looking
2477 at the stack pointer. For truly "frameless" functions this
2478 might work too. */
c4f35dd8 2479
e0c62198
L		 2480 if (cache->saved_sp_reg != -1)
2481 {
8fbca658
PA		 2482 /* Stack pointer has been saved. */
2483 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2484 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2485
e0c62198
L		 2486 /* We're halfway aligning the stack. */
2487 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2488 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2489
2490 /* This will be added back below. */
2491 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2492 }
2493 else
2494 {
2495 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
e17a4113
UW		 2496 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2497 + cache->sp_offset;
e0c62198 2498 }
c4f35dd8 2499 }
35883a3f
MK		 2500 else
2501 {
10458914 2502 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
e17a4113 2503 cache->base = extract_unsigned_integer (buf, 8, byte_order);
35883a3f 2504 }
c4f35dd8
MK		 2505
2506 /* Now that we have the base address for the stack frame we can
2507 calculate the value of %rsp in the calling frame. */
2508 cache->saved_sp = cache->base + 16;
2509
35883a3f
MK		 2510 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2511 frame we find it at the same offset from the reconstructed base
e0c62198
L		 2512 address. If we're halfway aligning the stack, %rip is handled
2513 differently (see above). */
2514 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2515 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
35883a3f 2516
c4f35dd8
MK		 2517 /* Adjust all the saved registers such that they contain addresses
2518 instead of offsets. */
e53bef9f 2519 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 2520 if (cache->saved_regs[i] != -1)
2521 cache->saved_regs[i] += cache->base;
2522
8fbca658
PA		 2523 cache->base_p = 1;
2524}
2525
2526static struct amd64_frame_cache *
2527amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2528{
8fbca658
PA		 2529 struct amd64_frame_cache *cache;
2530
2531 if (*this_cache)
9a3c8263 2532 return (struct amd64_frame_cache *) *this_cache;
8fbca658
PA		 2533
2534 cache = amd64_alloc_frame_cache ();
2535 *this_cache = cache;
2536
492d29ea 2537 TRY
8fbca658
PA		 2538 {
2539 amd64_frame_cache_1 (this_frame, cache);
2540 }
492d29ea 2541 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2542 {
2543 if (ex.error != NOT_AVAILABLE_ERROR)
2544 throw_exception (ex);
2545 }
492d29ea 2546 END_CATCH
8fbca658 2547
c4f35dd8 2548 return cache;
6d686a84
ML		 2549}
2550
8fbca658
PA		 2551static enum unwind_stop_reason
2552amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2553 void **this_cache)
2554{
2555 struct amd64_frame_cache *cache =
2556 amd64_frame_cache (this_frame, this_cache);
2557
2558 if (!cache->base_p)
2559 return UNWIND_UNAVAILABLE;
2560
2561 /* This marks the outermost frame. */
2562 if (cache->base == 0)
2563 return UNWIND_OUTERMOST;
2564
2565 return UNWIND_NO_REASON;
2566}
2567
c4f35dd8 2568static void
10458914 2569amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
e53bef9f 2570 struct frame_id *this_id)
c4f35dd8 2571{
e53bef9f 2572 struct amd64_frame_cache *cache =
10458914 2573 amd64_frame_cache (this_frame, this_cache);
c4f35dd8 2574
8fbca658 2575 if (!cache->base_p)
5ce0145d
PA		 2576 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2577 else if (cache->base == 0)
2578 {
2579 /* This marks the outermost frame. */
2580 return;
2581 }
2582 else
2583 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
c4f35dd8 2584}
e76e1718 2585
10458914
DJ		 2586static struct value *
2587amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2588 int regnum)
53e95fcf 2589{
10458914 2590 struct gdbarch *gdbarch = get_frame_arch (this_frame);
e53bef9f 2591 struct amd64_frame_cache *cache =
10458914 2592 amd64_frame_cache (this_frame, this_cache);
e76e1718 2593
c4f35dd8 2594 gdb_assert (regnum >= 0);
b1ab997b 2595
2ae02b47 2596 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
10458914 2597 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
e76e1718 2598
e53bef9f 2599 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
10458914
DJ		 2600 return frame_unwind_got_memory (this_frame, regnum,
2601 cache->saved_regs[regnum]);
e76e1718 2602
10458914 2603 return frame_unwind_got_register (this_frame, regnum, regnum);
c4f35dd8 2604}
e76e1718 2605
e53bef9f 2606static const struct frame_unwind amd64_frame_unwind =
c4f35dd8
MK		 2607{
2608 NORMAL_FRAME,
8fbca658 2609 amd64_frame_unwind_stop_reason,
e53bef9f 2610 amd64_frame_this_id,
10458914
DJ		 2611 amd64_frame_prev_register,
2612 NULL,
2613 default_frame_sniffer
c4f35dd8 2614};
c4f35dd8 2615\f
6710bf39
SS		 2616/* Generate a bytecode expression to get the value of the saved PC. */
2617
2618static void
2619amd64_gen_return_address (struct gdbarch *gdbarch,
2620 struct agent_expr *ax, struct axs_value *value,
2621 CORE_ADDR scope)
2622{
2623 /* The following sequence assumes the traditional use of the base
2624 register. */
2625 ax_reg (ax, AMD64_RBP_REGNUM);
2626 ax_const_l (ax, 8);
2627 ax_simple (ax, aop_add);
2628 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2629 value->kind = axs_lvalue_memory;
2630}
2631\f
e76e1718 2632
c4f35dd8
MK		 2633/* Signal trampolines. */
2634
2635/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2636 64-bit variants. This would require using identical frame caches
2637 on both platforms. */
2638
e53bef9f 2639static struct amd64_frame_cache *
10458914 2640amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2641{
e17a4113
UW		 2642 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2643 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2644 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e53bef9f 2645 struct amd64_frame_cache *cache;
c4f35dd8 2646 CORE_ADDR addr;
d8de1ef7 2647 gdb_byte buf[8];
2b5e0749 2648 int i;
c4f35dd8
MK		 2649
2650 if (*this_cache)
9a3c8263 2651 return (struct amd64_frame_cache *) *this_cache;
c4f35dd8 2652
e53bef9f 2653 cache = amd64_alloc_frame_cache ();
c4f35dd8 2654
492d29ea 2655 TRY
8fbca658
PA		 2656 {
2657 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2658 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2659
2660 addr = tdep->sigcontext_addr (this_frame);
2661 gdb_assert (tdep->sc_reg_offset);
2662 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2663 for (i = 0; i < tdep->sc_num_regs; i++)
2664 if (tdep->sc_reg_offset[i] != -1)
2665 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
c4f35dd8 2666
8fbca658
PA		 2667 cache->base_p = 1;
2668 }
492d29ea 2669 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2670 {
2671 if (ex.error != NOT_AVAILABLE_ERROR)
2672 throw_exception (ex);
2673 }
492d29ea 2674 END_CATCH
c4f35dd8
MK		 2675
2676 *this_cache = cache;
2677 return cache;
53e95fcf
JS		 2678}
2679
8fbca658
PA		 2680static enum unwind_stop_reason
2681amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2682 void **this_cache)
2683{
2684 struct amd64_frame_cache *cache =
2685 amd64_sigtramp_frame_cache (this_frame, this_cache);
2686
2687 if (!cache->base_p)
2688 return UNWIND_UNAVAILABLE;
2689
2690 return UNWIND_NO_REASON;
2691}
2692
c4f35dd8 2693static void
10458914 2694amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
e53bef9f 2695 void **this_cache, struct frame_id *this_id)
c4f35dd8 2696{
e53bef9f 2697 struct amd64_frame_cache *cache =
10458914 2698 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2699
8fbca658 2700 if (!cache->base_p)
5ce0145d
PA		 2701 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2702 else if (cache->base == 0)
2703 {
2704 /* This marks the outermost frame. */
2705 return;
2706 }
2707 else
2708 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
c4f35dd8
MK		 2709}
2710
10458914
DJ		 2711static struct value *
2712amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2713 void **this_cache, int regnum)
c4f35dd8
MK		 2714{
2715 /* Make sure we've initialized the cache. */
10458914 2716 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2717
10458914 2718 return amd64_frame_prev_register (this_frame, this_cache, regnum);
c4f35dd8
MK		 2719}
2720
10458914
DJ		 2721static int
2722amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2723 struct frame_info *this_frame,
2724 void **this_cache)
c4f35dd8 2725{
10458914 2726 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
911bc6ee
MK		 2727
2728 /* We shouldn't even bother if we don't have a sigcontext_addr
2729 handler. */
2730 if (tdep->sigcontext_addr == NULL)
10458914 2731 return 0;
911bc6ee
MK		 2732
2733 if (tdep->sigtramp_p != NULL)
2734 {
10458914
DJ		 2735 if (tdep->sigtramp_p (this_frame))
2736 return 1;
911bc6ee 2737 }
c4f35dd8 2738
911bc6ee 2739 if (tdep->sigtramp_start != 0)
1c3545ae 2740 {
10458914 2741 CORE_ADDR pc = get_frame_pc (this_frame);
1c3545ae 2742
911bc6ee
MK		 2743 gdb_assert (tdep->sigtramp_end != 0);
2744 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
10458914 2745 return 1;
1c3545ae 2746 }
c4f35dd8 2747
10458914 2748 return 0;
c4f35dd8 2749}
10458914
DJ		 2750
2751static const struct frame_unwind amd64_sigtramp_frame_unwind =
2752{
2753 SIGTRAMP_FRAME,
8fbca658 2754 amd64_sigtramp_frame_unwind_stop_reason,
10458914
DJ		 2755 amd64_sigtramp_frame_this_id,
2756 amd64_sigtramp_frame_prev_register,
2757 NULL,
2758 amd64_sigtramp_frame_sniffer
2759};
c4f35dd8
MK		 2760\f
2761
2762static CORE_ADDR
10458914 2763amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2764{
e53bef9f 2765 struct amd64_frame_cache *cache =
10458914 2766 amd64_frame_cache (this_frame, this_cache);
c4f35dd8
MK		 2767
2768 return cache->base;
2769}
2770
e53bef9f 2771static const struct frame_base amd64_frame_base =
c4f35dd8 2772{
e53bef9f
MK		 2773 &amd64_frame_unwind,
2774 amd64_frame_base_address,
2775 amd64_frame_base_address,
2776 amd64_frame_base_address
c4f35dd8
MK		 2777};
2778
872761f4
MS		 2779/* Normal frames, but in a function epilogue. */
2780
c9cf6e20
MG		 2781/* Implement the stack_frame_destroyed_p gdbarch method.
2782
2783 The epilogue is defined here as the 'ret' instruction, which will
872761f4
MS		 2784 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2785 the function's stack frame. */
2786
2787static int
c9cf6e20 2788amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
872761f4
MS		 2789{
2790 gdb_byte insn;
43f3e411 2791 struct compunit_symtab *cust;
e0d00bc7 2792
43f3e411
DE		 2793 cust = find_pc_compunit_symtab (pc);
2794 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
e0d00bc7 2795 return 0;
872761f4
MS		 2796
2797 if (target_read_memory (pc, &insn, 1))
2798 return 0; /* Can't read memory at pc. */
2799
2800 if (insn != 0xc3) /* 'ret' instruction. */
2801 return 0;
2802
2803 return 1;
2804}
2805
2806static int
2807amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2808 struct frame_info *this_frame,
2809 void **this_prologue_cache)
2810{
2811 if (frame_relative_level (this_frame) == 0)
c9cf6e20
MG		 2812 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2813 get_frame_pc (this_frame));
872761f4
MS		 2814 else
2815 return 0;
2816}
2817
2818static struct amd64_frame_cache *
2819amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2820{
2821 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2822 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2823 struct amd64_frame_cache *cache;
6c10c06b 2824 gdb_byte buf[8];
872761f4
MS		 2825
2826 if (*this_cache)
9a3c8263 2827 return (struct amd64_frame_cache *) *this_cache;
872761f4
MS		 2828
2829 cache = amd64_alloc_frame_cache ();
2830 *this_cache = cache;
2831
492d29ea 2832 TRY
8fbca658
PA		 2833 {
2834 /* Cache base will be %esp plus cache->sp_offset (-8). */
2835 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2836 cache->base = extract_unsigned_integer (buf, 8,
2837 byte_order) + cache->sp_offset;
2838
2839 /* Cache pc will be the frame func. */
2840 cache->pc = get_frame_pc (this_frame);
872761f4 2841
8fbca658
PA		 2842 /* The saved %esp will be at cache->base plus 16. */
2843 cache->saved_sp = cache->base + 16;
872761f4 2844
8fbca658
PA		 2845 /* The saved %eip will be at cache->base plus 8. */
2846 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
872761f4 2847
8fbca658
PA		 2848 cache->base_p = 1;
2849 }
492d29ea 2850 CATCH (ex, RETURN_MASK_ERROR)
7556d4a4
PA		 2851 {
2852 if (ex.error != NOT_AVAILABLE_ERROR)
2853 throw_exception (ex);
2854 }
492d29ea 2855 END_CATCH
872761f4
MS		 2856
2857 return cache;
2858}
2859
8fbca658
PA		 2860static enum unwind_stop_reason
2861amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2862 void **this_cache)
2863{
2864 struct amd64_frame_cache *cache
2865 = amd64_epilogue_frame_cache (this_frame, this_cache);
2866
2867 if (!cache->base_p)
2868 return UNWIND_UNAVAILABLE;
2869
2870 return UNWIND_NO_REASON;
2871}
2872
872761f4
MS		 2873static void
2874amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2875 void **this_cache,
2876 struct frame_id *this_id)
2877{
2878 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2879 this_cache);
2880
8fbca658 2881 if (!cache->base_p)
5ce0145d
PA		 2882 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2883 else
2884 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
872761f4
MS		 2885}
2886
2887static const struct frame_unwind amd64_epilogue_frame_unwind =
2888{
2889 NORMAL_FRAME,
8fbca658 2890 amd64_epilogue_frame_unwind_stop_reason,
872761f4
MS		 2891 amd64_epilogue_frame_this_id,
2892 amd64_frame_prev_register,
2893 NULL,
2894 amd64_epilogue_frame_sniffer
2895};
2896
166f4c7b 2897static struct frame_id
10458914 2898amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
166f4c7b 2899{
c4f35dd8
MK		 2900 CORE_ADDR fp;
2901
10458914 2902 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
c4f35dd8 2903
10458914 2904 return frame_id_build (fp + 16, get_frame_pc (this_frame));
166f4c7b
ML		 2905}
2906
8b148df9
AC		 2907/* 16 byte align the SP per frame requirements. */
2908
2909static CORE_ADDR
e53bef9f 2910amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
8b148df9
AC		 2911{
2912 return sp & -(CORE_ADDR)16;
2913}
473f17b0
MK		 2914\f
2915
593adc23
MK		 2916/* Supply register REGNUM from the buffer specified by FPREGS and LEN
2917 in the floating-point register set REGSET to register cache
2918 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
473f17b0
MK		 2919
2920static void
e53bef9f
MK		 2921amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
2922 int regnum, const void *fpregs, size_t len)
473f17b0 2923{
09424cff
AA		 2924 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2925 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
473f17b0 2926
1528345d 2927 gdb_assert (len >= tdep->sizeof_fpregset);
90f90721 2928 amd64_supply_fxsave (regcache, regnum, fpregs);
473f17b0 2929}
8b148df9 2930
593adc23
MK		 2931/* Collect register REGNUM from the register cache REGCACHE and store
2932 it in the buffer specified by FPREGS and LEN as described by the
2933 floating-point register set REGSET. If REGNUM is -1, do this for
2934 all registers in REGSET. */
2935
2936static void
2937amd64_collect_fpregset (const struct regset *regset,
2938 const struct regcache *regcache,
2939 int regnum, void *fpregs, size_t len)
2940{
09424cff
AA		 2941 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2942 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
593adc23 2943
1528345d 2944 gdb_assert (len >= tdep->sizeof_fpregset);
593adc23
MK		 2945 amd64_collect_fxsave (regcache, regnum, fpregs);
2946}
2947
8f0435f7 2948const struct regset amd64_fpregset =
ecc37a5a
AA		 2949 {
2950 NULL, amd64_supply_fpregset, amd64_collect_fpregset
2951 };
c6b33596
MK		 2952\f
2953
436675d3
PA		 2954/* Figure out where the longjmp will land. Slurp the jmp_buf out of
2955 %rdi. We expect its value to be a pointer to the jmp_buf structure
2956 from which we extract the address that we will land at. This
2957 address is copied into PC. This routine returns non-zero on
2958 success. */
2959
2960static int
2961amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2962{
2963 gdb_byte buf[8];
2964 CORE_ADDR jb_addr;
2965 struct gdbarch *gdbarch = get_frame_arch (frame);
2966 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
0dfff4cb 2967 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 2968
2969 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2970 longjmp will land. */
2971 if (jb_pc_offset == -1)
2972 return 0;
2973
2974 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
0dfff4cb
UW		 2975 jb_addr= extract_typed_address
2976 (buf, builtin_type (gdbarch)->builtin_data_ptr);
436675d3
PA		 2977 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
2978 return 0;
2979
0dfff4cb 2980 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 2981
2982 return 1;
2983}
2984
cf648174
HZ		 2985static const int amd64_record_regmap[] =
2986{
2987 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
2988 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
2989 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
2990 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
2991 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
2992 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
2993};
2994
2213a65d 2995void
90f90721 2996amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
53e95fcf 2997{
0c1a73d6 2998 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
90884b2b 2999 const struct target_desc *tdesc = info.target_desc;
05c0465e
SDJ		 3000 static const char *const stap_integer_prefixes[] = { "$", NULL };
3001 static const char *const stap_register_prefixes[] = { "%", NULL };
3002 static const char *const stap_register_indirection_prefixes[] = { "(",
3003 NULL };
3004 static const char *const stap_register_indirection_suffixes[] = { ")",
3005 NULL };
53e95fcf 3006
473f17b0
MK		 3007 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3008 floating-point registers. */
3009 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
8f0435f7 3010 tdep->fpregset = &amd64_fpregset;
473f17b0 3011
90884b2b
L		 3012 if (! tdesc_has_registers (tdesc))
3013 tdesc = tdesc_amd64;
3014 tdep->tdesc = tdesc;
3015
3016 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
3017 tdep->register_names = amd64_register_names;
3018
01f9f808
MS		 3019 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
3020 {
3021 tdep->zmmh_register_names = amd64_zmmh_names;
3022 tdep->k_register_names = amd64_k_names;
3023 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
3024 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
3025
3026 tdep->num_zmm_regs = 32;
3027 tdep->num_xmm_avx512_regs = 16;
3028 tdep->num_ymm_avx512_regs = 16;
3029
3030 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
3031 tdep->k0_regnum = AMD64_K0_REGNUM;
3032 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3033 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3034 }
3035
a055a187
L		 3036 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3037 {
3038 tdep->ymmh_register_names = amd64_ymmh_names;
3039 tdep->num_ymm_regs = 16;
3040 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3041 }
3042
e43e105e
WT		 3043 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3044 {
3045 tdep->mpx_register_names = amd64_mpx_names;
3046 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3047 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3048 }
3049
fe01d668 3050 tdep->num_byte_regs = 20;
1ba53b71
L		 3051 tdep->num_word_regs = 16;
3052 tdep->num_dword_regs = 16;
3053 /* Avoid wiring in the MMX registers for now. */
3054 tdep->num_mmx_regs = 0;
3055
3543a589
TT		 3056 set_gdbarch_pseudo_register_read_value (gdbarch,
3057 amd64_pseudo_register_read_value);
1ba53b71
L		 3058 set_gdbarch_pseudo_register_write (gdbarch,
3059 amd64_pseudo_register_write);
62e5fd57
MK		 3060 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3061 amd64_ax_pseudo_register_collect);
1ba53b71
L		 3062
3063 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3064
5716833c 3065 /* AMD64 has an FPU and 16 SSE registers. */
90f90721 3066 tdep->st0_regnum = AMD64_ST0_REGNUM;
0c1a73d6 3067 tdep->num_xmm_regs = 16;
53e95fcf 3068
0c1a73d6 3069 /* This is what all the fuss is about. */
53e95fcf
JS		 3070 set_gdbarch_long_bit (gdbarch, 64);
3071 set_gdbarch_long_long_bit (gdbarch, 64);
3072 set_gdbarch_ptr_bit (gdbarch, 64);
3073
e53bef9f
MK		 3074 /* In contrast to the i386, on AMD64 a `long double' actually takes
3075 up 128 bits, even though it's still based on the i387 extended
3076 floating-point format which has only 80 significant bits. */
b83b026c
MK		 3077 set_gdbarch_long_double_bit (gdbarch, 128);
3078
e53bef9f 3079 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
b83b026c
MK		 3080
3081 /* Register numbers of various important registers. */
90f90721
MK		 3082 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3083 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3084 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3085 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
b83b026c 3086
e53bef9f
MK		 3087 /* The "default" register numbering scheme for AMD64 is referred to
3088 as the "DWARF Register Number Mapping" in the System V psABI.
3089 The preferred debugging format for all known AMD64 targets is
3090 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3091 DWARF-1), but we provide the same mapping just in case. This
3092 mapping is also used for stabs, which GCC does support. */
3093 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
e53bef9f 3094 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
de220d0f 3095
c4f35dd8 3096 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
e53bef9f 3097 be in use on any of the supported AMD64 targets. */
53e95fcf 3098
c4f35dd8 3099 /* Call dummy code. */
e53bef9f
MK		 3100 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3101 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
8b148df9 3102 set_gdbarch_frame_red_zone_size (gdbarch, 128);
53e95fcf 3103
83acabca 3104 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
d532c08f
MK		 3105 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3106 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3107
efb1c01c 3108 set_gdbarch_return_value (gdbarch, amd64_return_value);
53e95fcf 3109
e53bef9f 3110 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
53e95fcf 3111
cf648174
HZ		 3112 tdep->record_regmap = amd64_record_regmap;
3113
10458914 3114 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
53e95fcf 3115
872761f4
MS		 3116 /* Hook the function epilogue frame unwinder. This unwinder is
3117 appended to the list first, so that it supercedes the other
3118 unwinders in function epilogues. */
3119 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3120
3121 /* Hook the prologue-based frame unwinders. */
10458914
DJ		 3122 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3123 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
e53bef9f 3124 frame_base_set_default (gdbarch, &amd64_frame_base);
c6b33596 3125
436675d3 3126 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
dde08ee1
PA		 3127
3128 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
6710bf39
SS		 3129
3130 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
55aa24fb
SDJ		 3131
3132 /* SystemTap variables and functions. */
05c0465e
SDJ		 3133 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3134 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3135 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3136 stap_register_indirection_prefixes);
3137 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3138 stap_register_indirection_suffixes);
55aa24fb
SDJ		 3139 set_gdbarch_stap_is_single_operand (gdbarch,
3140 i386_stap_is_single_operand);
3141 set_gdbarch_stap_parse_special_token (gdbarch,
3142 i386_stap_parse_special_token);
c2170eef
MM		 3143 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3144 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3145 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
c4f35dd8 3146}
fff4548b
MK		 3147\f
3148
3149static struct type *
3150amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3151{
3152 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3153
3154 switch (regnum - tdep->eax_regnum)
3155 {
3156 case AMD64_RBP_REGNUM: /* %ebp */
3157 case AMD64_RSP_REGNUM: /* %esp */
3158 return builtin_type (gdbarch)->builtin_data_ptr;
3159 case AMD64_RIP_REGNUM: /* %eip */
3160 return builtin_type (gdbarch)->builtin_func_ptr;
3161 }
3162
3163 return i386_pseudo_register_type (gdbarch, regnum);
3164}
3165
3166void
3167amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3168{
3169 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3170 const struct target_desc *tdesc = info.target_desc;
3171
3172 amd64_init_abi (info, gdbarch);
3173
3174 if (! tdesc_has_registers (tdesc))
3175 tdesc = tdesc_x32;
3176 tdep->tdesc = tdesc;
3177
3178 tdep->num_dword_regs = 17;
3179 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3180
3181 set_gdbarch_long_bit (gdbarch, 32);
3182 set_gdbarch_ptr_bit (gdbarch, 32);
3183}
90884b2b 3184
97de3545
JB		 3185/* Return the target description for a specified XSAVE feature mask. */
3186
3187const struct target_desc *
3188amd64_target_description (uint64_t xcr0)
3189{
3190 switch (xcr0 & X86_XSTATE_ALL_MASK)
3191 {
3192 case X86_XSTATE_MPX_AVX512_MASK:
3193 case X86_XSTATE_AVX512_MASK:
3194 return tdesc_amd64_avx512;
3195 case X86_XSTATE_MPX_MASK:
3196 return tdesc_amd64_mpx;
2b863f51
WT		 3197 case X86_XSTATE_AVX_MPX_MASK:
3198 return tdesc_amd64_avx_mpx;
97de3545
JB		 3199 case X86_XSTATE_AVX_MASK:
3200 return tdesc_amd64_avx;
3201 default:
3202 return tdesc_amd64;
3203 }
3204}
3205
90884b2b
L		 3206/* Provide a prototype to silence -Wmissing-prototypes. */
3207void _initialize_amd64_tdep (void);
3208
3209void
3210_initialize_amd64_tdep (void)
3211{
3212 initialize_tdesc_amd64 ();
a055a187 3213 initialize_tdesc_amd64_avx ();
e43e105e 3214 initialize_tdesc_amd64_mpx ();
2b863f51 3215 initialize_tdesc_amd64_avx_mpx ();
01f9f808
MS		 3216 initialize_tdesc_amd64_avx512 ();
3217
ac1438b5
L		 3218 initialize_tdesc_x32 ();
3219 initialize_tdesc_x32_avx ();
01f9f808 3220 initialize_tdesc_x32_avx512 ();
90884b2b 3221}
c4f35dd8
MK		 3222\f
3223
41d041d6
MK		 3224/* The 64-bit FXSAVE format differs from the 32-bit format in the
3225 sense that the instruction pointer and data pointer are simply
3226 64-bit offsets into the code segment and the data segment instead
3227 of a selector offset pair. The functions below store the upper 32
3228 bits of these pointers (instead of just the 16-bits of the segment
3229 selector). */
3230
3231/* Fill register REGNUM in REGCACHE with the appropriate
0485f6ad
MK		 3232 floating-point or SSE register value from *FXSAVE. If REGNUM is
3233 -1, do this for all registers. This function masks off any of the
3234 reserved bits in *FXSAVE. */
c4f35dd8
MK		 3235
3236void
90f90721 3237amd64_supply_fxsave (struct regcache *regcache, int regnum,
20a6ec49 3238 const void *fxsave)
c4f35dd8 3239{
20a6ec49
MD		 3240 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3241 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3242
41d041d6 3243 i387_supply_fxsave (regcache, regnum, fxsave);
c4f35dd8 3244
233dfcf0
L		 3245 if (fxsave
3246 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
c4f35dd8 3247 {
9a3c8263 3248 const gdb_byte *regs = (const gdb_byte *) fxsave;
41d041d6 3249
20a6ec49
MD		 3250 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3251 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3252 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3253 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
c4f35dd8 3254 }
0c1a73d6
MK		 3255}
3256
a055a187
L		 3257/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3258
3259void
3260amd64_supply_xsave (struct regcache *regcache, int regnum,
3261 const void *xsave)
3262{
3263 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3264 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3265
3266 i387_supply_xsave (regcache, regnum, xsave);
3267
233dfcf0
L		 3268 if (xsave
3269 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187 3270 {
9a3c8263 3271 const gdb_byte *regs = (const gdb_byte *) xsave;
a055a187
L		 3272
3273 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3274 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep),
3275 regs + 12);
3276 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3277 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep),
3278 regs + 20);
3279 }
3280}
3281
3c017e40
MK		 3282/* Fill register REGNUM (if it is a floating-point or SSE register) in
3283 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3284 all registers. This function doesn't touch any of the reserved
3285 bits in *FXSAVE. */
3286
3287void
3288amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3289 void *fxsave)
3290{
20a6ec49
MD		 3291 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3292 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3293 gdb_byte *regs = (gdb_byte *) fxsave;
3c017e40
MK		 3294
3295 i387_collect_fxsave (regcache, regnum, fxsave);
3296
233dfcf0 3297 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
f0ef85a5 3298 {
20a6ec49
MD		 3299 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3300 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12);
3301 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3302 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20);
f0ef85a5 3303 }
3c017e40 3304}
a055a187 3305
7a9dd1b2 3306/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
a055a187
L		 3307
3308void
3309amd64_collect_xsave (const struct regcache *regcache, int regnum,
3310 void *xsave, int gcore)
3311{
3312 struct gdbarch *gdbarch = get_regcache_arch (regcache);
3313 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3314 gdb_byte *regs = (gdb_byte *) xsave;
a055a187
L		 3315
3316 i387_collect_xsave (regcache, regnum, xsave, gcore);
3317
233dfcf0 3318 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187
L		 3319 {
3320 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
3321 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep),
3322 regs + 12);
3323 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
3324 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep),
3325 regs + 20);
3326 }
3327}
GDB Binutils - Deliverables
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