gdb: Fix parameter passing to mi_create_breakpoint
[deliverable/binutils-gdb.git] / gdb / amd64-tdep.h
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90f90721 1/* Target-dependent definitions for AMD64.
c4f35dd8 2
61baf725 3 Copyright (C) 2001-2017 Free Software Foundation, Inc.
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4 Contributed by Jiri Smid, SuSE Labs.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
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11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
53e95fcf 20
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21#ifndef AMD64_TDEP_H
22#define AMD64_TDEP_H
53e95fcf 23
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24struct gdbarch;
25struct frame_info;
221c12ff 26struct regcache;
da3331ec 27
53e95fcf 28#include "i386-tdep.h"
53e95fcf 29
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30/* Register numbers of various important registers. */
31
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32enum amd64_regnum
33{
34 AMD64_RAX_REGNUM, /* %rax */
35 AMD64_RBX_REGNUM, /* %rbx */
36 AMD64_RCX_REGNUM, /* %rcx */
37 AMD64_RDX_REGNUM, /* %rdx */
38 AMD64_RSI_REGNUM, /* %rsi */
39 AMD64_RDI_REGNUM, /* %rdi */
40 AMD64_RBP_REGNUM, /* %rbp */
41 AMD64_RSP_REGNUM, /* %rsp */
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42 AMD64_R8_REGNUM, /* %r8 */
43 AMD64_R9_REGNUM, /* %r9 */
44 AMD64_R10_REGNUM, /* %r10 */
45 AMD64_R11_REGNUM, /* %r11 */
46 AMD64_R12_REGNUM, /* %r12 */
47 AMD64_R13_REGNUM, /* %r13 */
48 AMD64_R14_REGNUM, /* %r14 */
49 AMD64_R15_REGNUM, /* %r15 */
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50 AMD64_RIP_REGNUM, /* %rip */
51 AMD64_EFLAGS_REGNUM, /* %eflags */
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52 AMD64_CS_REGNUM, /* %cs */
53 AMD64_SS_REGNUM, /* %ss */
54 AMD64_DS_REGNUM, /* %ds */
55 AMD64_ES_REGNUM, /* %es */
56 AMD64_FS_REGNUM, /* %fs */
57 AMD64_GS_REGNUM, /* %gs */
90f90721 58 AMD64_ST0_REGNUM = 24, /* %st0 */
7f7930dd 59 AMD64_ST1_REGNUM, /* %st1 */
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60 AMD64_FCTRL_REGNUM = AMD64_ST0_REGNUM + 8,
61 AMD64_FSTAT_REGNUM = AMD64_ST0_REGNUM + 9,
7f7930dd 62 AMD64_FTAG_REGNUM = AMD64_ST0_REGNUM + 10,
90f90721 63 AMD64_XMM0_REGNUM = 40, /* %xmm0 */
c6f4c129 64 AMD64_XMM1_REGNUM, /* %xmm1 */
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65 AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16,
66 AMD64_YMM0H_REGNUM, /* %ymm0h */
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67 AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15,
68 AMD64_BND0R_REGNUM = AMD64_YMM15H_REGNUM + 1,
69 AMD64_BND3R_REGNUM = AMD64_BND0R_REGNUM + 3,
70 AMD64_BNDCFGU_REGNUM,
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71 AMD64_BNDSTATUS_REGNUM,
72 AMD64_XMM16_REGNUM,
73 AMD64_XMM31_REGNUM = AMD64_XMM16_REGNUM + 15,
74 AMD64_YMM16H_REGNUM,
75 AMD64_YMM31H_REGNUM = AMD64_YMM16H_REGNUM + 15,
76 AMD64_K0_REGNUM,
77 AMD64_K7_REGNUM = AMD64_K0_REGNUM + 7,
78 AMD64_ZMM0H_REGNUM,
2735833d 79 AMD64_ZMM31H_REGNUM = AMD64_ZMM0H_REGNUM + 31,
51547df6 80 AMD64_PKRU_REGNUM,
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81 AMD64_FSBASE_REGNUM,
82 AMD64_GSBASE_REGNUM
90f90721 83};
402ecd56 84
c4f35dd8 85/* Number of general purpose registers. */
90f90721 86#define AMD64_NUM_GREGS 24
c4f35dd8 87
2735833d 88#define AMD64_NUM_REGS (AMD64_GSBASE_REGNUM + 1)
a055a187 89
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90extern struct target_desc *tdesc_amd64;
91
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92extern struct displaced_step_closure *amd64_displaced_step_copy_insn
93 (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
94 struct regcache *regs);
95extern void amd64_displaced_step_fixup (struct gdbarch *gdbarch,
96 struct displaced_step_closure *closure,
97 CORE_ADDR from, CORE_ADDR to,
98 struct regcache *regs);
99
90f90721 100extern void amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch);
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101extern void amd64_x32_init_abi (struct gdbarch_info info,
102 struct gdbarch *gdbarch);
97de3545 103extern const struct target_desc *amd64_target_description (uint64_t xcr0);
53e95fcf 104
41d041d6 105/* Fill register REGNUM in REGCACHE with the appropriate
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106 floating-point or SSE register value from *FXSAVE. If REGNUM is
107 -1, do this for all registers. This function masks off any of the
108 reserved bits in *FXSAVE. */
b64bbf8c 109
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110extern void amd64_supply_fxsave (struct regcache *regcache, int regnum,
111 const void *fxsave);
baed091b 112
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113/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
114extern void amd64_supply_xsave (struct regcache *regcache, int regnum,
115 const void *xsave);
116
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117/* Fill register REGNUM (if it is a floating-point or SSE register) in
118 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
119 all registers. This function doesn't touch any of the reserved
120 bits in *FXSAVE. */
121
122extern void amd64_collect_fxsave (const struct regcache *regcache, int regnum,
123 void *fxsave);
7a9dd1b2 124/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
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125extern void amd64_collect_xsave (const struct regcache *regcache,
126 int regnum, void *xsave, int gcore);
b246147c 127\f
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128/* Floating-point register set. */
129extern const struct regset amd64_fpregset;
b246147c 130
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131/* Variables exported from amd64-linux-tdep.c. */
132extern int amd64_linux_gregset_reg_offset[];
133
03b62bbb 134/* Variables exported from amd64-nbsd-tdep.c. */
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135extern int amd64nbsd_r_reg_offset[];
136
03b62bbb 137/* Variables exported from amd64-obsd-tdep.c. */
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138extern int amd64obsd_r_reg_offset[];
139
03b62bbb 140/* Variables exported from amd64-fbsd-tdep.c. */
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141extern CORE_ADDR amd64fbsd_sigtramp_start_addr;
142extern CORE_ADDR amd64fbsd_sigtramp_end_addr;
b246147c 143extern int amd64fbsd_sc_reg_offset[];
53e95fcf 144
9c1488cb 145#endif /* amd64-tdep.h */
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