Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
1e698235 | 3 | 2001, 2002, 2003 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
29 | #include "symfile.h" | |
30 | #include "gdb_string.h" | |
e8b09175 | 31 | #include "dis-asm.h" /* For register flavors. */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
34e8f22d | 35 | #include "arch-utils.h" |
a42dd537 | 36 | #include "solib-svr4.h" |
4be87837 | 37 | #include "osabi.h" |
34e8f22d RE |
38 | |
39 | #include "arm-tdep.h" | |
26216b98 | 40 | #include "gdb/sim-arm.h" |
34e8f22d | 41 | |
082fc60d RE |
42 | #include "elf-bfd.h" |
43 | #include "coff/internal.h" | |
97e03143 | 44 | #include "elf/arm.h" |
c906108c | 45 | |
26216b98 AC |
46 | #include "gdb_assert.h" |
47 | ||
6529d2dd AC |
48 | static int arm_debug; |
49 | ||
2a451106 KB |
50 | /* Each OS has a different mechanism for accessing the various |
51 | registers stored in the sigcontext structure. | |
52 | ||
53 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
54 | function pointer) which may be used to determine the addresses | |
55 | of the various saved registers in the sigcontext structure. | |
56 | ||
57 | For the ARM target, there are three parameters to this function. | |
58 | The first is the pc value of the frame under consideration, the | |
59 | second the stack pointer of this frame, and the last is the | |
60 | register number to fetch. | |
61 | ||
62 | If the tm.h file does not define this macro, then it's assumed that | |
63 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
64 | be 0. | |
65 | ||
66 | When it comes time to multi-arching this code, see the identically | |
67 | named machinery in ia64-tdep.c for an example of how it could be | |
68 | done. It should not be necessary to modify the code below where | |
69 | this macro is used. */ | |
70 | ||
3bb04bdd AC |
71 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
72 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
73 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
74 | #endif | |
75 | #else | |
76 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
77 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
78 | #endif |
79 | ||
082fc60d RE |
80 | /* Macros for setting and testing a bit in a minimal symbol that marks |
81 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
82 | is used for this purpose. This field is already being used to store | |
83 | the symbol size, so the assumption is that the symbol size cannot | |
84 | exceed 2^31. | |
85 | ||
86 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
87 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
88 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
89 | i.e. the "info" field with the "special" bit | |
90 | masked out. */ | |
91 | ||
92 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
93 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
94 | | 0x80000000) | |
95 | ||
96 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
97 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
98 | ||
99 | #define MSYMBOL_SIZE(msym) \ | |
100 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
ed9a39eb | 101 | |
94c30b78 | 102 | /* Number of different reg name sets (options). */ |
bc90b915 FN |
103 | static int num_flavor_options; |
104 | ||
105 | /* We have more registers than the disassembler as gdb can print the value | |
106 | of special registers as well. | |
107 | The general register names are overwritten by whatever is being used by | |
94c30b78 | 108 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
bc90b915 | 109 | |
94c30b78 | 110 | /* Initial value: Register names used in ARM's ISA documentation. */ |
bc90b915 | 111 | static char * arm_register_name_strings[] = |
da59e081 JM |
112 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
113 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
114 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
115 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
116 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
117 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 118 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 119 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 120 | |
bc90b915 | 121 | /* Valid register name flavors. */ |
53904c9e | 122 | static const char **valid_flavors; |
ed9a39eb | 123 | |
94c30b78 | 124 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 125 | static const char *disassembly_flavor; |
94c30b78 | 126 | /* Index to that option in the opcodes table. */ |
da3c6d4a | 127 | static int current_option; |
96baa820 | 128 | |
ed9a39eb JM |
129 | /* This is used to keep the bfd arch_info in sync with the disassembly |
130 | flavor. */ | |
131 | static void set_disassembly_flavor_sfunc(char *, int, | |
132 | struct cmd_list_element *); | |
133 | static void set_disassembly_flavor (void); | |
134 | ||
b508a996 RE |
135 | static void convert_from_extended (const struct floatformat *, const void *, |
136 | void *); | |
137 | static void convert_to_extended (const struct floatformat *, void *, | |
138 | const void *); | |
ed9a39eb JM |
139 | |
140 | /* Define other aspects of the stack frame. We keep the offsets of | |
141 | all saved registers, 'cause we need 'em a lot! We also keep the | |
142 | current size of the stack frame, and the offset of the frame | |
143 | pointer from the stack pointer (for frameless functions, and when | |
94c30b78 | 144 | we're still in the prologue of a function with a frame). */ |
ed9a39eb JM |
145 | |
146 | struct frame_extra_info | |
c3b4394c RE |
147 | { |
148 | int framesize; | |
149 | int frameoffset; | |
150 | int framereg; | |
151 | }; | |
ed9a39eb | 152 | |
bc90b915 FN |
153 | /* Addresses for calling Thumb functions have the bit 0 set. |
154 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
155 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
156 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
157 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
158 | ||
39bbf761 | 159 | static int |
ed9a39eb | 160 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 161 | { |
8bedc050 | 162 | return (DEPRECATED_FRAME_SAVED_PC (thisframe) >= LOWEST_PC); |
c906108c SS |
163 | } |
164 | ||
94c30b78 | 165 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
166 | |
167 | int arm_apcs_32 = 1; | |
168 | ||
ed9a39eb JM |
169 | /* Flag set by arm_fix_call_dummy that tells whether the target |
170 | function is a Thumb function. This flag is checked by | |
171 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
172 | its use in valops.c) to pass the function address as an additional | |
173 | parameter. */ | |
c906108c SS |
174 | |
175 | static int target_is_thumb; | |
176 | ||
ed9a39eb JM |
177 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
178 | function is a Thumb function. This flag is checked by | |
179 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
180 | |
181 | static int caller_is_thumb; | |
182 | ||
ed9a39eb JM |
183 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
184 | function. */ | |
c906108c | 185 | |
34e8f22d | 186 | int |
2a451106 | 187 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 188 | { |
c5aa993b | 189 | struct minimal_symbol *sym; |
c906108c | 190 | |
ed9a39eb | 191 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
192 | if (IS_THUMB_ADDR (memaddr)) |
193 | return 1; | |
194 | ||
ed9a39eb | 195 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
196 | sym = lookup_minimal_symbol_by_pc (memaddr); |
197 | if (sym) | |
198 | { | |
c5aa993b | 199 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
200 | } |
201 | else | |
ed9a39eb JM |
202 | { |
203 | return 0; | |
204 | } | |
c906108c SS |
205 | } |
206 | ||
ed9a39eb JM |
207 | /* Determine if the program counter specified in MEMADDR is in a call |
208 | dummy being called from a Thumb function. */ | |
c906108c | 209 | |
34e8f22d | 210 | int |
2a451106 | 211 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 212 | { |
c5aa993b | 213 | CORE_ADDR sp = read_sp (); |
c906108c | 214 | |
dfcd3bfb JM |
215 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
216 | is the best we can do. We are trying to determine if the pc is on | |
217 | the stack, which (hopefully) will only happen in a call dummy. | |
218 | We hope the current stack pointer is not so far alway from the dummy | |
219 | frame location (true if we have not pushed large data structures or | |
220 | gone too many levels deep) and that our 1024 is not enough to consider | |
94c30b78 | 221 | code regions as part of the stack (true for most practical purposes). */ |
ae45cd16 | 222 | if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
c906108c SS |
223 | return caller_is_thumb; |
224 | else | |
225 | return 0; | |
226 | } | |
227 | ||
181c1381 | 228 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 229 | static CORE_ADDR |
ed9a39eb | 230 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 231 | { |
a3a2ee65 JT |
232 | if (arm_apcs_32) |
233 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); | |
c906108c | 234 | else |
a3a2ee65 | 235 | return (val & 0x03fffffc); |
c906108c SS |
236 | } |
237 | ||
181c1381 RE |
238 | /* When reading symbols, we need to zap the low bit of the address, |
239 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 240 | static CORE_ADDR |
181c1381 RE |
241 | arm_smash_text_address (CORE_ADDR val) |
242 | { | |
243 | return val & ~1; | |
244 | } | |
245 | ||
34e8f22d RE |
246 | /* Immediately after a function call, return the saved pc. Can't |
247 | always go through the frames for this because on some machines the | |
248 | new frame is not set up until the new function executes some | |
249 | instructions. */ | |
250 | ||
251 | static CORE_ADDR | |
ed9a39eb | 252 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c | 253 | { |
34e8f22d | 254 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
c906108c SS |
255 | } |
256 | ||
0defa245 RE |
257 | /* Determine whether the function invocation represented by FI has a |
258 | frame on the stack associated with it. If it does return zero, | |
259 | otherwise return 1. */ | |
260 | ||
148754e5 | 261 | static int |
ed9a39eb | 262 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 263 | { |
392a587b | 264 | CORE_ADDR func_start, after_prologue; |
96baa820 | 265 | int frameless; |
ed9a39eb | 266 | |
0defa245 RE |
267 | /* Sometimes we have functions that do a little setup (like saving the |
268 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
269 | The symbol table will report this as a prologue. However, it is | |
270 | important not to try to parse these partial frames as frames, or we | |
271 | will get really confused. | |
272 | ||
273 | So I will demand 3 instructions between the start & end of the | |
274 | prologue before I call it a real prologue, i.e. at least | |
275 | mov ip, sp, | |
276 | stmdb sp!, {} | |
277 | sub sp, ip, #4. */ | |
278 | ||
50abf9e5 | 279 | func_start = (get_pc_function_start (get_frame_pc (fi)) + FUNCTION_START_OFFSET); |
7be570e7 | 280 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 281 | |
96baa820 | 282 | /* There are some frameless functions whose first two instructions |
ed9a39eb | 283 | follow the standard APCS form, in which case after_prologue will |
94c30b78 | 284 | be func_start + 8. */ |
ed9a39eb | 285 | |
96baa820 | 286 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
287 | return frameless; |
288 | } | |
289 | ||
0defa245 | 290 | /* The address of the arguments in the frame. */ |
148754e5 | 291 | static CORE_ADDR |
0defa245 RE |
292 | arm_frame_args_address (struct frame_info *fi) |
293 | { | |
1e2330ba | 294 | return get_frame_base (fi); |
0defa245 RE |
295 | } |
296 | ||
297 | /* The address of the local variables in the frame. */ | |
148754e5 | 298 | static CORE_ADDR |
0defa245 RE |
299 | arm_frame_locals_address (struct frame_info *fi) |
300 | { | |
1e2330ba | 301 | return get_frame_base (fi); |
0defa245 RE |
302 | } |
303 | ||
304 | /* The number of arguments being passed in the frame. */ | |
148754e5 | 305 | static int |
0defa245 RE |
306 | arm_frame_num_args (struct frame_info *fi) |
307 | { | |
308 | /* We have no way of knowing. */ | |
309 | return -1; | |
310 | } | |
311 | ||
c906108c | 312 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
313 | push {r7, lr} |
314 | add sp, sp, #-28 | |
315 | add r7, sp, #12 | |
c906108c | 316 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
317 | mov r7, sp |
318 | ||
319 | or like this: | |
320 | push {r7, lr} | |
321 | mov r7, sp | |
322 | sub sp, #12 | |
323 | ||
324 | or, on tpcs, like this: | |
325 | sub sp,#16 | |
326 | push {r7, lr} | |
327 | (many instructions) | |
328 | mov r7, sp | |
329 | sub sp, #12 | |
330 | ||
331 | There is always one instruction of three classes: | |
332 | 1 - push | |
333 | 2 - setting of r7 | |
334 | 3 - adjusting of sp | |
335 | ||
336 | When we have found at least one of each class we are done with the prolog. | |
337 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 338 | */ |
c906108c SS |
339 | |
340 | static CORE_ADDR | |
c7885828 | 341 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
342 | { |
343 | CORE_ADDR current_pc; | |
da3c6d4a MS |
344 | /* findmask: |
345 | bit 0 - push { rlist } | |
346 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
347 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
348 | */ | |
349 | int findmask = 0; | |
350 | ||
94c30b78 MS |
351 | for (current_pc = pc; |
352 | current_pc + 2 < func_end && current_pc < pc + 40; | |
da3c6d4a | 353 | current_pc += 2) |
c906108c SS |
354 | { |
355 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
356 | ||
94c30b78 | 357 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 358 | { |
94c30b78 | 359 | findmask |= 1; /* push found */ |
da59e081 | 360 | } |
da3c6d4a MS |
361 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
362 | sub sp, #simm */ | |
da59e081 | 363 | { |
94c30b78 | 364 | if ((findmask & 1) == 0) /* before push ? */ |
da59e081 JM |
365 | continue; |
366 | else | |
94c30b78 | 367 | findmask |= 4; /* add/sub sp found */ |
da59e081 JM |
368 | } |
369 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
370 | { | |
94c30b78 | 371 | findmask |= 2; /* setting of r7 found */ |
da59e081 JM |
372 | } |
373 | else if (insn == 0x466f) /* mov r7, sp */ | |
374 | { | |
94c30b78 | 375 | findmask |= 2; /* setting of r7 found */ |
da59e081 | 376 | } |
3d74b771 FF |
377 | else if (findmask == (4+2+1)) |
378 | { | |
da3c6d4a MS |
379 | /* We have found one of each type of prologue instruction */ |
380 | break; | |
3d74b771 | 381 | } |
da59e081 | 382 | else |
94c30b78 | 383 | /* Something in the prolog that we don't care about or some |
da3c6d4a | 384 | instruction from outside the prolog scheduled here for |
94c30b78 | 385 | optimization. */ |
da3c6d4a | 386 | continue; |
c906108c SS |
387 | } |
388 | ||
389 | return current_pc; | |
390 | } | |
391 | ||
da3c6d4a MS |
392 | /* Advance the PC across any function entry prologue instructions to |
393 | reach some "real" code. | |
34e8f22d RE |
394 | |
395 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 396 | prologue: |
c906108c | 397 | |
c5aa993b JM |
398 | mov ip, sp |
399 | [stmfd sp!, {a1,a2,a3,a4}] | |
400 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
401 | [stfe f7, [sp, #-12]!] |
402 | [stfe f6, [sp, #-12]!] | |
403 | [stfe f5, [sp, #-12]!] | |
404 | [stfe f4, [sp, #-12]!] | |
405 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 406 | |
34e8f22d | 407 | static CORE_ADDR |
ed9a39eb | 408 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
409 | { |
410 | unsigned long inst; | |
411 | CORE_ADDR skip_pc; | |
b8d5e71d | 412 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 413 | char *func_name; |
c906108c SS |
414 | struct symtab_and_line sal; |
415 | ||
848cfffb | 416 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
ae45cd16 | 417 | if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0)) |
848cfffb AC |
418 | return pc; |
419 | ||
96baa820 | 420 | /* See what the symbol table says. */ |
ed9a39eb | 421 | |
50f6fb4b | 422 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 423 | { |
50f6fb4b CV |
424 | struct symbol *sym; |
425 | ||
426 | /* Found a function. */ | |
427 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
428 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
429 | { | |
94c30b78 | 430 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
431 | sal = find_pc_line (func_addr, 0); |
432 | if ((sal.line != 0) && (sal.end < func_end)) | |
433 | return sal.end; | |
434 | } | |
c906108c SS |
435 | } |
436 | ||
437 | /* Check if this is Thumb code. */ | |
438 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 439 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
440 | |
441 | /* Can't find the prologue end in the symbol table, try it the hard way | |
94c30b78 | 442 | by disassembling the instructions. */ |
c906108c | 443 | |
b8d5e71d MS |
444 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
445 | if (func_end == 0 || func_end > pc + 64) | |
446 | func_end = pc + 64; | |
c906108c | 447 | |
b8d5e71d | 448 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 449 | { |
f43845b3 | 450 | inst = read_memory_integer (skip_pc, 4); |
f43845b3 | 451 | |
b8d5e71d MS |
452 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
453 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
454 | continue; | |
c906108c | 455 | |
b8d5e71d MS |
456 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
457 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
458 | continue; | |
c906108c | 459 | |
b8d5e71d MS |
460 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
461 | continue; | |
c906108c | 462 | |
b8d5e71d MS |
463 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
464 | continue; | |
11d3b27d | 465 | |
b8d5e71d MS |
466 | /* Any insns after this point may float into the code, if it makes |
467 | for better instruction scheduling, so we skip them only if we | |
468 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 469 | |
b8d5e71d MS |
470 | /* We may have either one sfmfd instruction here, or several stfe |
471 | insns, depending on the version of floating point code we | |
472 | support. */ | |
473 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
474 | continue; | |
475 | ||
476 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
477 | continue; | |
478 | ||
479 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
480 | continue; | |
481 | ||
482 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
483 | continue; | |
484 | ||
485 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
486 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
487 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
488 | continue; | |
489 | ||
490 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
491 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
492 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
493 | continue; | |
494 | ||
495 | /* Un-recognized instruction; stop scanning. */ | |
496 | break; | |
f43845b3 | 497 | } |
c906108c | 498 | |
b8d5e71d | 499 | return skip_pc; /* End of prologue */ |
c906108c | 500 | } |
94c30b78 | 501 | |
c5aa993b | 502 | /* *INDENT-OFF* */ |
c906108c SS |
503 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
504 | This function decodes a Thumb function prologue to determine: | |
505 | 1) the size of the stack frame | |
506 | 2) which registers are saved on it | |
507 | 3) the offsets of saved regs | |
508 | 4) the offset from the stack pointer to the frame pointer | |
509 | This information is stored in the "extra" fields of the frame_info. | |
510 | ||
da59e081 JM |
511 | A typical Thumb function prologue would create this stack frame |
512 | (offsets relative to FP) | |
c906108c SS |
513 | old SP -> 24 stack parameters |
514 | 20 LR | |
515 | 16 R7 | |
516 | R7 -> 0 local variables (16 bytes) | |
517 | SP -> -12 additional stack space (12 bytes) | |
518 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
519 | 12 bytes. The frame register is R7. |
520 | ||
da3c6d4a MS |
521 | The comments for thumb_skip_prolog() describe the algorithm we use |
522 | to detect the end of the prolog. */ | |
c5aa993b JM |
523 | /* *INDENT-ON* */ |
524 | ||
c906108c | 525 | static void |
ed9a39eb | 526 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
527 | { |
528 | CORE_ADDR prologue_start; | |
529 | CORE_ADDR prologue_end; | |
530 | CORE_ADDR current_pc; | |
94c30b78 | 531 | /* Which register has been copied to register n? */ |
da3c6d4a MS |
532 | int saved_reg[16]; |
533 | /* findmask: | |
534 | bit 0 - push { rlist } | |
535 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
536 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
537 | */ | |
538 | int findmask = 0; | |
c5aa993b | 539 | int i; |
c906108c | 540 | |
848cfffb | 541 | /* Don't try to scan dummy frames. */ |
07555a72 | 542 | if (fi != NULL |
50abf9e5 | 543 | && DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb AC |
544 | return; |
545 | ||
50abf9e5 | 546 | if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end)) |
c906108c SS |
547 | { |
548 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
549 | ||
94c30b78 | 550 | if (sal.line == 0) /* no line info, use current PC */ |
50abf9e5 | 551 | prologue_end = get_frame_pc (fi); |
c906108c | 552 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 553 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
554 | } |
555 | else | |
da3c6d4a MS |
556 | /* We're in the boondocks: allow for |
557 | 16 pushes, an add, and "mv fp,sp". */ | |
558 | prologue_end = prologue_start + 40; | |
c906108c | 559 | |
50abf9e5 | 560 | prologue_end = min (prologue_end, get_frame_pc (fi)); |
c906108c SS |
561 | |
562 | /* Initialize the saved register map. When register H is copied to | |
563 | register L, we will put H in saved_reg[L]. */ | |
564 | for (i = 0; i < 16; i++) | |
565 | saved_reg[i] = i; | |
566 | ||
567 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
568 | frame pointer, adjust the stack pointer, and save registers. |
569 | Do this until all basic prolog instructions are found. */ | |
c906108c | 570 | |
da50a4b7 | 571 | get_frame_extra_info (fi)->framesize = 0; |
da59e081 JM |
572 | for (current_pc = prologue_start; |
573 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
574 | current_pc += 2) | |
c906108c SS |
575 | { |
576 | unsigned short insn; | |
577 | int regno; | |
578 | int offset; | |
579 | ||
580 | insn = read_memory_unsigned_integer (current_pc, 2); | |
581 | ||
c5aa993b | 582 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 583 | { |
da59e081 | 584 | int mask; |
94c30b78 | 585 | findmask |= 1; /* push found */ |
c906108c SS |
586 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
587 | whether to save LR (R14). */ | |
da59e081 | 588 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c | 589 | |
b8d5e71d | 590 | /* Calculate offsets of saved R0-R7 and LR. */ |
34e8f22d | 591 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
c906108c | 592 | if (mask & (1 << regno)) |
c5aa993b | 593 | { |
da50a4b7 | 594 | get_frame_extra_info (fi)->framesize += 4; |
b2fb4676 | 595 | get_frame_saved_regs (fi)[saved_reg[regno]] = |
da50a4b7 | 596 | -(get_frame_extra_info (fi)->framesize); |
da3c6d4a MS |
597 | /* Reset saved register map. */ |
598 | saved_reg[regno] = regno; | |
c906108c SS |
599 | } |
600 | } | |
da3c6d4a MS |
601 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
602 | sub sp, #simm */ | |
c906108c | 603 | { |
b8d5e71d | 604 | if ((findmask & 1) == 0) /* before push? */ |
da59e081 JM |
605 | continue; |
606 | else | |
94c30b78 | 607 | findmask |= 4; /* add/sub sp found */ |
da59e081 | 608 | |
94c30b78 MS |
609 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
610 | if (insn & 0x80) /* is it signed? (==subtracting) */ | |
da59e081 | 611 | { |
da50a4b7 | 612 | get_frame_extra_info (fi)->frameoffset += offset; |
da59e081 JM |
613 | offset = -offset; |
614 | } | |
da50a4b7 | 615 | get_frame_extra_info (fi)->framesize -= offset; |
c906108c SS |
616 | } |
617 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
618 | { | |
94c30b78 | 619 | findmask |= 2; /* setting of r7 found */ |
da50a4b7 | 620 | get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM; |
c3b4394c | 621 | /* get scaled offset */ |
da50a4b7 | 622 | get_frame_extra_info (fi)->frameoffset = (insn & 0xff) << 2; |
c906108c | 623 | } |
da59e081 | 624 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 625 | { |
94c30b78 | 626 | findmask |= 2; /* setting of r7 found */ |
da50a4b7 AC |
627 | get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM; |
628 | get_frame_extra_info (fi)->frameoffset = 0; | |
34e8f22d | 629 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
c906108c SS |
630 | } |
631 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
632 | { | |
da3c6d4a | 633 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 634 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
94c30b78 | 635 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
636 | } |
637 | else | |
da3c6d4a MS |
638 | /* Something in the prolog that we don't care about or some |
639 | instruction from outside the prolog scheduled here for | |
640 | optimization. */ | |
641 | continue; | |
c906108c SS |
642 | } |
643 | } | |
644 | ||
ed9a39eb | 645 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
646 | 1) the size of the stack frame |
647 | 2) which registers are saved on it | |
648 | 3) the offsets of saved regs | |
649 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
650 | This information is stored in the "extra" fields of the frame_info. |
651 | ||
96baa820 JM |
652 | There are two basic forms for the ARM prologue. The fixed argument |
653 | function call will look like: | |
ed9a39eb JM |
654 | |
655 | mov ip, sp | |
656 | stmfd sp!, {fp, ip, lr, pc} | |
657 | sub fp, ip, #4 | |
658 | [sub sp, sp, #4] | |
96baa820 | 659 | |
c906108c | 660 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
661 | IP -> 4 (caller's stack) |
662 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
663 | -4 LR (return address in caller) | |
664 | -8 IP (copy of caller's SP) | |
665 | -12 FP (caller's FP) | |
666 | SP -> -28 Local variables | |
667 | ||
c906108c | 668 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
669 | 28 bytes. The stmfd call can also save any of the vN registers it |
670 | plans to use, which increases the frame size accordingly. | |
671 | ||
672 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
673 | because the ARM Store instructions always store PC + 8 when you read | |
674 | the PC register. | |
ed9a39eb | 675 | |
96baa820 JM |
676 | A variable argument function call will look like: |
677 | ||
ed9a39eb JM |
678 | mov ip, sp |
679 | stmfd sp!, {a1, a2, a3, a4} | |
680 | stmfd sp!, {fp, ip, lr, pc} | |
681 | sub fp, ip, #20 | |
682 | ||
96baa820 | 683 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
684 | IP -> 20 (caller's stack) |
685 | 16 A4 | |
686 | 12 A3 | |
687 | 8 A2 | |
688 | 4 A1 | |
689 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
690 | -4 LR (return address in caller) | |
691 | -8 IP (copy of caller's SP) | |
692 | -12 FP (caller's FP) | |
693 | SP -> -28 Local variables | |
96baa820 JM |
694 | |
695 | The frame size would thus be 48 bytes, and the frame offset would be | |
696 | 28 bytes. | |
697 | ||
698 | There is another potential complication, which is that the optimizer | |
699 | will try to separate the store of fp in the "stmfd" instruction from | |
700 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
701 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
702 | ||
703 | Also, note, the original version of the ARM toolchain claimed that there | |
704 | should be an | |
705 | ||
706 | instruction at the end of the prologue. I have never seen GCC produce | |
707 | this, and the ARM docs don't mention it. We still test for it below in | |
708 | case it happens... | |
ed9a39eb JM |
709 | |
710 | */ | |
c906108c SS |
711 | |
712 | static void | |
ed9a39eb | 713 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
714 | { |
715 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 716 | LONGEST return_value; |
c906108c SS |
717 | CORE_ADDR prologue_start, prologue_end, current_pc; |
718 | ||
c906108c | 719 | /* Assume there is no frame until proven otherwise. */ |
da50a4b7 AC |
720 | get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM; |
721 | get_frame_extra_info (fi)->framesize = 0; | |
722 | get_frame_extra_info (fi)->frameoffset = 0; | |
c906108c SS |
723 | |
724 | /* Check for Thumb prologue. */ | |
50abf9e5 | 725 | if (arm_pc_is_thumb (get_frame_pc (fi))) |
c906108c SS |
726 | { |
727 | thumb_scan_prologue (fi); | |
c906108c SS |
728 | return; |
729 | } | |
730 | ||
731 | /* Find the function prologue. If we can't find the function in | |
732 | the symbol table, peek in the stack frame to find the PC. */ | |
50abf9e5 | 733 | if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end)) |
c906108c | 734 | { |
2a451106 KB |
735 | /* One way to find the end of the prologue (which works well |
736 | for unoptimized code) is to do the following: | |
737 | ||
738 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
739 | ||
740 | if (sal.line == 0) | |
50abf9e5 | 741 | prologue_end = get_frame_pc (fi); |
2a451106 KB |
742 | else if (sal.end < prologue_end) |
743 | prologue_end = sal.end; | |
744 | ||
745 | This mechanism is very accurate so long as the optimizer | |
746 | doesn't move any instructions from the function body into the | |
747 | prologue. If this happens, sal.end will be the last | |
748 | instruction in the first hunk of prologue code just before | |
749 | the first instruction that the scheduler has moved from | |
750 | the body to the prologue. | |
751 | ||
752 | In order to make sure that we scan all of the prologue | |
753 | instructions, we use a slightly less accurate mechanism which | |
754 | may scan more than necessary. To help compensate for this | |
755 | lack of accuracy, the prologue scanning loop below contains | |
756 | several clauses which'll cause the loop to terminate early if | |
757 | an implausible prologue instruction is encountered. | |
758 | ||
759 | The expression | |
760 | ||
761 | prologue_start + 64 | |
762 | ||
763 | is a suitable endpoint since it accounts for the largest | |
764 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 765 | the scheduler. */ |
2a451106 KB |
766 | |
767 | if (prologue_end > prologue_start + 64) | |
768 | { | |
94c30b78 | 769 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 770 | } |
c906108c SS |
771 | } |
772 | else | |
773 | { | |
94c30b78 MS |
774 | /* Get address of the stmfd in the prologue of the callee; |
775 | the saved PC is the address of the stmfd + 8. */ | |
1e2330ba | 776 | if (!safe_read_memory_integer (get_frame_base (fi), 4, &return_value)) |
16a0f3e7 EZ |
777 | return; |
778 | else | |
779 | { | |
780 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
94c30b78 | 781 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 782 | } |
c906108c SS |
783 | } |
784 | ||
785 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 786 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 787 | |
96baa820 JM |
788 | Be careful, however, and if it doesn't look like a prologue, |
789 | don't try to scan it. If, for instance, a frameless function | |
790 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 791 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
792 | and other operations that rely on a knowledge of the stack |
793 | traceback. | |
794 | ||
795 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 796 | if we don't see this as the first insn, we will stop. |
c906108c | 797 | |
f43845b3 MS |
798 | [Note: This doesn't seem to be true any longer, so it's now an |
799 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 800 | |
f43845b3 MS |
801 | [Note further: The "mov ip,sp" only seems to be missing in |
802 | frameless functions at optimization level "-O2" or above, | |
803 | in which case it is often (but not always) replaced by | |
b8d5e71d | 804 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 805 | |
f43845b3 MS |
806 | sp_offset = fp_offset = 0; |
807 | ||
94c30b78 MS |
808 | for (current_pc = prologue_start; |
809 | current_pc < prologue_end; | |
f43845b3 | 810 | current_pc += 4) |
96baa820 | 811 | { |
d4473757 KB |
812 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
813 | ||
94c30b78 | 814 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 MS |
815 | { |
816 | continue; | |
817 | } | |
94c30b78 | 818 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 MS |
819 | { |
820 | /* Function is frameless: extra_info defaults OK? */ | |
821 | continue; | |
822 | } | |
823 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
824 | /* stmfd sp!, {..., fp, ip, lr, pc} |
825 | or | |
826 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 827 | { |
d4473757 | 828 | int mask = insn & 0xffff; |
ed9a39eb | 829 | |
94c30b78 | 830 | /* Calculate offsets of saved registers. */ |
34e8f22d | 831 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
832 | if (mask & (1 << regno)) |
833 | { | |
834 | sp_offset -= 4; | |
b2fb4676 | 835 | get_frame_saved_regs (fi)[regno] = sp_offset; |
d4473757 KB |
836 | } |
837 | } | |
b8d5e71d MS |
838 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
839 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
840 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
841 | { | |
842 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
843 | continue; | |
844 | } | |
845 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
846 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
847 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
848 | { |
849 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
850 | continue; | |
851 | } | |
d4473757 KB |
852 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
853 | { | |
94c30b78 MS |
854 | unsigned imm = insn & 0xff; /* immediate value */ |
855 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
856 | imm = (imm >> rot) | (imm << (32 - rot)); |
857 | fp_offset = -imm; | |
da50a4b7 | 858 | get_frame_extra_info (fi)->framereg = ARM_FP_REGNUM; |
d4473757 KB |
859 | } |
860 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
861 | { | |
94c30b78 MS |
862 | unsigned imm = insn & 0xff; /* immediate value */ |
863 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 KB |
864 | imm = (imm >> rot) | (imm << (32 - rot)); |
865 | sp_offset -= imm; | |
866 | } | |
867 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
868 | { | |
869 | sp_offset -= 12; | |
34e8f22d | 870 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
b2fb4676 | 871 | get_frame_saved_regs (fi)[regno] = sp_offset; |
d4473757 KB |
872 | } |
873 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
874 | { | |
875 | int n_saved_fp_regs; | |
876 | unsigned int fp_start_reg, fp_bound_reg; | |
877 | ||
94c30b78 | 878 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 879 | { |
d4473757 KB |
880 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
881 | n_saved_fp_regs = 3; | |
882 | else | |
883 | n_saved_fp_regs = 1; | |
96baa820 | 884 | } |
d4473757 | 885 | else |
96baa820 | 886 | { |
d4473757 KB |
887 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
888 | n_saved_fp_regs = 2; | |
889 | else | |
890 | n_saved_fp_regs = 4; | |
96baa820 | 891 | } |
d4473757 | 892 | |
34e8f22d | 893 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
894 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
895 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
896 | { |
897 | sp_offset -= 12; | |
b2fb4676 | 898 | get_frame_saved_regs (fi)[fp_start_reg++] = sp_offset; |
96baa820 | 899 | } |
c906108c | 900 | } |
d4473757 | 901 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 902 | break; /* Condition not true, exit early */ |
b8d5e71d | 903 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 904 | break; /* Don't scan past a block load */ |
d4473757 KB |
905 | else |
906 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 907 | so we just skip what we don't recognize. */ |
d4473757 | 908 | continue; |
c906108c SS |
909 | } |
910 | ||
94c30b78 MS |
911 | /* The frame size is just the negative of the offset (from the |
912 | original SP) of the last thing thing we pushed on the stack. | |
913 | The frame offset is [new FP] - [new SP]. */ | |
da50a4b7 AC |
914 | get_frame_extra_info (fi)->framesize = -sp_offset; |
915 | if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM) | |
916 | get_frame_extra_info (fi)->frameoffset = fp_offset - sp_offset; | |
d4473757 | 917 | else |
da50a4b7 | 918 | get_frame_extra_info (fi)->frameoffset = 0; |
c906108c SS |
919 | } |
920 | ||
ed9a39eb JM |
921 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
922 | One thing we might want to do here is to check REGNUM against the | |
923 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
924 | the stack somewhere. This would provide a graceful failure mode | |
925 | when trying to get the value of caller-saves registers for an inner | |
926 | frame. */ | |
c906108c SS |
927 | |
928 | static CORE_ADDR | |
ed9a39eb | 929 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 930 | { |
848cfffb AC |
931 | /* NOTE: cagney/2002-05-03: This function really shouldn't be |
932 | needed. Instead the (still being written) register unwind | |
933 | function could be called directly. */ | |
11c02a10 | 934 | for (; fi; fi = get_next_frame (fi)) |
848cfffb | 935 | { |
50abf9e5 | 936 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb | 937 | { |
1e2330ba AC |
938 | return deprecated_read_register_dummy (get_frame_pc (fi), |
939 | get_frame_base (fi), regnum); | |
848cfffb | 940 | } |
b2fb4676 | 941 | else if (get_frame_saved_regs (fi)[regnum] != 0) |
848cfffb AC |
942 | { |
943 | /* NOTE: cagney/2002-05-03: This would normally need to | |
944 | handle ARM_SP_REGNUM as a special case as, according to | |
945 | the frame.h comments, saved_regs[SP_REGNUM] contains the | |
946 | SP value not its address. It appears that the ARM isn't | |
947 | doing this though. */ | |
b2fb4676 | 948 | return read_memory_integer (get_frame_saved_regs (fi)[regnum], |
848cfffb AC |
949 | REGISTER_RAW_SIZE (regnum)); |
950 | } | |
951 | } | |
c906108c SS |
952 | return read_register (regnum); |
953 | } | |
148754e5 RE |
954 | /* Function: frame_chain Given a GDB frame, determine the address of |
955 | the calling function's frame. This will be used to create a new | |
e9582e71 | 956 | GDB frame struct, and then DEPRECATED_INIT_EXTRA_FRAME_INFO and |
a5afb99f AC |
957 | DEPRECATED_INIT_FRAME_PC will be called for the new frame. For |
958 | ARM, we save the frame size when we initialize the frame_info. */ | |
c5aa993b | 959 | |
148754e5 | 960 | static CORE_ADDR |
ed9a39eb | 961 | arm_frame_chain (struct frame_info *fi) |
c906108c | 962 | { |
848cfffb | 963 | CORE_ADDR caller_pc; |
da50a4b7 | 964 | int framereg = get_frame_extra_info (fi)->framereg; |
c906108c | 965 | |
50abf9e5 | 966 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
848cfffb | 967 | /* A generic call dummy's frame is the same as caller's. */ |
1e2330ba | 968 | return get_frame_base (fi); |
848cfffb | 969 | |
50abf9e5 | 970 | if (get_frame_pc (fi) < LOWEST_PC) |
c906108c SS |
971 | return 0; |
972 | ||
973 | /* If the caller is the startup code, we're at the end of the chain. */ | |
8bedc050 | 974 | caller_pc = DEPRECATED_FRAME_SAVED_PC (fi); |
c906108c SS |
975 | |
976 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
977 | the frame register of the caller is different from ours. | |
978 | So we must scan the prologue of the caller to determine its | |
94c30b78 | 979 | frame register number. */ |
c3b4394c RE |
980 | /* XXX Fixme, we should try to do this without creating a temporary |
981 | caller_fi. */ | |
50abf9e5 | 982 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (get_frame_pc (fi))) |
c906108c | 983 | { |
f6c609c4 AC |
984 | struct cleanup *old_chain = make_cleanup (null_cleanup, NULL); |
985 | struct frame_info *caller_fi = | |
986 | deprecated_frame_xmalloc_with_cleanup (SIZEOF_FRAME_SAVED_REGS, | |
987 | sizeof (struct frame_extra_info)); | |
c3b4394c RE |
988 | |
989 | /* Now, scan the prologue and obtain the frame register. */ | |
f6c609c4 AC |
990 | deprecated_update_frame_pc_hack (caller_fi, caller_pc); |
991 | arm_scan_prologue (caller_fi); | |
da50a4b7 | 992 | framereg = get_frame_extra_info (caller_fi)->framereg; |
c3b4394c RE |
993 | |
994 | /* Deallocate the storage associated with the temporary frame | |
995 | created above. */ | |
996 | do_cleanups (old_chain); | |
c906108c SS |
997 | } |
998 | ||
999 | /* If the caller used a frame register, return its value. | |
1000 | Otherwise, return the caller's stack pointer. */ | |
34e8f22d | 1001 | if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM) |
c906108c SS |
1002 | return arm_find_callers_reg (fi, framereg); |
1003 | else | |
da50a4b7 | 1004 | return get_frame_base (fi) + get_frame_extra_info (fi)->framesize; |
c906108c SS |
1005 | } |
1006 | ||
ed9a39eb JM |
1007 | /* This function actually figures out the frame address for a given pc |
1008 | and sp. This is tricky because we sometimes don't use an explicit | |
1009 | frame pointer, and the previous stack pointer isn't necessarily | |
1010 | recorded on the stack. The only reliable way to get this info is | |
1011 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1012 | this is the next frame up the chain AFTER a frameless function. If | |
1013 | this is true, then the frame value for this frame is still in the | |
1014 | fp register. */ | |
c906108c | 1015 | |
148754e5 | 1016 | static void |
ed9a39eb | 1017 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1018 | { |
1019 | int reg; | |
f079148d | 1020 | CORE_ADDR sp; |
c906108c | 1021 | |
b2fb4676 | 1022 | if (get_frame_saved_regs (fi) == NULL) |
c3b4394c RE |
1023 | frame_saved_regs_zalloc (fi); |
1024 | ||
a00a19e9 | 1025 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
c3b4394c | 1026 | |
da50a4b7 AC |
1027 | get_frame_extra_info (fi)->framesize = 0; |
1028 | get_frame_extra_info (fi)->frameoffset = 0; | |
1029 | get_frame_extra_info (fi)->framereg = 0; | |
c3b4394c | 1030 | |
11c02a10 | 1031 | if (get_next_frame (fi)) |
8bedc050 | 1032 | deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); |
c906108c | 1033 | |
b2fb4676 | 1034 | memset (get_frame_saved_regs (fi), '\000', sizeof get_frame_saved_regs (fi)); |
c906108c | 1035 | |
da3c6d4a MS |
1036 | /* Compute stack pointer for this frame. We use this value for both |
1037 | the sigtramp and call dummy cases. */ | |
11c02a10 | 1038 | if (!get_next_frame (fi)) |
f079148d | 1039 | sp = read_sp(); |
11c02a10 | 1040 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
848cfffb AC |
1041 | /* For generic dummy frames, pull the value direct from the frame. |
1042 | Having an unwind function to do this would be nice. */ | |
11c02a10 AC |
1043 | sp = deprecated_read_register_dummy (get_frame_pc (get_next_frame (fi)), |
1044 | get_frame_base (get_next_frame (fi)), | |
135c175f | 1045 | ARM_SP_REGNUM); |
f079148d | 1046 | else |
da50a4b7 AC |
1047 | sp = (get_frame_base (get_next_frame (fi)) |
1048 | - get_frame_extra_info (get_next_frame (fi))->frameoffset | |
1049 | + get_frame_extra_info (get_next_frame (fi))->framesize); | |
f079148d | 1050 | |
d7bd68ca | 1051 | /* Determine whether or not we're in a sigtramp frame. |
5a203e44 AC |
1052 | Unfortunately, it isn't sufficient to test (get_frame_type (fi) |
1053 | == SIGTRAMP_FRAME) because this value is sometimes set after | |
e9582e71 | 1054 | invoking DEPRECATED_INIT_EXTRA_FRAME_INFO. So we test *both* |
5a203e44 AC |
1055 | (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to |
1056 | determine if we need to use the sigcontext addresses for the | |
1057 | saved registers. | |
2a451106 | 1058 | |
d7bd68ca AC |
1059 | Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare |
1060 | against the name of the function, the code below will have to be | |
1061 | changed to first fetch the name of the function and then pass | |
1062 | this name to PC_IN_SIGTRAMP. */ | |
2a451106 | 1063 | |
5a203e44 AC |
1064 | /* FIXME: cagney/2002-11-18: This problem will go away once |
1065 | frame.c:get_prev_frame() is modified to set the frame's type | |
1066 | before calling functions like this. */ | |
1067 | ||
3bb04bdd | 1068 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
50abf9e5 | 1069 | && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (get_frame_pc (fi), (char *)0))) |
2a451106 | 1070 | { |
2a451106 | 1071 | for (reg = 0; reg < NUM_REGS; reg++) |
b2fb4676 | 1072 | get_frame_saved_regs (fi)[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, get_frame_pc (fi), reg); |
2a451106 | 1073 | |
94c30b78 | 1074 | /* FIXME: What about thumb mode? */ |
da50a4b7 AC |
1075 | get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM; |
1076 | deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (fi)[get_frame_extra_info (fi)->framereg], REGISTER_RAW_SIZE (get_frame_extra_info (fi)->framereg))); | |
1077 | get_frame_extra_info (fi)->framesize = 0; | |
1078 | get_frame_extra_info (fi)->frameoffset = 0; | |
2a451106 KB |
1079 | |
1080 | } | |
1081 | else | |
c906108c SS |
1082 | { |
1083 | arm_scan_prologue (fi); | |
1084 | ||
11c02a10 | 1085 | if (!get_next_frame (fi)) |
94c30b78 | 1086 | /* This is the innermost frame? */ |
da50a4b7 | 1087 | deprecated_update_frame_base_hack (fi, read_register (get_frame_extra_info (fi)->framereg)); |
11c02a10 | 1088 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
848cfffb AC |
1089 | /* Next inner most frame is a dummy, just grab its frame. |
1090 | Dummy frames always have the same FP as their caller. */ | |
11c02a10 | 1091 | deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi))); |
da50a4b7 AC |
1092 | else if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM |
1093 | || get_frame_extra_info (fi)->framereg == THUMB_FP_REGNUM) | |
ed9a39eb JM |
1094 | { |
1095 | /* not the innermost frame */ | |
94c30b78 | 1096 | /* If we have an FP, the callee saved it. */ |
da50a4b7 AC |
1097 | if (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg] != 0) |
1098 | deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg], 4)); | |
ed9a39eb JM |
1099 | else if (fromleaf) |
1100 | /* If we were called by a frameless fn. then our frame is | |
94c30b78 | 1101 | still in the frame pointer register on the board... */ |
b0c6b05c | 1102 | deprecated_update_frame_base_hack (fi, read_fp ()); |
ed9a39eb | 1103 | } |
c906108c | 1104 | |
ed9a39eb JM |
1105 | /* Calculate actual addresses of saved registers using offsets |
1106 | determined by arm_scan_prologue. */ | |
c906108c | 1107 | for (reg = 0; reg < NUM_REGS; reg++) |
b2fb4676 | 1108 | if (get_frame_saved_regs (fi)[reg] != 0) |
da50a4b7 AC |
1109 | get_frame_saved_regs (fi)[reg] |
1110 | += (get_frame_base (fi) | |
1111 | + get_frame_extra_info (fi)->framesize | |
1112 | - get_frame_extra_info (fi)->frameoffset); | |
c906108c SS |
1113 | } |
1114 | } | |
1115 | ||
1116 | ||
34e8f22d | 1117 | /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM |
ed9a39eb JM |
1118 | is saved in the stack anywhere, otherwise we get it from the |
1119 | registers. | |
c906108c SS |
1120 | |
1121 | The old definition of this function was a macro: | |
c5aa993b | 1122 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1123 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c | 1124 | |
148754e5 | 1125 | static CORE_ADDR |
ed9a39eb | 1126 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1127 | { |
848cfffb | 1128 | /* If a dummy frame, pull the PC out of the frame's register buffer. */ |
50abf9e5 | 1129 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0)) |
1e2330ba AC |
1130 | return deprecated_read_register_dummy (get_frame_pc (fi), |
1131 | get_frame_base (fi), ARM_PC_REGNUM); | |
848cfffb | 1132 | |
1e2330ba AC |
1133 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), |
1134 | (get_frame_base (fi) | |
da50a4b7 | 1135 | - get_frame_extra_info (fi)->frameoffset), |
1e2330ba | 1136 | get_frame_base (fi))) |
f079148d | 1137 | { |
b2fb4676 | 1138 | return read_memory_integer (get_frame_saved_regs (fi)[ARM_PC_REGNUM], |
34e8f22d | 1139 | REGISTER_RAW_SIZE (ARM_PC_REGNUM)); |
f079148d KB |
1140 | } |
1141 | else | |
c906108c | 1142 | { |
34e8f22d | 1143 | CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM); |
c906108c SS |
1144 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
1145 | } | |
1146 | } | |
1147 | ||
c906108c SS |
1148 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1149 | Examine the Program Status Register to decide which state we're in. */ | |
1150 | ||
148754e5 RE |
1151 | static CORE_ADDR |
1152 | arm_read_fp (void) | |
c906108c | 1153 | { |
34e8f22d | 1154 | if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
c906108c SS |
1155 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
1156 | else | |
34e8f22d | 1157 | return read_register (ARM_FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1158 | } |
1159 | ||
148754e5 RE |
1160 | /* Store into a struct frame_saved_regs the addresses of the saved |
1161 | registers of frame described by FRAME_INFO. This includes special | |
1162 | registers such as PC and FP saved in special ways in the stack | |
1163 | frame. SP is even more special: the address we return for it IS | |
1164 | the sp for the next frame. */ | |
c906108c | 1165 | |
148754e5 | 1166 | static void |
c3b4394c | 1167 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1168 | { |
c3b4394c | 1169 | |
b2fb4676 | 1170 | if (get_frame_saved_regs (fip)) |
c3b4394c RE |
1171 | return; |
1172 | ||
1173 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1174 | } |
1175 | ||
848cfffb AC |
1176 | /* Set the return address for a generic dummy frame. ARM uses the |
1177 | entry point. */ | |
1178 | ||
1179 | static CORE_ADDR | |
1180 | arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1181 | { | |
1182 | write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ()); | |
1183 | return sp; | |
1184 | } | |
1185 | ||
148754e5 RE |
1186 | /* Push an empty stack frame, to record the current PC, etc. */ |
1187 | ||
1188 | static void | |
ed9a39eb | 1189 | arm_push_dummy_frame (void) |
c906108c | 1190 | { |
34e8f22d | 1191 | CORE_ADDR old_sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1192 | CORE_ADDR sp = old_sp; |
1193 | CORE_ADDR fp, prologue_start; | |
1194 | int regnum; | |
1195 | ||
1196 | /* Push the two dummy prologue instructions in reverse order, | |
1197 | so that they'll be in the correct low-to-high order in memory. */ | |
1198 | /* sub fp, ip, #4 */ | |
1199 | sp = push_word (sp, 0xe24cb004); | |
1200 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1201 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1202 | ||
ed9a39eb JM |
1203 | /* Push a pointer to the dummy prologue + 12, because when stm |
1204 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1205 | instruction itself plus 12. */ |
1206 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1207 | |
f079148d | 1208 | /* Push the processor status. */ |
34e8f22d | 1209 | sp = push_word (sp, read_register (ARM_PS_REGNUM)); |
f079148d KB |
1210 | |
1211 | /* Push all 16 registers starting with r15. */ | |
34e8f22d | 1212 | for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--) |
c906108c | 1213 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1214 | |
f079148d | 1215 | /* Update fp (for both Thumb and ARM) and sp. */ |
34e8f22d | 1216 | write_register (ARM_FP_REGNUM, fp); |
c906108c | 1217 | write_register (THUMB_FP_REGNUM, fp); |
34e8f22d | 1218 | write_register (ARM_SP_REGNUM, sp); |
c906108c SS |
1219 | } |
1220 | ||
6eb69eab RE |
1221 | /* CALL_DUMMY_WORDS: |
1222 | This sequence of words is the instructions | |
1223 | ||
1224 | mov lr,pc | |
1225 | mov pc,r4 | |
1226 | illegal | |
1227 | ||
1228 | Note this is 12 bytes. */ | |
1229 | ||
34e8f22d | 1230 | static LONGEST arm_call_dummy_words[] = |
6eb69eab RE |
1231 | { |
1232 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1233 | }; | |
1234 | ||
3fb4b924 RE |
1235 | /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy |
1236 | breakpoint to the proper address in the call dummy, so that | |
1237 | `finish' after a stop in a call dummy works. | |
1238 | ||
d7b486e7 RE |
1239 | FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an |
1240 | optimal solution, but the call to arm_fix_call_dummy is immediately | |
1241 | followed by a call to run_stack_dummy, which is the only function | |
1242 | where call_dummy_breakpoint_offset is actually used. */ | |
3fb4b924 RE |
1243 | |
1244 | ||
1245 | static void | |
1246 | arm_set_call_dummy_breakpoint_offset (void) | |
1247 | { | |
1248 | if (caller_is_thumb) | |
1249 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4); | |
1250 | else | |
1251 | set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8); | |
1252 | } | |
1253 | ||
c906108c | 1254 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1255 | in Thumb or ARM mode, and whether the target function is Thumb or |
1256 | ARM. There are three different situations requiring three | |
c906108c SS |
1257 | different dummies: |
1258 | ||
1259 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1260 | been copied into the dummy parameter to this function. |
c906108c | 1261 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1262 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1263 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1264 | works for calling both ARM and Thumb functions. |
c906108c | 1265 | |
ed9a39eb JM |
1266 | All three call dummies expect to receive the target function |
1267 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c | 1268 | |
34e8f22d | 1269 | static void |
ed9a39eb | 1270 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1271 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1272 | { |
1273 | static short thumb_dummy[4] = | |
1274 | { | |
c5aa993b JM |
1275 | 0xf000, 0xf801, /* bl label */ |
1276 | 0xdf18, /* swi 24 */ | |
1277 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1278 | }; |
1279 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1280 | ||
94c30b78 | 1281 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
c5aa993b | 1282 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
3fb4b924 | 1283 | arm_set_call_dummy_breakpoint_offset (); |
c906108c | 1284 | |
ed9a39eb JM |
1285 | /* If the target function is Thumb, set the low bit of the function |
1286 | address. And if the CPU is currently in ARM mode, patch the | |
1287 | second instruction of call dummy to use a BX instruction to | |
1288 | switch to Thumb mode. */ | |
c906108c SS |
1289 | target_is_thumb = arm_pc_is_thumb (fun); |
1290 | if (target_is_thumb) | |
1291 | { | |
1292 | fun |= 1; | |
1293 | if (!caller_is_thumb) | |
1294 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1295 | } | |
1296 | ||
1297 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1298 | instead of the ARM one that's already been copied. This will | |
1299 | work for both Thumb and ARM target functions. */ | |
1300 | if (caller_is_thumb) | |
1301 | { | |
1302 | int i; | |
1303 | char *p = dummy; | |
1304 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1305 | ||
1306 | for (i = 0; i < len; i++) | |
1307 | { | |
1308 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1309 | p += sizeof (thumb_dummy[0]); | |
1310 | } | |
1311 | } | |
1312 | ||
ed9a39eb | 1313 | /* Put the target address in r4; the call dummy will copy this to |
94c30b78 | 1314 | the PC. */ |
c906108c SS |
1315 | write_register (4, fun); |
1316 | } | |
1317 | ||
ed9a39eb JM |
1318 | /* Note: ScottB |
1319 | ||
1320 | This function does not support passing parameters using the FPA | |
1321 | variant of the APCS. It passes any floating point arguments in the | |
1322 | general registers and/or on the stack. */ | |
c906108c | 1323 | |
39bbf761 | 1324 | static CORE_ADDR |
ea7c478f | 1325 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1326 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1327 | { |
6529d2dd AC |
1328 | CORE_ADDR fp; |
1329 | int argnum; | |
1330 | int argreg; | |
1331 | int nstack; | |
1332 | int simd_argreg; | |
1333 | int second_pass; | |
1334 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
ed9a39eb JM |
1335 | |
1336 | /* Walk through the list of args and determine how large a temporary | |
1337 | stack is required. Need to take care here as structs may be | |
6529d2dd AC |
1338 | passed on the stack, and we have to to push them. On the second |
1339 | pass, do the store. */ | |
1340 | nstack = 0; | |
1341 | fp = sp; | |
1342 | for (second_pass = 0; second_pass < 2; second_pass++) | |
c906108c | 1343 | { |
6529d2dd AC |
1344 | /* Compute the FP using the information computed during the |
1345 | first pass. */ | |
1346 | if (second_pass) | |
1347 | fp = sp - nstack; | |
1348 | ||
1349 | simd_argreg = 0; | |
1350 | argreg = ARM_A1_REGNUM; | |
1351 | nstack = 0; | |
1352 | ||
1353 | /* The struct_return pointer occupies the first parameter | |
1354 | passing register. */ | |
1355 | if (struct_return) | |
c906108c | 1356 | { |
6529d2dd AC |
1357 | if (second_pass) |
1358 | { | |
1359 | if (arm_debug) | |
1360 | fprintf_unfiltered (gdb_stdlog, | |
1361 | "struct return in %s = 0x%s\n", | |
1362 | REGISTER_NAME (argreg), | |
1363 | paddr (struct_addr)); | |
1364 | write_register (argreg, struct_addr); | |
1365 | } | |
1366 | argreg++; | |
c906108c | 1367 | } |
ed9a39eb | 1368 | |
6529d2dd AC |
1369 | for (argnum = 0; argnum < nargs; argnum++) |
1370 | { | |
1371 | int len; | |
1372 | struct type *arg_type; | |
1373 | struct type *target_type; | |
1374 | enum type_code typecode; | |
1375 | char *val; | |
1376 | ||
1377 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1378 | len = TYPE_LENGTH (arg_type); | |
1379 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1380 | typecode = TYPE_CODE (arg_type); | |
1381 | val = VALUE_CONTENTS (args[argnum]); | |
1382 | ||
1383 | /* If the argument is a pointer to a function, and it is a | |
1384 | Thumb function, create a LOCAL copy of the value and set | |
1385 | the THUMB bit in it. */ | |
1386 | if (second_pass | |
1387 | && TYPE_CODE_PTR == typecode | |
1388 | && target_type != NULL | |
1389 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1390 | { |
6529d2dd AC |
1391 | CORE_ADDR regval = extract_address (val, len); |
1392 | if (arm_pc_is_thumb (regval)) | |
1393 | { | |
1394 | val = alloca (len); | |
1395 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1396 | } | |
c906108c | 1397 | } |
6529d2dd AC |
1398 | |
1399 | /* Copy the argument to general registers or the stack in | |
1400 | register-sized pieces. Large arguments are split between | |
1401 | registers and stack. */ | |
1402 | while (len > 0) | |
ed9a39eb | 1403 | { |
6529d2dd AC |
1404 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1405 | ||
1406 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1407 | { | |
1408 | /* The argument is being passed in a general purpose | |
1409 | register. */ | |
1410 | if (second_pass) | |
1411 | { | |
1412 | CORE_ADDR regval = extract_address (val, | |
1413 | partial_len); | |
1414 | if (arm_debug) | |
1415 | fprintf_unfiltered (gdb_stdlog, | |
1416 | "arg %d in %s = 0x%s\n", | |
1417 | argnum, | |
1418 | REGISTER_NAME (argreg), | |
1419 | phex (regval, REGISTER_SIZE)); | |
1420 | write_register (argreg, regval); | |
1421 | } | |
1422 | argreg++; | |
1423 | } | |
1424 | else | |
1425 | { | |
1426 | if (second_pass) | |
1427 | { | |
1428 | /* Push the arguments onto the stack. */ | |
1429 | if (arm_debug) | |
1430 | fprintf_unfiltered (gdb_stdlog, | |
1431 | "arg %d @ 0x%s + %d\n", | |
1432 | argnum, paddr (fp), nstack); | |
1433 | write_memory (fp + nstack, val, REGISTER_SIZE); | |
1434 | } | |
1435 | nstack += REGISTER_SIZE; | |
1436 | } | |
1437 | ||
1438 | len -= partial_len; | |
1439 | val += partial_len; | |
ed9a39eb JM |
1440 | } |
1441 | ||
c906108c SS |
1442 | } |
1443 | } | |
c906108c | 1444 | |
f211c6d4 | 1445 | /* Return the bottom of the argument list (pointed to by fp). */ |
6529d2dd | 1446 | return fp; |
c906108c SS |
1447 | } |
1448 | ||
da3c6d4a MS |
1449 | /* Pop the current frame. So long as the frame info has been |
1450 | initialized properly (see arm_init_extra_frame_info), this code | |
1451 | works for dummy frames as well as regular frames. I.e, there's no | |
1452 | need to have a special case for dummy frames. */ | |
148754e5 | 1453 | static void |
ed9a39eb | 1454 | arm_pop_frame (void) |
c906108c | 1455 | { |
c906108c | 1456 | int regnum; |
8b93c638 | 1457 | struct frame_info *frame = get_current_frame (); |
da50a4b7 AC |
1458 | CORE_ADDR old_SP = (get_frame_base (frame) |
1459 | - get_frame_extra_info (frame)->frameoffset | |
1460 | + get_frame_extra_info (frame)->framesize); | |
c906108c | 1461 | |
1e2330ba AC |
1462 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1463 | get_frame_base (frame), | |
1464 | get_frame_base (frame))) | |
848cfffb AC |
1465 | { |
1466 | generic_pop_dummy_frame (); | |
1467 | flush_cached_frames (); | |
1468 | return; | |
1469 | } | |
1470 | ||
f079148d | 1471 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
b2fb4676 | 1472 | if (get_frame_saved_regs (frame)[regnum] != 0) |
f079148d | 1473 | write_register (regnum, |
b2fb4676 | 1474 | read_memory_integer (get_frame_saved_regs (frame)[regnum], |
f079148d | 1475 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1476 | |
8bedc050 | 1477 | write_register (ARM_PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame)); |
34e8f22d | 1478 | write_register (ARM_SP_REGNUM, old_SP); |
c906108c SS |
1479 | |
1480 | flush_cached_frames (); | |
1481 | } | |
1482 | ||
1483 | static void | |
ed9a39eb | 1484 | print_fpu_flags (int flags) |
c906108c | 1485 | { |
c5aa993b JM |
1486 | if (flags & (1 << 0)) |
1487 | fputs ("IVO ", stdout); | |
1488 | if (flags & (1 << 1)) | |
1489 | fputs ("DVZ ", stdout); | |
1490 | if (flags & (1 << 2)) | |
1491 | fputs ("OFL ", stdout); | |
1492 | if (flags & (1 << 3)) | |
1493 | fputs ("UFL ", stdout); | |
1494 | if (flags & (1 << 4)) | |
1495 | fputs ("INX ", stdout); | |
1496 | putchar ('\n'); | |
c906108c SS |
1497 | } |
1498 | ||
5e74b15c RE |
1499 | /* Print interesting information about the floating point processor |
1500 | (if present) or emulator. */ | |
34e8f22d | 1501 | static void |
d855c300 | 1502 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1503 | struct frame_info *frame, const char *args) |
c906108c | 1504 | { |
34e8f22d | 1505 | register unsigned long status = read_register (ARM_FPS_REGNUM); |
c5aa993b JM |
1506 | int type; |
1507 | ||
1508 | type = (status >> 24) & 127; | |
1509 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1510 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1511 | type); |
1512 | fputs ("mask: ", stdout); | |
1513 | print_fpu_flags (status >> 16); | |
1514 | fputs ("flags: ", stdout); | |
1515 | print_fpu_flags (status); | |
c906108c SS |
1516 | } |
1517 | ||
34e8f22d RE |
1518 | /* Return the GDB type object for the "standard" data type of data in |
1519 | register N. */ | |
1520 | ||
1521 | static struct type * | |
032758dc AC |
1522 | arm_register_type (int regnum) |
1523 | { | |
34e8f22d | 1524 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
032758dc | 1525 | { |
d7449b42 | 1526 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1527 | return builtin_type_arm_ext_big; |
1528 | else | |
1529 | return builtin_type_arm_ext_littlebyte_bigword; | |
1530 | } | |
1531 | else | |
1532 | return builtin_type_int32; | |
1533 | } | |
1534 | ||
34e8f22d RE |
1535 | /* Index within `registers' of the first byte of the space for |
1536 | register N. */ | |
1537 | ||
1538 | static int | |
1539 | arm_register_byte (int regnum) | |
1540 | { | |
1541 | if (regnum < ARM_F0_REGNUM) | |
1542 | return regnum * INT_REGISTER_RAW_SIZE; | |
1543 | else if (regnum < ARM_PS_REGNUM) | |
1544 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1545 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE); | |
1546 | else | |
1547 | return (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
1548 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
1549 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); | |
1550 | } | |
1551 | ||
1552 | /* Number of bytes of storage in the actual machine representation for | |
1553 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
1554 | 12 bytes in length. */ | |
1555 | ||
1556 | static int | |
1557 | arm_register_raw_size (int regnum) | |
1558 | { | |
1559 | if (regnum < ARM_F0_REGNUM) | |
1560 | return INT_REGISTER_RAW_SIZE; | |
1561 | else if (regnum < ARM_FPS_REGNUM) | |
1562 | return FP_REGISTER_RAW_SIZE; | |
1563 | else | |
1564 | return STATUS_REGISTER_SIZE; | |
1565 | } | |
1566 | ||
1567 | /* Number of bytes of storage in a program's representation | |
1568 | for register N. */ | |
1569 | static int | |
1570 | arm_register_virtual_size (int regnum) | |
1571 | { | |
1572 | if (regnum < ARM_F0_REGNUM) | |
1573 | return INT_REGISTER_VIRTUAL_SIZE; | |
1574 | else if (regnum < ARM_FPS_REGNUM) | |
1575 | return FP_REGISTER_VIRTUAL_SIZE; | |
1576 | else | |
1577 | return STATUS_REGISTER_SIZE; | |
1578 | } | |
1579 | ||
26216b98 AC |
1580 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1581 | static int | |
1582 | arm_register_sim_regno (int regnum) | |
1583 | { | |
1584 | int reg = regnum; | |
1585 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
1586 | ||
1587 | if (reg < NUM_GREGS) | |
1588 | return SIM_ARM_R0_REGNUM + reg; | |
1589 | reg -= NUM_GREGS; | |
1590 | ||
1591 | if (reg < NUM_FREGS) | |
1592 | return SIM_ARM_FP0_REGNUM + reg; | |
1593 | reg -= NUM_FREGS; | |
1594 | ||
1595 | if (reg < NUM_SREGS) | |
1596 | return SIM_ARM_FPS_REGNUM + reg; | |
1597 | reg -= NUM_SREGS; | |
1598 | ||
1599 | internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum); | |
1600 | } | |
34e8f22d | 1601 | |
a37b3cc0 AC |
1602 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1603 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1604 | It is thought that this is is the floating-point register format on | |
1605 | little-endian systems. */ | |
c906108c | 1606 | |
ed9a39eb | 1607 | static void |
b508a996 RE |
1608 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
1609 | void *dbl) | |
c906108c | 1610 | { |
a37b3cc0 | 1611 | DOUBLEST d; |
d7449b42 | 1612 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1613 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1614 | else | |
1615 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1616 | ptr, &d); | |
b508a996 | 1617 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1618 | } |
1619 | ||
34e8f22d | 1620 | static void |
b508a996 | 1621 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
c906108c | 1622 | { |
a37b3cc0 | 1623 | DOUBLEST d; |
b508a996 | 1624 | floatformat_to_doublest (fmt, ptr, &d); |
d7449b42 | 1625 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1626 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1627 | else | |
1628 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1629 | &d, dbl); | |
c906108c | 1630 | } |
ed9a39eb | 1631 | |
c906108c | 1632 | static int |
ed9a39eb | 1633 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1634 | { |
1635 | if (cond == INST_AL || cond == INST_NV) | |
1636 | return 1; | |
1637 | ||
1638 | switch (cond) | |
1639 | { | |
1640 | case INST_EQ: | |
1641 | return ((status_reg & FLAG_Z) != 0); | |
1642 | case INST_NE: | |
1643 | return ((status_reg & FLAG_Z) == 0); | |
1644 | case INST_CS: | |
1645 | return ((status_reg & FLAG_C) != 0); | |
1646 | case INST_CC: | |
1647 | return ((status_reg & FLAG_C) == 0); | |
1648 | case INST_MI: | |
1649 | return ((status_reg & FLAG_N) != 0); | |
1650 | case INST_PL: | |
1651 | return ((status_reg & FLAG_N) == 0); | |
1652 | case INST_VS: | |
1653 | return ((status_reg & FLAG_V) != 0); | |
1654 | case INST_VC: | |
1655 | return ((status_reg & FLAG_V) == 0); | |
1656 | case INST_HI: | |
1657 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1658 | case INST_LS: | |
1659 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1660 | case INST_GE: | |
1661 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1662 | case INST_LT: | |
1663 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1664 | case INST_GT: | |
1665 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1666 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1667 | case INST_LE: |
1668 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1669 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1670 | } |
1671 | return 1; | |
1672 | } | |
1673 | ||
9512d7fd | 1674 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1675 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1676 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1677 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1678 | #define sbits(obj,st,fn) \ | |
1679 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1680 | #define BranchDest(addr,instr) \ | |
1681 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1682 | #define ARM_PC_32 1 | |
1683 | ||
1684 | static unsigned long | |
ed9a39eb JM |
1685 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1686 | unsigned long status_reg) | |
c906108c SS |
1687 | { |
1688 | unsigned long res, shift; | |
1689 | int rm = bits (inst, 0, 3); | |
1690 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1691 | |
1692 | if (bit (inst, 4)) | |
c906108c SS |
1693 | { |
1694 | int rs = bits (inst, 8, 11); | |
1695 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1696 | } | |
1697 | else | |
1698 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1699 | |
1700 | res = (rm == 15 | |
c906108c | 1701 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1702 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1703 | : read_register (rm)); |
1704 | ||
1705 | switch (shifttype) | |
1706 | { | |
c5aa993b | 1707 | case 0: /* LSL */ |
c906108c SS |
1708 | res = shift >= 32 ? 0 : res << shift; |
1709 | break; | |
c5aa993b JM |
1710 | |
1711 | case 1: /* LSR */ | |
c906108c SS |
1712 | res = shift >= 32 ? 0 : res >> shift; |
1713 | break; | |
1714 | ||
c5aa993b JM |
1715 | case 2: /* ASR */ |
1716 | if (shift >= 32) | |
1717 | shift = 31; | |
c906108c SS |
1718 | res = ((res & 0x80000000L) |
1719 | ? ~((~res) >> shift) : res >> shift); | |
1720 | break; | |
1721 | ||
c5aa993b | 1722 | case 3: /* ROR/RRX */ |
c906108c SS |
1723 | shift &= 31; |
1724 | if (shift == 0) | |
1725 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1726 | else | |
c5aa993b | 1727 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1728 | break; |
1729 | } | |
1730 | ||
1731 | return res & 0xffffffff; | |
1732 | } | |
1733 | ||
c906108c SS |
1734 | /* Return number of 1-bits in VAL. */ |
1735 | ||
1736 | static int | |
ed9a39eb | 1737 | bitcount (unsigned long val) |
c906108c SS |
1738 | { |
1739 | int nbits; | |
1740 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1741 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1742 | return nbits; |
1743 | } | |
1744 | ||
34e8f22d | 1745 | CORE_ADDR |
ed9a39eb | 1746 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1747 | { |
c5aa993b | 1748 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1749 | unsigned short inst1 = read_memory_integer (pc, 2); |
94c30b78 | 1750 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1751 | unsigned long offset; |
1752 | ||
1753 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1754 | { | |
1755 | CORE_ADDR sp; | |
1756 | ||
1757 | /* Fetch the saved PC from the stack. It's stored above | |
1758 | all of the other registers. */ | |
1759 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
34e8f22d | 1760 | sp = read_register (ARM_SP_REGNUM); |
c906108c SS |
1761 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
1762 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1763 | if (nextpc == pc) | |
1764 | error ("Infinite loop detected"); | |
1765 | } | |
1766 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1767 | { | |
34e8f22d | 1768 | unsigned long status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1769 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1770 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1771 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1772 | } | |
1773 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1774 | { | |
1775 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1776 | } | |
1777 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1778 | { | |
1779 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1780 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1781 | nextpc = pc_val + offset; |
1782 | } | |
1783 | ||
1784 | return nextpc; | |
1785 | } | |
1786 | ||
34e8f22d | 1787 | CORE_ADDR |
ed9a39eb | 1788 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1789 | { |
1790 | unsigned long pc_val; | |
1791 | unsigned long this_instr; | |
1792 | unsigned long status; | |
1793 | CORE_ADDR nextpc; | |
1794 | ||
1795 | if (arm_pc_is_thumb (pc)) | |
1796 | return thumb_get_next_pc (pc); | |
1797 | ||
1798 | pc_val = (unsigned long) pc; | |
1799 | this_instr = read_memory_integer (pc, 4); | |
34e8f22d | 1800 | status = read_register (ARM_PS_REGNUM); |
c5aa993b | 1801 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1802 | |
1803 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1804 | { | |
1805 | switch (bits (this_instr, 24, 27)) | |
1806 | { | |
c5aa993b | 1807 | case 0x0: |
94c30b78 | 1808 | case 0x1: /* data processing */ |
c5aa993b JM |
1809 | case 0x2: |
1810 | case 0x3: | |
c906108c SS |
1811 | { |
1812 | unsigned long operand1, operand2, result = 0; | |
1813 | unsigned long rn; | |
1814 | int c; | |
c5aa993b | 1815 | |
c906108c SS |
1816 | if (bits (this_instr, 12, 15) != 15) |
1817 | break; | |
1818 | ||
1819 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1820 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1821 | error ("Illegal update to pc in instruction"); |
1822 | ||
1823 | /* Multiply into PC */ | |
1824 | c = (status & FLAG_C) ? 1 : 0; | |
1825 | rn = bits (this_instr, 16, 19); | |
1826 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1827 | |
c906108c SS |
1828 | if (bit (this_instr, 25)) |
1829 | { | |
1830 | unsigned long immval = bits (this_instr, 0, 7); | |
1831 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1832 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1833 | & 0xffffffff; | |
c906108c | 1834 | } |
c5aa993b | 1835 | else /* operand 2 is a shifted register */ |
c906108c | 1836 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1837 | |
c906108c SS |
1838 | switch (bits (this_instr, 21, 24)) |
1839 | { | |
c5aa993b | 1840 | case 0x0: /*and */ |
c906108c SS |
1841 | result = operand1 & operand2; |
1842 | break; | |
1843 | ||
c5aa993b | 1844 | case 0x1: /*eor */ |
c906108c SS |
1845 | result = operand1 ^ operand2; |
1846 | break; | |
1847 | ||
c5aa993b | 1848 | case 0x2: /*sub */ |
c906108c SS |
1849 | result = operand1 - operand2; |
1850 | break; | |
1851 | ||
c5aa993b | 1852 | case 0x3: /*rsb */ |
c906108c SS |
1853 | result = operand2 - operand1; |
1854 | break; | |
1855 | ||
c5aa993b | 1856 | case 0x4: /*add */ |
c906108c SS |
1857 | result = operand1 + operand2; |
1858 | break; | |
1859 | ||
c5aa993b | 1860 | case 0x5: /*adc */ |
c906108c SS |
1861 | result = operand1 + operand2 + c; |
1862 | break; | |
1863 | ||
c5aa993b | 1864 | case 0x6: /*sbc */ |
c906108c SS |
1865 | result = operand1 - operand2 + c; |
1866 | break; | |
1867 | ||
c5aa993b | 1868 | case 0x7: /*rsc */ |
c906108c SS |
1869 | result = operand2 - operand1 + c; |
1870 | break; | |
1871 | ||
c5aa993b JM |
1872 | case 0x8: |
1873 | case 0x9: | |
1874 | case 0xa: | |
1875 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1876 | result = (unsigned long) nextpc; |
1877 | break; | |
1878 | ||
c5aa993b | 1879 | case 0xc: /*orr */ |
c906108c SS |
1880 | result = operand1 | operand2; |
1881 | break; | |
1882 | ||
c5aa993b | 1883 | case 0xd: /*mov */ |
c906108c SS |
1884 | /* Always step into a function. */ |
1885 | result = operand2; | |
c5aa993b | 1886 | break; |
c906108c | 1887 | |
c5aa993b | 1888 | case 0xe: /*bic */ |
c906108c SS |
1889 | result = operand1 & ~operand2; |
1890 | break; | |
1891 | ||
c5aa993b | 1892 | case 0xf: /*mvn */ |
c906108c SS |
1893 | result = ~operand2; |
1894 | break; | |
1895 | } | |
1896 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1897 | ||
1898 | if (nextpc == pc) | |
1899 | error ("Infinite loop detected"); | |
1900 | break; | |
1901 | } | |
c5aa993b JM |
1902 | |
1903 | case 0x4: | |
1904 | case 0x5: /* data transfer */ | |
1905 | case 0x6: | |
1906 | case 0x7: | |
c906108c SS |
1907 | if (bit (this_instr, 20)) |
1908 | { | |
1909 | /* load */ | |
1910 | if (bits (this_instr, 12, 15) == 15) | |
1911 | { | |
1912 | /* rd == pc */ | |
c5aa993b | 1913 | unsigned long rn; |
c906108c | 1914 | unsigned long base; |
c5aa993b | 1915 | |
c906108c SS |
1916 | if (bit (this_instr, 22)) |
1917 | error ("Illegal update to pc in instruction"); | |
1918 | ||
1919 | /* byte write to PC */ | |
1920 | rn = bits (this_instr, 16, 19); | |
1921 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1922 | if (bit (this_instr, 24)) | |
1923 | { | |
1924 | /* pre-indexed */ | |
1925 | int c = (status & FLAG_C) ? 1 : 0; | |
1926 | unsigned long offset = | |
c5aa993b | 1927 | (bit (this_instr, 25) |
ed9a39eb | 1928 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1929 | : bits (this_instr, 0, 11)); |
c906108c SS |
1930 | |
1931 | if (bit (this_instr, 23)) | |
1932 | base += offset; | |
1933 | else | |
1934 | base -= offset; | |
1935 | } | |
c5aa993b | 1936 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1937 | 4); |
c5aa993b | 1938 | |
c906108c SS |
1939 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1940 | ||
1941 | if (nextpc == pc) | |
1942 | error ("Infinite loop detected"); | |
1943 | } | |
1944 | } | |
1945 | break; | |
c5aa993b JM |
1946 | |
1947 | case 0x8: | |
1948 | case 0x9: /* block transfer */ | |
c906108c SS |
1949 | if (bit (this_instr, 20)) |
1950 | { | |
1951 | /* LDM */ | |
1952 | if (bit (this_instr, 15)) | |
1953 | { | |
1954 | /* loading pc */ | |
1955 | int offset = 0; | |
1956 | ||
1957 | if (bit (this_instr, 23)) | |
1958 | { | |
1959 | /* up */ | |
1960 | unsigned long reglist = bits (this_instr, 0, 14); | |
1961 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1962 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1963 | offset += 4; |
1964 | } | |
1965 | else if (bit (this_instr, 24)) | |
1966 | offset = -4; | |
c5aa993b | 1967 | |
c906108c | 1968 | { |
c5aa993b JM |
1969 | unsigned long rn_val = |
1970 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1971 | nextpc = |
1972 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1973 | + offset), |
c906108c SS |
1974 | 4); |
1975 | } | |
1976 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1977 | if (nextpc == pc) | |
1978 | error ("Infinite loop detected"); | |
1979 | } | |
1980 | } | |
1981 | break; | |
c5aa993b JM |
1982 | |
1983 | case 0xb: /* branch & link */ | |
1984 | case 0xa: /* branch */ | |
c906108c SS |
1985 | { |
1986 | nextpc = BranchDest (pc, this_instr); | |
1987 | ||
1988 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1989 | if (nextpc == pc) | |
1990 | error ("Infinite loop detected"); | |
1991 | break; | |
1992 | } | |
c5aa993b JM |
1993 | |
1994 | case 0xc: | |
1995 | case 0xd: | |
1996 | case 0xe: /* coproc ops */ | |
1997 | case 0xf: /* SWI */ | |
c906108c SS |
1998 | break; |
1999 | ||
2000 | default: | |
97e03143 | 2001 | fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n"); |
c906108c SS |
2002 | return (pc); |
2003 | } | |
2004 | } | |
2005 | ||
2006 | return nextpc; | |
2007 | } | |
2008 | ||
9512d7fd FN |
2009 | /* single_step() is called just before we want to resume the inferior, |
2010 | if we want to single-step it but there is no hardware or kernel | |
2011 | single-step support. We find the target of the coming instruction | |
2012 | and breakpoint it. | |
2013 | ||
94c30b78 MS |
2014 | single_step() is also called just after the inferior stops. If we |
2015 | had set up a simulated single-step, we undo our damage. */ | |
9512d7fd | 2016 | |
34e8f22d RE |
2017 | static void |
2018 | arm_software_single_step (enum target_signal sig, int insert_bpt) | |
9512d7fd | 2019 | { |
b8d5e71d | 2020 | static int next_pc; /* State between setting and unsetting. */ |
9512d7fd FN |
2021 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
2022 | ||
2023 | if (insert_bpt) | |
2024 | { | |
34e8f22d | 2025 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
80fcf3f0 | 2026 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2027 | } |
2028 | else | |
80fcf3f0 | 2029 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2030 | } |
9512d7fd | 2031 | |
c906108c SS |
2032 | #include "bfd-in2.h" |
2033 | #include "libcoff.h" | |
2034 | ||
2035 | static int | |
ed9a39eb | 2036 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2037 | { |
2038 | if (arm_pc_is_thumb (memaddr)) | |
2039 | { | |
c5aa993b JM |
2040 | static asymbol *asym; |
2041 | static combined_entry_type ce; | |
2042 | static struct coff_symbol_struct csym; | |
27cddce2 | 2043 | static struct bfd fake_bfd; |
c5aa993b | 2044 | static bfd_target fake_target; |
c906108c SS |
2045 | |
2046 | if (csym.native == NULL) | |
2047 | { | |
da3c6d4a MS |
2048 | /* Create a fake symbol vector containing a Thumb symbol. |
2049 | This is solely so that the code in print_insn_little_arm() | |
2050 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2051 | the presence of a Thumb symbol and switch to decoding | |
2052 | Thumb instructions. */ | |
c5aa993b JM |
2053 | |
2054 | fake_target.flavour = bfd_target_coff_flavour; | |
2055 | fake_bfd.xvec = &fake_target; | |
c906108c | 2056 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2057 | csym.native = &ce; |
2058 | csym.symbol.the_bfd = &fake_bfd; | |
2059 | csym.symbol.name = "fake"; | |
2060 | asym = (asymbol *) & csym; | |
c906108c | 2061 | } |
c5aa993b | 2062 | |
c906108c | 2063 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2064 | info->symbols = &asym; |
c906108c SS |
2065 | } |
2066 | else | |
2067 | info->symbols = NULL; | |
c5aa993b | 2068 | |
d7449b42 | 2069 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2070 | return print_insn_big_arm (memaddr, info); |
2071 | else | |
2072 | return print_insn_little_arm (memaddr, info); | |
2073 | } | |
2074 | ||
66e810cd RE |
2075 | /* The following define instruction sequences that will cause ARM |
2076 | cpu's to take an undefined instruction trap. These are used to | |
2077 | signal a breakpoint to GDB. | |
2078 | ||
2079 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2080 | modes. A different instruction is required for each mode. The ARM | |
2081 | cpu's can also be big or little endian. Thus four different | |
2082 | instructions are needed to support all cases. | |
2083 | ||
2084 | Note: ARMv4 defines several new instructions that will take the | |
2085 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2086 | not in fact add the new instructions. The new undefined | |
2087 | instructions in ARMv4 are all instructions that had no defined | |
2088 | behaviour in earlier chips. There is no guarantee that they will | |
2089 | raise an exception, but may be treated as NOP's. In practice, it | |
2090 | may only safe to rely on instructions matching: | |
2091 | ||
2092 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2093 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2094 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2095 | ||
2096 | Even this may only true if the condition predicate is true. The | |
2097 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2098 | ||
2099 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2100 | and NetBSD all use a software interrupt rather than an undefined | |
2101 | instruction to force a trap. This can be handled by by the | |
2102 | abi-specific code during establishment of the gdbarch vector. */ | |
2103 | ||
2104 | ||
d7b486e7 RE |
2105 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
2106 | override these definitions. */ | |
66e810cd RE |
2107 | #ifndef ARM_LE_BREAKPOINT |
2108 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
2109 | #endif | |
2110 | #ifndef ARM_BE_BREAKPOINT | |
2111 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
2112 | #endif | |
2113 | #ifndef THUMB_LE_BREAKPOINT | |
2114 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
2115 | #endif | |
2116 | #ifndef THUMB_BE_BREAKPOINT | |
2117 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
2118 | #endif | |
2119 | ||
2120 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2121 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2122 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2123 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2124 | ||
34e8f22d RE |
2125 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2126 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2127 | breakpoint should be used. It returns a pointer to a string of |
2128 | bytes that encode a breakpoint instruction, stores the length of | |
2129 | the string to *lenptr, and adjusts the program counter (if | |
2130 | necessary) to point to the actual memory location where the | |
c906108c SS |
2131 | breakpoint should be inserted. */ |
2132 | ||
34e8f22d RE |
2133 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
2134 | breakpoints and storing their handles instread of what was in | |
2135 | memory. It is nice that this is the same size as a handle - | |
94c30b78 | 2136 | otherwise remote-rdp will have to change. */ |
34e8f22d | 2137 | |
ab89facf | 2138 | static const unsigned char * |
ed9a39eb | 2139 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2140 | { |
66e810cd RE |
2141 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2142 | ||
c906108c SS |
2143 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
2144 | { | |
66e810cd RE |
2145 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2146 | *lenptr = tdep->thumb_breakpoint_size; | |
2147 | return tdep->thumb_breakpoint; | |
c906108c SS |
2148 | } |
2149 | else | |
2150 | { | |
66e810cd RE |
2151 | *lenptr = tdep->arm_breakpoint_size; |
2152 | return tdep->arm_breakpoint; | |
c906108c SS |
2153 | } |
2154 | } | |
ed9a39eb JM |
2155 | |
2156 | /* Extract from an array REGBUF containing the (raw) register state a | |
2157 | function return value of type TYPE, and copy that, in virtual | |
2158 | format, into VALBUF. */ | |
2159 | ||
34e8f22d | 2160 | static void |
ed9a39eb | 2161 | arm_extract_return_value (struct type *type, |
b508a996 RE |
2162 | struct regcache *regs, |
2163 | void *dst) | |
ed9a39eb | 2164 | { |
b508a996 RE |
2165 | bfd_byte *valbuf = dst; |
2166 | ||
ed9a39eb | 2167 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 RE |
2168 | { |
2169 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2170 | ||
2171 | switch (tdep->fp_model) | |
2172 | { | |
2173 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2174 | { |
2175 | /* The value is in register F0 in internal format. We need to | |
2176 | extract the raw value and then convert it to the desired | |
2177 | internal type. */ | |
2178 | bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE]; | |
2179 | ||
2180 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2181 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
2182 | valbuf); | |
2183 | } | |
08216dd7 RE |
2184 | break; |
2185 | ||
2186 | case ARM_FLOAT_SOFT: | |
2187 | case ARM_FLOAT_SOFT_VFP: | |
b508a996 RE |
2188 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2189 | if (TYPE_LENGTH (type) > 4) | |
2190 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
2191 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2192 | break; |
2193 | ||
2194 | default: | |
2195 | internal_error | |
2196 | (__FILE__, __LINE__, | |
2197 | "arm_extract_return_value: Floating point model not supported"); | |
2198 | break; | |
2199 | } | |
2200 | } | |
b508a996 RE |
2201 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2202 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2203 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2204 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2205 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2206 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2207 | { | |
2208 | /* If the the type is a plain integer, then the access is | |
2209 | straight-forward. Otherwise we have to play around a bit more. */ | |
2210 | int len = TYPE_LENGTH (type); | |
2211 | int regno = ARM_A1_REGNUM; | |
2212 | ULONGEST tmp; | |
2213 | ||
2214 | while (len > 0) | |
2215 | { | |
2216 | /* By using store_unsigned_integer we avoid having to do | |
2217 | anything special for small big-endian values. */ | |
2218 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2219 | store_unsigned_integer (valbuf, | |
2220 | (len > INT_REGISTER_RAW_SIZE | |
2221 | ? INT_REGISTER_RAW_SIZE : len), | |
2222 | tmp); | |
2223 | len -= INT_REGISTER_RAW_SIZE; | |
2224 | valbuf += INT_REGISTER_RAW_SIZE; | |
2225 | } | |
2226 | } | |
ed9a39eb | 2227 | else |
b508a996 RE |
2228 | { |
2229 | /* For a structure or union the behaviour is as if the value had | |
2230 | been stored to word-aligned memory and then loaded into | |
2231 | registers with 32-bit load instruction(s). */ | |
2232 | int len = TYPE_LENGTH (type); | |
2233 | int regno = ARM_A1_REGNUM; | |
2234 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2235 | ||
2236 | while (len > 0) | |
2237 | { | |
2238 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2239 | memcpy (valbuf, tmpbuf, | |
2240 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2241 | len -= INT_REGISTER_RAW_SIZE; | |
2242 | valbuf += INT_REGISTER_RAW_SIZE; | |
2243 | } | |
2244 | } | |
34e8f22d RE |
2245 | } |
2246 | ||
67255d04 RE |
2247 | /* Extract from an array REGBUF containing the (raw) register state |
2248 | the address in which a function should return its structure value. */ | |
2249 | ||
2250 | static CORE_ADDR | |
95f95911 | 2251 | arm_extract_struct_value_address (struct regcache *regcache) |
67255d04 | 2252 | { |
95f95911 MS |
2253 | ULONGEST ret; |
2254 | ||
2255 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); | |
2256 | return ret; | |
67255d04 RE |
2257 | } |
2258 | ||
2259 | /* Will a function return an aggregate type in memory or in a | |
2260 | register? Return 0 if an aggregate type can be returned in a | |
2261 | register, 1 if it must be returned in memory. */ | |
2262 | ||
2263 | static int | |
2264 | arm_use_struct_convention (int gcc_p, struct type *type) | |
2265 | { | |
2266 | int nRc; | |
2267 | register enum type_code code; | |
2268 | ||
2269 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
2270 | registers. For an aggregate type to be integer like, its size | |
2271 | must be less than or equal to REGISTER_SIZE and the offset of | |
2272 | each addressable subfield must be zero. Note that bit fields are | |
2273 | not addressable, and all addressable subfields of unions always | |
2274 | start at offset zero. | |
2275 | ||
2276 | This function is based on the behaviour of GCC 2.95.1. | |
2277 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2278 | ||
2279 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2280 | parameters correctly for a function returning the following | |
2281 | structure: struct { float f;}; This should be returned in memory, | |
2282 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2283 | know of any way to detect if a function like the above has been | |
2284 | compiled with the correct calling convention. */ | |
2285 | ||
2286 | /* All aggregate types that won't fit in a register must be returned | |
2287 | in memory. */ | |
2288 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
2289 | { | |
2290 | return 1; | |
2291 | } | |
2292 | ||
2293 | /* The only aggregate types that can be returned in a register are | |
2294 | structs and unions. Arrays must be returned in memory. */ | |
2295 | code = TYPE_CODE (type); | |
2296 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2297 | { | |
2298 | return 1; | |
2299 | } | |
2300 | ||
2301 | /* Assume all other aggregate types can be returned in a register. | |
2302 | Run a check for structures, unions and arrays. */ | |
2303 | nRc = 0; | |
2304 | ||
2305 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2306 | { | |
2307 | int i; | |
2308 | /* Need to check if this struct/union is "integer" like. For | |
2309 | this to be true, its size must be less than or equal to | |
2310 | REGISTER_SIZE and the offset of each addressable subfield | |
2311 | must be zero. Note that bit fields are not addressable, and | |
2312 | unions always start at offset zero. If any of the subfields | |
2313 | is a floating point type, the struct/union cannot be an | |
2314 | integer type. */ | |
2315 | ||
2316 | /* For each field in the object, check: | |
2317 | 1) Is it FP? --> yes, nRc = 1; | |
2318 | 2) Is it addressable (bitpos != 0) and | |
2319 | not packed (bitsize == 0)? | |
2320 | --> yes, nRc = 1 | |
2321 | */ | |
2322 | ||
2323 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2324 | { | |
2325 | enum type_code field_type_code; | |
2326 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
2327 | ||
2328 | /* Is it a floating point type field? */ | |
2329 | if (field_type_code == TYPE_CODE_FLT) | |
2330 | { | |
2331 | nRc = 1; | |
2332 | break; | |
2333 | } | |
2334 | ||
2335 | /* If bitpos != 0, then we have to care about it. */ | |
2336 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2337 | { | |
2338 | /* Bitfields are not addressable. If the field bitsize is | |
2339 | zero, then the field is not packed. Hence it cannot be | |
2340 | a bitfield or any other packed type. */ | |
2341 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2342 | { | |
2343 | nRc = 1; | |
2344 | break; | |
2345 | } | |
2346 | } | |
2347 | } | |
2348 | } | |
2349 | ||
2350 | return nRc; | |
2351 | } | |
2352 | ||
34e8f22d RE |
2353 | /* Write into appropriate registers a function return value of type |
2354 | TYPE, given in virtual format. */ | |
2355 | ||
2356 | static void | |
b508a996 RE |
2357 | arm_store_return_value (struct type *type, struct regcache *regs, |
2358 | const void *src) | |
34e8f22d | 2359 | { |
b508a996 RE |
2360 | const bfd_byte *valbuf = src; |
2361 | ||
34e8f22d RE |
2362 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2363 | { | |
08216dd7 | 2364 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7bbcf283 | 2365 | char buf[ARM_MAX_REGISTER_RAW_SIZE]; |
34e8f22d | 2366 | |
08216dd7 RE |
2367 | switch (tdep->fp_model) |
2368 | { | |
2369 | case ARM_FLOAT_FPA: | |
2370 | ||
b508a996 RE |
2371 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
2372 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); | |
08216dd7 RE |
2373 | break; |
2374 | ||
2375 | case ARM_FLOAT_SOFT: | |
2376 | case ARM_FLOAT_SOFT_VFP: | |
b508a996 RE |
2377 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2378 | if (TYPE_LENGTH (type) > 4) | |
2379 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
2380 | valbuf + INT_REGISTER_RAW_SIZE); | |
08216dd7 RE |
2381 | break; |
2382 | ||
2383 | default: | |
2384 | internal_error | |
2385 | (__FILE__, __LINE__, | |
2386 | "arm_store_return_value: Floating point model not supported"); | |
2387 | break; | |
2388 | } | |
34e8f22d | 2389 | } |
b508a996 RE |
2390 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2391 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2392 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2393 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2394 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2395 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2396 | { | |
2397 | if (TYPE_LENGTH (type) <= 4) | |
2398 | { | |
2399 | /* Values of one word or less are zero/sign-extended and | |
2400 | returned in r0. */ | |
2401 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2402 | LONGEST val = unpack_long (type, valbuf); | |
2403 | ||
2404 | store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val); | |
2405 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); | |
2406 | } | |
2407 | else | |
2408 | { | |
2409 | /* Integral values greater than one word are stored in consecutive | |
2410 | registers starting with r0. This will always be a multiple of | |
2411 | the regiser size. */ | |
2412 | int len = TYPE_LENGTH (type); | |
2413 | int regno = ARM_A1_REGNUM; | |
2414 | ||
2415 | while (len > 0) | |
2416 | { | |
2417 | regcache_cooked_write (regs, regno++, valbuf); | |
2418 | len -= INT_REGISTER_RAW_SIZE; | |
2419 | valbuf += INT_REGISTER_RAW_SIZE; | |
2420 | } | |
2421 | } | |
2422 | } | |
34e8f22d | 2423 | else |
b508a996 RE |
2424 | { |
2425 | /* For a structure or union the behaviour is as if the value had | |
2426 | been stored to word-aligned memory and then loaded into | |
2427 | registers with 32-bit load instruction(s). */ | |
2428 | int len = TYPE_LENGTH (type); | |
2429 | int regno = ARM_A1_REGNUM; | |
2430 | bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE]; | |
2431 | ||
2432 | while (len > 0) | |
2433 | { | |
2434 | memcpy (tmpbuf, valbuf, | |
2435 | len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len); | |
2436 | regcache_cooked_write (regs, regno++, tmpbuf); | |
2437 | len -= INT_REGISTER_RAW_SIZE; | |
2438 | valbuf += INT_REGISTER_RAW_SIZE; | |
2439 | } | |
2440 | } | |
34e8f22d RE |
2441 | } |
2442 | ||
2443 | /* Store the address of the place in which to copy the structure the | |
94c30b78 | 2444 | subroutine will return. This is called from call_function. */ |
34e8f22d RE |
2445 | |
2446 | static void | |
2447 | arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
2448 | { | |
2449 | write_register (ARM_A1_REGNUM, addr); | |
ed9a39eb JM |
2450 | } |
2451 | ||
9df628e0 RE |
2452 | static int |
2453 | arm_get_longjmp_target (CORE_ADDR *pc) | |
2454 | { | |
2455 | CORE_ADDR jb_addr; | |
2456 | char buf[INT_REGISTER_RAW_SIZE]; | |
2457 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2458 | ||
2459 | jb_addr = read_register (ARM_A1_REGNUM); | |
2460 | ||
2461 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2462 | INT_REGISTER_RAW_SIZE)) | |
2463 | return 0; | |
2464 | ||
2465 | *pc = extract_address (buf, INT_REGISTER_RAW_SIZE); | |
2466 | return 1; | |
2467 | } | |
2468 | ||
ed9a39eb | 2469 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
c906108c SS |
2470 | |
2471 | int | |
ed9a39eb | 2472 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2473 | { |
2474 | CORE_ADDR start_addr; | |
2475 | ||
ed9a39eb JM |
2476 | /* Find the starting address of the function containing the PC. If |
2477 | the caller didn't give us a name, look it up at the same time. */ | |
94c30b78 MS |
2478 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
2479 | &start_addr, NULL)) | |
c906108c SS |
2480 | return 0; |
2481 | ||
2482 | return strncmp (name, "_call_via_r", 11) == 0; | |
2483 | } | |
2484 | ||
ed9a39eb JM |
2485 | /* If PC is in a Thumb call or return stub, return the address of the |
2486 | target PC, which is in a register. The thunk functions are called | |
2487 | _called_via_xx, where x is the register name. The possible names | |
2488 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2489 | |
2490 | CORE_ADDR | |
ed9a39eb | 2491 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2492 | { |
c5aa993b | 2493 | char *name; |
c906108c SS |
2494 | CORE_ADDR start_addr; |
2495 | ||
2496 | /* Find the starting address and name of the function containing the PC. */ | |
2497 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2498 | return 0; | |
2499 | ||
2500 | /* Call thunks always start with "_call_via_". */ | |
2501 | if (strncmp (name, "_call_via_", 10) == 0) | |
2502 | { | |
ed9a39eb JM |
2503 | /* Use the name suffix to determine which register contains the |
2504 | target PC. */ | |
c5aa993b JM |
2505 | static char *table[15] = |
2506 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2507 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2508 | }; | |
c906108c SS |
2509 | int regno; |
2510 | ||
2511 | for (regno = 0; regno <= 14; regno++) | |
2512 | if (strcmp (&name[10], table[regno]) == 0) | |
2513 | return read_register (regno); | |
2514 | } | |
ed9a39eb | 2515 | |
c5aa993b | 2516 | return 0; /* not a stub */ |
c906108c SS |
2517 | } |
2518 | ||
da3c6d4a MS |
2519 | /* If the user changes the register disassembly flavor used for info |
2520 | register and other commands, we have to also switch the flavor used | |
2521 | in opcodes for disassembly output. This function is run in the set | |
94c30b78 | 2522 | disassembly_flavor command, and does that. */ |
bc90b915 FN |
2523 | |
2524 | static void | |
2525 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2526 | struct cmd_list_element *c) | |
2527 | { | |
2528 | set_disassembly_flavor (); | |
2529 | } | |
2530 | \f | |
966fbf70 | 2531 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2532 | static const char * |
34e8f22d | 2533 | arm_register_name (int i) |
966fbf70 RE |
2534 | { |
2535 | return arm_register_names[i]; | |
2536 | } | |
2537 | ||
bc90b915 FN |
2538 | static void |
2539 | set_disassembly_flavor (void) | |
2540 | { | |
2541 | const char *setname, *setdesc, **regnames; | |
2542 | int numregs, j; | |
2543 | ||
94c30b78 | 2544 | /* Find the flavor that the user wants in the opcodes table. */ |
bc90b915 FN |
2545 | int current = 0; |
2546 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2547 | while ((disassembly_flavor != setname) | |
2548 | && (current < num_flavor_options)) | |
2549 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2550 | current_option = current; | |
2551 | ||
94c30b78 | 2552 | /* Fill our copy. */ |
bc90b915 FN |
2553 | for (j = 0; j < numregs; j++) |
2554 | arm_register_names[j] = (char *) regnames[j]; | |
2555 | ||
94c30b78 | 2556 | /* Adjust case. */ |
34e8f22d | 2557 | if (isupper (*regnames[ARM_PC_REGNUM])) |
bc90b915 | 2558 | { |
34e8f22d RE |
2559 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
2560 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; | |
bc90b915 FN |
2561 | } |
2562 | else | |
2563 | { | |
34e8f22d RE |
2564 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
2565 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; | |
bc90b915 FN |
2566 | } |
2567 | ||
94c30b78 | 2568 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2569 | set_arm_regname_option (current); |
2570 | } | |
2571 | ||
2572 | /* arm_othernames implements the "othernames" command. This is kind | |
2573 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2574 | also used for the x86 gdb. I will keep this around, however, in | |
94c30b78 | 2575 | case anyone is actually using it. */ |
bc90b915 FN |
2576 | |
2577 | static void | |
2578 | arm_othernames (char *names, int n) | |
2579 | { | |
94c30b78 | 2580 | /* Circle through the various flavors. */ |
bc90b915 FN |
2581 | current_option = (current_option + 1) % num_flavor_options; |
2582 | ||
2583 | disassembly_flavor = valid_flavors[current_option]; | |
94c30b78 | 2584 | set_disassembly_flavor (); |
bc90b915 FN |
2585 | } |
2586 | ||
a42dd537 KB |
2587 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2588 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2589 | Note, however, that link.h is not actually referred to in this file. | |
2590 | Instead, the relevant structs offsets were obtained from examining | |
2591 | link.h. (We can't refer to link.h from this file because the host | |
2592 | system won't necessarily have it, or if it does, the structs which | |
94c30b78 | 2593 | it defines will refer to the host system, not the target). */ |
a42dd537 KB |
2594 | |
2595 | struct link_map_offsets * | |
2596 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2597 | { | |
2598 | static struct link_map_offsets lmo; | |
2599 | static struct link_map_offsets *lmp = 0; | |
2600 | ||
2601 | if (lmp == 0) | |
2602 | { | |
2603 | lmp = &lmo; | |
2604 | ||
2605 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
94c30b78 | 2606 | need. */ |
a42dd537 KB |
2607 | |
2608 | lmo.r_map_offset = 4; | |
2609 | lmo.r_map_size = 4; | |
2610 | ||
2611 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
94c30b78 | 2612 | need. */ |
a42dd537 KB |
2613 | |
2614 | lmo.l_addr_offset = 0; | |
2615 | lmo.l_addr_size = 4; | |
2616 | ||
2617 | lmo.l_name_offset = 4; | |
2618 | lmo.l_name_size = 4; | |
2619 | ||
2620 | lmo.l_next_offset = 12; | |
2621 | lmo.l_next_size = 4; | |
2622 | ||
2623 | lmo.l_prev_offset = 16; | |
2624 | lmo.l_prev_size = 4; | |
2625 | } | |
2626 | ||
2627 | return lmp; | |
2628 | } | |
2629 | ||
082fc60d RE |
2630 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2631 | function. */ | |
2632 | ||
2633 | static int | |
2634 | coff_sym_is_thumb (int val) | |
2635 | { | |
2636 | return (val == C_THUMBEXT || | |
2637 | val == C_THUMBSTAT || | |
2638 | val == C_THUMBEXTFUNC || | |
2639 | val == C_THUMBSTATFUNC || | |
2640 | val == C_THUMBLABEL); | |
2641 | } | |
2642 | ||
2643 | /* arm_coff_make_msymbol_special() | |
2644 | arm_elf_make_msymbol_special() | |
2645 | ||
2646 | These functions test whether the COFF or ELF symbol corresponds to | |
2647 | an address in thumb code, and set a "special" bit in a minimal | |
2648 | symbol to indicate that it does. */ | |
2649 | ||
34e8f22d | 2650 | static void |
082fc60d RE |
2651 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2652 | { | |
2653 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2654 | STT_ARM_TFUNC). */ | |
2655 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2656 | == STT_LOPROC) | |
2657 | MSYMBOL_SET_SPECIAL (msym); | |
2658 | } | |
2659 | ||
34e8f22d | 2660 | static void |
082fc60d RE |
2661 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2662 | { | |
2663 | if (coff_sym_is_thumb (val)) | |
2664 | MSYMBOL_SET_SPECIAL (msym); | |
2665 | } | |
2666 | ||
97e03143 | 2667 | \f |
70f80edf JT |
2668 | static enum gdb_osabi |
2669 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2670 | { |
70f80edf JT |
2671 | unsigned int elfosabi, eflags; |
2672 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; | |
97e03143 | 2673 | |
70f80edf | 2674 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2675 | |
70f80edf | 2676 | switch (elfosabi) |
97e03143 | 2677 | { |
70f80edf JT |
2678 | case ELFOSABI_NONE: |
2679 | /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the | |
2680 | file are conforming to the base specification for that machine | |
2681 | (there are no OS-specific extensions). In order to determine the | |
2682 | real OS in use we must look for OS notes that have been added. */ | |
2683 | bfd_map_over_sections (abfd, | |
2684 | generic_elf_osabi_sniff_abi_tag_sections, | |
2685 | &osabi); | |
2686 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2687 | { |
70f80edf JT |
2688 | /* Existing ARM tools don't set this field, so look at the EI_FLAGS |
2689 | field for more information. */ | |
2690 | eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags); | |
2691 | switch (eflags) | |
97e03143 | 2692 | { |
70f80edf JT |
2693 | case EF_ARM_EABI_VER1: |
2694 | osabi = GDB_OSABI_ARM_EABI_V1; | |
97e03143 RE |
2695 | break; |
2696 | ||
70f80edf JT |
2697 | case EF_ARM_EABI_VER2: |
2698 | osabi = GDB_OSABI_ARM_EABI_V2; | |
97e03143 RE |
2699 | break; |
2700 | ||
70f80edf JT |
2701 | case EF_ARM_EABI_UNKNOWN: |
2702 | /* Assume GNU tools. */ | |
2703 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2704 | break; |
2705 | ||
70f80edf JT |
2706 | default: |
2707 | internal_error (__FILE__, __LINE__, | |
2708 | "arm_elf_osabi_sniffer: Unknown ARM EABI " | |
2709 | "version 0x%x", eflags); | |
97e03143 RE |
2710 | } |
2711 | } | |
70f80edf | 2712 | break; |
97e03143 | 2713 | |
70f80edf JT |
2714 | case ELFOSABI_ARM: |
2715 | /* GNU tools use this value. Check note sections in this case, | |
2716 | as well. */ | |
97e03143 | 2717 | bfd_map_over_sections (abfd, |
70f80edf JT |
2718 | generic_elf_osabi_sniff_abi_tag_sections, |
2719 | &osabi); | |
2720 | if (osabi == GDB_OSABI_UNKNOWN) | |
97e03143 | 2721 | { |
70f80edf JT |
2722 | /* Assume APCS ABI. */ |
2723 | osabi = GDB_OSABI_ARM_APCS; | |
97e03143 RE |
2724 | } |
2725 | break; | |
2726 | ||
97e03143 | 2727 | case ELFOSABI_FREEBSD: |
70f80edf JT |
2728 | osabi = GDB_OSABI_FREEBSD_ELF; |
2729 | break; | |
97e03143 | 2730 | |
70f80edf JT |
2731 | case ELFOSABI_NETBSD: |
2732 | osabi = GDB_OSABI_NETBSD_ELF; | |
2733 | break; | |
97e03143 | 2734 | |
70f80edf JT |
2735 | case ELFOSABI_LINUX: |
2736 | osabi = GDB_OSABI_LINUX; | |
2737 | break; | |
97e03143 RE |
2738 | } |
2739 | ||
70f80edf | 2740 | return osabi; |
97e03143 RE |
2741 | } |
2742 | ||
70f80edf | 2743 | \f |
da3c6d4a MS |
2744 | /* Initialize the current architecture based on INFO. If possible, |
2745 | re-use an architecture from ARCHES, which is a list of | |
2746 | architectures already created during this debugging session. | |
97e03143 | 2747 | |
da3c6d4a MS |
2748 | Called e.g. at program startup, when reading a core file, and when |
2749 | reading a binary file. */ | |
97e03143 | 2750 | |
39bbf761 RE |
2751 | static struct gdbarch * |
2752 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2753 | { | |
97e03143 | 2754 | struct gdbarch_tdep *tdep; |
39bbf761 RE |
2755 | struct gdbarch *gdbarch; |
2756 | ||
97e03143 | 2757 | /* Try to deterimine the ABI of the object we are loading. */ |
39bbf761 | 2758 | |
4be87837 | 2759 | if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) |
97e03143 | 2760 | { |
4be87837 | 2761 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2762 | { |
4be87837 DJ |
2763 | case bfd_target_aout_flavour: |
2764 | /* Assume it's an old APCS-style ABI. */ | |
2765 | info.osabi = GDB_OSABI_ARM_APCS; | |
2766 | break; | |
97e03143 | 2767 | |
4be87837 DJ |
2768 | case bfd_target_coff_flavour: |
2769 | /* Assume it's an old APCS-style ABI. */ | |
2770 | /* XXX WinCE? */ | |
2771 | info.osabi = GDB_OSABI_ARM_APCS; | |
2772 | break; | |
97e03143 | 2773 | |
4be87837 DJ |
2774 | default: |
2775 | /* Leave it as "unknown". */ | |
50ceaba5 | 2776 | break; |
97e03143 RE |
2777 | } |
2778 | } | |
2779 | ||
4be87837 DJ |
2780 | /* If there is already a candidate, use it. */ |
2781 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2782 | if (arches != NULL) | |
2783 | return arches->gdbarch; | |
97e03143 RE |
2784 | |
2785 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2786 | gdbarch = gdbarch_alloc (&info, tdep); | |
2787 | ||
a5afb99f AC |
2788 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
2789 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
2790 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
2791 | ||
08216dd7 RE |
2792 | /* This is the way it has always defaulted. */ |
2793 | tdep->fp_model = ARM_FLOAT_FPA; | |
2794 | ||
2795 | /* Breakpoints. */ | |
67255d04 RE |
2796 | switch (info.byte_order) |
2797 | { | |
2798 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
2799 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
2800 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
2801 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
2802 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
2803 | ||
67255d04 RE |
2804 | break; |
2805 | ||
2806 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
2807 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
2808 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
2809 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
2810 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
2811 | ||
67255d04 RE |
2812 | break; |
2813 | ||
2814 | default: | |
2815 | internal_error (__FILE__, __LINE__, | |
2816 | "arm_gdbarch_init: bad byte order for float format"); | |
2817 | } | |
2818 | ||
d7b486e7 RE |
2819 | /* On ARM targets char defaults to unsigned. */ |
2820 | set_gdbarch_char_signed (gdbarch, 0); | |
2821 | ||
9df628e0 | 2822 | /* This should be low enough for everything. */ |
97e03143 | 2823 | tdep->lowest_pc = 0x20; |
94c30b78 | 2824 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 2825 | |
848cfffb AC |
2826 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
2827 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
2828 | ||
2829 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
2830 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
2831 | ||
2832 | set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words); | |
2833 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); | |
2834 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
2835 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
2836 | ||
2837 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); | |
848cfffb AC |
2838 | |
2839 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
2840 | set_gdbarch_push_return_address (gdbarch, arm_push_return_address); | |
39bbf761 | 2841 | |
39bbf761 RE |
2842 | set_gdbarch_push_arguments (gdbarch, arm_push_arguments); |
2843 | ||
148754e5 | 2844 | /* Frame handling. */ |
39bbf761 | 2845 | set_gdbarch_frame_chain_valid (gdbarch, arm_frame_chain_valid); |
e9582e71 | 2846 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, arm_init_extra_frame_info); |
148754e5 RE |
2847 | set_gdbarch_read_fp (gdbarch, arm_read_fp); |
2848 | set_gdbarch_frame_chain (gdbarch, arm_frame_chain); | |
2849 | set_gdbarch_frameless_function_invocation | |
2850 | (gdbarch, arm_frameless_function_invocation); | |
8bedc050 | 2851 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, arm_frame_saved_pc); |
148754e5 RE |
2852 | set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address); |
2853 | set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address); | |
2854 | set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args); | |
2855 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
f30ee0bc | 2856 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs); |
749b82f6 | 2857 | set_gdbarch_deprecated_pop_frame (gdbarch, arm_pop_frame); |
148754e5 | 2858 | |
34e8f22d RE |
2859 | /* Address manipulation. */ |
2860 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
2861 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
2862 | ||
2863 | /* Offset from address of function to start of its code. */ | |
2864 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2865 | ||
2866 | /* Advance PC across function entry code. */ | |
2867 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
2868 | ||
2869 | /* Get the PC when a frame might not be available. */ | |
2870 | set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); | |
2871 | ||
2872 | /* The stack grows downward. */ | |
2873 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2874 | ||
2875 | /* Breakpoint manipulation. */ | |
2876 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
2877 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2878 | ||
2879 | /* Information about registers, etc. */ | |
2880 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
94c30b78 | 2881 | set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
2882 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
2883 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
2884 | set_gdbarch_register_byte (gdbarch, arm_register_byte); | |
2885 | set_gdbarch_register_bytes (gdbarch, | |
2886 | (NUM_GREGS * INT_REGISTER_RAW_SIZE | |
2887 | + NUM_FREGS * FP_REGISTER_RAW_SIZE | |
2888 | + NUM_SREGS * STATUS_REGISTER_SIZE)); | |
2889 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); | |
2890 | set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size); | |
2891 | set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size); | |
a0ed5532 AC |
2892 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE); |
2893 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE); | |
34e8f22d RE |
2894 | set_gdbarch_register_virtual_type (gdbarch, arm_register_type); |
2895 | ||
26216b98 AC |
2896 | /* Internal <-> external register number maps. */ |
2897 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); | |
2898 | ||
34e8f22d RE |
2899 | /* Integer registers are 4 bytes. */ |
2900 | set_gdbarch_register_size (gdbarch, 4); | |
2901 | set_gdbarch_register_name (gdbarch, arm_register_name); | |
2902 | ||
2903 | /* Returning results. */ | |
b508a996 RE |
2904 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
2905 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); | |
34e8f22d | 2906 | set_gdbarch_store_struct_return (gdbarch, arm_store_struct_return); |
67255d04 | 2907 | set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention); |
95f95911 | 2908 | set_gdbarch_extract_struct_value_address (gdbarch, |
67255d04 | 2909 | arm_extract_struct_value_address); |
34e8f22d RE |
2910 | |
2911 | /* Single stepping. */ | |
2912 | /* XXX For an RDI target we should ask the target if it can single-step. */ | |
2913 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); | |
2914 | ||
2915 | /* Minsymbol frobbing. */ | |
2916 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
2917 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
2918 | arm_coff_make_msymbol_special); | |
2919 | ||
97e03143 | 2920 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 2921 | gdbarch_init_osabi (info, gdbarch); |
97e03143 RE |
2922 | |
2923 | /* Now we have tuned the configuration, set a few final things, | |
2924 | based on what the OS ABI has told us. */ | |
2925 | ||
9df628e0 RE |
2926 | if (tdep->jb_pc >= 0) |
2927 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
2928 | ||
08216dd7 RE |
2929 | /* Floating point sizes and format. */ |
2930 | switch (info.byte_order) | |
2931 | { | |
2932 | case BFD_ENDIAN_BIG: | |
2933 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); | |
2934 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); | |
2935 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
2936 | ||
2937 | break; | |
2938 | ||
2939 | case BFD_ENDIAN_LITTLE: | |
2940 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); | |
2941 | if (tdep->fp_model == ARM_FLOAT_VFP | |
2942 | || tdep->fp_model == ARM_FLOAT_SOFT_VFP) | |
2943 | { | |
2944 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); | |
2945 | set_gdbarch_long_double_format (gdbarch, | |
2946 | &floatformat_ieee_double_little); | |
2947 | } | |
2948 | else | |
2949 | { | |
2950 | set_gdbarch_double_format | |
2951 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2952 | set_gdbarch_long_double_format | |
2953 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); | |
2954 | } | |
2955 | break; | |
2956 | ||
2957 | default: | |
2958 | internal_error (__FILE__, __LINE__, | |
2959 | "arm_gdbarch_init: bad byte order for float format"); | |
2960 | } | |
2961 | ||
39bbf761 RE |
2962 | return gdbarch; |
2963 | } | |
2964 | ||
97e03143 RE |
2965 | static void |
2966 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2967 | { | |
2968 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2969 | ||
2970 | if (tdep == NULL) | |
2971 | return; | |
2972 | ||
97e03143 RE |
2973 | fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx", |
2974 | (unsigned long) tdep->lowest_pc); | |
2975 | } | |
2976 | ||
2977 | static void | |
2978 | arm_init_abi_eabi_v1 (struct gdbarch_info info, | |
2979 | struct gdbarch *gdbarch) | |
2980 | { | |
2981 | /* Place-holder. */ | |
2982 | } | |
2983 | ||
2984 | static void | |
2985 | arm_init_abi_eabi_v2 (struct gdbarch_info info, | |
2986 | struct gdbarch *gdbarch) | |
2987 | { | |
2988 | /* Place-holder. */ | |
2989 | } | |
2990 | ||
2991 | static void | |
2992 | arm_init_abi_apcs (struct gdbarch_info info, | |
2993 | struct gdbarch *gdbarch) | |
2994 | { | |
2995 | /* Place-holder. */ | |
2996 | } | |
2997 | ||
c906108c | 2998 | void |
ed9a39eb | 2999 | _initialize_arm_tdep (void) |
c906108c | 3000 | { |
bc90b915 FN |
3001 | struct ui_file *stb; |
3002 | long length; | |
96baa820 | 3003 | struct cmd_list_element *new_cmd; |
53904c9e AC |
3004 | const char *setname; |
3005 | const char *setdesc; | |
3006 | const char **regnames; | |
bc90b915 FN |
3007 | int numregs, i, j; |
3008 | static char *helptext; | |
085dd6e6 | 3009 | |
39bbf761 | 3010 | if (GDB_MULTI_ARCH) |
97e03143 RE |
3011 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
3012 | ||
70f80edf JT |
3013 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3014 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3015 | bfd_target_elf_flavour, | |
3016 | arm_elf_osabi_sniffer); | |
3017 | ||
97e03143 | 3018 | /* Register some ABI variants for embedded systems. */ |
05816f70 | 3019 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1, |
70f80edf | 3020 | arm_init_abi_eabi_v1); |
05816f70 | 3021 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2, |
70f80edf | 3022 | arm_init_abi_eabi_v2); |
05816f70 | 3023 | gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS, |
70f80edf | 3024 | arm_init_abi_apcs); |
39bbf761 | 3025 | |
c906108c | 3026 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 3027 | |
94c30b78 | 3028 | /* Get the number of possible sets of register names defined in opcodes. */ |
bc90b915 FN |
3029 | num_flavor_options = get_arm_regname_num_options (); |
3030 | ||
94c30b78 | 3031 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3032 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3033 | |
94c30b78 | 3034 | /* Begin creating the help text. */ |
bc90b915 FN |
3035 | stb = mem_fileopen (); |
3036 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
3037 | The valid values are:\n"); | |
ed9a39eb | 3038 | |
94c30b78 | 3039 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
bc90b915 FN |
3040 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); |
3041 | for (i = 0; i < num_flavor_options; i++) | |
3042 | { | |
3043 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 3044 | valid_flavors[i] = setname; |
bc90b915 FN |
3045 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
3046 | setdesc); | |
94c30b78 | 3047 | /* Copy the default names (if found) and synchronize disassembler. */ |
bc90b915 FN |
3048 | if (!strcmp (setname, "std")) |
3049 | { | |
53904c9e | 3050 | disassembly_flavor = setname; |
bc90b915 FN |
3051 | current_option = i; |
3052 | for (j = 0; j < numregs; j++) | |
3053 | arm_register_names[j] = (char *) regnames[j]; | |
3054 | set_arm_regname_option (i); | |
3055 | } | |
3056 | } | |
94c30b78 | 3057 | /* Mark the end of valid options. */ |
bc90b915 | 3058 | valid_flavors[num_flavor_options] = NULL; |
c906108c | 3059 | |
94c30b78 | 3060 | /* Finish the creation of the help text. */ |
bc90b915 FN |
3061 | fprintf_unfiltered (stb, "The default is \"std\"."); |
3062 | helptext = ui_file_xstrdup (stb, &length); | |
3063 | ui_file_delete (stb); | |
ed9a39eb | 3064 | |
94c30b78 | 3065 | /* Add the disassembly-flavor command. */ |
96baa820 | 3066 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 3067 | valid_flavors, |
1ed2a135 | 3068 | &disassembly_flavor, |
bc90b915 | 3069 | helptext, |
ed9a39eb | 3070 | &setlist); |
9f60d481 | 3071 | set_cmd_sfunc (new_cmd, set_disassembly_flavor_sfunc); |
ed9a39eb JM |
3072 | add_show_from_set (new_cmd, &showlist); |
3073 | ||
c906108c SS |
3074 | /* ??? Maybe this should be a boolean. */ |
3075 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 3076 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 3077 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 3078 | &showlist); |
c906108c | 3079 | |
94c30b78 | 3080 | /* Add the deprecated "othernames" command. */ |
bc90b915 FN |
3081 | |
3082 | add_com ("othernames", class_obscure, arm_othernames, | |
3083 | "Switch to the next set of register names."); | |
c3b4394c | 3084 | |
6529d2dd AC |
3085 | /* Debugging flag. */ |
3086 | add_show_from_set (add_set_cmd ("arm", class_maintenance, var_zinteger, | |
3087 | &arm_debug, "Set arm debugging.\n\ | |
3088 | When non-zero, arm specific debugging is enabled.", &setdebuglist), | |
3089 | &showdebuglist); | |
c906108c | 3090 | } |