Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
0fd88904 | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
9b254dd1 DJ |
4 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
5 | Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 21 | |
34e8f22d RE |
22 | #include <ctype.h> /* XXX for isupper () */ |
23 | ||
c906108c SS |
24 | #include "defs.h" |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "gdbcmd.h" | |
28 | #include "gdbcore.h" | |
c906108c | 29 | #include "gdb_string.h" |
afd7eef0 | 30 | #include "dis-asm.h" /* For register styles. */ |
4e052eda | 31 | #include "regcache.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
34e8f22d | 34 | #include "arch-utils.h" |
4be87837 | 35 | #include "osabi.h" |
eb5492fa DJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
38 | #include "trad-frame.h" | |
842e1f1e DJ |
39 | #include "objfiles.h" |
40 | #include "dwarf2-frame.h" | |
e4c16157 | 41 | #include "gdbtypes.h" |
29d73ae4 | 42 | #include "prologue-value.h" |
123dc839 DJ |
43 | #include "target-descriptions.h" |
44 | #include "user-regs.h" | |
34e8f22d RE |
45 | |
46 | #include "arm-tdep.h" | |
26216b98 | 47 | #include "gdb/sim-arm.h" |
34e8f22d | 48 | |
082fc60d RE |
49 | #include "elf-bfd.h" |
50 | #include "coff/internal.h" | |
97e03143 | 51 | #include "elf/arm.h" |
c906108c | 52 | |
26216b98 AC |
53 | #include "gdb_assert.h" |
54 | ||
6529d2dd AC |
55 | static int arm_debug; |
56 | ||
082fc60d RE |
57 | /* Macros for setting and testing a bit in a minimal symbol that marks |
58 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
f594e5e9 | 59 | is used for this purpose. |
082fc60d RE |
60 | |
61 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
f594e5e9 | 62 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
082fc60d RE |
63 | |
64 | #define MSYMBOL_SET_SPECIAL(msym) \ | |
65 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ | |
66 | | 0x80000000) | |
67 | ||
68 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
69 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
70 | ||
afd7eef0 RE |
71 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
72 | static struct cmd_list_element *setarmcmdlist = NULL; | |
73 | static struct cmd_list_element *showarmcmdlist = NULL; | |
74 | ||
fd50bc42 RE |
75 | /* The type of floating-point to use. Keep this in sync with enum |
76 | arm_float_model, and the help string in _initialize_arm_tdep. */ | |
77 | static const char *fp_model_strings[] = | |
78 | { | |
79 | "auto", | |
80 | "softfpa", | |
81 | "fpa", | |
82 | "softvfp", | |
28e97307 DJ |
83 | "vfp", |
84 | NULL | |
fd50bc42 RE |
85 | }; |
86 | ||
87 | /* A variable that can be configured by the user. */ | |
88 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; | |
89 | static const char *current_fp_model = "auto"; | |
90 | ||
28e97307 DJ |
91 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
92 | static const char *arm_abi_strings[] = | |
93 | { | |
94 | "auto", | |
95 | "APCS", | |
96 | "AAPCS", | |
97 | NULL | |
98 | }; | |
99 | ||
100 | /* A variable that can be configured by the user. */ | |
101 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; | |
102 | static const char *arm_abi_string = "auto"; | |
103 | ||
0428b8f5 DJ |
104 | /* The execution mode to assume. */ |
105 | static const char *arm_mode_strings[] = | |
106 | { | |
107 | "auto", | |
108 | "arm", | |
109 | "thumb" | |
110 | }; | |
111 | ||
112 | static const char *arm_fallback_mode_string = "auto"; | |
113 | static const char *arm_force_mode_string = "auto"; | |
114 | ||
94c30b78 | 115 | /* Number of different reg name sets (options). */ |
afd7eef0 | 116 | static int num_disassembly_options; |
bc90b915 | 117 | |
123dc839 DJ |
118 | /* The standard register names, and all the valid aliases for them. */ |
119 | static const struct | |
120 | { | |
121 | const char *name; | |
122 | int regnum; | |
123 | } arm_register_aliases[] = { | |
124 | /* Basic register numbers. */ | |
125 | { "r0", 0 }, | |
126 | { "r1", 1 }, | |
127 | { "r2", 2 }, | |
128 | { "r3", 3 }, | |
129 | { "r4", 4 }, | |
130 | { "r5", 5 }, | |
131 | { "r6", 6 }, | |
132 | { "r7", 7 }, | |
133 | { "r8", 8 }, | |
134 | { "r9", 9 }, | |
135 | { "r10", 10 }, | |
136 | { "r11", 11 }, | |
137 | { "r12", 12 }, | |
138 | { "r13", 13 }, | |
139 | { "r14", 14 }, | |
140 | { "r15", 15 }, | |
141 | /* Synonyms (argument and variable registers). */ | |
142 | { "a1", 0 }, | |
143 | { "a2", 1 }, | |
144 | { "a3", 2 }, | |
145 | { "a4", 3 }, | |
146 | { "v1", 4 }, | |
147 | { "v2", 5 }, | |
148 | { "v3", 6 }, | |
149 | { "v4", 7 }, | |
150 | { "v5", 8 }, | |
151 | { "v6", 9 }, | |
152 | { "v7", 10 }, | |
153 | { "v8", 11 }, | |
154 | /* Other platform-specific names for r9. */ | |
155 | { "sb", 9 }, | |
156 | { "tr", 9 }, | |
157 | /* Special names. */ | |
158 | { "ip", 12 }, | |
159 | { "sp", 13 }, | |
160 | { "lr", 14 }, | |
161 | { "pc", 15 }, | |
162 | /* Names used by GCC (not listed in the ARM EABI). */ | |
163 | { "sl", 10 }, | |
164 | { "fp", 11 }, | |
165 | /* A special name from the older ATPCS. */ | |
166 | { "wr", 7 }, | |
167 | }; | |
bc90b915 | 168 | |
123dc839 | 169 | static const char *const arm_register_names[] = |
da59e081 JM |
170 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
171 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
172 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
173 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
174 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
175 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
94c30b78 | 176 | "fps", "cpsr" }; /* 24 25 */ |
ed9a39eb | 177 | |
afd7eef0 RE |
178 | /* Valid register name styles. */ |
179 | static const char **valid_disassembly_styles; | |
ed9a39eb | 180 | |
afd7eef0 RE |
181 | /* Disassembly style to use. Default to "std" register names. */ |
182 | static const char *disassembly_style; | |
96baa820 | 183 | |
ed9a39eb | 184 | /* This is used to keep the bfd arch_info in sync with the disassembly |
afd7eef0 RE |
185 | style. */ |
186 | static void set_disassembly_style_sfunc(char *, int, | |
ed9a39eb | 187 | struct cmd_list_element *); |
afd7eef0 | 188 | static void set_disassembly_style (void); |
ed9a39eb | 189 | |
b508a996 | 190 | static void convert_from_extended (const struct floatformat *, const void *, |
be8626e0 | 191 | void *, int); |
b508a996 | 192 | static void convert_to_extended (const struct floatformat *, void *, |
be8626e0 | 193 | const void *, int); |
ed9a39eb | 194 | |
9b8d791a | 195 | struct arm_prologue_cache |
c3b4394c | 196 | { |
eb5492fa DJ |
197 | /* The stack pointer at the time this frame was created; i.e. the |
198 | caller's stack pointer when this function was called. It is used | |
199 | to identify this frame. */ | |
200 | CORE_ADDR prev_sp; | |
201 | ||
4be43953 DJ |
202 | /* The frame base for this frame is just prev_sp - frame size. |
203 | FRAMESIZE is the distance from the frame pointer to the | |
204 | initial stack pointer. */ | |
eb5492fa | 205 | |
c3b4394c | 206 | int framesize; |
eb5492fa DJ |
207 | |
208 | /* The register used to hold the frame pointer for this frame. */ | |
c3b4394c | 209 | int framereg; |
eb5492fa DJ |
210 | |
211 | /* Saved register offsets. */ | |
212 | struct trad_frame_saved_reg *saved_regs; | |
c3b4394c | 213 | }; |
ed9a39eb | 214 | |
bc90b915 FN |
215 | /* Addresses for calling Thumb functions have the bit 0 set. |
216 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
217 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
218 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
219 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
220 | ||
94c30b78 | 221 | /* Set to true if the 32-bit mode is in use. */ |
c906108c SS |
222 | |
223 | int arm_apcs_32 = 1; | |
224 | ||
b39cc962 DJ |
225 | /* Determine if FRAME is executing in Thumb mode. */ |
226 | ||
227 | static int | |
228 | arm_frame_is_thumb (struct frame_info *frame) | |
229 | { | |
230 | CORE_ADDR cpsr; | |
231 | ||
232 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either | |
233 | directly (from a signal frame or dummy frame) or by interpreting | |
234 | the saved LR (from a prologue or DWARF frame). So consult it and | |
235 | trust the unwinders. */ | |
236 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); | |
237 | ||
238 | return (cpsr & CPSR_T) != 0; | |
239 | } | |
240 | ||
ed9a39eb | 241 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
b39cc962 DJ |
242 | function. This function should be called for addresses unrelated to |
243 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ | |
c906108c | 244 | |
ad527d2e | 245 | static int |
2a451106 | 246 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 247 | { |
c5aa993b | 248 | struct minimal_symbol *sym; |
c906108c | 249 | |
ed9a39eb | 250 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
251 | if (IS_THUMB_ADDR (memaddr)) |
252 | return 1; | |
253 | ||
0428b8f5 DJ |
254 | /* If the user wants to override the symbol table, let him. */ |
255 | if (strcmp (arm_force_mode_string, "arm") == 0) | |
256 | return 0; | |
257 | if (strcmp (arm_force_mode_string, "thumb") == 0) | |
258 | return 1; | |
259 | ||
ed9a39eb | 260 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
261 | sym = lookup_minimal_symbol_by_pc (memaddr); |
262 | if (sym) | |
0428b8f5 DJ |
263 | return (MSYMBOL_IS_SPECIAL (sym)); |
264 | ||
265 | /* If the user wants to override the fallback mode, let them. */ | |
266 | if (strcmp (arm_fallback_mode_string, "arm") == 0) | |
267 | return 0; | |
268 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) | |
269 | return 1; | |
270 | ||
271 | /* If we couldn't find any symbol, but we're talking to a running | |
272 | target, then trust the current value of $cpsr. This lets | |
273 | "display/i $pc" always show the correct mode (though if there is | |
274 | a symbol table we will not reach here, so it still may not be | |
275 | displayed in the mode it will be executed). */ | |
276 | if (target_has_registers) | |
277 | return arm_frame_is_thumb (get_current_frame ()); | |
278 | ||
279 | /* Otherwise we're out of luck; we assume ARM. */ | |
280 | return 0; | |
c906108c SS |
281 | } |
282 | ||
181c1381 | 283 | /* Remove useless bits from addresses in a running program. */ |
34e8f22d | 284 | static CORE_ADDR |
ed9a39eb | 285 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c | 286 | { |
a3a2ee65 | 287 | if (arm_apcs_32) |
dd6be234 | 288 | return UNMAKE_THUMB_ADDR (val); |
c906108c | 289 | else |
a3a2ee65 | 290 | return (val & 0x03fffffc); |
c906108c SS |
291 | } |
292 | ||
181c1381 RE |
293 | /* When reading symbols, we need to zap the low bit of the address, |
294 | which may be set to 1 for Thumb functions. */ | |
34e8f22d | 295 | static CORE_ADDR |
181c1381 RE |
296 | arm_smash_text_address (CORE_ADDR val) |
297 | { | |
298 | return val & ~1; | |
299 | } | |
300 | ||
29d73ae4 DJ |
301 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
302 | and frame pointer. Scan until we encounter a store that could | |
303 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
c906108c SS |
304 | |
305 | static CORE_ADDR | |
29d73ae4 DJ |
306 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
307 | CORE_ADDR start, CORE_ADDR limit, | |
308 | struct arm_prologue_cache *cache) | |
c906108c | 309 | { |
29d73ae4 DJ |
310 | int i; |
311 | pv_t regs[16]; | |
312 | struct pv_area *stack; | |
313 | struct cleanup *back_to; | |
314 | CORE_ADDR offset; | |
da3c6d4a | 315 | |
29d73ae4 DJ |
316 | for (i = 0; i < 16; i++) |
317 | regs[i] = pv_register (i, 0); | |
318 | stack = make_pv_area (ARM_SP_REGNUM); | |
319 | back_to = make_cleanup_free_pv_area (stack); | |
320 | ||
29d73ae4 | 321 | while (start < limit) |
c906108c | 322 | { |
29d73ae4 DJ |
323 | unsigned short insn; |
324 | ||
325 | insn = read_memory_unsigned_integer (start, 2); | |
c906108c | 326 | |
94c30b78 | 327 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
da59e081 | 328 | { |
29d73ae4 DJ |
329 | int regno; |
330 | int mask; | |
4be43953 DJ |
331 | |
332 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) | |
333 | break; | |
29d73ae4 DJ |
334 | |
335 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
336 | whether to save LR (R14). */ | |
337 | mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
338 | ||
339 | /* Calculate offsets of saved R0-R7 and LR. */ | |
340 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) | |
341 | if (mask & (1 << regno)) | |
342 | { | |
29d73ae4 DJ |
343 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
344 | -4); | |
345 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
346 | } | |
da59e081 | 347 | } |
da3c6d4a MS |
348 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
349 | sub sp, #simm */ | |
da59e081 | 350 | { |
29d73ae4 DJ |
351 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
352 | if (insn & 0x80) /* Check for SUB. */ | |
353 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], | |
354 | -offset); | |
da59e081 | 355 | else |
29d73ae4 DJ |
356 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
357 | offset); | |
da59e081 JM |
358 | } |
359 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
29d73ae4 DJ |
360 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
361 | (insn & 0xff) << 2); | |
362 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ | |
da59e081 | 363 | { |
29d73ae4 DJ |
364 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
365 | int src_reg = (insn & 0x78) >> 3; | |
366 | regs[dst_reg] = regs[src_reg]; | |
da59e081 | 367 | } |
29d73ae4 | 368 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
da59e081 | 369 | { |
29d73ae4 DJ |
370 | /* Handle stores to the stack. Normally pushes are used, |
371 | but with GCC -mtpcs-frame, there may be other stores | |
372 | in the prologue to create the frame. */ | |
373 | int regno = (insn >> 8) & 0x7; | |
374 | pv_t addr; | |
375 | ||
376 | offset = (insn & 0xff) << 2; | |
377 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); | |
378 | ||
379 | if (pv_area_store_would_trash (stack, addr)) | |
380 | break; | |
381 | ||
382 | pv_area_store (stack, addr, 4, regs[regno]); | |
da59e081 | 383 | } |
29d73ae4 | 384 | else |
3d74b771 | 385 | { |
29d73ae4 DJ |
386 | /* We don't know what this instruction is. We're finished |
387 | scanning. NOTE: Recognizing more safe-to-ignore | |
388 | instructions here will improve support for optimized | |
389 | code. */ | |
da3c6d4a | 390 | break; |
3d74b771 | 391 | } |
29d73ae4 DJ |
392 | |
393 | start += 2; | |
c906108c SS |
394 | } |
395 | ||
29d73ae4 DJ |
396 | if (cache == NULL) |
397 | { | |
398 | do_cleanups (back_to); | |
399 | return start; | |
400 | } | |
401 | ||
29d73ae4 DJ |
402 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
403 | { | |
404 | /* Frame pointer is fp. Frame size is constant. */ | |
405 | cache->framereg = ARM_FP_REGNUM; | |
406 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
407 | } | |
408 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) | |
409 | { | |
410 | /* Frame pointer is r7. Frame size is constant. */ | |
411 | cache->framereg = THUMB_FP_REGNUM; | |
412 | cache->framesize = -regs[THUMB_FP_REGNUM].k; | |
413 | } | |
414 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
415 | { | |
416 | /* Try the stack pointer... this is a bit desperate. */ | |
417 | cache->framereg = ARM_SP_REGNUM; | |
418 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
419 | } | |
420 | else | |
421 | { | |
422 | /* We're just out of luck. We don't know where the frame is. */ | |
423 | cache->framereg = -1; | |
424 | cache->framesize = 0; | |
425 | } | |
426 | ||
427 | for (i = 0; i < 16; i++) | |
428 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) | |
429 | cache->saved_regs[i].addr = offset; | |
430 | ||
431 | do_cleanups (back_to); | |
432 | return start; | |
c906108c SS |
433 | } |
434 | ||
da3c6d4a MS |
435 | /* Advance the PC across any function entry prologue instructions to |
436 | reach some "real" code. | |
34e8f22d RE |
437 | |
438 | The APCS (ARM Procedure Call Standard) defines the following | |
ed9a39eb | 439 | prologue: |
c906108c | 440 | |
c5aa993b JM |
441 | mov ip, sp |
442 | [stmfd sp!, {a1,a2,a3,a4}] | |
443 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
444 | [stfe f7, [sp, #-12]!] |
445 | [stfe f6, [sp, #-12]!] | |
446 | [stfe f5, [sp, #-12]!] | |
447 | [stfe f4, [sp, #-12]!] | |
448 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c | 449 | |
34e8f22d | 450 | static CORE_ADDR |
6093d2eb | 451 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c SS |
452 | { |
453 | unsigned long inst; | |
454 | CORE_ADDR skip_pc; | |
b8d5e71d | 455 | CORE_ADDR func_addr, func_end = 0; |
50f6fb4b | 456 | char *func_name; |
c906108c SS |
457 | struct symtab_and_line sal; |
458 | ||
848cfffb | 459 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
30a4a8e0 | 460 | if (deprecated_pc_in_call_dummy (pc)) |
848cfffb AC |
461 | return pc; |
462 | ||
96baa820 | 463 | /* See what the symbol table says. */ |
ed9a39eb | 464 | |
50f6fb4b | 465 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 466 | { |
50f6fb4b CV |
467 | struct symbol *sym; |
468 | ||
469 | /* Found a function. */ | |
176620f1 | 470 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
50f6fb4b CV |
471 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
472 | { | |
94c30b78 | 473 | /* Don't use this trick for assembly source files. */ |
50f6fb4b CV |
474 | sal = find_pc_line (func_addr, 0); |
475 | if ((sal.line != 0) && (sal.end < func_end)) | |
476 | return sal.end; | |
477 | } | |
c906108c SS |
478 | } |
479 | ||
c906108c | 480 | /* Can't find the prologue end in the symbol table, try it the hard way |
94c30b78 | 481 | by disassembling the instructions. */ |
c906108c | 482 | |
b8d5e71d MS |
483 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
484 | if (func_end == 0 || func_end > pc + 64) | |
485 | func_end = pc + 64; | |
c906108c | 486 | |
29d73ae4 DJ |
487 | /* Check if this is Thumb code. */ |
488 | if (arm_pc_is_thumb (pc)) | |
6093d2eb | 489 | return thumb_analyze_prologue (gdbarch, pc, func_end, NULL); |
29d73ae4 | 490 | |
b8d5e71d | 491 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
f43845b3 | 492 | { |
1c5bada0 | 493 | inst = read_memory_unsigned_integer (skip_pc, 4); |
f43845b3 | 494 | |
b8d5e71d MS |
495 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
496 | if (inst == 0xe1a0c00d) /* mov ip, sp */ | |
497 | continue; | |
c906108c | 498 | |
28cd8767 JG |
499 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
500 | continue; | |
501 | ||
502 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
503 | continue; | |
504 | ||
b8d5e71d MS |
505 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
506 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ | |
507 | continue; | |
c906108c | 508 | |
b8d5e71d MS |
509 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
510 | continue; | |
c906108c | 511 | |
b8d5e71d MS |
512 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
513 | continue; | |
11d3b27d | 514 | |
b8d5e71d MS |
515 | /* Any insns after this point may float into the code, if it makes |
516 | for better instruction scheduling, so we skip them only if we | |
517 | find them, but still consider the function to be frame-ful. */ | |
f43845b3 | 518 | |
b8d5e71d MS |
519 | /* We may have either one sfmfd instruction here, or several stfe |
520 | insns, depending on the version of floating point code we | |
521 | support. */ | |
522 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ | |
523 | continue; | |
524 | ||
525 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ | |
526 | continue; | |
527 | ||
528 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ | |
529 | continue; | |
530 | ||
531 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ | |
532 | continue; | |
533 | ||
534 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ | |
535 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ | |
536 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ | |
537 | continue; | |
538 | ||
539 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ | |
540 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ | |
541 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ | |
542 | continue; | |
543 | ||
544 | /* Un-recognized instruction; stop scanning. */ | |
545 | break; | |
f43845b3 | 546 | } |
c906108c | 547 | |
b8d5e71d | 548 | return skip_pc; /* End of prologue */ |
c906108c | 549 | } |
94c30b78 | 550 | |
c5aa993b | 551 | /* *INDENT-OFF* */ |
c906108c SS |
552 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
553 | This function decodes a Thumb function prologue to determine: | |
554 | 1) the size of the stack frame | |
555 | 2) which registers are saved on it | |
556 | 3) the offsets of saved regs | |
557 | 4) the offset from the stack pointer to the frame pointer | |
c906108c | 558 | |
da59e081 JM |
559 | A typical Thumb function prologue would create this stack frame |
560 | (offsets relative to FP) | |
c906108c SS |
561 | old SP -> 24 stack parameters |
562 | 20 LR | |
563 | 16 R7 | |
564 | R7 -> 0 local variables (16 bytes) | |
565 | SP -> -12 additional stack space (12 bytes) | |
566 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
567 | 12 bytes. The frame register is R7. |
568 | ||
da3c6d4a MS |
569 | The comments for thumb_skip_prolog() describe the algorithm we use |
570 | to detect the end of the prolog. */ | |
c5aa993b JM |
571 | /* *INDENT-ON* */ |
572 | ||
c906108c | 573 | static void |
be8626e0 | 574 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
b39cc962 | 575 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
c906108c SS |
576 | { |
577 | CORE_ADDR prologue_start; | |
578 | CORE_ADDR prologue_end; | |
579 | CORE_ADDR current_pc; | |
c906108c | 580 | |
b39cc962 DJ |
581 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
582 | &prologue_end)) | |
c906108c SS |
583 | { |
584 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
585 | ||
94c30b78 | 586 | if (sal.line == 0) /* no line info, use current PC */ |
eb5492fa | 587 | prologue_end = prev_pc; |
c906108c | 588 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
94c30b78 | 589 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
590 | } |
591 | else | |
f7060f85 DJ |
592 | /* We're in the boondocks: we have no idea where the start of the |
593 | function is. */ | |
594 | return; | |
c906108c | 595 | |
eb5492fa | 596 | prologue_end = min (prologue_end, prev_pc); |
c906108c | 597 | |
be8626e0 | 598 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
c906108c SS |
599 | } |
600 | ||
ed9a39eb | 601 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
602 | 1) the size of the stack frame |
603 | 2) which registers are saved on it | |
604 | 3) the offsets of saved regs | |
605 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
606 | This information is stored in the "extra" fields of the frame_info. |
607 | ||
96baa820 JM |
608 | There are two basic forms for the ARM prologue. The fixed argument |
609 | function call will look like: | |
ed9a39eb JM |
610 | |
611 | mov ip, sp | |
612 | stmfd sp!, {fp, ip, lr, pc} | |
613 | sub fp, ip, #4 | |
614 | [sub sp, sp, #4] | |
96baa820 | 615 | |
c906108c | 616 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
617 | IP -> 4 (caller's stack) |
618 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
619 | -4 LR (return address in caller) | |
620 | -8 IP (copy of caller's SP) | |
621 | -12 FP (caller's FP) | |
622 | SP -> -28 Local variables | |
623 | ||
c906108c | 624 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
625 | 28 bytes. The stmfd call can also save any of the vN registers it |
626 | plans to use, which increases the frame size accordingly. | |
627 | ||
628 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
629 | because the ARM Store instructions always store PC + 8 when you read | |
630 | the PC register. | |
ed9a39eb | 631 | |
96baa820 JM |
632 | A variable argument function call will look like: |
633 | ||
ed9a39eb JM |
634 | mov ip, sp |
635 | stmfd sp!, {a1, a2, a3, a4} | |
636 | stmfd sp!, {fp, ip, lr, pc} | |
637 | sub fp, ip, #20 | |
638 | ||
96baa820 | 639 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
640 | IP -> 20 (caller's stack) |
641 | 16 A4 | |
642 | 12 A3 | |
643 | 8 A2 | |
644 | 4 A1 | |
645 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
646 | -4 LR (return address in caller) | |
647 | -8 IP (copy of caller's SP) | |
648 | -12 FP (caller's FP) | |
649 | SP -> -28 Local variables | |
96baa820 JM |
650 | |
651 | The frame size would thus be 48 bytes, and the frame offset would be | |
652 | 28 bytes. | |
653 | ||
654 | There is another potential complication, which is that the optimizer | |
655 | will try to separate the store of fp in the "stmfd" instruction from | |
656 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
657 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
658 | ||
659 | Also, note, the original version of the ARM toolchain claimed that there | |
660 | should be an | |
661 | ||
662 | instruction at the end of the prologue. I have never seen GCC produce | |
663 | this, and the ARM docs don't mention it. We still test for it below in | |
664 | case it happens... | |
ed9a39eb JM |
665 | |
666 | */ | |
c906108c SS |
667 | |
668 | static void | |
a262aec2 | 669 | arm_scan_prologue (struct frame_info *this_frame, |
2af46ca0 | 670 | struct arm_prologue_cache *cache) |
c906108c | 671 | { |
a262aec2 | 672 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
4be43953 | 673 | int regno; |
c906108c | 674 | CORE_ADDR prologue_start, prologue_end, current_pc; |
a262aec2 | 675 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
b39cc962 | 676 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); |
4be43953 DJ |
677 | pv_t regs[ARM_FPS_REGNUM]; |
678 | struct pv_area *stack; | |
679 | struct cleanup *back_to; | |
680 | CORE_ADDR offset; | |
c906108c | 681 | |
c906108c | 682 | /* Assume there is no frame until proven otherwise. */ |
9b8d791a DJ |
683 | cache->framereg = ARM_SP_REGNUM; |
684 | cache->framesize = 0; | |
c906108c SS |
685 | |
686 | /* Check for Thumb prologue. */ | |
b39cc962 | 687 | if (arm_frame_is_thumb (this_frame)) |
c906108c | 688 | { |
b39cc962 | 689 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); |
c906108c SS |
690 | return; |
691 | } | |
692 | ||
693 | /* Find the function prologue. If we can't find the function in | |
694 | the symbol table, peek in the stack frame to find the PC. */ | |
b39cc962 DJ |
695 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
696 | &prologue_end)) | |
c906108c | 697 | { |
2a451106 KB |
698 | /* One way to find the end of the prologue (which works well |
699 | for unoptimized code) is to do the following: | |
700 | ||
701 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
702 | ||
703 | if (sal.line == 0) | |
eb5492fa | 704 | prologue_end = prev_pc; |
2a451106 KB |
705 | else if (sal.end < prologue_end) |
706 | prologue_end = sal.end; | |
707 | ||
708 | This mechanism is very accurate so long as the optimizer | |
709 | doesn't move any instructions from the function body into the | |
710 | prologue. If this happens, sal.end will be the last | |
711 | instruction in the first hunk of prologue code just before | |
712 | the first instruction that the scheduler has moved from | |
713 | the body to the prologue. | |
714 | ||
715 | In order to make sure that we scan all of the prologue | |
716 | instructions, we use a slightly less accurate mechanism which | |
717 | may scan more than necessary. To help compensate for this | |
718 | lack of accuracy, the prologue scanning loop below contains | |
719 | several clauses which'll cause the loop to terminate early if | |
720 | an implausible prologue instruction is encountered. | |
721 | ||
722 | The expression | |
723 | ||
724 | prologue_start + 64 | |
725 | ||
726 | is a suitable endpoint since it accounts for the largest | |
727 | possible prologue plus up to five instructions inserted by | |
94c30b78 | 728 | the scheduler. */ |
2a451106 KB |
729 | |
730 | if (prologue_end > prologue_start + 64) | |
731 | { | |
94c30b78 | 732 | prologue_end = prologue_start + 64; /* See above. */ |
2a451106 | 733 | } |
c906108c SS |
734 | } |
735 | else | |
736 | { | |
eb5492fa DJ |
737 | /* We have no symbol information. Our only option is to assume this |
738 | function has a standard stack frame and the normal frame register. | |
739 | Then, we can find the value of our frame pointer on entrance to | |
740 | the callee (or at the present moment if this is the innermost frame). | |
741 | The value stored there should be the address of the stmfd + 8. */ | |
742 | CORE_ADDR frame_loc; | |
743 | LONGEST return_value; | |
744 | ||
a262aec2 | 745 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
eb5492fa | 746 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) |
16a0f3e7 EZ |
747 | return; |
748 | else | |
749 | { | |
bf6ae464 | 750 | prologue_start = gdbarch_addr_bits_remove |
2af46ca0 | 751 | (gdbarch, return_value) - 8; |
94c30b78 | 752 | prologue_end = prologue_start + 64; /* See above. */ |
16a0f3e7 | 753 | } |
c906108c SS |
754 | } |
755 | ||
eb5492fa DJ |
756 | if (prev_pc < prologue_end) |
757 | prologue_end = prev_pc; | |
758 | ||
c906108c | 759 | /* Now search the prologue looking for instructions that set up the |
96baa820 | 760 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 761 | |
96baa820 JM |
762 | Be careful, however, and if it doesn't look like a prologue, |
763 | don't try to scan it. If, for instance, a frameless function | |
764 | begins with stmfd sp!, then we will tell ourselves there is | |
b8d5e71d | 765 | a frame, which will confuse stack traceback, as well as "finish" |
96baa820 JM |
766 | and other operations that rely on a knowledge of the stack |
767 | traceback. | |
768 | ||
769 | In the APCS, the prologue should start with "mov ip, sp" so | |
f43845b3 | 770 | if we don't see this as the first insn, we will stop. |
c906108c | 771 | |
f43845b3 MS |
772 | [Note: This doesn't seem to be true any longer, so it's now an |
773 | optional part of the prologue. - Kevin Buettner, 2001-11-20] | |
c906108c | 774 | |
f43845b3 MS |
775 | [Note further: The "mov ip,sp" only seems to be missing in |
776 | frameless functions at optimization level "-O2" or above, | |
777 | in which case it is often (but not always) replaced by | |
b8d5e71d | 778 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
d4473757 | 779 | |
4be43953 DJ |
780 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
781 | regs[regno] = pv_register (regno, 0); | |
782 | stack = make_pv_area (ARM_SP_REGNUM); | |
783 | back_to = make_cleanup_free_pv_area (stack); | |
784 | ||
94c30b78 MS |
785 | for (current_pc = prologue_start; |
786 | current_pc < prologue_end; | |
f43845b3 | 787 | current_pc += 4) |
96baa820 | 788 | { |
d4473757 KB |
789 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
790 | ||
94c30b78 | 791 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
f43845b3 | 792 | { |
4be43953 | 793 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
28cd8767 JG |
794 | continue; |
795 | } | |
796 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ | |
797 | { | |
798 | unsigned imm = insn & 0xff; /* immediate value */ | |
799 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
800 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 801 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm); |
28cd8767 JG |
802 | continue; |
803 | } | |
804 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ | |
805 | { | |
806 | unsigned imm = insn & 0xff; /* immediate value */ | |
807 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
808 | imm = (imm >> rot) | (imm << (32 - rot)); | |
4be43953 | 809 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
f43845b3 MS |
810 | continue; |
811 | } | |
94c30b78 | 812 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
f43845b3 | 813 | { |
4be43953 DJ |
814 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
815 | break; | |
816 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); | |
817 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]); | |
f43845b3 MS |
818 | continue; |
819 | } | |
820 | else if ((insn & 0xffff0000) == 0xe92d0000) | |
d4473757 KB |
821 | /* stmfd sp!, {..., fp, ip, lr, pc} |
822 | or | |
823 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 824 | { |
d4473757 | 825 | int mask = insn & 0xffff; |
ed9a39eb | 826 | |
4be43953 DJ |
827 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
828 | break; | |
829 | ||
94c30b78 | 830 | /* Calculate offsets of saved registers. */ |
34e8f22d | 831 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
d4473757 KB |
832 | if (mask & (1 << regno)) |
833 | { | |
4be43953 DJ |
834 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
835 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); | |
d4473757 KB |
836 | } |
837 | } | |
b8d5e71d MS |
838 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
839 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ | |
840 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ | |
841 | { | |
842 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
843 | continue; | |
844 | } | |
845 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ | |
846 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ | |
847 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ | |
f43845b3 MS |
848 | { |
849 | /* No need to add this to saved_regs -- it's just an arg reg. */ | |
850 | continue; | |
851 | } | |
d4473757 KB |
852 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
853 | { | |
94c30b78 MS |
854 | unsigned imm = insn & 0xff; /* immediate value */ |
855 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 856 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 857 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
d4473757 KB |
858 | } |
859 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
860 | { | |
94c30b78 MS |
861 | unsigned imm = insn & 0xff; /* immediate value */ |
862 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
d4473757 | 863 | imm = (imm >> rot) | (imm << (32 - rot)); |
4be43953 | 864 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
d4473757 | 865 | } |
ff6f572f | 866 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ |
2af46ca0 | 867 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 | 868 | { |
4be43953 DJ |
869 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
870 | break; | |
871 | ||
872 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); | |
34e8f22d | 873 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
4be43953 | 874 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
d4473757 | 875 | } |
ff6f572f | 876 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ |
2af46ca0 | 877 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
d4473757 KB |
878 | { |
879 | int n_saved_fp_regs; | |
880 | unsigned int fp_start_reg, fp_bound_reg; | |
881 | ||
4be43953 DJ |
882 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
883 | break; | |
884 | ||
94c30b78 | 885 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
96baa820 | 886 | { |
d4473757 KB |
887 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
888 | n_saved_fp_regs = 3; | |
889 | else | |
890 | n_saved_fp_regs = 1; | |
96baa820 | 891 | } |
d4473757 | 892 | else |
96baa820 | 893 | { |
d4473757 KB |
894 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
895 | n_saved_fp_regs = 2; | |
896 | else | |
897 | n_saved_fp_regs = 4; | |
96baa820 | 898 | } |
d4473757 | 899 | |
34e8f22d | 900 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
d4473757 KB |
901 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
902 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 | 903 | { |
4be43953 DJ |
904 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
905 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, | |
906 | regs[fp_start_reg++]); | |
96baa820 | 907 | } |
c906108c | 908 | } |
d4473757 | 909 | else if ((insn & 0xf0000000) != 0xe0000000) |
94c30b78 | 910 | break; /* Condition not true, exit early */ |
b8d5e71d | 911 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
94c30b78 | 912 | break; /* Don't scan past a block load */ |
d4473757 KB |
913 | else |
914 | /* The optimizer might shove anything into the prologue, | |
94c30b78 | 915 | so we just skip what we don't recognize. */ |
d4473757 | 916 | continue; |
c906108c SS |
917 | } |
918 | ||
4be43953 DJ |
919 | /* The frame size is just the distance from the frame register |
920 | to the original stack pointer. */ | |
921 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) | |
922 | { | |
923 | /* Frame pointer is fp. */ | |
924 | cache->framereg = ARM_FP_REGNUM; | |
925 | cache->framesize = -regs[ARM_FP_REGNUM].k; | |
926 | } | |
927 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) | |
928 | { | |
929 | /* Try the stack pointer... this is a bit desperate. */ | |
930 | cache->framereg = ARM_SP_REGNUM; | |
931 | cache->framesize = -regs[ARM_SP_REGNUM].k; | |
932 | } | |
d4473757 | 933 | else |
4be43953 DJ |
934 | { |
935 | /* We're just out of luck. We don't know where the frame is. */ | |
936 | cache->framereg = -1; | |
937 | cache->framesize = 0; | |
938 | } | |
939 | ||
940 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) | |
941 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) | |
942 | cache->saved_regs[regno].addr = offset; | |
943 | ||
944 | do_cleanups (back_to); | |
c906108c SS |
945 | } |
946 | ||
eb5492fa | 947 | static struct arm_prologue_cache * |
a262aec2 | 948 | arm_make_prologue_cache (struct frame_info *this_frame) |
c906108c | 949 | { |
eb5492fa DJ |
950 | int reg; |
951 | struct arm_prologue_cache *cache; | |
952 | CORE_ADDR unwound_fp; | |
c5aa993b | 953 | |
35d5d4ee | 954 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 955 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c906108c | 956 | |
a262aec2 | 957 | arm_scan_prologue (this_frame, cache); |
848cfffb | 958 | |
a262aec2 | 959 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
eb5492fa DJ |
960 | if (unwound_fp == 0) |
961 | return cache; | |
c906108c | 962 | |
4be43953 | 963 | cache->prev_sp = unwound_fp + cache->framesize; |
c906108c | 964 | |
eb5492fa DJ |
965 | /* Calculate actual addresses of saved registers using offsets |
966 | determined by arm_scan_prologue. */ | |
a262aec2 | 967 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
e28a332c | 968 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
eb5492fa DJ |
969 | cache->saved_regs[reg].addr += cache->prev_sp; |
970 | ||
971 | return cache; | |
c906108c SS |
972 | } |
973 | ||
eb5492fa DJ |
974 | /* Our frame ID for a normal frame is the current function's starting PC |
975 | and the caller's SP when we were called. */ | |
c906108c | 976 | |
148754e5 | 977 | static void |
a262aec2 | 978 | arm_prologue_this_id (struct frame_info *this_frame, |
eb5492fa DJ |
979 | void **this_cache, |
980 | struct frame_id *this_id) | |
c906108c | 981 | { |
eb5492fa DJ |
982 | struct arm_prologue_cache *cache; |
983 | struct frame_id id; | |
2c404490 | 984 | CORE_ADDR pc, func; |
f079148d | 985 | |
eb5492fa | 986 | if (*this_cache == NULL) |
a262aec2 | 987 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 988 | cache = *this_cache; |
2a451106 | 989 | |
2c404490 DJ |
990 | /* This is meant to halt the backtrace at "_start". */ |
991 | pc = get_frame_pc (this_frame); | |
992 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) | |
eb5492fa | 993 | return; |
5a203e44 | 994 | |
eb5492fa DJ |
995 | /* If we've hit a wall, stop. */ |
996 | if (cache->prev_sp == 0) | |
997 | return; | |
24de872b | 998 | |
2c404490 | 999 | func = get_frame_func (this_frame); |
eb5492fa | 1000 | id = frame_id_build (cache->prev_sp, func); |
eb5492fa | 1001 | *this_id = id; |
c906108c SS |
1002 | } |
1003 | ||
a262aec2 DJ |
1004 | static struct value * |
1005 | arm_prologue_prev_register (struct frame_info *this_frame, | |
eb5492fa | 1006 | void **this_cache, |
a262aec2 | 1007 | int prev_regnum) |
24de872b DJ |
1008 | { |
1009 | struct arm_prologue_cache *cache; | |
1010 | ||
eb5492fa | 1011 | if (*this_cache == NULL) |
a262aec2 | 1012 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa | 1013 | cache = *this_cache; |
24de872b | 1014 | |
eb5492fa | 1015 | /* If we are asked to unwind the PC, then we need to return the LR |
b39cc962 DJ |
1016 | instead. The prologue may save PC, but it will point into this |
1017 | frame's prologue, not the next frame's resume location. Also | |
1018 | strip the saved T bit. A valid LR may have the low bit set, but | |
1019 | a valid PC never does. */ | |
eb5492fa | 1020 | if (prev_regnum == ARM_PC_REGNUM) |
b39cc962 DJ |
1021 | { |
1022 | CORE_ADDR lr; | |
1023 | ||
1024 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1025 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
1026 | arm_addr_bits_remove (lr)); | |
1027 | } | |
24de872b | 1028 | |
eb5492fa | 1029 | /* SP is generally not saved to the stack, but this frame is |
a262aec2 | 1030 | identified by the next frame's stack pointer at the time of the call. |
eb5492fa DJ |
1031 | The value was already reconstructed into PREV_SP. */ |
1032 | if (prev_regnum == ARM_SP_REGNUM) | |
a262aec2 | 1033 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
eb5492fa | 1034 | |
b39cc962 DJ |
1035 | /* The CPSR may have been changed by the call instruction and by the |
1036 | called function. The only bit we can reconstruct is the T bit, | |
1037 | by checking the low bit of LR as of the call. This is a reliable | |
1038 | indicator of Thumb-ness except for some ARM v4T pre-interworking | |
1039 | Thumb code, which could get away with a clear low bit as long as | |
1040 | the called function did not use bx. Guess that all other | |
1041 | bits are unchanged; the condition flags are presumably lost, | |
1042 | but the processor status is likely valid. */ | |
1043 | if (prev_regnum == ARM_PS_REGNUM) | |
1044 | { | |
1045 | CORE_ADDR lr, cpsr; | |
1046 | ||
1047 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); | |
1048 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1049 | if (IS_THUMB_ADDR (lr)) | |
1050 | cpsr |= CPSR_T; | |
1051 | else | |
1052 | cpsr &= ~CPSR_T; | |
1053 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); | |
1054 | } | |
1055 | ||
a262aec2 DJ |
1056 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
1057 | prev_regnum); | |
eb5492fa DJ |
1058 | } |
1059 | ||
1060 | struct frame_unwind arm_prologue_unwind = { | |
1061 | NORMAL_FRAME, | |
1062 | arm_prologue_this_id, | |
a262aec2 DJ |
1063 | arm_prologue_prev_register, |
1064 | NULL, | |
1065 | default_frame_sniffer | |
eb5492fa DJ |
1066 | }; |
1067 | ||
909cf6ea | 1068 | static struct arm_prologue_cache * |
a262aec2 | 1069 | arm_make_stub_cache (struct frame_info *this_frame) |
909cf6ea DJ |
1070 | { |
1071 | int reg; | |
1072 | struct arm_prologue_cache *cache; | |
1073 | CORE_ADDR unwound_fp; | |
1074 | ||
35d5d4ee | 1075 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
a262aec2 | 1076 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
909cf6ea | 1077 | |
a262aec2 | 1078 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
909cf6ea DJ |
1079 | |
1080 | return cache; | |
1081 | } | |
1082 | ||
1083 | /* Our frame ID for a stub frame is the current SP and LR. */ | |
1084 | ||
1085 | static void | |
a262aec2 | 1086 | arm_stub_this_id (struct frame_info *this_frame, |
909cf6ea DJ |
1087 | void **this_cache, |
1088 | struct frame_id *this_id) | |
1089 | { | |
1090 | struct arm_prologue_cache *cache; | |
1091 | ||
1092 | if (*this_cache == NULL) | |
a262aec2 | 1093 | *this_cache = arm_make_stub_cache (this_frame); |
909cf6ea DJ |
1094 | cache = *this_cache; |
1095 | ||
a262aec2 | 1096 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
909cf6ea DJ |
1097 | } |
1098 | ||
a262aec2 DJ |
1099 | static int |
1100 | arm_stub_unwind_sniffer (const struct frame_unwind *self, | |
1101 | struct frame_info *this_frame, | |
1102 | void **this_prologue_cache) | |
909cf6ea | 1103 | { |
93d42b30 | 1104 | CORE_ADDR addr_in_block; |
909cf6ea DJ |
1105 | char dummy[4]; |
1106 | ||
a262aec2 | 1107 | addr_in_block = get_frame_address_in_block (this_frame); |
93d42b30 | 1108 | if (in_plt_section (addr_in_block, NULL) |
a262aec2 DJ |
1109 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
1110 | return 1; | |
909cf6ea | 1111 | |
a262aec2 | 1112 | return 0; |
909cf6ea DJ |
1113 | } |
1114 | ||
a262aec2 DJ |
1115 | struct frame_unwind arm_stub_unwind = { |
1116 | NORMAL_FRAME, | |
1117 | arm_stub_this_id, | |
1118 | arm_prologue_prev_register, | |
1119 | NULL, | |
1120 | arm_stub_unwind_sniffer | |
1121 | }; | |
1122 | ||
24de872b | 1123 | static CORE_ADDR |
a262aec2 | 1124 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
24de872b DJ |
1125 | { |
1126 | struct arm_prologue_cache *cache; | |
1127 | ||
eb5492fa | 1128 | if (*this_cache == NULL) |
a262aec2 | 1129 | *this_cache = arm_make_prologue_cache (this_frame); |
eb5492fa DJ |
1130 | cache = *this_cache; |
1131 | ||
4be43953 | 1132 | return cache->prev_sp - cache->framesize; |
24de872b DJ |
1133 | } |
1134 | ||
eb5492fa DJ |
1135 | struct frame_base arm_normal_base = { |
1136 | &arm_prologue_unwind, | |
1137 | arm_normal_frame_base, | |
1138 | arm_normal_frame_base, | |
1139 | arm_normal_frame_base | |
1140 | }; | |
1141 | ||
a262aec2 | 1142 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
eb5492fa DJ |
1143 | dummy frame. The frame ID's base needs to match the TOS value |
1144 | saved by save_dummy_frame_tos() and returned from | |
1145 | arm_push_dummy_call, and the PC needs to match the dummy frame's | |
1146 | breakpoint. */ | |
c906108c | 1147 | |
eb5492fa | 1148 | static struct frame_id |
a262aec2 | 1149 | arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c906108c | 1150 | { |
a262aec2 DJ |
1151 | return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM), |
1152 | get_frame_pc (this_frame)); | |
eb5492fa | 1153 | } |
c3b4394c | 1154 | |
eb5492fa DJ |
1155 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
1156 | be used to construct the previous frame's ID, after looking up the | |
1157 | containing function). */ | |
c3b4394c | 1158 | |
eb5492fa DJ |
1159 | static CORE_ADDR |
1160 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1161 | { | |
1162 | CORE_ADDR pc; | |
1163 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); | |
59ea4f70 | 1164 | return arm_addr_bits_remove (pc); |
eb5492fa DJ |
1165 | } |
1166 | ||
1167 | static CORE_ADDR | |
1168 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) | |
1169 | { | |
1170 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); | |
c906108c SS |
1171 | } |
1172 | ||
b39cc962 DJ |
1173 | static struct value * |
1174 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, | |
1175 | int regnum) | |
1176 | { | |
1177 | CORE_ADDR lr, cpsr; | |
1178 | ||
1179 | switch (regnum) | |
1180 | { | |
1181 | case ARM_PC_REGNUM: | |
1182 | /* The PC is normally copied from the return column, which | |
1183 | describes saves of LR. However, that version may have an | |
1184 | extra bit set to indicate Thumb state. The bit is not | |
1185 | part of the PC. */ | |
1186 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); | |
1187 | return frame_unwind_got_constant (this_frame, regnum, | |
1188 | arm_addr_bits_remove (lr)); | |
1189 | ||
1190 | case ARM_PS_REGNUM: | |
1191 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ | |
ca38c58e | 1192 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
b39cc962 DJ |
1193 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
1194 | if (IS_THUMB_ADDR (lr)) | |
1195 | cpsr |= CPSR_T; | |
1196 | else | |
1197 | cpsr &= ~CPSR_T; | |
ca38c58e | 1198 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
b39cc962 DJ |
1199 | |
1200 | default: | |
1201 | internal_error (__FILE__, __LINE__, | |
1202 | _("Unexpected register %d"), regnum); | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | static void | |
1207 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1208 | struct dwarf2_frame_state_reg *reg, | |
1209 | struct frame_info *this_frame) | |
1210 | { | |
1211 | switch (regnum) | |
1212 | { | |
1213 | case ARM_PC_REGNUM: | |
1214 | case ARM_PS_REGNUM: | |
1215 | reg->how = DWARF2_FRAME_REG_FN; | |
1216 | reg->loc.fn = arm_dwarf2_prev_register; | |
1217 | break; | |
1218 | case ARM_SP_REGNUM: | |
1219 | reg->how = DWARF2_FRAME_REG_CFA; | |
1220 | break; | |
1221 | } | |
1222 | } | |
1223 | ||
2dd604e7 RE |
1224 | /* When arguments must be pushed onto the stack, they go on in reverse |
1225 | order. The code below implements a FILO (stack) to do this. */ | |
1226 | ||
1227 | struct stack_item | |
1228 | { | |
1229 | int len; | |
1230 | struct stack_item *prev; | |
1231 | void *data; | |
1232 | }; | |
1233 | ||
1234 | static struct stack_item * | |
1235 | push_stack_item (struct stack_item *prev, void *contents, int len) | |
1236 | { | |
1237 | struct stack_item *si; | |
1238 | si = xmalloc (sizeof (struct stack_item)); | |
226c7fbc | 1239 | si->data = xmalloc (len); |
2dd604e7 RE |
1240 | si->len = len; |
1241 | si->prev = prev; | |
1242 | memcpy (si->data, contents, len); | |
1243 | return si; | |
1244 | } | |
1245 | ||
1246 | static struct stack_item * | |
1247 | pop_stack_item (struct stack_item *si) | |
1248 | { | |
1249 | struct stack_item *dead = si; | |
1250 | si = si->prev; | |
1251 | xfree (dead->data); | |
1252 | xfree (dead); | |
1253 | return si; | |
1254 | } | |
1255 | ||
2af48f68 PB |
1256 | |
1257 | /* Return the alignment (in bytes) of the given type. */ | |
1258 | ||
1259 | static int | |
1260 | arm_type_align (struct type *t) | |
1261 | { | |
1262 | int n; | |
1263 | int align; | |
1264 | int falign; | |
1265 | ||
1266 | t = check_typedef (t); | |
1267 | switch (TYPE_CODE (t)) | |
1268 | { | |
1269 | default: | |
1270 | /* Should never happen. */ | |
1271 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); | |
1272 | return 4; | |
1273 | ||
1274 | case TYPE_CODE_PTR: | |
1275 | case TYPE_CODE_ENUM: | |
1276 | case TYPE_CODE_INT: | |
1277 | case TYPE_CODE_FLT: | |
1278 | case TYPE_CODE_SET: | |
1279 | case TYPE_CODE_RANGE: | |
1280 | case TYPE_CODE_BITSTRING: | |
1281 | case TYPE_CODE_REF: | |
1282 | case TYPE_CODE_CHAR: | |
1283 | case TYPE_CODE_BOOL: | |
1284 | return TYPE_LENGTH (t); | |
1285 | ||
1286 | case TYPE_CODE_ARRAY: | |
1287 | case TYPE_CODE_COMPLEX: | |
1288 | /* TODO: What about vector types? */ | |
1289 | return arm_type_align (TYPE_TARGET_TYPE (t)); | |
1290 | ||
1291 | case TYPE_CODE_STRUCT: | |
1292 | case TYPE_CODE_UNION: | |
1293 | align = 1; | |
1294 | for (n = 0; n < TYPE_NFIELDS (t); n++) | |
1295 | { | |
1296 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); | |
1297 | if (falign > align) | |
1298 | align = falign; | |
1299 | } | |
1300 | return align; | |
1301 | } | |
1302 | } | |
1303 | ||
2dd604e7 RE |
1304 | /* We currently only support passing parameters in integer registers. This |
1305 | conforms with GCC's default model. Several other variants exist and | |
1306 | we should probably support some of them based on the selected ABI. */ | |
1307 | ||
1308 | static CORE_ADDR | |
7d9b040b | 1309 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1310 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1311 | struct value **args, CORE_ADDR sp, int struct_return, | |
1312 | CORE_ADDR struct_addr) | |
2dd604e7 RE |
1313 | { |
1314 | int argnum; | |
1315 | int argreg; | |
1316 | int nstack; | |
1317 | struct stack_item *si = NULL; | |
1318 | ||
6a65450a AC |
1319 | /* Set the return address. For the ARM, the return breakpoint is |
1320 | always at BP_ADDR. */ | |
2dd604e7 | 1321 | /* XXX Fix for Thumb. */ |
6a65450a | 1322 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
2dd604e7 RE |
1323 | |
1324 | /* Walk through the list of args and determine how large a temporary | |
1325 | stack is required. Need to take care here as structs may be | |
1326 | passed on the stack, and we have to to push them. */ | |
1327 | nstack = 0; | |
1328 | ||
1329 | argreg = ARM_A1_REGNUM; | |
1330 | nstack = 0; | |
1331 | ||
2dd604e7 RE |
1332 | /* The struct_return pointer occupies the first parameter |
1333 | passing register. */ | |
1334 | if (struct_return) | |
1335 | { | |
1336 | if (arm_debug) | |
1337 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", | |
2af46ca0 | 1338 | gdbarch_register_name (gdbarch, argreg), |
c9f4d572 | 1339 | paddr (struct_addr)); |
2dd604e7 RE |
1340 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
1341 | argreg++; | |
1342 | } | |
1343 | ||
1344 | for (argnum = 0; argnum < nargs; argnum++) | |
1345 | { | |
1346 | int len; | |
1347 | struct type *arg_type; | |
1348 | struct type *target_type; | |
1349 | enum type_code typecode; | |
0fd88904 | 1350 | bfd_byte *val; |
2af48f68 | 1351 | int align; |
2dd604e7 | 1352 | |
df407dfe | 1353 | arg_type = check_typedef (value_type (args[argnum])); |
2dd604e7 RE |
1354 | len = TYPE_LENGTH (arg_type); |
1355 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1356 | typecode = TYPE_CODE (arg_type); | |
0fd88904 | 1357 | val = value_contents_writeable (args[argnum]); |
2dd604e7 | 1358 | |
2af48f68 PB |
1359 | align = arm_type_align (arg_type); |
1360 | /* Round alignment up to a whole number of words. */ | |
1361 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); | |
1362 | /* Different ABIs have different maximum alignments. */ | |
1363 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) | |
1364 | { | |
1365 | /* The APCS ABI only requires word alignment. */ | |
1366 | align = INT_REGISTER_SIZE; | |
1367 | } | |
1368 | else | |
1369 | { | |
1370 | /* The AAPCS requires at most doubleword alignment. */ | |
1371 | if (align > INT_REGISTER_SIZE * 2) | |
1372 | align = INT_REGISTER_SIZE * 2; | |
1373 | } | |
1374 | ||
1375 | /* Push stack padding for dowubleword alignment. */ | |
1376 | if (nstack & (align - 1)) | |
1377 | { | |
1378 | si = push_stack_item (si, val, INT_REGISTER_SIZE); | |
1379 | nstack += INT_REGISTER_SIZE; | |
1380 | } | |
1381 | ||
1382 | /* Doubleword aligned quantities must go in even register pairs. */ | |
1383 | if (argreg <= ARM_LAST_ARG_REGNUM | |
1384 | && align > INT_REGISTER_SIZE | |
1385 | && argreg & 1) | |
1386 | argreg++; | |
1387 | ||
2dd604e7 RE |
1388 | /* If the argument is a pointer to a function, and it is a |
1389 | Thumb function, create a LOCAL copy of the value and set | |
1390 | the THUMB bit in it. */ | |
1391 | if (TYPE_CODE_PTR == typecode | |
1392 | && target_type != NULL | |
1393 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
1394 | { | |
7c0b4a20 | 1395 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
2dd604e7 RE |
1396 | if (arm_pc_is_thumb (regval)) |
1397 | { | |
1398 | val = alloca (len); | |
fbd9dcd3 | 1399 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
2dd604e7 RE |
1400 | } |
1401 | } | |
1402 | ||
1403 | /* Copy the argument to general registers or the stack in | |
1404 | register-sized pieces. Large arguments are split between | |
1405 | registers and stack. */ | |
1406 | while (len > 0) | |
1407 | { | |
f0c9063c | 1408 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
2dd604e7 RE |
1409 | |
1410 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
1411 | { | |
1412 | /* The argument is being passed in a general purpose | |
1413 | register. */ | |
7c0b4a20 | 1414 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
2af46ca0 | 1415 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
8bf8793c | 1416 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
2dd604e7 RE |
1417 | if (arm_debug) |
1418 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", | |
c9f4d572 UW |
1419 | argnum, |
1420 | gdbarch_register_name | |
2af46ca0 | 1421 | (gdbarch, argreg), |
f0c9063c | 1422 | phex (regval, INT_REGISTER_SIZE)); |
2dd604e7 RE |
1423 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
1424 | argreg++; | |
1425 | } | |
1426 | else | |
1427 | { | |
1428 | /* Push the arguments onto the stack. */ | |
1429 | if (arm_debug) | |
1430 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", | |
1431 | argnum, nstack); | |
f0c9063c UW |
1432 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
1433 | nstack += INT_REGISTER_SIZE; | |
2dd604e7 RE |
1434 | } |
1435 | ||
1436 | len -= partial_len; | |
1437 | val += partial_len; | |
1438 | } | |
1439 | } | |
1440 | /* If we have an odd number of words to push, then decrement the stack | |
1441 | by one word now, so first stack argument will be dword aligned. */ | |
1442 | if (nstack & 4) | |
1443 | sp -= 4; | |
1444 | ||
1445 | while (si) | |
1446 | { | |
1447 | sp -= si->len; | |
1448 | write_memory (sp, si->data, si->len); | |
1449 | si = pop_stack_item (si); | |
1450 | } | |
1451 | ||
1452 | /* Finally, update teh SP register. */ | |
1453 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); | |
1454 | ||
1455 | return sp; | |
1456 | } | |
1457 | ||
f53f0d0b PB |
1458 | |
1459 | /* Always align the frame to an 8-byte boundary. This is required on | |
1460 | some platforms and harmless on the rest. */ | |
1461 | ||
1462 | static CORE_ADDR | |
1463 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1464 | { | |
1465 | /* Align the stack to eight bytes. */ | |
1466 | return sp & ~ (CORE_ADDR) 7; | |
1467 | } | |
1468 | ||
c906108c | 1469 | static void |
ed9a39eb | 1470 | print_fpu_flags (int flags) |
c906108c | 1471 | { |
c5aa993b JM |
1472 | if (flags & (1 << 0)) |
1473 | fputs ("IVO ", stdout); | |
1474 | if (flags & (1 << 1)) | |
1475 | fputs ("DVZ ", stdout); | |
1476 | if (flags & (1 << 2)) | |
1477 | fputs ("OFL ", stdout); | |
1478 | if (flags & (1 << 3)) | |
1479 | fputs ("UFL ", stdout); | |
1480 | if (flags & (1 << 4)) | |
1481 | fputs ("INX ", stdout); | |
1482 | putchar ('\n'); | |
c906108c SS |
1483 | } |
1484 | ||
5e74b15c RE |
1485 | /* Print interesting information about the floating point processor |
1486 | (if present) or emulator. */ | |
34e8f22d | 1487 | static void |
d855c300 | 1488 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
23e3a7ac | 1489 | struct frame_info *frame, const char *args) |
c906108c | 1490 | { |
9c9acae0 | 1491 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
c5aa993b JM |
1492 | int type; |
1493 | ||
1494 | type = (status >> 24) & 127; | |
edefbb7c AC |
1495 | if (status & (1 << 31)) |
1496 | printf (_("Hardware FPU type %d\n"), type); | |
1497 | else | |
1498 | printf (_("Software FPU type %d\n"), type); | |
1499 | /* i18n: [floating point unit] mask */ | |
1500 | fputs (_("mask: "), stdout); | |
c5aa993b | 1501 | print_fpu_flags (status >> 16); |
edefbb7c AC |
1502 | /* i18n: [floating point unit] flags */ |
1503 | fputs (_("flags: "), stdout); | |
c5aa993b | 1504 | print_fpu_flags (status); |
c906108c SS |
1505 | } |
1506 | ||
34e8f22d RE |
1507 | /* Return the GDB type object for the "standard" data type of data in |
1508 | register N. */ | |
1509 | ||
1510 | static struct type * | |
7a5ea0d4 | 1511 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
032758dc | 1512 | { |
34e8f22d | 1513 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
8da61cc4 | 1514 | return builtin_type_arm_ext; |
e4c16157 DJ |
1515 | else if (regnum == ARM_SP_REGNUM) |
1516 | return builtin_type_void_data_ptr; | |
1517 | else if (regnum == ARM_PC_REGNUM) | |
1518 | return builtin_type_void_func_ptr; | |
ff6f572f DJ |
1519 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
1520 | /* These registers are only supported on targets which supply | |
1521 | an XML description. */ | |
1522 | return builtin_type_int0; | |
032758dc | 1523 | else |
e4c16157 | 1524 | return builtin_type_uint32; |
032758dc AC |
1525 | } |
1526 | ||
ff6f572f DJ |
1527 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
1528 | number. */ | |
1529 | ||
1530 | static int | |
d3f73121 | 1531 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
ff6f572f DJ |
1532 | { |
1533 | /* Core integer regs. */ | |
1534 | if (reg >= 0 && reg <= 15) | |
1535 | return reg; | |
1536 | ||
1537 | /* Legacy FPA encoding. These were once used in a way which | |
1538 | overlapped with VFP register numbering, so their use is | |
1539 | discouraged, but GDB doesn't support the ARM toolchain | |
1540 | which used them for VFP. */ | |
1541 | if (reg >= 16 && reg <= 23) | |
1542 | return ARM_F0_REGNUM + reg - 16; | |
1543 | ||
1544 | /* New assignments for the FPA registers. */ | |
1545 | if (reg >= 96 && reg <= 103) | |
1546 | return ARM_F0_REGNUM + reg - 96; | |
1547 | ||
1548 | /* WMMX register assignments. */ | |
1549 | if (reg >= 104 && reg <= 111) | |
1550 | return ARM_WCGR0_REGNUM + reg - 104; | |
1551 | ||
1552 | if (reg >= 112 && reg <= 127) | |
1553 | return ARM_WR0_REGNUM + reg - 112; | |
1554 | ||
1555 | if (reg >= 192 && reg <= 199) | |
1556 | return ARM_WC0_REGNUM + reg - 192; | |
1557 | ||
1558 | return -1; | |
1559 | } | |
1560 | ||
26216b98 AC |
1561 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
1562 | static int | |
e7faf938 | 1563 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
26216b98 AC |
1564 | { |
1565 | int reg = regnum; | |
e7faf938 | 1566 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
26216b98 | 1567 | |
ff6f572f DJ |
1568 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
1569 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; | |
1570 | ||
1571 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) | |
1572 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; | |
1573 | ||
1574 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) | |
1575 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; | |
1576 | ||
26216b98 AC |
1577 | if (reg < NUM_GREGS) |
1578 | return SIM_ARM_R0_REGNUM + reg; | |
1579 | reg -= NUM_GREGS; | |
1580 | ||
1581 | if (reg < NUM_FREGS) | |
1582 | return SIM_ARM_FP0_REGNUM + reg; | |
1583 | reg -= NUM_FREGS; | |
1584 | ||
1585 | if (reg < NUM_SREGS) | |
1586 | return SIM_ARM_FPS_REGNUM + reg; | |
1587 | reg -= NUM_SREGS; | |
1588 | ||
edefbb7c | 1589 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
26216b98 | 1590 | } |
34e8f22d | 1591 | |
a37b3cc0 AC |
1592 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1593 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1594 | It is thought that this is is the floating-point register format on | |
1595 | little-endian systems. */ | |
c906108c | 1596 | |
ed9a39eb | 1597 | static void |
b508a996 | 1598 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
be8626e0 | 1599 | void *dbl, int endianess) |
c906108c | 1600 | { |
a37b3cc0 | 1601 | DOUBLEST d; |
be8626e0 MD |
1602 | |
1603 | if (endianess == BFD_ENDIAN_BIG) | |
a37b3cc0 AC |
1604 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1605 | else | |
1606 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1607 | ptr, &d); | |
b508a996 | 1608 | floatformat_from_doublest (fmt, &d, dbl); |
c906108c SS |
1609 | } |
1610 | ||
34e8f22d | 1611 | static void |
be8626e0 MD |
1612 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
1613 | int endianess) | |
c906108c | 1614 | { |
a37b3cc0 | 1615 | DOUBLEST d; |
be8626e0 | 1616 | |
b508a996 | 1617 | floatformat_to_doublest (fmt, ptr, &d); |
be8626e0 | 1618 | if (endianess == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1619 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1620 | else | |
1621 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1622 | &d, dbl); | |
c906108c | 1623 | } |
ed9a39eb | 1624 | |
c906108c | 1625 | static int |
ed9a39eb | 1626 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1627 | { |
1628 | if (cond == INST_AL || cond == INST_NV) | |
1629 | return 1; | |
1630 | ||
1631 | switch (cond) | |
1632 | { | |
1633 | case INST_EQ: | |
1634 | return ((status_reg & FLAG_Z) != 0); | |
1635 | case INST_NE: | |
1636 | return ((status_reg & FLAG_Z) == 0); | |
1637 | case INST_CS: | |
1638 | return ((status_reg & FLAG_C) != 0); | |
1639 | case INST_CC: | |
1640 | return ((status_reg & FLAG_C) == 0); | |
1641 | case INST_MI: | |
1642 | return ((status_reg & FLAG_N) != 0); | |
1643 | case INST_PL: | |
1644 | return ((status_reg & FLAG_N) == 0); | |
1645 | case INST_VS: | |
1646 | return ((status_reg & FLAG_V) != 0); | |
1647 | case INST_VC: | |
1648 | return ((status_reg & FLAG_V) == 0); | |
1649 | case INST_HI: | |
1650 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1651 | case INST_LS: | |
1652 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1653 | case INST_GE: | |
1654 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1655 | case INST_LT: | |
1656 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1657 | case INST_GT: | |
1658 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1659 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1660 | case INST_LE: |
1661 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1662 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1663 | } |
1664 | return 1; | |
1665 | } | |
1666 | ||
9512d7fd | 1667 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1668 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1669 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1670 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1671 | #define sbits(obj,st,fn) \ | |
1672 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1673 | #define BranchDest(addr,instr) \ | |
1674 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1675 | #define ARM_PC_32 1 | |
1676 | ||
1677 | static unsigned long | |
0b1b3e42 UW |
1678 | shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, |
1679 | unsigned long pc_val, unsigned long status_reg) | |
c906108c SS |
1680 | { |
1681 | unsigned long res, shift; | |
1682 | int rm = bits (inst, 0, 3); | |
1683 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1684 | |
1685 | if (bit (inst, 4)) | |
c906108c SS |
1686 | { |
1687 | int rs = bits (inst, 8, 11); | |
0b1b3e42 UW |
1688 | shift = (rs == 15 ? pc_val + 8 |
1689 | : get_frame_register_unsigned (frame, rs)) & 0xFF; | |
c906108c SS |
1690 | } |
1691 | else | |
1692 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1693 | |
1694 | res = (rm == 15 | |
c906108c | 1695 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1696 | + (bit (inst, 4) ? 12 : 8)) |
0b1b3e42 | 1697 | : get_frame_register_unsigned (frame, rm)); |
c906108c SS |
1698 | |
1699 | switch (shifttype) | |
1700 | { | |
c5aa993b | 1701 | case 0: /* LSL */ |
c906108c SS |
1702 | res = shift >= 32 ? 0 : res << shift; |
1703 | break; | |
c5aa993b JM |
1704 | |
1705 | case 1: /* LSR */ | |
c906108c SS |
1706 | res = shift >= 32 ? 0 : res >> shift; |
1707 | break; | |
1708 | ||
c5aa993b JM |
1709 | case 2: /* ASR */ |
1710 | if (shift >= 32) | |
1711 | shift = 31; | |
c906108c SS |
1712 | res = ((res & 0x80000000L) |
1713 | ? ~((~res) >> shift) : res >> shift); | |
1714 | break; | |
1715 | ||
c5aa993b | 1716 | case 3: /* ROR/RRX */ |
c906108c SS |
1717 | shift &= 31; |
1718 | if (shift == 0) | |
1719 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1720 | else | |
c5aa993b | 1721 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1722 | break; |
1723 | } | |
1724 | ||
1725 | return res & 0xffffffff; | |
1726 | } | |
1727 | ||
c906108c SS |
1728 | /* Return number of 1-bits in VAL. */ |
1729 | ||
1730 | static int | |
ed9a39eb | 1731 | bitcount (unsigned long val) |
c906108c SS |
1732 | { |
1733 | int nbits; | |
1734 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1735 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1736 | return nbits; |
1737 | } | |
1738 | ||
ad527d2e | 1739 | static CORE_ADDR |
0b1b3e42 | 1740 | thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1741 | { |
2af46ca0 | 1742 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b | 1743 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
1c5bada0 | 1744 | unsigned short inst1 = read_memory_unsigned_integer (pc, 2); |
94c30b78 | 1745 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1746 | unsigned long offset; |
1747 | ||
1748 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1749 | { | |
1750 | CORE_ADDR sp; | |
1751 | ||
1752 | /* Fetch the saved PC from the stack. It's stored above | |
1753 | all of the other registers. */ | |
f0c9063c | 1754 | offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; |
0b1b3e42 | 1755 | sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
1c5bada0 | 1756 | nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4); |
2af46ca0 | 1757 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c | 1758 | if (nextpc == pc) |
edefbb7c | 1759 | error (_("Infinite loop detected")); |
c906108c SS |
1760 | } |
1761 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1762 | { | |
0b1b3e42 | 1763 | unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 1764 | unsigned long cond = bits (inst1, 8, 11); |
94c30b78 | 1765 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
c906108c SS |
1766 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
1767 | } | |
1768 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1769 | { | |
1770 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1771 | } | |
aa17d93e | 1772 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
c906108c | 1773 | { |
1c5bada0 | 1774 | unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2); |
c5aa993b | 1775 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c | 1776 | nextpc = pc_val + offset; |
aa17d93e DJ |
1777 | /* For BLX make sure to clear the low bits. */ |
1778 | if (bits (inst2, 11, 12) == 1) | |
1779 | nextpc = nextpc & 0xfffffffc; | |
c906108c | 1780 | } |
aa17d93e | 1781 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
9498281f DJ |
1782 | { |
1783 | if (bits (inst1, 3, 6) == 0x0f) | |
1784 | nextpc = pc_val; | |
1785 | else | |
0b1b3e42 | 1786 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); |
9498281f | 1787 | |
2af46ca0 | 1788 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
9498281f | 1789 | if (nextpc == pc) |
edefbb7c | 1790 | error (_("Infinite loop detected")); |
9498281f | 1791 | } |
c906108c SS |
1792 | |
1793 | return nextpc; | |
1794 | } | |
1795 | ||
daddc3c1 | 1796 | CORE_ADDR |
0b1b3e42 | 1797 | arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1798 | { |
2af46ca0 | 1799 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c SS |
1800 | unsigned long pc_val; |
1801 | unsigned long this_instr; | |
1802 | unsigned long status; | |
1803 | CORE_ADDR nextpc; | |
1804 | ||
b39cc962 | 1805 | if (arm_frame_is_thumb (frame)) |
0b1b3e42 | 1806 | return thumb_get_next_pc (frame, pc); |
c906108c SS |
1807 | |
1808 | pc_val = (unsigned long) pc; | |
1c5bada0 | 1809 | this_instr = read_memory_unsigned_integer (pc, 4); |
0b1b3e42 | 1810 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
c5aa993b | 1811 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c | 1812 | |
daddc3c1 DJ |
1813 | if (bits (this_instr, 28, 31) == INST_NV) |
1814 | switch (bits (this_instr, 24, 27)) | |
1815 | { | |
1816 | case 0xa: | |
1817 | case 0xb: | |
1818 | { | |
1819 | /* Branch with Link and change to Thumb. */ | |
1820 | nextpc = BranchDest (pc, this_instr); | |
1821 | nextpc |= bit (this_instr, 24) << 1; | |
1822 | ||
e1e01acd | 1823 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
daddc3c1 DJ |
1824 | if (nextpc == pc) |
1825 | error (_("Infinite loop detected")); | |
1826 | break; | |
1827 | } | |
1828 | case 0xc: | |
1829 | case 0xd: | |
1830 | case 0xe: | |
1831 | /* Coprocessor register transfer. */ | |
1832 | if (bits (this_instr, 12, 15) == 15) | |
1833 | error (_("Invalid update to pc in instruction")); | |
1834 | break; | |
1835 | } | |
1836 | else if (condition_true (bits (this_instr, 28, 31), status)) | |
c906108c SS |
1837 | { |
1838 | switch (bits (this_instr, 24, 27)) | |
1839 | { | |
c5aa993b | 1840 | case 0x0: |
94c30b78 | 1841 | case 0x1: /* data processing */ |
c5aa993b JM |
1842 | case 0x2: |
1843 | case 0x3: | |
c906108c SS |
1844 | { |
1845 | unsigned long operand1, operand2, result = 0; | |
1846 | unsigned long rn; | |
1847 | int c; | |
c5aa993b | 1848 | |
c906108c SS |
1849 | if (bits (this_instr, 12, 15) != 15) |
1850 | break; | |
1851 | ||
1852 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1853 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
edefbb7c | 1854 | error (_("Invalid update to pc in instruction")); |
c906108c | 1855 | |
9498281f | 1856 | /* BX <reg>, BLX <reg> */ |
e150acc7 PB |
1857 | if (bits (this_instr, 4, 27) == 0x12fff1 |
1858 | || bits (this_instr, 4, 27) == 0x12fff3) | |
9498281f DJ |
1859 | { |
1860 | rn = bits (this_instr, 0, 3); | |
0b1b3e42 UW |
1861 | result = (rn == 15) ? pc_val + 8 |
1862 | : get_frame_register_unsigned (frame, rn); | |
bf6ae464 | 1863 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
2af46ca0 | 1864 | (gdbarch, result); |
9498281f DJ |
1865 | |
1866 | if (nextpc == pc) | |
edefbb7c | 1867 | error (_("Infinite loop detected")); |
9498281f DJ |
1868 | |
1869 | return nextpc; | |
1870 | } | |
1871 | ||
c906108c SS |
1872 | /* Multiply into PC */ |
1873 | c = (status & FLAG_C) ? 1 : 0; | |
1874 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
1875 | operand1 = (rn == 15) ? pc_val + 8 |
1876 | : get_frame_register_unsigned (frame, rn); | |
c5aa993b | 1877 | |
c906108c SS |
1878 | if (bit (this_instr, 25)) |
1879 | { | |
1880 | unsigned long immval = bits (this_instr, 0, 7); | |
1881 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1882 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1883 | & 0xffffffff; | |
c906108c | 1884 | } |
c5aa993b | 1885 | else /* operand 2 is a shifted register */ |
0b1b3e42 | 1886 | operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status); |
c5aa993b | 1887 | |
c906108c SS |
1888 | switch (bits (this_instr, 21, 24)) |
1889 | { | |
c5aa993b | 1890 | case 0x0: /*and */ |
c906108c SS |
1891 | result = operand1 & operand2; |
1892 | break; | |
1893 | ||
c5aa993b | 1894 | case 0x1: /*eor */ |
c906108c SS |
1895 | result = operand1 ^ operand2; |
1896 | break; | |
1897 | ||
c5aa993b | 1898 | case 0x2: /*sub */ |
c906108c SS |
1899 | result = operand1 - operand2; |
1900 | break; | |
1901 | ||
c5aa993b | 1902 | case 0x3: /*rsb */ |
c906108c SS |
1903 | result = operand2 - operand1; |
1904 | break; | |
1905 | ||
c5aa993b | 1906 | case 0x4: /*add */ |
c906108c SS |
1907 | result = operand1 + operand2; |
1908 | break; | |
1909 | ||
c5aa993b | 1910 | case 0x5: /*adc */ |
c906108c SS |
1911 | result = operand1 + operand2 + c; |
1912 | break; | |
1913 | ||
c5aa993b | 1914 | case 0x6: /*sbc */ |
c906108c SS |
1915 | result = operand1 - operand2 + c; |
1916 | break; | |
1917 | ||
c5aa993b | 1918 | case 0x7: /*rsc */ |
c906108c SS |
1919 | result = operand2 - operand1 + c; |
1920 | break; | |
1921 | ||
c5aa993b JM |
1922 | case 0x8: |
1923 | case 0x9: | |
1924 | case 0xa: | |
1925 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1926 | result = (unsigned long) nextpc; |
1927 | break; | |
1928 | ||
c5aa993b | 1929 | case 0xc: /*orr */ |
c906108c SS |
1930 | result = operand1 | operand2; |
1931 | break; | |
1932 | ||
c5aa993b | 1933 | case 0xd: /*mov */ |
c906108c SS |
1934 | /* Always step into a function. */ |
1935 | result = operand2; | |
c5aa993b | 1936 | break; |
c906108c | 1937 | |
c5aa993b | 1938 | case 0xe: /*bic */ |
c906108c SS |
1939 | result = operand1 & ~operand2; |
1940 | break; | |
1941 | ||
c5aa993b | 1942 | case 0xf: /*mvn */ |
c906108c SS |
1943 | result = ~operand2; |
1944 | break; | |
1945 | } | |
bf6ae464 | 1946 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
2af46ca0 | 1947 | (gdbarch, result); |
c906108c SS |
1948 | |
1949 | if (nextpc == pc) | |
edefbb7c | 1950 | error (_("Infinite loop detected")); |
c906108c SS |
1951 | break; |
1952 | } | |
c5aa993b JM |
1953 | |
1954 | case 0x4: | |
1955 | case 0x5: /* data transfer */ | |
1956 | case 0x6: | |
1957 | case 0x7: | |
c906108c SS |
1958 | if (bit (this_instr, 20)) |
1959 | { | |
1960 | /* load */ | |
1961 | if (bits (this_instr, 12, 15) == 15) | |
1962 | { | |
1963 | /* rd == pc */ | |
c5aa993b | 1964 | unsigned long rn; |
c906108c | 1965 | unsigned long base; |
c5aa993b | 1966 | |
c906108c | 1967 | if (bit (this_instr, 22)) |
edefbb7c | 1968 | error (_("Invalid update to pc in instruction")); |
c906108c SS |
1969 | |
1970 | /* byte write to PC */ | |
1971 | rn = bits (this_instr, 16, 19); | |
0b1b3e42 UW |
1972 | base = (rn == 15) ? pc_val + 8 |
1973 | : get_frame_register_unsigned (frame, rn); | |
c906108c SS |
1974 | if (bit (this_instr, 24)) |
1975 | { | |
1976 | /* pre-indexed */ | |
1977 | int c = (status & FLAG_C) ? 1 : 0; | |
1978 | unsigned long offset = | |
c5aa993b | 1979 | (bit (this_instr, 25) |
0b1b3e42 | 1980 | ? shifted_reg_val (frame, this_instr, c, pc_val, status) |
c5aa993b | 1981 | : bits (this_instr, 0, 11)); |
c906108c SS |
1982 | |
1983 | if (bit (this_instr, 23)) | |
1984 | base += offset; | |
1985 | else | |
1986 | base -= offset; | |
1987 | } | |
c5aa993b | 1988 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1989 | 4); |
c5aa993b | 1990 | |
2af46ca0 | 1991 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c SS |
1992 | |
1993 | if (nextpc == pc) | |
edefbb7c | 1994 | error (_("Infinite loop detected")); |
c906108c SS |
1995 | } |
1996 | } | |
1997 | break; | |
c5aa993b JM |
1998 | |
1999 | case 0x8: | |
2000 | case 0x9: /* block transfer */ | |
c906108c SS |
2001 | if (bit (this_instr, 20)) |
2002 | { | |
2003 | /* LDM */ | |
2004 | if (bit (this_instr, 15)) | |
2005 | { | |
2006 | /* loading pc */ | |
2007 | int offset = 0; | |
2008 | ||
2009 | if (bit (this_instr, 23)) | |
2010 | { | |
2011 | /* up */ | |
2012 | unsigned long reglist = bits (this_instr, 0, 14); | |
2013 | offset = bitcount (reglist) * 4; | |
c5aa993b | 2014 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
2015 | offset += 4; |
2016 | } | |
2017 | else if (bit (this_instr, 24)) | |
2018 | offset = -4; | |
c5aa993b | 2019 | |
c906108c | 2020 | { |
c5aa993b | 2021 | unsigned long rn_val = |
0b1b3e42 UW |
2022 | get_frame_register_unsigned (frame, |
2023 | bits (this_instr, 16, 19)); | |
c906108c SS |
2024 | nextpc = |
2025 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 2026 | + offset), |
c906108c SS |
2027 | 4); |
2028 | } | |
bf6ae464 | 2029 | nextpc = gdbarch_addr_bits_remove |
2af46ca0 | 2030 | (gdbarch, nextpc); |
c906108c | 2031 | if (nextpc == pc) |
edefbb7c | 2032 | error (_("Infinite loop detected")); |
c906108c SS |
2033 | } |
2034 | } | |
2035 | break; | |
c5aa993b JM |
2036 | |
2037 | case 0xb: /* branch & link */ | |
2038 | case 0xa: /* branch */ | |
c906108c SS |
2039 | { |
2040 | nextpc = BranchDest (pc, this_instr); | |
2041 | ||
2af46ca0 | 2042 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
c906108c | 2043 | if (nextpc == pc) |
edefbb7c | 2044 | error (_("Infinite loop detected")); |
c906108c SS |
2045 | break; |
2046 | } | |
c5aa993b JM |
2047 | |
2048 | case 0xc: | |
2049 | case 0xd: | |
2050 | case 0xe: /* coproc ops */ | |
2051 | case 0xf: /* SWI */ | |
c906108c SS |
2052 | break; |
2053 | ||
2054 | default: | |
edefbb7c | 2055 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
c906108c SS |
2056 | return (pc); |
2057 | } | |
2058 | } | |
2059 | ||
2060 | return nextpc; | |
2061 | } | |
2062 | ||
9512d7fd FN |
2063 | /* single_step() is called just before we want to resume the inferior, |
2064 | if we want to single-step it but there is no hardware or kernel | |
2065 | single-step support. We find the target of the coming instruction | |
e0cd558a | 2066 | and breakpoint it. */ |
9512d7fd | 2067 | |
190dce09 | 2068 | int |
0b1b3e42 | 2069 | arm_software_single_step (struct frame_info *frame) |
9512d7fd | 2070 | { |
8181d85f DJ |
2071 | /* NOTE: This may insert the wrong breakpoint instruction when |
2072 | single-stepping over a mode-changing instruction, if the | |
2073 | CPSR heuristics are used. */ | |
9512d7fd | 2074 | |
0b1b3e42 | 2075 | CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); |
e0cd558a | 2076 | insert_single_step_breakpoint (next_pc); |
e6590a1b UW |
2077 | |
2078 | return 1; | |
9512d7fd | 2079 | } |
9512d7fd | 2080 | |
c906108c SS |
2081 | #include "bfd-in2.h" |
2082 | #include "libcoff.h" | |
2083 | ||
2084 | static int | |
ed9a39eb | 2085 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2086 | { |
2087 | if (arm_pc_is_thumb (memaddr)) | |
2088 | { | |
c5aa993b JM |
2089 | static asymbol *asym; |
2090 | static combined_entry_type ce; | |
2091 | static struct coff_symbol_struct csym; | |
27cddce2 | 2092 | static struct bfd fake_bfd; |
c5aa993b | 2093 | static bfd_target fake_target; |
c906108c SS |
2094 | |
2095 | if (csym.native == NULL) | |
2096 | { | |
da3c6d4a MS |
2097 | /* Create a fake symbol vector containing a Thumb symbol. |
2098 | This is solely so that the code in print_insn_little_arm() | |
2099 | and print_insn_big_arm() in opcodes/arm-dis.c will detect | |
2100 | the presence of a Thumb symbol and switch to decoding | |
2101 | Thumb instructions. */ | |
c5aa993b JM |
2102 | |
2103 | fake_target.flavour = bfd_target_coff_flavour; | |
2104 | fake_bfd.xvec = &fake_target; | |
c906108c | 2105 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2106 | csym.native = &ce; |
2107 | csym.symbol.the_bfd = &fake_bfd; | |
2108 | csym.symbol.name = "fake"; | |
2109 | asym = (asymbol *) & csym; | |
c906108c | 2110 | } |
c5aa993b | 2111 | |
c906108c | 2112 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2113 | info->symbols = &asym; |
c906108c SS |
2114 | } |
2115 | else | |
2116 | info->symbols = NULL; | |
c5aa993b | 2117 | |
40887e1a | 2118 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
2119 | return print_insn_big_arm (memaddr, info); |
2120 | else | |
2121 | return print_insn_little_arm (memaddr, info); | |
2122 | } | |
2123 | ||
66e810cd RE |
2124 | /* The following define instruction sequences that will cause ARM |
2125 | cpu's to take an undefined instruction trap. These are used to | |
2126 | signal a breakpoint to GDB. | |
2127 | ||
2128 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
2129 | modes. A different instruction is required for each mode. The ARM | |
2130 | cpu's can also be big or little endian. Thus four different | |
2131 | instructions are needed to support all cases. | |
2132 | ||
2133 | Note: ARMv4 defines several new instructions that will take the | |
2134 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
2135 | not in fact add the new instructions. The new undefined | |
2136 | instructions in ARMv4 are all instructions that had no defined | |
2137 | behaviour in earlier chips. There is no guarantee that they will | |
2138 | raise an exception, but may be treated as NOP's. In practice, it | |
2139 | may only safe to rely on instructions matching: | |
2140 | ||
2141 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
2142 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
2143 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
2144 | ||
2145 | Even this may only true if the condition predicate is true. The | |
2146 | following use a condition predicate of ALWAYS so it is always TRUE. | |
2147 | ||
2148 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, | |
2149 | and NetBSD all use a software interrupt rather than an undefined | |
2150 | instruction to force a trap. This can be handled by by the | |
2151 | abi-specific code during establishment of the gdbarch vector. */ | |
2152 | ||
66e810cd | 2153 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
66e810cd | 2154 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
190dce09 UW |
2155 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} |
2156 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} | |
66e810cd RE |
2157 | |
2158 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; | |
2159 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; | |
2160 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2161 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2162 | ||
34e8f22d RE |
2163 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
2164 | the program counter value to determine whether a 16-bit or 32-bit | |
ed9a39eb JM |
2165 | breakpoint should be used. It returns a pointer to a string of |
2166 | bytes that encode a breakpoint instruction, stores the length of | |
2167 | the string to *lenptr, and adjusts the program counter (if | |
2168 | necessary) to point to the actual memory location where the | |
c906108c SS |
2169 | breakpoint should be inserted. */ |
2170 | ||
ab89facf | 2171 | static const unsigned char * |
67d57894 | 2172 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
c906108c | 2173 | { |
67d57894 | 2174 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
66e810cd | 2175 | |
4bf7064c | 2176 | if (arm_pc_is_thumb (*pcptr)) |
c906108c | 2177 | { |
66e810cd RE |
2178 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
2179 | *lenptr = tdep->thumb_breakpoint_size; | |
2180 | return tdep->thumb_breakpoint; | |
c906108c SS |
2181 | } |
2182 | else | |
2183 | { | |
66e810cd RE |
2184 | *lenptr = tdep->arm_breakpoint_size; |
2185 | return tdep->arm_breakpoint; | |
c906108c SS |
2186 | } |
2187 | } | |
ed9a39eb JM |
2188 | |
2189 | /* Extract from an array REGBUF containing the (raw) register state a | |
2190 | function return value of type TYPE, and copy that, in virtual | |
2191 | format, into VALBUF. */ | |
2192 | ||
34e8f22d | 2193 | static void |
5238cf52 MK |
2194 | arm_extract_return_value (struct type *type, struct regcache *regs, |
2195 | gdb_byte *valbuf) | |
ed9a39eb | 2196 | { |
be8626e0 MD |
2197 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
2198 | ||
ed9a39eb | 2199 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
08216dd7 | 2200 | { |
be8626e0 | 2201 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
2202 | { |
2203 | case ARM_FLOAT_FPA: | |
b508a996 RE |
2204 | { |
2205 | /* The value is in register F0 in internal format. We need to | |
2206 | extract the raw value and then convert it to the desired | |
2207 | internal type. */ | |
7a5ea0d4 | 2208 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
b508a996 RE |
2209 | |
2210 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); | |
2211 | convert_from_extended (floatformat_from_type (type), tmpbuf, | |
be8626e0 | 2212 | valbuf, gdbarch_byte_order (gdbarch)); |
b508a996 | 2213 | } |
08216dd7 RE |
2214 | break; |
2215 | ||
fd50bc42 | 2216 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2217 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2218 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
2219 | if (TYPE_LENGTH (type) > 4) | |
2220 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2221 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2222 | break; |
2223 | ||
2224 | default: | |
2225 | internal_error | |
2226 | (__FILE__, __LINE__, | |
edefbb7c | 2227 | _("arm_extract_return_value: Floating point model not supported")); |
08216dd7 RE |
2228 | break; |
2229 | } | |
2230 | } | |
b508a996 RE |
2231 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2232 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2233 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2234 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2235 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2236 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2237 | { | |
2238 | /* If the the type is a plain integer, then the access is | |
2239 | straight-forward. Otherwise we have to play around a bit more. */ | |
2240 | int len = TYPE_LENGTH (type); | |
2241 | int regno = ARM_A1_REGNUM; | |
2242 | ULONGEST tmp; | |
2243 | ||
2244 | while (len > 0) | |
2245 | { | |
2246 | /* By using store_unsigned_integer we avoid having to do | |
2247 | anything special for small big-endian values. */ | |
2248 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2249 | store_unsigned_integer (valbuf, | |
7a5ea0d4 DJ |
2250 | (len > INT_REGISTER_SIZE |
2251 | ? INT_REGISTER_SIZE : len), | |
b508a996 | 2252 | tmp); |
7a5ea0d4 DJ |
2253 | len -= INT_REGISTER_SIZE; |
2254 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2255 | } |
2256 | } | |
ed9a39eb | 2257 | else |
b508a996 RE |
2258 | { |
2259 | /* For a structure or union the behaviour is as if the value had | |
2260 | been stored to word-aligned memory and then loaded into | |
2261 | registers with 32-bit load instruction(s). */ | |
2262 | int len = TYPE_LENGTH (type); | |
2263 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2264 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2265 | |
2266 | while (len > 0) | |
2267 | { | |
2268 | regcache_cooked_read (regs, regno++, tmpbuf); | |
2269 | memcpy (valbuf, tmpbuf, | |
7a5ea0d4 DJ |
2270 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
2271 | len -= INT_REGISTER_SIZE; | |
2272 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2273 | } |
2274 | } | |
34e8f22d RE |
2275 | } |
2276 | ||
67255d04 RE |
2277 | |
2278 | /* Will a function return an aggregate type in memory or in a | |
2279 | register? Return 0 if an aggregate type can be returned in a | |
2280 | register, 1 if it must be returned in memory. */ | |
2281 | ||
2282 | static int | |
2af48f68 | 2283 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
67255d04 RE |
2284 | { |
2285 | int nRc; | |
52f0bd74 | 2286 | enum type_code code; |
67255d04 | 2287 | |
44e1a9eb DJ |
2288 | CHECK_TYPEDEF (type); |
2289 | ||
67255d04 RE |
2290 | /* In the ARM ABI, "integer" like aggregate types are returned in |
2291 | registers. For an aggregate type to be integer like, its size | |
f0c9063c | 2292 | must be less than or equal to INT_REGISTER_SIZE and the |
b1e29e33 AC |
2293 | offset of each addressable subfield must be zero. Note that bit |
2294 | fields are not addressable, and all addressable subfields of | |
2295 | unions always start at offset zero. | |
67255d04 RE |
2296 | |
2297 | This function is based on the behaviour of GCC 2.95.1. | |
2298 | See: gcc/arm.c: arm_return_in_memory() for details. | |
2299 | ||
2300 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
2301 | parameters correctly for a function returning the following | |
2302 | structure: struct { float f;}; This should be returned in memory, | |
2303 | not a register. Richard Earnshaw sent me a patch, but I do not | |
2304 | know of any way to detect if a function like the above has been | |
2305 | compiled with the correct calling convention. */ | |
2306 | ||
2307 | /* All aggregate types that won't fit in a register must be returned | |
2308 | in memory. */ | |
f0c9063c | 2309 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) |
67255d04 RE |
2310 | { |
2311 | return 1; | |
2312 | } | |
2313 | ||
2af48f68 PB |
2314 | /* The AAPCS says all aggregates not larger than a word are returned |
2315 | in a register. */ | |
2316 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) | |
2317 | return 0; | |
2318 | ||
67255d04 RE |
2319 | /* The only aggregate types that can be returned in a register are |
2320 | structs and unions. Arrays must be returned in memory. */ | |
2321 | code = TYPE_CODE (type); | |
2322 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
2323 | { | |
2324 | return 1; | |
2325 | } | |
2326 | ||
2327 | /* Assume all other aggregate types can be returned in a register. | |
2328 | Run a check for structures, unions and arrays. */ | |
2329 | nRc = 0; | |
2330 | ||
2331 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
2332 | { | |
2333 | int i; | |
2334 | /* Need to check if this struct/union is "integer" like. For | |
2335 | this to be true, its size must be less than or equal to | |
f0c9063c | 2336 | INT_REGISTER_SIZE and the offset of each addressable |
b1e29e33 AC |
2337 | subfield must be zero. Note that bit fields are not |
2338 | addressable, and unions always start at offset zero. If any | |
2339 | of the subfields is a floating point type, the struct/union | |
2340 | cannot be an integer type. */ | |
67255d04 RE |
2341 | |
2342 | /* For each field in the object, check: | |
2343 | 1) Is it FP? --> yes, nRc = 1; | |
2344 | 2) Is it addressable (bitpos != 0) and | |
2345 | not packed (bitsize == 0)? | |
2346 | --> yes, nRc = 1 | |
2347 | */ | |
2348 | ||
2349 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2350 | { | |
2351 | enum type_code field_type_code; | |
44e1a9eb | 2352 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
67255d04 RE |
2353 | |
2354 | /* Is it a floating point type field? */ | |
2355 | if (field_type_code == TYPE_CODE_FLT) | |
2356 | { | |
2357 | nRc = 1; | |
2358 | break; | |
2359 | } | |
2360 | ||
2361 | /* If bitpos != 0, then we have to care about it. */ | |
2362 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
2363 | { | |
2364 | /* Bitfields are not addressable. If the field bitsize is | |
2365 | zero, then the field is not packed. Hence it cannot be | |
2366 | a bitfield or any other packed type. */ | |
2367 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
2368 | { | |
2369 | nRc = 1; | |
2370 | break; | |
2371 | } | |
2372 | } | |
2373 | } | |
2374 | } | |
2375 | ||
2376 | return nRc; | |
2377 | } | |
2378 | ||
34e8f22d RE |
2379 | /* Write into appropriate registers a function return value of type |
2380 | TYPE, given in virtual format. */ | |
2381 | ||
2382 | static void | |
b508a996 | 2383 | arm_store_return_value (struct type *type, struct regcache *regs, |
5238cf52 | 2384 | const gdb_byte *valbuf) |
34e8f22d | 2385 | { |
be8626e0 MD |
2386 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
2387 | ||
34e8f22d RE |
2388 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2389 | { | |
7a5ea0d4 | 2390 | char buf[MAX_REGISTER_SIZE]; |
34e8f22d | 2391 | |
be8626e0 | 2392 | switch (gdbarch_tdep (gdbarch)->fp_model) |
08216dd7 RE |
2393 | { |
2394 | case ARM_FLOAT_FPA: | |
2395 | ||
be8626e0 MD |
2396 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
2397 | gdbarch_byte_order (gdbarch)); | |
b508a996 | 2398 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
08216dd7 RE |
2399 | break; |
2400 | ||
fd50bc42 | 2401 | case ARM_FLOAT_SOFT_FPA: |
08216dd7 | 2402 | case ARM_FLOAT_SOFT_VFP: |
b508a996 RE |
2403 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
2404 | if (TYPE_LENGTH (type) > 4) | |
2405 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, | |
7a5ea0d4 | 2406 | valbuf + INT_REGISTER_SIZE); |
08216dd7 RE |
2407 | break; |
2408 | ||
2409 | default: | |
2410 | internal_error | |
2411 | (__FILE__, __LINE__, | |
edefbb7c | 2412 | _("arm_store_return_value: Floating point model not supported")); |
08216dd7 RE |
2413 | break; |
2414 | } | |
34e8f22d | 2415 | } |
b508a996 RE |
2416 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
2417 | || TYPE_CODE (type) == TYPE_CODE_CHAR | |
2418 | || TYPE_CODE (type) == TYPE_CODE_BOOL | |
2419 | || TYPE_CODE (type) == TYPE_CODE_PTR | |
2420 | || TYPE_CODE (type) == TYPE_CODE_REF | |
2421 | || TYPE_CODE (type) == TYPE_CODE_ENUM) | |
2422 | { | |
2423 | if (TYPE_LENGTH (type) <= 4) | |
2424 | { | |
2425 | /* Values of one word or less are zero/sign-extended and | |
2426 | returned in r0. */ | |
7a5ea0d4 | 2427 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2428 | LONGEST val = unpack_long (type, valbuf); |
2429 | ||
7a5ea0d4 | 2430 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
b508a996 RE |
2431 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
2432 | } | |
2433 | else | |
2434 | { | |
2435 | /* Integral values greater than one word are stored in consecutive | |
2436 | registers starting with r0. This will always be a multiple of | |
2437 | the regiser size. */ | |
2438 | int len = TYPE_LENGTH (type); | |
2439 | int regno = ARM_A1_REGNUM; | |
2440 | ||
2441 | while (len > 0) | |
2442 | { | |
2443 | regcache_cooked_write (regs, regno++, valbuf); | |
7a5ea0d4 DJ |
2444 | len -= INT_REGISTER_SIZE; |
2445 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2446 | } |
2447 | } | |
2448 | } | |
34e8f22d | 2449 | else |
b508a996 RE |
2450 | { |
2451 | /* For a structure or union the behaviour is as if the value had | |
2452 | been stored to word-aligned memory and then loaded into | |
2453 | registers with 32-bit load instruction(s). */ | |
2454 | int len = TYPE_LENGTH (type); | |
2455 | int regno = ARM_A1_REGNUM; | |
7a5ea0d4 | 2456 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
b508a996 RE |
2457 | |
2458 | while (len > 0) | |
2459 | { | |
2460 | memcpy (tmpbuf, valbuf, | |
7a5ea0d4 | 2461 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
b508a996 | 2462 | regcache_cooked_write (regs, regno++, tmpbuf); |
7a5ea0d4 DJ |
2463 | len -= INT_REGISTER_SIZE; |
2464 | valbuf += INT_REGISTER_SIZE; | |
b508a996 RE |
2465 | } |
2466 | } | |
34e8f22d RE |
2467 | } |
2468 | ||
2af48f68 PB |
2469 | |
2470 | /* Handle function return values. */ | |
2471 | ||
2472 | static enum return_value_convention | |
c055b101 CV |
2473 | arm_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2474 | struct type *valtype, struct regcache *regcache, | |
2475 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2af48f68 | 2476 | { |
7c00367c MK |
2477 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2478 | ||
2af48f68 PB |
2479 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
2480 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
2481 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
2482 | { | |
7c00367c MK |
2483 | if (tdep->struct_return == pcc_struct_return |
2484 | || arm_return_in_memory (gdbarch, valtype)) | |
2af48f68 PB |
2485 | return RETURN_VALUE_STRUCT_CONVENTION; |
2486 | } | |
2487 | ||
2488 | if (writebuf) | |
2489 | arm_store_return_value (valtype, regcache, writebuf); | |
2490 | ||
2491 | if (readbuf) | |
2492 | arm_extract_return_value (valtype, regcache, readbuf); | |
2493 | ||
2494 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2495 | } | |
2496 | ||
2497 | ||
9df628e0 | 2498 | static int |
60ade65d | 2499 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
9df628e0 RE |
2500 | { |
2501 | CORE_ADDR jb_addr; | |
7a5ea0d4 | 2502 | char buf[INT_REGISTER_SIZE]; |
60ade65d | 2503 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); |
9df628e0 | 2504 | |
60ade65d | 2505 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
9df628e0 RE |
2506 | |
2507 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
7a5ea0d4 | 2508 | INT_REGISTER_SIZE)) |
9df628e0 RE |
2509 | return 0; |
2510 | ||
7a5ea0d4 | 2511 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
9df628e0 RE |
2512 | return 1; |
2513 | } | |
2514 | ||
faa95490 DJ |
2515 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
2516 | return the target PC. Otherwise return 0. */ | |
c906108c SS |
2517 | |
2518 | CORE_ADDR | |
52f729a7 | 2519 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2520 | { |
c5aa993b | 2521 | char *name; |
faa95490 | 2522 | int namelen; |
c906108c SS |
2523 | CORE_ADDR start_addr; |
2524 | ||
2525 | /* Find the starting address and name of the function containing the PC. */ | |
2526 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2527 | return 0; | |
2528 | ||
faa95490 DJ |
2529 | /* If PC is in a Thumb call or return stub, return the address of the |
2530 | target PC, which is in a register. The thunk functions are called | |
2531 | _call_via_xx, where x is the register name. The possible names | |
2532 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2533 | if (strncmp (name, "_call_via_", 10) == 0) |
2534 | { | |
ed9a39eb JM |
2535 | /* Use the name suffix to determine which register contains the |
2536 | target PC. */ | |
c5aa993b JM |
2537 | static char *table[15] = |
2538 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2539 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2540 | }; | |
c906108c | 2541 | int regno; |
faa95490 | 2542 | int offset = strlen (name) - 2; |
c906108c SS |
2543 | |
2544 | for (regno = 0; regno <= 14; regno++) | |
faa95490 | 2545 | if (strcmp (&name[offset], table[regno]) == 0) |
52f729a7 | 2546 | return get_frame_register_unsigned (frame, regno); |
c906108c | 2547 | } |
ed9a39eb | 2548 | |
faa95490 DJ |
2549 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
2550 | non-interworking calls to foo. We could decode the stubs | |
2551 | to find the target but it's easier to use the symbol table. */ | |
2552 | namelen = strlen (name); | |
2553 | if (name[0] == '_' && name[1] == '_' | |
2554 | && ((namelen > 2 + strlen ("_from_thumb") | |
2555 | && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb", | |
2556 | strlen ("_from_thumb")) == 0) | |
2557 | || (namelen > 2 + strlen ("_from_arm") | |
2558 | && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm", | |
2559 | strlen ("_from_arm")) == 0))) | |
2560 | { | |
2561 | char *target_name; | |
2562 | int target_len = namelen - 2; | |
2563 | struct minimal_symbol *minsym; | |
2564 | struct objfile *objfile; | |
2565 | struct obj_section *sec; | |
2566 | ||
2567 | if (name[namelen - 1] == 'b') | |
2568 | target_len -= strlen ("_from_thumb"); | |
2569 | else | |
2570 | target_len -= strlen ("_from_arm"); | |
2571 | ||
2572 | target_name = alloca (target_len + 1); | |
2573 | memcpy (target_name, name + 2, target_len); | |
2574 | target_name[target_len] = '\0'; | |
2575 | ||
2576 | sec = find_pc_section (pc); | |
2577 | objfile = (sec == NULL) ? NULL : sec->objfile; | |
2578 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); | |
2579 | if (minsym != NULL) | |
2580 | return SYMBOL_VALUE_ADDRESS (minsym); | |
2581 | else | |
2582 | return 0; | |
2583 | } | |
2584 | ||
c5aa993b | 2585 | return 0; /* not a stub */ |
c906108c SS |
2586 | } |
2587 | ||
afd7eef0 RE |
2588 | static void |
2589 | set_arm_command (char *args, int from_tty) | |
2590 | { | |
edefbb7c AC |
2591 | printf_unfiltered (_("\ |
2592 | \"set arm\" must be followed by an apporpriate subcommand.\n")); | |
afd7eef0 RE |
2593 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
2594 | } | |
2595 | ||
2596 | static void | |
2597 | show_arm_command (char *args, int from_tty) | |
2598 | { | |
26304000 | 2599 | cmd_show_list (showarmcmdlist, from_tty, ""); |
afd7eef0 RE |
2600 | } |
2601 | ||
28e97307 DJ |
2602 | static void |
2603 | arm_update_current_architecture (void) | |
fd50bc42 | 2604 | { |
28e97307 | 2605 | struct gdbarch_info info; |
fd50bc42 | 2606 | |
28e97307 DJ |
2607 | /* If the current architecture is not ARM, we have nothing to do. */ |
2608 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) | |
2609 | return; | |
fd50bc42 | 2610 | |
28e97307 DJ |
2611 | /* Update the architecture. */ |
2612 | gdbarch_info_init (&info); | |
fd50bc42 | 2613 | |
28e97307 DJ |
2614 | if (!gdbarch_update_p (info)) |
2615 | internal_error (__FILE__, __LINE__, "could not update architecture"); | |
fd50bc42 RE |
2616 | } |
2617 | ||
2618 | static void | |
2619 | set_fp_model_sfunc (char *args, int from_tty, | |
2620 | struct cmd_list_element *c) | |
2621 | { | |
2622 | enum arm_float_model fp_model; | |
2623 | ||
2624 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) | |
2625 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) | |
2626 | { | |
2627 | arm_fp_model = fp_model; | |
2628 | break; | |
2629 | } | |
2630 | ||
2631 | if (fp_model == ARM_FLOAT_LAST) | |
edefbb7c | 2632 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
fd50bc42 RE |
2633 | current_fp_model); |
2634 | ||
28e97307 | 2635 | arm_update_current_architecture (); |
fd50bc42 RE |
2636 | } |
2637 | ||
2638 | static void | |
08546159 AC |
2639 | show_fp_model (struct ui_file *file, int from_tty, |
2640 | struct cmd_list_element *c, const char *value) | |
fd50bc42 RE |
2641 | { |
2642 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2643 | ||
28e97307 | 2644 | if (arm_fp_model == ARM_FLOAT_AUTO |
fd50bc42 | 2645 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
28e97307 DJ |
2646 | fprintf_filtered (file, _("\ |
2647 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), | |
2648 | fp_model_strings[tdep->fp_model]); | |
2649 | else | |
2650 | fprintf_filtered (file, _("\ | |
2651 | The current ARM floating point model is \"%s\".\n"), | |
2652 | fp_model_strings[arm_fp_model]); | |
2653 | } | |
2654 | ||
2655 | static void | |
2656 | arm_set_abi (char *args, int from_tty, | |
2657 | struct cmd_list_element *c) | |
2658 | { | |
2659 | enum arm_abi_kind arm_abi; | |
2660 | ||
2661 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) | |
2662 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) | |
2663 | { | |
2664 | arm_abi_global = arm_abi; | |
2665 | break; | |
2666 | } | |
2667 | ||
2668 | if (arm_abi == ARM_ABI_LAST) | |
2669 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), | |
2670 | arm_abi_string); | |
2671 | ||
2672 | arm_update_current_architecture (); | |
2673 | } | |
2674 | ||
2675 | static void | |
2676 | arm_show_abi (struct ui_file *file, int from_tty, | |
2677 | struct cmd_list_element *c, const char *value) | |
2678 | { | |
2679 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2680 | ||
2681 | if (arm_abi_global == ARM_ABI_AUTO | |
2682 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) | |
2683 | fprintf_filtered (file, _("\ | |
2684 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), | |
2685 | arm_abi_strings[tdep->arm_abi]); | |
2686 | else | |
2687 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), | |
2688 | arm_abi_string); | |
fd50bc42 RE |
2689 | } |
2690 | ||
0428b8f5 DJ |
2691 | static void |
2692 | arm_show_fallback_mode (struct ui_file *file, int from_tty, | |
2693 | struct cmd_list_element *c, const char *value) | |
2694 | { | |
2695 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2696 | ||
2697 | fprintf_filtered (file, _("\ | |
2698 | The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"), | |
2699 | arm_fallback_mode_string); | |
2700 | } | |
2701 | ||
2702 | static void | |
2703 | arm_show_force_mode (struct ui_file *file, int from_tty, | |
2704 | struct cmd_list_element *c, const char *value) | |
2705 | { | |
2706 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2707 | ||
2708 | fprintf_filtered (file, _("\ | |
2709 | The current execution mode assumed (even when symbols are available) is \"%s\".\n"), | |
2710 | arm_force_mode_string); | |
2711 | } | |
2712 | ||
afd7eef0 RE |
2713 | /* If the user changes the register disassembly style used for info |
2714 | register and other commands, we have to also switch the style used | |
2715 | in opcodes for disassembly output. This function is run in the "set | |
2716 | arm disassembly" command, and does that. */ | |
bc90b915 FN |
2717 | |
2718 | static void | |
afd7eef0 | 2719 | set_disassembly_style_sfunc (char *args, int from_tty, |
bc90b915 FN |
2720 | struct cmd_list_element *c) |
2721 | { | |
afd7eef0 | 2722 | set_disassembly_style (); |
bc90b915 FN |
2723 | } |
2724 | \f | |
966fbf70 | 2725 | /* Return the ARM register name corresponding to register I. */ |
a208b0cb | 2726 | static const char * |
d93859e2 | 2727 | arm_register_name (struct gdbarch *gdbarch, int i) |
966fbf70 | 2728 | { |
ff6f572f DJ |
2729 | if (i >= ARRAY_SIZE (arm_register_names)) |
2730 | /* These registers are only supported on targets which supply | |
2731 | an XML description. */ | |
2732 | return ""; | |
2733 | ||
966fbf70 RE |
2734 | return arm_register_names[i]; |
2735 | } | |
2736 | ||
bc90b915 | 2737 | static void |
afd7eef0 | 2738 | set_disassembly_style (void) |
bc90b915 | 2739 | { |
123dc839 | 2740 | int current; |
bc90b915 | 2741 | |
123dc839 DJ |
2742 | /* Find the style that the user wants. */ |
2743 | for (current = 0; current < num_disassembly_options; current++) | |
2744 | if (disassembly_style == valid_disassembly_styles[current]) | |
2745 | break; | |
2746 | gdb_assert (current < num_disassembly_options); | |
bc90b915 | 2747 | |
94c30b78 | 2748 | /* Synchronize the disassembler. */ |
bc90b915 FN |
2749 | set_arm_regname_option (current); |
2750 | } | |
2751 | ||
082fc60d RE |
2752 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2753 | function. */ | |
2754 | ||
2755 | static int | |
2756 | coff_sym_is_thumb (int val) | |
2757 | { | |
2758 | return (val == C_THUMBEXT || | |
2759 | val == C_THUMBSTAT || | |
2760 | val == C_THUMBEXTFUNC || | |
2761 | val == C_THUMBSTATFUNC || | |
2762 | val == C_THUMBLABEL); | |
2763 | } | |
2764 | ||
2765 | /* arm_coff_make_msymbol_special() | |
2766 | arm_elf_make_msymbol_special() | |
2767 | ||
2768 | These functions test whether the COFF or ELF symbol corresponds to | |
2769 | an address in thumb code, and set a "special" bit in a minimal | |
2770 | symbol to indicate that it does. */ | |
2771 | ||
34e8f22d | 2772 | static void |
082fc60d RE |
2773 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
2774 | { | |
2775 | /* Thumb symbols are of type STT_LOPROC, (synonymous with | |
2776 | STT_ARM_TFUNC). */ | |
2777 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) | |
2778 | == STT_LOPROC) | |
2779 | MSYMBOL_SET_SPECIAL (msym); | |
2780 | } | |
2781 | ||
34e8f22d | 2782 | static void |
082fc60d RE |
2783 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
2784 | { | |
2785 | if (coff_sym_is_thumb (val)) | |
2786 | MSYMBOL_SET_SPECIAL (msym); | |
2787 | } | |
2788 | ||
756fe439 | 2789 | static void |
61a1198a | 2790 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
756fe439 | 2791 | { |
61a1198a | 2792 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
756fe439 DJ |
2793 | |
2794 | /* If necessary, set the T bit. */ | |
2795 | if (arm_apcs_32) | |
2796 | { | |
61a1198a UW |
2797 | ULONGEST val; |
2798 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); | |
756fe439 | 2799 | if (arm_pc_is_thumb (pc)) |
b39cc962 | 2800 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T); |
756fe439 | 2801 | else |
61a1198a | 2802 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
b39cc962 | 2803 | val & ~(ULONGEST) CPSR_T); |
756fe439 DJ |
2804 | } |
2805 | } | |
123dc839 DJ |
2806 | |
2807 | static struct value * | |
2808 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) | |
2809 | { | |
2810 | const int *reg_p = baton; | |
2811 | return value_of_register (*reg_p, frame); | |
2812 | } | |
97e03143 | 2813 | \f |
70f80edf JT |
2814 | static enum gdb_osabi |
2815 | arm_elf_osabi_sniffer (bfd *abfd) | |
97e03143 | 2816 | { |
2af48f68 | 2817 | unsigned int elfosabi; |
70f80edf | 2818 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
97e03143 | 2819 | |
70f80edf | 2820 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
97e03143 | 2821 | |
28e97307 DJ |
2822 | if (elfosabi == ELFOSABI_ARM) |
2823 | /* GNU tools use this value. Check note sections in this case, | |
2824 | as well. */ | |
2825 | bfd_map_over_sections (abfd, | |
2826 | generic_elf_osabi_sniff_abi_tag_sections, | |
2827 | &osabi); | |
97e03143 | 2828 | |
28e97307 | 2829 | /* Anything else will be handled by the generic ELF sniffer. */ |
70f80edf | 2830 | return osabi; |
97e03143 RE |
2831 | } |
2832 | ||
70f80edf | 2833 | \f |
da3c6d4a MS |
2834 | /* Initialize the current architecture based on INFO. If possible, |
2835 | re-use an architecture from ARCHES, which is a list of | |
2836 | architectures already created during this debugging session. | |
97e03143 | 2837 | |
da3c6d4a MS |
2838 | Called e.g. at program startup, when reading a core file, and when |
2839 | reading a binary file. */ | |
97e03143 | 2840 | |
39bbf761 RE |
2841 | static struct gdbarch * |
2842 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2843 | { | |
97e03143 | 2844 | struct gdbarch_tdep *tdep; |
39bbf761 | 2845 | struct gdbarch *gdbarch; |
28e97307 DJ |
2846 | struct gdbarch_list *best_arch; |
2847 | enum arm_abi_kind arm_abi = arm_abi_global; | |
2848 | enum arm_float_model fp_model = arm_fp_model; | |
123dc839 DJ |
2849 | struct tdesc_arch_data *tdesc_data = NULL; |
2850 | int i; | |
ff6f572f | 2851 | int have_fpa_registers = 1; |
123dc839 DJ |
2852 | |
2853 | /* Check any target description for validity. */ | |
2854 | if (tdesc_has_registers (info.target_desc)) | |
2855 | { | |
2856 | /* For most registers we require GDB's default names; but also allow | |
2857 | the numeric names for sp / lr / pc, as a convenience. */ | |
2858 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; | |
2859 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; | |
2860 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; | |
2861 | ||
2862 | const struct tdesc_feature *feature; | |
2863 | int i, valid_p; | |
2864 | ||
2865 | feature = tdesc_find_feature (info.target_desc, | |
2866 | "org.gnu.gdb.arm.core"); | |
2867 | if (feature == NULL) | |
2868 | return NULL; | |
2869 | ||
2870 | tdesc_data = tdesc_data_alloc (); | |
2871 | ||
2872 | valid_p = 1; | |
2873 | for (i = 0; i < ARM_SP_REGNUM; i++) | |
2874 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
2875 | arm_register_names[i]); | |
2876 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2877 | ARM_SP_REGNUM, | |
2878 | arm_sp_names); | |
2879 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2880 | ARM_LR_REGNUM, | |
2881 | arm_lr_names); | |
2882 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
2883 | ARM_PC_REGNUM, | |
2884 | arm_pc_names); | |
2885 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
2886 | ARM_PS_REGNUM, "cpsr"); | |
2887 | ||
2888 | if (!valid_p) | |
2889 | { | |
2890 | tdesc_data_cleanup (tdesc_data); | |
2891 | return NULL; | |
2892 | } | |
2893 | ||
2894 | feature = tdesc_find_feature (info.target_desc, | |
2895 | "org.gnu.gdb.arm.fpa"); | |
2896 | if (feature != NULL) | |
2897 | { | |
2898 | valid_p = 1; | |
2899 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) | |
2900 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
2901 | arm_register_names[i]); | |
2902 | if (!valid_p) | |
2903 | { | |
2904 | tdesc_data_cleanup (tdesc_data); | |
2905 | return NULL; | |
2906 | } | |
2907 | } | |
ff6f572f DJ |
2908 | else |
2909 | have_fpa_registers = 0; | |
2910 | ||
2911 | feature = tdesc_find_feature (info.target_desc, | |
2912 | "org.gnu.gdb.xscale.iwmmxt"); | |
2913 | if (feature != NULL) | |
2914 | { | |
2915 | static const char *const iwmmxt_names[] = { | |
2916 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", | |
2917 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", | |
2918 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", | |
2919 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", | |
2920 | }; | |
2921 | ||
2922 | valid_p = 1; | |
2923 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) | |
2924 | valid_p | |
2925 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
2926 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2927 | ||
2928 | /* Check for the control registers, but do not fail if they | |
2929 | are missing. */ | |
2930 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) | |
2931 | tdesc_numbered_register (feature, tdesc_data, i, | |
2932 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2933 | ||
2934 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) | |
2935 | valid_p | |
2936 | &= tdesc_numbered_register (feature, tdesc_data, i, | |
2937 | iwmmxt_names[i - ARM_WR0_REGNUM]); | |
2938 | ||
2939 | if (!valid_p) | |
2940 | { | |
2941 | tdesc_data_cleanup (tdesc_data); | |
2942 | return NULL; | |
2943 | } | |
2944 | } | |
123dc839 | 2945 | } |
39bbf761 | 2946 | |
28e97307 DJ |
2947 | /* If we have an object to base this architecture on, try to determine |
2948 | its ABI. */ | |
39bbf761 | 2949 | |
28e97307 | 2950 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
97e03143 | 2951 | { |
6b26d61a | 2952 | int ei_osabi, e_flags; |
28e97307 | 2953 | |
4be87837 | 2954 | switch (bfd_get_flavour (info.abfd)) |
97e03143 | 2955 | { |
4be87837 DJ |
2956 | case bfd_target_aout_flavour: |
2957 | /* Assume it's an old APCS-style ABI. */ | |
28e97307 | 2958 | arm_abi = ARM_ABI_APCS; |
4be87837 | 2959 | break; |
97e03143 | 2960 | |
4be87837 DJ |
2961 | case bfd_target_coff_flavour: |
2962 | /* Assume it's an old APCS-style ABI. */ | |
2963 | /* XXX WinCE? */ | |
28e97307 DJ |
2964 | arm_abi = ARM_ABI_APCS; |
2965 | break; | |
2966 | ||
2967 | case bfd_target_elf_flavour: | |
2968 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; | |
6b26d61a MK |
2969 | e_flags = elf_elfheader (info.abfd)->e_flags; |
2970 | ||
28e97307 DJ |
2971 | if (ei_osabi == ELFOSABI_ARM) |
2972 | { | |
2973 | /* GNU tools used to use this value, but do not for EABI | |
6b26d61a MK |
2974 | objects. There's nowhere to tag an EABI version |
2975 | anyway, so assume APCS. */ | |
28e97307 DJ |
2976 | arm_abi = ARM_ABI_APCS; |
2977 | } | |
2978 | else if (ei_osabi == ELFOSABI_NONE) | |
2979 | { | |
6b26d61a | 2980 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
28e97307 DJ |
2981 | |
2982 | switch (eabi_ver) | |
2983 | { | |
2984 | case EF_ARM_EABI_UNKNOWN: | |
2985 | /* Assume GNU tools. */ | |
2986 | arm_abi = ARM_ABI_APCS; | |
2987 | break; | |
2988 | ||
2989 | case EF_ARM_EABI_VER4: | |
625b5003 | 2990 | case EF_ARM_EABI_VER5: |
28e97307 | 2991 | arm_abi = ARM_ABI_AAPCS; |
2af48f68 PB |
2992 | /* EABI binaries default to VFP float ordering. */ |
2993 | if (fp_model == ARM_FLOAT_AUTO) | |
2994 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
2995 | break; |
2996 | ||
2997 | default: | |
6b26d61a | 2998 | /* Leave it as "auto". */ |
28e97307 | 2999 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
6b26d61a MK |
3000 | break; |
3001 | } | |
3002 | } | |
3003 | ||
3004 | if (fp_model == ARM_FLOAT_AUTO) | |
3005 | { | |
3006 | int e_flags = elf_elfheader (info.abfd)->e_flags; | |
3007 | ||
3008 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) | |
3009 | { | |
3010 | case 0: | |
3011 | /* Leave it as "auto". Strictly speaking this case | |
3012 | means FPA, but almost nobody uses that now, and | |
3013 | many toolchains fail to set the appropriate bits | |
3014 | for the floating-point model they use. */ | |
3015 | break; | |
3016 | case EF_ARM_SOFT_FLOAT: | |
3017 | fp_model = ARM_FLOAT_SOFT_FPA; | |
3018 | break; | |
3019 | case EF_ARM_VFP_FLOAT: | |
3020 | fp_model = ARM_FLOAT_VFP; | |
3021 | break; | |
3022 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: | |
3023 | fp_model = ARM_FLOAT_SOFT_VFP; | |
28e97307 DJ |
3024 | break; |
3025 | } | |
3026 | } | |
4be87837 | 3027 | break; |
97e03143 | 3028 | |
4be87837 | 3029 | default: |
28e97307 | 3030 | /* Leave it as "auto". */ |
50ceaba5 | 3031 | break; |
97e03143 RE |
3032 | } |
3033 | } | |
3034 | ||
28e97307 DJ |
3035 | /* If there is already a candidate, use it. */ |
3036 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
3037 | best_arch != NULL; | |
3038 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
3039 | { | |
b8926edc DJ |
3040 | if (arm_abi != ARM_ABI_AUTO |
3041 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) | |
28e97307 DJ |
3042 | continue; |
3043 | ||
b8926edc DJ |
3044 | if (fp_model != ARM_FLOAT_AUTO |
3045 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) | |
28e97307 DJ |
3046 | continue; |
3047 | ||
3048 | /* Found a match. */ | |
3049 | break; | |
3050 | } | |
97e03143 | 3051 | |
28e97307 | 3052 | if (best_arch != NULL) |
123dc839 DJ |
3053 | { |
3054 | if (tdesc_data != NULL) | |
3055 | tdesc_data_cleanup (tdesc_data); | |
3056 | return best_arch->gdbarch; | |
3057 | } | |
28e97307 DJ |
3058 | |
3059 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); | |
97e03143 RE |
3060 | gdbarch = gdbarch_alloc (&info, tdep); |
3061 | ||
28e97307 DJ |
3062 | /* Record additional information about the architecture we are defining. |
3063 | These are gdbarch discriminators, like the OSABI. */ | |
3064 | tdep->arm_abi = arm_abi; | |
3065 | tdep->fp_model = fp_model; | |
ff6f572f | 3066 | tdep->have_fpa_registers = have_fpa_registers; |
08216dd7 RE |
3067 | |
3068 | /* Breakpoints. */ | |
67255d04 RE |
3069 | switch (info.byte_order) |
3070 | { | |
3071 | case BFD_ENDIAN_BIG: | |
66e810cd RE |
3072 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
3073 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); | |
3074 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; | |
3075 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); | |
3076 | ||
67255d04 RE |
3077 | break; |
3078 | ||
3079 | case BFD_ENDIAN_LITTLE: | |
66e810cd RE |
3080 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
3081 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); | |
3082 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; | |
3083 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); | |
3084 | ||
67255d04 RE |
3085 | break; |
3086 | ||
3087 | default: | |
3088 | internal_error (__FILE__, __LINE__, | |
edefbb7c | 3089 | _("arm_gdbarch_init: bad byte order for float format")); |
67255d04 RE |
3090 | } |
3091 | ||
d7b486e7 RE |
3092 | /* On ARM targets char defaults to unsigned. */ |
3093 | set_gdbarch_char_signed (gdbarch, 0); | |
3094 | ||
9df628e0 | 3095 | /* This should be low enough for everything. */ |
97e03143 | 3096 | tdep->lowest_pc = 0x20; |
94c30b78 | 3097 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
97e03143 | 3098 | |
7c00367c MK |
3099 | /* The default, for both APCS and AAPCS, is to return small |
3100 | structures in registers. */ | |
3101 | tdep->struct_return = reg_struct_return; | |
3102 | ||
2dd604e7 | 3103 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
f53f0d0b | 3104 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
39bbf761 | 3105 | |
756fe439 DJ |
3106 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
3107 | ||
148754e5 | 3108 | /* Frame handling. */ |
a262aec2 | 3109 | set_gdbarch_dummy_id (gdbarch, arm_dummy_id); |
eb5492fa DJ |
3110 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
3111 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); | |
3112 | ||
eb5492fa | 3113 | frame_base_set_default (gdbarch, &arm_normal_base); |
148754e5 | 3114 | |
34e8f22d RE |
3115 | /* Address manipulation. */ |
3116 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); | |
3117 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); | |
3118 | ||
34e8f22d RE |
3119 | /* Advance PC across function entry code. */ |
3120 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); | |
3121 | ||
190dce09 UW |
3122 | /* Skip trampolines. */ |
3123 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); | |
3124 | ||
34e8f22d RE |
3125 | /* The stack grows downward. */ |
3126 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3127 | ||
3128 | /* Breakpoint manipulation. */ | |
3129 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); | |
34e8f22d RE |
3130 | |
3131 | /* Information about registers, etc. */ | |
0ba6dca9 | 3132 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
34e8f22d RE |
3133 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
3134 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); | |
ff6f572f | 3135 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
7a5ea0d4 | 3136 | set_gdbarch_register_type (gdbarch, arm_register_type); |
34e8f22d | 3137 | |
ff6f572f DJ |
3138 | /* This "info float" is FPA-specific. Use the generic version if we |
3139 | do not have FPA. */ | |
3140 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) | |
3141 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); | |
3142 | ||
26216b98 | 3143 | /* Internal <-> external register number maps. */ |
ff6f572f DJ |
3144 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
3145 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); | |
26216b98 AC |
3146 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
3147 | ||
34e8f22d RE |
3148 | set_gdbarch_register_name (gdbarch, arm_register_name); |
3149 | ||
3150 | /* Returning results. */ | |
2af48f68 | 3151 | set_gdbarch_return_value (gdbarch, arm_return_value); |
34e8f22d | 3152 | |
03d48a7d RE |
3153 | /* Disassembly. */ |
3154 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); | |
3155 | ||
34e8f22d RE |
3156 | /* Minsymbol frobbing. */ |
3157 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); | |
3158 | set_gdbarch_coff_make_msymbol_special (gdbarch, | |
3159 | arm_coff_make_msymbol_special); | |
3160 | ||
0d5de010 DJ |
3161 | /* Virtual tables. */ |
3162 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
3163 | ||
97e03143 | 3164 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
4be87837 | 3165 | gdbarch_init_osabi (info, gdbarch); |
97e03143 | 3166 | |
b39cc962 DJ |
3167 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
3168 | ||
eb5492fa | 3169 | /* Add some default predicates. */ |
a262aec2 DJ |
3170 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
3171 | dwarf2_append_unwinders (gdbarch); | |
3172 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); | |
eb5492fa | 3173 | |
97e03143 RE |
3174 | /* Now we have tuned the configuration, set a few final things, |
3175 | based on what the OS ABI has told us. */ | |
3176 | ||
b8926edc DJ |
3177 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
3178 | binaries are always marked. */ | |
3179 | if (tdep->arm_abi == ARM_ABI_AUTO) | |
3180 | tdep->arm_abi = ARM_ABI_APCS; | |
3181 | ||
3182 | /* We used to default to FPA for generic ARM, but almost nobody | |
3183 | uses that now, and we now provide a way for the user to force | |
3184 | the model. So default to the most useful variant. */ | |
3185 | if (tdep->fp_model == ARM_FLOAT_AUTO) | |
3186 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; | |
3187 | ||
9df628e0 RE |
3188 | if (tdep->jb_pc >= 0) |
3189 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); | |
3190 | ||
08216dd7 | 3191 | /* Floating point sizes and format. */ |
8da61cc4 | 3192 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
b8926edc | 3193 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
08216dd7 | 3194 | { |
8da61cc4 DJ |
3195 | set_gdbarch_double_format |
3196 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
3197 | set_gdbarch_long_double_format | |
3198 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); | |
3199 | } | |
3200 | else | |
3201 | { | |
3202 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
3203 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
08216dd7 RE |
3204 | } |
3205 | ||
123dc839 | 3206 | if (tdesc_data) |
7cc46491 | 3207 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
123dc839 DJ |
3208 | |
3209 | /* Add standard register aliases. We add aliases even for those | |
3210 | nanes which are used by the current architecture - it's simpler, | |
3211 | and does no harm, since nothing ever lists user registers. */ | |
3212 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) | |
3213 | user_reg_add (gdbarch, arm_register_aliases[i].name, | |
3214 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); | |
3215 | ||
39bbf761 RE |
3216 | return gdbarch; |
3217 | } | |
3218 | ||
97e03143 | 3219 | static void |
2af46ca0 | 3220 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
97e03143 | 3221 | { |
2af46ca0 | 3222 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
97e03143 RE |
3223 | |
3224 | if (tdep == NULL) | |
3225 | return; | |
3226 | ||
edefbb7c | 3227 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
97e03143 RE |
3228 | (unsigned long) tdep->lowest_pc); |
3229 | } | |
3230 | ||
a78f21af AC |
3231 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
3232 | ||
c906108c | 3233 | void |
ed9a39eb | 3234 | _initialize_arm_tdep (void) |
c906108c | 3235 | { |
bc90b915 FN |
3236 | struct ui_file *stb; |
3237 | long length; | |
26304000 | 3238 | struct cmd_list_element *new_set, *new_show; |
53904c9e AC |
3239 | const char *setname; |
3240 | const char *setdesc; | |
4bd7b427 | 3241 | const char *const *regnames; |
bc90b915 FN |
3242 | int numregs, i, j; |
3243 | static char *helptext; | |
edefbb7c AC |
3244 | char regdesc[1024], *rdptr = regdesc; |
3245 | size_t rest = sizeof (regdesc); | |
085dd6e6 | 3246 | |
42cf1509 | 3247 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
97e03143 | 3248 | |
70f80edf JT |
3249 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
3250 | gdbarch_register_osabi_sniffer (bfd_arch_arm, | |
3251 | bfd_target_elf_flavour, | |
3252 | arm_elf_osabi_sniffer); | |
3253 | ||
94c30b78 | 3254 | /* Get the number of possible sets of register names defined in opcodes. */ |
afd7eef0 RE |
3255 | num_disassembly_options = get_arm_regname_num_options (); |
3256 | ||
3257 | /* Add root prefix command for all "set arm"/"show arm" commands. */ | |
3258 | add_prefix_cmd ("arm", no_class, set_arm_command, | |
edefbb7c | 3259 | _("Various ARM-specific commands."), |
afd7eef0 RE |
3260 | &setarmcmdlist, "set arm ", 0, &setlist); |
3261 | ||
3262 | add_prefix_cmd ("arm", no_class, show_arm_command, | |
edefbb7c | 3263 | _("Various ARM-specific commands."), |
afd7eef0 | 3264 | &showarmcmdlist, "show arm ", 0, &showlist); |
bc90b915 | 3265 | |
94c30b78 | 3266 | /* Sync the opcode insn printer with our register viewer. */ |
bc90b915 | 3267 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 3268 | |
eefe576e AC |
3269 | /* Initialize the array that will be passed to |
3270 | add_setshow_enum_cmd(). */ | |
afd7eef0 RE |
3271 | valid_disassembly_styles |
3272 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); | |
3273 | for (i = 0; i < num_disassembly_options; i++) | |
bc90b915 FN |
3274 | { |
3275 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
afd7eef0 | 3276 | valid_disassembly_styles[i] = setname; |
edefbb7c AC |
3277 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
3278 | rdptr += length; | |
3279 | rest -= length; | |
123dc839 DJ |
3280 | /* When we find the default names, tell the disassembler to use |
3281 | them. */ | |
bc90b915 FN |
3282 | if (!strcmp (setname, "std")) |
3283 | { | |
afd7eef0 | 3284 | disassembly_style = setname; |
bc90b915 FN |
3285 | set_arm_regname_option (i); |
3286 | } | |
3287 | } | |
94c30b78 | 3288 | /* Mark the end of valid options. */ |
afd7eef0 | 3289 | valid_disassembly_styles[num_disassembly_options] = NULL; |
c906108c | 3290 | |
edefbb7c AC |
3291 | /* Create the help text. */ |
3292 | stb = mem_fileopen (); | |
3293 | fprintf_unfiltered (stb, "%s%s%s", | |
3294 | _("The valid values are:\n"), | |
3295 | regdesc, | |
3296 | _("The default is \"std\".")); | |
bc90b915 FN |
3297 | helptext = ui_file_xstrdup (stb, &length); |
3298 | ui_file_delete (stb); | |
ed9a39eb | 3299 | |
edefbb7c AC |
3300 | add_setshow_enum_cmd("disassembler", no_class, |
3301 | valid_disassembly_styles, &disassembly_style, | |
3302 | _("Set the disassembly style."), | |
3303 | _("Show the disassembly style."), | |
3304 | helptext, | |
2c5b56ce | 3305 | set_disassembly_style_sfunc, |
7915a72c | 3306 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
7376b4c2 | 3307 | &setarmcmdlist, &showarmcmdlist); |
edefbb7c AC |
3308 | |
3309 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, | |
3310 | _("Set usage of ARM 32-bit mode."), | |
3311 | _("Show usage of ARM 32-bit mode."), | |
3312 | _("When off, a 26-bit PC will be used."), | |
2c5b56ce | 3313 | NULL, |
7915a72c | 3314 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
26304000 | 3315 | &setarmcmdlist, &showarmcmdlist); |
c906108c | 3316 | |
fd50bc42 | 3317 | /* Add a command to allow the user to force the FPU model. */ |
edefbb7c AC |
3318 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
3319 | _("Set the floating point type."), | |
3320 | _("Show the floating point type."), | |
3321 | _("auto - Determine the FP typefrom the OS-ABI.\n\ | |
3322 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ | |
3323 | fpa - FPA co-processor (GCC compiled).\n\ | |
3324 | softvfp - Software FP with pure-endian doubles.\n\ | |
3325 | vfp - VFP co-processor."), | |
edefbb7c | 3326 | set_fp_model_sfunc, show_fp_model, |
7376b4c2 | 3327 | &setarmcmdlist, &showarmcmdlist); |
fd50bc42 | 3328 | |
28e97307 DJ |
3329 | /* Add a command to allow the user to force the ABI. */ |
3330 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, | |
3331 | _("Set the ABI."), | |
3332 | _("Show the ABI."), | |
3333 | NULL, arm_set_abi, arm_show_abi, | |
3334 | &setarmcmdlist, &showarmcmdlist); | |
3335 | ||
0428b8f5 DJ |
3336 | /* Add two commands to allow the user to force the assumed |
3337 | execution mode. */ | |
3338 | add_setshow_enum_cmd ("fallback-mode", class_support, | |
3339 | arm_mode_strings, &arm_fallback_mode_string, | |
3340 | _("Set the mode assumed when symbols are unavailable."), | |
3341 | _("Show the mode assumed when symbols are unavailable."), | |
3342 | NULL, NULL, arm_show_fallback_mode, | |
3343 | &setarmcmdlist, &showarmcmdlist); | |
3344 | add_setshow_enum_cmd ("force-mode", class_support, | |
3345 | arm_mode_strings, &arm_force_mode_string, | |
3346 | _("Set the mode assumed even when symbols are available."), | |
3347 | _("Show the mode assumed even when symbols are available."), | |
3348 | NULL, NULL, arm_show_force_mode, | |
3349 | &setarmcmdlist, &showarmcmdlist); | |
3350 | ||
6529d2dd | 3351 | /* Debugging flag. */ |
edefbb7c AC |
3352 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
3353 | _("Set ARM debugging."), | |
3354 | _("Show ARM debugging."), | |
3355 | _("When on, arm-specific debugging is enabled."), | |
2c5b56ce | 3356 | NULL, |
7915a72c | 3357 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
26304000 | 3358 | &setdebuglist, &showdebuglist); |
c906108c | 3359 | } |