Commit | Line | Data |
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ed9a39eb | 1 | /* Common target dependent code for GDB on ARM systems. |
b6ba6518 | 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
c3b4394c | 3 | 2001, 2002 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
27 | #include "symfile.h" | |
28 | #include "gdb_string.h" | |
29 | #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ | |
e8b09175 | 30 | #include "dis-asm.h" /* For register flavors. */ |
30f6df08 | 31 | #include <ctype.h> /* for isupper () */ |
4e052eda | 32 | #include "regcache.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
a42dd537 | 35 | #include "solib-svr4.h" |
c906108c | 36 | |
2a451106 KB |
37 | /* Each OS has a different mechanism for accessing the various |
38 | registers stored in the sigcontext structure. | |
39 | ||
40 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or | |
41 | function pointer) which may be used to determine the addresses | |
42 | of the various saved registers in the sigcontext structure. | |
43 | ||
44 | For the ARM target, there are three parameters to this function. | |
45 | The first is the pc value of the frame under consideration, the | |
46 | second the stack pointer of this frame, and the last is the | |
47 | register number to fetch. | |
48 | ||
49 | If the tm.h file does not define this macro, then it's assumed that | |
50 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to | |
51 | be 0. | |
52 | ||
53 | When it comes time to multi-arching this code, see the identically | |
54 | named machinery in ia64-tdep.c for an example of how it could be | |
55 | done. It should not be necessary to modify the code below where | |
56 | this macro is used. */ | |
57 | ||
3bb04bdd AC |
58 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
59 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P | |
60 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 | |
61 | #endif | |
62 | #else | |
63 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 | |
64 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 | |
2a451106 KB |
65 | #endif |
66 | ||
ed9a39eb JM |
67 | extern void _initialize_arm_tdep (void); |
68 | ||
bc90b915 FN |
69 | /* Number of different reg name sets (options). */ |
70 | static int num_flavor_options; | |
71 | ||
72 | /* We have more registers than the disassembler as gdb can print the value | |
73 | of special registers as well. | |
74 | The general register names are overwritten by whatever is being used by | |
75 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ | |
76 | ||
77 | /* Initial value: Register names used in ARM's ISA documentation. */ | |
78 | static char * arm_register_name_strings[] = | |
da59e081 JM |
79 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
80 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
81 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
82 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ | |
83 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
84 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
bc90b915 | 85 | "fps", "cpsr" }; /* 24 25 */ |
966fbf70 | 86 | static char **arm_register_names = arm_register_name_strings; |
ed9a39eb | 87 | |
bc90b915 | 88 | /* Valid register name flavors. */ |
53904c9e | 89 | static const char **valid_flavors; |
ed9a39eb | 90 | |
bc90b915 | 91 | /* Disassembly flavor to use. Default to "std" register names. */ |
53904c9e | 92 | static const char *disassembly_flavor; |
bc90b915 | 93 | static int current_option; /* Index to that option in the opcodes table. */ |
96baa820 | 94 | |
ed9a39eb JM |
95 | /* This is used to keep the bfd arch_info in sync with the disassembly |
96 | flavor. */ | |
97 | static void set_disassembly_flavor_sfunc(char *, int, | |
98 | struct cmd_list_element *); | |
99 | static void set_disassembly_flavor (void); | |
100 | ||
101 | static void convert_from_extended (void *ptr, void *dbl); | |
102 | ||
103 | /* Define other aspects of the stack frame. We keep the offsets of | |
104 | all saved registers, 'cause we need 'em a lot! We also keep the | |
105 | current size of the stack frame, and the offset of the frame | |
106 | pointer from the stack pointer (for frameless functions, and when | |
107 | we're still in the prologue of a function with a frame) */ | |
108 | ||
109 | struct frame_extra_info | |
c3b4394c RE |
110 | { |
111 | int framesize; | |
112 | int frameoffset; | |
113 | int framereg; | |
114 | }; | |
ed9a39eb | 115 | |
bc90b915 FN |
116 | /* Addresses for calling Thumb functions have the bit 0 set. |
117 | Here are some macros to test, set, or clear bit 0 of addresses. */ | |
118 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
119 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
120 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
121 | ||
ed9a39eb JM |
122 | /* Will a function return an aggregate type in memory or in a |
123 | register? Return 0 if an aggregate type can be returned in a | |
124 | register, 1 if it must be returned in memory. */ | |
085dd6e6 | 125 | |
c906108c | 126 | int |
ed9a39eb | 127 | arm_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 128 | { |
ed9a39eb JM |
129 | int nRc; |
130 | register enum type_code code; | |
131 | ||
132 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
133 | registers. For an aggregate type to be integer like, its size | |
134 | must be less than or equal to REGISTER_SIZE and the offset of | |
135 | each addressable subfield must be zero. Note that bit fields are | |
136 | not addressable, and all addressable subfields of unions always | |
137 | start at offset zero. | |
138 | ||
139 | This function is based on the behaviour of GCC 2.95.1. | |
140 | See: gcc/arm.c: arm_return_in_memory() for details. | |
141 | ||
142 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
143 | parameters correctly for a function returning the following | |
144 | structure: struct { float f;}; This should be returned in memory, | |
145 | not a register. Richard Earnshaw sent me a patch, but I do not | |
146 | know of any way to detect if a function like the above has been | |
147 | compiled with the correct calling convention. */ | |
148 | ||
149 | /* All aggregate types that won't fit in a register must be returned | |
150 | in memory. */ | |
151 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
152 | { | |
153 | return 1; | |
154 | } | |
155 | ||
156 | /* The only aggregate types that can be returned in a register are | |
157 | structs and unions. Arrays must be returned in memory. */ | |
158 | code = TYPE_CODE (type); | |
159 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
160 | { | |
161 | return 1; | |
162 | } | |
163 | ||
164 | /* Assume all other aggregate types can be returned in a register. | |
165 | Run a check for structures, unions and arrays. */ | |
166 | nRc = 0; | |
167 | ||
168 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
169 | { | |
170 | int i; | |
171 | /* Need to check if this struct/union is "integer" like. For | |
172 | this to be true, its size must be less than or equal to | |
173 | REGISTER_SIZE and the offset of each addressable subfield | |
174 | must be zero. Note that bit fields are not addressable, and | |
175 | unions always start at offset zero. If any of the subfields | |
176 | is a floating point type, the struct/union cannot be an | |
177 | integer type. */ | |
178 | ||
179 | /* For each field in the object, check: | |
180 | 1) Is it FP? --> yes, nRc = 1; | |
181 | 2) Is it addressable (bitpos != 0) and | |
182 | not packed (bitsize == 0)? | |
183 | --> yes, nRc = 1 | |
184 | */ | |
185 | ||
186 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
187 | { | |
188 | enum type_code field_type_code; | |
189 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
190 | ||
191 | /* Is it a floating point type field? */ | |
192 | if (field_type_code == TYPE_CODE_FLT) | |
193 | { | |
194 | nRc = 1; | |
195 | break; | |
196 | } | |
197 | ||
198 | /* If bitpos != 0, then we have to care about it. */ | |
199 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
200 | { | |
201 | /* Bitfields are not addressable. If the field bitsize is | |
202 | zero, then the field is not packed. Hence it cannot be | |
203 | a bitfield or any other packed type. */ | |
204 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
205 | { | |
206 | nRc = 1; | |
207 | break; | |
208 | } | |
209 | } | |
210 | } | |
211 | } | |
212 | ||
213 | return nRc; | |
c906108c SS |
214 | } |
215 | ||
216 | int | |
ed9a39eb | 217 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 218 | { |
c906108c SS |
219 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
220 | } | |
221 | ||
222 | /* Set to true if the 32-bit mode is in use. */ | |
223 | ||
224 | int arm_apcs_32 = 1; | |
225 | ||
ed9a39eb JM |
226 | /* Flag set by arm_fix_call_dummy that tells whether the target |
227 | function is a Thumb function. This flag is checked by | |
228 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
229 | its use in valops.c) to pass the function address as an additional | |
230 | parameter. */ | |
c906108c SS |
231 | |
232 | static int target_is_thumb; | |
233 | ||
ed9a39eb JM |
234 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
235 | function is a Thumb function. This flag is checked by | |
236 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
237 | |
238 | static int caller_is_thumb; | |
239 | ||
ed9a39eb JM |
240 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
241 | function. */ | |
c906108c SS |
242 | |
243 | int | |
2a451106 | 244 | arm_pc_is_thumb (CORE_ADDR memaddr) |
c906108c | 245 | { |
c5aa993b | 246 | struct minimal_symbol *sym; |
c906108c | 247 | |
ed9a39eb | 248 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
249 | if (IS_THUMB_ADDR (memaddr)) |
250 | return 1; | |
251 | ||
ed9a39eb | 252 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
253 | sym = lookup_minimal_symbol_by_pc (memaddr); |
254 | if (sym) | |
255 | { | |
c5aa993b | 256 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
257 | } |
258 | else | |
ed9a39eb JM |
259 | { |
260 | return 0; | |
261 | } | |
c906108c SS |
262 | } |
263 | ||
ed9a39eb JM |
264 | /* Determine if the program counter specified in MEMADDR is in a call |
265 | dummy being called from a Thumb function. */ | |
c906108c SS |
266 | |
267 | int | |
2a451106 | 268 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
c906108c | 269 | { |
c5aa993b | 270 | CORE_ADDR sp = read_sp (); |
c906108c | 271 | |
dfcd3bfb JM |
272 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
273 | is the best we can do. We are trying to determine if the pc is on | |
274 | the stack, which (hopefully) will only happen in a call dummy. | |
275 | We hope the current stack pointer is not so far alway from the dummy | |
276 | frame location (true if we have not pushed large data structures or | |
277 | gone too many levels deep) and that our 1024 is not enough to consider | |
278 | code regions as part of the stack (true for most practical purposes) */ | |
279 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) | |
c906108c SS |
280 | return caller_is_thumb; |
281 | else | |
282 | return 0; | |
283 | } | |
284 | ||
285 | CORE_ADDR | |
ed9a39eb | 286 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c SS |
287 | { |
288 | if (arm_pc_is_thumb (val)) | |
289 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
290 | else | |
291 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
292 | } | |
293 | ||
294 | CORE_ADDR | |
ed9a39eb | 295 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c SS |
296 | { |
297 | return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); | |
298 | } | |
299 | ||
0defa245 RE |
300 | /* Determine whether the function invocation represented by FI has a |
301 | frame on the stack associated with it. If it does return zero, | |
302 | otherwise return 1. */ | |
303 | ||
392a587b | 304 | int |
ed9a39eb | 305 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 306 | { |
392a587b | 307 | CORE_ADDR func_start, after_prologue; |
96baa820 | 308 | int frameless; |
ed9a39eb | 309 | |
0defa245 RE |
310 | /* Sometimes we have functions that do a little setup (like saving the |
311 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
312 | The symbol table will report this as a prologue. However, it is | |
313 | important not to try to parse these partial frames as frames, or we | |
314 | will get really confused. | |
315 | ||
316 | So I will demand 3 instructions between the start & end of the | |
317 | prologue before I call it a real prologue, i.e. at least | |
318 | mov ip, sp, | |
319 | stmdb sp!, {} | |
320 | sub sp, ip, #4. */ | |
321 | ||
392a587b | 322 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 323 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 324 | |
96baa820 | 325 | /* There are some frameless functions whose first two instructions |
ed9a39eb JM |
326 | follow the standard APCS form, in which case after_prologue will |
327 | be func_start + 8. */ | |
328 | ||
96baa820 | 329 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
330 | return frameless; |
331 | } | |
332 | ||
0defa245 RE |
333 | /* The address of the arguments in the frame. */ |
334 | CORE_ADDR | |
335 | arm_frame_args_address (struct frame_info *fi) | |
336 | { | |
337 | return fi->frame; | |
338 | } | |
339 | ||
340 | /* The address of the local variables in the frame. */ | |
341 | CORE_ADDR | |
342 | arm_frame_locals_address (struct frame_info *fi) | |
343 | { | |
344 | return fi->frame; | |
345 | } | |
346 | ||
347 | /* The number of arguments being passed in the frame. */ | |
348 | int | |
349 | arm_frame_num_args (struct frame_info *fi) | |
350 | { | |
351 | /* We have no way of knowing. */ | |
352 | return -1; | |
353 | } | |
354 | ||
c906108c | 355 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
356 | push {r7, lr} |
357 | add sp, sp, #-28 | |
358 | add r7, sp, #12 | |
c906108c | 359 | Sometimes the latter instruction may be replaced by: |
da59e081 JM |
360 | mov r7, sp |
361 | ||
362 | or like this: | |
363 | push {r7, lr} | |
364 | mov r7, sp | |
365 | sub sp, #12 | |
366 | ||
367 | or, on tpcs, like this: | |
368 | sub sp,#16 | |
369 | push {r7, lr} | |
370 | (many instructions) | |
371 | mov r7, sp | |
372 | sub sp, #12 | |
373 | ||
374 | There is always one instruction of three classes: | |
375 | 1 - push | |
376 | 2 - setting of r7 | |
377 | 3 - adjusting of sp | |
378 | ||
379 | When we have found at least one of each class we are done with the prolog. | |
380 | Note that the "sub sp, #NN" before the push does not count. | |
ed9a39eb | 381 | */ |
c906108c SS |
382 | |
383 | static CORE_ADDR | |
c7885828 | 384 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
c906108c SS |
385 | { |
386 | CORE_ADDR current_pc; | |
da59e081 JM |
387 | int findmask = 0; /* findmask: |
388 | bit 0 - push { rlist } | |
389 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
390 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
391 | */ | |
c906108c | 392 | |
c7885828 | 393 | for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2) |
c906108c SS |
394 | { |
395 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
396 | ||
da59e081 JM |
397 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
398 | { | |
399 | findmask |= 1; /* push found */ | |
400 | } | |
401 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ | |
402 | { | |
403 | if ((findmask & 1) == 0) /* before push ? */ | |
404 | continue; | |
405 | else | |
406 | findmask |= 4; /* add/sub sp found */ | |
407 | } | |
408 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
409 | { | |
410 | findmask |= 2; /* setting of r7 found */ | |
411 | } | |
412 | else if (insn == 0x466f) /* mov r7, sp */ | |
413 | { | |
414 | findmask |= 2; /* setting of r7 found */ | |
415 | } | |
3d74b771 FF |
416 | else if (findmask == (4+2+1)) |
417 | { | |
418 | break; /* We have found one of each type of prologue instruction */ | |
419 | } | |
da59e081 JM |
420 | else |
421 | continue; /* something in the prolog that we don't care about or some | |
422 | instruction from outside the prolog scheduled here for optimization */ | |
c906108c SS |
423 | } |
424 | ||
425 | return current_pc; | |
426 | } | |
427 | ||
ed9a39eb JM |
428 | /* The APCS (ARM Procedure Call Standard) defines the following |
429 | prologue: | |
c906108c | 430 | |
c5aa993b JM |
431 | mov ip, sp |
432 | [stmfd sp!, {a1,a2,a3,a4}] | |
433 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
434 | [stfe f7, [sp, #-12]!] |
435 | [stfe f6, [sp, #-12]!] | |
436 | [stfe f5, [sp, #-12]!] | |
437 | [stfe f4, [sp, #-12]!] | |
438 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c SS |
439 | |
440 | CORE_ADDR | |
ed9a39eb | 441 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
442 | { |
443 | unsigned long inst; | |
444 | CORE_ADDR skip_pc; | |
445 | CORE_ADDR func_addr, func_end; | |
50f6fb4b | 446 | char *func_name; |
c906108c SS |
447 | struct symtab_and_line sal; |
448 | ||
96baa820 | 449 | /* See what the symbol table says. */ |
ed9a39eb | 450 | |
50f6fb4b | 451 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
c906108c | 452 | { |
50f6fb4b CV |
453 | struct symbol *sym; |
454 | ||
455 | /* Found a function. */ | |
456 | sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL); | |
457 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) | |
458 | { | |
459 | /* Don't use this trick for assembly source files. */ | |
460 | sal = find_pc_line (func_addr, 0); | |
461 | if ((sal.line != 0) && (sal.end < func_end)) | |
462 | return sal.end; | |
463 | } | |
c906108c SS |
464 | } |
465 | ||
466 | /* Check if this is Thumb code. */ | |
467 | if (arm_pc_is_thumb (pc)) | |
c7885828 | 468 | return thumb_skip_prologue (pc, func_end); |
c906108c SS |
469 | |
470 | /* Can't find the prologue end in the symbol table, try it the hard way | |
471 | by disassembling the instructions. */ | |
472 | skip_pc = pc; | |
473 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 474 | if (inst != 0xe1a0c00d) /* mov ip, sp */ |
c906108c SS |
475 | return pc; |
476 | ||
477 | skip_pc += 4; | |
478 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 479 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
c906108c SS |
480 | { |
481 | skip_pc += 4; | |
482 | inst = read_memory_integer (skip_pc, 4); | |
483 | } | |
484 | ||
c5aa993b | 485 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ |
c906108c SS |
486 | return pc; |
487 | ||
488 | skip_pc += 4; | |
489 | inst = read_memory_integer (skip_pc, 4); | |
490 | ||
491 | /* Any insns after this point may float into the code, if it makes | |
ed9a39eb JM |
492 | for better instruction scheduling, so we skip them only if we |
493 | find them, but still consdier the function to be frame-ful. */ | |
c906108c | 494 | |
ed9a39eb JM |
495 | /* We may have either one sfmfd instruction here, or several stfe |
496 | insns, depending on the version of floating point code we | |
497 | support. */ | |
c5aa993b | 498 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
c906108c SS |
499 | { |
500 | skip_pc += 4; | |
501 | inst = read_memory_integer (skip_pc, 4); | |
502 | } | |
503 | else | |
504 | { | |
c5aa993b JM |
505 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
506 | { | |
507 | skip_pc += 4; | |
508 | inst = read_memory_integer (skip_pc, 4); | |
509 | } | |
c906108c SS |
510 | } |
511 | ||
c5aa993b | 512 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
c906108c SS |
513 | skip_pc += 4; |
514 | ||
515 | return skip_pc; | |
516 | } | |
c5aa993b | 517 | /* *INDENT-OFF* */ |
c906108c SS |
518 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
519 | This function decodes a Thumb function prologue to determine: | |
520 | 1) the size of the stack frame | |
521 | 2) which registers are saved on it | |
522 | 3) the offsets of saved regs | |
523 | 4) the offset from the stack pointer to the frame pointer | |
524 | This information is stored in the "extra" fields of the frame_info. | |
525 | ||
da59e081 JM |
526 | A typical Thumb function prologue would create this stack frame |
527 | (offsets relative to FP) | |
c906108c SS |
528 | old SP -> 24 stack parameters |
529 | 20 LR | |
530 | 16 R7 | |
531 | R7 -> 0 local variables (16 bytes) | |
532 | SP -> -12 additional stack space (12 bytes) | |
533 | The frame size would thus be 36 bytes, and the frame offset would be | |
da59e081 JM |
534 | 12 bytes. The frame register is R7. |
535 | ||
536 | The comments for thumb_skip_prolog() describe the algorithm we use to detect | |
537 | the end of the prolog */ | |
c5aa993b JM |
538 | /* *INDENT-ON* */ |
539 | ||
c906108c | 540 | static void |
ed9a39eb | 541 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
542 | { |
543 | CORE_ADDR prologue_start; | |
544 | CORE_ADDR prologue_end; | |
545 | CORE_ADDR current_pc; | |
c5aa993b | 546 | int saved_reg[16]; /* which register has been copied to register n? */ |
da59e081 JM |
547 | int findmask = 0; /* findmask: |
548 | bit 0 - push { rlist } | |
549 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) | |
550 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) | |
551 | */ | |
c5aa993b | 552 | int i; |
c906108c | 553 | |
c5aa993b | 554 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
555 | { |
556 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
557 | ||
c5aa993b | 558 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
559 | prologue_end = fi->pc; |
560 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
c5aa993b | 561 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
562 | } |
563 | else | |
c5aa993b JM |
564 | prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */ |
565 | /* 16 pushes, an add, and "mv fp,sp" */ | |
c906108c SS |
566 | |
567 | prologue_end = min (prologue_end, fi->pc); | |
568 | ||
569 | /* Initialize the saved register map. When register H is copied to | |
570 | register L, we will put H in saved_reg[L]. */ | |
571 | for (i = 0; i < 16; i++) | |
572 | saved_reg[i] = i; | |
573 | ||
574 | /* Search the prologue looking for instructions that set up the | |
da59e081 JM |
575 | frame pointer, adjust the stack pointer, and save registers. |
576 | Do this until all basic prolog instructions are found. */ | |
c906108c | 577 | |
c3b4394c | 578 | fi->extra_info->framesize = 0; |
da59e081 JM |
579 | for (current_pc = prologue_start; |
580 | (current_pc < prologue_end) && ((findmask & 7) != 7); | |
581 | current_pc += 2) | |
c906108c SS |
582 | { |
583 | unsigned short insn; | |
584 | int regno; | |
585 | int offset; | |
586 | ||
587 | insn = read_memory_unsigned_integer (current_pc, 2); | |
588 | ||
c5aa993b | 589 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c | 590 | { |
da59e081 JM |
591 | int mask; |
592 | findmask |= 1; /* push found */ | |
c906108c SS |
593 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
594 | whether to save LR (R14). */ | |
da59e081 | 595 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
c906108c SS |
596 | |
597 | /* Calculate offsets of saved R0-R7 and LR. */ | |
598 | for (regno = LR_REGNUM; regno >= 0; regno--) | |
599 | if (mask & (1 << regno)) | |
c5aa993b | 600 | { |
c3b4394c RE |
601 | fi->extra_info->framesize += 4; |
602 | fi->saved_regs[saved_reg[regno]] = | |
603 | -(fi->extra_info->framesize); | |
c906108c SS |
604 | saved_reg[regno] = regno; /* reset saved register map */ |
605 | } | |
606 | } | |
da59e081 | 607 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ |
c906108c | 608 | { |
da59e081 JM |
609 | if ((findmask & 1) == 0) /* before push ? */ |
610 | continue; | |
611 | else | |
612 | findmask |= 4; /* add/sub sp found */ | |
613 | ||
c5aa993b | 614 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
da59e081 JM |
615 | if (insn & 0x80) /* is it signed? (==subtracting) */ |
616 | { | |
c3b4394c | 617 | fi->extra_info->frameoffset += offset; |
da59e081 JM |
618 | offset = -offset; |
619 | } | |
c3b4394c | 620 | fi->extra_info->framesize -= offset; |
c906108c SS |
621 | } |
622 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
623 | { | |
da59e081 | 624 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
625 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
626 | /* get scaled offset */ | |
627 | fi->extra_info->frameoffset = (insn & 0xff) << 2; | |
c906108c | 628 | } |
da59e081 | 629 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c | 630 | { |
da59e081 | 631 | findmask |= 2; /* setting of r7 found */ |
c3b4394c RE |
632 | fi->extra_info->framereg = THUMB_FP_REGNUM; |
633 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
634 | saved_reg[THUMB_FP_REGNUM] = SP_REGNUM; |
635 | } | |
636 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
637 | { | |
c5aa993b | 638 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 639 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
c5aa993b | 640 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
641 | } |
642 | else | |
da59e081 JM |
643 | continue; /* something in the prolog that we don't care about or some |
644 | instruction from outside the prolog scheduled here for optimization */ | |
c906108c SS |
645 | } |
646 | } | |
647 | ||
ed9a39eb JM |
648 | /* Check if prologue for this frame's PC has already been scanned. If |
649 | it has, copy the relevant information about that prologue and | |
c906108c SS |
650 | return non-zero. Otherwise do not copy anything and return zero. |
651 | ||
652 | The information saved in the cache includes: | |
c5aa993b JM |
653 | * the frame register number; |
654 | * the size of the stack frame; | |
655 | * the offsets of saved regs (relative to the old SP); and | |
656 | * the offset from the stack pointer to the frame pointer | |
c906108c | 657 | |
ed9a39eb JM |
658 | The cache contains only one entry, since this is adequate for the |
659 | typical sequence of prologue scan requests we get. When performing | |
660 | a backtrace, GDB will usually ask to scan the same function twice | |
661 | in a row (once to get the frame chain, and once to fill in the | |
662 | extra frame information). */ | |
c906108c SS |
663 | |
664 | static struct frame_info prologue_cache; | |
665 | ||
666 | static int | |
ed9a39eb | 667 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
668 | { |
669 | int i; | |
670 | ||
671 | if (fi->pc == prologue_cache.pc) | |
672 | { | |
c3b4394c RE |
673 | fi->extra_info->framereg = prologue_cache.extra_info->framereg; |
674 | fi->extra_info->framesize = prologue_cache.extra_info->framesize; | |
675 | fi->extra_info->frameoffset = prologue_cache.extra_info->frameoffset; | |
676 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) | |
677 | fi->saved_regs[i] = prologue_cache.saved_regs[i]; | |
c906108c SS |
678 | return 1; |
679 | } | |
680 | else | |
681 | return 0; | |
682 | } | |
683 | ||
684 | ||
ed9a39eb | 685 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
686 | |
687 | static void | |
ed9a39eb | 688 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
689 | { |
690 | int i; | |
691 | ||
c5aa993b | 692 | prologue_cache.pc = fi->pc; |
c3b4394c RE |
693 | prologue_cache.extra_info->framereg = fi->extra_info->framereg; |
694 | prologue_cache.extra_info->framesize = fi->extra_info->framesize; | |
695 | prologue_cache.extra_info->frameoffset = fi->extra_info->frameoffset; | |
c5aa993b | 696 | |
c3b4394c RE |
697 | for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) |
698 | prologue_cache.saved_regs[i] = fi->saved_regs[i]; | |
c906108c SS |
699 | } |
700 | ||
701 | ||
ed9a39eb | 702 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
703 | 1) the size of the stack frame |
704 | 2) which registers are saved on it | |
705 | 3) the offsets of saved regs | |
706 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
707 | This information is stored in the "extra" fields of the frame_info. |
708 | ||
96baa820 JM |
709 | There are two basic forms for the ARM prologue. The fixed argument |
710 | function call will look like: | |
ed9a39eb JM |
711 | |
712 | mov ip, sp | |
713 | stmfd sp!, {fp, ip, lr, pc} | |
714 | sub fp, ip, #4 | |
715 | [sub sp, sp, #4] | |
96baa820 | 716 | |
c906108c | 717 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
718 | IP -> 4 (caller's stack) |
719 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
720 | -4 LR (return address in caller) | |
721 | -8 IP (copy of caller's SP) | |
722 | -12 FP (caller's FP) | |
723 | SP -> -28 Local variables | |
724 | ||
c906108c | 725 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
726 | 28 bytes. The stmfd call can also save any of the vN registers it |
727 | plans to use, which increases the frame size accordingly. | |
728 | ||
729 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
730 | because the ARM Store instructions always store PC + 8 when you read | |
731 | the PC register. | |
ed9a39eb | 732 | |
96baa820 JM |
733 | A variable argument function call will look like: |
734 | ||
ed9a39eb JM |
735 | mov ip, sp |
736 | stmfd sp!, {a1, a2, a3, a4} | |
737 | stmfd sp!, {fp, ip, lr, pc} | |
738 | sub fp, ip, #20 | |
739 | ||
96baa820 | 740 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
741 | IP -> 20 (caller's stack) |
742 | 16 A4 | |
743 | 12 A3 | |
744 | 8 A2 | |
745 | 4 A1 | |
746 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
747 | -4 LR (return address in caller) | |
748 | -8 IP (copy of caller's SP) | |
749 | -12 FP (caller's FP) | |
750 | SP -> -28 Local variables | |
96baa820 JM |
751 | |
752 | The frame size would thus be 48 bytes, and the frame offset would be | |
753 | 28 bytes. | |
754 | ||
755 | There is another potential complication, which is that the optimizer | |
756 | will try to separate the store of fp in the "stmfd" instruction from | |
757 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
758 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
759 | ||
760 | Also, note, the original version of the ARM toolchain claimed that there | |
761 | should be an | |
762 | ||
763 | instruction at the end of the prologue. I have never seen GCC produce | |
764 | this, and the ARM docs don't mention it. We still test for it below in | |
765 | case it happens... | |
ed9a39eb JM |
766 | |
767 | */ | |
c906108c SS |
768 | |
769 | static void | |
ed9a39eb | 770 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
771 | { |
772 | int regno, sp_offset, fp_offset; | |
16a0f3e7 | 773 | LONGEST return_value; |
c906108c SS |
774 | CORE_ADDR prologue_start, prologue_end, current_pc; |
775 | ||
776 | /* Check if this function is already in the cache of frame information. */ | |
777 | if (check_prologue_cache (fi)) | |
778 | return; | |
779 | ||
780 | /* Assume there is no frame until proven otherwise. */ | |
c3b4394c RE |
781 | fi->extra_info->framereg = SP_REGNUM; |
782 | fi->extra_info->framesize = 0; | |
783 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
784 | |
785 | /* Check for Thumb prologue. */ | |
786 | if (arm_pc_is_thumb (fi->pc)) | |
787 | { | |
788 | thumb_scan_prologue (fi); | |
789 | save_prologue_cache (fi); | |
790 | return; | |
791 | } | |
792 | ||
793 | /* Find the function prologue. If we can't find the function in | |
794 | the symbol table, peek in the stack frame to find the PC. */ | |
795 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
796 | { | |
2a451106 KB |
797 | /* One way to find the end of the prologue (which works well |
798 | for unoptimized code) is to do the following: | |
799 | ||
800 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
801 | ||
802 | if (sal.line == 0) | |
803 | prologue_end = fi->pc; | |
804 | else if (sal.end < prologue_end) | |
805 | prologue_end = sal.end; | |
806 | ||
807 | This mechanism is very accurate so long as the optimizer | |
808 | doesn't move any instructions from the function body into the | |
809 | prologue. If this happens, sal.end will be the last | |
810 | instruction in the first hunk of prologue code just before | |
811 | the first instruction that the scheduler has moved from | |
812 | the body to the prologue. | |
813 | ||
814 | In order to make sure that we scan all of the prologue | |
815 | instructions, we use a slightly less accurate mechanism which | |
816 | may scan more than necessary. To help compensate for this | |
817 | lack of accuracy, the prologue scanning loop below contains | |
818 | several clauses which'll cause the loop to terminate early if | |
819 | an implausible prologue instruction is encountered. | |
820 | ||
821 | The expression | |
822 | ||
823 | prologue_start + 64 | |
824 | ||
825 | is a suitable endpoint since it accounts for the largest | |
826 | possible prologue plus up to five instructions inserted by | |
827 | the scheduler. */ | |
828 | ||
829 | if (prologue_end > prologue_start + 64) | |
830 | { | |
831 | prologue_end = prologue_start + 64; /* See above. */ | |
832 | } | |
c906108c SS |
833 | } |
834 | else | |
835 | { | |
836 | /* Get address of the stmfd in the prologue of the callee; the saved | |
96baa820 | 837 | PC is the address of the stmfd + 8. */ |
16a0f3e7 EZ |
838 | if (!safe_read_memory_integer (fi->frame, 4, &return_value)) |
839 | return; | |
840 | else | |
841 | { | |
842 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; | |
843 | prologue_end = prologue_start + 64; /* See above. */ | |
844 | } | |
c906108c SS |
845 | } |
846 | ||
847 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 848 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 849 | |
96baa820 JM |
850 | Be careful, however, and if it doesn't look like a prologue, |
851 | don't try to scan it. If, for instance, a frameless function | |
852 | begins with stmfd sp!, then we will tell ourselves there is | |
853 | a frame, which will confuse stack traceback, as well ad"finish" | |
854 | and other operations that rely on a knowledge of the stack | |
855 | traceback. | |
856 | ||
857 | In the APCS, the prologue should start with "mov ip, sp" so | |
d4473757 KB |
858 | if we don't see this as the first insn, we will stop. [Note: |
859 | This doesn't seem to be true any longer, so it's now an optional | |
860 | part of the prologue. - Kevin Buettner, 2001-11-20] */ | |
c906108c SS |
861 | |
862 | sp_offset = fp_offset = 0; | |
c906108c | 863 | |
ed9a39eb JM |
864 | if (read_memory_unsigned_integer (prologue_start, 4) |
865 | == 0xe1a0c00d) /* mov ip, sp */ | |
d4473757 KB |
866 | current_pc = prologue_start + 4; |
867 | else | |
868 | current_pc = prologue_start; | |
869 | ||
870 | for (; current_pc < prologue_end; current_pc += 4) | |
96baa820 | 871 | { |
d4473757 KB |
872 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
873 | ||
874 | if ((insn & 0xffff0000) == 0xe92d0000) | |
875 | /* stmfd sp!, {..., fp, ip, lr, pc} | |
876 | or | |
877 | stmfd sp!, {a1, a2, a3, a4} */ | |
c906108c | 878 | { |
d4473757 | 879 | int mask = insn & 0xffff; |
ed9a39eb | 880 | |
d4473757 KB |
881 | /* Calculate offsets of saved registers. */ |
882 | for (regno = PC_REGNUM; regno >= 0; regno--) | |
883 | if (mask & (1 << regno)) | |
884 | { | |
885 | sp_offset -= 4; | |
c3b4394c | 886 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
887 | } |
888 | } | |
889 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ | |
890 | { | |
891 | unsigned imm = insn & 0xff; /* immediate value */ | |
892 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
893 | imm = (imm >> rot) | (imm << (32 - rot)); | |
894 | fp_offset = -imm; | |
c3b4394c | 895 | fi->extra_info->framereg = FP_REGNUM; |
d4473757 KB |
896 | } |
897 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ | |
898 | { | |
899 | unsigned imm = insn & 0xff; /* immediate value */ | |
900 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
901 | imm = (imm >> rot) | (imm << (32 - rot)); | |
902 | sp_offset -= imm; | |
903 | } | |
904 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ | |
905 | { | |
906 | sp_offset -= 12; | |
907 | regno = F0_REGNUM + ((insn >> 12) & 0x07); | |
c3b4394c | 908 | fi->saved_regs[regno] = sp_offset; |
d4473757 KB |
909 | } |
910 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ | |
911 | { | |
912 | int n_saved_fp_regs; | |
913 | unsigned int fp_start_reg, fp_bound_reg; | |
914 | ||
915 | if ((insn & 0x800) == 0x800) /* N0 is set */ | |
96baa820 | 916 | { |
d4473757 KB |
917 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
918 | n_saved_fp_regs = 3; | |
919 | else | |
920 | n_saved_fp_regs = 1; | |
96baa820 | 921 | } |
d4473757 | 922 | else |
96baa820 | 923 | { |
d4473757 KB |
924 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
925 | n_saved_fp_regs = 2; | |
926 | else | |
927 | n_saved_fp_regs = 4; | |
96baa820 | 928 | } |
d4473757 KB |
929 | |
930 | fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7); | |
931 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; | |
932 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
96baa820 JM |
933 | { |
934 | sp_offset -= 12; | |
c3b4394c | 935 | fi->saved_regs[fp_start_reg++] = sp_offset; |
96baa820 | 936 | } |
c906108c | 937 | } |
d4473757 KB |
938 | else if ((insn & 0xf0000000) != 0xe0000000) |
939 | break; /* Condition not true, exit early */ | |
940 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ | |
941 | break; /* Don't scan past a block load */ | |
942 | else | |
943 | /* The optimizer might shove anything into the prologue, | |
944 | so we just skip what we don't recognize. */ | |
945 | continue; | |
c906108c SS |
946 | } |
947 | ||
948 | /* The frame size is just the negative of the offset (from the original SP) | |
949 | of the last thing thing we pushed on the stack. The frame offset is | |
950 | [new FP] - [new SP]. */ | |
c3b4394c RE |
951 | fi->extra_info->framesize = -sp_offset; |
952 | if (fi->extra_info->framereg == FP_REGNUM) | |
953 | fi->extra_info->frameoffset = fp_offset - sp_offset; | |
d4473757 | 954 | else |
c3b4394c | 955 | fi->extra_info->frameoffset = 0; |
ed9a39eb | 956 | |
c906108c SS |
957 | save_prologue_cache (fi); |
958 | } | |
959 | ||
ed9a39eb JM |
960 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
961 | One thing we might want to do here is to check REGNUM against the | |
962 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
963 | the stack somewhere. This would provide a graceful failure mode | |
964 | when trying to get the value of caller-saves registers for an inner | |
965 | frame. */ | |
c906108c SS |
966 | |
967 | static CORE_ADDR | |
ed9a39eb | 968 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c SS |
969 | { |
970 | for (; fi; fi = fi->next) | |
c5aa993b JM |
971 | |
972 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
c906108c SS |
973 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
974 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
975 | else | |
976 | #endif | |
c3b4394c RE |
977 | if (fi->saved_regs[regnum] != 0) |
978 | return read_memory_integer (fi->saved_regs[regnum], | |
c5aa993b | 979 | REGISTER_RAW_SIZE (regnum)); |
c906108c SS |
980 | return read_register (regnum); |
981 | } | |
c5aa993b | 982 | /* *INDENT-OFF* */ |
c906108c SS |
983 | /* Function: frame_chain |
984 | Given a GDB frame, determine the address of the calling function's frame. | |
985 | This will be used to create a new GDB frame struct, and then | |
986 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
987 | For ARM, we save the frame size when we initialize the frame_info. | |
988 | ||
989 | The original definition of this function was a macro in tm-arm.h: | |
990 | { In the case of the ARM, the frame's nominal address is the FP value, | |
991 | and 12 bytes before comes the saved previous FP value as a 4-byte word. } | |
992 | ||
993 | #define FRAME_CHAIN(thisframe) \ | |
994 | ((thisframe)->pc >= LOWEST_PC ? \ | |
995 | read_memory_integer ((thisframe)->frame - 12, 4) :\ | |
996 | 0) | |
997 | */ | |
c5aa993b JM |
998 | /* *INDENT-ON* */ |
999 | ||
c906108c | 1000 | CORE_ADDR |
ed9a39eb | 1001 | arm_frame_chain (struct frame_info *fi) |
c906108c | 1002 | { |
c5aa993b | 1003 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
1004 | CORE_ADDR fn_start, callers_pc, fp; |
1005 | ||
1006 | /* is this a dummy frame? */ | |
1007 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
c5aa993b | 1008 | return fi->frame; /* dummy frame same as caller's frame */ |
c906108c SS |
1009 | |
1010 | /* is caller-of-this a dummy frame? */ | |
c5aa993b | 1011 | callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */ |
c906108c | 1012 | fp = arm_find_callers_reg (fi, FP_REGNUM); |
c5aa993b JM |
1013 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) |
1014 | return fp; /* dummy frame's frame may bear no relation to ours */ | |
c906108c SS |
1015 | |
1016 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) | |
1017 | if (fn_start == entry_point_address ()) | |
c5aa993b | 1018 | return 0; /* in _start fn, don't chain further */ |
c906108c SS |
1019 | #endif |
1020 | CORE_ADDR caller_pc, fn_start; | |
c3b4394c | 1021 | int framereg = fi->extra_info->framereg; |
c906108c SS |
1022 | |
1023 | if (fi->pc < LOWEST_PC) | |
1024 | return 0; | |
1025 | ||
1026 | /* If the caller is the startup code, we're at the end of the chain. */ | |
1027 | caller_pc = FRAME_SAVED_PC (fi); | |
1028 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) | |
1029 | if (fn_start == entry_point_address ()) | |
1030 | return 0; | |
1031 | ||
1032 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
1033 | the frame register of the caller is different from ours. | |
1034 | So we must scan the prologue of the caller to determine its | |
1035 | frame register number. */ | |
c3b4394c RE |
1036 | /* XXX Fixme, we should try to do this without creating a temporary |
1037 | caller_fi. */ | |
c906108c SS |
1038 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) |
1039 | { | |
c3b4394c RE |
1040 | struct frame_info caller_fi; |
1041 | struct cleanup *old_chain; | |
1042 | ||
1043 | /* Create a temporary frame suitable for scanning the caller's | |
1044 | prologue. (Ugh.) */ | |
c5aa993b | 1045 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c3b4394c RE |
1046 | caller_fi.extra_info = (struct frame_extra_info *) |
1047 | xcalloc (1, sizeof (struct frame_extra_info)); | |
1048 | old_chain = make_cleanup (xfree, caller_fi.extra_info); | |
1049 | caller_fi.saved_regs = (CORE_ADDR *) | |
1050 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
1051 | make_cleanup (xfree, caller_fi.saved_regs); | |
1052 | ||
1053 | /* Now, scan the prologue and obtain the frame register. */ | |
c906108c | 1054 | caller_fi.pc = caller_pc; |
c5aa993b | 1055 | arm_scan_prologue (&caller_fi); |
c3b4394c RE |
1056 | framereg = caller_fi.extra_info->framereg; |
1057 | ||
1058 | /* Deallocate the storage associated with the temporary frame | |
1059 | created above. */ | |
1060 | do_cleanups (old_chain); | |
c906108c SS |
1061 | } |
1062 | ||
1063 | /* If the caller used a frame register, return its value. | |
1064 | Otherwise, return the caller's stack pointer. */ | |
1065 | if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM) | |
1066 | return arm_find_callers_reg (fi, framereg); | |
1067 | else | |
c3b4394c | 1068 | return fi->frame + fi->extra_info->framesize; |
c906108c SS |
1069 | } |
1070 | ||
ed9a39eb JM |
1071 | /* This function actually figures out the frame address for a given pc |
1072 | and sp. This is tricky because we sometimes don't use an explicit | |
1073 | frame pointer, and the previous stack pointer isn't necessarily | |
1074 | recorded on the stack. The only reliable way to get this info is | |
1075 | to examine the prologue. FROMLEAF is a little confusing, it means | |
1076 | this is the next frame up the chain AFTER a frameless function. If | |
1077 | this is true, then the frame value for this frame is still in the | |
1078 | fp register. */ | |
c906108c SS |
1079 | |
1080 | void | |
ed9a39eb | 1081 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
1082 | { |
1083 | int reg; | |
f079148d | 1084 | CORE_ADDR sp; |
c906108c | 1085 | |
c3b4394c RE |
1086 | if (fi->saved_regs == NULL) |
1087 | frame_saved_regs_zalloc (fi); | |
1088 | ||
1089 | fi->extra_info = (struct frame_extra_info *) | |
1090 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1091 | ||
1092 | fi->extra_info->framesize = 0; | |
1093 | fi->extra_info->frameoffset = 0; | |
1094 | fi->extra_info->framereg = 0; | |
1095 | ||
c906108c SS |
1096 | if (fi->next) |
1097 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1098 | ||
c3b4394c | 1099 | memset (fi->saved_regs, '\000', sizeof fi->saved_regs); |
c906108c | 1100 | |
c5aa993b | 1101 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
1102 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
1103 | { | |
1104 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
c5aa993b JM |
1105 | by assuming it's always FP. */ |
1106 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
c3b4394c RE |
1107 | fi->extra_info->framesize = 0; |
1108 | fi->extra_info->frameoffset = 0; | |
c906108c SS |
1109 | return; |
1110 | } | |
c5aa993b | 1111 | else |
c906108c | 1112 | #endif |
2a451106 | 1113 | |
f079148d KB |
1114 | /* Compute stack pointer for this frame. We use this value for both the |
1115 | sigtramp and call dummy cases. */ | |
1116 | if (!fi->next) | |
1117 | sp = read_sp(); | |
1118 | else | |
c3b4394c RE |
1119 | sp = (fi->next->frame - fi->next->extra_info->frameoffset |
1120 | + fi->next->extra_info->framesize); | |
f079148d | 1121 | |
2a451106 KB |
1122 | /* Determine whether or not we're in a sigtramp frame. |
1123 | Unfortunately, it isn't sufficient to test | |
1124 | fi->signal_handler_caller because this value is sometimes set | |
1125 | after invoking INIT_EXTRA_FRAME_INFO. So we test *both* | |
1126 | fi->signal_handler_caller and IN_SIGTRAMP to determine if we need | |
1127 | to use the sigcontext addresses for the saved registers. | |
1128 | ||
1129 | Note: If an ARM IN_SIGTRAMP method ever needs to compare against | |
1130 | the name of the function, the code below will have to be changed | |
1131 | to first fetch the name of the function and then pass this name | |
f079148d | 1132 | to IN_SIGTRAMP. */ |
2a451106 | 1133 | |
3bb04bdd | 1134 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
dd96c05b | 1135 | && (fi->signal_handler_caller || IN_SIGTRAMP (fi->pc, (char *)0))) |
2a451106 | 1136 | { |
2a451106 | 1137 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c | 1138 | fi->saved_regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); |
2a451106 KB |
1139 | |
1140 | /* FIXME: What about thumb mode? */ | |
c3b4394c RE |
1141 | fi->extra_info->framereg = SP_REGNUM; |
1142 | fi->frame = | |
1143 | read_memory_integer (fi->saved_regs[fi->extra_info->framereg], | |
1144 | REGISTER_RAW_SIZE (fi->extra_info->framereg)); | |
1145 | fi->extra_info->framesize = 0; | |
1146 | fi->extra_info->frameoffset = 0; | |
2a451106 KB |
1147 | |
1148 | } | |
f079148d KB |
1149 | else if (PC_IN_CALL_DUMMY (fi->pc, sp, fi->frame)) |
1150 | { | |
1151 | CORE_ADDR rp; | |
1152 | CORE_ADDR callers_sp; | |
1153 | ||
1154 | /* Set rp point at the high end of the saved registers. */ | |
1155 | rp = fi->frame - REGISTER_SIZE; | |
1156 | ||
1157 | /* Fill in addresses of saved registers. */ | |
c3b4394c | 1158 | fi->saved_regs[PS_REGNUM] = rp; |
f079148d KB |
1159 | rp -= REGISTER_RAW_SIZE (PS_REGNUM); |
1160 | for (reg = PC_REGNUM; reg >= 0; reg--) | |
1161 | { | |
c3b4394c | 1162 | fi->saved_regs[reg] = rp; |
f079148d KB |
1163 | rp -= REGISTER_RAW_SIZE (reg); |
1164 | } | |
1165 | ||
c3b4394c | 1166 | callers_sp = read_memory_integer (fi->saved_regs[SP_REGNUM], |
f079148d | 1167 | REGISTER_RAW_SIZE (SP_REGNUM)); |
c3b4394c RE |
1168 | fi->extra_info->framereg = FP_REGNUM; |
1169 | fi->extra_info->framesize = callers_sp - sp; | |
1170 | fi->extra_info->frameoffset = fi->frame - sp; | |
f079148d | 1171 | } |
2a451106 | 1172 | else |
c906108c SS |
1173 | { |
1174 | arm_scan_prologue (fi); | |
1175 | ||
104c1213 JM |
1176 | if (!fi->next) |
1177 | /* this is the innermost frame? */ | |
c3b4394c RE |
1178 | fi->frame = read_register (fi->extra_info->framereg); |
1179 | else if (fi->extra_info->framereg == FP_REGNUM | |
1180 | || fi->extra_info->framereg == THUMB_FP_REGNUM) | |
ed9a39eb JM |
1181 | { |
1182 | /* not the innermost frame */ | |
1183 | /* If we have an FP, the callee saved it. */ | |
c3b4394c | 1184 | if (fi->next->saved_regs[fi->extra_info->framereg] != 0) |
ed9a39eb | 1185 | fi->frame = |
c3b4394c RE |
1186 | read_memory_integer (fi->next |
1187 | ->saved_regs[fi->extra_info->framereg], 4); | |
ed9a39eb JM |
1188 | else if (fromleaf) |
1189 | /* If we were called by a frameless fn. then our frame is | |
1190 | still in the frame pointer register on the board... */ | |
1191 | fi->frame = read_fp (); | |
1192 | } | |
c906108c | 1193 | |
ed9a39eb JM |
1194 | /* Calculate actual addresses of saved registers using offsets |
1195 | determined by arm_scan_prologue. */ | |
c906108c | 1196 | for (reg = 0; reg < NUM_REGS; reg++) |
c3b4394c RE |
1197 | if (fi->saved_regs[reg] != 0) |
1198 | fi->saved_regs[reg] += (fi->frame + fi->extra_info->framesize | |
1199 | - fi->extra_info->frameoffset); | |
c906108c SS |
1200 | } |
1201 | } | |
1202 | ||
1203 | ||
ed9a39eb JM |
1204 | /* Find the caller of this frame. We do this by seeing if LR_REGNUM |
1205 | is saved in the stack anywhere, otherwise we get it from the | |
1206 | registers. | |
c906108c SS |
1207 | |
1208 | The old definition of this function was a macro: | |
c5aa993b | 1209 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 1210 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c SS |
1211 | |
1212 | CORE_ADDR | |
ed9a39eb | 1213 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 1214 | { |
c5aa993b | 1215 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
1216 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
1217 | return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
1218 | else | |
1219 | #endif | |
c3b4394c RE |
1220 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame - fi->extra_info->frameoffset, |
1221 | fi->frame)) | |
f079148d | 1222 | { |
c3b4394c RE |
1223 | return read_memory_integer (fi->saved_regs[PC_REGNUM], |
1224 | REGISTER_RAW_SIZE (PC_REGNUM)); | |
f079148d KB |
1225 | } |
1226 | else | |
c906108c SS |
1227 | { |
1228 | CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM); | |
1229 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
1230 | } | |
1231 | } | |
1232 | ||
c906108c SS |
1233 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
1234 | Examine the Program Status Register to decide which state we're in. */ | |
1235 | ||
1236 | CORE_ADDR | |
ed9a39eb | 1237 | arm_target_read_fp (void) |
c906108c SS |
1238 | { |
1239 | if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ | |
1240 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ | |
1241 | else | |
c5aa993b | 1242 | return read_register (FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
1243 | } |
1244 | ||
ed9a39eb | 1245 | /* Calculate the frame offsets of the saved registers (ARM version). */ |
c906108c | 1246 | |
c906108c | 1247 | void |
c3b4394c | 1248 | arm_frame_init_saved_regs (struct frame_info *fip) |
c906108c | 1249 | { |
c3b4394c RE |
1250 | |
1251 | if (fip->saved_regs) | |
1252 | return; | |
1253 | ||
1254 | arm_init_extra_frame_info (0, fip); | |
c906108c SS |
1255 | } |
1256 | ||
c906108c | 1257 | void |
ed9a39eb | 1258 | arm_push_dummy_frame (void) |
c906108c SS |
1259 | { |
1260 | CORE_ADDR old_sp = read_register (SP_REGNUM); | |
1261 | CORE_ADDR sp = old_sp; | |
1262 | CORE_ADDR fp, prologue_start; | |
1263 | int regnum; | |
1264 | ||
1265 | /* Push the two dummy prologue instructions in reverse order, | |
1266 | so that they'll be in the correct low-to-high order in memory. */ | |
1267 | /* sub fp, ip, #4 */ | |
1268 | sp = push_word (sp, 0xe24cb004); | |
1269 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
1270 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
1271 | ||
ed9a39eb JM |
1272 | /* Push a pointer to the dummy prologue + 12, because when stm |
1273 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
1274 | instruction itself plus 12. */ |
1275 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 1276 | |
f079148d KB |
1277 | /* Push the processor status. */ |
1278 | sp = push_word (sp, read_register (PS_REGNUM)); | |
1279 | ||
1280 | /* Push all 16 registers starting with r15. */ | |
1281 | for (regnum = PC_REGNUM; regnum >= 0; regnum--) | |
c906108c | 1282 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1283 | |
f079148d | 1284 | /* Update fp (for both Thumb and ARM) and sp. */ |
c906108c SS |
1285 | write_register (FP_REGNUM, fp); |
1286 | write_register (THUMB_FP_REGNUM, fp); | |
1287 | write_register (SP_REGNUM, sp); | |
1288 | } | |
1289 | ||
6eb69eab RE |
1290 | /* CALL_DUMMY_WORDS: |
1291 | This sequence of words is the instructions | |
1292 | ||
1293 | mov lr,pc | |
1294 | mov pc,r4 | |
1295 | illegal | |
1296 | ||
1297 | Note this is 12 bytes. */ | |
1298 | ||
1299 | LONGEST arm_call_dummy_words[] = | |
1300 | { | |
1301 | 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe | |
1302 | }; | |
1303 | ||
c906108c | 1304 | /* Fix up the call dummy, based on whether the processor is currently |
ed9a39eb JM |
1305 | in Thumb or ARM mode, and whether the target function is Thumb or |
1306 | ARM. There are three different situations requiring three | |
c906108c SS |
1307 | different dummies: |
1308 | ||
1309 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1310 | been copied into the dummy parameter to this function. |
c906108c | 1311 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1312 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1313 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1314 | works for calling both ARM and Thumb functions. |
c906108c | 1315 | |
ed9a39eb JM |
1316 | All three call dummies expect to receive the target function |
1317 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c SS |
1318 | |
1319 | void | |
ed9a39eb | 1320 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 1321 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
1322 | { |
1323 | static short thumb_dummy[4] = | |
1324 | { | |
c5aa993b JM |
1325 | 0xf000, 0xf801, /* bl label */ |
1326 | 0xdf18, /* swi 24 */ | |
1327 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1328 | }; |
1329 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1330 | ||
1331 | /* Set flag indicating whether the current PC is in a Thumb function. */ | |
c5aa993b | 1332 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
c906108c | 1333 | |
ed9a39eb JM |
1334 | /* If the target function is Thumb, set the low bit of the function |
1335 | address. And if the CPU is currently in ARM mode, patch the | |
1336 | second instruction of call dummy to use a BX instruction to | |
1337 | switch to Thumb mode. */ | |
c906108c SS |
1338 | target_is_thumb = arm_pc_is_thumb (fun); |
1339 | if (target_is_thumb) | |
1340 | { | |
1341 | fun |= 1; | |
1342 | if (!caller_is_thumb) | |
1343 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1344 | } | |
1345 | ||
1346 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1347 | instead of the ARM one that's already been copied. This will | |
1348 | work for both Thumb and ARM target functions. */ | |
1349 | if (caller_is_thumb) | |
1350 | { | |
1351 | int i; | |
1352 | char *p = dummy; | |
1353 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1354 | ||
1355 | for (i = 0; i < len; i++) | |
1356 | { | |
1357 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1358 | p += sizeof (thumb_dummy[0]); | |
1359 | } | |
1360 | } | |
1361 | ||
ed9a39eb JM |
1362 | /* Put the target address in r4; the call dummy will copy this to |
1363 | the PC. */ | |
c906108c SS |
1364 | write_register (4, fun); |
1365 | } | |
1366 | ||
c906108c | 1367 | /* Return the offset in the call dummy of the instruction that needs |
ed9a39eb JM |
1368 | to have a breakpoint placed on it. This is the offset of the 'swi |
1369 | 24' instruction, which is no longer actually used, but simply acts | |
c906108c SS |
1370 | as a place-holder now. |
1371 | ||
ed9a39eb | 1372 | This implements the CALL_DUMMY_BREAK_OFFSET macro. */ |
c906108c SS |
1373 | |
1374 | int | |
ed9a39eb | 1375 | arm_call_dummy_breakpoint_offset (void) |
c906108c SS |
1376 | { |
1377 | if (caller_is_thumb) | |
1378 | return 4; | |
1379 | else | |
1380 | return 8; | |
1381 | } | |
1382 | ||
ed9a39eb JM |
1383 | /* Note: ScottB |
1384 | ||
1385 | This function does not support passing parameters using the FPA | |
1386 | variant of the APCS. It passes any floating point arguments in the | |
1387 | general registers and/or on the stack. */ | |
c906108c SS |
1388 | |
1389 | CORE_ADDR | |
ea7c478f | 1390 | arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
ed9a39eb | 1391 | int struct_return, CORE_ADDR struct_addr) |
c906108c | 1392 | { |
ed9a39eb JM |
1393 | char *fp; |
1394 | int argnum, argreg, nstack_size; | |
1395 | ||
1396 | /* Walk through the list of args and determine how large a temporary | |
1397 | stack is required. Need to take care here as structs may be | |
1398 | passed on the stack, and we have to to push them. */ | |
1399 | nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ | |
1400 | if (struct_return) /* The struct address goes in A1. */ | |
1401 | nstack_size += REGISTER_SIZE; | |
1402 | ||
1403 | /* Walk through the arguments and add their size to nstack_size. */ | |
1404 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 1405 | { |
c906108c | 1406 | int len; |
ed9a39eb JM |
1407 | struct type *arg_type; |
1408 | ||
1409 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1410 | len = TYPE_LENGTH (arg_type); | |
c906108c | 1411 | |
ed9a39eb JM |
1412 | /* ANSI C code passes float arguments as integers, K&R code |
1413 | passes float arguments as doubles. Correct for this here. */ | |
1414 | if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len) | |
1415 | nstack_size += FP_REGISTER_VIRTUAL_SIZE; | |
1416 | else | |
1417 | nstack_size += len; | |
1418 | } | |
c906108c | 1419 | |
ed9a39eb JM |
1420 | /* Allocate room on the stack, and initialize our stack frame |
1421 | pointer. */ | |
1422 | fp = NULL; | |
1423 | if (nstack_size > 0) | |
1424 | { | |
1425 | sp -= nstack_size; | |
1426 | fp = (char *) sp; | |
1427 | } | |
1428 | ||
1429 | /* Initialize the integer argument register pointer. */ | |
c906108c | 1430 | argreg = A1_REGNUM; |
c906108c | 1431 | |
ed9a39eb JM |
1432 | /* The struct_return pointer occupies the first parameter passing |
1433 | register. */ | |
c906108c | 1434 | if (struct_return) |
c5aa993b | 1435 | write_register (argreg++, struct_addr); |
c906108c | 1436 | |
ed9a39eb JM |
1437 | /* Process arguments from left to right. Store as many as allowed |
1438 | in the parameter passing registers (A1-A4), and save the rest on | |
1439 | the temporary stack. */ | |
c5aa993b | 1440 | for (argnum = 0; argnum < nargs; argnum++) |
c906108c | 1441 | { |
ed9a39eb | 1442 | int len; |
c5aa993b | 1443 | char *val; |
c5aa993b | 1444 | CORE_ADDR regval; |
ed9a39eb JM |
1445 | enum type_code typecode; |
1446 | struct type *arg_type, *target_type; | |
1447 | ||
1448 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1449 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1450 | len = TYPE_LENGTH (arg_type); | |
1451 | typecode = TYPE_CODE (arg_type); | |
1452 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1453 | ||
1454 | /* ANSI C code passes float arguments as integers, K&R code | |
1455 | passes float arguments as doubles. The .stabs record for | |
1456 | for ANSI prototype floating point arguments records the | |
1457 | type as FP_INTEGER, while a K&R style (no prototype) | |
1458 | .stabs records the type as FP_FLOAT. In this latter case | |
1459 | the compiler converts the float arguments to double before | |
1460 | calling the function. */ | |
1461 | if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len) | |
1462 | { | |
a37b3cc0 AC |
1463 | DOUBLEST dblval; |
1464 | dblval = extract_floating (val, len); | |
1465 | len = TARGET_DOUBLE_BIT / TARGET_CHAR_BIT; | |
1466 | val = alloca (len); | |
1467 | store_floating (val, len, dblval); | |
ed9a39eb | 1468 | } |
da59e081 JM |
1469 | #if 1 |
1470 | /* I don't know why this code was disable. The only logical use | |
1471 | for a function pointer is to call that function, so setting | |
1472 | the mode bit is perfectly fine. FN */ | |
ed9a39eb | 1473 | /* If the argument is a pointer to a function, and it is a Thumb |
c906108c | 1474 | function, set the low bit of the pointer. */ |
ed9a39eb JM |
1475 | if (TYPE_CODE_PTR == typecode |
1476 | && NULL != target_type | |
1477 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1478 | { |
ed9a39eb | 1479 | CORE_ADDR regval = extract_address (val, len); |
c906108c SS |
1480 | if (arm_pc_is_thumb (regval)) |
1481 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1482 | } | |
c906108c | 1483 | #endif |
ed9a39eb JM |
1484 | /* Copy the argument to general registers or the stack in |
1485 | register-sized pieces. Large arguments are split between | |
1486 | registers and stack. */ | |
1487 | while (len > 0) | |
c906108c | 1488 | { |
ed9a39eb JM |
1489 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1490 | ||
1491 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
c906108c | 1492 | { |
ed9a39eb JM |
1493 | /* It's an argument being passed in a general register. */ |
1494 | regval = extract_address (val, partial_len); | |
1495 | write_register (argreg++, regval); | |
c906108c | 1496 | } |
ed9a39eb JM |
1497 | else |
1498 | { | |
1499 | /* Push the arguments onto the stack. */ | |
1500 | write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); | |
1501 | fp += REGISTER_SIZE; | |
1502 | } | |
1503 | ||
1504 | len -= partial_len; | |
1505 | val += partial_len; | |
c906108c SS |
1506 | } |
1507 | } | |
c906108c SS |
1508 | |
1509 | /* Return adjusted stack pointer. */ | |
1510 | return sp; | |
1511 | } | |
1512 | ||
f079148d KB |
1513 | /* Pop the current frame. So long as the frame info has been initialized |
1514 | properly (see arm_init_extra_frame_info), this code works for dummy frames | |
1515 | as well as regular frames. I.e, there's no need to have a special case | |
1516 | for dummy frames. */ | |
c906108c | 1517 | void |
ed9a39eb | 1518 | arm_pop_frame (void) |
c906108c | 1519 | { |
c906108c | 1520 | int regnum; |
8b93c638 | 1521 | struct frame_info *frame = get_current_frame (); |
c3b4394c RE |
1522 | CORE_ADDR old_SP = (frame->frame - frame->extra_info->frameoffset |
1523 | + frame->extra_info->framesize); | |
c906108c | 1524 | |
f079148d | 1525 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
c3b4394c | 1526 | if (frame->saved_regs[regnum] != 0) |
f079148d | 1527 | write_register (regnum, |
c3b4394c | 1528 | read_memory_integer (frame->saved_regs[regnum], |
f079148d | 1529 | REGISTER_RAW_SIZE (regnum))); |
8b93c638 | 1530 | |
f079148d KB |
1531 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
1532 | write_register (SP_REGNUM, old_SP); | |
c906108c SS |
1533 | |
1534 | flush_cached_frames (); | |
1535 | } | |
1536 | ||
1537 | static void | |
ed9a39eb | 1538 | print_fpu_flags (int flags) |
c906108c | 1539 | { |
c5aa993b JM |
1540 | if (flags & (1 << 0)) |
1541 | fputs ("IVO ", stdout); | |
1542 | if (flags & (1 << 1)) | |
1543 | fputs ("DVZ ", stdout); | |
1544 | if (flags & (1 << 2)) | |
1545 | fputs ("OFL ", stdout); | |
1546 | if (flags & (1 << 3)) | |
1547 | fputs ("UFL ", stdout); | |
1548 | if (flags & (1 << 4)) | |
1549 | fputs ("INX ", stdout); | |
1550 | putchar ('\n'); | |
c906108c SS |
1551 | } |
1552 | ||
1553 | void | |
ed9a39eb | 1554 | arm_float_info (void) |
c906108c | 1555 | { |
c5aa993b JM |
1556 | register unsigned long status = read_register (FPS_REGNUM); |
1557 | int type; | |
1558 | ||
1559 | type = (status >> 24) & 127; | |
1560 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1561 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1562 | type); |
1563 | fputs ("mask: ", stdout); | |
1564 | print_fpu_flags (status >> 16); | |
1565 | fputs ("flags: ", stdout); | |
1566 | print_fpu_flags (status); | |
c906108c SS |
1567 | } |
1568 | ||
032758dc AC |
1569 | struct type * |
1570 | arm_register_type (int regnum) | |
1571 | { | |
1572 | if (regnum >= F0_REGNUM && regnum < F0_REGNUM + NUM_FREGS) | |
1573 | { | |
d7449b42 | 1574 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
032758dc AC |
1575 | return builtin_type_arm_ext_big; |
1576 | else | |
1577 | return builtin_type_arm_ext_littlebyte_bigword; | |
1578 | } | |
1579 | else | |
1580 | return builtin_type_int32; | |
1581 | } | |
1582 | ||
a37b3cc0 AC |
1583 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
1584 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. | |
1585 | It is thought that this is is the floating-point register format on | |
1586 | little-endian systems. */ | |
c906108c | 1587 | |
ed9a39eb JM |
1588 | static void |
1589 | convert_from_extended (void *ptr, void *dbl) | |
c906108c | 1590 | { |
a37b3cc0 | 1591 | DOUBLEST d; |
d7449b42 | 1592 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1593 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
1594 | else | |
1595 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1596 | ptr, &d); | |
1597 | floatformat_from_doublest (TARGET_DOUBLE_FORMAT, &d, dbl); | |
c906108c SS |
1598 | } |
1599 | ||
c5aa993b | 1600 | void |
ed9a39eb | 1601 | convert_to_extended (void *dbl, void *ptr) |
c906108c | 1602 | { |
a37b3cc0 AC |
1603 | DOUBLEST d; |
1604 | floatformat_to_doublest (TARGET_DOUBLE_FORMAT, ptr, &d); | |
d7449b42 | 1605 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
a37b3cc0 AC |
1606 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
1607 | else | |
1608 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, | |
1609 | &d, dbl); | |
c906108c | 1610 | } |
ed9a39eb | 1611 | |
c906108c | 1612 | static int |
ed9a39eb | 1613 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1614 | { |
1615 | if (cond == INST_AL || cond == INST_NV) | |
1616 | return 1; | |
1617 | ||
1618 | switch (cond) | |
1619 | { | |
1620 | case INST_EQ: | |
1621 | return ((status_reg & FLAG_Z) != 0); | |
1622 | case INST_NE: | |
1623 | return ((status_reg & FLAG_Z) == 0); | |
1624 | case INST_CS: | |
1625 | return ((status_reg & FLAG_C) != 0); | |
1626 | case INST_CC: | |
1627 | return ((status_reg & FLAG_C) == 0); | |
1628 | case INST_MI: | |
1629 | return ((status_reg & FLAG_N) != 0); | |
1630 | case INST_PL: | |
1631 | return ((status_reg & FLAG_N) == 0); | |
1632 | case INST_VS: | |
1633 | return ((status_reg & FLAG_V) != 0); | |
1634 | case INST_VC: | |
1635 | return ((status_reg & FLAG_V) == 0); | |
1636 | case INST_HI: | |
1637 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1638 | case INST_LS: | |
1639 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1640 | case INST_GE: | |
1641 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1642 | case INST_LT: | |
1643 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1644 | case INST_GT: | |
1645 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1646 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1647 | case INST_LE: |
1648 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1649 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1650 | } |
1651 | return 1; | |
1652 | } | |
1653 | ||
9512d7fd | 1654 | /* Support routines for single stepping. Calculate the next PC value. */ |
c906108c SS |
1655 | #define submask(x) ((1L << ((x) + 1)) - 1) |
1656 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1657 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1658 | #define sbits(obj,st,fn) \ | |
1659 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1660 | #define BranchDest(addr,instr) \ | |
1661 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1662 | #define ARM_PC_32 1 | |
1663 | ||
1664 | static unsigned long | |
ed9a39eb JM |
1665 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1666 | unsigned long status_reg) | |
c906108c SS |
1667 | { |
1668 | unsigned long res, shift; | |
1669 | int rm = bits (inst, 0, 3); | |
1670 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1671 | |
1672 | if (bit (inst, 4)) | |
c906108c SS |
1673 | { |
1674 | int rs = bits (inst, 8, 11); | |
1675 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1676 | } | |
1677 | else | |
1678 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1679 | |
1680 | res = (rm == 15 | |
c906108c | 1681 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1682 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1683 | : read_register (rm)); |
1684 | ||
1685 | switch (shifttype) | |
1686 | { | |
c5aa993b | 1687 | case 0: /* LSL */ |
c906108c SS |
1688 | res = shift >= 32 ? 0 : res << shift; |
1689 | break; | |
c5aa993b JM |
1690 | |
1691 | case 1: /* LSR */ | |
c906108c SS |
1692 | res = shift >= 32 ? 0 : res >> shift; |
1693 | break; | |
1694 | ||
c5aa993b JM |
1695 | case 2: /* ASR */ |
1696 | if (shift >= 32) | |
1697 | shift = 31; | |
c906108c SS |
1698 | res = ((res & 0x80000000L) |
1699 | ? ~((~res) >> shift) : res >> shift); | |
1700 | break; | |
1701 | ||
c5aa993b | 1702 | case 3: /* ROR/RRX */ |
c906108c SS |
1703 | shift &= 31; |
1704 | if (shift == 0) | |
1705 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1706 | else | |
c5aa993b | 1707 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1708 | break; |
1709 | } | |
1710 | ||
1711 | return res & 0xffffffff; | |
1712 | } | |
1713 | ||
c906108c SS |
1714 | /* Return number of 1-bits in VAL. */ |
1715 | ||
1716 | static int | |
ed9a39eb | 1717 | bitcount (unsigned long val) |
c906108c SS |
1718 | { |
1719 | int nbits; | |
1720 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1721 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1722 | return nbits; |
1723 | } | |
1724 | ||
c906108c | 1725 | static CORE_ADDR |
ed9a39eb | 1726 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1727 | { |
c5aa993b | 1728 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1729 | unsigned short inst1 = read_memory_integer (pc, 2); |
c5aa993b | 1730 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1731 | unsigned long offset; |
1732 | ||
1733 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1734 | { | |
1735 | CORE_ADDR sp; | |
1736 | ||
1737 | /* Fetch the saved PC from the stack. It's stored above | |
1738 | all of the other registers. */ | |
1739 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
1740 | sp = read_register (SP_REGNUM); | |
1741 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); | |
1742 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1743 | if (nextpc == pc) | |
1744 | error ("Infinite loop detected"); | |
1745 | } | |
1746 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1747 | { | |
1748 | unsigned long status = read_register (PS_REGNUM); | |
c5aa993b | 1749 | unsigned long cond = bits (inst1, 8, 11); |
c906108c SS |
1750 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
1751 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); | |
1752 | } | |
1753 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1754 | { | |
1755 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1756 | } | |
1757 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1758 | { | |
1759 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1760 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1761 | nextpc = pc_val + offset; |
1762 | } | |
1763 | ||
1764 | return nextpc; | |
1765 | } | |
1766 | ||
c906108c | 1767 | CORE_ADDR |
ed9a39eb | 1768 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1769 | { |
1770 | unsigned long pc_val; | |
1771 | unsigned long this_instr; | |
1772 | unsigned long status; | |
1773 | CORE_ADDR nextpc; | |
1774 | ||
1775 | if (arm_pc_is_thumb (pc)) | |
1776 | return thumb_get_next_pc (pc); | |
1777 | ||
1778 | pc_val = (unsigned long) pc; | |
1779 | this_instr = read_memory_integer (pc, 4); | |
1780 | status = read_register (PS_REGNUM); | |
c5aa993b | 1781 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1782 | |
1783 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1784 | { | |
1785 | switch (bits (this_instr, 24, 27)) | |
1786 | { | |
c5aa993b JM |
1787 | case 0x0: |
1788 | case 0x1: /* data processing */ | |
1789 | case 0x2: | |
1790 | case 0x3: | |
c906108c SS |
1791 | { |
1792 | unsigned long operand1, operand2, result = 0; | |
1793 | unsigned long rn; | |
1794 | int c; | |
c5aa993b | 1795 | |
c906108c SS |
1796 | if (bits (this_instr, 12, 15) != 15) |
1797 | break; | |
1798 | ||
1799 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1800 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1801 | error ("Illegal update to pc in instruction"); |
1802 | ||
1803 | /* Multiply into PC */ | |
1804 | c = (status & FLAG_C) ? 1 : 0; | |
1805 | rn = bits (this_instr, 16, 19); | |
1806 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1807 | |
c906108c SS |
1808 | if (bit (this_instr, 25)) |
1809 | { | |
1810 | unsigned long immval = bits (this_instr, 0, 7); | |
1811 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1812 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1813 | & 0xffffffff; | |
c906108c | 1814 | } |
c5aa993b | 1815 | else /* operand 2 is a shifted register */ |
c906108c | 1816 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1817 | |
c906108c SS |
1818 | switch (bits (this_instr, 21, 24)) |
1819 | { | |
c5aa993b | 1820 | case 0x0: /*and */ |
c906108c SS |
1821 | result = operand1 & operand2; |
1822 | break; | |
1823 | ||
c5aa993b | 1824 | case 0x1: /*eor */ |
c906108c SS |
1825 | result = operand1 ^ operand2; |
1826 | break; | |
1827 | ||
c5aa993b | 1828 | case 0x2: /*sub */ |
c906108c SS |
1829 | result = operand1 - operand2; |
1830 | break; | |
1831 | ||
c5aa993b | 1832 | case 0x3: /*rsb */ |
c906108c SS |
1833 | result = operand2 - operand1; |
1834 | break; | |
1835 | ||
c5aa993b | 1836 | case 0x4: /*add */ |
c906108c SS |
1837 | result = operand1 + operand2; |
1838 | break; | |
1839 | ||
c5aa993b | 1840 | case 0x5: /*adc */ |
c906108c SS |
1841 | result = operand1 + operand2 + c; |
1842 | break; | |
1843 | ||
c5aa993b | 1844 | case 0x6: /*sbc */ |
c906108c SS |
1845 | result = operand1 - operand2 + c; |
1846 | break; | |
1847 | ||
c5aa993b | 1848 | case 0x7: /*rsc */ |
c906108c SS |
1849 | result = operand2 - operand1 + c; |
1850 | break; | |
1851 | ||
c5aa993b JM |
1852 | case 0x8: |
1853 | case 0x9: | |
1854 | case 0xa: | |
1855 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1856 | result = (unsigned long) nextpc; |
1857 | break; | |
1858 | ||
c5aa993b | 1859 | case 0xc: /*orr */ |
c906108c SS |
1860 | result = operand1 | operand2; |
1861 | break; | |
1862 | ||
c5aa993b | 1863 | case 0xd: /*mov */ |
c906108c SS |
1864 | /* Always step into a function. */ |
1865 | result = operand2; | |
c5aa993b | 1866 | break; |
c906108c | 1867 | |
c5aa993b | 1868 | case 0xe: /*bic */ |
c906108c SS |
1869 | result = operand1 & ~operand2; |
1870 | break; | |
1871 | ||
c5aa993b | 1872 | case 0xf: /*mvn */ |
c906108c SS |
1873 | result = ~operand2; |
1874 | break; | |
1875 | } | |
1876 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1877 | ||
1878 | if (nextpc == pc) | |
1879 | error ("Infinite loop detected"); | |
1880 | break; | |
1881 | } | |
c5aa993b JM |
1882 | |
1883 | case 0x4: | |
1884 | case 0x5: /* data transfer */ | |
1885 | case 0x6: | |
1886 | case 0x7: | |
c906108c SS |
1887 | if (bit (this_instr, 20)) |
1888 | { | |
1889 | /* load */ | |
1890 | if (bits (this_instr, 12, 15) == 15) | |
1891 | { | |
1892 | /* rd == pc */ | |
c5aa993b | 1893 | unsigned long rn; |
c906108c | 1894 | unsigned long base; |
c5aa993b | 1895 | |
c906108c SS |
1896 | if (bit (this_instr, 22)) |
1897 | error ("Illegal update to pc in instruction"); | |
1898 | ||
1899 | /* byte write to PC */ | |
1900 | rn = bits (this_instr, 16, 19); | |
1901 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1902 | if (bit (this_instr, 24)) | |
1903 | { | |
1904 | /* pre-indexed */ | |
1905 | int c = (status & FLAG_C) ? 1 : 0; | |
1906 | unsigned long offset = | |
c5aa993b | 1907 | (bit (this_instr, 25) |
ed9a39eb | 1908 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1909 | : bits (this_instr, 0, 11)); |
c906108c SS |
1910 | |
1911 | if (bit (this_instr, 23)) | |
1912 | base += offset; | |
1913 | else | |
1914 | base -= offset; | |
1915 | } | |
c5aa993b | 1916 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1917 | 4); |
c5aa993b | 1918 | |
c906108c SS |
1919 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1920 | ||
1921 | if (nextpc == pc) | |
1922 | error ("Infinite loop detected"); | |
1923 | } | |
1924 | } | |
1925 | break; | |
c5aa993b JM |
1926 | |
1927 | case 0x8: | |
1928 | case 0x9: /* block transfer */ | |
c906108c SS |
1929 | if (bit (this_instr, 20)) |
1930 | { | |
1931 | /* LDM */ | |
1932 | if (bit (this_instr, 15)) | |
1933 | { | |
1934 | /* loading pc */ | |
1935 | int offset = 0; | |
1936 | ||
1937 | if (bit (this_instr, 23)) | |
1938 | { | |
1939 | /* up */ | |
1940 | unsigned long reglist = bits (this_instr, 0, 14); | |
1941 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1942 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1943 | offset += 4; |
1944 | } | |
1945 | else if (bit (this_instr, 24)) | |
1946 | offset = -4; | |
c5aa993b | 1947 | |
c906108c | 1948 | { |
c5aa993b JM |
1949 | unsigned long rn_val = |
1950 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1951 | nextpc = |
1952 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1953 | + offset), |
c906108c SS |
1954 | 4); |
1955 | } | |
1956 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1957 | if (nextpc == pc) | |
1958 | error ("Infinite loop detected"); | |
1959 | } | |
1960 | } | |
1961 | break; | |
c5aa993b JM |
1962 | |
1963 | case 0xb: /* branch & link */ | |
1964 | case 0xa: /* branch */ | |
c906108c SS |
1965 | { |
1966 | nextpc = BranchDest (pc, this_instr); | |
1967 | ||
1968 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1969 | if (nextpc == pc) | |
1970 | error ("Infinite loop detected"); | |
1971 | break; | |
1972 | } | |
c5aa993b JM |
1973 | |
1974 | case 0xc: | |
1975 | case 0xd: | |
1976 | case 0xe: /* coproc ops */ | |
1977 | case 0xf: /* SWI */ | |
c906108c SS |
1978 | break; |
1979 | ||
1980 | default: | |
1981 | fprintf (stderr, "Bad bit-field extraction\n"); | |
1982 | return (pc); | |
1983 | } | |
1984 | } | |
1985 | ||
1986 | return nextpc; | |
1987 | } | |
1988 | ||
9512d7fd FN |
1989 | /* single_step() is called just before we want to resume the inferior, |
1990 | if we want to single-step it but there is no hardware or kernel | |
1991 | single-step support. We find the target of the coming instruction | |
1992 | and breakpoint it. | |
1993 | ||
1994 | single_step is also called just after the inferior stops. If we had | |
1995 | set up a simulated single-step, we undo our damage. */ | |
1996 | ||
1997 | void | |
1998 | arm_software_single_step (ignore, insert_bpt) | |
1999 | int ignore; /* Signal, not needed */ | |
2000 | int insert_bpt; | |
2001 | { | |
2002 | static int next_pc; /* State between setting and unsetting. */ | |
2003 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ | |
2004 | ||
2005 | if (insert_bpt) | |
2006 | { | |
2007 | next_pc = arm_get_next_pc (read_register (PC_REGNUM)); | |
80fcf3f0 | 2008 | target_insert_breakpoint (next_pc, break_mem); |
9512d7fd FN |
2009 | } |
2010 | else | |
80fcf3f0 | 2011 | target_remove_breakpoint (next_pc, break_mem); |
9512d7fd | 2012 | } |
9512d7fd | 2013 | |
c906108c SS |
2014 | #include "bfd-in2.h" |
2015 | #include "libcoff.h" | |
2016 | ||
2017 | static int | |
ed9a39eb | 2018 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
2019 | { |
2020 | if (arm_pc_is_thumb (memaddr)) | |
2021 | { | |
c5aa993b JM |
2022 | static asymbol *asym; |
2023 | static combined_entry_type ce; | |
2024 | static struct coff_symbol_struct csym; | |
2025 | static struct _bfd fake_bfd; | |
2026 | static bfd_target fake_target; | |
c906108c SS |
2027 | |
2028 | if (csym.native == NULL) | |
2029 | { | |
2030 | /* Create a fake symbol vector containing a Thumb symbol. This is | |
2031 | solely so that the code in print_insn_little_arm() and | |
2032 | print_insn_big_arm() in opcodes/arm-dis.c will detect the presence | |
2033 | of a Thumb symbol and switch to decoding Thumb instructions. */ | |
c5aa993b JM |
2034 | |
2035 | fake_target.flavour = bfd_target_coff_flavour; | |
2036 | fake_bfd.xvec = &fake_target; | |
c906108c | 2037 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
2038 | csym.native = &ce; |
2039 | csym.symbol.the_bfd = &fake_bfd; | |
2040 | csym.symbol.name = "fake"; | |
2041 | asym = (asymbol *) & csym; | |
c906108c | 2042 | } |
c5aa993b | 2043 | |
c906108c | 2044 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 2045 | info->symbols = &asym; |
c906108c SS |
2046 | } |
2047 | else | |
2048 | info->symbols = NULL; | |
c5aa993b | 2049 | |
d7449b42 | 2050 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
2051 | return print_insn_big_arm (memaddr, info); |
2052 | else | |
2053 | return print_insn_little_arm (memaddr, info); | |
2054 | } | |
2055 | ||
ed9a39eb JM |
2056 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the |
2057 | program counter value to determine whether a 16-bit or 32-bit | |
2058 | breakpoint should be used. It returns a pointer to a string of | |
2059 | bytes that encode a breakpoint instruction, stores the length of | |
2060 | the string to *lenptr, and adjusts the program counter (if | |
2061 | necessary) to point to the actual memory location where the | |
c906108c SS |
2062 | breakpoint should be inserted. */ |
2063 | ||
2064 | unsigned char * | |
ed9a39eb | 2065 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c SS |
2066 | { |
2067 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) | |
2068 | { | |
d7449b42 | 2069 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c5aa993b JM |
2070 | { |
2071 | static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT; | |
2072 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
2073 | *lenptr = sizeof (thumb_breakpoint); | |
2074 | return thumb_breakpoint; | |
2075 | } | |
c906108c | 2076 | else |
c5aa993b JM |
2077 | { |
2078 | static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT; | |
2079 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
2080 | *lenptr = sizeof (thumb_breakpoint); | |
2081 | return thumb_breakpoint; | |
2082 | } | |
c906108c SS |
2083 | } |
2084 | else | |
2085 | { | |
d7449b42 | 2086 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c5aa993b JM |
2087 | { |
2088 | static char arm_breakpoint[] = ARM_BE_BREAKPOINT; | |
2089 | *lenptr = sizeof (arm_breakpoint); | |
2090 | return arm_breakpoint; | |
2091 | } | |
c906108c | 2092 | else |
c5aa993b JM |
2093 | { |
2094 | static char arm_breakpoint[] = ARM_LE_BREAKPOINT; | |
2095 | *lenptr = sizeof (arm_breakpoint); | |
2096 | return arm_breakpoint; | |
2097 | } | |
c906108c SS |
2098 | } |
2099 | } | |
ed9a39eb JM |
2100 | |
2101 | /* Extract from an array REGBUF containing the (raw) register state a | |
2102 | function return value of type TYPE, and copy that, in virtual | |
2103 | format, into VALBUF. */ | |
2104 | ||
2105 | void | |
2106 | arm_extract_return_value (struct type *type, | |
2107 | char regbuf[REGISTER_BYTES], | |
2108 | char *valbuf) | |
2109 | { | |
2110 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
2111 | convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf); | |
2112 | else | |
2113 | memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type)); | |
2114 | } | |
2115 | ||
2116 | /* Return non-zero if the PC is inside a thumb call thunk. */ | |
c906108c SS |
2117 | |
2118 | int | |
ed9a39eb | 2119 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
2120 | { |
2121 | CORE_ADDR start_addr; | |
2122 | ||
ed9a39eb JM |
2123 | /* Find the starting address of the function containing the PC. If |
2124 | the caller didn't give us a name, look it up at the same time. */ | |
c906108c SS |
2125 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) |
2126 | return 0; | |
2127 | ||
2128 | return strncmp (name, "_call_via_r", 11) == 0; | |
2129 | } | |
2130 | ||
ed9a39eb JM |
2131 | /* If PC is in a Thumb call or return stub, return the address of the |
2132 | target PC, which is in a register. The thunk functions are called | |
2133 | _called_via_xx, where x is the register name. The possible names | |
2134 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
2135 | |
2136 | CORE_ADDR | |
ed9a39eb | 2137 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 2138 | { |
c5aa993b | 2139 | char *name; |
c906108c SS |
2140 | CORE_ADDR start_addr; |
2141 | ||
2142 | /* Find the starting address and name of the function containing the PC. */ | |
2143 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
2144 | return 0; | |
2145 | ||
2146 | /* Call thunks always start with "_call_via_". */ | |
2147 | if (strncmp (name, "_call_via_", 10) == 0) | |
2148 | { | |
ed9a39eb JM |
2149 | /* Use the name suffix to determine which register contains the |
2150 | target PC. */ | |
c5aa993b JM |
2151 | static char *table[15] = |
2152 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
2153 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
2154 | }; | |
c906108c SS |
2155 | int regno; |
2156 | ||
2157 | for (regno = 0; regno <= 14; regno++) | |
2158 | if (strcmp (&name[10], table[regno]) == 0) | |
2159 | return read_register (regno); | |
2160 | } | |
ed9a39eb | 2161 | |
c5aa993b | 2162 | return 0; /* not a stub */ |
c906108c SS |
2163 | } |
2164 | ||
bc90b915 FN |
2165 | /* If the user changes the register disassembly flavor used for info register |
2166 | and other commands, we have to also switch the flavor used in opcodes | |
2167 | for disassembly output. | |
2168 | This function is run in the set disassembly_flavor command, and does that. */ | |
2169 | ||
2170 | static void | |
2171 | set_disassembly_flavor_sfunc (char *args, int from_tty, | |
2172 | struct cmd_list_element *c) | |
2173 | { | |
2174 | set_disassembly_flavor (); | |
2175 | } | |
2176 | \f | |
966fbf70 RE |
2177 | /* Return the ARM register name corresponding to register I. */ |
2178 | char * | |
2179 | arm_register_name(int i) | |
2180 | { | |
2181 | return arm_register_names[i]; | |
2182 | } | |
2183 | ||
bc90b915 FN |
2184 | static void |
2185 | set_disassembly_flavor (void) | |
2186 | { | |
2187 | const char *setname, *setdesc, **regnames; | |
2188 | int numregs, j; | |
2189 | ||
2190 | /* Find the flavor that the user wants in the opcodes table. */ | |
2191 | int current = 0; | |
2192 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); | |
2193 | while ((disassembly_flavor != setname) | |
2194 | && (current < num_flavor_options)) | |
2195 | get_arm_regnames (++current, &setname, &setdesc, ®names); | |
2196 | current_option = current; | |
2197 | ||
2198 | /* Fill our copy. */ | |
2199 | for (j = 0; j < numregs; j++) | |
2200 | arm_register_names[j] = (char *) regnames[j]; | |
2201 | ||
2202 | /* Adjust case. */ | |
2203 | if (isupper (*regnames[PC_REGNUM])) | |
2204 | { | |
2205 | arm_register_names[FPS_REGNUM] = "FPS"; | |
2206 | arm_register_names[PS_REGNUM] = "CPSR"; | |
2207 | } | |
2208 | else | |
2209 | { | |
2210 | arm_register_names[FPS_REGNUM] = "fps"; | |
2211 | arm_register_names[PS_REGNUM] = "cpsr"; | |
2212 | } | |
2213 | ||
2214 | /* Synchronize the disassembler. */ | |
2215 | set_arm_regname_option (current); | |
2216 | } | |
2217 | ||
2218 | /* arm_othernames implements the "othernames" command. This is kind | |
2219 | of hacky, and I prefer the set-show disassembly-flavor which is | |
2220 | also used for the x86 gdb. I will keep this around, however, in | |
2221 | case anyone is actually using it. */ | |
2222 | ||
2223 | static void | |
2224 | arm_othernames (char *names, int n) | |
2225 | { | |
2226 | /* Circle through the various flavors. */ | |
2227 | current_option = (current_option + 1) % num_flavor_options; | |
2228 | ||
2229 | disassembly_flavor = valid_flavors[current_option]; | |
2230 | set_disassembly_flavor (); | |
2231 | } | |
2232 | ||
a42dd537 KB |
2233 | /* Fetch, and possibly build, an appropriate link_map_offsets structure |
2234 | for ARM linux targets using the struct offsets defined in <link.h>. | |
2235 | Note, however, that link.h is not actually referred to in this file. | |
2236 | Instead, the relevant structs offsets were obtained from examining | |
2237 | link.h. (We can't refer to link.h from this file because the host | |
2238 | system won't necessarily have it, or if it does, the structs which | |
2239 | it defines will refer to the host system, not the target.) */ | |
2240 | ||
2241 | struct link_map_offsets * | |
2242 | arm_linux_svr4_fetch_link_map_offsets (void) | |
2243 | { | |
2244 | static struct link_map_offsets lmo; | |
2245 | static struct link_map_offsets *lmp = 0; | |
2246 | ||
2247 | if (lmp == 0) | |
2248 | { | |
2249 | lmp = &lmo; | |
2250 | ||
2251 | lmo.r_debug_size = 8; /* Actual size is 20, but this is all we | |
2252 | need. */ | |
2253 | ||
2254 | lmo.r_map_offset = 4; | |
2255 | lmo.r_map_size = 4; | |
2256 | ||
2257 | lmo.link_map_size = 20; /* Actual size is 552, but this is all we | |
2258 | need. */ | |
2259 | ||
2260 | lmo.l_addr_offset = 0; | |
2261 | lmo.l_addr_size = 4; | |
2262 | ||
2263 | lmo.l_name_offset = 4; | |
2264 | lmo.l_name_size = 4; | |
2265 | ||
2266 | lmo.l_next_offset = 12; | |
2267 | lmo.l_next_size = 4; | |
2268 | ||
2269 | lmo.l_prev_offset = 16; | |
2270 | lmo.l_prev_size = 4; | |
2271 | } | |
2272 | ||
2273 | return lmp; | |
2274 | } | |
2275 | ||
c906108c | 2276 | void |
ed9a39eb | 2277 | _initialize_arm_tdep (void) |
c906108c | 2278 | { |
bc90b915 FN |
2279 | struct ui_file *stb; |
2280 | long length; | |
96baa820 | 2281 | struct cmd_list_element *new_cmd; |
53904c9e AC |
2282 | const char *setname; |
2283 | const char *setdesc; | |
2284 | const char **regnames; | |
bc90b915 FN |
2285 | int numregs, i, j; |
2286 | static char *helptext; | |
085dd6e6 | 2287 | |
c906108c | 2288 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 2289 | |
bc90b915 FN |
2290 | /* Get the number of possible sets of register names defined in opcodes. */ |
2291 | num_flavor_options = get_arm_regname_num_options (); | |
2292 | ||
085dd6e6 | 2293 | /* Sync the opcode insn printer with our register viewer: */ |
bc90b915 | 2294 | parse_arm_disassembler_option ("reg-names-std"); |
c5aa993b | 2295 | |
bc90b915 FN |
2296 | /* Begin creating the help text. */ |
2297 | stb = mem_fileopen (); | |
2298 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ | |
2299 | The valid values are:\n"); | |
ed9a39eb | 2300 | |
bc90b915 FN |
2301 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
2302 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); | |
2303 | for (i = 0; i < num_flavor_options; i++) | |
2304 | { | |
2305 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); | |
53904c9e | 2306 | valid_flavors[i] = setname; |
bc90b915 FN |
2307 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
2308 | setdesc); | |
2309 | /* Copy the default names (if found) and synchronize disassembler. */ | |
2310 | if (!strcmp (setname, "std")) | |
2311 | { | |
53904c9e | 2312 | disassembly_flavor = setname; |
bc90b915 FN |
2313 | current_option = i; |
2314 | for (j = 0; j < numregs; j++) | |
2315 | arm_register_names[j] = (char *) regnames[j]; | |
2316 | set_arm_regname_option (i); | |
2317 | } | |
2318 | } | |
2319 | /* Mark the end of valid options. */ | |
2320 | valid_flavors[num_flavor_options] = NULL; | |
c906108c | 2321 | |
bc90b915 FN |
2322 | /* Finish the creation of the help text. */ |
2323 | fprintf_unfiltered (stb, "The default is \"std\"."); | |
2324 | helptext = ui_file_xstrdup (stb, &length); | |
2325 | ui_file_delete (stb); | |
ed9a39eb | 2326 | |
bc90b915 | 2327 | /* Add the disassembly-flavor command */ |
96baa820 | 2328 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb | 2329 | valid_flavors, |
1ed2a135 | 2330 | &disassembly_flavor, |
bc90b915 | 2331 | helptext, |
ed9a39eb | 2332 | &setlist); |
96baa820 | 2333 | new_cmd->function.sfunc = set_disassembly_flavor_sfunc; |
ed9a39eb JM |
2334 | add_show_from_set (new_cmd, &showlist); |
2335 | ||
c906108c SS |
2336 | /* ??? Maybe this should be a boolean. */ |
2337 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 2338 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 2339 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 2340 | &showlist); |
c906108c | 2341 | |
bc90b915 FN |
2342 | /* Add the deprecated "othernames" command */ |
2343 | ||
2344 | add_com ("othernames", class_obscure, arm_othernames, | |
2345 | "Switch to the next set of register names."); | |
c3b4394c RE |
2346 | |
2347 | /* Fill in the prologue_cache fields. */ | |
2348 | prologue_cache.extra_info = (struct frame_extra_info *) | |
2349 | xcalloc (1, sizeof (struct frame_extra_info)); | |
2350 | prologue_cache.saved_regs = (CORE_ADDR *) | |
2351 | xcalloc (1, SIZEOF_FRAME_SAVED_REGS); | |
c906108c SS |
2352 | } |
2353 | ||
ed9a39eb JM |
2354 | /* Test whether the coff symbol specific value corresponds to a Thumb |
2355 | function. */ | |
2356 | ||
c906108c | 2357 | int |
c5aa993b | 2358 | coff_sym_is_thumb (int val) |
c906108c | 2359 | { |
c5aa993b JM |
2360 | return (val == C_THUMBEXT || |
2361 | val == C_THUMBSTAT || | |
2362 | val == C_THUMBEXTFUNC || | |
2363 | val == C_THUMBSTATFUNC || | |
2364 | val == C_THUMBLABEL); | |
c906108c | 2365 | } |