[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 2002-2015 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_TDEP_H
#define ARM_TDEP_H

/* Forward declarations.  */
struct gdbarch;
struct regset;
struct address_space;

#include "arch/arm.h"

/* Say how long FP registers are.  Used for documentation purposes and
   code readability in this header.  IEEE extended doubles are 80
   bits.  DWORD aligned they use 96 bits.  */
#define FP_REGISTER_SIZE	12

/* Say how long VFP double precision registers are.  Used for documentation
   purposes and code readability.  These are fixed at 64 bits.  */
#define VFP_REGISTER_SIZE	8

/* Number of machine registers.  The only define actually required 
   is gdbarch_num_regs.  The other definitions are used for documentation
   purposes and code readability.  */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
   (and called PS for processor status) so the status bits can be cleared
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
   in PS.  */
#define NUM_FREGS	8	/* Number of floating point registers.  */
#define NUM_SREGS	2	/* Number of status registers.  */
#define NUM_GREGS	16	/* Number of general purpose registers.  */


/* Type of floating-point code in use by inferior.  There are really 3 models
   that are traditionally supported (plus the endianness issue), but gcc can
   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
   functions are passed in floating-point registers.  

   In addition to the traditional models, VFP adds two more. 

   If you update this enum, don't forget to update fp_model_strings in 
   arm-tdep.c.  */

enum arm_float_model
{
  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
  ARM_FLOAT_LAST	/* Keep at end.  */
};

/* ABI used by the inferior.  */
enum arm_abi_kind
{
  ARM_ABI_AUTO,
  ARM_ABI_APCS,
  ARM_ABI_AAPCS,
  ARM_ABI_LAST
};

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Target-dependent structure in gdbarch.  */
struct gdbarch_tdep
{
  /* The ABI for this architecture.  It should never be set to
     ARM_ABI_AUTO.  */
  enum arm_abi_kind arm_abi;

  enum arm_float_model fp_model; /* Floating point calling conventions.  */

  int have_fpa_registers;	/* Does the target report the FPA registers?  */
  int have_wmmx_registers;	/* Does the target report the WMMX registers?  */
  /* The number of VFP registers reported by the target.  It is zero
     if VFP registers are not supported.  */
  int vfp_register_count;
  int have_vfp_pseudos;		/* Are we synthesizing the single precision
				   VFP registers?  */
  int have_neon_pseudos;	/* Are we synthesizing the quad precision
				   NEON registers?  Requires
				   have_vfp_pseudos.  */
  int have_neon;		/* Do we have a NEON unit?  */

  int is_m;			/* Does the target follow the "M" profile.  */
  CORE_ADDR lowest_pc;		/* Lowest address at which instructions 
				   will appear.  */

  const gdb_byte *arm_breakpoint;	/* Breakpoint pattern for an ARM insn.  */
  int arm_breakpoint_size;	/* And its size.  */
  const gdb_byte *thumb_breakpoint;	/* Breakpoint pattern for a Thumb insn.  */
  int thumb_breakpoint_size;	/* And its size.  */

  /* If the Thumb breakpoint is an undefined instruction (which is
     affected by IT blocks) rather than a BKPT instruction (which is
     not), then we need a 32-bit Thumb breakpoint to preserve the
     instruction count in IT blocks.  */
  const gdb_byte *thumb2_breakpoint;
  int thumb2_breakpoint_size;

  int jb_pc;			/* Offset to PC value in jump buffer.
				   If this is negative, longjmp support
				   will be disabled.  */
  size_t jb_elt_size;		/* And the size of each entry in the buf.  */

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* ISA-specific data types.  */
  struct type *arm_ext_type;
  struct type *neon_double_type;
  struct type *neon_quad_type;

  /* Return the expected next PC if FRAME is stopped at a syscall
     instruction.  */
  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);

   /* syscall record.  */
  int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};

/* Structures used for displaced stepping.  */

/* The maximum number of temporaries available for displaced instructions.  */
#define DISPLACED_TEMPS			16
/* The maximum number of modified instructions generated for one single-stepped
   instruction, including the breakpoint (usually at the end of the instruction
   sequence) and any scratch words, etc.  */
#define DISPLACED_MODIFIED_INSNS	8

struct displaced_step_closure
{
  ULONGEST tmp[DISPLACED_TEMPS];
  int rd;
  int wrote_to_pc;
  union
  {
    struct
    {
      int xfersize;
      int rn;			   /* Writeback register.  */
      unsigned int immed : 1;      /* Offset is immediate.  */
      unsigned int writeback : 1;  /* Perform base-register writeback.  */
      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
    } ldst;

    struct
    {
      unsigned long dest;
      unsigned int link : 1;
      unsigned int exchange : 1;
      unsigned int cond : 4;
    } branch;

    struct
    {
      unsigned int regmask;
      int rn;
      CORE_ADDR xfer_addr;
      unsigned int load : 1;
      unsigned int user : 1;
      unsigned int increment : 1;
      unsigned int before : 1;
      unsigned int writeback : 1;
      unsigned int cond : 4;
    } block;

    struct
    {
      unsigned int immed : 1;
    } preload;

    struct
    {
      /* If non-NULL, override generic SVC handling (e.g. for a particular
         OS).  */
      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
			  struct displaced_step_closure *dsc);
    } svc;
  } u;

  /* The size of original instruction, 2 or 4.  */
  unsigned int insn_size;
  /* True if the original insn (and thus all replacement insns) are Thumb
     instead of ARM.   */
  unsigned int is_thumb;

  /* The slots in the array is used in this way below,
     - ARM instruction occupies one slot,
     - Thumb 16 bit instruction occupies one slot,
     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
  unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
  int numinsns;
  CORE_ADDR insn_addr;
  CORE_ADDR scratch_base;
  void (*cleanup) (struct gdbarch *, struct regcache *,
		   struct displaced_step_closure *);
};

/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
   write may write to the PC, specifies the way the CPSR T bit, etc. is
   modified by the instruction.  */

enum pc_write_style
{
  BRANCH_WRITE_PC,
  BX_WRITE_PC,
  LOAD_WRITE_PC,
  ALU_WRITE_PC,
  CANNOT_WRITE_PC
};

extern void
  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct regcache *regs,
			      struct displaced_step_closure *dsc);
extern void
  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct displaced_step_closure *dsc);
extern ULONGEST
  displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
		      int regno);
extern void
  displaced_write_reg (struct regcache *regs,
		       struct displaced_step_closure *dsc, int regno,
		       ULONGEST val, enum pc_write_style write_pc);

CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
void arm_insert_single_step_breakpoint (struct gdbarch *,
					struct address_space *, CORE_ADDR);
int arm_deal_with_atomic_sequence (struct frame_info *);
int arm_software_single_step (struct frame_info *);
int arm_frame_is_thumb (struct frame_info *frame);

extern struct displaced_step_closure *
  arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
				struct regcache *);
extern void arm_displaced_step_fixup (struct gdbarch *,
				      struct displaced_step_closure *,
				      CORE_ADDR, CORE_ADDR, struct regcache *);

/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
extern int arm_psr_thumb_bit (struct gdbarch *);

/* Is the instruction at the given memory address a Thumb or ARM
   instruction?  */
extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

extern int arm_process_record (struct gdbarch *gdbarch, 
                               struct regcache *regcache, CORE_ADDR addr);
/* Functions exported from armbsd-tdep.h.  */

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */

extern void
  armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
				       iterate_over_regset_sections_cb *cb,
				       void *cb_data,
				       const struct regcache *regcache);

/* Target descriptions.  */
extern struct target_desc *tdesc_arm_with_m;
extern struct target_desc *tdesc_arm_with_iwmmxt;
extern struct target_desc *tdesc_arm_with_vfpv2;
extern struct target_desc *tdesc_arm_with_vfpv3;
extern struct target_desc *tdesc_arm_with_neon;

#endif /* arm-tdep.h */
Commit	Line	Data
34e8f22d	1	/* Common target dependent code for GDB on ARM systems.
32d0add0	2	Copyright (C) 2002-2015 Free Software Foundation, Inc.
34e8f22d RE	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
a9762ec7	8	the Free Software Foundation; either version 3 of the License, or
34e8f22d RE	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
a9762ec7	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
34e8f22d	18
47ccd048 MK	19	#ifndef ARM_TDEP_H
	20	#define ARM_TDEP_H
	21
cb587d83	22	/* Forward declarations. */
47ccd048	23	struct gdbarch;
cb587d83	24	struct regset;
3352110b	25	struct address_space;
cb587d83	26
ec741292	27	#include "arch/arm.h"
34e8f22d	28
34e8f22d RE	29	/* Say how long FP registers are. Used for documentation purposes and
	30	code readability in this header. IEEE extended doubles are 80
	31	bits. DWORD aligned they use 96 bits. */
7a5ea0d4	32	#define FP_REGISTER_SIZE 12
34e8f22d	33
3184d3f9 JL	34	/* Say how long VFP double precision registers are. Used for documentation
	35	purposes and code readability. These are fixed at 64 bits. */
	36	#define VFP_REGISTER_SIZE 8
	37
34e8f22d	38	/* Number of machine registers. The only define actually required
f57d151a	39	is gdbarch_num_regs. The other definitions are used for documentation
34e8f22d RE	40	purposes and code readability. */
	41	/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
	42	(and called PS for processor status) so the status bits can be cleared
	43	from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
	44	in PS. */
	45	#define NUM_FREGS 8 /* Number of floating point registers. */
	46	#define NUM_SREGS 2 /* Number of status registers. */
	47	#define NUM_GREGS 16 /* Number of general purpose registers. */
	48
	49
9779414d	50
08216dd7 RE	51	/* Type of floating-point code in use by inferior. There are really 3 models
	52	that are traditionally supported (plus the endianness issue), but gcc can
	53	only generate 2 of those. The third is APCS_FLOAT, where arguments to
	54	functions are passed in floating-point registers.
	55
fd50bc42 RE	56	In addition to the traditional models, VFP adds two more.
	57
	58	If you update this enum, don't forget to update fp_model_strings in
	59	arm-tdep.c. */
08216dd7 RE	60
	61	enum arm_float_model
	62	{
fd50bc42 RE	63	ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
	64	ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
	65	ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
	66	ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
	67	ARM_FLOAT_VFP, /* Full VFP calling convention. */
	68	ARM_FLOAT_LAST /* Keep at end. */
08216dd7 RE	69	};
08216dd7 RE	70
28e97307 DJ	71	/* ABI used by the inferior. */
	72	enum arm_abi_kind
	73	{
	74	ARM_ABI_AUTO,
	75	ARM_ABI_APCS,
	76	ARM_ABI_AAPCS,
	77	ARM_ABI_LAST
	78	};
fd50bc42	79
7c00367c MK	80	/* Convention for returning structures. */
	81
	82	enum struct_return
	83	{
	84	pcc_struct_return, /* Return "short" structures in memory. */
	85	reg_struct_return /* Return "short" structures in registers. */
	86	};
	87
97e03143 RE	88	/* Target-dependent structure in gdbarch. */
	89	struct gdbarch_tdep
	90	{
28e97307 DJ	91	/* The ABI for this architecture. It should never be set to
	92	ARM_ABI_AUTO. */
	93	enum arm_abi_kind arm_abi;
	94
08216dd7 RE	95	enum arm_float_model fp_model; /* Floating point calling conventions. */
08216dd7 RE	96
ff6f572f	97	int have_fpa_registers; /* Does the target report the FPA registers? */
a56cc1ce	98	int have_wmmx_registers; /* Does the target report the WMMX registers? */
330c6ca9 YQ	99	/* The number of VFP registers reported by the target. It is zero
	100	if VFP registers are not supported. */
	101	int vfp_register_count;
58d6951d DJ	102	int have_vfp_pseudos; /* Are we synthesizing the single precision
	103	VFP registers? */
	104	int have_neon_pseudos; /* Are we synthesizing the quad precision
	105	NEON registers? Requires
	106	have_vfp_pseudos. */
	107	int have_neon; /* Do we have a NEON unit? */
ff6f572f	108
9779414d	109	int is_m; /* Does the target follow the "M" profile. */
97e03143 RE	110	CORE_ADDR lowest_pc; /* Lowest address at which instructions
97e03143 RE	111	will appear. */
9df628e0	112
948f8e3d	113	const gdb_byte arm_breakpoint; / Breakpoint pattern for an ARM insn. */
9df628e0	114	int arm_breakpoint_size; /* And its size. */
948f8e3d	115	const gdb_byte thumb_breakpoint; / Breakpoint pattern for a Thumb insn. */
9df628e0 RE	116	int thumb_breakpoint_size; /* And its size. */
9df628e0 RE	117
177321bd DJ	118	/* If the Thumb breakpoint is an undefined instruction (which is
	119	affected by IT blocks) rather than a BKPT instruction (which is
	120	not), then we need a 32-bit Thumb breakpoint to preserve the
	121	instruction count in IT blocks. */
948f8e3d	122	const gdb_byte *thumb2_breakpoint;
177321bd DJ	123	int thumb2_breakpoint_size;
177321bd DJ	124
0963b4bd	125	int jb_pc; /* Offset to PC value in jump buffer.
9df628e0 RE	126	If this is negative, longjmp support
	127	will be disabled. */
	128	size_t jb_elt_size; /* And the size of each entry in the buf. */
cb587d83	129
7c00367c MK	130	/* Convention for returning structures. */
	131	enum struct_return struct_return;
	132
27067745 UW	133	/* ISA-specific data types. */
27067745 UW	134	struct type *arm_ext_type;
58d6951d DJ	135	struct type *neon_double_type;
58d6951d DJ	136	struct type *neon_quad_type;
25b41d01 YQ	137
	138	/* Return the expected next PC if FRAME is stopped at a syscall
	139	instruction. */
	140	CORE_ADDR (syscall_next_pc) (struct frame_info frame);
72508ac0	141
97dfe206 OJ	142	/* syscall record. */
97dfe206 OJ	143	int (arm_syscall_record) (struct regcache regcache, unsigned long svc_number);
97e03143 RE	144	};
97e03143 RE	145
cca44b1b JB	146	/* Structures used for displaced stepping. */
	147
	148	/* The maximum number of temporaries available for displaced instructions. */
	149	#define DISPLACED_TEMPS 16
	150	/* The maximum number of modified instructions generated for one single-stepped
	151	instruction, including the breakpoint (usually at the end of the instruction
	152	sequence) and any scratch words, etc. */
	153	#define DISPLACED_MODIFIED_INSNS 8
	154
	155	struct displaced_step_closure
	156	{
	157	ULONGEST tmp[DISPLACED_TEMPS];
	158	int rd;
	159	int wrote_to_pc;
	160	union
	161	{
	162	struct
	163	{
	164	int xfersize;
	165	int rn; /* Writeback register. */
	166	unsigned int immed : 1; /* Offset is immediate. */
	167	unsigned int writeback : 1; /* Perform base-register writeback. */
	168	unsigned int restore_r4 : 1; /* Used r4 as scratch. */
	169	} ldst;
	170
	171	struct
	172	{
	173	unsigned long dest;
	174	unsigned int link : 1;
	175	unsigned int exchange : 1;
	176	unsigned int cond : 4;
	177	} branch;
	178
	179	struct
	180	{
	181	unsigned int regmask;
	182	int rn;
	183	CORE_ADDR xfer_addr;
	184	unsigned int load : 1;
	185	unsigned int user : 1;
	186	unsigned int increment : 1;
	187	unsigned int before : 1;
	188	unsigned int writeback : 1;
	189	unsigned int cond : 4;
	190	} block;
	191
	192	struct
	193	{
	194	unsigned int immed : 1;
	195	} preload;
	196
	197	struct
	198	{
	199	/* If non-NULL, override generic SVC handling (e.g. for a particular
	200	OS). */
bd18283a	201	int (copy_svc_os) (struct gdbarch gdbarch, struct regcache *regs,
cca44b1b JB	202	struct displaced_step_closure *dsc);
	203	} svc;
	204	} u;
4db71c0b YQ	205
	206	/* The size of original instruction, 2 or 4. */
	207	unsigned int insn_size;
	208	/* True if the original insn (and thus all replacement insns) are Thumb
	209	instead of ARM. */
	210	unsigned int is_thumb;
	211
	212	/* The slots in the array is used in this way below,
	213	- ARM instruction occupies one slot,
	214	- Thumb 16 bit instruction occupies one slot,
	215	- Thumb 32-bit instruction occupies two slots, one part for each. */
cca44b1b JB	216	unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
	217	int numinsns;
	218	CORE_ADDR insn_addr;
	219	CORE_ADDR scratch_base;
	220	void (cleanup) (struct gdbarch , struct regcache *,
	221	struct displaced_step_closure *);
	222	};
	223
	224	/* Values for the WRITE_PC argument to displaced_write_reg. If the register
	225	write may write to the PC, specifies the way the CPSR T bit, etc. is
	226	modified by the instruction. */
	227
	228	enum pc_write_style
	229	{
	230	BRANCH_WRITE_PC,
	231	BX_WRITE_PC,
	232	LOAD_WRITE_PC,
	233	ALU_WRITE_PC,
	234	CANNOT_WRITE_PC
	235	};
	236
	237	extern void
b434a28f YQ	238	arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
b434a28f YQ	239	CORE_ADDR to, struct regcache *regs,
cca44b1b JB	240	struct displaced_step_closure *dsc);
	241	extern void
	242	arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
	243	CORE_ADDR to, struct displaced_step_closure *dsc);
	244	extern ULONGEST
36073a92 YQ	245	displaced_read_reg (struct regcache regs, struct displaced_step_closure dsc,
36073a92 YQ	246	int regno);
cca44b1b JB	247	extern void
	248	displaced_write_reg (struct regcache *regs,
	249	struct displaced_step_closure *dsc, int regno,
	250	ULONGEST val, enum pc_write_style write_pc);
7c00367c	251
6dc13412	252	CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
daddc3c1	253	CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
18819fa6 UW	254	void arm_insert_single_step_breakpoint (struct gdbarch *,
18819fa6 UW	255	struct address_space *, CORE_ADDR);
35f73cfc	256	int arm_deal_with_atomic_sequence (struct frame_info *);
0b1b3e42	257	int arm_software_single_step (struct frame_info *);
25b41d01	258	int arm_frame_is_thumb (struct frame_info *frame);
190dce09	259
cca44b1b JB	260	extern struct displaced_step_closure *
	261	arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
	262	struct regcache *);
	263	extern void arm_displaced_step_fixup (struct gdbarch *,
	264	struct displaced_step_closure *,
	265	CORE_ADDR, CORE_ADDR, struct regcache *);
	266
478fd957 UW	267	/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
	268	extern int arm_psr_thumb_bit (struct gdbarch *);
	269
e3039479 UW	270	/* Is the instruction at the given memory address a Thumb or ARM
	271	instruction? */
	272	extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
	273
72508ac0 PO	274	extern int arm_process_record (struct gdbarch *gdbarch,
72508ac0 PO	275	struct regcache *regcache, CORE_ADDR addr);
47ccd048 MK	276	/* Functions exported from armbsd-tdep.h. */
	277
	278	/* Return the appropriate register set for the core section identified
	279	by SECT_NAME and SECT_SIZE. */
	280
ed09174e AA	281	extern void
	282	armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
	283	iterate_over_regset_sections_cb *cb,
	284	void *cb_data,
	285	const struct regcache *regcache);
47ccd048	286
ef7e8358 UW	287	/* Target descriptions. */
	288	extern struct target_desc *tdesc_arm_with_m;
	289	extern struct target_desc *tdesc_arm_with_iwmmxt;
	290	extern struct target_desc *tdesc_arm_with_vfpv2;
	291	extern struct target_desc *tdesc_arm_with_vfpv3;
	292	extern struct target_desc *tdesc_arm_with_neon;
	293
47ccd048	294	#endif /* arm-tdep.h */