Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
32d0add0 | 2 | Copyright (C) 1995-2015 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
bd9e6534 | 22 | #include "linux-aarch32-low.h" |
0a30fbc4 | 23 | |
bd9e6534 | 24 | #include <sys/uio.h> |
3743bb4f DE |
25 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
26 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
27 | #ifndef ELFMAG0 | |
58d6951d | 28 | #include <elf.h> |
3743bb4f | 29 | #endif |
5826e159 | 30 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 31 | #include <signal.h> |
9308fc88 | 32 | |
8689682c AT |
33 | #include "arch/arm.h" |
34 | ||
58d6951d | 35 | /* Defined in auto-generated files. */ |
d05b4ac3 | 36 | void init_registers_arm (void); |
3aee8918 PA |
37 | extern const struct target_desc *tdesc_arm; |
38 | ||
d05b4ac3 | 39 | void init_registers_arm_with_iwmmxt (void); |
3aee8918 PA |
40 | extern const struct target_desc *tdesc_arm_with_iwmmxt; |
41 | ||
58d6951d | 42 | void init_registers_arm_with_vfpv2 (void); |
3aee8918 PA |
43 | extern const struct target_desc *tdesc_arm_with_vfpv2; |
44 | ||
58d6951d | 45 | void init_registers_arm_with_vfpv3 (void); |
3aee8918 PA |
46 | extern const struct target_desc *tdesc_arm_with_vfpv3; |
47 | ||
9308fc88 DJ |
48 | #ifndef PTRACE_GET_THREAD_AREA |
49 | #define PTRACE_GET_THREAD_AREA 22 | |
50 | #endif | |
51 | ||
fb1e4ffc DJ |
52 | #ifndef PTRACE_GETWMMXREGS |
53 | # define PTRACE_GETWMMXREGS 18 | |
54 | # define PTRACE_SETWMMXREGS 19 | |
55 | #endif | |
56 | ||
58d6951d DJ |
57 | #ifndef PTRACE_GETVFPREGS |
58 | # define PTRACE_GETVFPREGS 27 | |
59 | # define PTRACE_SETVFPREGS 28 | |
60 | #endif | |
61 | ||
09b4ad9f UW |
62 | #ifndef PTRACE_GETHBPREGS |
63 | #define PTRACE_GETHBPREGS 29 | |
64 | #define PTRACE_SETHBPREGS 30 | |
65 | #endif | |
66 | ||
67 | /* Information describing the hardware breakpoint capabilities. */ | |
71487fd7 | 68 | static struct |
09b4ad9f UW |
69 | { |
70 | unsigned char arch; | |
71 | unsigned char max_wp_length; | |
72 | unsigned char wp_count; | |
73 | unsigned char bp_count; | |
71487fd7 | 74 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
75 | |
76 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
77 | typedef enum | |
78 | { | |
79 | arm_hwbp_break = 0, | |
80 | arm_hwbp_load = 1, | |
81 | arm_hwbp_store = 2, | |
82 | arm_hwbp_access = 3 | |
83 | } arm_hwbp_type; | |
84 | ||
8689682c AT |
85 | /* Enum describing the different kinds of breakpoints. */ |
86 | enum arm_breakpoint_kinds | |
87 | { | |
88 | ARM_BP_KIND_THUMB = 2, | |
89 | ARM_BP_KIND_THUMB2 = 3, | |
90 | ARM_BP_KIND_ARM = 4, | |
91 | }; | |
92 | ||
09b4ad9f UW |
93 | /* Type describing an ARM Hardware Breakpoint Control register value. */ |
94 | typedef unsigned int arm_hwbp_control_t; | |
95 | ||
96 | /* Structure used to keep track of hardware break-/watch-points. */ | |
97 | struct arm_linux_hw_breakpoint | |
98 | { | |
99 | /* Address to break on, or being watched. */ | |
100 | unsigned int address; | |
101 | /* Control register for break-/watch- point. */ | |
102 | arm_hwbp_control_t control; | |
103 | }; | |
104 | ||
105 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
106 | assume a maximum number of supported break-/watchpoints. */ | |
107 | #define MAX_BPTS 32 | |
108 | #define MAX_WPTS 32 | |
109 | ||
110 | /* Per-process arch-specific data we want to keep. */ | |
111 | struct arch_process_info | |
112 | { | |
113 | /* Hardware breakpoints for this process. */ | |
114 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
115 | /* Hardware watchpoints for this process. */ | |
116 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
117 | }; | |
118 | ||
119 | /* Per-thread arch-specific data we want to keep. */ | |
120 | struct arch_lwp_info | |
121 | { | |
122 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
123 | char bpts_changed[MAX_BPTS]; | |
124 | char wpts_changed[MAX_WPTS]; | |
125 | /* Cached stopped data address. */ | |
126 | CORE_ADDR stopped_data_address; | |
127 | }; | |
128 | ||
58d6951d DJ |
129 | /* These are in <asm/elf.h> in current kernels. */ |
130 | #define HWCAP_VFP 64 | |
131 | #define HWCAP_IWMMXT 512 | |
132 | #define HWCAP_NEON 4096 | |
133 | #define HWCAP_VFPv3 8192 | |
134 | #define HWCAP_VFPv3D16 16384 | |
135 | ||
0a30fbc4 DJ |
136 | #ifdef HAVE_SYS_REG_H |
137 | #include <sys/reg.h> | |
138 | #endif | |
139 | ||
23ce3b1c | 140 | #define arm_num_regs 26 |
0a30fbc4 | 141 | |
2ec06d2e | 142 | static int arm_regmap[] = { |
0a30fbc4 DJ |
143 | 0, 4, 8, 12, 16, 20, 24, 28, |
144 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
145 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
146 | 64 | |
0a30fbc4 DJ |
147 | }; |
148 | ||
2ec06d2e DJ |
149 | static int |
150 | arm_cannot_store_register (int regno) | |
0a30fbc4 | 151 | { |
2ec06d2e | 152 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
153 | } |
154 | ||
2ec06d2e DJ |
155 | static int |
156 | arm_cannot_fetch_register (int regno) | |
0a30fbc4 | 157 | { |
2ec06d2e | 158 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
159 | } |
160 | ||
fb1e4ffc | 161 | static void |
442ea881 | 162 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc DJ |
163 | { |
164 | int i; | |
165 | ||
89abb039 | 166 | if (regcache->tdesc != tdesc_arm_with_iwmmxt) |
58d6951d DJ |
167 | return; |
168 | ||
fb1e4ffc | 169 | for (i = 0; i < 16; i++) |
442ea881 | 170 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
171 | |
172 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
173 | for (i = 0; i < 6; i++) | |
442ea881 PA |
174 | collect_register (regcache, arm_num_regs + i + 16, |
175 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
176 | } |
177 | ||
178 | static void | |
442ea881 | 179 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc DJ |
180 | { |
181 | int i; | |
182 | ||
89abb039 | 183 | if (regcache->tdesc != tdesc_arm_with_iwmmxt) |
58d6951d DJ |
184 | return; |
185 | ||
fb1e4ffc | 186 | for (i = 0; i < 16; i++) |
442ea881 | 187 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
188 | |
189 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
190 | for (i = 0; i < 6; i++) | |
442ea881 PA |
191 | supply_register (regcache, arm_num_regs + i + 16, |
192 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
193 | } |
194 | ||
58d6951d | 195 | static void |
442ea881 | 196 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 197 | { |
bd9e6534 | 198 | int num; |
58d6951d | 199 | |
89abb039 YQ |
200 | if (regcache->tdesc == tdesc_arm_with_neon |
201 | || regcache->tdesc == tdesc_arm_with_vfpv3) | |
58d6951d | 202 | num = 32; |
89abb039 | 203 | else if (regcache->tdesc == tdesc_arm_with_vfpv2) |
58d6951d | 204 | num = 16; |
89abb039 YQ |
205 | else |
206 | return; | |
58d6951d | 207 | |
bd9e6534 | 208 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
209 | } |
210 | ||
211 | static void | |
442ea881 | 212 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 213 | { |
bd9e6534 | 214 | int num; |
58d6951d | 215 | |
89abb039 YQ |
216 | if (regcache->tdesc == tdesc_arm_with_neon |
217 | || regcache->tdesc == tdesc_arm_with_vfpv3) | |
58d6951d | 218 | num = 32; |
89abb039 | 219 | else if (regcache->tdesc == tdesc_arm_with_vfpv2) |
58d6951d | 220 | num = 16; |
89abb039 YQ |
221 | else |
222 | return; | |
58d6951d | 223 | |
bd9e6534 | 224 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 225 | } |
fb1e4ffc | 226 | |
d677d77d DJ |
227 | extern int debug_threads; |
228 | ||
0d62e5e8 | 229 | static CORE_ADDR |
442ea881 | 230 | arm_get_pc (struct regcache *regcache) |
0d62e5e8 DJ |
231 | { |
232 | unsigned long pc; | |
442ea881 | 233 | collect_register_by_name (regcache, "pc", &pc); |
d677d77d | 234 | if (debug_threads) |
87ce2a04 | 235 | debug_printf ("stop pc is %08lx\n", pc); |
0d62e5e8 DJ |
236 | return pc; |
237 | } | |
238 | ||
239 | static void | |
442ea881 | 240 | arm_set_pc (struct regcache *regcache, CORE_ADDR pc) |
0d62e5e8 DJ |
241 | { |
242 | unsigned long newpc = pc; | |
442ea881 | 243 | supply_register_by_name (regcache, "pc", &newpc); |
0d62e5e8 DJ |
244 | } |
245 | ||
aeb75bf5 | 246 | /* Correct in either endianness. */ |
b0b4b501 | 247 | #define arm_abi_breakpoint 0xef9f0001UL |
0d62e5e8 | 248 | |
9d1fb177 DJ |
249 | /* For new EABI binaries. We recognize it regardless of which ABI |
250 | is used for gdbserver, so single threaded debugging should work | |
251 | OK, but for multi-threaded debugging we only insert the current | |
252 | ABI's breakpoint instruction. For now at least. */ | |
b0b4b501 AT |
253 | #define arm_eabi_breakpoint 0xe7f001f0UL |
254 | ||
255 | #ifndef __ARM_EABI__ | |
256 | static const unsigned long arm_breakpoint = arm_abi_breakpoint; | |
257 | #else | |
258 | static const unsigned long arm_breakpoint = arm_eabi_breakpoint; | |
259 | #endif | |
260 | ||
261 | #define arm_breakpoint_len 4 | |
262 | static const unsigned short thumb_breakpoint = 0xde01; | |
263 | #define thumb_breakpoint_len 2 | |
264 | static const unsigned short thumb2_breakpoint[] = { 0xf7f0, 0xa000 }; | |
265 | #define thumb2_breakpoint_len 4 | |
9d1fb177 | 266 | |
769ef81f AT |
267 | /* Returns 1 if the current instruction set is thumb, 0 otherwise. */ |
268 | ||
0d62e5e8 | 269 | static int |
769ef81f | 270 | arm_is_thumb_mode (void) |
0d62e5e8 | 271 | { |
0bfdf32f | 272 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
aeb75bf5 | 273 | unsigned long cpsr; |
0d62e5e8 | 274 | |
442ea881 | 275 | collect_register_by_name (regcache, "cpsr", &cpsr); |
0d62e5e8 | 276 | |
aeb75bf5 | 277 | if (cpsr & 0x20) |
769ef81f AT |
278 | return 1; |
279 | else | |
280 | return 0; | |
281 | } | |
282 | ||
283 | /* Returns 1 if there is a software breakpoint at location. */ | |
284 | ||
285 | static int | |
286 | arm_breakpoint_at (CORE_ADDR where) | |
287 | { | |
288 | if (arm_is_thumb_mode ()) | |
aeb75bf5 DJ |
289 | { |
290 | /* Thumb mode. */ | |
291 | unsigned short insn; | |
9d1fb177 | 292 | |
aeb75bf5 DJ |
293 | (*the_target->read_memory) (where, (unsigned char *) &insn, 2); |
294 | if (insn == thumb_breakpoint) | |
295 | return 1; | |
177321bd DJ |
296 | |
297 | if (insn == thumb2_breakpoint[0]) | |
298 | { | |
299 | (*the_target->read_memory) (where + 2, (unsigned char *) &insn, 2); | |
300 | if (insn == thumb2_breakpoint[1]) | |
301 | return 1; | |
302 | } | |
aeb75bf5 DJ |
303 | } |
304 | else | |
305 | { | |
306 | /* ARM mode. */ | |
307 | unsigned long insn; | |
308 | ||
309 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); | |
b0b4b501 | 310 | if (insn == arm_abi_breakpoint) |
aeb75bf5 DJ |
311 | return 1; |
312 | ||
313 | if (insn == arm_eabi_breakpoint) | |
314 | return 1; | |
315 | } | |
9d1fb177 | 316 | |
0d62e5e8 DJ |
317 | return 0; |
318 | } | |
319 | ||
3b2fc2ea DJ |
320 | /* We only place breakpoints in empty marker functions, and thread locking |
321 | is outside of the function. So rather than importing software single-step, | |
322 | we can just run until exit. */ | |
323 | static CORE_ADDR | |
442ea881 | 324 | arm_reinsert_addr (void) |
3b2fc2ea | 325 | { |
0bfdf32f | 326 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
3b2fc2ea | 327 | unsigned long pc; |
442ea881 | 328 | collect_register_by_name (regcache, "lr", &pc); |
3b2fc2ea DJ |
329 | return pc; |
330 | } | |
331 | ||
9308fc88 DJ |
332 | /* Fetch the thread-local storage pointer for libthread_db. */ |
333 | ||
334 | ps_err_e | |
335 | ps_get_thread_area (const struct ps_prochandle *ph, | |
1b3f6016 | 336 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
337 | { |
338 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
339 | return PS_ERR; | |
340 | ||
341 | /* IDX is the bias from the thread pointer to the beginning of the | |
342 | thread descriptor. It has to be subtracted due to implementation | |
343 | quirks in libthread_db. */ | |
344 | *base = (void *) ((char *)*base - idx); | |
345 | ||
346 | return PS_OK; | |
347 | } | |
348 | ||
09b4ad9f | 349 | |
71487fd7 UW |
350 | /* Query Hardware Breakpoint information for the target we are attached to |
351 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
352 | static void | |
353 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 354 | { |
71487fd7 | 355 | unsigned int val; |
09b4ad9f | 356 | |
71487fd7 UW |
357 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
358 | return; | |
09b4ad9f | 359 | |
71487fd7 UW |
360 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
361 | if (arm_linux_hwbp_cap.arch == 0) | |
362 | return; | |
09b4ad9f | 363 | |
71487fd7 UW |
364 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
365 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
366 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 367 | |
71487fd7 UW |
368 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
369 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
370 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
371 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
372 | } |
373 | ||
374 | /* How many hardware breakpoints are available? */ | |
375 | static int | |
376 | arm_linux_get_hw_breakpoint_count (void) | |
377 | { | |
71487fd7 | 378 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
379 | } |
380 | ||
381 | /* How many hardware watchpoints are available? */ | |
382 | static int | |
383 | arm_linux_get_hw_watchpoint_count (void) | |
384 | { | |
71487fd7 | 385 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
386 | } |
387 | ||
388 | /* Maximum length of area watched by hardware watchpoint. */ | |
389 | static int | |
390 | arm_linux_get_hw_watchpoint_max_length (void) | |
391 | { | |
71487fd7 | 392 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
393 | } |
394 | ||
395 | /* Initialize an ARM hardware break-/watch-point control register value. | |
396 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
397 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
398 | */ | |
399 | static arm_hwbp_control_t | |
400 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
401 | arm_hwbp_type hwbp_type, | |
402 | int enable) | |
403 | { | |
404 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
405 | gdb_assert (hwbp_type != arm_hwbp_break | |
406 | || ((byte_address_select & 0xfU) != 0)); | |
407 | ||
408 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
409 | } | |
410 | ||
411 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
412 | static int | |
413 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
414 | { | |
415 | return control & 0x1; | |
416 | } | |
417 | ||
418 | /* Is the breakpoint control value CONTROL initialized? */ | |
419 | static int | |
420 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
421 | { | |
422 | return control != 0; | |
423 | } | |
424 | ||
425 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
426 | static arm_hwbp_control_t | |
427 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
428 | { | |
429 | return control & ~0x1; | |
430 | } | |
431 | ||
432 | /* Are two break-/watch-points equal? */ | |
433 | static int | |
434 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
435 | const struct arm_linux_hw_breakpoint *p2) | |
436 | { | |
437 | return p1->address == p2->address && p1->control == p2->control; | |
438 | } | |
439 | ||
802e8e6d PA |
440 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
441 | ||
171de4b8 | 442 | static arm_hwbp_type |
802e8e6d PA |
443 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) |
444 | { | |
445 | switch (raw_type) | |
446 | { | |
447 | case raw_bkpt_type_hw: | |
448 | return arm_hwbp_break; | |
449 | case raw_bkpt_type_write_wp: | |
450 | return arm_hwbp_store; | |
451 | case raw_bkpt_type_read_wp: | |
452 | return arm_hwbp_load; | |
453 | case raw_bkpt_type_access_wp: | |
454 | return arm_hwbp_access; | |
455 | default: | |
456 | gdb_assert_not_reached ("unhandled raw type"); | |
457 | } | |
458 | } | |
459 | ||
09b4ad9f UW |
460 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
461 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
462 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
463 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
464 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 465 | static int |
802e8e6d PA |
466 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
467 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
468 | { |
469 | arm_hwbp_type hwbp_type; | |
470 | unsigned mask; | |
471 | ||
802e8e6d | 472 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
473 | |
474 | if (hwbp_type == arm_hwbp_break) | |
475 | { | |
476 | /* For breakpoints, the length field encodes the mode. */ | |
477 | switch (len) | |
478 | { | |
479 | case 2: /* 16-bit Thumb mode breakpoint */ | |
480 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
481 | mask = 0x3; |
482 | addr &= ~1; | |
09b4ad9f UW |
483 | break; |
484 | case 4: /* 32-bit ARM mode breakpoint */ | |
485 | mask = 0xf; | |
fcf303ab | 486 | addr &= ~3; |
09b4ad9f UW |
487 | break; |
488 | default: | |
489 | /* Unsupported. */ | |
b62e2b27 | 490 | return -2; |
09b4ad9f | 491 | } |
09b4ad9f UW |
492 | } |
493 | else | |
494 | { | |
495 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
496 | CORE_ADDR aligned_addr; | |
497 | ||
498 | /* Can not set watchpoints for zero or negative lengths. */ | |
499 | if (len <= 0) | |
b62e2b27 | 500 | return -2; |
09b4ad9f UW |
501 | /* The current ptrace interface can only handle watchpoints that are a |
502 | power of 2. */ | |
503 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 504 | return -2; |
09b4ad9f UW |
505 | |
506 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
507 | range covered by a watchpoint. */ | |
508 | aligned_addr = addr & ~(max_wp_length - 1); | |
509 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 510 | return -2; |
09b4ad9f UW |
511 | |
512 | mask = (1 << len) - 1; | |
513 | } | |
514 | ||
515 | p->address = (unsigned int) addr; | |
516 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
517 | ||
518 | return hwbp_type != arm_hwbp_break; | |
519 | } | |
520 | ||
521 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
522 | the current process. */ | |
523 | ||
524 | struct update_registers_data | |
525 | { | |
526 | int watch; | |
527 | int i; | |
528 | }; | |
529 | ||
530 | static int | |
531 | update_registers_callback (struct inferior_list_entry *entry, void *arg) | |
532 | { | |
d86d4aaf DE |
533 | struct thread_info *thread = (struct thread_info *) entry; |
534 | struct lwp_info *lwp = get_thread_lwp (thread); | |
09b4ad9f UW |
535 | struct update_registers_data *data = (struct update_registers_data *) arg; |
536 | ||
537 | /* Only update the threads of the current process. */ | |
0bfdf32f | 538 | if (pid_of (thread) == pid_of (current_thread)) |
09b4ad9f UW |
539 | { |
540 | /* The actual update is done later just before resuming the lwp, | |
541 | we just mark that the registers need updating. */ | |
542 | if (data->watch) | |
543 | lwp->arch_private->wpts_changed[data->i] = 1; | |
544 | else | |
545 | lwp->arch_private->bpts_changed[data->i] = 1; | |
546 | ||
547 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
548 | we can update its breakpoint registers. */ | |
549 | if (!lwp->stopped) | |
550 | linux_stop_lwp (lwp); | |
551 | } | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
802e8e6d PA |
556 | static int |
557 | arm_supports_z_point_type (char z_type) | |
558 | { | |
559 | switch (z_type) | |
560 | { | |
abeead09 | 561 | case Z_PACKET_SW_BP: |
802e8e6d PA |
562 | case Z_PACKET_HW_BP: |
563 | case Z_PACKET_WRITE_WP: | |
564 | case Z_PACKET_READ_WP: | |
565 | case Z_PACKET_ACCESS_WP: | |
566 | return 1; | |
567 | default: | |
568 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
569 | return 0; | |
570 | } | |
571 | } | |
572 | ||
09b4ad9f UW |
573 | /* Insert hardware break-/watchpoint. */ |
574 | static int | |
802e8e6d PA |
575 | arm_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
576 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
577 | { |
578 | struct process_info *proc = current_process (); | |
579 | struct arm_linux_hw_breakpoint p, *pts; | |
580 | int watch, i, count; | |
581 | ||
582 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
583 | if (watch < 0) | |
584 | { | |
585 | /* Unsupported. */ | |
b62e2b27 | 586 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
587 | } |
588 | ||
589 | if (watch) | |
590 | { | |
591 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 592 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
593 | } |
594 | else | |
595 | { | |
596 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 597 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
598 | } |
599 | ||
600 | for (i = 0; i < count; i++) | |
601 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
602 | { | |
603 | struct update_registers_data data = { watch, i }; | |
604 | pts[i] = p; | |
d86d4aaf | 605 | find_inferior (&all_threads, update_registers_callback, &data); |
09b4ad9f UW |
606 | return 0; |
607 | } | |
608 | ||
609 | /* We're out of watchpoints. */ | |
610 | return -1; | |
611 | } | |
612 | ||
613 | /* Remove hardware break-/watchpoint. */ | |
614 | static int | |
802e8e6d PA |
615 | arm_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
616 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
617 | { |
618 | struct process_info *proc = current_process (); | |
619 | struct arm_linux_hw_breakpoint p, *pts; | |
620 | int watch, i, count; | |
621 | ||
622 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
623 | if (watch < 0) | |
624 | { | |
625 | /* Unsupported. */ | |
626 | return -1; | |
627 | } | |
628 | ||
629 | if (watch) | |
630 | { | |
631 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 632 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
633 | } |
634 | else | |
635 | { | |
636 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 637 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
638 | } |
639 | ||
640 | for (i = 0; i < count; i++) | |
641 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
642 | { | |
643 | struct update_registers_data data = { watch, i }; | |
644 | pts[i].control = arm_hwbp_control_disable (pts[i].control); | |
d86d4aaf | 645 | find_inferior (&all_threads, update_registers_callback, &data); |
09b4ad9f UW |
646 | return 0; |
647 | } | |
648 | ||
649 | /* No watchpoint matched. */ | |
650 | return -1; | |
651 | } | |
652 | ||
653 | /* Return whether current thread is stopped due to a watchpoint. */ | |
654 | static int | |
655 | arm_stopped_by_watchpoint (void) | |
656 | { | |
0bfdf32f | 657 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 658 | siginfo_t siginfo; |
09b4ad9f UW |
659 | |
660 | /* We must be able to set hardware watchpoints. */ | |
661 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
662 | return 0; | |
663 | ||
664 | /* Retrieve siginfo. */ | |
665 | errno = 0; | |
0bfdf32f | 666 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f UW |
667 | if (errno != 0) |
668 | return 0; | |
669 | ||
670 | /* This must be a hardware breakpoint. */ | |
671 | if (siginfo.si_signo != SIGTRAP | |
672 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
673 | return 0; | |
674 | ||
675 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
676 | a watchpoint. */ | |
677 | if (siginfo.si_errno >= 0) | |
678 | return 0; | |
679 | ||
680 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
681 | lwp->arch_private->stopped_data_address | |
682 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
683 | ||
684 | return 1; | |
685 | } | |
686 | ||
687 | /* Return data address that triggered watchpoint. Called only if | |
688 | arm_stopped_by_watchpoint returned true. */ | |
689 | static CORE_ADDR | |
690 | arm_stopped_data_address (void) | |
691 | { | |
0bfdf32f | 692 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
693 | return lwp->arch_private->stopped_data_address; |
694 | } | |
695 | ||
696 | /* Called when a new process is created. */ | |
697 | static struct arch_process_info * | |
698 | arm_new_process (void) | |
699 | { | |
8d749320 | 700 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
701 | return info; |
702 | } | |
703 | ||
704 | /* Called when a new thread is detected. */ | |
34c703da GB |
705 | static void |
706 | arm_new_thread (struct lwp_info *lwp) | |
09b4ad9f | 707 | { |
8d749320 | 708 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
709 | int i; |
710 | ||
711 | for (i = 0; i < MAX_BPTS; i++) | |
712 | info->bpts_changed[i] = 1; | |
713 | for (i = 0; i < MAX_WPTS; i++) | |
714 | info->wpts_changed[i] = 1; | |
715 | ||
34c703da | 716 | lwp->arch_private = info; |
09b4ad9f UW |
717 | } |
718 | ||
3a8a0396 DB |
719 | static void |
720 | arm_new_fork (struct process_info *parent, struct process_info *child) | |
721 | { | |
69291610 HW |
722 | struct arch_process_info *parent_proc_info; |
723 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
724 | struct lwp_info *child_lwp; |
725 | struct arch_lwp_info *child_lwp_info; | |
726 | int i; | |
727 | ||
728 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
729 | gdb_assert (parent->priv != NULL |
730 | && parent->priv->arch_private != NULL); | |
731 | gdb_assert (child->priv != NULL | |
732 | && child->priv->arch_private != NULL); | |
3a8a0396 | 733 | |
69291610 HW |
734 | parent_proc_info = parent->priv->arch_private; |
735 | child_proc_info = child->priv->arch_private; | |
736 | ||
3a8a0396 DB |
737 | /* Linux kernel before 2.6.33 commit |
738 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
739 | will inherit hardware debug registers from parent | |
740 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
741 | zeroed debug registers. | |
742 | ||
743 | GDB core assumes the child inherits the watchpoints/hw | |
744 | breakpoints of the parent, and will remove them all from the | |
745 | forked off process. Copy the debug registers mirrors into the | |
746 | new process so that all breakpoints and watchpoints can be | |
747 | removed together. The debug registers mirror will become zeroed | |
748 | in the end before detaching the forked off process, thus making | |
749 | this compatible with older Linux kernels too. */ | |
750 | ||
751 | *child_proc_info = *parent_proc_info; | |
752 | ||
753 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
754 | make sure that the registers will be updated. */ | |
755 | child_lwp = find_lwp_pid (ptid_of (child)); | |
756 | child_lwp_info = child_lwp->arch_private; | |
757 | for (i = 0; i < MAX_BPTS; i++) | |
758 | child_lwp_info->bpts_changed[i] = 1; | |
759 | for (i = 0; i < MAX_WPTS; i++) | |
760 | child_lwp_info->wpts_changed[i] = 1; | |
761 | } | |
762 | ||
09b4ad9f UW |
763 | /* Called when resuming a thread. |
764 | If the debug regs have changed, update the thread's copies. */ | |
765 | static void | |
766 | arm_prepare_to_resume (struct lwp_info *lwp) | |
767 | { | |
d86d4aaf DE |
768 | struct thread_info *thread = get_lwp_thread (lwp); |
769 | int pid = lwpid_of (thread); | |
770 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 771 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
772 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
773 | int i; | |
774 | ||
775 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
776 | if (lwp_info->bpts_changed[i]) | |
777 | { | |
778 | errno = 0; | |
779 | ||
780 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 781 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 782 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 783 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 784 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
785 | |
786 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 787 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 788 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 789 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 790 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
791 | |
792 | lwp_info->bpts_changed[i] = 0; | |
793 | } | |
794 | ||
795 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
796 | if (lwp_info->wpts_changed[i]) | |
797 | { | |
798 | errno = 0; | |
799 | ||
800 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 801 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 802 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 803 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 804 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
805 | |
806 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 807 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 808 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 809 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 810 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
811 | |
812 | lwp_info->wpts_changed[i] = 0; | |
813 | } | |
814 | } | |
815 | ||
816 | ||
58d6951d DJ |
817 | static int |
818 | arm_get_hwcap (unsigned long *valp) | |
819 | { | |
04248ead | 820 | unsigned char *data = (unsigned char *) alloca (8); |
58d6951d DJ |
821 | int offset = 0; |
822 | ||
823 | while ((*the_target->read_auxv) (offset, data, 8) == 8) | |
824 | { | |
825 | unsigned int *data_p = (unsigned int *)data; | |
826 | if (data_p[0] == AT_HWCAP) | |
827 | { | |
828 | *valp = data_p[1]; | |
829 | return 1; | |
830 | } | |
831 | ||
832 | offset += 8; | |
833 | } | |
834 | ||
835 | *valp = 0; | |
836 | return 0; | |
837 | } | |
838 | ||
3aee8918 PA |
839 | static const struct target_desc * |
840 | arm_read_description (void) | |
58d6951d | 841 | { |
0bfdf32f | 842 | int pid = lwpid_of (current_thread); |
e8b41681 | 843 | unsigned long arm_hwcap = 0; |
71487fd7 UW |
844 | |
845 | /* Query hardware watchpoint/breakpoint capabilities. */ | |
846 | arm_linux_init_hwbp_cap (pid); | |
847 | ||
58d6951d | 848 | if (arm_get_hwcap (&arm_hwcap) == 0) |
3aee8918 | 849 | return tdesc_arm; |
58d6951d DJ |
850 | |
851 | if (arm_hwcap & HWCAP_IWMMXT) | |
3aee8918 | 852 | return tdesc_arm_with_iwmmxt; |
58d6951d DJ |
853 | |
854 | if (arm_hwcap & HWCAP_VFP) | |
855 | { | |
3aee8918 | 856 | const struct target_desc *result; |
58d6951d DJ |
857 | char *buf; |
858 | ||
859 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
860 | it with VFP. */ | |
861 | if (arm_hwcap & HWCAP_NEON) | |
3aee8918 | 862 | result = tdesc_arm_with_neon; |
58d6951d | 863 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
3aee8918 | 864 | result = tdesc_arm_with_vfpv3; |
58d6951d | 865 | else |
3aee8918 | 866 | result = tdesc_arm_with_vfpv2; |
58d6951d DJ |
867 | |
868 | /* Now make sure that the kernel supports reading these | |
869 | registers. Support was added in 2.6.30. */ | |
58d6951d | 870 | errno = 0; |
04248ead | 871 | buf = (char *) xmalloc (32 * 8 + 4); |
58d6951d DJ |
872 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
873 | && errno == EIO) | |
e8b41681 YQ |
874 | result = tdesc_arm; |
875 | ||
58d6951d DJ |
876 | free (buf); |
877 | ||
3aee8918 | 878 | return result; |
58d6951d DJ |
879 | } |
880 | ||
881 | /* The default configuration uses legacy FPA registers, probably | |
882 | simulated. */ | |
3aee8918 | 883 | return tdesc_arm; |
58d6951d DJ |
884 | } |
885 | ||
3aee8918 PA |
886 | static void |
887 | arm_arch_setup (void) | |
888 | { | |
bd9e6534 YQ |
889 | int tid = lwpid_of (current_thread); |
890 | int gpregs[18]; | |
891 | struct iovec iov; | |
892 | ||
3aee8918 | 893 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
894 | |
895 | iov.iov_base = gpregs; | |
896 | iov.iov_len = sizeof (gpregs); | |
897 | ||
898 | /* Check if PTRACE_GETREGSET works. */ | |
899 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
900 | have_ptrace_getregset = 1; | |
901 | else | |
902 | have_ptrace_getregset = 0; | |
3aee8918 PA |
903 | } |
904 | ||
bd9e6534 YQ |
905 | /* Register sets without using PTRACE_GETREGSET. */ |
906 | ||
3aee8918 | 907 | static struct regset_info arm_regsets[] = { |
1570b33e | 908 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4, |
fb1e4ffc DJ |
909 | GENERAL_REGS, |
910 | arm_fill_gregset, arm_store_gregset }, | |
1570b33e | 911 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4, |
fb1e4ffc DJ |
912 | EXTENDED_REGS, |
913 | arm_fill_wmmxregset, arm_store_wmmxregset }, | |
1570b33e | 914 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4, |
58d6951d DJ |
915 | EXTENDED_REGS, |
916 | arm_fill_vfpregset, arm_store_vfpregset }, | |
50bc912a | 917 | NULL_REGSET |
fb1e4ffc DJ |
918 | }; |
919 | ||
3aee8918 PA |
920 | static struct regsets_info arm_regsets_info = |
921 | { | |
922 | arm_regsets, /* regsets */ | |
923 | 0, /* num_regsets */ | |
924 | NULL, /* disabled_regsets */ | |
925 | }; | |
926 | ||
927 | static struct usrregs_info arm_usrregs_info = | |
928 | { | |
929 | arm_num_regs, | |
930 | arm_regmap, | |
931 | }; | |
932 | ||
bd9e6534 | 933 | static struct regs_info regs_info_arm = |
3aee8918 PA |
934 | { |
935 | NULL, /* regset_bitmap */ | |
936 | &arm_usrregs_info, | |
937 | &arm_regsets_info | |
938 | }; | |
939 | ||
940 | static const struct regs_info * | |
941 | arm_regs_info (void) | |
942 | { | |
bd9e6534 YQ |
943 | const struct target_desc *tdesc = current_process ()->tdesc; |
944 | ||
945 | if (have_ptrace_getregset == 1 | |
946 | && (tdesc == tdesc_arm_with_neon || tdesc == tdesc_arm_with_vfpv3)) | |
947 | return ®s_info_aarch32; | |
948 | else | |
949 | return ®s_info_arm; | |
3aee8918 PA |
950 | } |
951 | ||
8689682c AT |
952 | /* Implementation of linux_target_ops method "breakpoint_kind_from_pc". |
953 | ||
954 | Determine the type and size of breakpoint to insert at PCPTR. Uses the | |
955 | program counter value to determine whether a 16-bit or 32-bit breakpoint | |
956 | should be used. It returns the breakpoint's kind, and adjusts the program | |
957 | counter (if necessary) to point to the actual memory location where the | |
958 | breakpoint should be inserted. */ | |
959 | ||
960 | static int | |
961 | arm_breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
962 | { | |
963 | if (IS_THUMB_ADDR (*pcptr)) | |
964 | { | |
965 | gdb_byte buf[2]; | |
966 | ||
967 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
968 | ||
969 | /* Check whether we are replacing a thumb2 32-bit instruction. */ | |
970 | if ((*the_target->read_memory) (*pcptr, buf, 2) == 0) | |
971 | { | |
972 | unsigned short inst1 = 0; | |
973 | ||
974 | (*the_target->read_memory) (*pcptr, (gdb_byte *) &inst1, 2); | |
975 | if (thumb_insn_size (inst1) == 4) | |
976 | return ARM_BP_KIND_THUMB2; | |
977 | } | |
978 | return ARM_BP_KIND_THUMB; | |
979 | } | |
980 | else | |
981 | return ARM_BP_KIND_ARM; | |
982 | } | |
983 | ||
984 | /* Implementation of the linux_target_ops method "sw_breakpoint_from_kind". */ | |
aeb75bf5 | 985 | |
dd373349 AT |
986 | static const gdb_byte * |
987 | arm_sw_breakpoint_from_kind (int kind , int *size) | |
988 | { | |
989 | *size = arm_breakpoint_len; | |
aeb75bf5 DJ |
990 | /* Define an ARM-mode breakpoint; we only set breakpoints in the C |
991 | library, which is most likely to be ARM. If the kernel supports | |
992 | clone events, we will never insert a breakpoint, so even a Thumb | |
993 | C library will work; so will mixing EABI/non-EABI gdbserver and | |
994 | application. */ | |
8689682c AT |
995 | switch (kind) |
996 | { | |
997 | case ARM_BP_KIND_THUMB: | |
998 | *size = thumb_breakpoint_len; | |
999 | return (gdb_byte *) &thumb_breakpoint; | |
1000 | case ARM_BP_KIND_THUMB2: | |
1001 | *size = thumb2_breakpoint_len; | |
1002 | return (gdb_byte *) &thumb2_breakpoint; | |
1003 | case ARM_BP_KIND_ARM: | |
1004 | *size = arm_breakpoint_len; | |
8689682c | 1005 | return (const gdb_byte *) &arm_breakpoint; |
8689682c AT |
1006 | default: |
1007 | return NULL; | |
1008 | } | |
1009 | return NULL; | |
dd373349 AT |
1010 | } |
1011 | ||
769ef81f AT |
1012 | /* Implementation of the linux_target_ops method |
1013 | "breakpoint_kind_from_current_state". */ | |
1014 | ||
1015 | static int | |
1016 | arm_breakpoint_kind_from_current_state (CORE_ADDR *pcptr) | |
1017 | { | |
1018 | if (arm_is_thumb_mode ()) | |
1019 | { | |
1020 | *pcptr = MAKE_THUMB_ADDR (*pcptr); | |
1021 | return arm_breakpoint_kind_from_pc (pcptr); | |
1022 | } | |
1023 | else | |
1024 | { | |
1025 | return arm_breakpoint_kind_from_pc (pcptr); | |
1026 | } | |
1027 | } | |
1028 | ||
dd373349 AT |
1029 | struct linux_target_ops the_low_target = { |
1030 | arm_arch_setup, | |
1031 | arm_regs_info, | |
1032 | arm_cannot_fetch_register, | |
1033 | arm_cannot_store_register, | |
1034 | NULL, /* fetch_register */ | |
1035 | arm_get_pc, | |
1036 | arm_set_pc, | |
8689682c | 1037 | arm_breakpoint_kind_from_pc, |
dd373349 | 1038 | arm_sw_breakpoint_from_kind, |
3b2fc2ea | 1039 | arm_reinsert_addr, |
0d62e5e8 DJ |
1040 | 0, |
1041 | arm_breakpoint_at, | |
802e8e6d | 1042 | arm_supports_z_point_type, |
09b4ad9f UW |
1043 | arm_insert_point, |
1044 | arm_remove_point, | |
1045 | arm_stopped_by_watchpoint, | |
1046 | arm_stopped_data_address, | |
1047 | NULL, /* collect_ptrace_register */ | |
1048 | NULL, /* supply_ptrace_register */ | |
1049 | NULL, /* siginfo_fixup */ | |
1050 | arm_new_process, | |
1051 | arm_new_thread, | |
3a8a0396 | 1052 | arm_new_fork, |
09b4ad9f | 1053 | arm_prepare_to_resume, |
769ef81f AT |
1054 | NULL, /* process_qsupported */ |
1055 | NULL, /* supports_tracepoints */ | |
1056 | NULL, /* get_thread_area */ | |
1057 | NULL, /* install_fast_tracepoint_jump_pad */ | |
1058 | NULL, /* emit_ops */ | |
1059 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
1060 | NULL, /* supports_range_stepping */ | |
1061 | arm_breakpoint_kind_from_current_state | |
2ec06d2e | 1062 | }; |
3aee8918 PA |
1063 | |
1064 | void | |
1065 | initialize_low_arch (void) | |
1066 | { | |
1067 | /* Initialize the Linux target descriptions. */ | |
1068 | init_registers_arm (); | |
1069 | init_registers_arm_with_iwmmxt (); | |
1070 | init_registers_arm_with_vfpv2 (); | |
1071 | init_registers_arm_with_vfpv3 (); | |
bd9e6534 YQ |
1072 | |
1073 | initialize_low_arch_aarch32 (); | |
3aee8918 PA |
1074 | |
1075 | initialize_regsets_info (&arm_regsets_info); | |
1076 | } |