New gdbserver option --debug-format=timestamp.
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-arm-low.c
CommitLineData
0a30fbc4 1/* GNU/Linux/ARM specific low level interface, for the remote server for GDB.
ecd75fc8 2 Copyright (C) 1995-2014 Free Software Foundation, Inc.
0a30fbc4
DJ
3
4 This file is part of GDB.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
a9762ec7 8 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
a9762ec7 17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ
18
19#include "server.h"
58caa3dc 20#include "linux-low.h"
0a30fbc4 21
3743bb4f
DE
22/* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h.
23 On Bionic elf.h and linux/elf.h have conflicting definitions. */
24#ifndef ELFMAG0
58d6951d 25#include <elf.h>
3743bb4f 26#endif
9308fc88 27#include <sys/ptrace.h>
09b4ad9f 28#include <signal.h>
9308fc88 29
58d6951d 30/* Defined in auto-generated files. */
d05b4ac3 31void init_registers_arm (void);
3aee8918
PA
32extern const struct target_desc *tdesc_arm;
33
d05b4ac3 34void init_registers_arm_with_iwmmxt (void);
3aee8918
PA
35extern const struct target_desc *tdesc_arm_with_iwmmxt;
36
58d6951d 37void init_registers_arm_with_vfpv2 (void);
3aee8918
PA
38extern const struct target_desc *tdesc_arm_with_vfpv2;
39
58d6951d 40void init_registers_arm_with_vfpv3 (void);
3aee8918
PA
41extern const struct target_desc *tdesc_arm_with_vfpv3;
42
58d6951d 43void init_registers_arm_with_neon (void);
3aee8918 44extern const struct target_desc *tdesc_arm_with_neon;
d05b4ac3 45
9308fc88
DJ
46#ifndef PTRACE_GET_THREAD_AREA
47#define PTRACE_GET_THREAD_AREA 22
48#endif
49
fb1e4ffc
DJ
50#ifndef PTRACE_GETWMMXREGS
51# define PTRACE_GETWMMXREGS 18
52# define PTRACE_SETWMMXREGS 19
53#endif
54
58d6951d
DJ
55#ifndef PTRACE_GETVFPREGS
56# define PTRACE_GETVFPREGS 27
57# define PTRACE_SETVFPREGS 28
58#endif
59
09b4ad9f
UW
60#ifndef PTRACE_GETHBPREGS
61#define PTRACE_GETHBPREGS 29
62#define PTRACE_SETHBPREGS 30
63#endif
64
65/* Information describing the hardware breakpoint capabilities. */
71487fd7 66static struct
09b4ad9f
UW
67{
68 unsigned char arch;
69 unsigned char max_wp_length;
70 unsigned char wp_count;
71 unsigned char bp_count;
71487fd7 72} arm_linux_hwbp_cap;
09b4ad9f
UW
73
74/* Enum describing the different types of ARM hardware break-/watch-points. */
75typedef enum
76{
77 arm_hwbp_break = 0,
78 arm_hwbp_load = 1,
79 arm_hwbp_store = 2,
80 arm_hwbp_access = 3
81} arm_hwbp_type;
82
83/* Type describing an ARM Hardware Breakpoint Control register value. */
84typedef unsigned int arm_hwbp_control_t;
85
86/* Structure used to keep track of hardware break-/watch-points. */
87struct arm_linux_hw_breakpoint
88{
89 /* Address to break on, or being watched. */
90 unsigned int address;
91 /* Control register for break-/watch- point. */
92 arm_hwbp_control_t control;
93};
94
95/* Since we cannot dynamically allocate subfields of arch_process_info,
96 assume a maximum number of supported break-/watchpoints. */
97#define MAX_BPTS 32
98#define MAX_WPTS 32
99
100/* Per-process arch-specific data we want to keep. */
101struct arch_process_info
102{
103 /* Hardware breakpoints for this process. */
104 struct arm_linux_hw_breakpoint bpts[MAX_BPTS];
105 /* Hardware watchpoints for this process. */
106 struct arm_linux_hw_breakpoint wpts[MAX_WPTS];
107};
108
109/* Per-thread arch-specific data we want to keep. */
110struct arch_lwp_info
111{
112 /* Non-zero if our copy differs from what's recorded in the thread. */
113 char bpts_changed[MAX_BPTS];
114 char wpts_changed[MAX_WPTS];
115 /* Cached stopped data address. */
116 CORE_ADDR stopped_data_address;
117};
118
58d6951d
DJ
119static unsigned long arm_hwcap;
120
121/* These are in <asm/elf.h> in current kernels. */
122#define HWCAP_VFP 64
123#define HWCAP_IWMMXT 512
124#define HWCAP_NEON 4096
125#define HWCAP_VFPv3 8192
126#define HWCAP_VFPv3D16 16384
127
0a30fbc4
DJ
128#ifdef HAVE_SYS_REG_H
129#include <sys/reg.h>
130#endif
131
23ce3b1c 132#define arm_num_regs 26
0a30fbc4 133
2ec06d2e 134static int arm_regmap[] = {
0a30fbc4
DJ
135 0, 4, 8, 12, 16, 20, 24, 28,
136 32, 36, 40, 44, 48, 52, 56, 60,
23ce3b1c
DJ
137 -1, -1, -1, -1, -1, -1, -1, -1, -1,
138 64
0a30fbc4
DJ
139};
140
2ec06d2e
DJ
141static int
142arm_cannot_store_register (int regno)
0a30fbc4 143{
2ec06d2e 144 return (regno >= arm_num_regs);
0a30fbc4
DJ
145}
146
2ec06d2e
DJ
147static int
148arm_cannot_fetch_register (int regno)
0a30fbc4 149{
2ec06d2e 150 return (regno >= arm_num_regs);
0a30fbc4
DJ
151}
152
fb1e4ffc 153static void
442ea881 154arm_fill_gregset (struct regcache *regcache, void *buf)
fb1e4ffc
DJ
155{
156 int i;
157
158 for (i = 0; i < arm_num_regs; i++)
159 if (arm_regmap[i] != -1)
442ea881 160 collect_register (regcache, i, ((char *) buf) + arm_regmap[i]);
fb1e4ffc
DJ
161}
162
163static void
442ea881 164arm_store_gregset (struct regcache *regcache, const void *buf)
fb1e4ffc
DJ
165{
166 int i;
167 char zerobuf[8];
168
169 memset (zerobuf, 0, 8);
170 for (i = 0; i < arm_num_regs; i++)
171 if (arm_regmap[i] != -1)
442ea881 172 supply_register (regcache, i, ((char *) buf) + arm_regmap[i]);
fb1e4ffc 173 else
442ea881 174 supply_register (regcache, i, zerobuf);
fb1e4ffc
DJ
175}
176
fb1e4ffc 177static void
442ea881 178arm_fill_wmmxregset (struct regcache *regcache, void *buf)
fb1e4ffc
DJ
179{
180 int i;
181
58d6951d
DJ
182 if (!(arm_hwcap & HWCAP_IWMMXT))
183 return;
184
fb1e4ffc 185 for (i = 0; i < 16; i++)
442ea881 186 collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8);
fb1e4ffc
DJ
187
188 /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */
189 for (i = 0; i < 6; i++)
442ea881
PA
190 collect_register (regcache, arm_num_regs + i + 16,
191 (char *) buf + 16 * 8 + i * 4);
fb1e4ffc
DJ
192}
193
194static void
442ea881 195arm_store_wmmxregset (struct regcache *regcache, const void *buf)
fb1e4ffc
DJ
196{
197 int i;
198
58d6951d
DJ
199 if (!(arm_hwcap & HWCAP_IWMMXT))
200 return;
201
fb1e4ffc 202 for (i = 0; i < 16; i++)
442ea881 203 supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8);
fb1e4ffc
DJ
204
205 /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */
206 for (i = 0; i < 6; i++)
442ea881
PA
207 supply_register (regcache, arm_num_regs + i + 16,
208 (char *) buf + 16 * 8 + i * 4);
fb1e4ffc
DJ
209}
210
58d6951d 211static void
442ea881 212arm_fill_vfpregset (struct regcache *regcache, void *buf)
58d6951d
DJ
213{
214 int i, num, base;
215
216 if (!(arm_hwcap & HWCAP_VFP))
217 return;
218
219 if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
220 num = 32;
221 else
222 num = 16;
223
3aee8918 224 base = find_regno (regcache->tdesc, "d0");
58d6951d 225 for (i = 0; i < num; i++)
442ea881 226 collect_register (regcache, base + i, (char *) buf + i * 8);
58d6951d 227
442ea881 228 collect_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8);
58d6951d
DJ
229}
230
231static void
442ea881 232arm_store_vfpregset (struct regcache *regcache, const void *buf)
58d6951d
DJ
233{
234 int i, num, base;
235
236 if (!(arm_hwcap & HWCAP_VFP))
237 return;
238
239 if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
240 num = 32;
241 else
242 num = 16;
243
3aee8918 244 base = find_regno (regcache->tdesc, "d0");
58d6951d 245 for (i = 0; i < num; i++)
442ea881 246 supply_register (regcache, base + i, (char *) buf + i * 8);
58d6951d 247
442ea881 248 supply_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8);
58d6951d 249}
fb1e4ffc 250
d677d77d
DJ
251extern int debug_threads;
252
0d62e5e8 253static CORE_ADDR
442ea881 254arm_get_pc (struct regcache *regcache)
0d62e5e8
DJ
255{
256 unsigned long pc;
442ea881 257 collect_register_by_name (regcache, "pc", &pc);
d677d77d 258 if (debug_threads)
87ce2a04 259 debug_printf ("stop pc is %08lx\n", pc);
0d62e5e8
DJ
260 return pc;
261}
262
263static void
442ea881 264arm_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8
DJ
265{
266 unsigned long newpc = pc;
442ea881 267 supply_register_by_name (regcache, "pc", &newpc);
0d62e5e8
DJ
268}
269
aeb75bf5 270/* Correct in either endianness. */
0d62e5e8
DJ
271static const unsigned long arm_breakpoint = 0xef9f0001;
272#define arm_breakpoint_len 4
aeb75bf5 273static const unsigned short thumb_breakpoint = 0xde01;
177321bd 274static const unsigned short thumb2_breakpoint[] = { 0xf7f0, 0xa000 };
0d62e5e8 275
9d1fb177
DJ
276/* For new EABI binaries. We recognize it regardless of which ABI
277 is used for gdbserver, so single threaded debugging should work
278 OK, but for multi-threaded debugging we only insert the current
279 ABI's breakpoint instruction. For now at least. */
280static const unsigned long arm_eabi_breakpoint = 0xe7f001f0;
281
0d62e5e8
DJ
282static int
283arm_breakpoint_at (CORE_ADDR where)
284{
442ea881 285 struct regcache *regcache = get_thread_regcache (current_inferior, 1);
aeb75bf5 286 unsigned long cpsr;
0d62e5e8 287
442ea881 288 collect_register_by_name (regcache, "cpsr", &cpsr);
0d62e5e8 289
aeb75bf5
DJ
290 if (cpsr & 0x20)
291 {
292 /* Thumb mode. */
293 unsigned short insn;
9d1fb177 294
aeb75bf5
DJ
295 (*the_target->read_memory) (where, (unsigned char *) &insn, 2);
296 if (insn == thumb_breakpoint)
297 return 1;
177321bd
DJ
298
299 if (insn == thumb2_breakpoint[0])
300 {
301 (*the_target->read_memory) (where + 2, (unsigned char *) &insn, 2);
302 if (insn == thumb2_breakpoint[1])
303 return 1;
304 }
aeb75bf5
DJ
305 }
306 else
307 {
308 /* ARM mode. */
309 unsigned long insn;
310
311 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
312 if (insn == arm_breakpoint)
313 return 1;
314
315 if (insn == arm_eabi_breakpoint)
316 return 1;
317 }
9d1fb177 318
0d62e5e8
DJ
319 return 0;
320}
321
3b2fc2ea
DJ
322/* We only place breakpoints in empty marker functions, and thread locking
323 is outside of the function. So rather than importing software single-step,
324 we can just run until exit. */
325static CORE_ADDR
442ea881 326arm_reinsert_addr (void)
3b2fc2ea 327{
442ea881 328 struct regcache *regcache = get_thread_regcache (current_inferior, 1);
3b2fc2ea 329 unsigned long pc;
442ea881 330 collect_register_by_name (regcache, "lr", &pc);
3b2fc2ea
DJ
331 return pc;
332}
333
9308fc88
DJ
334/* Fetch the thread-local storage pointer for libthread_db. */
335
336ps_err_e
337ps_get_thread_area (const struct ps_prochandle *ph,
1b3f6016 338 lwpid_t lwpid, int idx, void **base)
9308fc88
DJ
339{
340 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
341 return PS_ERR;
342
343 /* IDX is the bias from the thread pointer to the beginning of the
344 thread descriptor. It has to be subtracted due to implementation
345 quirks in libthread_db. */
346 *base = (void *) ((char *)*base - idx);
347
348 return PS_OK;
349}
350
09b4ad9f 351
71487fd7
UW
352/* Query Hardware Breakpoint information for the target we are attached to
353 (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */
354static void
355arm_linux_init_hwbp_cap (int pid)
09b4ad9f 356{
71487fd7 357 unsigned int val;
09b4ad9f 358
71487fd7
UW
359 if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0)
360 return;
09b4ad9f 361
71487fd7
UW
362 arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff);
363 if (arm_linux_hwbp_cap.arch == 0)
364 return;
09b4ad9f 365
71487fd7
UW
366 arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff);
367 arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff);
368 arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff);
09b4ad9f 369
71487fd7
UW
370 if (arm_linux_hwbp_cap.wp_count > MAX_WPTS)
371 internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints");
372 if (arm_linux_hwbp_cap.bp_count > MAX_BPTS)
373 internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints");
09b4ad9f
UW
374}
375
376/* How many hardware breakpoints are available? */
377static int
378arm_linux_get_hw_breakpoint_count (void)
379{
71487fd7 380 return arm_linux_hwbp_cap.bp_count;
09b4ad9f
UW
381}
382
383/* How many hardware watchpoints are available? */
384static int
385arm_linux_get_hw_watchpoint_count (void)
386{
71487fd7 387 return arm_linux_hwbp_cap.wp_count;
09b4ad9f
UW
388}
389
390/* Maximum length of area watched by hardware watchpoint. */
391static int
392arm_linux_get_hw_watchpoint_max_length (void)
393{
71487fd7 394 return arm_linux_hwbp_cap.max_wp_length;
09b4ad9f
UW
395}
396
397/* Initialize an ARM hardware break-/watch-point control register value.
398 BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the
399 type of break-/watch-point; ENABLE indicates whether the point is enabled.
400 */
401static arm_hwbp_control_t
402arm_hwbp_control_initialize (unsigned byte_address_select,
403 arm_hwbp_type hwbp_type,
404 int enable)
405{
406 gdb_assert ((byte_address_select & ~0xffU) == 0);
407 gdb_assert (hwbp_type != arm_hwbp_break
408 || ((byte_address_select & 0xfU) != 0));
409
410 return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable;
411}
412
413/* Does the breakpoint control value CONTROL have the enable bit set? */
414static int
415arm_hwbp_control_is_enabled (arm_hwbp_control_t control)
416{
417 return control & 0x1;
418}
419
420/* Is the breakpoint control value CONTROL initialized? */
421static int
422arm_hwbp_control_is_initialized (arm_hwbp_control_t control)
423{
424 return control != 0;
425}
426
427/* Change a breakpoint control word so that it is in the disabled state. */
428static arm_hwbp_control_t
429arm_hwbp_control_disable (arm_hwbp_control_t control)
430{
431 return control & ~0x1;
432}
433
434/* Are two break-/watch-points equal? */
435static int
436arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1,
437 const struct arm_linux_hw_breakpoint *p2)
438{
439 return p1->address == p2->address && p1->control == p2->control;
440}
441
442/* Initialize the hardware breakpoint structure P for a breakpoint or
443 watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE.
b62e2b27
UW
444 Returns -1 if TYPE is unsupported, or -2 if the particular combination
445 of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE
446 represents a breakpoint and 1 if type represents a watchpoint. */
09b4ad9f
UW
447static int
448arm_linux_hw_point_initialize (char type, CORE_ADDR addr, int len,
449 struct arm_linux_hw_breakpoint *p)
450{
451 arm_hwbp_type hwbp_type;
452 unsigned mask;
453
454 /* Breakpoint/watchpoint types (GDB terminology):
455 0 = memory breakpoint for instructions
456 (not supported; done via memory write instead)
457 1 = hardware breakpoint for instructions (supported)
458 2 = write watchpoint (supported)
459 3 = read watchpoint (supported)
460 4 = access watchpoint (supported). */
461 switch (type)
462 {
463 case '1':
464 hwbp_type = arm_hwbp_break;
465 break;
466 case '2':
467 hwbp_type = arm_hwbp_store;
468 break;
469 case '3':
470 hwbp_type = arm_hwbp_load;
471 break;
472 case '4':
473 hwbp_type = arm_hwbp_access;
474 break;
475 default:
476 /* Unsupported. */
477 return -1;
478 }
479
480 if (hwbp_type == arm_hwbp_break)
481 {
482 /* For breakpoints, the length field encodes the mode. */
483 switch (len)
484 {
485 case 2: /* 16-bit Thumb mode breakpoint */
486 case 3: /* 32-bit Thumb mode breakpoint */
fcf303ab
UW
487 mask = 0x3;
488 addr &= ~1;
09b4ad9f
UW
489 break;
490 case 4: /* 32-bit ARM mode breakpoint */
491 mask = 0xf;
fcf303ab 492 addr &= ~3;
09b4ad9f
UW
493 break;
494 default:
495 /* Unsupported. */
b62e2b27 496 return -2;
09b4ad9f 497 }
09b4ad9f
UW
498 }
499 else
500 {
501 CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length ();
502 CORE_ADDR aligned_addr;
503
504 /* Can not set watchpoints for zero or negative lengths. */
505 if (len <= 0)
b62e2b27 506 return -2;
09b4ad9f
UW
507 /* The current ptrace interface can only handle watchpoints that are a
508 power of 2. */
509 if ((len & (len - 1)) != 0)
b62e2b27 510 return -2;
09b4ad9f
UW
511
512 /* Test that the range [ADDR, ADDR + LEN) fits into the largest address
513 range covered by a watchpoint. */
514 aligned_addr = addr & ~(max_wp_length - 1);
515 if (aligned_addr + max_wp_length < addr + len)
b62e2b27 516 return -2;
09b4ad9f
UW
517
518 mask = (1 << len) - 1;
519 }
520
521 p->address = (unsigned int) addr;
522 p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1);
523
524 return hwbp_type != arm_hwbp_break;
525}
526
527/* Callback to mark a watch-/breakpoint to be updated in all threads of
528 the current process. */
529
530struct update_registers_data
531{
532 int watch;
533 int i;
534};
535
536static int
537update_registers_callback (struct inferior_list_entry *entry, void *arg)
538{
539 struct lwp_info *lwp = (struct lwp_info *) entry;
540 struct update_registers_data *data = (struct update_registers_data *) arg;
541
542 /* Only update the threads of the current process. */
543 if (pid_of (lwp) == pid_of (get_thread_lwp (current_inferior)))
544 {
545 /* The actual update is done later just before resuming the lwp,
546 we just mark that the registers need updating. */
547 if (data->watch)
548 lwp->arch_private->wpts_changed[data->i] = 1;
549 else
550 lwp->arch_private->bpts_changed[data->i] = 1;
551
552 /* If the lwp isn't stopped, force it to momentarily pause, so
553 we can update its breakpoint registers. */
554 if (!lwp->stopped)
555 linux_stop_lwp (lwp);
556 }
557
558 return 0;
559}
560
561/* Insert hardware break-/watchpoint. */
562static int
563arm_insert_point (char type, CORE_ADDR addr, int len)
564{
565 struct process_info *proc = current_process ();
566 struct arm_linux_hw_breakpoint p, *pts;
567 int watch, i, count;
568
569 watch = arm_linux_hw_point_initialize (type, addr, len, &p);
570 if (watch < 0)
571 {
572 /* Unsupported. */
b62e2b27 573 return watch == -1 ? 1 : -1;
09b4ad9f
UW
574 }
575
576 if (watch)
577 {
578 count = arm_linux_get_hw_watchpoint_count ();
579 pts = proc->private->arch_private->wpts;
580 }
581 else
582 {
583 count = arm_linux_get_hw_breakpoint_count ();
584 pts = proc->private->arch_private->bpts;
585 }
586
587 for (i = 0; i < count; i++)
588 if (!arm_hwbp_control_is_enabled (pts[i].control))
589 {
590 struct update_registers_data data = { watch, i };
591 pts[i] = p;
592 find_inferior (&all_lwps, update_registers_callback, &data);
593 return 0;
594 }
595
596 /* We're out of watchpoints. */
597 return -1;
598}
599
600/* Remove hardware break-/watchpoint. */
601static int
602arm_remove_point (char type, CORE_ADDR addr, int len)
603{
604 struct process_info *proc = current_process ();
605 struct arm_linux_hw_breakpoint p, *pts;
606 int watch, i, count;
607
608 watch = arm_linux_hw_point_initialize (type, addr, len, &p);
609 if (watch < 0)
610 {
611 /* Unsupported. */
612 return -1;
613 }
614
615 if (watch)
616 {
617 count = arm_linux_get_hw_watchpoint_count ();
618 pts = proc->private->arch_private->wpts;
619 }
620 else
621 {
622 count = arm_linux_get_hw_breakpoint_count ();
623 pts = proc->private->arch_private->bpts;
624 }
625
626 for (i = 0; i < count; i++)
627 if (arm_linux_hw_breakpoint_equal (&p, pts + i))
628 {
629 struct update_registers_data data = { watch, i };
630 pts[i].control = arm_hwbp_control_disable (pts[i].control);
631 find_inferior (&all_lwps, update_registers_callback, &data);
632 return 0;
633 }
634
635 /* No watchpoint matched. */
636 return -1;
637}
638
639/* Return whether current thread is stopped due to a watchpoint. */
640static int
641arm_stopped_by_watchpoint (void)
642{
643 struct lwp_info *lwp = get_thread_lwp (current_inferior);
a5362b9a 644 siginfo_t siginfo;
09b4ad9f
UW
645
646 /* We must be able to set hardware watchpoints. */
647 if (arm_linux_get_hw_watchpoint_count () == 0)
648 return 0;
649
650 /* Retrieve siginfo. */
651 errno = 0;
652 ptrace (PTRACE_GETSIGINFO, lwpid_of (lwp), 0, &siginfo);
653 if (errno != 0)
654 return 0;
655
656 /* This must be a hardware breakpoint. */
657 if (siginfo.si_signo != SIGTRAP
658 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
659 return 0;
660
661 /* If we are in a positive slot then we're looking at a breakpoint and not
662 a watchpoint. */
663 if (siginfo.si_errno >= 0)
664 return 0;
665
666 /* Cache stopped data address for use by arm_stopped_data_address. */
667 lwp->arch_private->stopped_data_address
668 = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
669
670 return 1;
671}
672
673/* Return data address that triggered watchpoint. Called only if
674 arm_stopped_by_watchpoint returned true. */
675static CORE_ADDR
676arm_stopped_data_address (void)
677{
678 struct lwp_info *lwp = get_thread_lwp (current_inferior);
679 return lwp->arch_private->stopped_data_address;
680}
681
682/* Called when a new process is created. */
683static struct arch_process_info *
684arm_new_process (void)
685{
686 struct arch_process_info *info = xcalloc (1, sizeof (*info));
687 return info;
688}
689
690/* Called when a new thread is detected. */
691static struct arch_lwp_info *
692arm_new_thread (void)
693{
694 struct arch_lwp_info *info = xcalloc (1, sizeof (*info));
695 int i;
696
697 for (i = 0; i < MAX_BPTS; i++)
698 info->bpts_changed[i] = 1;
699 for (i = 0; i < MAX_WPTS; i++)
700 info->wpts_changed[i] = 1;
701
702 return info;
703}
704
705/* Called when resuming a thread.
706 If the debug regs have changed, update the thread's copies. */
707static void
708arm_prepare_to_resume (struct lwp_info *lwp)
709{
710 int pid = lwpid_of (lwp);
711 struct process_info *proc = find_process_pid (pid_of (lwp));
712 struct arch_process_info *proc_info = proc->private->arch_private;
713 struct arch_lwp_info *lwp_info = lwp->arch_private;
714 int i;
715
716 for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++)
717 if (lwp_info->bpts_changed[i])
718 {
719 errno = 0;
720
721 if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control))
f15f9948 722 if (ptrace (PTRACE_SETHBPREGS, pid,
b8e1b30e 723 (PTRACE_TYPE_ARG3) ((i << 1) + 1),
f15f9948 724 &proc_info->bpts[i].address) < 0)
71487fd7 725 perror_with_name ("Unexpected error setting breakpoint address");
09b4ad9f
UW
726
727 if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control))
f15f9948 728 if (ptrace (PTRACE_SETHBPREGS, pid,
b8e1b30e 729 (PTRACE_TYPE_ARG3) ((i << 1) + 2),
f15f9948 730 &proc_info->bpts[i].control) < 0)
71487fd7 731 perror_with_name ("Unexpected error setting breakpoint");
09b4ad9f
UW
732
733 lwp_info->bpts_changed[i] = 0;
734 }
735
736 for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++)
737 if (lwp_info->wpts_changed[i])
738 {
739 errno = 0;
740
741 if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control))
f15f9948 742 if (ptrace (PTRACE_SETHBPREGS, pid,
b8e1b30e 743 (PTRACE_TYPE_ARG3) -((i << 1) + 1),
f15f9948 744 &proc_info->wpts[i].address) < 0)
71487fd7 745 perror_with_name ("Unexpected error setting watchpoint address");
09b4ad9f
UW
746
747 if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control))
f15f9948 748 if (ptrace (PTRACE_SETHBPREGS, pid,
b8e1b30e 749 (PTRACE_TYPE_ARG3) -((i << 1) + 2),
f15f9948 750 &proc_info->wpts[i].control) < 0)
71487fd7 751 perror_with_name ("Unexpected error setting watchpoint");
09b4ad9f
UW
752
753 lwp_info->wpts_changed[i] = 0;
754 }
755}
756
757
58d6951d
DJ
758static int
759arm_get_hwcap (unsigned long *valp)
760{
761 unsigned char *data = alloca (8);
762 int offset = 0;
763
764 while ((*the_target->read_auxv) (offset, data, 8) == 8)
765 {
766 unsigned int *data_p = (unsigned int *)data;
767 if (data_p[0] == AT_HWCAP)
768 {
769 *valp = data_p[1];
770 return 1;
771 }
772
773 offset += 8;
774 }
775
776 *valp = 0;
777 return 0;
778}
779
3aee8918
PA
780static const struct target_desc *
781arm_read_description (void)
58d6951d 782{
71487fd7
UW
783 int pid = lwpid_of (get_thread_lwp (current_inferior));
784
785 /* Query hardware watchpoint/breakpoint capabilities. */
786 arm_linux_init_hwbp_cap (pid);
787
58d6951d
DJ
788 arm_hwcap = 0;
789 if (arm_get_hwcap (&arm_hwcap) == 0)
3aee8918 790 return tdesc_arm;
58d6951d
DJ
791
792 if (arm_hwcap & HWCAP_IWMMXT)
3aee8918 793 return tdesc_arm_with_iwmmxt;
58d6951d
DJ
794
795 if (arm_hwcap & HWCAP_VFP)
796 {
3aee8918 797 const struct target_desc *result;
58d6951d
DJ
798 char *buf;
799
800 /* NEON implies either no VFP, or VFPv3-D32. We only support
801 it with VFP. */
802 if (arm_hwcap & HWCAP_NEON)
3aee8918 803 result = tdesc_arm_with_neon;
58d6951d 804 else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3)
3aee8918 805 result = tdesc_arm_with_vfpv3;
58d6951d 806 else
3aee8918 807 result = tdesc_arm_with_vfpv2;
58d6951d
DJ
808
809 /* Now make sure that the kernel supports reading these
810 registers. Support was added in 2.6.30. */
58d6951d 811 errno = 0;
c3e8aadd 812 buf = xmalloc (32 * 8 + 4);
58d6951d
DJ
813 if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
814 && errno == EIO)
815 {
816 arm_hwcap = 0;
3aee8918 817 result = tdesc_arm;
58d6951d
DJ
818 }
819 free (buf);
820
3aee8918 821 return result;
58d6951d
DJ
822 }
823
824 /* The default configuration uses legacy FPA registers, probably
825 simulated. */
3aee8918 826 return tdesc_arm;
58d6951d
DJ
827}
828
3aee8918
PA
829static void
830arm_arch_setup (void)
831{
832 current_process ()->tdesc = arm_read_description ();
833}
834
835static struct regset_info arm_regsets[] = {
1570b33e 836 { PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4,
fb1e4ffc
DJ
837 GENERAL_REGS,
838 arm_fill_gregset, arm_store_gregset },
1570b33e 839 { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4,
fb1e4ffc
DJ
840 EXTENDED_REGS,
841 arm_fill_wmmxregset, arm_store_wmmxregset },
1570b33e 842 { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4,
58d6951d
DJ
843 EXTENDED_REGS,
844 arm_fill_vfpregset, arm_store_vfpregset },
1570b33e 845 { 0, 0, 0, -1, -1, NULL, NULL }
fb1e4ffc
DJ
846};
847
3aee8918
PA
848static struct regsets_info arm_regsets_info =
849 {
850 arm_regsets, /* regsets */
851 0, /* num_regsets */
852 NULL, /* disabled_regsets */
853 };
854
855static struct usrregs_info arm_usrregs_info =
856 {
857 arm_num_regs,
858 arm_regmap,
859 };
860
861static struct regs_info regs_info =
862 {
863 NULL, /* regset_bitmap */
864 &arm_usrregs_info,
865 &arm_regsets_info
866 };
867
868static const struct regs_info *
869arm_regs_info (void)
870{
871 return &regs_info;
872}
873
2ec06d2e 874struct linux_target_ops the_low_target = {
58d6951d 875 arm_arch_setup,
3aee8918 876 arm_regs_info,
2ec06d2e
DJ
877 arm_cannot_fetch_register,
878 arm_cannot_store_register,
c14dfd32 879 NULL, /* fetch_register */
0d62e5e8
DJ
880 arm_get_pc,
881 arm_set_pc,
aeb75bf5
DJ
882
883 /* Define an ARM-mode breakpoint; we only set breakpoints in the C
884 library, which is most likely to be ARM. If the kernel supports
885 clone events, we will never insert a breakpoint, so even a Thumb
886 C library will work; so will mixing EABI/non-EABI gdbserver and
887 application. */
9d1fb177 888#ifndef __ARM_EABI__
f450004a 889 (const unsigned char *) &arm_breakpoint,
9d1fb177
DJ
890#else
891 (const unsigned char *) &arm_eabi_breakpoint,
892#endif
0d62e5e8 893 arm_breakpoint_len,
3b2fc2ea 894 arm_reinsert_addr,
0d62e5e8
DJ
895 0,
896 arm_breakpoint_at,
09b4ad9f
UW
897 arm_insert_point,
898 arm_remove_point,
899 arm_stopped_by_watchpoint,
900 arm_stopped_data_address,
901 NULL, /* collect_ptrace_register */
902 NULL, /* supply_ptrace_register */
903 NULL, /* siginfo_fixup */
904 arm_new_process,
905 arm_new_thread,
906 arm_prepare_to_resume,
2ec06d2e 907};
3aee8918
PA
908
909void
910initialize_low_arch (void)
911{
912 /* Initialize the Linux target descriptions. */
913 init_registers_arm ();
914 init_registers_arm_with_iwmmxt ();
915 init_registers_arm_with_vfpv2 ();
916 init_registers_arm_with_vfpv3 ();
917 init_registers_arm_with_neon ();
918
919 initialize_regsets_info (&arm_regsets_info);
920}
This page took 0.9981 seconds and 4 git commands to generate.