Commit | Line | Data |
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45b134e5 | 1 | /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. |
28e7fd62 | 2 | Copyright (C) 1995-2013 Free Software Foundation, Inc. |
45b134e5 OF |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
45b134e5 OF |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
45b134e5 OF |
18 | |
19 | #include "server.h" | |
20 | #include "linux-low.h" | |
21 | #include <sys/ptrace.h> | |
22 | ||
d05b4ac3 UW |
23 | /* Defined in auto-generated file reg-crisv32.c. */ |
24 | void init_registers_crisv32 (void); | |
3aee8918 | 25 | extern const struct target_desc *tdesc_crisv32; |
d05b4ac3 | 26 | |
45b134e5 OF |
27 | /* CRISv32 */ |
28 | #define cris_num_regs 49 | |
29 | ||
30 | /* Note: Ignoring USP (having the stack pointer in two locations causes trouble | |
31 | without any significant gain). */ | |
32 | ||
33 | /* Locations need to match <include/asm/arch/ptrace.h>. */ | |
34 | static int cris_regmap[] = { | |
35 | 1*4, 2*4, 3*4, 4*4, | |
36 | 5*4, 6*4, 7*4, 8*4, | |
37 | 9*4, 10*4, 11*4, 12*4, | |
38 | 13*4, 14*4, 24*4, 15*4, | |
39 | ||
40 | -1, -1, -1, 16*4, | |
41 | -1, 22*4, 23*4, 17*4, | |
42 | -1, -1, 21*4, 20*4, | |
43 | -1, 19*4, -1, 18*4, | |
44 | ||
45 | 25*4, | |
46 | ||
1b3f6016 | 47 | 26*4, -1, -1, 29*4, |
45b134e5 OF |
48 | 30*4, 31*4, 32*4, 33*4, |
49 | 34*4, 35*4, 36*4, 37*4, | |
50 | 38*4, 39*4, 40*4, -1 | |
1b3f6016 | 51 | |
45b134e5 OF |
52 | }; |
53 | ||
54 | extern int debug_threads; | |
55 | ||
56 | static CORE_ADDR | |
442ea881 | 57 | cris_get_pc (struct regcache *regcache) |
45b134e5 OF |
58 | { |
59 | unsigned long pc; | |
442ea881 | 60 | collect_register_by_name (regcache, "pc", &pc); |
45b134e5 OF |
61 | if (debug_threads) |
62 | fprintf (stderr, "stop pc is %08lx\n", pc); | |
63 | return pc; | |
64 | } | |
65 | ||
66 | static void | |
442ea881 | 67 | cris_set_pc (struct regcache *regcache, CORE_ADDR pc) |
45b134e5 OF |
68 | { |
69 | unsigned long newpc = pc; | |
442ea881 | 70 | supply_register_by_name (regcache, "pc", &newpc); |
45b134e5 OF |
71 | } |
72 | ||
73 | static const unsigned short cris_breakpoint = 0xe938; | |
74 | #define cris_breakpoint_len 2 | |
75 | ||
76 | static int | |
77 | cris_breakpoint_at (CORE_ADDR where) | |
78 | { | |
79 | unsigned short insn; | |
80 | ||
f450004a DJ |
81 | (*the_target->read_memory) (where, (unsigned char *) &insn, |
82 | cris_breakpoint_len); | |
45b134e5 OF |
83 | if (insn == cris_breakpoint) |
84 | return 1; | |
85 | ||
86 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
87 | one. */ | |
88 | return 0; | |
89 | } | |
90 | ||
91 | /* We only place breakpoints in empty marker functions, and thread locking | |
92 | is outside of the function. So rather than importing software single-step, | |
93 | we can just run until exit. */ | |
94 | ||
95 | /* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP | |
96 | for CRISv32. Without it, td_ta_event_getmsg in thread_db_create_event | |
97 | will fail when debugging multi-threaded applications. */ | |
98 | ||
99 | static CORE_ADDR | |
100 | cris_reinsert_addr (void) | |
101 | { | |
442ea881 | 102 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
45b134e5 | 103 | unsigned long pc; |
442ea881 | 104 | collect_register_by_name (regcache, "srp", &pc); |
45b134e5 OF |
105 | return pc; |
106 | } | |
107 | ||
108 | static void | |
442ea881 PA |
109 | cris_write_data_breakpoint (struct regcache *regcache, |
110 | int bp, unsigned long start, unsigned long end) | |
45b134e5 OF |
111 | { |
112 | switch (bp) | |
113 | { | |
114 | case 0: | |
442ea881 PA |
115 | supply_register_by_name (regcache, "s3", &start); |
116 | supply_register_by_name (regcache, "s4", &end); | |
45b134e5 OF |
117 | break; |
118 | case 1: | |
442ea881 PA |
119 | supply_register_by_name (regcache, "s5", &start); |
120 | supply_register_by_name (regcache, "s6", &end); | |
45b134e5 OF |
121 | break; |
122 | case 2: | |
442ea881 PA |
123 | supply_register_by_name (regcache, "s7", &start); |
124 | supply_register_by_name (regcache, "s8", &end); | |
45b134e5 OF |
125 | break; |
126 | case 3: | |
442ea881 PA |
127 | supply_register_by_name (regcache, "s9", &start); |
128 | supply_register_by_name (regcache, "s10", &end); | |
45b134e5 OF |
129 | break; |
130 | case 4: | |
442ea881 PA |
131 | supply_register_by_name (regcache, "s11", &start); |
132 | supply_register_by_name (regcache, "s12", &end); | |
45b134e5 OF |
133 | break; |
134 | case 5: | |
442ea881 PA |
135 | supply_register_by_name (regcache, "s13", &start); |
136 | supply_register_by_name (regcache, "s14", &end); | |
45b134e5 OF |
137 | break; |
138 | } | |
139 | } | |
140 | ||
141 | static int | |
d993e290 | 142 | cris_insert_point (char type, CORE_ADDR addr, int len) |
45b134e5 OF |
143 | { |
144 | int bp; | |
145 | unsigned long bp_ctrl; | |
146 | unsigned long start, end; | |
147 | unsigned long ccs; | |
442ea881 | 148 | struct regcache *regcache; |
1b3f6016 | 149 | |
45b134e5 OF |
150 | /* Breakpoint/watchpoint types (GDB terminology): |
151 | 0 = memory breakpoint for instructions | |
152 | (not supported; done via memory write instead) | |
153 | 1 = hardware breakpoint for instructions (not supported) | |
154 | 2 = write watchpoint (supported) | |
155 | 3 = read watchpoint (supported) | |
156 | 4 = access watchpoint (supported). */ | |
1b3f6016 PA |
157 | |
158 | if (type < '2' || type > '4') | |
45b134e5 OF |
159 | { |
160 | /* Unsupported. */ | |
161 | return 1; | |
162 | } | |
163 | ||
442ea881 PA |
164 | regcache = get_thread_regcache (current_inferior, 1); |
165 | ||
45b134e5 OF |
166 | /* Read watchpoints are set as access watchpoints, because of GDB's |
167 | inability to deal with pure read watchpoints. */ | |
168 | if (type == '3') | |
169 | type = '4'; | |
170 | ||
171 | /* Get the configuration register. */ | |
442ea881 | 172 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
173 | |
174 | /* The watchpoint allocation scheme is the simplest possible. | |
175 | For example, if a region is watched for read and | |
176 | a write watch is requested, a new watchpoint will | |
177 | be used. Also, if a watch for a region that is already | |
178 | covered by one or more existing watchpoints, a new | |
179 | watchpoint will be used. */ | |
1b3f6016 | 180 | |
45b134e5 OF |
181 | /* First, find a free data watchpoint. */ |
182 | for (bp = 0; bp < 6; bp++) | |
183 | { | |
184 | /* Each data watchpoint's control registers occupy 2 bits | |
185 | (hence the 3), starting at bit 2 for D0 (hence the 2) | |
186 | with 4 bits between for each watchpoint (yes, the 4). */ | |
1b3f6016 | 187 | if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) |
45b134e5 OF |
188 | break; |
189 | } | |
1b3f6016 | 190 | |
45b134e5 OF |
191 | if (bp > 5) |
192 | { | |
193 | /* We're out of watchpoints. */ | |
194 | return -1; | |
195 | } | |
196 | ||
197 | /* Configure the control register first. */ | |
198 | if (type == '3' || type == '4') | |
199 | { | |
200 | /* Trigger on read. */ | |
201 | bp_ctrl |= (1 << (2 + bp * 4)); | |
202 | } | |
1b3f6016 | 203 | if (type == '2' || type == '4') |
45b134e5 OF |
204 | { |
205 | /* Trigger on write. */ | |
206 | bp_ctrl |= (2 << (2 + bp * 4)); | |
207 | } | |
1b3f6016 | 208 | |
45b134e5 | 209 | /* Setup the configuration register. */ |
442ea881 | 210 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
1b3f6016 | 211 | |
45b134e5 OF |
212 | /* Setup the range. */ |
213 | start = addr; | |
214 | end = addr + len - 1; | |
215 | ||
216 | /* Configure the watchpoint register. */ | |
442ea881 | 217 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 | 218 | |
442ea881 | 219 | collect_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
220 | /* Set the S1 flag to enable watchpoints. */ |
221 | ccs |= (1 << 19); | |
442ea881 | 222 | supply_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
227 | static int | |
d993e290 | 228 | cris_remove_point (char type, CORE_ADDR addr, int len) |
45b134e5 OF |
229 | { |
230 | int bp; | |
231 | unsigned long bp_ctrl; | |
232 | unsigned long start, end; | |
442ea881 | 233 | struct regcache *regcache; |
07c04788 | 234 | unsigned long bp_d_regs[12]; |
1b3f6016 | 235 | |
45b134e5 OF |
236 | /* Breakpoint/watchpoint types: |
237 | 0 = memory breakpoint for instructions | |
238 | (not supported; done via memory write instead) | |
239 | 1 = hardware breakpoint for instructions (not supported) | |
240 | 2 = write watchpoint (supported) | |
241 | 3 = read watchpoint (supported) | |
242 | 4 = access watchpoint (supported). */ | |
243 | if (type < '2' || type > '4') | |
244 | return -1; | |
1b3f6016 | 245 | |
442ea881 PA |
246 | regcache = get_thread_regcache (current_inferior, 1); |
247 | ||
45b134e5 OF |
248 | /* Read watchpoints are set as access watchpoints, because of GDB's |
249 | inability to deal with pure read watchpoints. */ | |
250 | if (type == '3') | |
251 | type = '4'; | |
1b3f6016 | 252 | |
45b134e5 | 253 | /* Get the configuration register. */ |
442ea881 | 254 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
255 | |
256 | /* Try to find a watchpoint that is configured for the | |
257 | specified range, then check that read/write also matches. */ | |
1b3f6016 | 258 | |
45b134e5 OF |
259 | /* Ugly pointer arithmetic, since I cannot rely on a |
260 | single switch (addr) as there may be several watchpoints with | |
261 | the same start address for example. */ | |
262 | ||
45b134e5 | 263 | /* Get all range registers to simplify search. */ |
442ea881 PA |
264 | collect_register_by_name (regcache, "s3", &bp_d_regs[0]); |
265 | collect_register_by_name (regcache, "s4", &bp_d_regs[1]); | |
266 | collect_register_by_name (regcache, "s5", &bp_d_regs[2]); | |
267 | collect_register_by_name (regcache, "s6", &bp_d_regs[3]); | |
268 | collect_register_by_name (regcache, "s7", &bp_d_regs[4]); | |
269 | collect_register_by_name (regcache, "s8", &bp_d_regs[5]); | |
270 | collect_register_by_name (regcache, "s9", &bp_d_regs[6]); | |
271 | collect_register_by_name (regcache, "s10", &bp_d_regs[7]); | |
272 | collect_register_by_name (regcache, "s11", &bp_d_regs[8]); | |
273 | collect_register_by_name (regcache, "s12", &bp_d_regs[9]); | |
274 | collect_register_by_name (regcache, "s13", &bp_d_regs[10]); | |
275 | collect_register_by_name (regcache, "s14", &bp_d_regs[11]); | |
45b134e5 | 276 | |
1b3f6016 | 277 | for (bp = 0; bp < 6; bp++) |
45b134e5 | 278 | { |
1b3f6016 | 279 | if (bp_d_regs[bp * 2] == addr |
45b134e5 OF |
280 | && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { |
281 | /* Matching range. */ | |
282 | int bitpos = 2 + bp * 4; | |
283 | int rw_bits; | |
1b3f6016 | 284 | |
45b134e5 OF |
285 | /* Read/write bits for this BP. */ |
286 | rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; | |
1b3f6016 | 287 | |
45b134e5 | 288 | if ((type == '3' && rw_bits == 0x1) |
1b3f6016 | 289 | || (type == '2' && rw_bits == 0x2) |
45b134e5 OF |
290 | || (type == '4' && rw_bits == 0x3)) |
291 | { | |
292 | /* Read/write matched. */ | |
293 | break; | |
294 | } | |
295 | } | |
296 | } | |
1b3f6016 | 297 | |
45b134e5 OF |
298 | if (bp > 5) |
299 | { | |
300 | /* No watchpoint matched. */ | |
301 | return -1; | |
302 | } | |
1b3f6016 | 303 | |
45b134e5 OF |
304 | /* Found a matching watchpoint. Now, deconfigure it by |
305 | both disabling read/write in bp_ctrl and zeroing its | |
306 | start/end addresses. */ | |
307 | bp_ctrl &= ~(3 << (2 + (bp * 4))); | |
308 | /* Setup the configuration register. */ | |
442ea881 | 309 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
310 | |
311 | start = end = 0; | |
312 | /* Configure the watchpoint register. */ | |
442ea881 | 313 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 OF |
314 | |
315 | /* Note that we don't clear the S1 flag here. It's done when continuing. */ | |
316 | return 0; | |
317 | } | |
318 | ||
319 | static int | |
320 | cris_stopped_by_watchpoint (void) | |
321 | { | |
322 | unsigned long exs; | |
07c04788 | 323 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
45b134e5 | 324 | |
07c04788 | 325 | collect_register_by_name (regcache, "exs", &exs); |
45b134e5 OF |
326 | |
327 | return (((exs & 0xff00) >> 8) == 0xc); | |
328 | } | |
329 | ||
330 | static CORE_ADDR | |
331 | cris_stopped_data_address (void) | |
332 | { | |
333 | unsigned long eda; | |
07c04788 | 334 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
45b134e5 | 335 | |
07c04788 | 336 | collect_register_by_name (regcache, "eda", &eda); |
45b134e5 OF |
337 | |
338 | /* FIXME: Possibly adjust to match watched range. */ | |
339 | return eda; | |
340 | } | |
341 | ||
342 | static void | |
07c04788 | 343 | cris_fill_gregset (struct regcache *regcache, void *buf) |
45b134e5 OF |
344 | { |
345 | int i; | |
346 | ||
347 | for (i = 0; i < cris_num_regs; i++) | |
348 | { | |
349 | if (cris_regmap[i] != -1) | |
07c04788 | 350 | collect_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
351 | } |
352 | } | |
353 | ||
354 | static void | |
07c04788 | 355 | cris_store_gregset (struct regcache *regcache, const void *buf) |
45b134e5 OF |
356 | { |
357 | int i; | |
358 | ||
359 | for (i = 0; i < cris_num_regs; i++) | |
360 | { | |
361 | if (cris_regmap[i] != -1) | |
07c04788 | 362 | supply_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
363 | } |
364 | } | |
365 | ||
3aee8918 PA |
366 | static void |
367 | cris_arch_setup (void) | |
368 | { | |
369 | current_process ()->tdesc = tdesc_crisv32; | |
370 | } | |
371 | ||
372 | typedef unsigned long elf_gregset_t[cris_num_regs]; | |
373 | ||
374 | static struct regset_info cris_regsets[] = { | |
07c04788 | 375 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4, |
45b134e5 | 376 | GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, |
1570b33e | 377 | { 0, 0, 0, -1, -1, NULL, NULL } |
45b134e5 OF |
378 | }; |
379 | ||
3aee8918 PA |
380 | |
381 | static struct regsets_info cris_regsets_info = | |
382 | { | |
383 | cris_regsets, /* regsets */ | |
384 | 0, /* num_regsets */ | |
385 | NULL, /* disabled_regsets */ | |
386 | }; | |
387 | ||
388 | static struct usrregs_info cris_usrregs_info = | |
389 | { | |
390 | cris_num_regs, | |
391 | cris_regmap, | |
392 | }; | |
393 | ||
394 | static struct regs_info regs_info = | |
395 | { | |
396 | NULL, /* regset_bitmap */ | |
397 | &cris_usrregs_info, | |
398 | &cris_regsets_info | |
399 | }; | |
400 | ||
401 | static const struct regs_info * | |
402 | cris_regs_info (void) | |
403 | { | |
404 | return ®s_info; | |
405 | } | |
406 | ||
45b134e5 | 407 | struct linux_target_ops the_low_target = { |
3aee8918 PA |
408 | cris_arch_setup, |
409 | cris_regs_info, | |
45b134e5 | 410 | NULL, |
1faeff08 | 411 | NULL, |
c14dfd32 | 412 | NULL, /* fetch_register */ |
45b134e5 OF |
413 | cris_get_pc, |
414 | cris_set_pc, | |
f450004a | 415 | (const unsigned char *) &cris_breakpoint, |
45b134e5 OF |
416 | cris_breakpoint_len, |
417 | cris_reinsert_addr, | |
418 | 0, | |
419 | cris_breakpoint_at, | |
d993e290 PA |
420 | cris_insert_point, |
421 | cris_remove_point, | |
45b134e5 OF |
422 | cris_stopped_by_watchpoint, |
423 | cris_stopped_data_address, | |
424 | }; | |
3aee8918 PA |
425 | |
426 | void | |
427 | initialize_low_arch (void) | |
428 | { | |
429 | init_register_crisv32 (); | |
430 | ||
431 | initialize_regsets_info (&cris_regsets_info); | |
432 | } |