Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
ecd75fc8 | 2 | Copyright (C) 1995-2014 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
21b0f40c | 22 | #include <sys/ptrace.h> |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
d05b4ac3 UW |
28 | /* Defined in auto-generated file mips-linux.c. */ |
29 | void init_registers_mips_linux (void); | |
3aee8918 PA |
30 | extern const struct target_desc *tdesc_mips_linux; |
31 | ||
1faeff08 MR |
32 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
33 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
34 | extern const struct target_desc *tdesc_mips_dsp_linux; |
35 | ||
d05b4ac3 UW |
36 | /* Defined in auto-generated file mips64-linux.c. */ |
37 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
38 | extern const struct target_desc *tdesc_mips64_linux; |
39 | ||
1faeff08 MR |
40 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
41 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 42 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
43 | |
44 | #ifdef __mips64 | |
3aee8918 PA |
45 | #define tdesc_mips_linux tdesc_mips64_linux |
46 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 47 | #endif |
d05b4ac3 | 48 | |
21b0f40c DJ |
49 | #ifndef PTRACE_GET_THREAD_AREA |
50 | #define PTRACE_GET_THREAD_AREA 25 | |
51 | #endif | |
52 | ||
0a30fbc4 DJ |
53 | #ifdef HAVE_SYS_REG_H |
54 | #include <sys/reg.h> | |
55 | #endif | |
56 | ||
117ce543 | 57 | #define mips_num_regs 73 |
1faeff08 | 58 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
59 | |
60 | #include <asm/ptrace.h> | |
61 | ||
1faeff08 MR |
62 | #ifndef DSP_BASE |
63 | #define DSP_BASE 71 | |
64 | #define DSP_CONTROL 77 | |
65 | #endif | |
66 | ||
186947f7 DJ |
67 | union mips_register |
68 | { | |
69 | unsigned char buf[8]; | |
70 | ||
71 | /* Deliberately signed, for proper sign extension. */ | |
72 | int reg32; | |
73 | long long reg64; | |
74 | }; | |
75 | ||
0a30fbc4 DJ |
76 | /* Return the ptrace ``address'' of register REGNO. */ |
77 | ||
1faeff08 MR |
78 | #define mips_base_regs \ |
79 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
80 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
81 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
82 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
83 | \ | |
84 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
85 | \ | |
86 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
87 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
88 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
89 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
90 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
91 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
92 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
93 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
94 | FPC_CSR, FPC_EIR | |
95 | ||
96 | #define mips_dsp_regs \ | |
97 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
98 | DSP_BASE + 4, DSP_BASE + 5, \ | |
99 | DSP_CONTROL | |
100 | ||
101 | static int mips_regmap[mips_num_regs] = { | |
102 | mips_base_regs, | |
103 | 0 | |
104 | }; | |
0a30fbc4 | 105 | |
1faeff08 MR |
106 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
107 | mips_base_regs, | |
108 | mips_dsp_regs, | |
109 | 0 | |
110 | }; | |
0a30fbc4 | 111 | |
1faeff08 MR |
112 | /* DSP registers are not in any regset and can only be accessed |
113 | individually. */ | |
0a30fbc4 | 114 | |
1faeff08 MR |
115 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
116 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
117 | }; |
118 | ||
3aee8918 PA |
119 | static int have_dsp = -1; |
120 | ||
1faeff08 MR |
121 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
122 | user register set accordingly. */ | |
123 | ||
3aee8918 PA |
124 | static const struct target_desc * |
125 | mips_read_description (void) | |
1faeff08 | 126 | { |
3aee8918 | 127 | if (have_dsp < 0) |
1faeff08 | 128 | { |
d86d4aaf | 129 | int pid = lwpid_of (current_inferior); |
1faeff08 MR |
130 | |
131 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); | |
132 | switch (errno) | |
133 | { | |
134 | case 0: | |
3aee8918 | 135 | have_dsp = 1; |
1faeff08 MR |
136 | break; |
137 | case EIO: | |
3aee8918 | 138 | have_dsp = 0; |
1faeff08 MR |
139 | break; |
140 | default: | |
141 | perror_with_name ("ptrace"); | |
142 | break; | |
143 | } | |
144 | } | |
3aee8918 PA |
145 | |
146 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
147 | } | |
148 | ||
149 | static void | |
150 | mips_arch_setup (void) | |
151 | { | |
152 | current_process ()->tdesc = mips_read_description (); | |
153 | } | |
154 | ||
155 | static struct usrregs_info * | |
156 | get_usrregs_info (void) | |
157 | { | |
158 | const struct regs_info *regs_info = the_low_target.regs_info (); | |
159 | ||
160 | return regs_info->usrregs; | |
1faeff08 MR |
161 | } |
162 | ||
7a60ad40 YQ |
163 | /* Per-process arch-specific data we want to keep. */ |
164 | ||
165 | struct arch_process_info | |
166 | { | |
167 | /* -1 if the kernel and/or CPU do not support watch registers. | |
168 | 1 if watch_readback is valid and we can read style, num_valid | |
169 | and the masks. | |
170 | 0 if we need to read the watch_readback. */ | |
171 | ||
172 | int watch_readback_valid; | |
173 | ||
174 | /* Cached watch register read values. */ | |
175 | ||
176 | struct pt_watch_regs watch_readback; | |
177 | ||
178 | /* Current watchpoint requests for this process. */ | |
179 | ||
180 | struct mips_watchpoint *current_watches; | |
181 | ||
182 | /* The current set of watch register values for writing the | |
183 | registers. */ | |
184 | ||
185 | struct pt_watch_regs watch_mirror; | |
186 | }; | |
187 | ||
188 | /* Per-thread arch-specific data we want to keep. */ | |
189 | ||
190 | struct arch_lwp_info | |
191 | { | |
192 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
193 | int watch_registers_changed; | |
194 | }; | |
195 | ||
0a30fbc4 DJ |
196 | /* From mips-linux-nat.c. */ |
197 | ||
198 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
199 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
200 | ZERO_REGNUM. We also can not set BADVADDR, CAUSE, or FCRIR via | |
201 | ptrace(). */ | |
202 | ||
2ec06d2e DJ |
203 | static int |
204 | mips_cannot_fetch_register (int regno) | |
0a30fbc4 | 205 | { |
3aee8918 PA |
206 | const struct target_desc *tdesc; |
207 | ||
208 | if (get_usrregs_info ()->regmap[regno] == -1) | |
0a30fbc4 DJ |
209 | return 1; |
210 | ||
3aee8918 PA |
211 | tdesc = current_process ()->tdesc; |
212 | ||
213 | if (find_regno (tdesc, "r0") == regno) | |
0a30fbc4 DJ |
214 | return 1; |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
2ec06d2e DJ |
219 | static int |
220 | mips_cannot_store_register (int regno) | |
0a30fbc4 | 221 | { |
3aee8918 PA |
222 | const struct target_desc *tdesc; |
223 | ||
224 | if (get_usrregs_info ()->regmap[regno] == -1) | |
0a30fbc4 DJ |
225 | return 1; |
226 | ||
3aee8918 PA |
227 | tdesc = current_process ()->tdesc; |
228 | ||
229 | if (find_regno (tdesc, "r0") == regno) | |
0a30fbc4 DJ |
230 | return 1; |
231 | ||
3aee8918 | 232 | if (find_regno (tdesc, "cause") == regno) |
0a30fbc4 DJ |
233 | return 1; |
234 | ||
3aee8918 | 235 | if (find_regno (tdesc, "badvaddr") == regno) |
0a30fbc4 DJ |
236 | return 1; |
237 | ||
3aee8918 | 238 | if (find_regno (tdesc, "fir") == regno) |
0a30fbc4 DJ |
239 | return 1; |
240 | ||
241 | return 0; | |
242 | } | |
2ec06d2e | 243 | |
0d62e5e8 | 244 | static CORE_ADDR |
442ea881 | 245 | mips_get_pc (struct regcache *regcache) |
0d62e5e8 | 246 | { |
186947f7 | 247 | union mips_register pc; |
442ea881 | 248 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 249 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
250 | } |
251 | ||
252 | static void | |
442ea881 | 253 | mips_set_pc (struct regcache *regcache, CORE_ADDR pc) |
0d62e5e8 | 254 | { |
186947f7 | 255 | union mips_register newpc; |
3aee8918 | 256 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
257 | newpc.reg32 = pc; |
258 | else | |
259 | newpc.reg64 = pc; | |
260 | ||
442ea881 | 261 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
262 | } |
263 | ||
264 | /* Correct in either endianness. */ | |
186947f7 | 265 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
266 | #define mips_breakpoint_len 4 |
267 | ||
268 | /* We only place breakpoints in empty marker functions, and thread locking | |
269 | is outside of the function. So rather than importing software single-step, | |
270 | we can just run until exit. */ | |
271 | static CORE_ADDR | |
442ea881 | 272 | mips_reinsert_addr (void) |
0d62e5e8 | 273 | { |
442ea881 | 274 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
186947f7 | 275 | union mips_register ra; |
442ea881 | 276 | collect_register_by_name (regcache, "r31", ra.buf); |
3aee8918 | 277 | return register_size (regcache->tdesc, 0) == 4 ? ra.reg32 : ra.reg64; |
0d62e5e8 DJ |
278 | } |
279 | ||
280 | static int | |
281 | mips_breakpoint_at (CORE_ADDR where) | |
282 | { | |
186947f7 | 283 | unsigned int insn; |
0d62e5e8 | 284 | |
f450004a | 285 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); |
0d62e5e8 DJ |
286 | if (insn == mips_breakpoint) |
287 | return 1; | |
288 | ||
289 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
290 | one. */ | |
291 | return 0; | |
292 | } | |
293 | ||
7a60ad40 YQ |
294 | /* Mark the watch registers of lwp, represented by ENTRY, as changed, |
295 | if the lwp's process id is *PID_P. */ | |
296 | ||
297 | static int | |
298 | update_watch_registers_callback (struct inferior_list_entry *entry, | |
299 | void *pid_p) | |
300 | { | |
d86d4aaf DE |
301 | struct thread_info *thread = (struct thread_info *) entry; |
302 | struct lwp_info *lwp = get_thread_lwp (thread); | |
7a60ad40 YQ |
303 | int pid = *(int *) pid_p; |
304 | ||
305 | /* Only update the threads of this process. */ | |
d86d4aaf | 306 | if (pid_of (thread) == pid) |
7a60ad40 YQ |
307 | { |
308 | /* The actual update is done later just before resuming the lwp, | |
309 | we just mark that the registers need updating. */ | |
310 | lwp->arch_private->watch_registers_changed = 1; | |
311 | ||
312 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
313 | we can update its watch registers. */ | |
314 | if (!lwp->stopped) | |
315 | linux_stop_lwp (lwp); | |
316 | } | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
321 | /* This is the implementation of linux_target_ops method | |
322 | new_process. */ | |
323 | ||
324 | static struct arch_process_info * | |
325 | mips_linux_new_process (void) | |
326 | { | |
327 | struct arch_process_info *info = xcalloc (1, sizeof (*info)); | |
328 | ||
329 | return info; | |
330 | } | |
331 | ||
332 | /* This is the implementation of linux_target_ops method new_thread. | |
333 | Mark the watch registers as changed, so the threads' copies will | |
334 | be updated. */ | |
335 | ||
336 | static struct arch_lwp_info * | |
337 | mips_linux_new_thread (void) | |
338 | { | |
339 | struct arch_lwp_info *info = xcalloc (1, sizeof (*info)); | |
340 | ||
341 | info->watch_registers_changed = 1; | |
342 | ||
343 | return info; | |
344 | } | |
345 | ||
346 | /* This is the implementation of linux_target_ops method | |
347 | prepare_to_resume. If the watch regs have changed, update the | |
348 | thread's copies. */ | |
349 | ||
350 | static void | |
351 | mips_linux_prepare_to_resume (struct lwp_info *lwp) | |
352 | { | |
d86d4aaf | 353 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
7a60ad40 YQ |
354 | struct process_info *proc = find_process_pid (ptid_get_pid (ptid)); |
355 | struct arch_process_info *private = proc->private->arch_private; | |
356 | ||
357 | if (lwp->arch_private->watch_registers_changed) | |
358 | { | |
359 | /* Only update the watch registers if we have set or unset a | |
360 | watchpoint already. */ | |
361 | if (mips_linux_watch_get_num_valid (&private->watch_mirror) > 0) | |
362 | { | |
363 | /* Write the mirrored watch register values. */ | |
364 | int tid = ptid_get_lwp (ptid); | |
365 | ||
366 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
367 | &private->watch_mirror)) | |
368 | perror_with_name ("Couldn't write watch register"); | |
369 | } | |
370 | ||
371 | lwp->arch_private->watch_registers_changed = 0; | |
372 | } | |
373 | } | |
374 | ||
802e8e6d PA |
375 | static int |
376 | mips_supports_z_point_type (char z_type) | |
377 | { | |
378 | switch (z_type) | |
379 | { | |
380 | case Z_PACKET_WRITE_WP: | |
381 | case Z_PACKET_READ_WP: | |
382 | case Z_PACKET_ACCESS_WP: | |
383 | return 1; | |
384 | default: | |
385 | return 0; | |
386 | } | |
387 | } | |
388 | ||
7a60ad40 YQ |
389 | /* This is the implementation of linux_target_ops method |
390 | insert_point. */ | |
391 | ||
392 | static int | |
802e8e6d PA |
393 | mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
394 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
395 | { |
396 | struct process_info *proc = current_process (); | |
397 | struct arch_process_info *private = proc->private->arch_private; | |
398 | struct pt_watch_regs regs; | |
399 | struct mips_watchpoint *new_watch; | |
400 | struct mips_watchpoint **pw; | |
401 | int pid; | |
402 | long lwpid; | |
403 | enum target_hw_bp_type watch_type; | |
404 | uint32_t irw; | |
405 | ||
d86d4aaf | 406 | lwpid = lwpid_of (current_inferior); |
7a60ad40 YQ |
407 | if (!mips_linux_read_watch_registers (lwpid, |
408 | &private->watch_readback, | |
409 | &private->watch_readback_valid, | |
410 | 0)) | |
411 | return -1; | |
412 | ||
413 | if (len <= 0) | |
414 | return -1; | |
415 | ||
416 | regs = private->watch_readback; | |
417 | /* Add the current watches. */ | |
418 | mips_linux_watch_populate_regs (private->current_watches, ®s); | |
419 | ||
420 | /* Now try to add the new watch. */ | |
802e8e6d | 421 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
422 | irw = mips_linux_watch_type_to_irw (watch_type); |
423 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
424 | return -1; | |
425 | ||
426 | /* It fit. Stick it on the end of the list. */ | |
427 | new_watch = xmalloc (sizeof (struct mips_watchpoint)); | |
428 | new_watch->addr = addr; | |
429 | new_watch->len = len; | |
430 | new_watch->type = watch_type; | |
431 | new_watch->next = NULL; | |
432 | ||
433 | pw = &private->current_watches; | |
434 | while (*pw != NULL) | |
435 | pw = &(*pw)->next; | |
436 | *pw = new_watch; | |
437 | ||
438 | private->watch_mirror = regs; | |
439 | ||
440 | /* Only update the threads of this process. */ | |
441 | pid = pid_of (proc); | |
d86d4aaf | 442 | find_inferior (&all_threads, update_watch_registers_callback, &pid); |
7a60ad40 YQ |
443 | |
444 | return 0; | |
445 | } | |
446 | ||
447 | /* This is the implementation of linux_target_ops method | |
448 | remove_point. */ | |
449 | ||
450 | static int | |
802e8e6d PA |
451 | mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
452 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
453 | { |
454 | struct process_info *proc = current_process (); | |
455 | struct arch_process_info *private = proc->private->arch_private; | |
456 | ||
457 | int deleted_one; | |
458 | int pid; | |
459 | enum target_hw_bp_type watch_type; | |
460 | ||
461 | struct mips_watchpoint **pw; | |
462 | struct mips_watchpoint *w; | |
463 | ||
7a60ad40 | 464 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 465 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
466 | deleted_one = 0; |
467 | pw = &private->current_watches; | |
468 | while ((w = *pw)) | |
469 | { | |
470 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
471 | { | |
472 | *pw = w->next; | |
473 | free (w); | |
474 | deleted_one = 1; | |
475 | break; | |
476 | } | |
477 | pw = &(w->next); | |
478 | } | |
479 | ||
480 | if (!deleted_one) | |
481 | return -1; /* We don't know about it, fail doing nothing. */ | |
482 | ||
483 | /* At this point watch_readback is known to be valid because we | |
484 | could not have added the watch without reading it. */ | |
485 | gdb_assert (private->watch_readback_valid == 1); | |
486 | ||
487 | private->watch_mirror = private->watch_readback; | |
488 | mips_linux_watch_populate_regs (private->current_watches, | |
489 | &private->watch_mirror); | |
490 | ||
491 | /* Only update the threads of this process. */ | |
492 | pid = pid_of (proc); | |
d86d4aaf | 493 | find_inferior (&all_threads, update_watch_registers_callback, &pid); |
7a60ad40 YQ |
494 | return 0; |
495 | } | |
496 | ||
497 | /* This is the implementation of linux_target_ops method | |
498 | stopped_by_watchpoint. The watchhi R and W bits indicate | |
499 | the watch register triggered. */ | |
500 | ||
501 | static int | |
502 | mips_stopped_by_watchpoint (void) | |
503 | { | |
504 | struct process_info *proc = current_process (); | |
505 | struct arch_process_info *private = proc->private->arch_private; | |
506 | int n; | |
507 | int num_valid; | |
d86d4aaf | 508 | long lwpid = lwpid_of (current_inferior); |
7a60ad40 YQ |
509 | |
510 | if (!mips_linux_read_watch_registers (lwpid, | |
511 | &private->watch_readback, | |
512 | &private->watch_readback_valid, | |
513 | 1)) | |
514 | return 0; | |
515 | ||
516 | num_valid = mips_linux_watch_get_num_valid (&private->watch_readback); | |
517 | ||
518 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
519 | if (mips_linux_watch_get_watchhi (&private->watch_readback, n) | |
520 | & (R_MASK | W_MASK)) | |
521 | return 1; | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | /* This is the implementation of linux_target_ops method | |
527 | stopped_data_address. */ | |
528 | ||
529 | static CORE_ADDR | |
530 | mips_stopped_data_address (void) | |
531 | { | |
532 | struct process_info *proc = current_process (); | |
533 | struct arch_process_info *private = proc->private->arch_private; | |
534 | int n; | |
535 | int num_valid; | |
d86d4aaf | 536 | long lwpid = lwpid_of (current_inferior); |
7a60ad40 YQ |
537 | |
538 | /* On MIPS we don't know the low order 3 bits of the data address. | |
539 | GDB does not support remote targets that can't report the | |
540 | watchpoint address. So, make our best guess; return the starting | |
541 | address of a watchpoint request which overlaps the one that | |
542 | triggered. */ | |
543 | ||
544 | if (!mips_linux_read_watch_registers (lwpid, | |
545 | &private->watch_readback, | |
546 | &private->watch_readback_valid, | |
547 | 0)) | |
548 | return 0; | |
549 | ||
550 | num_valid = mips_linux_watch_get_num_valid (&private->watch_readback); | |
551 | ||
552 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
553 | if (mips_linux_watch_get_watchhi (&private->watch_readback, n) | |
554 | & (R_MASK | W_MASK)) | |
555 | { | |
556 | CORE_ADDR t_low, t_hi; | |
557 | int t_irw; | |
558 | struct mips_watchpoint *watch; | |
559 | ||
560 | t_low = mips_linux_watch_get_watchlo (&private->watch_readback, n); | |
561 | t_irw = t_low & IRW_MASK; | |
562 | t_hi = (mips_linux_watch_get_watchhi (&private->watch_readback, n) | |
563 | | IRW_MASK); | |
564 | t_low &= ~(CORE_ADDR)t_hi; | |
565 | ||
566 | for (watch = private->current_watches; | |
567 | watch != NULL; | |
568 | watch = watch->next) | |
569 | { | |
570 | CORE_ADDR addr = watch->addr; | |
571 | CORE_ADDR last_byte = addr + watch->len - 1; | |
572 | ||
573 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
574 | { | |
575 | /* Different type. */ | |
576 | continue; | |
577 | } | |
578 | /* Check for overlap of even a single byte. */ | |
579 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
580 | return addr; | |
581 | } | |
582 | } | |
583 | ||
584 | /* Shouldn't happen. */ | |
585 | return 0; | |
586 | } | |
587 | ||
21b0f40c DJ |
588 | /* Fetch the thread-local storage pointer for libthread_db. */ |
589 | ||
590 | ps_err_e | |
591 | ps_get_thread_area (const struct ps_prochandle *ph, | |
1b3f6016 | 592 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
593 | { |
594 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
595 | return PS_ERR; | |
596 | ||
597 | /* IDX is the bias from the thread pointer to the beginning of the | |
598 | thread descriptor. It has to be subtracted due to implementation | |
599 | quirks in libthread_db. */ | |
600 | *base = (void *) ((char *)*base - idx); | |
601 | ||
602 | return PS_OK; | |
603 | } | |
604 | ||
186947f7 DJ |
605 | #ifdef HAVE_PTRACE_GETREGS |
606 | ||
607 | static void | |
442ea881 PA |
608 | mips_collect_register (struct regcache *regcache, |
609 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
610 | { |
611 | union mips_register tmp_reg; | |
612 | ||
613 | if (use_64bit) | |
614 | { | |
442ea881 | 615 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
616 | *reg = tmp_reg; |
617 | } | |
618 | else | |
619 | { | |
442ea881 | 620 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
621 | reg->reg64 = tmp_reg.reg32; |
622 | } | |
623 | } | |
624 | ||
625 | static void | |
442ea881 PA |
626 | mips_supply_register (struct regcache *regcache, |
627 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
628 | { |
629 | int offset = 0; | |
630 | ||
631 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
632 | eight-byte slot. */ | |
633 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
634 | offset = 4; | |
635 | ||
442ea881 | 636 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
637 | } |
638 | ||
639 | static void | |
442ea881 PA |
640 | mips_collect_register_32bit (struct regcache *regcache, |
641 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
642 | { |
643 | union mips_register tmp_reg; | |
644 | int reg32; | |
645 | ||
442ea881 | 646 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
647 | reg32 = tmp_reg.reg64; |
648 | memcpy (buf, ®32, 4); | |
649 | } | |
650 | ||
651 | static void | |
442ea881 PA |
652 | mips_supply_register_32bit (struct regcache *regcache, |
653 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
654 | { |
655 | union mips_register tmp_reg; | |
656 | int reg32; | |
657 | ||
658 | memcpy (®32, buf, 4); | |
659 | tmp_reg.reg64 = reg32; | |
442ea881 | 660 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
661 | } |
662 | ||
663 | static void | |
442ea881 | 664 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 DJ |
665 | { |
666 | union mips_register *regset = buf; | |
667 | int i, use_64bit; | |
3aee8918 | 668 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 669 | |
3aee8918 | 670 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 671 | |
117ce543 | 672 | for (i = 1; i < 32; i++) |
442ea881 PA |
673 | mips_collect_register (regcache, use_64bit, i, regset + i); |
674 | ||
675 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 676 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 677 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 678 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 679 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 680 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 681 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 682 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 683 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 684 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 685 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 686 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
687 | |
688 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 689 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
690 | } |
691 | ||
692 | static void | |
442ea881 | 693 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 DJ |
694 | { |
695 | const union mips_register *regset = buf; | |
696 | int i, use_64bit; | |
697 | ||
3aee8918 | 698 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 DJ |
699 | |
700 | for (i = 0; i < 32; i++) | |
442ea881 PA |
701 | mips_supply_register (regcache, use_64bit, i, regset + i); |
702 | ||
442ea881 | 703 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
704 | find_regno (regcache->tdesc, "lo"), regset + 32); |
705 | mips_supply_register (regcache, use_64bit, | |
706 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 707 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 708 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 709 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
710 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
711 | mips_supply_register (regcache, use_64bit, | |
712 | find_regno (regcache->tdesc, "status"), regset + 36); | |
713 | mips_supply_register (regcache, use_64bit, | |
714 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
715 | |
716 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 717 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
718 | } |
719 | ||
720 | static void | |
442ea881 | 721 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 DJ |
722 | { |
723 | union mips_register *regset = buf; | |
724 | int i, use_64bit, first_fp, big_endian; | |
725 | ||
3aee8918 PA |
726 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
727 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
728 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
729 | ||
730 | /* See GDB for a discussion of this peculiar layout. */ | |
731 | for (i = 0; i < 32; i++) | |
732 | if (use_64bit) | |
442ea881 | 733 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 734 | else |
442ea881 | 735 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
736 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
737 | ||
442ea881 | 738 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
739 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
740 | mips_collect_register_32bit (regcache, use_64bit, | |
741 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
742 | regset[32].buf + 4); |
743 | } | |
744 | ||
745 | static void | |
442ea881 | 746 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 DJ |
747 | { |
748 | const union mips_register *regset = buf; | |
749 | int i, use_64bit, first_fp, big_endian; | |
750 | ||
3aee8918 PA |
751 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
752 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
753 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
754 | ||
755 | /* See GDB for a discussion of this peculiar layout. */ | |
756 | for (i = 0; i < 32; i++) | |
757 | if (use_64bit) | |
442ea881 | 758 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 759 | else |
442ea881 | 760 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
761 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
762 | ||
442ea881 | 763 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
764 | find_regno (regcache->tdesc, "fcsr"), |
765 | regset[32].buf); | |
766 | mips_supply_register_32bit (regcache, use_64bit, | |
767 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
768 | regset[32].buf + 4); |
769 | } | |
770 | #endif /* HAVE_PTRACE_GETREGS */ | |
771 | ||
3aee8918 | 772 | static struct regset_info mips_regsets[] = { |
186947f7 | 773 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 774 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 775 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 776 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
777 | mips_fill_fpregset, mips_store_fpregset }, |
778 | #endif /* HAVE_PTRACE_GETREGS */ | |
1570b33e | 779 | { 0, 0, 0, -1, -1, NULL, NULL } |
186947f7 DJ |
780 | }; |
781 | ||
3aee8918 PA |
782 | static struct regsets_info mips_regsets_info = |
783 | { | |
784 | mips_regsets, /* regsets */ | |
785 | 0, /* num_regsets */ | |
786 | NULL, /* disabled_regsets */ | |
787 | }; | |
788 | ||
789 | static struct usrregs_info mips_dsp_usrregs_info = | |
790 | { | |
791 | mips_dsp_num_regs, | |
792 | mips_dsp_regmap, | |
793 | }; | |
794 | ||
795 | static struct usrregs_info mips_usrregs_info = | |
796 | { | |
797 | mips_num_regs, | |
798 | mips_regmap, | |
799 | }; | |
800 | ||
801 | static struct regs_info dsp_regs_info = | |
802 | { | |
803 | mips_dsp_regset_bitmap, | |
804 | &mips_dsp_usrregs_info, | |
805 | &mips_regsets_info | |
806 | }; | |
807 | ||
808 | static struct regs_info regs_info = | |
809 | { | |
810 | NULL, /* regset_bitmap */ | |
811 | &mips_usrregs_info, | |
812 | &mips_regsets_info | |
813 | }; | |
814 | ||
815 | static const struct regs_info * | |
816 | mips_regs_info (void) | |
817 | { | |
818 | if (have_dsp) | |
819 | return &dsp_regs_info; | |
820 | else | |
821 | return ®s_info; | |
822 | } | |
823 | ||
2ec06d2e | 824 | struct linux_target_ops the_low_target = { |
1faeff08 | 825 | mips_arch_setup, |
3aee8918 | 826 | mips_regs_info, |
2ec06d2e DJ |
827 | mips_cannot_fetch_register, |
828 | mips_cannot_store_register, | |
c14dfd32 | 829 | NULL, /* fetch_register */ |
0d62e5e8 DJ |
830 | mips_get_pc, |
831 | mips_set_pc, | |
f450004a | 832 | (const unsigned char *) &mips_breakpoint, |
0d62e5e8 DJ |
833 | mips_breakpoint_len, |
834 | mips_reinsert_addr, | |
835 | 0, | |
836 | mips_breakpoint_at, | |
802e8e6d | 837 | mips_supports_z_point_type, |
7a60ad40 YQ |
838 | mips_insert_point, |
839 | mips_remove_point, | |
840 | mips_stopped_by_watchpoint, | |
841 | mips_stopped_data_address, | |
842 | NULL, | |
843 | NULL, | |
844 | NULL, /* siginfo_fixup */ | |
845 | mips_linux_new_process, | |
846 | mips_linux_new_thread, | |
847 | mips_linux_prepare_to_resume | |
2ec06d2e | 848 | }; |
3aee8918 PA |
849 | |
850 | void | |
851 | initialize_low_arch (void) | |
852 | { | |
853 | /* Initialize the Linux target descriptions. */ | |
854 | init_registers_mips_linux (); | |
855 | init_registers_mips_dsp_linux (); | |
856 | init_registers_mips64_linux (); | |
857 | init_registers_mips64_dsp_linux (); | |
858 | ||
859 | initialize_regsets_info (&mips_regsets_info); | |
860 | } |