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[PowerPC] Add support for PPR and DSCR
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-ppc-low.c
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
e2882c85 3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
bd64614e 31#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 32#include "ax.h"
33#include "tracepoint.h"
34
35#define PPC_FIELD(value, from, len) \
36 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
37#define PPC_SEXT(v, bs) \
38 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
39 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
40 - ((CORE_ADDR) 1 << ((bs) - 1)))
41#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
42#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
43#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
44#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 45
7ca18ed6
EBM		 46/* Holds the AT_HWCAP auxv entry. */
47
b6430ec3
UW		 48static unsigned long ppc_hwcap;
49
7ca18ed6
EBM		 50/* Holds the AT_HWCAP2 auxv entry. */
51
52static unsigned long ppc_hwcap2;
53
b6430ec3 54
7284e1be
UW		 55#define ppc_num_regs 73
56
5b0a002e
UW		 57#ifdef __powerpc64__
58/* We use a constant for FPSCR instead of PT_FPSCR, because
59 many shipped PPC64 kernels had the wrong value in ptrace.h. */
60static int ppc_regmap[] =
61 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
62 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
63 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
64 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
65 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
66 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
67 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
68 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
69 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
70 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
71 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
72 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
73 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
74 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
75 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
76 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
77 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 78 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
79 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 80#else
0a30fbc4 81/* Currently, don't check/send MQ. */
2ec06d2e 82static int ppc_regmap[] =
0a30fbc4
DJ		 83 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
84 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
85 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
86 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
87 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
88 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
89 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
90 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
91 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
92 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
93 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
94 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
95 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
96 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
97 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
98 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
99 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 100 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
101 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 102 };
103
104static int ppc_regmap_e500[] =
105 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
106 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
107 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
108 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
109 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
110 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
111 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
112 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
113 -1, -1, -1, -1,
114 -1, -1, -1, -1,
115 -1, -1, -1, -1,
116 -1, -1, -1, -1,
117 -1, -1, -1, -1,
118 -1, -1, -1, -1,
119 -1, -1, -1, -1,
120 -1, -1, -1, -1,
121 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 122 PT_CTR * 4, PT_XER * 4, -1,
123 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 124 };
5b0a002e 125#endif
0a30fbc4 126
7ca18ed6
EBM		 127/* Check whether the kernel provides a register set with number
128 REGSET_ID of size REGSETSIZE for process/thread TID. */
129
130static int
131ppc_check_regset (int tid, int regset_id, int regsetsize)
132{
133 void *buf = alloca (regsetsize);
134 struct iovec iov;
135
136 iov.iov_base = buf;
137 iov.iov_len = regsetsize;
138
139 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
140 || errno == ENODATA)
141 return 1;
142 return 0;
143}
144
2ec06d2e
DJ		 145static int
146ppc_cannot_store_register (int regno)
0a30fbc4 147{
3aee8918
PA		 148 const struct target_desc *tdesc = current_process ()->tdesc;
149
b6430ec3 150#ifndef __powerpc64__
bc1e36ca 151 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 152 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
153 && regno == find_regno (tdesc, "fpscr"))
bc1e36ca 154 return 2;
30ed0a8f 155#endif
bc1e36ca 156
7284e1be 157 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 158 if (regno == find_regno (tdesc, "orig_r3")
159 || regno == find_regno (tdesc, "trap"))
7284e1be
UW		 160 return 2;
161
0a30fbc4
DJ		 162 return 0;
163}
164
2ec06d2e
DJ		 165static int
166ppc_cannot_fetch_register (int regno)
0a30fbc4
DJ		 167{
168 return 0;
169}
170
5b0a002e 171static void
442ea881 172ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
5b0a002e 173{
76b233dd
UW		 174 memset (buf, 0, sizeof (long));
175
2e4bb98a
EBM		 176 if (__BYTE_ORDER == __LITTLE_ENDIAN)
177 {
178 /* Little-endian values always sit at the left end of the buffer. */
179 collect_register (regcache, regno, buf);
180 }
181 else if (__BYTE_ORDER == __BIG_ENDIAN)
182 {
183 /* Big-endian values sit at the right end of the buffer. In case of
184 registers whose sizes are smaller than sizeof (long), we must use a
185 padding to access them correctly. */
186 int size = register_size (regcache->tdesc, regno);
187
188 if (size < sizeof (long))
189 collect_register (regcache, regno, buf + sizeof (long) - size);
190 else
191 collect_register (regcache, regno, buf);
192 }
5b0a002e 193 else
2e4bb98a 194 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 195}
196
197static void
442ea881
PA		 198ppc_supply_ptrace_register (struct regcache *regcache,
199 int regno, const char *buf)
5b0a002e 200{
2e4bb98a
EBM		 201 if (__BYTE_ORDER == __LITTLE_ENDIAN)
202 {
203 /* Little-endian values always sit at the left end of the buffer. */
204 supply_register (regcache, regno, buf);
205 }
206 else if (__BYTE_ORDER == __BIG_ENDIAN)
207 {
208 /* Big-endian values sit at the right end of the buffer. In case of
209 registers whose sizes are smaller than sizeof (long), we must use a
210 padding to access them correctly. */
211 int size = register_size (regcache->tdesc, regno);
212
213 if (size < sizeof (long))
214 supply_register (regcache, regno, buf + sizeof (long) - size);
215 else
216 supply_register (regcache, regno, buf);
217 }
5b0a002e 218 else
2e4bb98a 219 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 220}
221
0b9ff2c0
UW		 222
223#define INSTR_SC 0x44000002
224#define NR_spu_run 0x0116
225
226/* If the PPU thread is currently stopped on a spu_run system call,
227 return to FD and ADDR the file handle and NPC parameter address
228 used with the system call. Return non-zero if successful. */
229static int
442ea881 230parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
0b9ff2c0
UW		 231{
232 CORE_ADDR curr_pc;
233 int curr_insn;
234 int curr_r0;
235
3aee8918 236 if (register_size (regcache->tdesc, 0) == 4)
0b9ff2c0
UW		 237 {
238 unsigned int pc, r0, r3, r4;
442ea881
PA		 239 collect_register_by_name (regcache, "pc", &pc);
240 collect_register_by_name (regcache, "r0", &r0);
241 collect_register_by_name (regcache, "orig_r3", &r3);
242 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 243 curr_pc = (CORE_ADDR) pc;
244 curr_r0 = (int) r0;
245 *fd = (int) r3;
246 *addr = (CORE_ADDR) r4;
247 }
248 else
249 {
250 unsigned long pc, r0, r3, r4;
442ea881
PA		 251 collect_register_by_name (regcache, "pc", &pc);
252 collect_register_by_name (regcache, "r0", &r0);
253 collect_register_by_name (regcache, "orig_r3", &r3);
254 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 255 curr_pc = (CORE_ADDR) pc;
256 curr_r0 = (int) r0;
257 *fd = (int) r3;
258 *addr = (CORE_ADDR) r4;
259 }
260
261 /* Fetch instruction preceding current NIP. */
262 if ((*the_target->read_memory) (curr_pc - 4,
263 (unsigned char *) &curr_insn, 4) != 0)
264 return 0;
265 /* It should be a "sc" instruction. */
266 if (curr_insn != INSTR_SC)
267 return 0;
268 /* System call number should be NR_spu_run. */
269 if (curr_r0 != NR_spu_run)
270 return 0;
271
272 return 1;
273}
274
0d62e5e8 275static CORE_ADDR
442ea881 276ppc_get_pc (struct regcache *regcache)
0d62e5e8 277{
0b9ff2c0
UW		 278 CORE_ADDR addr;
279 int fd;
280
442ea881 281 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 282 {
283 unsigned int pc;
284 (*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
493e2a69
MS		 285 return ((CORE_ADDR)1 << 63)
286 | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
0b9ff2c0 287 }
3aee8918 288 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 289 {
290 unsigned int pc;
442ea881 291 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 292 return (CORE_ADDR) pc;
293 }
294 else
295 {
296 unsigned long pc;
442ea881 297 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 298 return (CORE_ADDR) pc;
299 }
0d62e5e8
DJ		 300}
301
302static void
442ea881 303ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8 304{
0b9ff2c0
UW		 305 CORE_ADDR addr;
306 int fd;
307
442ea881 308 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 309 {
310 unsigned int newpc = pc;
311 (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
312 }
3aee8918 313 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 314 {
315 unsigned int newpc = pc;
442ea881 316 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 317 }
318 else
319 {
320 unsigned long newpc = pc;
442ea881 321 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 322 }
323}
324
b6430ec3
UW		 325
326static int
a2174ba4 327ppc_get_auxv (unsigned long type, unsigned long *valp)
b6430ec3 328{
3aee8918
PA		 329 const struct target_desc *tdesc = current_process ()->tdesc;
330 int wordsize = register_size (tdesc, 0);
2bc84e8a 331 unsigned char *data = (unsigned char *) alloca (2 * wordsize);
b6430ec3
UW		 332 int offset = 0;
333
334 while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
335 {
336 if (wordsize == 4)
337 {
338 unsigned int *data_p = (unsigned int *)data;
a2174ba4 339 if (data_p[0] == type)
b6430ec3
UW		 340 {
341 *valp = data_p[1];
342 return 1;
343 }
344 }
345 else
346 {
347 unsigned long *data_p = (unsigned long *)data;
a2174ba4 348 if (data_p[0] == type)
b6430ec3
UW		 349 {
350 *valp = data_p[1];
351 return 1;
352 }
353 }
354
355 offset += 2 * wordsize;
356 }
357
358 *valp = 0;
359 return 0;
360}
361
3aee8918
PA		 362#ifndef __powerpc64__
363static int ppc_regmap_adjusted;
364#endif
365
0d62e5e8 366
5b0a002e 367/* Correct in either endianness.
0d62e5e8
DJ		 368 This instruction is "twge r2, r2", which GDB uses as a software
369 breakpoint. */
5b0a002e 370static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 371#define ppc_breakpoint_len 4
372
dd373349
AT		 373/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
374
375static const gdb_byte *
376ppc_sw_breakpoint_from_kind (int kind, int *size)
377{
378 *size = ppc_breakpoint_len;
379 return (const gdb_byte *) &ppc_breakpoint;
380}
381
0d62e5e8
DJ		 382static int
383ppc_breakpoint_at (CORE_ADDR where)
384{
5b0a002e 385 unsigned int insn;
0d62e5e8 386
0b9ff2c0
UW		 387 if (where & ((CORE_ADDR)1 << 63))
388 {
389 char mem_annex[32];
390 sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
391 (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
392 NULL, where & 0xffffffff, 4);
393 if (insn == 0x3fff)
394 return 1;
395 }
396 else
397 {
398 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
399 if (insn == ppc_breakpoint)
400 return 1;
401 /* If necessary, recognize more trap instructions here. GDB only uses
402 the one. */
403 }
404
0d62e5e8
DJ		 405 return 0;
406}
407
657f9cde
WW		 408/* Implement supports_z_point_type target-ops.
409 Returns true if type Z_TYPE breakpoint is supported.
410
411 Handling software breakpoint at server side, so tracepoints
412 and breakpoints can be inserted at the same location. */
413
414static int
415ppc_supports_z_point_type (char z_type)
416{
417 switch (z_type)
418 {
419 case Z_PACKET_SW_BP:
420 return 1;
421 case Z_PACKET_HW_BP:
422 case Z_PACKET_WRITE_WP:
423 case Z_PACKET_ACCESS_WP:
424 default:
425 return 0;
426 }
427}
428
429/* Implement insert_point target-ops.
430 Returns 0 on success, -1 on failure and 1 on unsupported. */
431
432static int
433ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
434 int size, struct raw_breakpoint *bp)
435{
436 switch (type)
437 {
438 case raw_bkpt_type_sw:
439 return insert_memory_breakpoint (bp);
440
441 case raw_bkpt_type_hw:
442 case raw_bkpt_type_write_wp:
443 case raw_bkpt_type_access_wp:
444 default:
445 /* Unsupported. */
446 return 1;
447 }
448}
449
450/* Implement remove_point target-ops.
451 Returns 0 on success, -1 on failure and 1 on unsupported. */
452
453static int
454ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
455 int size, struct raw_breakpoint *bp)
456{
457 switch (type)
458 {
459 case raw_bkpt_type_sw:
460 return remove_memory_breakpoint (bp);
461
462 case raw_bkpt_type_hw:
463 case raw_bkpt_type_write_wp:
464 case raw_bkpt_type_access_wp:
465 default:
466 /* Unsupported. */
467 return 1;
468 }
469}
470
e9d25b98
DJ		 471/* Provide only a fill function for the general register set. ps_lgetregs
472 will use this for NPTL support. */
473
442ea881 474static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 475{
476 int i;
477
478 for (i = 0; i < 32; i++)
442ea881 479 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 480
481 for (i = 64; i < 70; i++)
442ea881 482 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
7284e1be
UW		 483
484 for (i = 71; i < 73; i++)
442ea881 485 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 486}
487
7ca18ed6
EBM		 488/* Program Priority Register regset fill function. */
489
490static void
491ppc_fill_pprregset (struct regcache *regcache, void *buf)
492{
493 char *ppr = (char *) buf;
494
495 collect_register_by_name (regcache, "ppr", ppr);
496}
497
498/* Program Priority Register regset store function. */
499
500static void
501ppc_store_pprregset (struct regcache *regcache, const void *buf)
502{
503 const char *ppr = (const char *) buf;
504
505 supply_register_by_name (regcache, "ppr", ppr);
506}
507
508/* Data Stream Control Register regset fill function. */
509
510static void
511ppc_fill_dscrregset (struct regcache *regcache, void *buf)
512{
513 char *dscr = (char *) buf;
514
515 collect_register_by_name (regcache, "dscr", dscr);
516}
517
518/* Data Stream Control Register regset store function. */
519
520static void
521ppc_store_dscrregset (struct regcache *regcache, const void *buf)
522{
523 const char *dscr = (const char *) buf;
524
525 supply_register_by_name (regcache, "dscr", dscr);
526}
527
677c5bb1 528static void
442ea881 529ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 530{
531 int i, base;
2bc84e8a 532 char *regset = (char *) buf;
677c5bb1 533
3aee8918 534 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 535 for (i = 0; i < 32; i++)
442ea881 536 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 537}
538
539static void
442ea881 540ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 541{
542 int i, base;
2bc84e8a 543 const char *regset = (const char *) buf;
677c5bb1 544
3aee8918 545 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 546 for (i = 0; i < 32; i++)
442ea881 547 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 548}
549
30ed0a8f 550static void
442ea881 551ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 552{
553 int i, base;
2bc84e8a 554 char *regset = (char *) buf;
1d75a658 555 int vscr_offset = 0;
30ed0a8f 556
3aee8918 557 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 558 for (i = 0; i < 32; i++)
442ea881 559 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 560
1d75a658
PFC		 561 if (__BYTE_ORDER == __BIG_ENDIAN)
562 vscr_offset = 12;
563
1d75a658
PFC		 564 collect_register_by_name (regcache, "vscr",
565 &regset[32 * 16 + vscr_offset]);
566
442ea881 567 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 568}
569
570static void
442ea881 571ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 572{
573 int i, base;
2bc84e8a 574 const char *regset = (const char *) buf;
1d75a658 575 int vscr_offset = 0;
30ed0a8f 576
3aee8918 577 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 578 for (i = 0; i < 32; i++)
442ea881 579 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 580
1d75a658
PFC		 581 if (__BYTE_ORDER == __BIG_ENDIAN)
582 vscr_offset = 12;
583
584 supply_register_by_name (regcache, "vscr",
585 &regset[32 * 16 + vscr_offset]);
442ea881 586 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 587}
588
30ed0a8f
DJ		 589struct gdb_evrregset_t
590{
591 unsigned long evr[32];
592 unsigned long long acc;
593 unsigned long spefscr;
594};
595
596static void
442ea881 597ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 598{
599 int i, ev0;
2bc84e8a 600 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 601
3aee8918 602 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 603 for (i = 0; i < 32; i++)
442ea881 604 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 605
442ea881
PA		 606 collect_register_by_name (regcache, "acc", &regset->acc);
607 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 608}
609
610static void
442ea881 611ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 612{
613 int i, ev0;
2bc84e8a 614 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 615
3aee8918 616 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 617 for (i = 0; i < 32; i++)
442ea881 618 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 619
442ea881
PA		 620 supply_register_by_name (regcache, "acc", &regset->acc);
621 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 622}
30ed0a8f 623
7d00775e
AT		 624/* Support for hardware single step. */
625
626static int
627ppc_supports_hardware_single_step (void)
628{
629 return 1;
630}
631
3aee8918 632static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 633 /* List the extra register sets before GENERAL_REGS. That way we will
634 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
635 general registers. Some kernels support these, but not the newer
636 PPC_PTRACE_GETREGS. */
7ca18ed6
EBM		 637 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
638 ppc_fill_pprregset, ppc_store_pprregset },
639 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
640 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 641 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 642 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 643 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 644 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 645 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 646 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 647 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 648 NULL_REGSET
e9d25b98
DJ		 649};
650
3aee8918
PA		 651static struct usrregs_info ppc_usrregs_info =
652 {
653 ppc_num_regs,
654 ppc_regmap,
655 };
656
657static struct regsets_info ppc_regsets_info =
658 {
659 ppc_regsets, /* regsets */
660 0, /* num_regsets */
661 NULL, /* disabled_regsets */
662 };
663
664static struct regs_info regs_info =
665 {
666 NULL, /* regset_bitmap */
667 &ppc_usrregs_info,
668 &ppc_regsets_info
669 };
670
671static const struct regs_info *
672ppc_regs_info (void)
673{
674 return &regs_info;
675}
676
e6c5bb05
SM		 677static void
678ppc_arch_setup (void)
679{
680 const struct target_desc *tdesc;
7273b5fc 681 struct regset_info *regset;
bd64614e 682 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 683
2e077f5e 684 int tid = lwpid_of (current_thread);
bd64614e 685
2e077f5e 686 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 687
bd64614e 688 if (features.wordsize == 4)
bd64614e 689 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 690 else
691 tdesc = tdesc_powerpc_64l;
692
693 current_process ()->tdesc = tdesc;
e6c5bb05 694
bd64614e
PFC		 695 /* The value of current_process ()->tdesc needs to be set for this
696 call. */
a2174ba4 697 ppc_get_auxv (AT_HWCAP, &ppc_hwcap);
7ca18ed6 698 ppc_get_auxv (AT_HWCAP2, &ppc_hwcap2);
bd64614e
PFC		 699
700 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
701
702 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
703 features.vsx = true;
704
705 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
706 features.altivec = true;
707
7ca18ed6
EBM		 708 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
709 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
710 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
711 features.ppr_dscr = true;
712
e6c5bb05 713 if (ppc_hwcap & PPC_FEATURE_CELL)
bd64614e
PFC		 714 features.cell = true;
715
716 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 717
718 /* On 32-bit machines, check for SPE registers.
719 Set the low target's regmap field as appropriately. */
720#ifndef __powerpc64__
721 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
722 tdesc = tdesc_powerpc_e500l;
723
724 if (!ppc_regmap_adjusted)
725 {
726 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
727 ppc_usrregs_info.regmap = ppc_regmap_e500;
728
729 /* If the FPSCR is 64-bit wide, we need to fetch the whole
730 64-bit slot and not just its second word. The PT_FPSCR
731 supplied in a 32-bit GDB compilation doesn't reflect
732 this. */
733 if (register_size (tdesc, 70) == 8)
734 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
735
736 ppc_regmap_adjusted = 1;
737 }
738#endif
bd64614e 739
e6c5bb05 740 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 741
742 for (regset = ppc_regsets; regset->size >= 0; regset++)
743 switch (regset->get_request)
744 {
745 case PTRACE_GETVRREGS:
d078308a 746 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 747 break;
748 case PTRACE_GETVSXREGS:
d078308a 749 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 750 break;
751 case PTRACE_GETEVRREGS:
752 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
753 regset->size = 32 * 4 + 8 + 4;
754 else
755 regset->size = 0;
756 break;
7ca18ed6
EBM		 757 case PTRACE_GETREGSET:
758 switch (regset->nt_type)
759 {
760 case NT_PPC_PPR:
761 regset->size = (features.ppr_dscr ?
762 PPC_LINUX_SIZEOF_PPRREGSET : 0);
763 break;
764 case NT_PPC_DSCR:
765 regset->size = (features.ppr_dscr ?
766 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
767 break;
768 default:
769 break;
770 }
771 break;
7273b5fc
PFC		 772 default:
773 break;
774 }
e6c5bb05
SM		 775}
776
a2174ba4
MK		 777/* Implementation of linux_target_ops method "supports_tracepoints". */
778
b04fd3be
MK		 779static int
780ppc_supports_tracepoints (void)
781{
782 return 1;
783}
784
a2174ba4
MK		 785/* Get the thread area address. This is used to recognize which
786 thread is which when tracing with the in-process agent library. We
787 don't read anything from the address, and treat it as opaque; it's
788 the address itself that we assume is unique per-thread. */
789
790static int
791ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
792{
f2907e49 793 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 794 struct thread_info *thr = get_lwp_thread (lwp);
795 struct regcache *regcache = get_thread_regcache (thr, 1);
796 ULONGEST tp = 0;
797
798#ifdef __powerpc64__
799 if (register_size (regcache->tdesc, 0) == 8)
800 collect_register_by_name (regcache, "r13", &tp);
801 else
802#endif
803 collect_register_by_name (regcache, "r2", &tp);
804
805 *addr = tp;
806
807 return 0;
808}
809
810#ifdef __powerpc64__
811
812/* Older glibc doesn't provide this. */
813
814#ifndef EF_PPC64_ABI
815#define EF_PPC64_ABI 3
816#endif
817
818/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
819 inferiors. */
820
821static int
822is_elfv2_inferior (void)
823{
824 /* To be used as fallback if we're unable to determine the right result -
825 assume inferior uses the same ABI as gdbserver. */
826#if _CALL_ELF == 2
827 const int def_res = 1;
828#else
829 const int def_res = 0;
830#endif
831 unsigned long phdr;
832 Elf64_Ehdr ehdr;
833
834 if (!ppc_get_auxv (AT_PHDR, &phdr))
835 return def_res;
836
837 /* Assume ELF header is at the beginning of the page where program headers
838 are located. If it doesn't look like one, bail. */
839
840 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
841 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
842 return def_res;
843
844 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
845}
846
847#endif
848
849/* Generate a ds-form instruction in BUF and return the number of bytes written
850
851 0 6 11 16 30 32
852 | OPCD | RST | RA | DS |XO| */
853
854__attribute__((unused)) /* Maybe unused due to conditional compilation. */
855static int
856gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
857{
858 uint32_t insn;
859
860 gdb_assert ((opcd & ~0x3f) == 0);
861 gdb_assert ((rst & ~0x1f) == 0);
862 gdb_assert ((ra & ~0x1f) == 0);
863 gdb_assert ((xo & ~0x3) == 0);
864
865 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
866 *buf = (opcd << 26) | insn;
867 return 1;
868}
869
870/* Followings are frequently used ds-form instructions. */
871
872#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
873#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
874#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
875#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
876
877/* Generate a d-form instruction in BUF.
878
879 0 6 11 16 32
880 | OPCD | RST | RA | D | */
881
882static int
883gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
884{
885 uint32_t insn;
886
887 gdb_assert ((opcd & ~0x3f) == 0);
888 gdb_assert ((rst & ~0x1f) == 0);
889 gdb_assert ((ra & ~0x1f) == 0);
890
891 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
892 *buf = (opcd << 26) | insn;
893 return 1;
894}
895
896/* Followings are frequently used d-form instructions. */
897
898#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
899#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
900#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
901#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
902#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
903#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
904#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
905#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
906#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
907
908/* Generate a xfx-form instruction in BUF and return the number of bytes
909 written.
910
911 0 6 11 21 31 32
912 | OPCD | RST | RI | XO |/| */
913
914static int
915gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
916{
917 uint32_t insn;
918 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
919
920 gdb_assert ((opcd & ~0x3f) == 0);
921 gdb_assert ((rst & ~0x1f) == 0);
922 gdb_assert ((xo & ~0x3ff) == 0);
923
924 insn = (rst << 21) | (n << 11) | (xo << 1);
925 *buf = (opcd << 26) | insn;
926 return 1;
927}
928
929/* Followings are frequently used xfx-form instructions. */
930
931#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
932#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
933#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
934#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
935#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
936 E & 0xf, 598)
937#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
938
939
940/* Generate a x-form instruction in BUF and return the number of bytes written.
941
942 0 6 11 16 21 31 32
943 | OPCD | RST | RA | RB | XO |RC| */
944
945static int
946gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
947{
948 uint32_t insn;
949
950 gdb_assert ((opcd & ~0x3f) == 0);
951 gdb_assert ((rst & ~0x1f) == 0);
952 gdb_assert ((ra & ~0x1f) == 0);
953 gdb_assert ((rb & ~0x1f) == 0);
954 gdb_assert ((xo & ~0x3ff) == 0);
955 gdb_assert ((rc & ~1) == 0);
956
957 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
958 *buf = (opcd << 26) | insn;
959 return 1;
960}
961
962/* Followings are frequently used x-form instructions. */
963
964#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
965#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
966#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
967#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
968/* Assume bf = cr7. */
969#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
970
971
972/* Generate a md-form instruction in BUF and return the number of bytes written.
973
974 0 6 11 16 21 27 30 31 32
975 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
976
977static int
978gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
979 int xo, int rc)
980{
981 uint32_t insn;
982 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
983 unsigned int sh0_4 = sh & 0x1f;
984 unsigned int sh5 = (sh >> 5) & 1;
985
986 gdb_assert ((opcd & ~0x3f) == 0);
987 gdb_assert ((rs & ~0x1f) == 0);
988 gdb_assert ((ra & ~0x1f) == 0);
989 gdb_assert ((sh & ~0x3f) == 0);
990 gdb_assert ((mb & ~0x3f) == 0);
991 gdb_assert ((xo & ~0x7) == 0);
992 gdb_assert ((rc & ~0x1) == 0);
993
994 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
995 | (sh5 << 1) | (xo << 2) | (rc & 1);
996 *buf = (opcd << 26) | insn;
997 return 1;
998}
999
1000/* The following are frequently used md-form instructions. */
1001
1002#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1003 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1004#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1005 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1006
1007/* Generate a i-form instruction in BUF and return the number of bytes written.
1008
1009 0 6 30 31 32
1010 | OPCD | LI |AA|LK| */
1011
1012static int
1013gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1014{
1015 uint32_t insn;
1016
1017 gdb_assert ((opcd & ~0x3f) == 0);
1018
1019 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1020 *buf = (opcd << 26) | insn;
1021 return 1;
1022}
1023
1024/* The following are frequently used i-form instructions. */
1025
1026#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1027#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1028
1029/* Generate a b-form instruction in BUF and return the number of bytes written.
1030
1031 0 6 11 16 30 31 32
1032 | OPCD | BO | BI | BD |AA|LK| */
1033
1034static int
1035gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1036 int aa, int lk)
1037{
1038 uint32_t insn;
1039
1040 gdb_assert ((opcd & ~0x3f) == 0);
1041 gdb_assert ((bo & ~0x1f) == 0);
1042 gdb_assert ((bi & ~0x1f) == 0);
1043
1044 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1045 *buf = (opcd << 26) | insn;
1046 return 1;
1047}
1048
1049/* The following are frequently used b-form instructions. */
1050/* Assume bi = cr7. */
1051#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1052
1053/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1054 respectively. They are primary used for save/restore GPRs in jump-pad,
1055 not used for bytecode compiling. */
1056
1057#ifdef __powerpc64__
1058#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1059 GEN_LD (buf, rt, ra, si) : \
1060 GEN_LWZ (buf, rt, ra, si))
1061#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1062 GEN_STD (buf, rt, ra, si) : \
1063 GEN_STW (buf, rt, ra, si))
1064#else
1065#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1066#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1067#endif
1068
1069/* Generate a sequence of instructions to load IMM in the register REG.
1070 Write the instructions in BUF and return the number of bytes written. */
1071
1072static int
1073gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1074{
1075 uint32_t *p = buf;
1076
1077 if ((imm + 32768) < 65536)
1078 {
1079 /* li reg, imm[15:0] */
1080 p += GEN_LI (p, reg, imm);
1081 }
1082 else if ((imm >> 32) == 0)
1083 {
1084 /* lis reg, imm[31:16]
1085 ori reg, reg, imm[15:0]
1086 rldicl reg, reg, 0, 32 */
1087 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1088 if ((imm & 0xffff) != 0)
1089 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1090 /* Clear upper 32-bit if sign-bit is set. */
1091 if (imm & (1u << 31) && is_64)
1092 p += GEN_RLDICL (p, reg, reg, 0, 32);
1093 }
1094 else
1095 {
1096 gdb_assert (is_64);
1097 /* lis reg, <imm[63:48]>
1098 ori reg, reg, <imm[48:32]>
1099 rldicr reg, reg, 32, 31
1100 oris reg, reg, <imm[31:16]>
1101 ori reg, reg, <imm[15:0]> */
1102 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1103 if (((imm >> 32) & 0xffff) != 0)
1104 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1105 p += GEN_RLDICR (p, reg, reg, 32, 31);
1106 if (((imm >> 16) & 0xffff) != 0)
1107 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1108 if ((imm & 0xffff) != 0)
1109 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1110 }
1111
1112 return p - buf;
1113}
1114
1115/* Generate a sequence for atomically exchange at location LOCK.
1116 This code sequence clobbers r6, r7, r8. LOCK is the location for
1117 the atomic-xchg, OLD_VALUE is expected old value stored in the
1118 location, and R_NEW is a register for the new value. */
1119
1120static int
1121gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1122 int is_64)
1123{
1124 const int r_lock = 6;
1125 const int r_old = 7;
1126 const int r_tmp = 8;
1127 uint32_t *p = buf;
1128
1129 /*
1130 1: lwarx TMP, 0, LOCK
1131 cmpwi TMP, OLD
1132 bne 1b
1133 stwcx. NEW, 0, LOCK
1134 bne 1b */
1135
1136 p += gen_limm (p, r_lock, lock, is_64);
1137 p += gen_limm (p, r_old, old_value, is_64);
1138
1139 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1140 p += GEN_CMPW (p, r_tmp, r_old);
1141 p += GEN_BNE (p, -8);
1142 p += GEN_STWCX (p, r_new, 0, r_lock);
1143 p += GEN_BNE (p, -16);
1144
1145 return p - buf;
1146}
1147
1148/* Generate a sequence of instructions for calling a function
1149 at address of FN. Return the number of bytes are written in BUF. */
1150
1151static int
1152gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1153{
1154 uint32_t *p = buf;
1155
1156 /* Must be called by r12 for caller to calculate TOC address. */
1157 p += gen_limm (p, 12, fn, is_64);
1158 if (is_opd)
1159 {
1160 p += GEN_LOAD (p, 11, 12, 16, is_64);
1161 p += GEN_LOAD (p, 2, 12, 8, is_64);
1162 p += GEN_LOAD (p, 12, 12, 0, is_64);
1163 }
1164 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1165 *p++ = 0x4e800421; /* bctrl */
1166
1167 return p - buf;
1168}
1169
1170/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1171 of instruction. This function is used to adjust pc-relative instructions
1172 when copying. */
1173
1174static void
1175ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1176{
1177 uint32_t insn, op6;
1178 long rel, newrel;
1179
1180 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1181 op6 = PPC_OP6 (insn);
1182
1183 if (op6 == 18 && (insn & 2) == 0)
1184 {
1185 /* branch && AA = 0 */
1186 rel = PPC_LI (insn);
1187 newrel = (oldloc - *to) + rel;
1188
1189 /* Out of range. Cannot relocate instruction. */
1190 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1191 return;
1192
1193 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1194 }
1195 else if (op6 == 16 && (insn & 2) == 0)
1196 {
1197 /* conditional branch && AA = 0 */
1198
1199 /* If the new relocation is too big for even a 26-bit unconditional
1200 branch, there is nothing we can do. Just abort.
1201
1202 Otherwise, if it can be fit in 16-bit conditional branch, just
1203 copy the instruction and relocate the address.
1204
1205 If the it's big for conditional-branch (16-bit), try to invert the
1206 condition and jump with 26-bit branch. For example,
1207
1208 beq .Lgoto
1209 INSN1
1210
1211 =>
1212
1213 bne 1f (+8)
1214 b .Lgoto
1215 1:INSN1
1216
1217 After this transform, we are actually jump from *TO+4 instead of *TO,
1218 so check the relocation again because it will be 1-insn farther then
1219 before if *TO is after OLDLOC.
1220
1221
1222 For BDNZT (or so) is transformed from
1223
1224 bdnzt eq, .Lgoto
1225 INSN1
1226
1227 =>
1228
1229 bdz 1f (+12)
1230 bf eq, 1f (+8)
1231 b .Lgoto
1232 1:INSN1
1233
1234 See also "BO field encodings". */
1235
1236 rel = PPC_BD (insn);
1237 newrel = (oldloc - *to) + rel;
1238
1239 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1240 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1241 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1242 {
1243 newrel -= 4;
1244
1245 /* Out of range. Cannot relocate instruction. */
1246 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1247 return;
1248
1249 if ((PPC_BO (insn) & 0x14) == 0x4)
1250 insn ^= (1 << 24);
1251 else if ((PPC_BO (insn) & 0x14) == 0x10)
1252 insn ^= (1 << 22);
1253
1254 /* Jump over the unconditional branch. */
1255 insn = (insn & ~0xfffc) | 0x8;
1256 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1257 *to += 4;
1258
1259 /* Build a unconditional branch and copy LK bit. */
1260 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1261 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1262 *to += 4;
1263
1264 return;
1265 }
1266 else if ((PPC_BO (insn) & 0x14) == 0)
1267 {
1268 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1269 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1270
1271 newrel -= 8;
1272
1273 /* Out of range. Cannot relocate instruction. */
1274 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1275 return;
1276
1277 /* Copy BI field. */
1278 bf_insn |= (insn & 0x1f0000);
1279
1280 /* Invert condition. */
1281 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1282 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1283
1284 write_inferior_memory (*to, (unsigned char *) &bdnz_insn, 4);
1285 *to += 4;
1286 write_inferior_memory (*to, (unsigned char *) &bf_insn, 4);
1287 *to += 4;
1288
1289 /* Build a unconditional branch and copy LK bit. */
1290 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1291 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1292 *to += 4;
1293
1294 return;
1295 }
1296 else /* (BO & 0x14) == 0x14, branch always. */
1297 {
1298 /* Out of range. Cannot relocate instruction. */
1299 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1300 return;
1301
1302 /* Build a unconditional branch and copy LK bit. */
1303 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1304 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1305 *to += 4;
1306
1307 return;
1308 }
1309 }
1310
1311 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1312 *to += 4;
1313}
1314
1315/* Implement install_fast_tracepoint_jump_pad of target_ops.
1316 See target.h for details. */
1317
1318static int
1319ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1320 CORE_ADDR collector,
1321 CORE_ADDR lockaddr,
1322 ULONGEST orig_size,
1323 CORE_ADDR *jump_entry,
1324 CORE_ADDR *trampoline,
1325 ULONGEST *trampoline_size,
1326 unsigned char *jjump_pad_insn,
1327 ULONGEST *jjump_pad_insn_size,
1328 CORE_ADDR *adjusted_insn_addr,
1329 CORE_ADDR *adjusted_insn_addr_end,
1330 char *err)
1331{
1332 uint32_t buf[256];
1333 uint32_t *p = buf;
1334 int j, offset;
1335 CORE_ADDR buildaddr = *jump_entry;
1336 const CORE_ADDR entryaddr = *jump_entry;
1337 int rsz, min_frame, frame_size, tp_reg;
1338#ifdef __powerpc64__
1339 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1340 int is_64 = register_size (regcache->tdesc, 0) == 8;
1341 int is_opd = is_64 && !is_elfv2_inferior ();
1342#else
1343 int is_64 = 0, is_opd = 0;
1344#endif
1345
1346#ifdef __powerpc64__
1347 if (is_64)
1348 {
1349 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1350 rsz = 8;
1351 min_frame = 112;
1352 frame_size = (40 * rsz) + min_frame;
1353 tp_reg = 13;
1354 }
1355 else
1356 {
1357#endif
1358 rsz = 4;
1359 min_frame = 16;
1360 frame_size = (40 * rsz) + min_frame;
1361 tp_reg = 2;
1362#ifdef __powerpc64__
1363 }
1364#endif
1365
1366 /* Stack frame layout for this jump pad,
1367
1368 High thread_area (r13/r2) |
1369 tpoint - collecting_t obj
1370 PC/<tpaddr> | +36
1371 CTR | +35
1372 LR | +34
1373 XER | +33
1374 CR | +32
1375 R31 |
1376 R29 |
1377 ... |
1378 R1 | +1
1379 R0 - collected registers
1380 ... |
1381 ... |
1382 Low Back-chain -
1383
1384
1385 The code flow of this jump pad,
1386
1387 1. Adjust SP
1388 2. Save GPR and SPR
1389 3. Prepare argument
1390 4. Call gdb_collector
1391 5. Restore GPR and SPR
1392 6. Restore SP
1393 7. Build a jump for back to the program
1394 8. Copy/relocate original instruction
1395 9. Build a jump for replacing orignal instruction. */
1396
1397 /* Adjust stack pointer. */
1398 if (is_64)
1399 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1400 else
1401 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1402
1403 /* Store GPRs. Save R1 later, because it had just been modified, but
1404 we want the original value. */
1405 for (j = 2; j < 32; j++)
1406 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1407 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1408 /* Set r0 to the original value of r1 before adjusting stack frame,
1409 and then save it. */
1410 p += GEN_ADDI (p, 0, 1, frame_size);
1411 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1412
1413 /* Save CR, XER, LR, and CTR. */
1414 p += GEN_MFCR (p, 3); /* mfcr r3 */
1415 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1416 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1417 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1418 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1419 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1420 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1421 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1422
1423 /* Save PC<tpaddr> */
1424 p += gen_limm (p, 3, tpaddr, is_64);
1425 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1426
1427
1428 /* Setup arguments to collector. */
1429 /* Set r4 to collected registers. */
1430 p += GEN_ADDI (p, 4, 1, min_frame);
1431 /* Set r3 to TPOINT. */
1432 p += gen_limm (p, 3, tpoint, is_64);
1433
1434 /* Prepare collecting_t object for lock. */
1435 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1436 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1437 /* Set R5 to collecting object. */
1438 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1439
1440 p += GEN_LWSYNC (p);
1441 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1442 p += GEN_LWSYNC (p);
1443
1444 /* Call to collector. */
1445 p += gen_call (p, collector, is_64, is_opd);
1446
1447 /* Simply write 0 to release the lock. */
1448 p += gen_limm (p, 3, lockaddr, is_64);
1449 p += gen_limm (p, 4, 0, is_64);
1450 p += GEN_LWSYNC (p);
1451 p += GEN_STORE (p, 4, 3, 0, is_64);
1452
1453 /* Restore stack and registers. */
1454 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1455 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1456 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1457 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1458 p += GEN_MTCR (p, 3); /* mtcr r3 */
1459 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1460 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1461 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1462
1463 /* Restore GPRs. */
1464 for (j = 2; j < 32; j++)
1465 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1466 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1467 /* Restore SP. */
1468 p += GEN_ADDI (p, 1, 1, frame_size);
1469
1470 /* Flush instructions to inferior memory. */
1471 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1472
1473 /* Now, insert the original instruction to execute in the jump pad. */
1474 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1475 *adjusted_insn_addr_end = *adjusted_insn_addr;
1476 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1477
1478 /* Verify the relocation size. If should be 4 for normal copy,
1479 8 or 12 for some conditional branch. */
1480 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1481 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1482 {
1483 sprintf (err, "E.Unexpected instruction length = %d"
1484 "when relocate instruction.",
1485 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1486 return 1;
1487 }
1488
1489 buildaddr = *adjusted_insn_addr_end;
1490 p = buf;
1491 /* Finally, write a jump back to the program. */
1492 offset = (tpaddr + 4) - buildaddr;
1493 if (offset >= (1 << 25) || offset < -(1 << 25))
1494 {
1495 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1496 "(offset 0x%x > 26-bit).", offset);
1497 return 1;
1498 }
1499 /* b <tpaddr+4> */
1500 p += GEN_B (p, offset);
1501 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1502 *jump_entry = buildaddr + (p - buf) * 4;
1503
1504 /* The jump pad is now built. Wire in a jump to our jump pad. This
1505 is always done last (by our caller actually), so that we can
1506 install fast tracepoints with threads running. This relies on
1507 the agent's atomic write support. */
1508 offset = entryaddr - tpaddr;
1509 if (offset >= (1 << 25) || offset < -(1 << 25))
1510 {
1511 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1512 "(offset 0x%x > 26-bit).", offset);
1513 return 1;
1514 }
1515 /* b <jentry> */
1516 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1517 *jjump_pad_insn_size = 4;
1518
1519 return 0;
1520}
1521
1522/* Returns the minimum instruction length for installing a tracepoint. */
1523
1524static int
1525ppc_get_min_fast_tracepoint_insn_len (void)
1526{
1527 return 4;
1528}
1529
14e2b6d9
MK		 1530/* Emits a given buffer into the target at current_insn_ptr. Length
1531 is in units of 32-bit words. */
1532
1533static void
1534emit_insns (uint32_t *buf, int n)
1535{
1536 n = n * sizeof (uint32_t);
1537 write_inferior_memory (current_insn_ptr, (unsigned char *) buf, n);
1538 current_insn_ptr += n;
1539}
1540
1541#define __EMIT_ASM(NAME, INSNS) \
1542 do \
1543 { \
1544 extern uint32_t start_bcax_ ## NAME []; \
1545 extern uint32_t end_bcax_ ## NAME []; \
1546 emit_insns (start_bcax_ ## NAME, \
1547 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1548 __asm__ (".section .text.__ppcbcax\n\t" \
1549 "start_bcax_" #NAME ":\n\t" \
1550 INSNS "\n\t" \
1551 "end_bcax_" #NAME ":\n\t" \
1552 ".previous\n\t"); \
1553 } while (0)
1554
1555#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1556#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1557
1558/*
1559
1560 Bytecode execution stack frame - 32-bit
1561
1562 | LR save area (SP + 4)
1563 SP' -> +- Back chain (SP + 0)
1564 | Save r31 for access saved arguments
1565 | Save r30 for bytecode stack pointer
1566 | Save r4 for incoming argument *value
1567 | Save r3 for incoming argument regs
1568 r30 -> +- Bytecode execution stack
1569 |
1570 | 64-byte (8 doublewords) at initial.
1571 | Expand stack as needed.
1572 |
1573 +-
1574 | Some padding for minimum stack frame and 16-byte alignment.
1575 | 16 bytes.
1576 SP +- Back-chain (SP')
1577
1578 initial frame size
1579 = 16 + (4 * 4) + 64
1580 = 96
1581
1582 r30 is the stack-pointer for bytecode machine.
1583 It should point to next-empty, so we can use LDU for pop.
1584 r3 is used for cache of the high part of TOP value.
1585 It was the first argument, pointer to regs.
1586 r4 is used for cache of the low part of TOP value.
1587 It was the second argument, pointer to the result.
1588 We should set *result = TOP after leaving this function.
1589
1590 Note:
1591 * To restore stack at epilogue
1592 => sp = r31
1593 * To check stack is big enough for bytecode execution.
1594 => r30 - 8 > SP + 8
1595 * To return execution result.
1596 => 0(r4) = TOP
1597
1598 */
1599
1600/* Regardless of endian, register 3 is always high part, 4 is low part.
1601 These defines are used when the register pair is stored/loaded.
1602 Likewise, to simplify code, have a similiar define for 5:6. */
1603
1604#if __BYTE_ORDER == __LITTLE_ENDIAN
1605#define TOP_FIRST "4"
1606#define TOP_SECOND "3"
1607#define TMP_FIRST "6"
1608#define TMP_SECOND "5"
1609#else
1610#define TOP_FIRST "3"
1611#define TOP_SECOND "4"
1612#define TMP_FIRST "5"
1613#define TMP_SECOND "6"
1614#endif
1615
1616/* Emit prologue in inferior memory. See above comments. */
1617
1618static void
1619ppc_emit_prologue (void)
1620{
1621 EMIT_ASM (/* Save return address. */
1622 "mflr 0 \n"
1623 "stw 0, 4(1) \n"
1624 /* Adjust SP. 96 is the initial frame size. */
1625 "stwu 1, -96(1) \n"
1626 /* Save r30 and incoming arguments. */
1627 "stw 31, 96-4(1) \n"
1628 "stw 30, 96-8(1) \n"
1629 "stw 4, 96-12(1) \n"
1630 "stw 3, 96-16(1) \n"
1631 /* Point r31 to original r1 for access arguments. */
1632 "addi 31, 1, 96 \n"
1633 /* Set r30 to pointing stack-top. */
1634 "addi 30, 1, 64 \n"
1635 /* Initial r3/TOP to 0. */
1636 "li 3, 0 \n"
1637 "li 4, 0 \n");
1638}
1639
1640/* Emit epilogue in inferior memory. See above comments. */
1641
1642static void
1643ppc_emit_epilogue (void)
1644{
1645 EMIT_ASM (/* *result = TOP */
1646 "lwz 5, -12(31) \n"
1647 "stw " TOP_FIRST ", 0(5) \n"
1648 "stw " TOP_SECOND ", 4(5) \n"
1649 /* Restore registers. */
1650 "lwz 31, -4(31) \n"
1651 "lwz 30, -8(31) \n"
1652 /* Restore SP. */
1653 "lwz 1, 0(1) \n"
1654 /* Restore LR. */
1655 "lwz 0, 4(1) \n"
1656 /* Return 0 for no-error. */
1657 "li 3, 0 \n"
1658 "mtlr 0 \n"
1659 "blr \n");
1660}
1661
1662/* TOP = stack[--sp] + TOP */
1663
1664static void
1665ppc_emit_add (void)
1666{
1667 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1668 "lwz " TMP_SECOND ", 4(30)\n"
1669 "addc 4, 6, 4 \n"
1670 "adde 3, 5, 3 \n");
1671}
1672
1673/* TOP = stack[--sp] - TOP */
1674
1675static void
1676ppc_emit_sub (void)
1677{
1678 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1679 "lwz " TMP_SECOND ", 4(30) \n"
1680 "subfc 4, 4, 6 \n"
1681 "subfe 3, 3, 5 \n");
1682}
1683
1684/* TOP = stack[--sp] * TOP */
1685
1686static void
1687ppc_emit_mul (void)
1688{
1689 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1690 "lwz " TMP_SECOND ", 4(30) \n"
1691 "mulhwu 7, 6, 4 \n"
1692 "mullw 3, 6, 3 \n"
1693 "mullw 5, 4, 5 \n"
1694 "mullw 4, 6, 4 \n"
1695 "add 3, 5, 3 \n"
1696 "add 3, 7, 3 \n");
1697}
1698
1699/* TOP = stack[--sp] << TOP */
1700
1701static void
1702ppc_emit_lsh (void)
1703{
1704 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1705 "lwz " TMP_SECOND ", 4(30) \n"
1706 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1707 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1708 "slw 5, 5, 4\n" /* Shift high part left */
1709 "slw 4, 6, 4\n" /* Shift low part left */
1710 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1711 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1712 "or 3, 5, 3\n"
1713 "or 3, 7, 3\n"); /* Assemble high part */
1714}
1715
1716/* Top = stack[--sp] >> TOP
1717 (Arithmetic shift right) */
1718
1719static void
1720ppc_emit_rsh_signed (void)
1721{
1722 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1723 "lwz " TMP_SECOND ", 4(30) \n"
1724 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1725 "sraw 3, 5, 4\n" /* Shift high part right */
1726 "cmpwi 7, 1\n"
1727 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1728 "sraw 4, 5, 7\n" /* Shift high to low */
1729 "b 2f\n"
1730 "1:\n"
1731 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1732 "srw 4, 6, 4\n" /* Shift low part right */
1733 "slw 5, 5, 7\n" /* Shift high to low */
1734 "or 4, 4, 5\n" /* Assemble low part */
1735 "2:\n");
1736}
1737
1738/* Top = stack[--sp] >> TOP
1739 (Logical shift right) */
1740
1741static void
1742ppc_emit_rsh_unsigned (void)
1743{
1744 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1745 "lwz " TMP_SECOND ", 4(30) \n"
1746 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1747 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1748 "srw 6, 6, 4\n" /* Shift low part right */
1749 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1750 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1751 "or 6, 6, 3\n"
1752 "srw 3, 5, 4\n" /* Shift high part right */
1753 "or 4, 6, 7\n"); /* Assemble low part */
1754}
1755
1756/* Emit code for signed-extension specified by ARG. */
1757
1758static void
1759ppc_emit_ext (int arg)
1760{
1761 switch (arg)
1762 {
1763 case 8:
1764 EMIT_ASM ("extsb 4, 4\n"
1765 "srawi 3, 4, 31");
1766 break;
1767 case 16:
1768 EMIT_ASM ("extsh 4, 4\n"
1769 "srawi 3, 4, 31");
1770 break;
1771 case 32:
1772 EMIT_ASM ("srawi 3, 4, 31");
1773 break;
1774 default:
1775 emit_error = 1;
1776 }
1777}
1778
1779/* Emit code for zero-extension specified by ARG. */
1780
1781static void
1782ppc_emit_zero_ext (int arg)
1783{
1784 switch (arg)
1785 {
1786 case 8:
1787 EMIT_ASM ("clrlwi 4,4,24\n"
1788 "li 3, 0\n");
1789 break;
1790 case 16:
1791 EMIT_ASM ("clrlwi 4,4,16\n"
1792 "li 3, 0\n");
1793 break;
1794 case 32:
1795 EMIT_ASM ("li 3, 0");
1796 break;
1797 default:
1798 emit_error = 1;
1799 }
1800}
1801
1802/* TOP = !TOP
1803 i.e., TOP = (TOP == 0) ? 1 : 0; */
1804
1805static void
1806ppc_emit_log_not (void)
1807{
1808 EMIT_ASM ("or 4, 3, 4 \n"
1809 "cntlzw 4, 4 \n"
1810 "srwi 4, 4, 5 \n"
1811 "li 3, 0 \n");
1812}
1813
1814/* TOP = stack[--sp] & TOP */
1815
1816static void
1817ppc_emit_bit_and (void)
1818{
1819 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1820 "lwz " TMP_SECOND ", 4(30) \n"
1821 "and 4, 6, 4 \n"
1822 "and 3, 5, 3 \n");
1823}
1824
1825/* TOP = stack[--sp] | TOP */
1826
1827static void
1828ppc_emit_bit_or (void)
1829{
1830 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1831 "lwz " TMP_SECOND ", 4(30) \n"
1832 "or 4, 6, 4 \n"
1833 "or 3, 5, 3 \n");
1834}
1835
1836/* TOP = stack[--sp] ^ TOP */
1837
1838static void
1839ppc_emit_bit_xor (void)
1840{
1841 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1842 "lwz " TMP_SECOND ", 4(30) \n"
1843 "xor 4, 6, 4 \n"
1844 "xor 3, 5, 3 \n");
1845}
1846
1847/* TOP = ~TOP
1848 i.e., TOP = ~(TOP | TOP) */
1849
1850static void
1851ppc_emit_bit_not (void)
1852{
1853 EMIT_ASM ("nor 3, 3, 3 \n"
1854 "nor 4, 4, 4 \n");
1855}
1856
1857/* TOP = stack[--sp] == TOP */
1858
1859static void
1860ppc_emit_equal (void)
1861{
1862 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1863 "lwz " TMP_SECOND ", 4(30) \n"
1864 "xor 4, 6, 4 \n"
1865 "xor 3, 5, 3 \n"
1866 "or 4, 3, 4 \n"
1867 "cntlzw 4, 4 \n"
1868 "srwi 4, 4, 5 \n"
1869 "li 3, 0 \n");
1870}
1871
1872/* TOP = stack[--sp] < TOP
1873 (Signed comparison) */
1874
1875static void
1876ppc_emit_less_signed (void)
1877{
1878 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1879 "lwz " TMP_SECOND ", 4(30) \n"
1880 "cmplw 6, 6, 4 \n"
1881 "cmpw 7, 5, 3 \n"
1882 /* CR6 bit 0 = low less and high equal */
1883 "crand 6*4+0, 6*4+0, 7*4+2\n"
1884 /* CR7 bit 0 = (low less and high equal) or high less */
1885 "cror 7*4+0, 7*4+0, 6*4+0\n"
1886 "mfcr 4 \n"
1887 "rlwinm 4, 4, 29, 31, 31 \n"
1888 "li 3, 0 \n");
1889}
1890
1891/* TOP = stack[--sp] < TOP
1892 (Unsigned comparison) */
1893
1894static void
1895ppc_emit_less_unsigned (void)
1896{
1897 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1898 "lwz " TMP_SECOND ", 4(30) \n"
1899 "cmplw 6, 6, 4 \n"
1900 "cmplw 7, 5, 3 \n"
1901 /* CR6 bit 0 = low less and high equal */
1902 "crand 6*4+0, 6*4+0, 7*4+2\n"
1903 /* CR7 bit 0 = (low less and high equal) or high less */
1904 "cror 7*4+0, 7*4+0, 6*4+0\n"
1905 "mfcr 4 \n"
1906 "rlwinm 4, 4, 29, 31, 31 \n"
1907 "li 3, 0 \n");
1908}
1909
1910/* Access the memory address in TOP in size of SIZE.
1911 Zero-extend the read value. */
1912
1913static void
1914ppc_emit_ref (int size)
1915{
1916 switch (size)
1917 {
1918 case 1:
1919 EMIT_ASM ("lbz 4, 0(4)\n"
1920 "li 3, 0");
1921 break;
1922 case 2:
1923 EMIT_ASM ("lhz 4, 0(4)\n"
1924 "li 3, 0");
1925 break;
1926 case 4:
1927 EMIT_ASM ("lwz 4, 0(4)\n"
1928 "li 3, 0");
1929 break;
1930 case 8:
1931 if (__BYTE_ORDER == __LITTLE_ENDIAN)
1932 EMIT_ASM ("lwz 3, 4(4)\n"
1933 "lwz 4, 0(4)");
1934 else
1935 EMIT_ASM ("lwz 3, 0(4)\n"
1936 "lwz 4, 4(4)");
1937 break;
1938 }
1939}
1940
1941/* TOP = NUM */
1942
1943static void
1944ppc_emit_const (LONGEST num)
1945{
1946 uint32_t buf[10];
1947 uint32_t *p = buf;
1948
1949 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
1950 p += gen_limm (p, 4, num & 0xffffffff, 0);
1951
1952 emit_insns (buf, p - buf);
1953 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
1954}
1955
1956/* Set TOP to the value of register REG by calling get_raw_reg function
1957 with two argument, collected buffer and register number. */
1958
1959static void
1960ppc_emit_reg (int reg)
1961{
1962 uint32_t buf[13];
1963 uint32_t *p = buf;
1964
1965 /* fctx->regs is passed in r3 and then saved in -16(31). */
1966 p += GEN_LWZ (p, 3, 31, -16);
1967 p += GEN_LI (p, 4, reg); /* li r4, reg */
1968 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
1969
1970 emit_insns (buf, p - buf);
1971 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
1972
1973 if (__BYTE_ORDER == __LITTLE_ENDIAN)
1974 {
1975 EMIT_ASM ("mr 5, 4\n"
1976 "mr 4, 3\n"
1977 "mr 3, 5\n");
1978 }
1979}
1980
1981/* TOP = stack[--sp] */
1982
1983static void
1984ppc_emit_pop (void)
1985{
1986 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
1987 "lwz " TOP_SECOND ", 4(30) \n");
1988}
1989
1990/* stack[sp++] = TOP
1991
1992 Because we may use up bytecode stack, expand 8 doublewords more
1993 if needed. */
1994
1995static void
1996ppc_emit_stack_flush (void)
1997{
1998 /* Make sure bytecode stack is big enough before push.
1999 Otherwise, expand 64-byte more. */
2000
2001 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2002 " stw " TOP_SECOND ", 4(30)\n"
2003 " addi 5, 30, -(8 + 8) \n"
2004 " cmpw 7, 5, 1 \n"
2005 " bgt 7, 1f \n"
2006 " stwu 31, -64(1) \n"
2007 "1:addi 30, 30, -8 \n");
2008}
2009
2010/* Swap TOP and stack[sp-1] */
2011
2012static void
2013ppc_emit_swap (void)
2014{
2015 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2016 "lwz " TMP_SECOND ", 12(30) \n"
2017 "stw " TOP_FIRST ", 8(30) \n"
2018 "stw " TOP_SECOND ", 12(30) \n"
2019 "mr 3, 5 \n"
2020 "mr 4, 6 \n");
2021}
2022
2023/* Discard N elements in the stack. Also used for ppc64. */
2024
2025static void
2026ppc_emit_stack_adjust (int n)
2027{
2028 uint32_t buf[6];
2029 uint32_t *p = buf;
2030
2031 n = n << 3;
2032 if ((n >> 15) != 0)
2033 {
2034 emit_error = 1;
2035 return;
2036 }
2037
2038 p += GEN_ADDI (p, 30, 30, n);
2039
2040 emit_insns (buf, p - buf);
2041 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2042}
2043
2044/* Call function FN. */
2045
2046static void
2047ppc_emit_call (CORE_ADDR fn)
2048{
2049 uint32_t buf[11];
2050 uint32_t *p = buf;
2051
2052 p += gen_call (p, fn, 0, 0);
2053
2054 emit_insns (buf, p - buf);
2055 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2056}
2057
2058/* FN's prototype is `LONGEST(*fn)(int)'.
2059 TOP = fn (arg1)
2060 */
2061
2062static void
2063ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2064{
2065 uint32_t buf[15];
2066 uint32_t *p = buf;
2067
2068 /* Setup argument. arg1 is a 16-bit value. */
2069 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2070 p += gen_call (p, fn, 0, 0);
2071
2072 emit_insns (buf, p - buf);
2073 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2074
2075 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2076 {
2077 EMIT_ASM ("mr 5, 4\n"
2078 "mr 4, 3\n"
2079 "mr 3, 5\n");
2080 }
2081}
2082
2083/* FN's prototype is `void(*fn)(int,LONGEST)'.
2084 fn (arg1, TOP)
2085
2086 TOP should be preserved/restored before/after the call. */
2087
2088static void
2089ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2090{
2091 uint32_t buf[21];
2092 uint32_t *p = buf;
2093
2094 /* Save TOP. 0(30) is next-empty. */
2095 p += GEN_STW (p, 3, 30, 0);
2096 p += GEN_STW (p, 4, 30, 4);
2097
2098 /* Setup argument. arg1 is a 16-bit value. */
2099 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2100 {
2101 p += GEN_MR (p, 5, 4);
2102 p += GEN_MR (p, 6, 3);
2103 }
2104 else
2105 {
2106 p += GEN_MR (p, 5, 3);
2107 p += GEN_MR (p, 6, 4);
2108 }
2109 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2110 p += gen_call (p, fn, 0, 0);
2111
2112 /* Restore TOP */
2113 p += GEN_LWZ (p, 3, 30, 0);
2114 p += GEN_LWZ (p, 4, 30, 4);
2115
2116 emit_insns (buf, p - buf);
2117 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2118}
2119
2120/* Note in the following goto ops:
2121
2122 When emitting goto, the target address is later relocated by
2123 write_goto_address. OFFSET_P is the offset of the branch instruction
2124 in the code sequence, and SIZE_P is how to relocate the instruction,
2125 recognized by ppc_write_goto_address. In current implementation,
2126 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2127 */
2128
2129/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2130
2131static void
2132ppc_emit_if_goto (int *offset_p, int *size_p)
2133{
2134 EMIT_ASM ("or. 3, 3, 4 \n"
2135 "lwzu " TOP_FIRST ", 8(30) \n"
2136 "lwz " TOP_SECOND ", 4(30) \n"
2137 "1:bne 0, 1b \n");
2138
2139 if (offset_p)
2140 *offset_p = 12;
2141 if (size_p)
2142 *size_p = 14;
2143}
2144
2145/* Unconditional goto. Also used for ppc64. */
2146
2147static void
2148ppc_emit_goto (int *offset_p, int *size_p)
2149{
2150 EMIT_ASM ("1:b 1b");
2151
2152 if (offset_p)
2153 *offset_p = 0;
2154 if (size_p)
2155 *size_p = 24;
2156}
2157
2158/* Goto if stack[--sp] == TOP */
2159
2160static void
2161ppc_emit_eq_goto (int *offset_p, int *size_p)
2162{
2163 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2164 "lwz " TMP_SECOND ", 4(30) \n"
2165 "xor 4, 6, 4 \n"
2166 "xor 3, 5, 3 \n"
2167 "or. 3, 3, 4 \n"
2168 "lwzu " TOP_FIRST ", 8(30) \n"
2169 "lwz " TOP_SECOND ", 4(30) \n"
2170 "1:beq 0, 1b \n");
2171
2172 if (offset_p)
2173 *offset_p = 28;
2174 if (size_p)
2175 *size_p = 14;
2176}
2177
2178/* Goto if stack[--sp] != TOP */
2179
2180static void
2181ppc_emit_ne_goto (int *offset_p, int *size_p)
2182{
2183 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2184 "lwz " TMP_SECOND ", 4(30) \n"
2185 "xor 4, 6, 4 \n"
2186 "xor 3, 5, 3 \n"
2187 "or. 3, 3, 4 \n"
2188 "lwzu " TOP_FIRST ", 8(30) \n"
2189 "lwz " TOP_SECOND ", 4(30) \n"
2190 "1:bne 0, 1b \n");
2191
2192 if (offset_p)
2193 *offset_p = 28;
2194 if (size_p)
2195 *size_p = 14;
2196}
2197
2198/* Goto if stack[--sp] < TOP */
2199
2200static void
2201ppc_emit_lt_goto (int *offset_p, int *size_p)
2202{
2203 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2204 "lwz " TMP_SECOND ", 4(30) \n"
2205 "cmplw 6, 6, 4 \n"
2206 "cmpw 7, 5, 3 \n"
2207 /* CR6 bit 0 = low less and high equal */
2208 "crand 6*4+0, 6*4+0, 7*4+2\n"
2209 /* CR7 bit 0 = (low less and high equal) or high less */
2210 "cror 7*4+0, 7*4+0, 6*4+0\n"
2211 "lwzu " TOP_FIRST ", 8(30) \n"
2212 "lwz " TOP_SECOND ", 4(30)\n"
2213 "1:blt 7, 1b \n");
2214
2215 if (offset_p)
2216 *offset_p = 32;
2217 if (size_p)
2218 *size_p = 14;
2219}
2220
2221/* Goto if stack[--sp] <= TOP */
2222
2223static void
2224ppc_emit_le_goto (int *offset_p, int *size_p)
2225{
2226 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2227 "lwz " TMP_SECOND ", 4(30) \n"
2228 "cmplw 6, 6, 4 \n"
2229 "cmpw 7, 5, 3 \n"
2230 /* CR6 bit 0 = low less/equal and high equal */
2231 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2232 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2233 "cror 7*4+0, 7*4+0, 6*4+0\n"
2234 "lwzu " TOP_FIRST ", 8(30) \n"
2235 "lwz " TOP_SECOND ", 4(30)\n"
2236 "1:blt 7, 1b \n");
2237
2238 if (offset_p)
2239 *offset_p = 32;
2240 if (size_p)
2241 *size_p = 14;
2242}
2243
2244/* Goto if stack[--sp] > TOP */
2245
2246static void
2247ppc_emit_gt_goto (int *offset_p, int *size_p)
2248{
2249 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2250 "lwz " TMP_SECOND ", 4(30) \n"
2251 "cmplw 6, 6, 4 \n"
2252 "cmpw 7, 5, 3 \n"
2253 /* CR6 bit 0 = low greater and high equal */
2254 "crand 6*4+0, 6*4+1, 7*4+2\n"
2255 /* CR7 bit 0 = (low greater and high equal) or high greater */
2256 "cror 7*4+0, 7*4+1, 6*4+0\n"
2257 "lwzu " TOP_FIRST ", 8(30) \n"
2258 "lwz " TOP_SECOND ", 4(30)\n"
2259 "1:blt 7, 1b \n");
2260
2261 if (offset_p)
2262 *offset_p = 32;
2263 if (size_p)
2264 *size_p = 14;
2265}
2266
2267/* Goto if stack[--sp] >= TOP */
2268
2269static void
2270ppc_emit_ge_goto (int *offset_p, int *size_p)
2271{
2272 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2273 "lwz " TMP_SECOND ", 4(30) \n"
2274 "cmplw 6, 6, 4 \n"
2275 "cmpw 7, 5, 3 \n"
2276 /* CR6 bit 0 = low ge and high equal */
2277 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2278 /* CR7 bit 0 = (low ge and high equal) or high greater */
2279 "cror 7*4+0, 7*4+1, 6*4+0\n"
2280 "lwzu " TOP_FIRST ", 8(30)\n"
2281 "lwz " TOP_SECOND ", 4(30)\n"
2282 "1:blt 7, 1b \n");
2283
2284 if (offset_p)
2285 *offset_p = 32;
2286 if (size_p)
2287 *size_p = 14;
2288}
2289
2290/* Relocate previous emitted branch instruction. FROM is the address
2291 of the branch instruction, TO is the goto target address, and SIZE
2292 if the value we set by *SIZE_P before. Currently, it is either
2293 24 or 14 of branch and conditional-branch instruction.
2294 Also used for ppc64. */
2295
2296static void
2297ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2298{
2299 long rel = to - from;
2300 uint32_t insn;
2301 int opcd;
2302
2303 read_inferior_memory (from, (unsigned char *) &insn, 4);
2304 opcd = (insn >> 26) & 0x3f;
2305
2306 switch (size)
2307 {
2308 case 14:
2309 if (opcd != 16
2310 || (rel >= (1 << 15) || rel < -(1 << 15)))
2311 emit_error = 1;
2312 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2313 break;
2314 case 24:
2315 if (opcd != 18
2316 || (rel >= (1 << 25) || rel < -(1 << 25)))
2317 emit_error = 1;
2318 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2319 break;
2320 default:
2321 emit_error = 1;
2322 }
2323
2324 if (!emit_error)
2325 write_inferior_memory (from, (unsigned char *) &insn, 4);
2326}
2327
2328/* Table of emit ops for 32-bit. */
2329
2330static struct emit_ops ppc_emit_ops_impl =
2331{
2332 ppc_emit_prologue,
2333 ppc_emit_epilogue,
2334 ppc_emit_add,
2335 ppc_emit_sub,
2336 ppc_emit_mul,
2337 ppc_emit_lsh,
2338 ppc_emit_rsh_signed,
2339 ppc_emit_rsh_unsigned,
2340 ppc_emit_ext,
2341 ppc_emit_log_not,
2342 ppc_emit_bit_and,
2343 ppc_emit_bit_or,
2344 ppc_emit_bit_xor,
2345 ppc_emit_bit_not,
2346 ppc_emit_equal,
2347 ppc_emit_less_signed,
2348 ppc_emit_less_unsigned,
2349 ppc_emit_ref,
2350 ppc_emit_if_goto,
2351 ppc_emit_goto,
2352 ppc_write_goto_address,
2353 ppc_emit_const,
2354 ppc_emit_call,
2355 ppc_emit_reg,
2356 ppc_emit_pop,
2357 ppc_emit_stack_flush,
2358 ppc_emit_zero_ext,
2359 ppc_emit_swap,
2360 ppc_emit_stack_adjust,
2361 ppc_emit_int_call_1,
2362 ppc_emit_void_call_2,
2363 ppc_emit_eq_goto,
2364 ppc_emit_ne_goto,
2365 ppc_emit_lt_goto,
2366 ppc_emit_le_goto,
2367 ppc_emit_gt_goto,
2368 ppc_emit_ge_goto
2369};
2370
2371#ifdef __powerpc64__
2372
2373/*
2374
2375 Bytecode execution stack frame - 64-bit
2376
2377 | LR save area (SP + 16)
2378 | CR save area (SP + 8)
2379 SP' -> +- Back chain (SP + 0)
2380 | Save r31 for access saved arguments
2381 | Save r30 for bytecode stack pointer
2382 | Save r4 for incoming argument *value
2383 | Save r3 for incoming argument regs
2384 r30 -> +- Bytecode execution stack
2385 |
2386 | 64-byte (8 doublewords) at initial.
2387 | Expand stack as needed.
2388 |
2389 +-
2390 | Some padding for minimum stack frame.
2391 | 112 for ELFv1.
2392 SP +- Back-chain (SP')
2393
2394 initial frame size
2395 = 112 + (4 * 8) + 64
2396 = 208
2397
2398 r30 is the stack-pointer for bytecode machine.
2399 It should point to next-empty, so we can use LDU for pop.
2400 r3 is used for cache of TOP value.
2401 It was the first argument, pointer to regs.
2402 r4 is the second argument, pointer to the result.
2403 We should set *result = TOP after leaving this function.
2404
2405 Note:
2406 * To restore stack at epilogue
2407 => sp = r31
2408 * To check stack is big enough for bytecode execution.
2409 => r30 - 8 > SP + 112
2410 * To return execution result.
2411 => 0(r4) = TOP
2412
2413 */
2414
2415/* Emit prologue in inferior memory. See above comments. */
2416
2417static void
2418ppc64v1_emit_prologue (void)
2419{
2420 /* On ELFv1, function pointers really point to function descriptor,
2421 so emit one here. We don't care about contents of words 1 and 2,
2422 so let them just overlap out code. */
2423 uint64_t opd = current_insn_ptr + 8;
2424 uint32_t buf[2];
2425
2426 /* Mind the strict aliasing rules. */
2427 memcpy (buf, &opd, sizeof buf);
2428 emit_insns(buf, 2);
2429 EMIT_ASM (/* Save return address. */
2430 "mflr 0 \n"
2431 "std 0, 16(1) \n"
2432 /* Save r30 and incoming arguments. */
2433 "std 31, -8(1) \n"
2434 "std 30, -16(1) \n"
2435 "std 4, -24(1) \n"
2436 "std 3, -32(1) \n"
2437 /* Point r31 to current r1 for access arguments. */
2438 "mr 31, 1 \n"
2439 /* Adjust SP. 208 is the initial frame size. */
2440 "stdu 1, -208(1) \n"
2441 /* Set r30 to pointing stack-top. */
2442 "addi 30, 1, 168 \n"
2443 /* Initial r3/TOP to 0. */
2444 "li 3, 0 \n");
2445}
2446
2447/* Emit prologue in inferior memory. See above comments. */
2448
2449static void
2450ppc64v2_emit_prologue (void)
2451{
2452 EMIT_ASM (/* Save return address. */
2453 "mflr 0 \n"
2454 "std 0, 16(1) \n"
2455 /* Save r30 and incoming arguments. */
2456 "std 31, -8(1) \n"
2457 "std 30, -16(1) \n"
2458 "std 4, -24(1) \n"
2459 "std 3, -32(1) \n"
2460 /* Point r31 to current r1 for access arguments. */
2461 "mr 31, 1 \n"
2462 /* Adjust SP. 208 is the initial frame size. */
2463 "stdu 1, -208(1) \n"
2464 /* Set r30 to pointing stack-top. */
2465 "addi 30, 1, 168 \n"
2466 /* Initial r3/TOP to 0. */
2467 "li 3, 0 \n");
2468}
2469
2470/* Emit epilogue in inferior memory. See above comments. */
2471
2472static void
2473ppc64_emit_epilogue (void)
2474{
2475 EMIT_ASM (/* Restore SP. */
2476 "ld 1, 0(1) \n"
2477 /* *result = TOP */
2478 "ld 4, -24(1) \n"
2479 "std 3, 0(4) \n"
2480 /* Restore registers. */
2481 "ld 31, -8(1) \n"
2482 "ld 30, -16(1) \n"
2483 /* Restore LR. */
2484 "ld 0, 16(1) \n"
2485 /* Return 0 for no-error. */
2486 "li 3, 0 \n"
2487 "mtlr 0 \n"
2488 "blr \n");
2489}
2490
2491/* TOP = stack[--sp] + TOP */
2492
2493static void
2494ppc64_emit_add (void)
2495{
2496 EMIT_ASM ("ldu 4, 8(30) \n"
2497 "add 3, 4, 3 \n");
2498}
2499
2500/* TOP = stack[--sp] - TOP */
2501
2502static void
2503ppc64_emit_sub (void)
2504{
2505 EMIT_ASM ("ldu 4, 8(30) \n"
2506 "sub 3, 4, 3 \n");
2507}
2508
2509/* TOP = stack[--sp] * TOP */
2510
2511static void
2512ppc64_emit_mul (void)
2513{
2514 EMIT_ASM ("ldu 4, 8(30) \n"
2515 "mulld 3, 4, 3 \n");
2516}
2517
2518/* TOP = stack[--sp] << TOP */
2519
2520static void
2521ppc64_emit_lsh (void)
2522{
2523 EMIT_ASM ("ldu 4, 8(30) \n"
2524 "sld 3, 4, 3 \n");
2525}
2526
2527/* Top = stack[--sp] >> TOP
2528 (Arithmetic shift right) */
2529
2530static void
2531ppc64_emit_rsh_signed (void)
2532{
2533 EMIT_ASM ("ldu 4, 8(30) \n"
2534 "srad 3, 4, 3 \n");
2535}
2536
2537/* Top = stack[--sp] >> TOP
2538 (Logical shift right) */
2539
2540static void
2541ppc64_emit_rsh_unsigned (void)
2542{
2543 EMIT_ASM ("ldu 4, 8(30) \n"
2544 "srd 3, 4, 3 \n");
2545}
2546
2547/* Emit code for signed-extension specified by ARG. */
2548
2549static void
2550ppc64_emit_ext (int arg)
2551{
2552 switch (arg)
2553 {
2554 case 8:
2555 EMIT_ASM ("extsb 3, 3");
2556 break;
2557 case 16:
2558 EMIT_ASM ("extsh 3, 3");
2559 break;
2560 case 32:
2561 EMIT_ASM ("extsw 3, 3");
2562 break;
2563 default:
2564 emit_error = 1;
2565 }
2566}
2567
2568/* Emit code for zero-extension specified by ARG. */
2569
2570static void
2571ppc64_emit_zero_ext (int arg)
2572{
2573 switch (arg)
2574 {
2575 case 8:
2576 EMIT_ASM ("rldicl 3,3,0,56");
2577 break;
2578 case 16:
2579 EMIT_ASM ("rldicl 3,3,0,48");
2580 break;
2581 case 32:
2582 EMIT_ASM ("rldicl 3,3,0,32");
2583 break;
2584 default:
2585 emit_error = 1;
2586 }
2587}
2588
2589/* TOP = !TOP
2590 i.e., TOP = (TOP == 0) ? 1 : 0; */
2591
2592static void
2593ppc64_emit_log_not (void)
2594{
2595 EMIT_ASM ("cntlzd 3, 3 \n"
2596 "srdi 3, 3, 6 \n");
2597}
2598
2599/* TOP = stack[--sp] & TOP */
2600
2601static void
2602ppc64_emit_bit_and (void)
2603{
2604 EMIT_ASM ("ldu 4, 8(30) \n"
2605 "and 3, 4, 3 \n");
2606}
2607
2608/* TOP = stack[--sp] | TOP */
2609
2610static void
2611ppc64_emit_bit_or (void)
2612{
2613 EMIT_ASM ("ldu 4, 8(30) \n"
2614 "or 3, 4, 3 \n");
2615}
2616
2617/* TOP = stack[--sp] ^ TOP */
2618
2619static void
2620ppc64_emit_bit_xor (void)
2621{
2622 EMIT_ASM ("ldu 4, 8(30) \n"
2623 "xor 3, 4, 3 \n");
2624}
2625
2626/* TOP = ~TOP
2627 i.e., TOP = ~(TOP | TOP) */
2628
2629static void
2630ppc64_emit_bit_not (void)
2631{
2632 EMIT_ASM ("nor 3, 3, 3 \n");
2633}
2634
2635/* TOP = stack[--sp] == TOP */
2636
2637static void
2638ppc64_emit_equal (void)
2639{
2640 EMIT_ASM ("ldu 4, 8(30) \n"
2641 "xor 3, 3, 4 \n"
2642 "cntlzd 3, 3 \n"
2643 "srdi 3, 3, 6 \n");
2644}
2645
2646/* TOP = stack[--sp] < TOP
2647 (Signed comparison) */
2648
2649static void
2650ppc64_emit_less_signed (void)
2651{
2652 EMIT_ASM ("ldu 4, 8(30) \n"
2653 "cmpd 7, 4, 3 \n"
2654 "mfcr 3 \n"
2655 "rlwinm 3, 3, 29, 31, 31 \n");
2656}
2657
2658/* TOP = stack[--sp] < TOP
2659 (Unsigned comparison) */
2660
2661static void
2662ppc64_emit_less_unsigned (void)
2663{
2664 EMIT_ASM ("ldu 4, 8(30) \n"
2665 "cmpld 7, 4, 3 \n"
2666 "mfcr 3 \n"
2667 "rlwinm 3, 3, 29, 31, 31 \n");
2668}
2669
2670/* Access the memory address in TOP in size of SIZE.
2671 Zero-extend the read value. */
2672
2673static void
2674ppc64_emit_ref (int size)
2675{
2676 switch (size)
2677 {
2678 case 1:
2679 EMIT_ASM ("lbz 3, 0(3)");
2680 break;
2681 case 2:
2682 EMIT_ASM ("lhz 3, 0(3)");
2683 break;
2684 case 4:
2685 EMIT_ASM ("lwz 3, 0(3)");
2686 break;
2687 case 8:
2688 EMIT_ASM ("ld 3, 0(3)");
2689 break;
2690 }
2691}
2692
2693/* TOP = NUM */
2694
2695static void
2696ppc64_emit_const (LONGEST num)
2697{
2698 uint32_t buf[5];
2699 uint32_t *p = buf;
2700
2701 p += gen_limm (p, 3, num, 1);
2702
2703 emit_insns (buf, p - buf);
2704 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2705}
2706
2707/* Set TOP to the value of register REG by calling get_raw_reg function
2708 with two argument, collected buffer and register number. */
2709
2710static void
2711ppc64v1_emit_reg (int reg)
2712{
2713 uint32_t buf[15];
2714 uint32_t *p = buf;
2715
2716 /* fctx->regs is passed in r3 and then saved in 176(1). */
2717 p += GEN_LD (p, 3, 31, -32);
2718 p += GEN_LI (p, 4, reg);
2719 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2720 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
2721 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2722
2723 emit_insns (buf, p - buf);
2724 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2725}
2726
2727/* Likewise, for ELFv2. */
2728
2729static void
2730ppc64v2_emit_reg (int reg)
2731{
2732 uint32_t buf[12];
2733 uint32_t *p = buf;
2734
2735 /* fctx->regs is passed in r3 and then saved in 176(1). */
2736 p += GEN_LD (p, 3, 31, -32);
2737 p += GEN_LI (p, 4, reg);
2738 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2739 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
2740 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2741
2742 emit_insns (buf, p - buf);
2743 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2744}
2745
2746/* TOP = stack[--sp] */
2747
2748static void
2749ppc64_emit_pop (void)
2750{
2751 EMIT_ASM ("ldu 3, 8(30)");
2752}
2753
2754/* stack[sp++] = TOP
2755
2756 Because we may use up bytecode stack, expand 8 doublewords more
2757 if needed. */
2758
2759static void
2760ppc64_emit_stack_flush (void)
2761{
2762 /* Make sure bytecode stack is big enough before push.
2763 Otherwise, expand 64-byte more. */
2764
2765 EMIT_ASM (" std 3, 0(30) \n"
2766 " addi 4, 30, -(112 + 8) \n"
2767 " cmpd 7, 4, 1 \n"
2768 " bgt 7, 1f \n"
2769 " stdu 31, -64(1) \n"
2770 "1:addi 30, 30, -8 \n");
2771}
2772
2773/* Swap TOP and stack[sp-1] */
2774
2775static void
2776ppc64_emit_swap (void)
2777{
2778 EMIT_ASM ("ld 4, 8(30) \n"
2779 "std 3, 8(30) \n"
2780 "mr 3, 4 \n");
2781}
2782
2783/* Call function FN - ELFv1. */
2784
2785static void
2786ppc64v1_emit_call (CORE_ADDR fn)
2787{
2788 uint32_t buf[13];
2789 uint32_t *p = buf;
2790
2791 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2792 p += gen_call (p, fn, 1, 1);
2793 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2794
2795 emit_insns (buf, p - buf);
2796 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2797}
2798
2799/* Call function FN - ELFv2. */
2800
2801static void
2802ppc64v2_emit_call (CORE_ADDR fn)
2803{
2804 uint32_t buf[10];
2805 uint32_t *p = buf;
2806
2807 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2808 p += gen_call (p, fn, 1, 0);
2809 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2810
2811 emit_insns (buf, p - buf);
2812 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2813}
2814
2815/* FN's prototype is `LONGEST(*fn)(int)'.
2816 TOP = fn (arg1)
2817 */
2818
2819static void
2820ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
2821{
2822 uint32_t buf[13];
2823 uint32_t *p = buf;
2824
2825 /* Setup argument. arg1 is a 16-bit value. */
2826 p += gen_limm (p, 3, arg1, 1);
2827 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2828 p += gen_call (p, fn, 1, 1);
2829 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2830
2831 emit_insns (buf, p - buf);
2832 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2833}
2834
2835/* Likewise for ELFv2. */
2836
2837static void
2838ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
2839{
2840 uint32_t buf[10];
2841 uint32_t *p = buf;
2842
2843 /* Setup argument. arg1 is a 16-bit value. */
2844 p += gen_limm (p, 3, arg1, 1);
2845 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2846 p += gen_call (p, fn, 1, 0);
2847 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2848
2849 emit_insns (buf, p - buf);
2850 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2851}
2852
2853/* FN's prototype is `void(*fn)(int,LONGEST)'.
2854 fn (arg1, TOP)
2855
2856 TOP should be preserved/restored before/after the call. */
2857
2858static void
2859ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
2860{
2861 uint32_t buf[17];
2862 uint32_t *p = buf;
2863
2864 /* Save TOP. 0(30) is next-empty. */
2865 p += GEN_STD (p, 3, 30, 0);
2866
2867 /* Setup argument. arg1 is a 16-bit value. */
2868 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
2869 p += gen_limm (p, 3, arg1, 1);
2870 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2871 p += gen_call (p, fn, 1, 1);
2872 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2873
2874 /* Restore TOP */
2875 p += GEN_LD (p, 3, 30, 0);
2876
2877 emit_insns (buf, p - buf);
2878 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2879}
2880
2881/* Likewise for ELFv2. */
2882
2883static void
2884ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
2885{
2886 uint32_t buf[14];
2887 uint32_t *p = buf;
2888
2889 /* Save TOP. 0(30) is next-empty. */
2890 p += GEN_STD (p, 3, 30, 0);
2891
2892 /* Setup argument. arg1 is a 16-bit value. */
2893 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
2894 p += gen_limm (p, 3, arg1, 1);
2895 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2896 p += gen_call (p, fn, 1, 0);
2897 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2898
2899 /* Restore TOP */
2900 p += GEN_LD (p, 3, 30, 0);
2901
2902 emit_insns (buf, p - buf);
2903 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2904}
2905
2906/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2907
2908static void
2909ppc64_emit_if_goto (int *offset_p, int *size_p)
2910{
2911 EMIT_ASM ("cmpdi 7, 3, 0 \n"
2912 "ldu 3, 8(30) \n"
2913 "1:bne 7, 1b \n");
2914
2915 if (offset_p)
2916 *offset_p = 8;
2917 if (size_p)
2918 *size_p = 14;
2919}
2920
2921/* Goto if stack[--sp] == TOP */
2922
2923static void
2924ppc64_emit_eq_goto (int *offset_p, int *size_p)
2925{
2926 EMIT_ASM ("ldu 4, 8(30) \n"
2927 "cmpd 7, 4, 3 \n"
2928 "ldu 3, 8(30) \n"
2929 "1:beq 7, 1b \n");
2930
2931 if (offset_p)
2932 *offset_p = 12;
2933 if (size_p)
2934 *size_p = 14;
2935}
2936
2937/* Goto if stack[--sp] != TOP */
2938
2939static void
2940ppc64_emit_ne_goto (int *offset_p, int *size_p)
2941{
2942 EMIT_ASM ("ldu 4, 8(30) \n"
2943 "cmpd 7, 4, 3 \n"
2944 "ldu 3, 8(30) \n"
2945 "1:bne 7, 1b \n");
2946
2947 if (offset_p)
2948 *offset_p = 12;
2949 if (size_p)
2950 *size_p = 14;
2951}
2952
2953/* Goto if stack[--sp] < TOP */
2954
2955static void
2956ppc64_emit_lt_goto (int *offset_p, int *size_p)
2957{
2958 EMIT_ASM ("ldu 4, 8(30) \n"
2959 "cmpd 7, 4, 3 \n"
2960 "ldu 3, 8(30) \n"
2961 "1:blt 7, 1b \n");
2962
2963 if (offset_p)
2964 *offset_p = 12;
2965 if (size_p)
2966 *size_p = 14;
2967}
2968
2969/* Goto if stack[--sp] <= TOP */
2970
2971static void
2972ppc64_emit_le_goto (int *offset_p, int *size_p)
2973{
2974 EMIT_ASM ("ldu 4, 8(30) \n"
2975 "cmpd 7, 4, 3 \n"
2976 "ldu 3, 8(30) \n"
2977 "1:ble 7, 1b \n");
2978
2979 if (offset_p)
2980 *offset_p = 12;
2981 if (size_p)
2982 *size_p = 14;
2983}
2984
2985/* Goto if stack[--sp] > TOP */
2986
2987static void
2988ppc64_emit_gt_goto (int *offset_p, int *size_p)
2989{
2990 EMIT_ASM ("ldu 4, 8(30) \n"
2991 "cmpd 7, 4, 3 \n"
2992 "ldu 3, 8(30) \n"
2993 "1:bgt 7, 1b \n");
2994
2995 if (offset_p)
2996 *offset_p = 12;
2997 if (size_p)
2998 *size_p = 14;
2999}
3000
3001/* Goto if stack[--sp] >= TOP */
3002
3003static void
3004ppc64_emit_ge_goto (int *offset_p, int *size_p)
3005{
3006 EMIT_ASM ("ldu 4, 8(30) \n"
3007 "cmpd 7, 4, 3 \n"
3008 "ldu 3, 8(30) \n"
3009 "1:bge 7, 1b \n");
3010
3011 if (offset_p)
3012 *offset_p = 12;
3013 if (size_p)
3014 *size_p = 14;
3015}
3016
3017/* Table of emit ops for 64-bit ELFv1. */
3018
3019static struct emit_ops ppc64v1_emit_ops_impl =
3020{
3021 ppc64v1_emit_prologue,
3022 ppc64_emit_epilogue,
3023 ppc64_emit_add,
3024 ppc64_emit_sub,
3025 ppc64_emit_mul,
3026 ppc64_emit_lsh,
3027 ppc64_emit_rsh_signed,
3028 ppc64_emit_rsh_unsigned,
3029 ppc64_emit_ext,
3030 ppc64_emit_log_not,
3031 ppc64_emit_bit_and,
3032 ppc64_emit_bit_or,
3033 ppc64_emit_bit_xor,
3034 ppc64_emit_bit_not,
3035 ppc64_emit_equal,
3036 ppc64_emit_less_signed,
3037 ppc64_emit_less_unsigned,
3038 ppc64_emit_ref,
3039 ppc64_emit_if_goto,
3040 ppc_emit_goto,
3041 ppc_write_goto_address,
3042 ppc64_emit_const,
3043 ppc64v1_emit_call,
3044 ppc64v1_emit_reg,
3045 ppc64_emit_pop,
3046 ppc64_emit_stack_flush,
3047 ppc64_emit_zero_ext,
3048 ppc64_emit_swap,
3049 ppc_emit_stack_adjust,
3050 ppc64v1_emit_int_call_1,
3051 ppc64v1_emit_void_call_2,
3052 ppc64_emit_eq_goto,
3053 ppc64_emit_ne_goto,
3054 ppc64_emit_lt_goto,
3055 ppc64_emit_le_goto,
3056 ppc64_emit_gt_goto,
3057 ppc64_emit_ge_goto
3058};
3059
3060/* Table of emit ops for 64-bit ELFv2. */
3061
3062static struct emit_ops ppc64v2_emit_ops_impl =
3063{
3064 ppc64v2_emit_prologue,
3065 ppc64_emit_epilogue,
3066 ppc64_emit_add,
3067 ppc64_emit_sub,
3068 ppc64_emit_mul,
3069 ppc64_emit_lsh,
3070 ppc64_emit_rsh_signed,
3071 ppc64_emit_rsh_unsigned,
3072 ppc64_emit_ext,
3073 ppc64_emit_log_not,
3074 ppc64_emit_bit_and,
3075 ppc64_emit_bit_or,
3076 ppc64_emit_bit_xor,
3077 ppc64_emit_bit_not,
3078 ppc64_emit_equal,
3079 ppc64_emit_less_signed,
3080 ppc64_emit_less_unsigned,
3081 ppc64_emit_ref,
3082 ppc64_emit_if_goto,
3083 ppc_emit_goto,
3084 ppc_write_goto_address,
3085 ppc64_emit_const,
3086 ppc64v2_emit_call,
3087 ppc64v2_emit_reg,
3088 ppc64_emit_pop,
3089 ppc64_emit_stack_flush,
3090 ppc64_emit_zero_ext,
3091 ppc64_emit_swap,
3092 ppc_emit_stack_adjust,
3093 ppc64v2_emit_int_call_1,
3094 ppc64v2_emit_void_call_2,
3095 ppc64_emit_eq_goto,
3096 ppc64_emit_ne_goto,
3097 ppc64_emit_lt_goto,
3098 ppc64_emit_le_goto,
3099 ppc64_emit_gt_goto,
3100 ppc64_emit_ge_goto
3101};
3102
3103#endif
3104
3105/* Implementation of linux_target_ops method "emit_ops". */
3106
3107static struct emit_ops *
3108ppc_emit_ops (void)
3109{
3110#ifdef __powerpc64__
3111 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3112
3113 if (register_size (regcache->tdesc, 0) == 8)
3114 {
3115 if (is_elfv2_inferior ())
3116 return &ppc64v2_emit_ops_impl;
3117 else
3118 return &ppc64v1_emit_ops_impl;
3119 }
3120#endif
3121 return &ppc_emit_ops_impl;
3122}
3123
a2174ba4
MK		 3124/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3125
3126static int
3127ppc_get_ipa_tdesc_idx (void)
3128{
3129 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3130 const struct target_desc *tdesc = regcache->tdesc;
3131
3132#ifdef __powerpc64__
3133 if (tdesc == tdesc_powerpc_64l)
3134 return PPC_TDESC_BASE;
3135 if (tdesc == tdesc_powerpc_altivec64l)
3136 return PPC_TDESC_ALTIVEC;
3137 if (tdesc == tdesc_powerpc_cell64l)
3138 return PPC_TDESC_CELL;
3139 if (tdesc == tdesc_powerpc_vsx64l)
3140 return PPC_TDESC_VSX;
3141 if (tdesc == tdesc_powerpc_isa205_64l)
3142 return PPC_TDESC_ISA205;
3143 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3144 return PPC_TDESC_ISA205_ALTIVEC;
3145 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3146 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3147 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3148 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
a2174ba4
MK		 3149#endif
3150
3151 if (tdesc == tdesc_powerpc_32l)
3152 return PPC_TDESC_BASE;
3153 if (tdesc == tdesc_powerpc_altivec32l)
3154 return PPC_TDESC_ALTIVEC;
3155 if (tdesc == tdesc_powerpc_cell32l)
3156 return PPC_TDESC_CELL;
3157 if (tdesc == tdesc_powerpc_vsx32l)
3158 return PPC_TDESC_VSX;
3159 if (tdesc == tdesc_powerpc_isa205_32l)
3160 return PPC_TDESC_ISA205;
3161 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3162 return PPC_TDESC_ISA205_ALTIVEC;
3163 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3164 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3165 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3166 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
a2174ba4
MK		 3167 if (tdesc == tdesc_powerpc_e500l)
3168 return PPC_TDESC_E500;
3169
3170 return 0;
3171}
3172
2ec06d2e 3173struct linux_target_ops the_low_target = {
6fe305f7 3174 ppc_arch_setup,
3aee8918 3175 ppc_regs_info,
2ec06d2e
DJ		 3176 ppc_cannot_fetch_register,
3177 ppc_cannot_store_register,
c14dfd32 3178 NULL, /* fetch_register */
0d62e5e8
DJ		 3179 ppc_get_pc,
3180 ppc_set_pc,
dd373349
AT		 3181 NULL, /* breakpoint_kind_from_pc */
3182 ppc_sw_breakpoint_from_kind,
0d62e5e8
DJ		 3183 NULL,
3184 0,
3185 ppc_breakpoint_at,
657f9cde
WW		 3186 ppc_supports_z_point_type,
3187 ppc_insert_point,
3188 ppc_remove_point,
5b0a002e
UW		 3189 NULL,
3190 NULL,
3191 ppc_collect_ptrace_register,
3192 ppc_supply_ptrace_register,
7d00775e
AT		 3193 NULL, /* siginfo_fixup */
3194 NULL, /* new_process */
04ec7890 3195 NULL, /* delete_process */
7d00775e 3196 NULL, /* new_thread */
466eecee 3197 NULL, /* delete_thread */
7d00775e
AT		 3198 NULL, /* new_fork */
3199 NULL, /* prepare_to_resume */
3200 NULL, /* process_qsupported */
b04fd3be 3201 ppc_supports_tracepoints,
a2174ba4
MK		 3202 ppc_get_thread_area,
3203 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3204 ppc_emit_ops,
a2174ba4 3205 ppc_get_min_fast_tracepoint_insn_len,
7d00775e
AT		 3206 NULL, /* supports_range_stepping */
3207 NULL, /* breakpoint_kind_from_current_state */
3208 ppc_supports_hardware_single_step,
a2174ba4
MK		 3209 NULL, /* get_syscall_trapinfo */
3210 ppc_get_ipa_tdesc_idx,
2ec06d2e 3211};
3aee8918
PA		 3212
3213void
3214initialize_low_arch (void)
3215{
3216 /* Initialize the Linux target descriptions. */
3217
3218 init_registers_powerpc_32l ();
3219 init_registers_powerpc_altivec32l ();
3220 init_registers_powerpc_cell32l ();
3221 init_registers_powerpc_vsx32l ();
3222 init_registers_powerpc_isa205_32l ();
3223 init_registers_powerpc_isa205_altivec32l ();
3224 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3225 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3aee8918 3226 init_registers_powerpc_e500l ();
a2174ba4 3227#if __powerpc64__
3aee8918
PA		 3228 init_registers_powerpc_64l ();
3229 init_registers_powerpc_altivec64l ();
3230 init_registers_powerpc_cell64l ();
3231 init_registers_powerpc_vsx64l ();
3232 init_registers_powerpc_isa205_64l ();
3233 init_registers_powerpc_isa205_altivec64l ();
3234 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3235 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
a2174ba4 3236#endif
3aee8918
PA		 3237
3238 initialize_regsets_info (&ppc_regsets_info);
3239}
GDB Binutils - Deliverables
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