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[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-ppc-low.c
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
42a4f53d 3 Copyright (C) 1995-2019 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
64f57f3d 31#include "nat/linux-ptrace.h"
bd64614e 32#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 33#include "ax.h"
34#include "tracepoint.h"
35
36#define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38#define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 46
7ca18ed6
EBM		 47/* Holds the AT_HWCAP auxv entry. */
48
b6430ec3
UW		 49static unsigned long ppc_hwcap;
50
7ca18ed6
EBM		 51/* Holds the AT_HWCAP2 auxv entry. */
52
53static unsigned long ppc_hwcap2;
54
b6430ec3 55
7284e1be
UW		 56#define ppc_num_regs 73
57
5b0a002e
UW		 58#ifdef __powerpc64__
59/* We use a constant for FPSCR instead of PT_FPSCR, because
60 many shipped PPC64 kernels had the wrong value in ptrace.h. */
61static int ppc_regmap[] =
62 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
63 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
64 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
65 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
66 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
67 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
68 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
69 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
70 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
71 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
72 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
73 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
74 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
75 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
76 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
77 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
78 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 79 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
80 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 81#else
0a30fbc4 82/* Currently, don't check/send MQ. */
2ec06d2e 83static int ppc_regmap[] =
0a30fbc4
DJ		 84 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
85 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
86 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
87 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
88 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
89 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
90 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
91 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
92 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
93 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
94 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
95 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
96 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
97 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
98 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
99 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
100 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 101 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
102 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 103 };
104
105static int ppc_regmap_e500[] =
106 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
107 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
108 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
109 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
110 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
111 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
112 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
113 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
114 -1, -1, -1, -1,
115 -1, -1, -1, -1,
116 -1, -1, -1, -1,
117 -1, -1, -1, -1,
118 -1, -1, -1, -1,
119 -1, -1, -1, -1,
120 -1, -1, -1, -1,
121 -1, -1, -1, -1,
122 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 123 PT_CTR * 4, PT_XER * 4, -1,
124 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 125 };
5b0a002e 126#endif
0a30fbc4 127
7ca18ed6
EBM		 128/* Check whether the kernel provides a register set with number
129 REGSET_ID of size REGSETSIZE for process/thread TID. */
130
131static int
132ppc_check_regset (int tid, int regset_id, int regsetsize)
133{
134 void *buf = alloca (regsetsize);
135 struct iovec iov;
136
137 iov.iov_base = buf;
138 iov.iov_len = regsetsize;
139
140 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
141 || errno == ENODATA)
142 return 1;
143 return 0;
144}
145
2ec06d2e
DJ		 146static int
147ppc_cannot_store_register (int regno)
0a30fbc4 148{
3aee8918
PA		 149 const struct target_desc *tdesc = current_process ()->tdesc;
150
b6430ec3 151#ifndef __powerpc64__
bc1e36ca 152 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 153 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
154 && regno == find_regno (tdesc, "fpscr"))
bc1e36ca 155 return 2;
30ed0a8f 156#endif
bc1e36ca 157
7284e1be 158 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 159 if (regno == find_regno (tdesc, "orig_r3")
160 || regno == find_regno (tdesc, "trap"))
7284e1be
UW		 161 return 2;
162
0a30fbc4
DJ		 163 return 0;
164}
165
2ec06d2e
DJ		 166static int
167ppc_cannot_fetch_register (int regno)
0a30fbc4
DJ		 168{
169 return 0;
170}
171
5b0a002e 172static void
442ea881 173ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
5b0a002e 174{
76b233dd
UW		 175 memset (buf, 0, sizeof (long));
176
2e4bb98a
EBM		 177 if (__BYTE_ORDER == __LITTLE_ENDIAN)
178 {
179 /* Little-endian values always sit at the left end of the buffer. */
180 collect_register (regcache, regno, buf);
181 }
182 else if (__BYTE_ORDER == __BIG_ENDIAN)
183 {
184 /* Big-endian values sit at the right end of the buffer. In case of
185 registers whose sizes are smaller than sizeof (long), we must use a
186 padding to access them correctly. */
187 int size = register_size (regcache->tdesc, regno);
188
189 if (size < sizeof (long))
190 collect_register (regcache, regno, buf + sizeof (long) - size);
191 else
192 collect_register (regcache, regno, buf);
193 }
5b0a002e 194 else
2e4bb98a 195 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 196}
197
198static void
442ea881
PA		 199ppc_supply_ptrace_register (struct regcache *regcache,
200 int regno, const char *buf)
5b0a002e 201{
2e4bb98a
EBM		 202 if (__BYTE_ORDER == __LITTLE_ENDIAN)
203 {
204 /* Little-endian values always sit at the left end of the buffer. */
205 supply_register (regcache, regno, buf);
206 }
207 else if (__BYTE_ORDER == __BIG_ENDIAN)
208 {
209 /* Big-endian values sit at the right end of the buffer. In case of
210 registers whose sizes are smaller than sizeof (long), we must use a
211 padding to access them correctly. */
212 int size = register_size (regcache->tdesc, regno);
213
214 if (size < sizeof (long))
215 supply_register (regcache, regno, buf + sizeof (long) - size);
216 else
217 supply_register (regcache, regno, buf);
218 }
5b0a002e 219 else
2e4bb98a 220 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 221}
222
0b9ff2c0
UW		 223
224#define INSTR_SC 0x44000002
225#define NR_spu_run 0x0116
226
227/* If the PPU thread is currently stopped on a spu_run system call,
228 return to FD and ADDR the file handle and NPC parameter address
229 used with the system call. Return non-zero if successful. */
230static int
442ea881 231parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
0b9ff2c0
UW		 232{
233 CORE_ADDR curr_pc;
234 int curr_insn;
235 int curr_r0;
236
3aee8918 237 if (register_size (regcache->tdesc, 0) == 4)
0b9ff2c0
UW		 238 {
239 unsigned int pc, r0, r3, r4;
442ea881
PA		 240 collect_register_by_name (regcache, "pc", &pc);
241 collect_register_by_name (regcache, "r0", &r0);
242 collect_register_by_name (regcache, "orig_r3", &r3);
243 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 244 curr_pc = (CORE_ADDR) pc;
245 curr_r0 = (int) r0;
246 *fd = (int) r3;
247 *addr = (CORE_ADDR) r4;
248 }
249 else
250 {
251 unsigned long pc, r0, r3, r4;
442ea881
PA		 252 collect_register_by_name (regcache, "pc", &pc);
253 collect_register_by_name (regcache, "r0", &r0);
254 collect_register_by_name (regcache, "orig_r3", &r3);
255 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 256 curr_pc = (CORE_ADDR) pc;
257 curr_r0 = (int) r0;
258 *fd = (int) r3;
259 *addr = (CORE_ADDR) r4;
260 }
261
262 /* Fetch instruction preceding current NIP. */
263 if ((*the_target->read_memory) (curr_pc - 4,
264 (unsigned char *) &curr_insn, 4) != 0)
265 return 0;
266 /* It should be a "sc" instruction. */
267 if (curr_insn != INSTR_SC)
268 return 0;
269 /* System call number should be NR_spu_run. */
270 if (curr_r0 != NR_spu_run)
271 return 0;
272
273 return 1;
274}
275
0d62e5e8 276static CORE_ADDR
442ea881 277ppc_get_pc (struct regcache *regcache)
0d62e5e8 278{
0b9ff2c0
UW		 279 CORE_ADDR addr;
280 int fd;
281
442ea881 282 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 283 {
284 unsigned int pc;
285 (*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
493e2a69
MS		 286 return ((CORE_ADDR)1 << 63)
287 | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
0b9ff2c0 288 }
3aee8918 289 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 290 {
291 unsigned int pc;
442ea881 292 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 293 return (CORE_ADDR) pc;
294 }
295 else
296 {
297 unsigned long pc;
442ea881 298 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 299 return (CORE_ADDR) pc;
300 }
0d62e5e8
DJ		 301}
302
303static void
442ea881 304ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8 305{
0b9ff2c0
UW		 306 CORE_ADDR addr;
307 int fd;
308
442ea881 309 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 310 {
311 unsigned int newpc = pc;
312 (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
313 }
3aee8918 314 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 315 {
316 unsigned int newpc = pc;
442ea881 317 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 318 }
319 else
320 {
321 unsigned long newpc = pc;
442ea881 322 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 323 }
324}
325
b6430ec3
UW		 326
327static int
a2174ba4 328ppc_get_auxv (unsigned long type, unsigned long *valp)
b6430ec3 329{
3aee8918
PA		 330 const struct target_desc *tdesc = current_process ()->tdesc;
331 int wordsize = register_size (tdesc, 0);
2bc84e8a 332 unsigned char *data = (unsigned char *) alloca (2 * wordsize);
b6430ec3
UW		 333 int offset = 0;
334
335 while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
336 {
337 if (wordsize == 4)
338 {
339 unsigned int *data_p = (unsigned int *)data;
a2174ba4 340 if (data_p[0] == type)
b6430ec3
UW		 341 {
342 *valp = data_p[1];
343 return 1;
344 }
345 }
346 else
347 {
348 unsigned long *data_p = (unsigned long *)data;
a2174ba4 349 if (data_p[0] == type)
b6430ec3
UW		 350 {
351 *valp = data_p[1];
352 return 1;
353 }
354 }
355
356 offset += 2 * wordsize;
357 }
358
359 *valp = 0;
360 return 0;
361}
362
3aee8918
PA		 363#ifndef __powerpc64__
364static int ppc_regmap_adjusted;
365#endif
366
0d62e5e8 367
5b0a002e 368/* Correct in either endianness.
0d62e5e8
DJ		 369 This instruction is "twge r2, r2", which GDB uses as a software
370 breakpoint. */
5b0a002e 371static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 372#define ppc_breakpoint_len 4
373
dd373349
AT		 374/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
375
376static const gdb_byte *
377ppc_sw_breakpoint_from_kind (int kind, int *size)
378{
379 *size = ppc_breakpoint_len;
380 return (const gdb_byte *) &ppc_breakpoint;
381}
382
0d62e5e8
DJ		 383static int
384ppc_breakpoint_at (CORE_ADDR where)
385{
5b0a002e 386 unsigned int insn;
0d62e5e8 387
0b9ff2c0
UW		 388 if (where & ((CORE_ADDR)1 << 63))
389 {
390 char mem_annex[32];
391 sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
392 (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
393 NULL, where & 0xffffffff, 4);
394 if (insn == 0x3fff)
395 return 1;
396 }
397 else
398 {
399 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
400 if (insn == ppc_breakpoint)
401 return 1;
402 /* If necessary, recognize more trap instructions here. GDB only uses
403 the one. */
404 }
405
0d62e5e8
DJ		 406 return 0;
407}
408
657f9cde
WW		 409/* Implement supports_z_point_type target-ops.
410 Returns true if type Z_TYPE breakpoint is supported.
411
412 Handling software breakpoint at server side, so tracepoints
413 and breakpoints can be inserted at the same location. */
414
415static int
416ppc_supports_z_point_type (char z_type)
417{
418 switch (z_type)
419 {
420 case Z_PACKET_SW_BP:
421 return 1;
422 case Z_PACKET_HW_BP:
423 case Z_PACKET_WRITE_WP:
424 case Z_PACKET_ACCESS_WP:
425 default:
426 return 0;
427 }
428}
429
430/* Implement insert_point target-ops.
431 Returns 0 on success, -1 on failure and 1 on unsupported. */
432
433static int
434ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
435 int size, struct raw_breakpoint *bp)
436{
437 switch (type)
438 {
439 case raw_bkpt_type_sw:
440 return insert_memory_breakpoint (bp);
441
442 case raw_bkpt_type_hw:
443 case raw_bkpt_type_write_wp:
444 case raw_bkpt_type_access_wp:
445 default:
446 /* Unsupported. */
447 return 1;
448 }
449}
450
451/* Implement remove_point target-ops.
452 Returns 0 on success, -1 on failure and 1 on unsupported. */
453
454static int
455ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
456 int size, struct raw_breakpoint *bp)
457{
458 switch (type)
459 {
460 case raw_bkpt_type_sw:
461 return remove_memory_breakpoint (bp);
462
463 case raw_bkpt_type_hw:
464 case raw_bkpt_type_write_wp:
465 case raw_bkpt_type_access_wp:
466 default:
467 /* Unsupported. */
468 return 1;
469 }
470}
471
e9d25b98
DJ		 472/* Provide only a fill function for the general register set. ps_lgetregs
473 will use this for NPTL support. */
474
442ea881 475static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 476{
477 int i;
478
479 for (i = 0; i < 32; i++)
442ea881 480 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 481
482 for (i = 64; i < 70; i++)
442ea881 483 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
7284e1be
UW		 484
485 for (i = 71; i < 73; i++)
442ea881 486 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 487}
488
7ca18ed6
EBM		 489/* Program Priority Register regset fill function. */
490
491static void
492ppc_fill_pprregset (struct regcache *regcache, void *buf)
493{
494 char *ppr = (char *) buf;
495
496 collect_register_by_name (regcache, "ppr", ppr);
497}
498
499/* Program Priority Register regset store function. */
500
501static void
502ppc_store_pprregset (struct regcache *regcache, const void *buf)
503{
504 const char *ppr = (const char *) buf;
505
506 supply_register_by_name (regcache, "ppr", ppr);
507}
508
509/* Data Stream Control Register regset fill function. */
510
511static void
512ppc_fill_dscrregset (struct regcache *regcache, void *buf)
513{
514 char *dscr = (char *) buf;
515
516 collect_register_by_name (regcache, "dscr", dscr);
517}
518
519/* Data Stream Control Register regset store function. */
520
521static void
522ppc_store_dscrregset (struct regcache *regcache, const void *buf)
523{
524 const char *dscr = (const char *) buf;
525
526 supply_register_by_name (regcache, "dscr", dscr);
527}
528
f2cf6173
EBM		 529/* Target Address Register regset fill function. */
530
531static void
532ppc_fill_tarregset (struct regcache *regcache, void *buf)
533{
534 char *tar = (char *) buf;
535
536 collect_register_by_name (regcache, "tar", tar);
537}
538
539/* Target Address Register regset store function. */
540
541static void
542ppc_store_tarregset (struct regcache *regcache, const void *buf)
543{
544 const char *tar = (const char *) buf;
545
546 supply_register_by_name (regcache, "tar", tar);
547}
548
232bfb86
EBM		 549/* Event-Based Branching regset store function. Unless the inferior
550 has a perf event open, ptrace can return in error when reading and
551 writing to the regset, with ENODATA. For reading, the registers
552 will correctly show as unavailable. For writing, gdbserver
553 currently only caches any register writes from P and G packets and
554 the stub always tries to write all the regsets when resuming the
555 inferior, which would result in frequent warnings. For this
556 reason, we don't define a fill function. This also means that the
557 client-side regcache will be dirty if the user tries to write to
558 the EBB registers. G packets that the client sends to write to
559 unrelated registers will also include data for EBB registers, even
560 if they are unavailable. */
561
562static void
563ppc_store_ebbregset (struct regcache *regcache, const void *buf)
564{
565 const char *regset = (const char *) buf;
566
567 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
568 .dat file is BESCR, EBBHR, EBBRR. */
569 supply_register_by_name (regcache, "ebbrr", &regset[0]);
570 supply_register_by_name (regcache, "ebbhr", &regset[8]);
571 supply_register_by_name (regcache, "bescr", &regset[16]);
572}
573
574/* Performance Monitoring Unit regset fill function. */
575
576static void
577ppc_fill_pmuregset (struct regcache *regcache, void *buf)
578{
579 char *regset = (char *) buf;
580
581 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
582 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
583 collect_register_by_name (regcache, "siar", &regset[0]);
584 collect_register_by_name (regcache, "sdar", &regset[8]);
585 collect_register_by_name (regcache, "sier", &regset[16]);
586 collect_register_by_name (regcache, "mmcr2", &regset[24]);
587 collect_register_by_name (regcache, "mmcr0", &regset[32]);
588}
589
590/* Performance Monitoring Unit regset store function. */
591
592static void
593ppc_store_pmuregset (struct regcache *regcache, const void *buf)
594{
595 const char *regset = (const char *) buf;
596
597 supply_register_by_name (regcache, "siar", &regset[0]);
598 supply_register_by_name (regcache, "sdar", &regset[8]);
599 supply_register_by_name (regcache, "sier", &regset[16]);
600 supply_register_by_name (regcache, "mmcr2", &regset[24]);
601 supply_register_by_name (regcache, "mmcr0", &regset[32]);
602}
603
8d619c01
EBM		 604/* Hardware Transactional Memory special-purpose register regset fill
605 function. */
606
607static void
608ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
609{
610 int i, base;
611 char *regset = (char *) buf;
612
613 base = find_regno (regcache->tdesc, "tfhar");
614 for (i = 0; i < 3; i++)
615 collect_register (regcache, base + i, &regset[i * 8]);
616}
617
618/* Hardware Transactional Memory special-purpose register regset store
619 function. */
620
621static void
622ppc_store_tm_sprregset (struct regcache *regcache, const void *buf)
623{
624 int i, base;
625 const char *regset = (const char *) buf;
626
627 base = find_regno (regcache->tdesc, "tfhar");
628 for (i = 0; i < 3; i++)
629 supply_register (regcache, base + i, &regset[i * 8]);
630}
631
632/* For the same reasons as the EBB regset, none of the HTM
633 checkpointed regsets have a fill function. These registers are
634 only available if the inferior is in a transaction. */
635
636/* Hardware Transactional Memory checkpointed general-purpose regset
637 store function. */
638
639static void
640ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf)
641{
642 int i, base, size, endian_offset;
643 const char *regset = (const char *) buf;
644
645 base = find_regno (regcache->tdesc, "cr0");
646 size = register_size (regcache->tdesc, base);
647
648 gdb_assert (size == 4 || size == 8);
649
650 for (i = 0; i < 32; i++)
651 supply_register (regcache, base + i, &regset[i * size]);
652
653 endian_offset = 0;
654
655 if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN))
656 endian_offset = 4;
657
658 supply_register_by_name (regcache, "ccr",
659 &regset[PT_CCR * size + endian_offset]);
660
661 supply_register_by_name (regcache, "cxer",
662 &regset[PT_XER * size + endian_offset]);
663
664 supply_register_by_name (regcache, "clr", &regset[PT_LNK * size]);
665 supply_register_by_name (regcache, "cctr", &regset[PT_CTR * size]);
666}
667
668/* Hardware Transactional Memory checkpointed floating-point regset
669 store function. */
670
671static void
672ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf)
673{
674 int i, base;
675 const char *regset = (const char *) buf;
676
677 base = find_regno (regcache->tdesc, "cf0");
678
679 for (i = 0; i < 32; i++)
680 supply_register (regcache, base + i, &regset[i * 8]);
681
682 supply_register_by_name (regcache, "cfpscr", &regset[32 * 8]);
683}
684
685/* Hardware Transactional Memory checkpointed vector regset store
686 function. */
687
688static void
689ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf)
690{
691 int i, base;
692 const char *regset = (const char *) buf;
693 int vscr_offset = 0;
694
695 base = find_regno (regcache->tdesc, "cvr0");
696
697 for (i = 0; i < 32; i++)
698 supply_register (regcache, base + i, &regset[i * 16]);
699
700 if (__BYTE_ORDER == __BIG_ENDIAN)
701 vscr_offset = 12;
702
703 supply_register_by_name (regcache, "cvscr",
704 &regset[32 * 16 + vscr_offset]);
705
706 supply_register_by_name (regcache, "cvrsave", &regset[33 * 16]);
707}
708
709/* Hardware Transactional Memory checkpointed vector-scalar regset
710 store function. */
711
712static void
713ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf)
714{
715 int i, base;
716 const char *regset = (const char *) buf;
717
718 base = find_regno (regcache->tdesc, "cvs0h");
719 for (i = 0; i < 32; i++)
720 supply_register (regcache, base + i, &regset[i * 8]);
721}
722
723/* Hardware Transactional Memory checkpointed Program Priority
724 Register regset store function. */
725
726static void
727ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf)
728{
729 const char *cppr = (const char *) buf;
730
731 supply_register_by_name (regcache, "cppr", cppr);
732}
733
734/* Hardware Transactional Memory checkpointed Data Stream Control
735 Register regset store function. */
736
737static void
738ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf)
739{
740 const char *cdscr = (const char *) buf;
741
742 supply_register_by_name (regcache, "cdscr", cdscr);
743}
744
745/* Hardware Transactional Memory checkpointed Target Address Register
746 regset store function. */
747
748static void
749ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf)
750{
751 const char *ctar = (const char *) buf;
752
753 supply_register_by_name (regcache, "ctar", ctar);
754}
755
677c5bb1 756static void
442ea881 757ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 758{
759 int i, base;
2bc84e8a 760 char *regset = (char *) buf;
677c5bb1 761
3aee8918 762 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 763 for (i = 0; i < 32; i++)
442ea881 764 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 765}
766
767static void
442ea881 768ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 769{
770 int i, base;
2bc84e8a 771 const char *regset = (const char *) buf;
677c5bb1 772
3aee8918 773 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 774 for (i = 0; i < 32; i++)
442ea881 775 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 776}
777
30ed0a8f 778static void
442ea881 779ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 780{
781 int i, base;
2bc84e8a 782 char *regset = (char *) buf;
1d75a658 783 int vscr_offset = 0;
30ed0a8f 784
3aee8918 785 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 786 for (i = 0; i < 32; i++)
442ea881 787 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 788
1d75a658
PFC		 789 if (__BYTE_ORDER == __BIG_ENDIAN)
790 vscr_offset = 12;
791
1d75a658
PFC		 792 collect_register_by_name (regcache, "vscr",
793 &regset[32 * 16 + vscr_offset]);
794
442ea881 795 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 796}
797
798static void
442ea881 799ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 800{
801 int i, base;
2bc84e8a 802 const char *regset = (const char *) buf;
1d75a658 803 int vscr_offset = 0;
30ed0a8f 804
3aee8918 805 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 806 for (i = 0; i < 32; i++)
442ea881 807 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 808
1d75a658
PFC		 809 if (__BYTE_ORDER == __BIG_ENDIAN)
810 vscr_offset = 12;
811
812 supply_register_by_name (regcache, "vscr",
813 &regset[32 * 16 + vscr_offset]);
442ea881 814 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 815}
816
30ed0a8f
DJ		 817struct gdb_evrregset_t
818{
819 unsigned long evr[32];
820 unsigned long long acc;
821 unsigned long spefscr;
822};
823
824static void
442ea881 825ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 826{
827 int i, ev0;
2bc84e8a 828 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 829
3aee8918 830 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 831 for (i = 0; i < 32; i++)
442ea881 832 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 833
442ea881
PA		 834 collect_register_by_name (regcache, "acc", &regset->acc);
835 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 836}
837
838static void
442ea881 839ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 840{
841 int i, ev0;
2bc84e8a 842 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 843
3aee8918 844 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 845 for (i = 0; i < 32; i++)
442ea881 846 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 847
442ea881
PA		 848 supply_register_by_name (regcache, "acc", &regset->acc);
849 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 850}
30ed0a8f 851
7d00775e
AT		 852/* Support for hardware single step. */
853
854static int
855ppc_supports_hardware_single_step (void)
856{
857 return 1;
858}
859
3aee8918 860static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 861 /* List the extra register sets before GENERAL_REGS. That way we will
862 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
863 general registers. Some kernels support these, but not the newer
864 PPC_PTRACE_GETREGS. */
8d619c01
EBM		 865 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS,
866 NULL, ppc_store_tm_ctarregset },
867 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS,
868 NULL, ppc_store_tm_cdscrregset },
869 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS,
870 NULL, ppc_store_tm_cpprregset },
871 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS,
872 NULL, ppc_store_tm_cvsxregset },
873 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS,
874 NULL, ppc_store_tm_cvrregset },
875 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS,
876 NULL, ppc_store_tm_cfprregset },
877 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS,
878 NULL, ppc_store_tm_cgprregset },
879 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
880 ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
232bfb86
EBM		 881 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
882 NULL, ppc_store_ebbregset },
883 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
884 ppc_fill_pmuregset, ppc_store_pmuregset },
f2cf6173
EBM		 885 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
886 ppc_fill_tarregset, ppc_store_tarregset },
7ca18ed6
EBM		 887 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
888 ppc_fill_pprregset, ppc_store_pprregset },
889 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
890 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 891 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 892 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 893 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 894 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 895 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 896 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 897 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 898 NULL_REGSET
e9d25b98
DJ		 899};
900
3aee8918
PA		 901static struct usrregs_info ppc_usrregs_info =
902 {
903 ppc_num_regs,
904 ppc_regmap,
905 };
906
907static struct regsets_info ppc_regsets_info =
908 {
909 ppc_regsets, /* regsets */
910 0, /* num_regsets */
911 NULL, /* disabled_regsets */
912 };
913
914static struct regs_info regs_info =
915 {
916 NULL, /* regset_bitmap */
917 &ppc_usrregs_info,
918 &ppc_regsets_info
919 };
920
921static const struct regs_info *
922ppc_regs_info (void)
923{
924 return &regs_info;
925}
926
e6c5bb05
SM		 927static void
928ppc_arch_setup (void)
929{
930 const struct target_desc *tdesc;
7273b5fc 931 struct regset_info *regset;
bd64614e 932 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 933
2e077f5e 934 int tid = lwpid_of (current_thread);
bd64614e 935
2e077f5e 936 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 937
bd64614e 938 if (features.wordsize == 4)
bd64614e 939 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 940 else
941 tdesc = tdesc_powerpc_64l;
942
943 current_process ()->tdesc = tdesc;
e6c5bb05 944
bd64614e
PFC		 945 /* The value of current_process ()->tdesc needs to be set for this
946 call. */
a2174ba4 947 ppc_get_auxv (AT_HWCAP, &ppc_hwcap);
7ca18ed6 948 ppc_get_auxv (AT_HWCAP2, &ppc_hwcap2);
bd64614e
PFC		 949
950 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
951
952 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
953 features.vsx = true;
954
955 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
956 features.altivec = true;
957
7ca18ed6
EBM		 958 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
959 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
960 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
f2cf6173
EBM		 961 {
962 features.ppr_dscr = true;
963 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
964 && (ppc_hwcap2 & PPC_FEATURE2_TAR)
232bfb86 965 && (ppc_hwcap2 & PPC_FEATURE2_EBB)
f2cf6173 966 && ppc_check_regset (tid, NT_PPC_TAR,
232bfb86
EBM		 967 PPC_LINUX_SIZEOF_TARREGSET)
968 && ppc_check_regset (tid, NT_PPC_EBB,
969 PPC_LINUX_SIZEOF_EBBREGSET)
970 && ppc_check_regset (tid, NT_PPC_PMU,
971 PPC_LINUX_SIZEOF_PMUREGSET))
8d619c01
EBM		 972 {
973 features.isa207 = true;
974 if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
975 && ppc_check_regset (tid, NT_PPC_TM_SPR,
976 PPC_LINUX_SIZEOF_TM_SPRREGSET))
977 features.htm = true;
978 }
f2cf6173 979 }
7ca18ed6 980
e6c5bb05 981 if (ppc_hwcap & PPC_FEATURE_CELL)
bd64614e
PFC		 982 features.cell = true;
983
984 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 985
986 /* On 32-bit machines, check for SPE registers.
987 Set the low target's regmap field as appropriately. */
988#ifndef __powerpc64__
989 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
990 tdesc = tdesc_powerpc_e500l;
991
992 if (!ppc_regmap_adjusted)
993 {
994 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
995 ppc_usrregs_info.regmap = ppc_regmap_e500;
996
997 /* If the FPSCR is 64-bit wide, we need to fetch the whole
998 64-bit slot and not just its second word. The PT_FPSCR
999 supplied in a 32-bit GDB compilation doesn't reflect
1000 this. */
1001 if (register_size (tdesc, 70) == 8)
1002 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
1003
1004 ppc_regmap_adjusted = 1;
1005 }
1006#endif
bd64614e 1007
e6c5bb05 1008 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 1009
1010 for (regset = ppc_regsets; regset->size >= 0; regset++)
1011 switch (regset->get_request)
1012 {
1013 case PTRACE_GETVRREGS:
d078308a 1014 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 1015 break;
1016 case PTRACE_GETVSXREGS:
d078308a 1017 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 1018 break;
1019 case PTRACE_GETEVRREGS:
1020 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
1021 regset->size = 32 * 4 + 8 + 4;
1022 else
1023 regset->size = 0;
1024 break;
7ca18ed6
EBM		 1025 case PTRACE_GETREGSET:
1026 switch (regset->nt_type)
1027 {
1028 case NT_PPC_PPR:
1029 regset->size = (features.ppr_dscr ?
1030 PPC_LINUX_SIZEOF_PPRREGSET : 0);
1031 break;
1032 case NT_PPC_DSCR:
1033 regset->size = (features.ppr_dscr ?
1034 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
1035 break;
f2cf6173
EBM		 1036 case NT_PPC_TAR:
1037 regset->size = (features.isa207 ?
1038 PPC_LINUX_SIZEOF_TARREGSET : 0);
1039 break;
232bfb86
EBM		 1040 case NT_PPC_EBB:
1041 regset->size = (features.isa207 ?
1042 PPC_LINUX_SIZEOF_EBBREGSET : 0);
1043 break;
1044 case NT_PPC_PMU:
1045 regset->size = (features.isa207 ?
1046 PPC_LINUX_SIZEOF_PMUREGSET : 0);
1047 break;
8d619c01
EBM		 1048 case NT_PPC_TM_SPR:
1049 regset->size = (features.htm ?
1050 PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
1051 break;
1052 case NT_PPC_TM_CGPR:
1053 if (features.wordsize == 4)
1054 regset->size = (features.htm ?
1055 PPC32_LINUX_SIZEOF_CGPRREGSET : 0);
1056 else
1057 regset->size = (features.htm ?
1058 PPC64_LINUX_SIZEOF_CGPRREGSET : 0);
1059 break;
1060 case NT_PPC_TM_CFPR:
1061 regset->size = (features.htm ?
1062 PPC_LINUX_SIZEOF_CFPRREGSET : 0);
1063 break;
1064 case NT_PPC_TM_CVMX:
1065 regset->size = (features.htm ?
1066 PPC_LINUX_SIZEOF_CVMXREGSET : 0);
1067 break;
1068 case NT_PPC_TM_CVSX:
1069 regset->size = (features.htm ?
1070 PPC_LINUX_SIZEOF_CVSXREGSET : 0);
1071 break;
1072 case NT_PPC_TM_CPPR:
1073 regset->size = (features.htm ?
1074 PPC_LINUX_SIZEOF_CPPRREGSET : 0);
1075 break;
1076 case NT_PPC_TM_CDSCR:
1077 regset->size = (features.htm ?
1078 PPC_LINUX_SIZEOF_CDSCRREGSET : 0);
1079 break;
1080 case NT_PPC_TM_CTAR:
1081 regset->size = (features.htm ?
1082 PPC_LINUX_SIZEOF_CTARREGSET : 0);
1083 break;
7ca18ed6
EBM		 1084 default:
1085 break;
1086 }
1087 break;
7273b5fc
PFC		 1088 default:
1089 break;
1090 }
e6c5bb05
SM		 1091}
1092
a2174ba4
MK		 1093/* Implementation of linux_target_ops method "supports_tracepoints". */
1094
b04fd3be
MK		 1095static int
1096ppc_supports_tracepoints (void)
1097{
1098 return 1;
1099}
1100
a2174ba4
MK		 1101/* Get the thread area address. This is used to recognize which
1102 thread is which when tracing with the in-process agent library. We
1103 don't read anything from the address, and treat it as opaque; it's
1104 the address itself that we assume is unique per-thread. */
1105
1106static int
1107ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
1108{
f2907e49 1109 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 1110 struct thread_info *thr = get_lwp_thread (lwp);
1111 struct regcache *regcache = get_thread_regcache (thr, 1);
1112 ULONGEST tp = 0;
1113
1114#ifdef __powerpc64__
1115 if (register_size (regcache->tdesc, 0) == 8)
1116 collect_register_by_name (regcache, "r13", &tp);
1117 else
1118#endif
1119 collect_register_by_name (regcache, "r2", &tp);
1120
1121 *addr = tp;
1122
1123 return 0;
1124}
1125
1126#ifdef __powerpc64__
1127
1128/* Older glibc doesn't provide this. */
1129
1130#ifndef EF_PPC64_ABI
1131#define EF_PPC64_ABI 3
1132#endif
1133
1134/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1135 inferiors. */
1136
1137static int
1138is_elfv2_inferior (void)
1139{
1140 /* To be used as fallback if we're unable to determine the right result -
1141 assume inferior uses the same ABI as gdbserver. */
1142#if _CALL_ELF == 2
1143 const int def_res = 1;
1144#else
1145 const int def_res = 0;
1146#endif
1147 unsigned long phdr;
1148 Elf64_Ehdr ehdr;
1149
1150 if (!ppc_get_auxv (AT_PHDR, &phdr))
1151 return def_res;
1152
1153 /* Assume ELF header is at the beginning of the page where program headers
1154 are located. If it doesn't look like one, bail. */
1155
1156 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
1157 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
1158 return def_res;
1159
1160 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
1161}
1162
1163#endif
1164
1165/* Generate a ds-form instruction in BUF and return the number of bytes written
1166
1167 0 6 11 16 30 32
1168 | OPCD | RST | RA | DS |XO| */
1169
1170__attribute__((unused)) /* Maybe unused due to conditional compilation. */
1171static int
1172gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
1173{
1174 uint32_t insn;
1175
1176 gdb_assert ((opcd & ~0x3f) == 0);
1177 gdb_assert ((rst & ~0x1f) == 0);
1178 gdb_assert ((ra & ~0x1f) == 0);
1179 gdb_assert ((xo & ~0x3) == 0);
1180
1181 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
1182 *buf = (opcd << 26) | insn;
1183 return 1;
1184}
1185
1186/* Followings are frequently used ds-form instructions. */
1187
1188#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1189#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1190#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1191#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1192
1193/* Generate a d-form instruction in BUF.
1194
1195 0 6 11 16 32
1196 | OPCD | RST | RA | D | */
1197
1198static int
1199gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
1200{
1201 uint32_t insn;
1202
1203 gdb_assert ((opcd & ~0x3f) == 0);
1204 gdb_assert ((rst & ~0x1f) == 0);
1205 gdb_assert ((ra & ~0x1f) == 0);
1206
1207 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
1208 *buf = (opcd << 26) | insn;
1209 return 1;
1210}
1211
1212/* Followings are frequently used d-form instructions. */
1213
1214#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1215#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1216#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1217#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1218#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1219#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1220#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1221#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1222#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1223
1224/* Generate a xfx-form instruction in BUF and return the number of bytes
1225 written.
1226
1227 0 6 11 21 31 32
1228 | OPCD | RST | RI | XO |/| */
1229
1230static int
1231gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
1232{
1233 uint32_t insn;
1234 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
1235
1236 gdb_assert ((opcd & ~0x3f) == 0);
1237 gdb_assert ((rst & ~0x1f) == 0);
1238 gdb_assert ((xo & ~0x3ff) == 0);
1239
1240 insn = (rst << 21) | (n << 11) | (xo << 1);
1241 *buf = (opcd << 26) | insn;
1242 return 1;
1243}
1244
1245/* Followings are frequently used xfx-form instructions. */
1246
1247#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1248#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1249#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1250#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1251#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1252 E & 0xf, 598)
1253#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1254
1255
1256/* Generate a x-form instruction in BUF and return the number of bytes written.
1257
1258 0 6 11 16 21 31 32
1259 | OPCD | RST | RA | RB | XO |RC| */
1260
1261static int
1262gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
1263{
1264 uint32_t insn;
1265
1266 gdb_assert ((opcd & ~0x3f) == 0);
1267 gdb_assert ((rst & ~0x1f) == 0);
1268 gdb_assert ((ra & ~0x1f) == 0);
1269 gdb_assert ((rb & ~0x1f) == 0);
1270 gdb_assert ((xo & ~0x3ff) == 0);
1271 gdb_assert ((rc & ~1) == 0);
1272
1273 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
1274 *buf = (opcd << 26) | insn;
1275 return 1;
1276}
1277
1278/* Followings are frequently used x-form instructions. */
1279
1280#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1281#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1282#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1283#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1284/* Assume bf = cr7. */
1285#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1286
1287
1288/* Generate a md-form instruction in BUF and return the number of bytes written.
1289
1290 0 6 11 16 21 27 30 31 32
1291 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1292
1293static int
1294gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
1295 int xo, int rc)
1296{
1297 uint32_t insn;
1298 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
1299 unsigned int sh0_4 = sh & 0x1f;
1300 unsigned int sh5 = (sh >> 5) & 1;
1301
1302 gdb_assert ((opcd & ~0x3f) == 0);
1303 gdb_assert ((rs & ~0x1f) == 0);
1304 gdb_assert ((ra & ~0x1f) == 0);
1305 gdb_assert ((sh & ~0x3f) == 0);
1306 gdb_assert ((mb & ~0x3f) == 0);
1307 gdb_assert ((xo & ~0x7) == 0);
1308 gdb_assert ((rc & ~0x1) == 0);
1309
1310 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
1311 | (sh5 << 1) | (xo << 2) | (rc & 1);
1312 *buf = (opcd << 26) | insn;
1313 return 1;
1314}
1315
1316/* The following are frequently used md-form instructions. */
1317
1318#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1319 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1320#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1321 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1322
1323/* Generate a i-form instruction in BUF and return the number of bytes written.
1324
1325 0 6 30 31 32
1326 | OPCD | LI |AA|LK| */
1327
1328static int
1329gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1330{
1331 uint32_t insn;
1332
1333 gdb_assert ((opcd & ~0x3f) == 0);
1334
1335 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1336 *buf = (opcd << 26) | insn;
1337 return 1;
1338}
1339
1340/* The following are frequently used i-form instructions. */
1341
1342#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1343#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1344
1345/* Generate a b-form instruction in BUF and return the number of bytes written.
1346
1347 0 6 11 16 30 31 32
1348 | OPCD | BO | BI | BD |AA|LK| */
1349
1350static int
1351gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1352 int aa, int lk)
1353{
1354 uint32_t insn;
1355
1356 gdb_assert ((opcd & ~0x3f) == 0);
1357 gdb_assert ((bo & ~0x1f) == 0);
1358 gdb_assert ((bi & ~0x1f) == 0);
1359
1360 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1361 *buf = (opcd << 26) | insn;
1362 return 1;
1363}
1364
1365/* The following are frequently used b-form instructions. */
1366/* Assume bi = cr7. */
1367#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1368
1369/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1370 respectively. They are primary used for save/restore GPRs in jump-pad,
1371 not used for bytecode compiling. */
1372
1373#ifdef __powerpc64__
1374#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1375 GEN_LD (buf, rt, ra, si) : \
1376 GEN_LWZ (buf, rt, ra, si))
1377#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1378 GEN_STD (buf, rt, ra, si) : \
1379 GEN_STW (buf, rt, ra, si))
1380#else
1381#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1382#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1383#endif
1384
1385/* Generate a sequence of instructions to load IMM in the register REG.
1386 Write the instructions in BUF and return the number of bytes written. */
1387
1388static int
1389gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1390{
1391 uint32_t *p = buf;
1392
1393 if ((imm + 32768) < 65536)
1394 {
1395 /* li reg, imm[15:0] */
1396 p += GEN_LI (p, reg, imm);
1397 }
1398 else if ((imm >> 32) == 0)
1399 {
1400 /* lis reg, imm[31:16]
1401 ori reg, reg, imm[15:0]
1402 rldicl reg, reg, 0, 32 */
1403 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1404 if ((imm & 0xffff) != 0)
1405 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1406 /* Clear upper 32-bit if sign-bit is set. */
1407 if (imm & (1u << 31) && is_64)
1408 p += GEN_RLDICL (p, reg, reg, 0, 32);
1409 }
1410 else
1411 {
1412 gdb_assert (is_64);
1413 /* lis reg, <imm[63:48]>
1414 ori reg, reg, <imm[48:32]>
1415 rldicr reg, reg, 32, 31
1416 oris reg, reg, <imm[31:16]>
1417 ori reg, reg, <imm[15:0]> */
1418 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1419 if (((imm >> 32) & 0xffff) != 0)
1420 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1421 p += GEN_RLDICR (p, reg, reg, 32, 31);
1422 if (((imm >> 16) & 0xffff) != 0)
1423 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1424 if ((imm & 0xffff) != 0)
1425 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1426 }
1427
1428 return p - buf;
1429}
1430
1431/* Generate a sequence for atomically exchange at location LOCK.
1432 This code sequence clobbers r6, r7, r8. LOCK is the location for
1433 the atomic-xchg, OLD_VALUE is expected old value stored in the
1434 location, and R_NEW is a register for the new value. */
1435
1436static int
1437gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1438 int is_64)
1439{
1440 const int r_lock = 6;
1441 const int r_old = 7;
1442 const int r_tmp = 8;
1443 uint32_t *p = buf;
1444
1445 /*
1446 1: lwarx TMP, 0, LOCK
1447 cmpwi TMP, OLD
1448 bne 1b
1449 stwcx. NEW, 0, LOCK
1450 bne 1b */
1451
1452 p += gen_limm (p, r_lock, lock, is_64);
1453 p += gen_limm (p, r_old, old_value, is_64);
1454
1455 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1456 p += GEN_CMPW (p, r_tmp, r_old);
1457 p += GEN_BNE (p, -8);
1458 p += GEN_STWCX (p, r_new, 0, r_lock);
1459 p += GEN_BNE (p, -16);
1460
1461 return p - buf;
1462}
1463
1464/* Generate a sequence of instructions for calling a function
1465 at address of FN. Return the number of bytes are written in BUF. */
1466
1467static int
1468gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1469{
1470 uint32_t *p = buf;
1471
1472 /* Must be called by r12 for caller to calculate TOC address. */
1473 p += gen_limm (p, 12, fn, is_64);
1474 if (is_opd)
1475 {
1476 p += GEN_LOAD (p, 11, 12, 16, is_64);
1477 p += GEN_LOAD (p, 2, 12, 8, is_64);
1478 p += GEN_LOAD (p, 12, 12, 0, is_64);
1479 }
1480 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1481 *p++ = 0x4e800421; /* bctrl */
1482
1483 return p - buf;
1484}
1485
1486/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1487 of instruction. This function is used to adjust pc-relative instructions
1488 when copying. */
1489
1490static void
1491ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1492{
1493 uint32_t insn, op6;
1494 long rel, newrel;
1495
1496 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1497 op6 = PPC_OP6 (insn);
1498
1499 if (op6 == 18 && (insn & 2) == 0)
1500 {
1501 /* branch && AA = 0 */
1502 rel = PPC_LI (insn);
1503 newrel = (oldloc - *to) + rel;
1504
1505 /* Out of range. Cannot relocate instruction. */
1506 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1507 return;
1508
1509 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1510 }
1511 else if (op6 == 16 && (insn & 2) == 0)
1512 {
1513 /* conditional branch && AA = 0 */
1514
1515 /* If the new relocation is too big for even a 26-bit unconditional
1516 branch, there is nothing we can do. Just abort.
1517
1518 Otherwise, if it can be fit in 16-bit conditional branch, just
1519 copy the instruction and relocate the address.
1520
1521 If the it's big for conditional-branch (16-bit), try to invert the
1522 condition and jump with 26-bit branch. For example,
1523
1524 beq .Lgoto
1525 INSN1
1526
1527 =>
1528
1529 bne 1f (+8)
1530 b .Lgoto
1531 1:INSN1
1532
1533 After this transform, we are actually jump from *TO+4 instead of *TO,
1534 so check the relocation again because it will be 1-insn farther then
1535 before if *TO is after OLDLOC.
1536
1537
1538 For BDNZT (or so) is transformed from
1539
1540 bdnzt eq, .Lgoto
1541 INSN1
1542
1543 =>
1544
1545 bdz 1f (+12)
1546 bf eq, 1f (+8)
1547 b .Lgoto
1548 1:INSN1
1549
1550 See also "BO field encodings". */
1551
1552 rel = PPC_BD (insn);
1553 newrel = (oldloc - *to) + rel;
1554
1555 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1556 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1557 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1558 {
1559 newrel -= 4;
1560
1561 /* Out of range. Cannot relocate instruction. */
1562 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1563 return;
1564
1565 if ((PPC_BO (insn) & 0x14) == 0x4)
1566 insn ^= (1 << 24);
1567 else if ((PPC_BO (insn) & 0x14) == 0x10)
1568 insn ^= (1 << 22);
1569
1570 /* Jump over the unconditional branch. */
1571 insn = (insn & ~0xfffc) | 0x8;
1572 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1573 *to += 4;
1574
1575 /* Build a unconditional branch and copy LK bit. */
1576 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1577 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1578 *to += 4;
1579
1580 return;
1581 }
1582 else if ((PPC_BO (insn) & 0x14) == 0)
1583 {
1584 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1585 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1586
1587 newrel -= 8;
1588
1589 /* Out of range. Cannot relocate instruction. */
1590 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1591 return;
1592
1593 /* Copy BI field. */
1594 bf_insn |= (insn & 0x1f0000);
1595
1596 /* Invert condition. */
1597 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1598 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1599
1600 write_inferior_memory (*to, (unsigned char *) &bdnz_insn, 4);
1601 *to += 4;
1602 write_inferior_memory (*to, (unsigned char *) &bf_insn, 4);
1603 *to += 4;
1604
1605 /* Build a unconditional branch and copy LK bit. */
1606 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1607 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1608 *to += 4;
1609
1610 return;
1611 }
1612 else /* (BO & 0x14) == 0x14, branch always. */
1613 {
1614 /* Out of range. Cannot relocate instruction. */
1615 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1616 return;
1617
1618 /* Build a unconditional branch and copy LK bit. */
1619 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1620 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1621 *to += 4;
1622
1623 return;
1624 }
1625 }
1626
1627 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1628 *to += 4;
1629}
1630
1631/* Implement install_fast_tracepoint_jump_pad of target_ops.
1632 See target.h for details. */
1633
1634static int
1635ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1636 CORE_ADDR collector,
1637 CORE_ADDR lockaddr,
1638 ULONGEST orig_size,
1639 CORE_ADDR *jump_entry,
1640 CORE_ADDR *trampoline,
1641 ULONGEST *trampoline_size,
1642 unsigned char *jjump_pad_insn,
1643 ULONGEST *jjump_pad_insn_size,
1644 CORE_ADDR *adjusted_insn_addr,
1645 CORE_ADDR *adjusted_insn_addr_end,
1646 char *err)
1647{
1648 uint32_t buf[256];
1649 uint32_t *p = buf;
1650 int j, offset;
1651 CORE_ADDR buildaddr = *jump_entry;
1652 const CORE_ADDR entryaddr = *jump_entry;
1653 int rsz, min_frame, frame_size, tp_reg;
1654#ifdef __powerpc64__
1655 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1656 int is_64 = register_size (regcache->tdesc, 0) == 8;
1657 int is_opd = is_64 && !is_elfv2_inferior ();
1658#else
1659 int is_64 = 0, is_opd = 0;
1660#endif
1661
1662#ifdef __powerpc64__
1663 if (is_64)
1664 {
1665 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1666 rsz = 8;
1667 min_frame = 112;
1668 frame_size = (40 * rsz) + min_frame;
1669 tp_reg = 13;
1670 }
1671 else
1672 {
1673#endif
1674 rsz = 4;
1675 min_frame = 16;
1676 frame_size = (40 * rsz) + min_frame;
1677 tp_reg = 2;
1678#ifdef __powerpc64__
1679 }
1680#endif
1681
1682 /* Stack frame layout for this jump pad,
1683
1684 High thread_area (r13/r2) |
1685 tpoint - collecting_t obj
1686 PC/<tpaddr> | +36
1687 CTR | +35
1688 LR | +34
1689 XER | +33
1690 CR | +32
1691 R31 |
1692 R29 |
1693 ... |
1694 R1 | +1
1695 R0 - collected registers
1696 ... |
1697 ... |
1698 Low Back-chain -
1699
1700
1701 The code flow of this jump pad,
1702
1703 1. Adjust SP
1704 2. Save GPR and SPR
1705 3. Prepare argument
1706 4. Call gdb_collector
1707 5. Restore GPR and SPR
1708 6. Restore SP
1709 7. Build a jump for back to the program
1710 8. Copy/relocate original instruction
1711 9. Build a jump for replacing orignal instruction. */
1712
1713 /* Adjust stack pointer. */
1714 if (is_64)
1715 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1716 else
1717 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1718
1719 /* Store GPRs. Save R1 later, because it had just been modified, but
1720 we want the original value. */
1721 for (j = 2; j < 32; j++)
1722 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1723 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1724 /* Set r0 to the original value of r1 before adjusting stack frame,
1725 and then save it. */
1726 p += GEN_ADDI (p, 0, 1, frame_size);
1727 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1728
1729 /* Save CR, XER, LR, and CTR. */
1730 p += GEN_MFCR (p, 3); /* mfcr r3 */
1731 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1732 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1733 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1734 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1735 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1736 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1737 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1738
1739 /* Save PC<tpaddr> */
1740 p += gen_limm (p, 3, tpaddr, is_64);
1741 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1742
1743
1744 /* Setup arguments to collector. */
1745 /* Set r4 to collected registers. */
1746 p += GEN_ADDI (p, 4, 1, min_frame);
1747 /* Set r3 to TPOINT. */
1748 p += gen_limm (p, 3, tpoint, is_64);
1749
1750 /* Prepare collecting_t object for lock. */
1751 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1752 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1753 /* Set R5 to collecting object. */
1754 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1755
1756 p += GEN_LWSYNC (p);
1757 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1758 p += GEN_LWSYNC (p);
1759
1760 /* Call to collector. */
1761 p += gen_call (p, collector, is_64, is_opd);
1762
1763 /* Simply write 0 to release the lock. */
1764 p += gen_limm (p, 3, lockaddr, is_64);
1765 p += gen_limm (p, 4, 0, is_64);
1766 p += GEN_LWSYNC (p);
1767 p += GEN_STORE (p, 4, 3, 0, is_64);
1768
1769 /* Restore stack and registers. */
1770 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1771 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1772 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1773 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1774 p += GEN_MTCR (p, 3); /* mtcr r3 */
1775 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1776 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1777 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1778
1779 /* Restore GPRs. */
1780 for (j = 2; j < 32; j++)
1781 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1782 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1783 /* Restore SP. */
1784 p += GEN_ADDI (p, 1, 1, frame_size);
1785
1786 /* Flush instructions to inferior memory. */
1787 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1788
1789 /* Now, insert the original instruction to execute in the jump pad. */
1790 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1791 *adjusted_insn_addr_end = *adjusted_insn_addr;
1792 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1793
1794 /* Verify the relocation size. If should be 4 for normal copy,
1795 8 or 12 for some conditional branch. */
1796 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1797 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1798 {
1799 sprintf (err, "E.Unexpected instruction length = %d"
1800 "when relocate instruction.",
1801 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1802 return 1;
1803 }
1804
1805 buildaddr = *adjusted_insn_addr_end;
1806 p = buf;
1807 /* Finally, write a jump back to the program. */
1808 offset = (tpaddr + 4) - buildaddr;
1809 if (offset >= (1 << 25) || offset < -(1 << 25))
1810 {
1811 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1812 "(offset 0x%x > 26-bit).", offset);
1813 return 1;
1814 }
1815 /* b <tpaddr+4> */
1816 p += GEN_B (p, offset);
1817 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1818 *jump_entry = buildaddr + (p - buf) * 4;
1819
1820 /* The jump pad is now built. Wire in a jump to our jump pad. This
1821 is always done last (by our caller actually), so that we can
1822 install fast tracepoints with threads running. This relies on
1823 the agent's atomic write support. */
1824 offset = entryaddr - tpaddr;
1825 if (offset >= (1 << 25) || offset < -(1 << 25))
1826 {
1827 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1828 "(offset 0x%x > 26-bit).", offset);
1829 return 1;
1830 }
1831 /* b <jentry> */
1832 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1833 *jjump_pad_insn_size = 4;
1834
1835 return 0;
1836}
1837
1838/* Returns the minimum instruction length for installing a tracepoint. */
1839
1840static int
1841ppc_get_min_fast_tracepoint_insn_len (void)
1842{
1843 return 4;
1844}
1845
14e2b6d9
MK		 1846/* Emits a given buffer into the target at current_insn_ptr. Length
1847 is in units of 32-bit words. */
1848
1849static void
1850emit_insns (uint32_t *buf, int n)
1851{
1852 n = n * sizeof (uint32_t);
1853 write_inferior_memory (current_insn_ptr, (unsigned char *) buf, n);
1854 current_insn_ptr += n;
1855}
1856
1857#define __EMIT_ASM(NAME, INSNS) \
1858 do \
1859 { \
1860 extern uint32_t start_bcax_ ## NAME []; \
1861 extern uint32_t end_bcax_ ## NAME []; \
1862 emit_insns (start_bcax_ ## NAME, \
1863 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1864 __asm__ (".section .text.__ppcbcax\n\t" \
1865 "start_bcax_" #NAME ":\n\t" \
1866 INSNS "\n\t" \
1867 "end_bcax_" #NAME ":\n\t" \
1868 ".previous\n\t"); \
1869 } while (0)
1870
1871#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1872#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1873
1874/*
1875
1876 Bytecode execution stack frame - 32-bit
1877
1878 | LR save area (SP + 4)
1879 SP' -> +- Back chain (SP + 0)
1880 | Save r31 for access saved arguments
1881 | Save r30 for bytecode stack pointer
1882 | Save r4 for incoming argument *value
1883 | Save r3 for incoming argument regs
1884 r30 -> +- Bytecode execution stack
1885 |
1886 | 64-byte (8 doublewords) at initial.
1887 | Expand stack as needed.
1888 |
1889 +-
1890 | Some padding for minimum stack frame and 16-byte alignment.
1891 | 16 bytes.
1892 SP +- Back-chain (SP')
1893
1894 initial frame size
1895 = 16 + (4 * 4) + 64
1896 = 96
1897
1898 r30 is the stack-pointer for bytecode machine.
1899 It should point to next-empty, so we can use LDU for pop.
1900 r3 is used for cache of the high part of TOP value.
1901 It was the first argument, pointer to regs.
1902 r4 is used for cache of the low part of TOP value.
1903 It was the second argument, pointer to the result.
1904 We should set *result = TOP after leaving this function.
1905
1906 Note:
1907 * To restore stack at epilogue
1908 => sp = r31
1909 * To check stack is big enough for bytecode execution.
1910 => r30 - 8 > SP + 8
1911 * To return execution result.
1912 => 0(r4) = TOP
1913
1914 */
1915
1916/* Regardless of endian, register 3 is always high part, 4 is low part.
1917 These defines are used when the register pair is stored/loaded.
1918 Likewise, to simplify code, have a similiar define for 5:6. */
1919
1920#if __BYTE_ORDER == __LITTLE_ENDIAN
1921#define TOP_FIRST "4"
1922#define TOP_SECOND "3"
1923#define TMP_FIRST "6"
1924#define TMP_SECOND "5"
1925#else
1926#define TOP_FIRST "3"
1927#define TOP_SECOND "4"
1928#define TMP_FIRST "5"
1929#define TMP_SECOND "6"
1930#endif
1931
1932/* Emit prologue in inferior memory. See above comments. */
1933
1934static void
1935ppc_emit_prologue (void)
1936{
1937 EMIT_ASM (/* Save return address. */
1938 "mflr 0 \n"
1939 "stw 0, 4(1) \n"
1940 /* Adjust SP. 96 is the initial frame size. */
1941 "stwu 1, -96(1) \n"
1942 /* Save r30 and incoming arguments. */
1943 "stw 31, 96-4(1) \n"
1944 "stw 30, 96-8(1) \n"
1945 "stw 4, 96-12(1) \n"
1946 "stw 3, 96-16(1) \n"
1947 /* Point r31 to original r1 for access arguments. */
1948 "addi 31, 1, 96 \n"
1949 /* Set r30 to pointing stack-top. */
1950 "addi 30, 1, 64 \n"
1951 /* Initial r3/TOP to 0. */
1952 "li 3, 0 \n"
1953 "li 4, 0 \n");
1954}
1955
1956/* Emit epilogue in inferior memory. See above comments. */
1957
1958static void
1959ppc_emit_epilogue (void)
1960{
1961 EMIT_ASM (/* *result = TOP */
1962 "lwz 5, -12(31) \n"
1963 "stw " TOP_FIRST ", 0(5) \n"
1964 "stw " TOP_SECOND ", 4(5) \n"
1965 /* Restore registers. */
1966 "lwz 31, -4(31) \n"
1967 "lwz 30, -8(31) \n"
1968 /* Restore SP. */
1969 "lwz 1, 0(1) \n"
1970 /* Restore LR. */
1971 "lwz 0, 4(1) \n"
1972 /* Return 0 for no-error. */
1973 "li 3, 0 \n"
1974 "mtlr 0 \n"
1975 "blr \n");
1976}
1977
1978/* TOP = stack[--sp] + TOP */
1979
1980static void
1981ppc_emit_add (void)
1982{
1983 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1984 "lwz " TMP_SECOND ", 4(30)\n"
1985 "addc 4, 6, 4 \n"
1986 "adde 3, 5, 3 \n");
1987}
1988
1989/* TOP = stack[--sp] - TOP */
1990
1991static void
1992ppc_emit_sub (void)
1993{
1994 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1995 "lwz " TMP_SECOND ", 4(30) \n"
1996 "subfc 4, 4, 6 \n"
1997 "subfe 3, 3, 5 \n");
1998}
1999
2000/* TOP = stack[--sp] * TOP */
2001
2002static void
2003ppc_emit_mul (void)
2004{
2005 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2006 "lwz " TMP_SECOND ", 4(30) \n"
2007 "mulhwu 7, 6, 4 \n"
2008 "mullw 3, 6, 3 \n"
2009 "mullw 5, 4, 5 \n"
2010 "mullw 4, 6, 4 \n"
2011 "add 3, 5, 3 \n"
2012 "add 3, 7, 3 \n");
2013}
2014
2015/* TOP = stack[--sp] << TOP */
2016
2017static void
2018ppc_emit_lsh (void)
2019{
2020 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2021 "lwz " TMP_SECOND ", 4(30) \n"
2022 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2023 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2024 "slw 5, 5, 4\n" /* Shift high part left */
2025 "slw 4, 6, 4\n" /* Shift low part left */
2026 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
2027 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
2028 "or 3, 5, 3\n"
2029 "or 3, 7, 3\n"); /* Assemble high part */
2030}
2031
2032/* Top = stack[--sp] >> TOP
2033 (Arithmetic shift right) */
2034
2035static void
2036ppc_emit_rsh_signed (void)
2037{
2038 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2039 "lwz " TMP_SECOND ", 4(30) \n"
2040 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2041 "sraw 3, 5, 4\n" /* Shift high part right */
2042 "cmpwi 7, 1\n"
2043 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
2044 "sraw 4, 5, 7\n" /* Shift high to low */
2045 "b 2f\n"
2046 "1:\n"
2047 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
2048 "srw 4, 6, 4\n" /* Shift low part right */
2049 "slw 5, 5, 7\n" /* Shift high to low */
2050 "or 4, 4, 5\n" /* Assemble low part */
2051 "2:\n");
2052}
2053
2054/* Top = stack[--sp] >> TOP
2055 (Logical shift right) */
2056
2057static void
2058ppc_emit_rsh_unsigned (void)
2059{
2060 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2061 "lwz " TMP_SECOND ", 4(30) \n"
2062 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2063 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2064 "srw 6, 6, 4\n" /* Shift low part right */
2065 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
2066 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
2067 "or 6, 6, 3\n"
2068 "srw 3, 5, 4\n" /* Shift high part right */
2069 "or 4, 6, 7\n"); /* Assemble low part */
2070}
2071
2072/* Emit code for signed-extension specified by ARG. */
2073
2074static void
2075ppc_emit_ext (int arg)
2076{
2077 switch (arg)
2078 {
2079 case 8:
2080 EMIT_ASM ("extsb 4, 4\n"
2081 "srawi 3, 4, 31");
2082 break;
2083 case 16:
2084 EMIT_ASM ("extsh 4, 4\n"
2085 "srawi 3, 4, 31");
2086 break;
2087 case 32:
2088 EMIT_ASM ("srawi 3, 4, 31");
2089 break;
2090 default:
2091 emit_error = 1;
2092 }
2093}
2094
2095/* Emit code for zero-extension specified by ARG. */
2096
2097static void
2098ppc_emit_zero_ext (int arg)
2099{
2100 switch (arg)
2101 {
2102 case 8:
2103 EMIT_ASM ("clrlwi 4,4,24\n"
2104 "li 3, 0\n");
2105 break;
2106 case 16:
2107 EMIT_ASM ("clrlwi 4,4,16\n"
2108 "li 3, 0\n");
2109 break;
2110 case 32:
2111 EMIT_ASM ("li 3, 0");
2112 break;
2113 default:
2114 emit_error = 1;
2115 }
2116}
2117
2118/* TOP = !TOP
2119 i.e., TOP = (TOP == 0) ? 1 : 0; */
2120
2121static void
2122ppc_emit_log_not (void)
2123{
2124 EMIT_ASM ("or 4, 3, 4 \n"
2125 "cntlzw 4, 4 \n"
2126 "srwi 4, 4, 5 \n"
2127 "li 3, 0 \n");
2128}
2129
2130/* TOP = stack[--sp] & TOP */
2131
2132static void
2133ppc_emit_bit_and (void)
2134{
2135 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2136 "lwz " TMP_SECOND ", 4(30) \n"
2137 "and 4, 6, 4 \n"
2138 "and 3, 5, 3 \n");
2139}
2140
2141/* TOP = stack[--sp] | TOP */
2142
2143static void
2144ppc_emit_bit_or (void)
2145{
2146 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2147 "lwz " TMP_SECOND ", 4(30) \n"
2148 "or 4, 6, 4 \n"
2149 "or 3, 5, 3 \n");
2150}
2151
2152/* TOP = stack[--sp] ^ TOP */
2153
2154static void
2155ppc_emit_bit_xor (void)
2156{
2157 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2158 "lwz " TMP_SECOND ", 4(30) \n"
2159 "xor 4, 6, 4 \n"
2160 "xor 3, 5, 3 \n");
2161}
2162
2163/* TOP = ~TOP
2164 i.e., TOP = ~(TOP | TOP) */
2165
2166static void
2167ppc_emit_bit_not (void)
2168{
2169 EMIT_ASM ("nor 3, 3, 3 \n"
2170 "nor 4, 4, 4 \n");
2171}
2172
2173/* TOP = stack[--sp] == TOP */
2174
2175static void
2176ppc_emit_equal (void)
2177{
2178 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2179 "lwz " TMP_SECOND ", 4(30) \n"
2180 "xor 4, 6, 4 \n"
2181 "xor 3, 5, 3 \n"
2182 "or 4, 3, 4 \n"
2183 "cntlzw 4, 4 \n"
2184 "srwi 4, 4, 5 \n"
2185 "li 3, 0 \n");
2186}
2187
2188/* TOP = stack[--sp] < TOP
2189 (Signed comparison) */
2190
2191static void
2192ppc_emit_less_signed (void)
2193{
2194 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2195 "lwz " TMP_SECOND ", 4(30) \n"
2196 "cmplw 6, 6, 4 \n"
2197 "cmpw 7, 5, 3 \n"
2198 /* CR6 bit 0 = low less and high equal */
2199 "crand 6*4+0, 6*4+0, 7*4+2\n"
2200 /* CR7 bit 0 = (low less and high equal) or high less */
2201 "cror 7*4+0, 7*4+0, 6*4+0\n"
2202 "mfcr 4 \n"
2203 "rlwinm 4, 4, 29, 31, 31 \n"
2204 "li 3, 0 \n");
2205}
2206
2207/* TOP = stack[--sp] < TOP
2208 (Unsigned comparison) */
2209
2210static void
2211ppc_emit_less_unsigned (void)
2212{
2213 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2214 "lwz " TMP_SECOND ", 4(30) \n"
2215 "cmplw 6, 6, 4 \n"
2216 "cmplw 7, 5, 3 \n"
2217 /* CR6 bit 0 = low less and high equal */
2218 "crand 6*4+0, 6*4+0, 7*4+2\n"
2219 /* CR7 bit 0 = (low less and high equal) or high less */
2220 "cror 7*4+0, 7*4+0, 6*4+0\n"
2221 "mfcr 4 \n"
2222 "rlwinm 4, 4, 29, 31, 31 \n"
2223 "li 3, 0 \n");
2224}
2225
2226/* Access the memory address in TOP in size of SIZE.
2227 Zero-extend the read value. */
2228
2229static void
2230ppc_emit_ref (int size)
2231{
2232 switch (size)
2233 {
2234 case 1:
2235 EMIT_ASM ("lbz 4, 0(4)\n"
2236 "li 3, 0");
2237 break;
2238 case 2:
2239 EMIT_ASM ("lhz 4, 0(4)\n"
2240 "li 3, 0");
2241 break;
2242 case 4:
2243 EMIT_ASM ("lwz 4, 0(4)\n"
2244 "li 3, 0");
2245 break;
2246 case 8:
2247 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2248 EMIT_ASM ("lwz 3, 4(4)\n"
2249 "lwz 4, 0(4)");
2250 else
2251 EMIT_ASM ("lwz 3, 0(4)\n"
2252 "lwz 4, 4(4)");
2253 break;
2254 }
2255}
2256
2257/* TOP = NUM */
2258
2259static void
2260ppc_emit_const (LONGEST num)
2261{
2262 uint32_t buf[10];
2263 uint32_t *p = buf;
2264
2265 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
2266 p += gen_limm (p, 4, num & 0xffffffff, 0);
2267
2268 emit_insns (buf, p - buf);
2269 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2270}
2271
2272/* Set TOP to the value of register REG by calling get_raw_reg function
2273 with two argument, collected buffer and register number. */
2274
2275static void
2276ppc_emit_reg (int reg)
2277{
2278 uint32_t buf[13];
2279 uint32_t *p = buf;
2280
2281 /* fctx->regs is passed in r3 and then saved in -16(31). */
2282 p += GEN_LWZ (p, 3, 31, -16);
2283 p += GEN_LI (p, 4, reg); /* li r4, reg */
2284 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
2285
2286 emit_insns (buf, p - buf);
2287 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2288
2289 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2290 {
2291 EMIT_ASM ("mr 5, 4\n"
2292 "mr 4, 3\n"
2293 "mr 3, 5\n");
2294 }
2295}
2296
2297/* TOP = stack[--sp] */
2298
2299static void
2300ppc_emit_pop (void)
2301{
2302 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
2303 "lwz " TOP_SECOND ", 4(30) \n");
2304}
2305
2306/* stack[sp++] = TOP
2307
2308 Because we may use up bytecode stack, expand 8 doublewords more
2309 if needed. */
2310
2311static void
2312ppc_emit_stack_flush (void)
2313{
2314 /* Make sure bytecode stack is big enough before push.
2315 Otherwise, expand 64-byte more. */
2316
2317 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2318 " stw " TOP_SECOND ", 4(30)\n"
2319 " addi 5, 30, -(8 + 8) \n"
2320 " cmpw 7, 5, 1 \n"
2321 " bgt 7, 1f \n"
2322 " stwu 31, -64(1) \n"
2323 "1:addi 30, 30, -8 \n");
2324}
2325
2326/* Swap TOP and stack[sp-1] */
2327
2328static void
2329ppc_emit_swap (void)
2330{
2331 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2332 "lwz " TMP_SECOND ", 12(30) \n"
2333 "stw " TOP_FIRST ", 8(30) \n"
2334 "stw " TOP_SECOND ", 12(30) \n"
2335 "mr 3, 5 \n"
2336 "mr 4, 6 \n");
2337}
2338
2339/* Discard N elements in the stack. Also used for ppc64. */
2340
2341static void
2342ppc_emit_stack_adjust (int n)
2343{
2344 uint32_t buf[6];
2345 uint32_t *p = buf;
2346
2347 n = n << 3;
2348 if ((n >> 15) != 0)
2349 {
2350 emit_error = 1;
2351 return;
2352 }
2353
2354 p += GEN_ADDI (p, 30, 30, n);
2355
2356 emit_insns (buf, p - buf);
2357 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2358}
2359
2360/* Call function FN. */
2361
2362static void
2363ppc_emit_call (CORE_ADDR fn)
2364{
2365 uint32_t buf[11];
2366 uint32_t *p = buf;
2367
2368 p += gen_call (p, fn, 0, 0);
2369
2370 emit_insns (buf, p - buf);
2371 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2372}
2373
2374/* FN's prototype is `LONGEST(*fn)(int)'.
2375 TOP = fn (arg1)
2376 */
2377
2378static void
2379ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2380{
2381 uint32_t buf[15];
2382 uint32_t *p = buf;
2383
2384 /* Setup argument. arg1 is a 16-bit value. */
2385 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2386 p += gen_call (p, fn, 0, 0);
2387
2388 emit_insns (buf, p - buf);
2389 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2390
2391 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2392 {
2393 EMIT_ASM ("mr 5, 4\n"
2394 "mr 4, 3\n"
2395 "mr 3, 5\n");
2396 }
2397}
2398
2399/* FN's prototype is `void(*fn)(int,LONGEST)'.
2400 fn (arg1, TOP)
2401
2402 TOP should be preserved/restored before/after the call. */
2403
2404static void
2405ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2406{
2407 uint32_t buf[21];
2408 uint32_t *p = buf;
2409
2410 /* Save TOP. 0(30) is next-empty. */
2411 p += GEN_STW (p, 3, 30, 0);
2412 p += GEN_STW (p, 4, 30, 4);
2413
2414 /* Setup argument. arg1 is a 16-bit value. */
2415 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2416 {
2417 p += GEN_MR (p, 5, 4);
2418 p += GEN_MR (p, 6, 3);
2419 }
2420 else
2421 {
2422 p += GEN_MR (p, 5, 3);
2423 p += GEN_MR (p, 6, 4);
2424 }
2425 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2426 p += gen_call (p, fn, 0, 0);
2427
2428 /* Restore TOP */
2429 p += GEN_LWZ (p, 3, 30, 0);
2430 p += GEN_LWZ (p, 4, 30, 4);
2431
2432 emit_insns (buf, p - buf);
2433 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2434}
2435
2436/* Note in the following goto ops:
2437
2438 When emitting goto, the target address is later relocated by
2439 write_goto_address. OFFSET_P is the offset of the branch instruction
2440 in the code sequence, and SIZE_P is how to relocate the instruction,
2441 recognized by ppc_write_goto_address. In current implementation,
2442 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2443 */
2444
2445/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2446
2447static void
2448ppc_emit_if_goto (int *offset_p, int *size_p)
2449{
2450 EMIT_ASM ("or. 3, 3, 4 \n"
2451 "lwzu " TOP_FIRST ", 8(30) \n"
2452 "lwz " TOP_SECOND ", 4(30) \n"
2453 "1:bne 0, 1b \n");
2454
2455 if (offset_p)
2456 *offset_p = 12;
2457 if (size_p)
2458 *size_p = 14;
2459}
2460
2461/* Unconditional goto. Also used for ppc64. */
2462
2463static void
2464ppc_emit_goto (int *offset_p, int *size_p)
2465{
2466 EMIT_ASM ("1:b 1b");
2467
2468 if (offset_p)
2469 *offset_p = 0;
2470 if (size_p)
2471 *size_p = 24;
2472}
2473
2474/* Goto if stack[--sp] == TOP */
2475
2476static void
2477ppc_emit_eq_goto (int *offset_p, int *size_p)
2478{
2479 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2480 "lwz " TMP_SECOND ", 4(30) \n"
2481 "xor 4, 6, 4 \n"
2482 "xor 3, 5, 3 \n"
2483 "or. 3, 3, 4 \n"
2484 "lwzu " TOP_FIRST ", 8(30) \n"
2485 "lwz " TOP_SECOND ", 4(30) \n"
2486 "1:beq 0, 1b \n");
2487
2488 if (offset_p)
2489 *offset_p = 28;
2490 if (size_p)
2491 *size_p = 14;
2492}
2493
2494/* Goto if stack[--sp] != TOP */
2495
2496static void
2497ppc_emit_ne_goto (int *offset_p, int *size_p)
2498{
2499 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2500 "lwz " TMP_SECOND ", 4(30) \n"
2501 "xor 4, 6, 4 \n"
2502 "xor 3, 5, 3 \n"
2503 "or. 3, 3, 4 \n"
2504 "lwzu " TOP_FIRST ", 8(30) \n"
2505 "lwz " TOP_SECOND ", 4(30) \n"
2506 "1:bne 0, 1b \n");
2507
2508 if (offset_p)
2509 *offset_p = 28;
2510 if (size_p)
2511 *size_p = 14;
2512}
2513
2514/* Goto if stack[--sp] < TOP */
2515
2516static void
2517ppc_emit_lt_goto (int *offset_p, int *size_p)
2518{
2519 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2520 "lwz " TMP_SECOND ", 4(30) \n"
2521 "cmplw 6, 6, 4 \n"
2522 "cmpw 7, 5, 3 \n"
2523 /* CR6 bit 0 = low less and high equal */
2524 "crand 6*4+0, 6*4+0, 7*4+2\n"
2525 /* CR7 bit 0 = (low less and high equal) or high less */
2526 "cror 7*4+0, 7*4+0, 6*4+0\n"
2527 "lwzu " TOP_FIRST ", 8(30) \n"
2528 "lwz " TOP_SECOND ", 4(30)\n"
2529 "1:blt 7, 1b \n");
2530
2531 if (offset_p)
2532 *offset_p = 32;
2533 if (size_p)
2534 *size_p = 14;
2535}
2536
2537/* Goto if stack[--sp] <= TOP */
2538
2539static void
2540ppc_emit_le_goto (int *offset_p, int *size_p)
2541{
2542 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2543 "lwz " TMP_SECOND ", 4(30) \n"
2544 "cmplw 6, 6, 4 \n"
2545 "cmpw 7, 5, 3 \n"
2546 /* CR6 bit 0 = low less/equal and high equal */
2547 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2548 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2549 "cror 7*4+0, 7*4+0, 6*4+0\n"
2550 "lwzu " TOP_FIRST ", 8(30) \n"
2551 "lwz " TOP_SECOND ", 4(30)\n"
2552 "1:blt 7, 1b \n");
2553
2554 if (offset_p)
2555 *offset_p = 32;
2556 if (size_p)
2557 *size_p = 14;
2558}
2559
2560/* Goto if stack[--sp] > TOP */
2561
2562static void
2563ppc_emit_gt_goto (int *offset_p, int *size_p)
2564{
2565 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2566 "lwz " TMP_SECOND ", 4(30) \n"
2567 "cmplw 6, 6, 4 \n"
2568 "cmpw 7, 5, 3 \n"
2569 /* CR6 bit 0 = low greater and high equal */
2570 "crand 6*4+0, 6*4+1, 7*4+2\n"
2571 /* CR7 bit 0 = (low greater and high equal) or high greater */
2572 "cror 7*4+0, 7*4+1, 6*4+0\n"
2573 "lwzu " TOP_FIRST ", 8(30) \n"
2574 "lwz " TOP_SECOND ", 4(30)\n"
2575 "1:blt 7, 1b \n");
2576
2577 if (offset_p)
2578 *offset_p = 32;
2579 if (size_p)
2580 *size_p = 14;
2581}
2582
2583/* Goto if stack[--sp] >= TOP */
2584
2585static void
2586ppc_emit_ge_goto (int *offset_p, int *size_p)
2587{
2588 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2589 "lwz " TMP_SECOND ", 4(30) \n"
2590 "cmplw 6, 6, 4 \n"
2591 "cmpw 7, 5, 3 \n"
2592 /* CR6 bit 0 = low ge and high equal */
2593 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2594 /* CR7 bit 0 = (low ge and high equal) or high greater */
2595 "cror 7*4+0, 7*4+1, 6*4+0\n"
2596 "lwzu " TOP_FIRST ", 8(30)\n"
2597 "lwz " TOP_SECOND ", 4(30)\n"
2598 "1:blt 7, 1b \n");
2599
2600 if (offset_p)
2601 *offset_p = 32;
2602 if (size_p)
2603 *size_p = 14;
2604}
2605
2606/* Relocate previous emitted branch instruction. FROM is the address
2607 of the branch instruction, TO is the goto target address, and SIZE
2608 if the value we set by *SIZE_P before. Currently, it is either
2609 24 or 14 of branch and conditional-branch instruction.
2610 Also used for ppc64. */
2611
2612static void
2613ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2614{
2615 long rel = to - from;
2616 uint32_t insn;
2617 int opcd;
2618
2619 read_inferior_memory (from, (unsigned char *) &insn, 4);
2620 opcd = (insn >> 26) & 0x3f;
2621
2622 switch (size)
2623 {
2624 case 14:
2625 if (opcd != 16
2626 || (rel >= (1 << 15) || rel < -(1 << 15)))
2627 emit_error = 1;
2628 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2629 break;
2630 case 24:
2631 if (opcd != 18
2632 || (rel >= (1 << 25) || rel < -(1 << 25)))
2633 emit_error = 1;
2634 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2635 break;
2636 default:
2637 emit_error = 1;
2638 }
2639
2640 if (!emit_error)
2641 write_inferior_memory (from, (unsigned char *) &insn, 4);
2642}
2643
2644/* Table of emit ops for 32-bit. */
2645
2646static struct emit_ops ppc_emit_ops_impl =
2647{
2648 ppc_emit_prologue,
2649 ppc_emit_epilogue,
2650 ppc_emit_add,
2651 ppc_emit_sub,
2652 ppc_emit_mul,
2653 ppc_emit_lsh,
2654 ppc_emit_rsh_signed,
2655 ppc_emit_rsh_unsigned,
2656 ppc_emit_ext,
2657 ppc_emit_log_not,
2658 ppc_emit_bit_and,
2659 ppc_emit_bit_or,
2660 ppc_emit_bit_xor,
2661 ppc_emit_bit_not,
2662 ppc_emit_equal,
2663 ppc_emit_less_signed,
2664 ppc_emit_less_unsigned,
2665 ppc_emit_ref,
2666 ppc_emit_if_goto,
2667 ppc_emit_goto,
2668 ppc_write_goto_address,
2669 ppc_emit_const,
2670 ppc_emit_call,
2671 ppc_emit_reg,
2672 ppc_emit_pop,
2673 ppc_emit_stack_flush,
2674 ppc_emit_zero_ext,
2675 ppc_emit_swap,
2676 ppc_emit_stack_adjust,
2677 ppc_emit_int_call_1,
2678 ppc_emit_void_call_2,
2679 ppc_emit_eq_goto,
2680 ppc_emit_ne_goto,
2681 ppc_emit_lt_goto,
2682 ppc_emit_le_goto,
2683 ppc_emit_gt_goto,
2684 ppc_emit_ge_goto
2685};
2686
2687#ifdef __powerpc64__
2688
2689/*
2690
2691 Bytecode execution stack frame - 64-bit
2692
2693 | LR save area (SP + 16)
2694 | CR save area (SP + 8)
2695 SP' -> +- Back chain (SP + 0)
2696 | Save r31 for access saved arguments
2697 | Save r30 for bytecode stack pointer
2698 | Save r4 for incoming argument *value
2699 | Save r3 for incoming argument regs
2700 r30 -> +- Bytecode execution stack
2701 |
2702 | 64-byte (8 doublewords) at initial.
2703 | Expand stack as needed.
2704 |
2705 +-
2706 | Some padding for minimum stack frame.
2707 | 112 for ELFv1.
2708 SP +- Back-chain (SP')
2709
2710 initial frame size
2711 = 112 + (4 * 8) + 64
2712 = 208
2713
2714 r30 is the stack-pointer for bytecode machine.
2715 It should point to next-empty, so we can use LDU for pop.
2716 r3 is used for cache of TOP value.
2717 It was the first argument, pointer to regs.
2718 r4 is the second argument, pointer to the result.
2719 We should set *result = TOP after leaving this function.
2720
2721 Note:
2722 * To restore stack at epilogue
2723 => sp = r31
2724 * To check stack is big enough for bytecode execution.
2725 => r30 - 8 > SP + 112
2726 * To return execution result.
2727 => 0(r4) = TOP
2728
2729 */
2730
2731/* Emit prologue in inferior memory. See above comments. */
2732
2733static void
2734ppc64v1_emit_prologue (void)
2735{
2736 /* On ELFv1, function pointers really point to function descriptor,
2737 so emit one here. We don't care about contents of words 1 and 2,
2738 so let them just overlap out code. */
2739 uint64_t opd = current_insn_ptr + 8;
2740 uint32_t buf[2];
2741
2742 /* Mind the strict aliasing rules. */
2743 memcpy (buf, &opd, sizeof buf);
2744 emit_insns(buf, 2);
2745 EMIT_ASM (/* Save return address. */
2746 "mflr 0 \n"
2747 "std 0, 16(1) \n"
2748 /* Save r30 and incoming arguments. */
2749 "std 31, -8(1) \n"
2750 "std 30, -16(1) \n"
2751 "std 4, -24(1) \n"
2752 "std 3, -32(1) \n"
2753 /* Point r31 to current r1 for access arguments. */
2754 "mr 31, 1 \n"
2755 /* Adjust SP. 208 is the initial frame size. */
2756 "stdu 1, -208(1) \n"
2757 /* Set r30 to pointing stack-top. */
2758 "addi 30, 1, 168 \n"
2759 /* Initial r3/TOP to 0. */
2760 "li 3, 0 \n");
2761}
2762
2763/* Emit prologue in inferior memory. See above comments. */
2764
2765static void
2766ppc64v2_emit_prologue (void)
2767{
2768 EMIT_ASM (/* Save return address. */
2769 "mflr 0 \n"
2770 "std 0, 16(1) \n"
2771 /* Save r30 and incoming arguments. */
2772 "std 31, -8(1) \n"
2773 "std 30, -16(1) \n"
2774 "std 4, -24(1) \n"
2775 "std 3, -32(1) \n"
2776 /* Point r31 to current r1 for access arguments. */
2777 "mr 31, 1 \n"
2778 /* Adjust SP. 208 is the initial frame size. */
2779 "stdu 1, -208(1) \n"
2780 /* Set r30 to pointing stack-top. */
2781 "addi 30, 1, 168 \n"
2782 /* Initial r3/TOP to 0. */
2783 "li 3, 0 \n");
2784}
2785
2786/* Emit epilogue in inferior memory. See above comments. */
2787
2788static void
2789ppc64_emit_epilogue (void)
2790{
2791 EMIT_ASM (/* Restore SP. */
2792 "ld 1, 0(1) \n"
2793 /* *result = TOP */
2794 "ld 4, -24(1) \n"
2795 "std 3, 0(4) \n"
2796 /* Restore registers. */
2797 "ld 31, -8(1) \n"
2798 "ld 30, -16(1) \n"
2799 /* Restore LR. */
2800 "ld 0, 16(1) \n"
2801 /* Return 0 for no-error. */
2802 "li 3, 0 \n"
2803 "mtlr 0 \n"
2804 "blr \n");
2805}
2806
2807/* TOP = stack[--sp] + TOP */
2808
2809static void
2810ppc64_emit_add (void)
2811{
2812 EMIT_ASM ("ldu 4, 8(30) \n"
2813 "add 3, 4, 3 \n");
2814}
2815
2816/* TOP = stack[--sp] - TOP */
2817
2818static void
2819ppc64_emit_sub (void)
2820{
2821 EMIT_ASM ("ldu 4, 8(30) \n"
2822 "sub 3, 4, 3 \n");
2823}
2824
2825/* TOP = stack[--sp] * TOP */
2826
2827static void
2828ppc64_emit_mul (void)
2829{
2830 EMIT_ASM ("ldu 4, 8(30) \n"
2831 "mulld 3, 4, 3 \n");
2832}
2833
2834/* TOP = stack[--sp] << TOP */
2835
2836static void
2837ppc64_emit_lsh (void)
2838{
2839 EMIT_ASM ("ldu 4, 8(30) \n"
2840 "sld 3, 4, 3 \n");
2841}
2842
2843/* Top = stack[--sp] >> TOP
2844 (Arithmetic shift right) */
2845
2846static void
2847ppc64_emit_rsh_signed (void)
2848{
2849 EMIT_ASM ("ldu 4, 8(30) \n"
2850 "srad 3, 4, 3 \n");
2851}
2852
2853/* Top = stack[--sp] >> TOP
2854 (Logical shift right) */
2855
2856static void
2857ppc64_emit_rsh_unsigned (void)
2858{
2859 EMIT_ASM ("ldu 4, 8(30) \n"
2860 "srd 3, 4, 3 \n");
2861}
2862
2863/* Emit code for signed-extension specified by ARG. */
2864
2865static void
2866ppc64_emit_ext (int arg)
2867{
2868 switch (arg)
2869 {
2870 case 8:
2871 EMIT_ASM ("extsb 3, 3");
2872 break;
2873 case 16:
2874 EMIT_ASM ("extsh 3, 3");
2875 break;
2876 case 32:
2877 EMIT_ASM ("extsw 3, 3");
2878 break;
2879 default:
2880 emit_error = 1;
2881 }
2882}
2883
2884/* Emit code for zero-extension specified by ARG. */
2885
2886static void
2887ppc64_emit_zero_ext (int arg)
2888{
2889 switch (arg)
2890 {
2891 case 8:
2892 EMIT_ASM ("rldicl 3,3,0,56");
2893 break;
2894 case 16:
2895 EMIT_ASM ("rldicl 3,3,0,48");
2896 break;
2897 case 32:
2898 EMIT_ASM ("rldicl 3,3,0,32");
2899 break;
2900 default:
2901 emit_error = 1;
2902 }
2903}
2904
2905/* TOP = !TOP
2906 i.e., TOP = (TOP == 0) ? 1 : 0; */
2907
2908static void
2909ppc64_emit_log_not (void)
2910{
2911 EMIT_ASM ("cntlzd 3, 3 \n"
2912 "srdi 3, 3, 6 \n");
2913}
2914
2915/* TOP = stack[--sp] & TOP */
2916
2917static void
2918ppc64_emit_bit_and (void)
2919{
2920 EMIT_ASM ("ldu 4, 8(30) \n"
2921 "and 3, 4, 3 \n");
2922}
2923
2924/* TOP = stack[--sp] | TOP */
2925
2926static void
2927ppc64_emit_bit_or (void)
2928{
2929 EMIT_ASM ("ldu 4, 8(30) \n"
2930 "or 3, 4, 3 \n");
2931}
2932
2933/* TOP = stack[--sp] ^ TOP */
2934
2935static void
2936ppc64_emit_bit_xor (void)
2937{
2938 EMIT_ASM ("ldu 4, 8(30) \n"
2939 "xor 3, 4, 3 \n");
2940}
2941
2942/* TOP = ~TOP
2943 i.e., TOP = ~(TOP | TOP) */
2944
2945static void
2946ppc64_emit_bit_not (void)
2947{
2948 EMIT_ASM ("nor 3, 3, 3 \n");
2949}
2950
2951/* TOP = stack[--sp] == TOP */
2952
2953static void
2954ppc64_emit_equal (void)
2955{
2956 EMIT_ASM ("ldu 4, 8(30) \n"
2957 "xor 3, 3, 4 \n"
2958 "cntlzd 3, 3 \n"
2959 "srdi 3, 3, 6 \n");
2960}
2961
2962/* TOP = stack[--sp] < TOP
2963 (Signed comparison) */
2964
2965static void
2966ppc64_emit_less_signed (void)
2967{
2968 EMIT_ASM ("ldu 4, 8(30) \n"
2969 "cmpd 7, 4, 3 \n"
2970 "mfcr 3 \n"
2971 "rlwinm 3, 3, 29, 31, 31 \n");
2972}
2973
2974/* TOP = stack[--sp] < TOP
2975 (Unsigned comparison) */
2976
2977static void
2978ppc64_emit_less_unsigned (void)
2979{
2980 EMIT_ASM ("ldu 4, 8(30) \n"
2981 "cmpld 7, 4, 3 \n"
2982 "mfcr 3 \n"
2983 "rlwinm 3, 3, 29, 31, 31 \n");
2984}
2985
2986/* Access the memory address in TOP in size of SIZE.
2987 Zero-extend the read value. */
2988
2989static void
2990ppc64_emit_ref (int size)
2991{
2992 switch (size)
2993 {
2994 case 1:
2995 EMIT_ASM ("lbz 3, 0(3)");
2996 break;
2997 case 2:
2998 EMIT_ASM ("lhz 3, 0(3)");
2999 break;
3000 case 4:
3001 EMIT_ASM ("lwz 3, 0(3)");
3002 break;
3003 case 8:
3004 EMIT_ASM ("ld 3, 0(3)");
3005 break;
3006 }
3007}
3008
3009/* TOP = NUM */
3010
3011static void
3012ppc64_emit_const (LONGEST num)
3013{
3014 uint32_t buf[5];
3015 uint32_t *p = buf;
3016
3017 p += gen_limm (p, 3, num, 1);
3018
3019 emit_insns (buf, p - buf);
3020 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3021}
3022
3023/* Set TOP to the value of register REG by calling get_raw_reg function
3024 with two argument, collected buffer and register number. */
3025
3026static void
3027ppc64v1_emit_reg (int reg)
3028{
3029 uint32_t buf[15];
3030 uint32_t *p = buf;
3031
3032 /* fctx->regs is passed in r3 and then saved in 176(1). */
3033 p += GEN_LD (p, 3, 31, -32);
3034 p += GEN_LI (p, 4, reg);
3035 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3036 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
3037 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3038
3039 emit_insns (buf, p - buf);
3040 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3041}
3042
3043/* Likewise, for ELFv2. */
3044
3045static void
3046ppc64v2_emit_reg (int reg)
3047{
3048 uint32_t buf[12];
3049 uint32_t *p = buf;
3050
3051 /* fctx->regs is passed in r3 and then saved in 176(1). */
3052 p += GEN_LD (p, 3, 31, -32);
3053 p += GEN_LI (p, 4, reg);
3054 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3055 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
3056 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3057
3058 emit_insns (buf, p - buf);
3059 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3060}
3061
3062/* TOP = stack[--sp] */
3063
3064static void
3065ppc64_emit_pop (void)
3066{
3067 EMIT_ASM ("ldu 3, 8(30)");
3068}
3069
3070/* stack[sp++] = TOP
3071
3072 Because we may use up bytecode stack, expand 8 doublewords more
3073 if needed. */
3074
3075static void
3076ppc64_emit_stack_flush (void)
3077{
3078 /* Make sure bytecode stack is big enough before push.
3079 Otherwise, expand 64-byte more. */
3080
3081 EMIT_ASM (" std 3, 0(30) \n"
3082 " addi 4, 30, -(112 + 8) \n"
3083 " cmpd 7, 4, 1 \n"
3084 " bgt 7, 1f \n"
3085 " stdu 31, -64(1) \n"
3086 "1:addi 30, 30, -8 \n");
3087}
3088
3089/* Swap TOP and stack[sp-1] */
3090
3091static void
3092ppc64_emit_swap (void)
3093{
3094 EMIT_ASM ("ld 4, 8(30) \n"
3095 "std 3, 8(30) \n"
3096 "mr 3, 4 \n");
3097}
3098
3099/* Call function FN - ELFv1. */
3100
3101static void
3102ppc64v1_emit_call (CORE_ADDR fn)
3103{
3104 uint32_t buf[13];
3105 uint32_t *p = buf;
3106
3107 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3108 p += gen_call (p, fn, 1, 1);
3109 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3110
3111 emit_insns (buf, p - buf);
3112 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3113}
3114
3115/* Call function FN - ELFv2. */
3116
3117static void
3118ppc64v2_emit_call (CORE_ADDR fn)
3119{
3120 uint32_t buf[10];
3121 uint32_t *p = buf;
3122
3123 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3124 p += gen_call (p, fn, 1, 0);
3125 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3126
3127 emit_insns (buf, p - buf);
3128 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3129}
3130
3131/* FN's prototype is `LONGEST(*fn)(int)'.
3132 TOP = fn (arg1)
3133 */
3134
3135static void
3136ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
3137{
3138 uint32_t buf[13];
3139 uint32_t *p = buf;
3140
3141 /* Setup argument. arg1 is a 16-bit value. */
3142 p += gen_limm (p, 3, arg1, 1);
3143 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3144 p += gen_call (p, fn, 1, 1);
3145 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3146
3147 emit_insns (buf, p - buf);
3148 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3149}
3150
3151/* Likewise for ELFv2. */
3152
3153static void
3154ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
3155{
3156 uint32_t buf[10];
3157 uint32_t *p = buf;
3158
3159 /* Setup argument. arg1 is a 16-bit value. */
3160 p += gen_limm (p, 3, arg1, 1);
3161 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3162 p += gen_call (p, fn, 1, 0);
3163 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3164
3165 emit_insns (buf, p - buf);
3166 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3167}
3168
3169/* FN's prototype is `void(*fn)(int,LONGEST)'.
3170 fn (arg1, TOP)
3171
3172 TOP should be preserved/restored before/after the call. */
3173
3174static void
3175ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
3176{
3177 uint32_t buf[17];
3178 uint32_t *p = buf;
3179
3180 /* Save TOP. 0(30) is next-empty. */
3181 p += GEN_STD (p, 3, 30, 0);
3182
3183 /* Setup argument. arg1 is a 16-bit value. */
3184 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3185 p += gen_limm (p, 3, arg1, 1);
3186 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3187 p += gen_call (p, fn, 1, 1);
3188 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3189
3190 /* Restore TOP */
3191 p += GEN_LD (p, 3, 30, 0);
3192
3193 emit_insns (buf, p - buf);
3194 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3195}
3196
3197/* Likewise for ELFv2. */
3198
3199static void
3200ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
3201{
3202 uint32_t buf[14];
3203 uint32_t *p = buf;
3204
3205 /* Save TOP. 0(30) is next-empty. */
3206 p += GEN_STD (p, 3, 30, 0);
3207
3208 /* Setup argument. arg1 is a 16-bit value. */
3209 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3210 p += gen_limm (p, 3, arg1, 1);
3211 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3212 p += gen_call (p, fn, 1, 0);
3213 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3214
3215 /* Restore TOP */
3216 p += GEN_LD (p, 3, 30, 0);
3217
3218 emit_insns (buf, p - buf);
3219 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3220}
3221
3222/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3223
3224static void
3225ppc64_emit_if_goto (int *offset_p, int *size_p)
3226{
3227 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3228 "ldu 3, 8(30) \n"
3229 "1:bne 7, 1b \n");
3230
3231 if (offset_p)
3232 *offset_p = 8;
3233 if (size_p)
3234 *size_p = 14;
3235}
3236
3237/* Goto if stack[--sp] == TOP */
3238
3239static void
3240ppc64_emit_eq_goto (int *offset_p, int *size_p)
3241{
3242 EMIT_ASM ("ldu 4, 8(30) \n"
3243 "cmpd 7, 4, 3 \n"
3244 "ldu 3, 8(30) \n"
3245 "1:beq 7, 1b \n");
3246
3247 if (offset_p)
3248 *offset_p = 12;
3249 if (size_p)
3250 *size_p = 14;
3251}
3252
3253/* Goto if stack[--sp] != TOP */
3254
3255static void
3256ppc64_emit_ne_goto (int *offset_p, int *size_p)
3257{
3258 EMIT_ASM ("ldu 4, 8(30) \n"
3259 "cmpd 7, 4, 3 \n"
3260 "ldu 3, 8(30) \n"
3261 "1:bne 7, 1b \n");
3262
3263 if (offset_p)
3264 *offset_p = 12;
3265 if (size_p)
3266 *size_p = 14;
3267}
3268
3269/* Goto if stack[--sp] < TOP */
3270
3271static void
3272ppc64_emit_lt_goto (int *offset_p, int *size_p)
3273{
3274 EMIT_ASM ("ldu 4, 8(30) \n"
3275 "cmpd 7, 4, 3 \n"
3276 "ldu 3, 8(30) \n"
3277 "1:blt 7, 1b \n");
3278
3279 if (offset_p)
3280 *offset_p = 12;
3281 if (size_p)
3282 *size_p = 14;
3283}
3284
3285/* Goto if stack[--sp] <= TOP */
3286
3287static void
3288ppc64_emit_le_goto (int *offset_p, int *size_p)
3289{
3290 EMIT_ASM ("ldu 4, 8(30) \n"
3291 "cmpd 7, 4, 3 \n"
3292 "ldu 3, 8(30) \n"
3293 "1:ble 7, 1b \n");
3294
3295 if (offset_p)
3296 *offset_p = 12;
3297 if (size_p)
3298 *size_p = 14;
3299}
3300
3301/* Goto if stack[--sp] > TOP */
3302
3303static void
3304ppc64_emit_gt_goto (int *offset_p, int *size_p)
3305{
3306 EMIT_ASM ("ldu 4, 8(30) \n"
3307 "cmpd 7, 4, 3 \n"
3308 "ldu 3, 8(30) \n"
3309 "1:bgt 7, 1b \n");
3310
3311 if (offset_p)
3312 *offset_p = 12;
3313 if (size_p)
3314 *size_p = 14;
3315}
3316
3317/* Goto if stack[--sp] >= TOP */
3318
3319static void
3320ppc64_emit_ge_goto (int *offset_p, int *size_p)
3321{
3322 EMIT_ASM ("ldu 4, 8(30) \n"
3323 "cmpd 7, 4, 3 \n"
3324 "ldu 3, 8(30) \n"
3325 "1:bge 7, 1b \n");
3326
3327 if (offset_p)
3328 *offset_p = 12;
3329 if (size_p)
3330 *size_p = 14;
3331}
3332
3333/* Table of emit ops for 64-bit ELFv1. */
3334
3335static struct emit_ops ppc64v1_emit_ops_impl =
3336{
3337 ppc64v1_emit_prologue,
3338 ppc64_emit_epilogue,
3339 ppc64_emit_add,
3340 ppc64_emit_sub,
3341 ppc64_emit_mul,
3342 ppc64_emit_lsh,
3343 ppc64_emit_rsh_signed,
3344 ppc64_emit_rsh_unsigned,
3345 ppc64_emit_ext,
3346 ppc64_emit_log_not,
3347 ppc64_emit_bit_and,
3348 ppc64_emit_bit_or,
3349 ppc64_emit_bit_xor,
3350 ppc64_emit_bit_not,
3351 ppc64_emit_equal,
3352 ppc64_emit_less_signed,
3353 ppc64_emit_less_unsigned,
3354 ppc64_emit_ref,
3355 ppc64_emit_if_goto,
3356 ppc_emit_goto,
3357 ppc_write_goto_address,
3358 ppc64_emit_const,
3359 ppc64v1_emit_call,
3360 ppc64v1_emit_reg,
3361 ppc64_emit_pop,
3362 ppc64_emit_stack_flush,
3363 ppc64_emit_zero_ext,
3364 ppc64_emit_swap,
3365 ppc_emit_stack_adjust,
3366 ppc64v1_emit_int_call_1,
3367 ppc64v1_emit_void_call_2,
3368 ppc64_emit_eq_goto,
3369 ppc64_emit_ne_goto,
3370 ppc64_emit_lt_goto,
3371 ppc64_emit_le_goto,
3372 ppc64_emit_gt_goto,
3373 ppc64_emit_ge_goto
3374};
3375
3376/* Table of emit ops for 64-bit ELFv2. */
3377
3378static struct emit_ops ppc64v2_emit_ops_impl =
3379{
3380 ppc64v2_emit_prologue,
3381 ppc64_emit_epilogue,
3382 ppc64_emit_add,
3383 ppc64_emit_sub,
3384 ppc64_emit_mul,
3385 ppc64_emit_lsh,
3386 ppc64_emit_rsh_signed,
3387 ppc64_emit_rsh_unsigned,
3388 ppc64_emit_ext,
3389 ppc64_emit_log_not,
3390 ppc64_emit_bit_and,
3391 ppc64_emit_bit_or,
3392 ppc64_emit_bit_xor,
3393 ppc64_emit_bit_not,
3394 ppc64_emit_equal,
3395 ppc64_emit_less_signed,
3396 ppc64_emit_less_unsigned,
3397 ppc64_emit_ref,
3398 ppc64_emit_if_goto,
3399 ppc_emit_goto,
3400 ppc_write_goto_address,
3401 ppc64_emit_const,
3402 ppc64v2_emit_call,
3403 ppc64v2_emit_reg,
3404 ppc64_emit_pop,
3405 ppc64_emit_stack_flush,
3406 ppc64_emit_zero_ext,
3407 ppc64_emit_swap,
3408 ppc_emit_stack_adjust,
3409 ppc64v2_emit_int_call_1,
3410 ppc64v2_emit_void_call_2,
3411 ppc64_emit_eq_goto,
3412 ppc64_emit_ne_goto,
3413 ppc64_emit_lt_goto,
3414 ppc64_emit_le_goto,
3415 ppc64_emit_gt_goto,
3416 ppc64_emit_ge_goto
3417};
3418
3419#endif
3420
3421/* Implementation of linux_target_ops method "emit_ops". */
3422
3423static struct emit_ops *
3424ppc_emit_ops (void)
3425{
3426#ifdef __powerpc64__
3427 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3428
3429 if (register_size (regcache->tdesc, 0) == 8)
3430 {
3431 if (is_elfv2_inferior ())
3432 return &ppc64v2_emit_ops_impl;
3433 else
3434 return &ppc64v1_emit_ops_impl;
3435 }
3436#endif
3437 return &ppc_emit_ops_impl;
3438}
3439
a2174ba4
MK		 3440/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3441
3442static int
3443ppc_get_ipa_tdesc_idx (void)
3444{
3445 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3446 const struct target_desc *tdesc = regcache->tdesc;
3447
3448#ifdef __powerpc64__
3449 if (tdesc == tdesc_powerpc_64l)
3450 return PPC_TDESC_BASE;
3451 if (tdesc == tdesc_powerpc_altivec64l)
3452 return PPC_TDESC_ALTIVEC;
3453 if (tdesc == tdesc_powerpc_cell64l)
3454 return PPC_TDESC_CELL;
3455 if (tdesc == tdesc_powerpc_vsx64l)
3456 return PPC_TDESC_VSX;
3457 if (tdesc == tdesc_powerpc_isa205_64l)
3458 return PPC_TDESC_ISA205;
3459 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3460 return PPC_TDESC_ISA205_ALTIVEC;
3461 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3462 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3463 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3464 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3465 if (tdesc == tdesc_powerpc_isa207_vsx64l)
3466 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3467 if (tdesc == tdesc_powerpc_isa207_htm_vsx64l)
3468 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3469#endif
3470
3471 if (tdesc == tdesc_powerpc_32l)
3472 return PPC_TDESC_BASE;
3473 if (tdesc == tdesc_powerpc_altivec32l)
3474 return PPC_TDESC_ALTIVEC;
3475 if (tdesc == tdesc_powerpc_cell32l)
3476 return PPC_TDESC_CELL;
3477 if (tdesc == tdesc_powerpc_vsx32l)
3478 return PPC_TDESC_VSX;
3479 if (tdesc == tdesc_powerpc_isa205_32l)
3480 return PPC_TDESC_ISA205;
3481 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3482 return PPC_TDESC_ISA205_ALTIVEC;
3483 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3484 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3485 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3486 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3487 if (tdesc == tdesc_powerpc_isa207_vsx32l)
3488 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3489 if (tdesc == tdesc_powerpc_isa207_htm_vsx32l)
3490 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3491 if (tdesc == tdesc_powerpc_e500l)
3492 return PPC_TDESC_E500;
3493
3494 return 0;
3495}
3496
2ec06d2e 3497struct linux_target_ops the_low_target = {
6fe305f7 3498 ppc_arch_setup,
3aee8918 3499 ppc_regs_info,
2ec06d2e
DJ		 3500 ppc_cannot_fetch_register,
3501 ppc_cannot_store_register,
c14dfd32 3502 NULL, /* fetch_register */
0d62e5e8
DJ		 3503 ppc_get_pc,
3504 ppc_set_pc,
dd373349
AT		 3505 NULL, /* breakpoint_kind_from_pc */
3506 ppc_sw_breakpoint_from_kind,
0d62e5e8
DJ		 3507 NULL,
3508 0,
3509 ppc_breakpoint_at,
657f9cde
WW		 3510 ppc_supports_z_point_type,
3511 ppc_insert_point,
3512 ppc_remove_point,
5b0a002e
UW		 3513 NULL,
3514 NULL,
3515 ppc_collect_ptrace_register,
3516 ppc_supply_ptrace_register,
7d00775e
AT		 3517 NULL, /* siginfo_fixup */
3518 NULL, /* new_process */
04ec7890 3519 NULL, /* delete_process */
7d00775e 3520 NULL, /* new_thread */
466eecee 3521 NULL, /* delete_thread */
7d00775e
AT		 3522 NULL, /* new_fork */
3523 NULL, /* prepare_to_resume */
3524 NULL, /* process_qsupported */
b04fd3be 3525 ppc_supports_tracepoints,
a2174ba4
MK		 3526 ppc_get_thread_area,
3527 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3528 ppc_emit_ops,
a2174ba4 3529 ppc_get_min_fast_tracepoint_insn_len,
7d00775e
AT		 3530 NULL, /* supports_range_stepping */
3531 NULL, /* breakpoint_kind_from_current_state */
3532 ppc_supports_hardware_single_step,
a2174ba4
MK		 3533 NULL, /* get_syscall_trapinfo */
3534 ppc_get_ipa_tdesc_idx,
2ec06d2e 3535};
3aee8918
PA		 3536
3537void
3538initialize_low_arch (void)
3539{
3540 /* Initialize the Linux target descriptions. */
3541
3542 init_registers_powerpc_32l ();
3543 init_registers_powerpc_altivec32l ();
3544 init_registers_powerpc_cell32l ();
3545 init_registers_powerpc_vsx32l ();
3546 init_registers_powerpc_isa205_32l ();
3547 init_registers_powerpc_isa205_altivec32l ();
3548 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3549 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
f2cf6173 3550 init_registers_powerpc_isa207_vsx32l ();
8d619c01 3551 init_registers_powerpc_isa207_htm_vsx32l ();
3aee8918 3552 init_registers_powerpc_e500l ();
a2174ba4 3553#if __powerpc64__
3aee8918
PA		 3554 init_registers_powerpc_64l ();
3555 init_registers_powerpc_altivec64l ();
3556 init_registers_powerpc_cell64l ();
3557 init_registers_powerpc_vsx64l ();
3558 init_registers_powerpc_isa205_64l ();
3559 init_registers_powerpc_isa205_altivec64l ();
3560 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3561 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
f2cf6173 3562 init_registers_powerpc_isa207_vsx64l ();
8d619c01 3563 init_registers_powerpc_isa207_htm_vsx64l ();
a2174ba4 3564#endif
3aee8918
PA		 3565
3566 initialize_regsets_info (&ppc_regsets_info);
3567}
GDB Binutils - Deliverables
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