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[PowerPC] Add support for TAR
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-ppc-low.c
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
e2882c85 3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
bd64614e 31#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 32#include "ax.h"
33#include "tracepoint.h"
34
35#define PPC_FIELD(value, from, len) \
36 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
37#define PPC_SEXT(v, bs) \
38 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
39 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
40 - ((CORE_ADDR) 1 << ((bs) - 1)))
41#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
42#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
43#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
44#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 45
7ca18ed6
EBM		 46/* Holds the AT_HWCAP auxv entry. */
47
b6430ec3
UW		 48static unsigned long ppc_hwcap;
49
7ca18ed6
EBM		 50/* Holds the AT_HWCAP2 auxv entry. */
51
52static unsigned long ppc_hwcap2;
53
b6430ec3 54
7284e1be
UW		 55#define ppc_num_regs 73
56
5b0a002e
UW		 57#ifdef __powerpc64__
58/* We use a constant for FPSCR instead of PT_FPSCR, because
59 many shipped PPC64 kernels had the wrong value in ptrace.h. */
60static int ppc_regmap[] =
61 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
62 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
63 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
64 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
65 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
66 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
67 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
68 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
69 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
70 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
71 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
72 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
73 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
74 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
75 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
76 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
77 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 78 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
79 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 80#else
0a30fbc4 81/* Currently, don't check/send MQ. */
2ec06d2e 82static int ppc_regmap[] =
0a30fbc4
DJ		 83 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
84 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
85 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
86 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
87 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
88 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
89 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
90 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
91 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
92 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
93 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
94 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
95 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
96 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
97 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
98 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
99 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 100 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
101 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 102 };
103
104static int ppc_regmap_e500[] =
105 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
106 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
107 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
108 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
109 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
110 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
111 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
112 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
113 -1, -1, -1, -1,
114 -1, -1, -1, -1,
115 -1, -1, -1, -1,
116 -1, -1, -1, -1,
117 -1, -1, -1, -1,
118 -1, -1, -1, -1,
119 -1, -1, -1, -1,
120 -1, -1, -1, -1,
121 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 122 PT_CTR * 4, PT_XER * 4, -1,
123 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 124 };
5b0a002e 125#endif
0a30fbc4 126
7ca18ed6
EBM		 127/* Check whether the kernel provides a register set with number
128 REGSET_ID of size REGSETSIZE for process/thread TID. */
129
130static int
131ppc_check_regset (int tid, int regset_id, int regsetsize)
132{
133 void *buf = alloca (regsetsize);
134 struct iovec iov;
135
136 iov.iov_base = buf;
137 iov.iov_len = regsetsize;
138
139 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
140 || errno == ENODATA)
141 return 1;
142 return 0;
143}
144
2ec06d2e
DJ		 145static int
146ppc_cannot_store_register (int regno)
0a30fbc4 147{
3aee8918
PA		 148 const struct target_desc *tdesc = current_process ()->tdesc;
149
b6430ec3 150#ifndef __powerpc64__
bc1e36ca 151 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 152 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
153 && regno == find_regno (tdesc, "fpscr"))
bc1e36ca 154 return 2;
30ed0a8f 155#endif
bc1e36ca 156
7284e1be 157 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 158 if (regno == find_regno (tdesc, "orig_r3")
159 || regno == find_regno (tdesc, "trap"))
7284e1be
UW		 160 return 2;
161
0a30fbc4
DJ		 162 return 0;
163}
164
2ec06d2e
DJ		 165static int
166ppc_cannot_fetch_register (int regno)
0a30fbc4
DJ		 167{
168 return 0;
169}
170
5b0a002e 171static void
442ea881 172ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
5b0a002e 173{
76b233dd
UW		 174 memset (buf, 0, sizeof (long));
175
2e4bb98a
EBM		 176 if (__BYTE_ORDER == __LITTLE_ENDIAN)
177 {
178 /* Little-endian values always sit at the left end of the buffer. */
179 collect_register (regcache, regno, buf);
180 }
181 else if (__BYTE_ORDER == __BIG_ENDIAN)
182 {
183 /* Big-endian values sit at the right end of the buffer. In case of
184 registers whose sizes are smaller than sizeof (long), we must use a
185 padding to access them correctly. */
186 int size = register_size (regcache->tdesc, regno);
187
188 if (size < sizeof (long))
189 collect_register (regcache, regno, buf + sizeof (long) - size);
190 else
191 collect_register (regcache, regno, buf);
192 }
5b0a002e 193 else
2e4bb98a 194 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 195}
196
197static void
442ea881
PA		 198ppc_supply_ptrace_register (struct regcache *regcache,
199 int regno, const char *buf)
5b0a002e 200{
2e4bb98a
EBM		 201 if (__BYTE_ORDER == __LITTLE_ENDIAN)
202 {
203 /* Little-endian values always sit at the left end of the buffer. */
204 supply_register (regcache, regno, buf);
205 }
206 else if (__BYTE_ORDER == __BIG_ENDIAN)
207 {
208 /* Big-endian values sit at the right end of the buffer. In case of
209 registers whose sizes are smaller than sizeof (long), we must use a
210 padding to access them correctly. */
211 int size = register_size (regcache->tdesc, regno);
212
213 if (size < sizeof (long))
214 supply_register (regcache, regno, buf + sizeof (long) - size);
215 else
216 supply_register (regcache, regno, buf);
217 }
5b0a002e 218 else
2e4bb98a 219 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 220}
221
0b9ff2c0
UW		 222
223#define INSTR_SC 0x44000002
224#define NR_spu_run 0x0116
225
226/* If the PPU thread is currently stopped on a spu_run system call,
227 return to FD and ADDR the file handle and NPC parameter address
228 used with the system call. Return non-zero if successful. */
229static int
442ea881 230parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
0b9ff2c0
UW		 231{
232 CORE_ADDR curr_pc;
233 int curr_insn;
234 int curr_r0;
235
3aee8918 236 if (register_size (regcache->tdesc, 0) == 4)
0b9ff2c0
UW		 237 {
238 unsigned int pc, r0, r3, r4;
442ea881
PA		 239 collect_register_by_name (regcache, "pc", &pc);
240 collect_register_by_name (regcache, "r0", &r0);
241 collect_register_by_name (regcache, "orig_r3", &r3);
242 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 243 curr_pc = (CORE_ADDR) pc;
244 curr_r0 = (int) r0;
245 *fd = (int) r3;
246 *addr = (CORE_ADDR) r4;
247 }
248 else
249 {
250 unsigned long pc, r0, r3, r4;
442ea881
PA		 251 collect_register_by_name (regcache, "pc", &pc);
252 collect_register_by_name (regcache, "r0", &r0);
253 collect_register_by_name (regcache, "orig_r3", &r3);
254 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 255 curr_pc = (CORE_ADDR) pc;
256 curr_r0 = (int) r0;
257 *fd = (int) r3;
258 *addr = (CORE_ADDR) r4;
259 }
260
261 /* Fetch instruction preceding current NIP. */
262 if ((*the_target->read_memory) (curr_pc - 4,
263 (unsigned char *) &curr_insn, 4) != 0)
264 return 0;
265 /* It should be a "sc" instruction. */
266 if (curr_insn != INSTR_SC)
267 return 0;
268 /* System call number should be NR_spu_run. */
269 if (curr_r0 != NR_spu_run)
270 return 0;
271
272 return 1;
273}
274
0d62e5e8 275static CORE_ADDR
442ea881 276ppc_get_pc (struct regcache *regcache)
0d62e5e8 277{
0b9ff2c0
UW		 278 CORE_ADDR addr;
279 int fd;
280
442ea881 281 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 282 {
283 unsigned int pc;
284 (*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
493e2a69
MS		 285 return ((CORE_ADDR)1 << 63)
286 | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
0b9ff2c0 287 }
3aee8918 288 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 289 {
290 unsigned int pc;
442ea881 291 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 292 return (CORE_ADDR) pc;
293 }
294 else
295 {
296 unsigned long pc;
442ea881 297 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 298 return (CORE_ADDR) pc;
299 }
0d62e5e8
DJ		 300}
301
302static void
442ea881 303ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8 304{
0b9ff2c0
UW		 305 CORE_ADDR addr;
306 int fd;
307
442ea881 308 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 309 {
310 unsigned int newpc = pc;
311 (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
312 }
3aee8918 313 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 314 {
315 unsigned int newpc = pc;
442ea881 316 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 317 }
318 else
319 {
320 unsigned long newpc = pc;
442ea881 321 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 322 }
323}
324
b6430ec3
UW		 325
326static int
a2174ba4 327ppc_get_auxv (unsigned long type, unsigned long *valp)
b6430ec3 328{
3aee8918
PA		 329 const struct target_desc *tdesc = current_process ()->tdesc;
330 int wordsize = register_size (tdesc, 0);
2bc84e8a 331 unsigned char *data = (unsigned char *) alloca (2 * wordsize);
b6430ec3
UW		 332 int offset = 0;
333
334 while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
335 {
336 if (wordsize == 4)
337 {
338 unsigned int *data_p = (unsigned int *)data;
a2174ba4 339 if (data_p[0] == type)
b6430ec3
UW		 340 {
341 *valp = data_p[1];
342 return 1;
343 }
344 }
345 else
346 {
347 unsigned long *data_p = (unsigned long *)data;
a2174ba4 348 if (data_p[0] == type)
b6430ec3
UW		 349 {
350 *valp = data_p[1];
351 return 1;
352 }
353 }
354
355 offset += 2 * wordsize;
356 }
357
358 *valp = 0;
359 return 0;
360}
361
3aee8918
PA		 362#ifndef __powerpc64__
363static int ppc_regmap_adjusted;
364#endif
365
0d62e5e8 366
5b0a002e 367/* Correct in either endianness.
0d62e5e8
DJ		 368 This instruction is "twge r2, r2", which GDB uses as a software
369 breakpoint. */
5b0a002e 370static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 371#define ppc_breakpoint_len 4
372
dd373349
AT		 373/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
374
375static const gdb_byte *
376ppc_sw_breakpoint_from_kind (int kind, int *size)
377{
378 *size = ppc_breakpoint_len;
379 return (const gdb_byte *) &ppc_breakpoint;
380}
381
0d62e5e8
DJ		 382static int
383ppc_breakpoint_at (CORE_ADDR where)
384{
5b0a002e 385 unsigned int insn;
0d62e5e8 386
0b9ff2c0
UW		 387 if (where & ((CORE_ADDR)1 << 63))
388 {
389 char mem_annex[32];
390 sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
391 (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
392 NULL, where & 0xffffffff, 4);
393 if (insn == 0x3fff)
394 return 1;
395 }
396 else
397 {
398 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
399 if (insn == ppc_breakpoint)
400 return 1;
401 /* If necessary, recognize more trap instructions here. GDB only uses
402 the one. */
403 }
404
0d62e5e8
DJ		 405 return 0;
406}
407
657f9cde
WW		 408/* Implement supports_z_point_type target-ops.
409 Returns true if type Z_TYPE breakpoint is supported.
410
411 Handling software breakpoint at server side, so tracepoints
412 and breakpoints can be inserted at the same location. */
413
414static int
415ppc_supports_z_point_type (char z_type)
416{
417 switch (z_type)
418 {
419 case Z_PACKET_SW_BP:
420 return 1;
421 case Z_PACKET_HW_BP:
422 case Z_PACKET_WRITE_WP:
423 case Z_PACKET_ACCESS_WP:
424 default:
425 return 0;
426 }
427}
428
429/* Implement insert_point target-ops.
430 Returns 0 on success, -1 on failure and 1 on unsupported. */
431
432static int
433ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
434 int size, struct raw_breakpoint *bp)
435{
436 switch (type)
437 {
438 case raw_bkpt_type_sw:
439 return insert_memory_breakpoint (bp);
440
441 case raw_bkpt_type_hw:
442 case raw_bkpt_type_write_wp:
443 case raw_bkpt_type_access_wp:
444 default:
445 /* Unsupported. */
446 return 1;
447 }
448}
449
450/* Implement remove_point target-ops.
451 Returns 0 on success, -1 on failure and 1 on unsupported. */
452
453static int
454ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
455 int size, struct raw_breakpoint *bp)
456{
457 switch (type)
458 {
459 case raw_bkpt_type_sw:
460 return remove_memory_breakpoint (bp);
461
462 case raw_bkpt_type_hw:
463 case raw_bkpt_type_write_wp:
464 case raw_bkpt_type_access_wp:
465 default:
466 /* Unsupported. */
467 return 1;
468 }
469}
470
e9d25b98
DJ		 471/* Provide only a fill function for the general register set. ps_lgetregs
472 will use this for NPTL support. */
473
442ea881 474static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 475{
476 int i;
477
478 for (i = 0; i < 32; i++)
442ea881 479 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 480
481 for (i = 64; i < 70; i++)
442ea881 482 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
7284e1be
UW		 483
484 for (i = 71; i < 73; i++)
442ea881 485 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 486}
487
7ca18ed6
EBM		 488/* Program Priority Register regset fill function. */
489
490static void
491ppc_fill_pprregset (struct regcache *regcache, void *buf)
492{
493 char *ppr = (char *) buf;
494
495 collect_register_by_name (regcache, "ppr", ppr);
496}
497
498/* Program Priority Register regset store function. */
499
500static void
501ppc_store_pprregset (struct regcache *regcache, const void *buf)
502{
503 const char *ppr = (const char *) buf;
504
505 supply_register_by_name (regcache, "ppr", ppr);
506}
507
508/* Data Stream Control Register regset fill function. */
509
510static void
511ppc_fill_dscrregset (struct regcache *regcache, void *buf)
512{
513 char *dscr = (char *) buf;
514
515 collect_register_by_name (regcache, "dscr", dscr);
516}
517
518/* Data Stream Control Register regset store function. */
519
520static void
521ppc_store_dscrregset (struct regcache *regcache, const void *buf)
522{
523 const char *dscr = (const char *) buf;
524
525 supply_register_by_name (regcache, "dscr", dscr);
526}
527
f2cf6173
EBM		 528/* Target Address Register regset fill function. */
529
530static void
531ppc_fill_tarregset (struct regcache *regcache, void *buf)
532{
533 char *tar = (char *) buf;
534
535 collect_register_by_name (regcache, "tar", tar);
536}
537
538/* Target Address Register regset store function. */
539
540static void
541ppc_store_tarregset (struct regcache *regcache, const void *buf)
542{
543 const char *tar = (const char *) buf;
544
545 supply_register_by_name (regcache, "tar", tar);
546}
547
677c5bb1 548static void
442ea881 549ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 550{
551 int i, base;
2bc84e8a 552 char *regset = (char *) buf;
677c5bb1 553
3aee8918 554 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 555 for (i = 0; i < 32; i++)
442ea881 556 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 557}
558
559static void
442ea881 560ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 561{
562 int i, base;
2bc84e8a 563 const char *regset = (const char *) buf;
677c5bb1 564
3aee8918 565 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 566 for (i = 0; i < 32; i++)
442ea881 567 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 568}
569
30ed0a8f 570static void
442ea881 571ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 572{
573 int i, base;
2bc84e8a 574 char *regset = (char *) buf;
1d75a658 575 int vscr_offset = 0;
30ed0a8f 576
3aee8918 577 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 578 for (i = 0; i < 32; i++)
442ea881 579 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 580
1d75a658
PFC		 581 if (__BYTE_ORDER == __BIG_ENDIAN)
582 vscr_offset = 12;
583
1d75a658
PFC		 584 collect_register_by_name (regcache, "vscr",
585 &regset[32 * 16 + vscr_offset]);
586
442ea881 587 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 588}
589
590static void
442ea881 591ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 592{
593 int i, base;
2bc84e8a 594 const char *regset = (const char *) buf;
1d75a658 595 int vscr_offset = 0;
30ed0a8f 596
3aee8918 597 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 598 for (i = 0; i < 32; i++)
442ea881 599 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 600
1d75a658
PFC		 601 if (__BYTE_ORDER == __BIG_ENDIAN)
602 vscr_offset = 12;
603
604 supply_register_by_name (regcache, "vscr",
605 &regset[32 * 16 + vscr_offset]);
442ea881 606 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 607}
608
30ed0a8f
DJ		 609struct gdb_evrregset_t
610{
611 unsigned long evr[32];
612 unsigned long long acc;
613 unsigned long spefscr;
614};
615
616static void
442ea881 617ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 618{
619 int i, ev0;
2bc84e8a 620 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 621
3aee8918 622 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 623 for (i = 0; i < 32; i++)
442ea881 624 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 625
442ea881
PA		 626 collect_register_by_name (regcache, "acc", &regset->acc);
627 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 628}
629
630static void
442ea881 631ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 632{
633 int i, ev0;
2bc84e8a 634 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 635
3aee8918 636 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 637 for (i = 0; i < 32; i++)
442ea881 638 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 639
442ea881
PA		 640 supply_register_by_name (regcache, "acc", &regset->acc);
641 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 642}
30ed0a8f 643
7d00775e
AT		 644/* Support for hardware single step. */
645
646static int
647ppc_supports_hardware_single_step (void)
648{
649 return 1;
650}
651
3aee8918 652static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 653 /* List the extra register sets before GENERAL_REGS. That way we will
654 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
655 general registers. Some kernels support these, but not the newer
656 PPC_PTRACE_GETREGS. */
f2cf6173
EBM		 657 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
658 ppc_fill_tarregset, ppc_store_tarregset },
7ca18ed6
EBM		 659 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
660 ppc_fill_pprregset, ppc_store_pprregset },
661 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
662 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 663 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 664 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 665 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 666 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 667 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 668 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 669 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 670 NULL_REGSET
e9d25b98
DJ		 671};
672
3aee8918
PA		 673static struct usrregs_info ppc_usrregs_info =
674 {
675 ppc_num_regs,
676 ppc_regmap,
677 };
678
679static struct regsets_info ppc_regsets_info =
680 {
681 ppc_regsets, /* regsets */
682 0, /* num_regsets */
683 NULL, /* disabled_regsets */
684 };
685
686static struct regs_info regs_info =
687 {
688 NULL, /* regset_bitmap */
689 &ppc_usrregs_info,
690 &ppc_regsets_info
691 };
692
693static const struct regs_info *
694ppc_regs_info (void)
695{
696 return &regs_info;
697}
698
e6c5bb05
SM		 699static void
700ppc_arch_setup (void)
701{
702 const struct target_desc *tdesc;
7273b5fc 703 struct regset_info *regset;
bd64614e 704 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 705
2e077f5e 706 int tid = lwpid_of (current_thread);
bd64614e 707
2e077f5e 708 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 709
bd64614e 710 if (features.wordsize == 4)
bd64614e 711 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 712 else
713 tdesc = tdesc_powerpc_64l;
714
715 current_process ()->tdesc = tdesc;
e6c5bb05 716
bd64614e
PFC		 717 /* The value of current_process ()->tdesc needs to be set for this
718 call. */
a2174ba4 719 ppc_get_auxv (AT_HWCAP, &ppc_hwcap);
7ca18ed6 720 ppc_get_auxv (AT_HWCAP2, &ppc_hwcap2);
bd64614e
PFC		 721
722 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
723
724 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
725 features.vsx = true;
726
727 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
728 features.altivec = true;
729
7ca18ed6
EBM		 730 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
731 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
732 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
f2cf6173
EBM		 733 {
734 features.ppr_dscr = true;
735 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
736 && (ppc_hwcap2 & PPC_FEATURE2_TAR)
737 && ppc_check_regset (tid, NT_PPC_TAR,
738 PPC_LINUX_SIZEOF_TARREGSET))
739 features.isa207 = true;
740 }
7ca18ed6 741
e6c5bb05 742 if (ppc_hwcap & PPC_FEATURE_CELL)
bd64614e
PFC		 743 features.cell = true;
744
745 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 746
747 /* On 32-bit machines, check for SPE registers.
748 Set the low target's regmap field as appropriately. */
749#ifndef __powerpc64__
750 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
751 tdesc = tdesc_powerpc_e500l;
752
753 if (!ppc_regmap_adjusted)
754 {
755 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
756 ppc_usrregs_info.regmap = ppc_regmap_e500;
757
758 /* If the FPSCR is 64-bit wide, we need to fetch the whole
759 64-bit slot and not just its second word. The PT_FPSCR
760 supplied in a 32-bit GDB compilation doesn't reflect
761 this. */
762 if (register_size (tdesc, 70) == 8)
763 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
764
765 ppc_regmap_adjusted = 1;
766 }
767#endif
bd64614e 768
e6c5bb05 769 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 770
771 for (regset = ppc_regsets; regset->size >= 0; regset++)
772 switch (regset->get_request)
773 {
774 case PTRACE_GETVRREGS:
d078308a 775 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 776 break;
777 case PTRACE_GETVSXREGS:
d078308a 778 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 779 break;
780 case PTRACE_GETEVRREGS:
781 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
782 regset->size = 32 * 4 + 8 + 4;
783 else
784 regset->size = 0;
785 break;
7ca18ed6
EBM		 786 case PTRACE_GETREGSET:
787 switch (regset->nt_type)
788 {
789 case NT_PPC_PPR:
790 regset->size = (features.ppr_dscr ?
791 PPC_LINUX_SIZEOF_PPRREGSET : 0);
792 break;
793 case NT_PPC_DSCR:
794 regset->size = (features.ppr_dscr ?
795 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
796 break;
f2cf6173
EBM		 797 case NT_PPC_TAR:
798 regset->size = (features.isa207 ?
799 PPC_LINUX_SIZEOF_TARREGSET : 0);
800 break;
7ca18ed6
EBM		 801 default:
802 break;
803 }
804 break;
7273b5fc
PFC		 805 default:
806 break;
807 }
e6c5bb05
SM		 808}
809
a2174ba4
MK		 810/* Implementation of linux_target_ops method "supports_tracepoints". */
811
b04fd3be
MK		 812static int
813ppc_supports_tracepoints (void)
814{
815 return 1;
816}
817
a2174ba4
MK		 818/* Get the thread area address. This is used to recognize which
819 thread is which when tracing with the in-process agent library. We
820 don't read anything from the address, and treat it as opaque; it's
821 the address itself that we assume is unique per-thread. */
822
823static int
824ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
825{
f2907e49 826 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 827 struct thread_info *thr = get_lwp_thread (lwp);
828 struct regcache *regcache = get_thread_regcache (thr, 1);
829 ULONGEST tp = 0;
830
831#ifdef __powerpc64__
832 if (register_size (regcache->tdesc, 0) == 8)
833 collect_register_by_name (regcache, "r13", &tp);
834 else
835#endif
836 collect_register_by_name (regcache, "r2", &tp);
837
838 *addr = tp;
839
840 return 0;
841}
842
843#ifdef __powerpc64__
844
845/* Older glibc doesn't provide this. */
846
847#ifndef EF_PPC64_ABI
848#define EF_PPC64_ABI 3
849#endif
850
851/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
852 inferiors. */
853
854static int
855is_elfv2_inferior (void)
856{
857 /* To be used as fallback if we're unable to determine the right result -
858 assume inferior uses the same ABI as gdbserver. */
859#if _CALL_ELF == 2
860 const int def_res = 1;
861#else
862 const int def_res = 0;
863#endif
864 unsigned long phdr;
865 Elf64_Ehdr ehdr;
866
867 if (!ppc_get_auxv (AT_PHDR, &phdr))
868 return def_res;
869
870 /* Assume ELF header is at the beginning of the page where program headers
871 are located. If it doesn't look like one, bail. */
872
873 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
874 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
875 return def_res;
876
877 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
878}
879
880#endif
881
882/* Generate a ds-form instruction in BUF and return the number of bytes written
883
884 0 6 11 16 30 32
885 | OPCD | RST | RA | DS |XO| */
886
887__attribute__((unused)) /* Maybe unused due to conditional compilation. */
888static int
889gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
890{
891 uint32_t insn;
892
893 gdb_assert ((opcd & ~0x3f) == 0);
894 gdb_assert ((rst & ~0x1f) == 0);
895 gdb_assert ((ra & ~0x1f) == 0);
896 gdb_assert ((xo & ~0x3) == 0);
897
898 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
899 *buf = (opcd << 26) | insn;
900 return 1;
901}
902
903/* Followings are frequently used ds-form instructions. */
904
905#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
906#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
907#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
908#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
909
910/* Generate a d-form instruction in BUF.
911
912 0 6 11 16 32
913 | OPCD | RST | RA | D | */
914
915static int
916gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
917{
918 uint32_t insn;
919
920 gdb_assert ((opcd & ~0x3f) == 0);
921 gdb_assert ((rst & ~0x1f) == 0);
922 gdb_assert ((ra & ~0x1f) == 0);
923
924 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
925 *buf = (opcd << 26) | insn;
926 return 1;
927}
928
929/* Followings are frequently used d-form instructions. */
930
931#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
932#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
933#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
934#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
935#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
936#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
937#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
938#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
939#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
940
941/* Generate a xfx-form instruction in BUF and return the number of bytes
942 written.
943
944 0 6 11 21 31 32
945 | OPCD | RST | RI | XO |/| */
946
947static int
948gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
949{
950 uint32_t insn;
951 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
952
953 gdb_assert ((opcd & ~0x3f) == 0);
954 gdb_assert ((rst & ~0x1f) == 0);
955 gdb_assert ((xo & ~0x3ff) == 0);
956
957 insn = (rst << 21) | (n << 11) | (xo << 1);
958 *buf = (opcd << 26) | insn;
959 return 1;
960}
961
962/* Followings are frequently used xfx-form instructions. */
963
964#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
965#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
966#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
967#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
968#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
969 E & 0xf, 598)
970#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
971
972
973/* Generate a x-form instruction in BUF and return the number of bytes written.
974
975 0 6 11 16 21 31 32
976 | OPCD | RST | RA | RB | XO |RC| */
977
978static int
979gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
980{
981 uint32_t insn;
982
983 gdb_assert ((opcd & ~0x3f) == 0);
984 gdb_assert ((rst & ~0x1f) == 0);
985 gdb_assert ((ra & ~0x1f) == 0);
986 gdb_assert ((rb & ~0x1f) == 0);
987 gdb_assert ((xo & ~0x3ff) == 0);
988 gdb_assert ((rc & ~1) == 0);
989
990 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
991 *buf = (opcd << 26) | insn;
992 return 1;
993}
994
995/* Followings are frequently used x-form instructions. */
996
997#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
998#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
999#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1000#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1001/* Assume bf = cr7. */
1002#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1003
1004
1005/* Generate a md-form instruction in BUF and return the number of bytes written.
1006
1007 0 6 11 16 21 27 30 31 32
1008 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1009
1010static int
1011gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
1012 int xo, int rc)
1013{
1014 uint32_t insn;
1015 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
1016 unsigned int sh0_4 = sh & 0x1f;
1017 unsigned int sh5 = (sh >> 5) & 1;
1018
1019 gdb_assert ((opcd & ~0x3f) == 0);
1020 gdb_assert ((rs & ~0x1f) == 0);
1021 gdb_assert ((ra & ~0x1f) == 0);
1022 gdb_assert ((sh & ~0x3f) == 0);
1023 gdb_assert ((mb & ~0x3f) == 0);
1024 gdb_assert ((xo & ~0x7) == 0);
1025 gdb_assert ((rc & ~0x1) == 0);
1026
1027 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
1028 | (sh5 << 1) | (xo << 2) | (rc & 1);
1029 *buf = (opcd << 26) | insn;
1030 return 1;
1031}
1032
1033/* The following are frequently used md-form instructions. */
1034
1035#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1036 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1037#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1038 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1039
1040/* Generate a i-form instruction in BUF and return the number of bytes written.
1041
1042 0 6 30 31 32
1043 | OPCD | LI |AA|LK| */
1044
1045static int
1046gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1047{
1048 uint32_t insn;
1049
1050 gdb_assert ((opcd & ~0x3f) == 0);
1051
1052 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1053 *buf = (opcd << 26) | insn;
1054 return 1;
1055}
1056
1057/* The following are frequently used i-form instructions. */
1058
1059#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1060#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1061
1062/* Generate a b-form instruction in BUF and return the number of bytes written.
1063
1064 0 6 11 16 30 31 32
1065 | OPCD | BO | BI | BD |AA|LK| */
1066
1067static int
1068gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1069 int aa, int lk)
1070{
1071 uint32_t insn;
1072
1073 gdb_assert ((opcd & ~0x3f) == 0);
1074 gdb_assert ((bo & ~0x1f) == 0);
1075 gdb_assert ((bi & ~0x1f) == 0);
1076
1077 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1078 *buf = (opcd << 26) | insn;
1079 return 1;
1080}
1081
1082/* The following are frequently used b-form instructions. */
1083/* Assume bi = cr7. */
1084#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1085
1086/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1087 respectively. They are primary used for save/restore GPRs in jump-pad,
1088 not used for bytecode compiling. */
1089
1090#ifdef __powerpc64__
1091#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1092 GEN_LD (buf, rt, ra, si) : \
1093 GEN_LWZ (buf, rt, ra, si))
1094#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1095 GEN_STD (buf, rt, ra, si) : \
1096 GEN_STW (buf, rt, ra, si))
1097#else
1098#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1099#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1100#endif
1101
1102/* Generate a sequence of instructions to load IMM in the register REG.
1103 Write the instructions in BUF and return the number of bytes written. */
1104
1105static int
1106gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1107{
1108 uint32_t *p = buf;
1109
1110 if ((imm + 32768) < 65536)
1111 {
1112 /* li reg, imm[15:0] */
1113 p += GEN_LI (p, reg, imm);
1114 }
1115 else if ((imm >> 32) == 0)
1116 {
1117 /* lis reg, imm[31:16]
1118 ori reg, reg, imm[15:0]
1119 rldicl reg, reg, 0, 32 */
1120 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1121 if ((imm & 0xffff) != 0)
1122 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1123 /* Clear upper 32-bit if sign-bit is set. */
1124 if (imm & (1u << 31) && is_64)
1125 p += GEN_RLDICL (p, reg, reg, 0, 32);
1126 }
1127 else
1128 {
1129 gdb_assert (is_64);
1130 /* lis reg, <imm[63:48]>
1131 ori reg, reg, <imm[48:32]>
1132 rldicr reg, reg, 32, 31
1133 oris reg, reg, <imm[31:16]>
1134 ori reg, reg, <imm[15:0]> */
1135 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1136 if (((imm >> 32) & 0xffff) != 0)
1137 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1138 p += GEN_RLDICR (p, reg, reg, 32, 31);
1139 if (((imm >> 16) & 0xffff) != 0)
1140 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1141 if ((imm & 0xffff) != 0)
1142 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1143 }
1144
1145 return p - buf;
1146}
1147
1148/* Generate a sequence for atomically exchange at location LOCK.
1149 This code sequence clobbers r6, r7, r8. LOCK is the location for
1150 the atomic-xchg, OLD_VALUE is expected old value stored in the
1151 location, and R_NEW is a register for the new value. */
1152
1153static int
1154gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1155 int is_64)
1156{
1157 const int r_lock = 6;
1158 const int r_old = 7;
1159 const int r_tmp = 8;
1160 uint32_t *p = buf;
1161
1162 /*
1163 1: lwarx TMP, 0, LOCK
1164 cmpwi TMP, OLD
1165 bne 1b
1166 stwcx. NEW, 0, LOCK
1167 bne 1b */
1168
1169 p += gen_limm (p, r_lock, lock, is_64);
1170 p += gen_limm (p, r_old, old_value, is_64);
1171
1172 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1173 p += GEN_CMPW (p, r_tmp, r_old);
1174 p += GEN_BNE (p, -8);
1175 p += GEN_STWCX (p, r_new, 0, r_lock);
1176 p += GEN_BNE (p, -16);
1177
1178 return p - buf;
1179}
1180
1181/* Generate a sequence of instructions for calling a function
1182 at address of FN. Return the number of bytes are written in BUF. */
1183
1184static int
1185gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1186{
1187 uint32_t *p = buf;
1188
1189 /* Must be called by r12 for caller to calculate TOC address. */
1190 p += gen_limm (p, 12, fn, is_64);
1191 if (is_opd)
1192 {
1193 p += GEN_LOAD (p, 11, 12, 16, is_64);
1194 p += GEN_LOAD (p, 2, 12, 8, is_64);
1195 p += GEN_LOAD (p, 12, 12, 0, is_64);
1196 }
1197 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1198 *p++ = 0x4e800421; /* bctrl */
1199
1200 return p - buf;
1201}
1202
1203/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1204 of instruction. This function is used to adjust pc-relative instructions
1205 when copying. */
1206
1207static void
1208ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1209{
1210 uint32_t insn, op6;
1211 long rel, newrel;
1212
1213 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1214 op6 = PPC_OP6 (insn);
1215
1216 if (op6 == 18 && (insn & 2) == 0)
1217 {
1218 /* branch && AA = 0 */
1219 rel = PPC_LI (insn);
1220 newrel = (oldloc - *to) + rel;
1221
1222 /* Out of range. Cannot relocate instruction. */
1223 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1224 return;
1225
1226 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1227 }
1228 else if (op6 == 16 && (insn & 2) == 0)
1229 {
1230 /* conditional branch && AA = 0 */
1231
1232 /* If the new relocation is too big for even a 26-bit unconditional
1233 branch, there is nothing we can do. Just abort.
1234
1235 Otherwise, if it can be fit in 16-bit conditional branch, just
1236 copy the instruction and relocate the address.
1237
1238 If the it's big for conditional-branch (16-bit), try to invert the
1239 condition and jump with 26-bit branch. For example,
1240
1241 beq .Lgoto
1242 INSN1
1243
1244 =>
1245
1246 bne 1f (+8)
1247 b .Lgoto
1248 1:INSN1
1249
1250 After this transform, we are actually jump from *TO+4 instead of *TO,
1251 so check the relocation again because it will be 1-insn farther then
1252 before if *TO is after OLDLOC.
1253
1254
1255 For BDNZT (or so) is transformed from
1256
1257 bdnzt eq, .Lgoto
1258 INSN1
1259
1260 =>
1261
1262 bdz 1f (+12)
1263 bf eq, 1f (+8)
1264 b .Lgoto
1265 1:INSN1
1266
1267 See also "BO field encodings". */
1268
1269 rel = PPC_BD (insn);
1270 newrel = (oldloc - *to) + rel;
1271
1272 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1273 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1274 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1275 {
1276 newrel -= 4;
1277
1278 /* Out of range. Cannot relocate instruction. */
1279 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1280 return;
1281
1282 if ((PPC_BO (insn) & 0x14) == 0x4)
1283 insn ^= (1 << 24);
1284 else if ((PPC_BO (insn) & 0x14) == 0x10)
1285 insn ^= (1 << 22);
1286
1287 /* Jump over the unconditional branch. */
1288 insn = (insn & ~0xfffc) | 0x8;
1289 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1290 *to += 4;
1291
1292 /* Build a unconditional branch and copy LK bit. */
1293 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1294 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1295 *to += 4;
1296
1297 return;
1298 }
1299 else if ((PPC_BO (insn) & 0x14) == 0)
1300 {
1301 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1302 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1303
1304 newrel -= 8;
1305
1306 /* Out of range. Cannot relocate instruction. */
1307 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1308 return;
1309
1310 /* Copy BI field. */
1311 bf_insn |= (insn & 0x1f0000);
1312
1313 /* Invert condition. */
1314 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1315 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1316
1317 write_inferior_memory (*to, (unsigned char *) &bdnz_insn, 4);
1318 *to += 4;
1319 write_inferior_memory (*to, (unsigned char *) &bf_insn, 4);
1320 *to += 4;
1321
1322 /* Build a unconditional branch and copy LK bit. */
1323 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1324 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1325 *to += 4;
1326
1327 return;
1328 }
1329 else /* (BO & 0x14) == 0x14, branch always. */
1330 {
1331 /* Out of range. Cannot relocate instruction. */
1332 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1333 return;
1334
1335 /* Build a unconditional branch and copy LK bit. */
1336 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1337 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1338 *to += 4;
1339
1340 return;
1341 }
1342 }
1343
1344 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1345 *to += 4;
1346}
1347
1348/* Implement install_fast_tracepoint_jump_pad of target_ops.
1349 See target.h for details. */
1350
1351static int
1352ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1353 CORE_ADDR collector,
1354 CORE_ADDR lockaddr,
1355 ULONGEST orig_size,
1356 CORE_ADDR *jump_entry,
1357 CORE_ADDR *trampoline,
1358 ULONGEST *trampoline_size,
1359 unsigned char *jjump_pad_insn,
1360 ULONGEST *jjump_pad_insn_size,
1361 CORE_ADDR *adjusted_insn_addr,
1362 CORE_ADDR *adjusted_insn_addr_end,
1363 char *err)
1364{
1365 uint32_t buf[256];
1366 uint32_t *p = buf;
1367 int j, offset;
1368 CORE_ADDR buildaddr = *jump_entry;
1369 const CORE_ADDR entryaddr = *jump_entry;
1370 int rsz, min_frame, frame_size, tp_reg;
1371#ifdef __powerpc64__
1372 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1373 int is_64 = register_size (regcache->tdesc, 0) == 8;
1374 int is_opd = is_64 && !is_elfv2_inferior ();
1375#else
1376 int is_64 = 0, is_opd = 0;
1377#endif
1378
1379#ifdef __powerpc64__
1380 if (is_64)
1381 {
1382 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1383 rsz = 8;
1384 min_frame = 112;
1385 frame_size = (40 * rsz) + min_frame;
1386 tp_reg = 13;
1387 }
1388 else
1389 {
1390#endif
1391 rsz = 4;
1392 min_frame = 16;
1393 frame_size = (40 * rsz) + min_frame;
1394 tp_reg = 2;
1395#ifdef __powerpc64__
1396 }
1397#endif
1398
1399 /* Stack frame layout for this jump pad,
1400
1401 High thread_area (r13/r2) |
1402 tpoint - collecting_t obj
1403 PC/<tpaddr> | +36
1404 CTR | +35
1405 LR | +34
1406 XER | +33
1407 CR | +32
1408 R31 |
1409 R29 |
1410 ... |
1411 R1 | +1
1412 R0 - collected registers
1413 ... |
1414 ... |
1415 Low Back-chain -
1416
1417
1418 The code flow of this jump pad,
1419
1420 1. Adjust SP
1421 2. Save GPR and SPR
1422 3. Prepare argument
1423 4. Call gdb_collector
1424 5. Restore GPR and SPR
1425 6. Restore SP
1426 7. Build a jump for back to the program
1427 8. Copy/relocate original instruction
1428 9. Build a jump for replacing orignal instruction. */
1429
1430 /* Adjust stack pointer. */
1431 if (is_64)
1432 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1433 else
1434 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1435
1436 /* Store GPRs. Save R1 later, because it had just been modified, but
1437 we want the original value. */
1438 for (j = 2; j < 32; j++)
1439 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1440 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1441 /* Set r0 to the original value of r1 before adjusting stack frame,
1442 and then save it. */
1443 p += GEN_ADDI (p, 0, 1, frame_size);
1444 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1445
1446 /* Save CR, XER, LR, and CTR. */
1447 p += GEN_MFCR (p, 3); /* mfcr r3 */
1448 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1449 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1450 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1451 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1452 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1453 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1454 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1455
1456 /* Save PC<tpaddr> */
1457 p += gen_limm (p, 3, tpaddr, is_64);
1458 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1459
1460
1461 /* Setup arguments to collector. */
1462 /* Set r4 to collected registers. */
1463 p += GEN_ADDI (p, 4, 1, min_frame);
1464 /* Set r3 to TPOINT. */
1465 p += gen_limm (p, 3, tpoint, is_64);
1466
1467 /* Prepare collecting_t object for lock. */
1468 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1469 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1470 /* Set R5 to collecting object. */
1471 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1472
1473 p += GEN_LWSYNC (p);
1474 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1475 p += GEN_LWSYNC (p);
1476
1477 /* Call to collector. */
1478 p += gen_call (p, collector, is_64, is_opd);
1479
1480 /* Simply write 0 to release the lock. */
1481 p += gen_limm (p, 3, lockaddr, is_64);
1482 p += gen_limm (p, 4, 0, is_64);
1483 p += GEN_LWSYNC (p);
1484 p += GEN_STORE (p, 4, 3, 0, is_64);
1485
1486 /* Restore stack and registers. */
1487 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1488 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1489 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1490 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1491 p += GEN_MTCR (p, 3); /* mtcr r3 */
1492 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1493 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1494 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1495
1496 /* Restore GPRs. */
1497 for (j = 2; j < 32; j++)
1498 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1499 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1500 /* Restore SP. */
1501 p += GEN_ADDI (p, 1, 1, frame_size);
1502
1503 /* Flush instructions to inferior memory. */
1504 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1505
1506 /* Now, insert the original instruction to execute in the jump pad. */
1507 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1508 *adjusted_insn_addr_end = *adjusted_insn_addr;
1509 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1510
1511 /* Verify the relocation size. If should be 4 for normal copy,
1512 8 or 12 for some conditional branch. */
1513 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1514 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1515 {
1516 sprintf (err, "E.Unexpected instruction length = %d"
1517 "when relocate instruction.",
1518 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1519 return 1;
1520 }
1521
1522 buildaddr = *adjusted_insn_addr_end;
1523 p = buf;
1524 /* Finally, write a jump back to the program. */
1525 offset = (tpaddr + 4) - buildaddr;
1526 if (offset >= (1 << 25) || offset < -(1 << 25))
1527 {
1528 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1529 "(offset 0x%x > 26-bit).", offset);
1530 return 1;
1531 }
1532 /* b <tpaddr+4> */
1533 p += GEN_B (p, offset);
1534 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1535 *jump_entry = buildaddr + (p - buf) * 4;
1536
1537 /* The jump pad is now built. Wire in a jump to our jump pad. This
1538 is always done last (by our caller actually), so that we can
1539 install fast tracepoints with threads running. This relies on
1540 the agent's atomic write support. */
1541 offset = entryaddr - tpaddr;
1542 if (offset >= (1 << 25) || offset < -(1 << 25))
1543 {
1544 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1545 "(offset 0x%x > 26-bit).", offset);
1546 return 1;
1547 }
1548 /* b <jentry> */
1549 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1550 *jjump_pad_insn_size = 4;
1551
1552 return 0;
1553}
1554
1555/* Returns the minimum instruction length for installing a tracepoint. */
1556
1557static int
1558ppc_get_min_fast_tracepoint_insn_len (void)
1559{
1560 return 4;
1561}
1562
14e2b6d9
MK		 1563/* Emits a given buffer into the target at current_insn_ptr. Length
1564 is in units of 32-bit words. */
1565
1566static void
1567emit_insns (uint32_t *buf, int n)
1568{
1569 n = n * sizeof (uint32_t);
1570 write_inferior_memory (current_insn_ptr, (unsigned char *) buf, n);
1571 current_insn_ptr += n;
1572}
1573
1574#define __EMIT_ASM(NAME, INSNS) \
1575 do \
1576 { \
1577 extern uint32_t start_bcax_ ## NAME []; \
1578 extern uint32_t end_bcax_ ## NAME []; \
1579 emit_insns (start_bcax_ ## NAME, \
1580 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1581 __asm__ (".section .text.__ppcbcax\n\t" \
1582 "start_bcax_" #NAME ":\n\t" \
1583 INSNS "\n\t" \
1584 "end_bcax_" #NAME ":\n\t" \
1585 ".previous\n\t"); \
1586 } while (0)
1587
1588#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1589#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1590
1591/*
1592
1593 Bytecode execution stack frame - 32-bit
1594
1595 | LR save area (SP + 4)
1596 SP' -> +- Back chain (SP + 0)
1597 | Save r31 for access saved arguments
1598 | Save r30 for bytecode stack pointer
1599 | Save r4 for incoming argument *value
1600 | Save r3 for incoming argument regs
1601 r30 -> +- Bytecode execution stack
1602 |
1603 | 64-byte (8 doublewords) at initial.
1604 | Expand stack as needed.
1605 |
1606 +-
1607 | Some padding for minimum stack frame and 16-byte alignment.
1608 | 16 bytes.
1609 SP +- Back-chain (SP')
1610
1611 initial frame size
1612 = 16 + (4 * 4) + 64
1613 = 96
1614
1615 r30 is the stack-pointer for bytecode machine.
1616 It should point to next-empty, so we can use LDU for pop.
1617 r3 is used for cache of the high part of TOP value.
1618 It was the first argument, pointer to regs.
1619 r4 is used for cache of the low part of TOP value.
1620 It was the second argument, pointer to the result.
1621 We should set *result = TOP after leaving this function.
1622
1623 Note:
1624 * To restore stack at epilogue
1625 => sp = r31
1626 * To check stack is big enough for bytecode execution.
1627 => r30 - 8 > SP + 8
1628 * To return execution result.
1629 => 0(r4) = TOP
1630
1631 */
1632
1633/* Regardless of endian, register 3 is always high part, 4 is low part.
1634 These defines are used when the register pair is stored/loaded.
1635 Likewise, to simplify code, have a similiar define for 5:6. */
1636
1637#if __BYTE_ORDER == __LITTLE_ENDIAN
1638#define TOP_FIRST "4"
1639#define TOP_SECOND "3"
1640#define TMP_FIRST "6"
1641#define TMP_SECOND "5"
1642#else
1643#define TOP_FIRST "3"
1644#define TOP_SECOND "4"
1645#define TMP_FIRST "5"
1646#define TMP_SECOND "6"
1647#endif
1648
1649/* Emit prologue in inferior memory. See above comments. */
1650
1651static void
1652ppc_emit_prologue (void)
1653{
1654 EMIT_ASM (/* Save return address. */
1655 "mflr 0 \n"
1656 "stw 0, 4(1) \n"
1657 /* Adjust SP. 96 is the initial frame size. */
1658 "stwu 1, -96(1) \n"
1659 /* Save r30 and incoming arguments. */
1660 "stw 31, 96-4(1) \n"
1661 "stw 30, 96-8(1) \n"
1662 "stw 4, 96-12(1) \n"
1663 "stw 3, 96-16(1) \n"
1664 /* Point r31 to original r1 for access arguments. */
1665 "addi 31, 1, 96 \n"
1666 /* Set r30 to pointing stack-top. */
1667 "addi 30, 1, 64 \n"
1668 /* Initial r3/TOP to 0. */
1669 "li 3, 0 \n"
1670 "li 4, 0 \n");
1671}
1672
1673/* Emit epilogue in inferior memory. See above comments. */
1674
1675static void
1676ppc_emit_epilogue (void)
1677{
1678 EMIT_ASM (/* *result = TOP */
1679 "lwz 5, -12(31) \n"
1680 "stw " TOP_FIRST ", 0(5) \n"
1681 "stw " TOP_SECOND ", 4(5) \n"
1682 /* Restore registers. */
1683 "lwz 31, -4(31) \n"
1684 "lwz 30, -8(31) \n"
1685 /* Restore SP. */
1686 "lwz 1, 0(1) \n"
1687 /* Restore LR. */
1688 "lwz 0, 4(1) \n"
1689 /* Return 0 for no-error. */
1690 "li 3, 0 \n"
1691 "mtlr 0 \n"
1692 "blr \n");
1693}
1694
1695/* TOP = stack[--sp] + TOP */
1696
1697static void
1698ppc_emit_add (void)
1699{
1700 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1701 "lwz " TMP_SECOND ", 4(30)\n"
1702 "addc 4, 6, 4 \n"
1703 "adde 3, 5, 3 \n");
1704}
1705
1706/* TOP = stack[--sp] - TOP */
1707
1708static void
1709ppc_emit_sub (void)
1710{
1711 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1712 "lwz " TMP_SECOND ", 4(30) \n"
1713 "subfc 4, 4, 6 \n"
1714 "subfe 3, 3, 5 \n");
1715}
1716
1717/* TOP = stack[--sp] * TOP */
1718
1719static void
1720ppc_emit_mul (void)
1721{
1722 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1723 "lwz " TMP_SECOND ", 4(30) \n"
1724 "mulhwu 7, 6, 4 \n"
1725 "mullw 3, 6, 3 \n"
1726 "mullw 5, 4, 5 \n"
1727 "mullw 4, 6, 4 \n"
1728 "add 3, 5, 3 \n"
1729 "add 3, 7, 3 \n");
1730}
1731
1732/* TOP = stack[--sp] << TOP */
1733
1734static void
1735ppc_emit_lsh (void)
1736{
1737 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1738 "lwz " TMP_SECOND ", 4(30) \n"
1739 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1740 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1741 "slw 5, 5, 4\n" /* Shift high part left */
1742 "slw 4, 6, 4\n" /* Shift low part left */
1743 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1744 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1745 "or 3, 5, 3\n"
1746 "or 3, 7, 3\n"); /* Assemble high part */
1747}
1748
1749/* Top = stack[--sp] >> TOP
1750 (Arithmetic shift right) */
1751
1752static void
1753ppc_emit_rsh_signed (void)
1754{
1755 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1756 "lwz " TMP_SECOND ", 4(30) \n"
1757 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1758 "sraw 3, 5, 4\n" /* Shift high part right */
1759 "cmpwi 7, 1\n"
1760 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1761 "sraw 4, 5, 7\n" /* Shift high to low */
1762 "b 2f\n"
1763 "1:\n"
1764 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1765 "srw 4, 6, 4\n" /* Shift low part right */
1766 "slw 5, 5, 7\n" /* Shift high to low */
1767 "or 4, 4, 5\n" /* Assemble low part */
1768 "2:\n");
1769}
1770
1771/* Top = stack[--sp] >> TOP
1772 (Logical shift right) */
1773
1774static void
1775ppc_emit_rsh_unsigned (void)
1776{
1777 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1778 "lwz " TMP_SECOND ", 4(30) \n"
1779 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1780 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1781 "srw 6, 6, 4\n" /* Shift low part right */
1782 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1783 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1784 "or 6, 6, 3\n"
1785 "srw 3, 5, 4\n" /* Shift high part right */
1786 "or 4, 6, 7\n"); /* Assemble low part */
1787}
1788
1789/* Emit code for signed-extension specified by ARG. */
1790
1791static void
1792ppc_emit_ext (int arg)
1793{
1794 switch (arg)
1795 {
1796 case 8:
1797 EMIT_ASM ("extsb 4, 4\n"
1798 "srawi 3, 4, 31");
1799 break;
1800 case 16:
1801 EMIT_ASM ("extsh 4, 4\n"
1802 "srawi 3, 4, 31");
1803 break;
1804 case 32:
1805 EMIT_ASM ("srawi 3, 4, 31");
1806 break;
1807 default:
1808 emit_error = 1;
1809 }
1810}
1811
1812/* Emit code for zero-extension specified by ARG. */
1813
1814static void
1815ppc_emit_zero_ext (int arg)
1816{
1817 switch (arg)
1818 {
1819 case 8:
1820 EMIT_ASM ("clrlwi 4,4,24\n"
1821 "li 3, 0\n");
1822 break;
1823 case 16:
1824 EMIT_ASM ("clrlwi 4,4,16\n"
1825 "li 3, 0\n");
1826 break;
1827 case 32:
1828 EMIT_ASM ("li 3, 0");
1829 break;
1830 default:
1831 emit_error = 1;
1832 }
1833}
1834
1835/* TOP = !TOP
1836 i.e., TOP = (TOP == 0) ? 1 : 0; */
1837
1838static void
1839ppc_emit_log_not (void)
1840{
1841 EMIT_ASM ("or 4, 3, 4 \n"
1842 "cntlzw 4, 4 \n"
1843 "srwi 4, 4, 5 \n"
1844 "li 3, 0 \n");
1845}
1846
1847/* TOP = stack[--sp] & TOP */
1848
1849static void
1850ppc_emit_bit_and (void)
1851{
1852 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1853 "lwz " TMP_SECOND ", 4(30) \n"
1854 "and 4, 6, 4 \n"
1855 "and 3, 5, 3 \n");
1856}
1857
1858/* TOP = stack[--sp] | TOP */
1859
1860static void
1861ppc_emit_bit_or (void)
1862{
1863 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1864 "lwz " TMP_SECOND ", 4(30) \n"
1865 "or 4, 6, 4 \n"
1866 "or 3, 5, 3 \n");
1867}
1868
1869/* TOP = stack[--sp] ^ TOP */
1870
1871static void
1872ppc_emit_bit_xor (void)
1873{
1874 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1875 "lwz " TMP_SECOND ", 4(30) \n"
1876 "xor 4, 6, 4 \n"
1877 "xor 3, 5, 3 \n");
1878}
1879
1880/* TOP = ~TOP
1881 i.e., TOP = ~(TOP | TOP) */
1882
1883static void
1884ppc_emit_bit_not (void)
1885{
1886 EMIT_ASM ("nor 3, 3, 3 \n"
1887 "nor 4, 4, 4 \n");
1888}
1889
1890/* TOP = stack[--sp] == TOP */
1891
1892static void
1893ppc_emit_equal (void)
1894{
1895 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1896 "lwz " TMP_SECOND ", 4(30) \n"
1897 "xor 4, 6, 4 \n"
1898 "xor 3, 5, 3 \n"
1899 "or 4, 3, 4 \n"
1900 "cntlzw 4, 4 \n"
1901 "srwi 4, 4, 5 \n"
1902 "li 3, 0 \n");
1903}
1904
1905/* TOP = stack[--sp] < TOP
1906 (Signed comparison) */
1907
1908static void
1909ppc_emit_less_signed (void)
1910{
1911 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1912 "lwz " TMP_SECOND ", 4(30) \n"
1913 "cmplw 6, 6, 4 \n"
1914 "cmpw 7, 5, 3 \n"
1915 /* CR6 bit 0 = low less and high equal */
1916 "crand 6*4+0, 6*4+0, 7*4+2\n"
1917 /* CR7 bit 0 = (low less and high equal) or high less */
1918 "cror 7*4+0, 7*4+0, 6*4+0\n"
1919 "mfcr 4 \n"
1920 "rlwinm 4, 4, 29, 31, 31 \n"
1921 "li 3, 0 \n");
1922}
1923
1924/* TOP = stack[--sp] < TOP
1925 (Unsigned comparison) */
1926
1927static void
1928ppc_emit_less_unsigned (void)
1929{
1930 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1931 "lwz " TMP_SECOND ", 4(30) \n"
1932 "cmplw 6, 6, 4 \n"
1933 "cmplw 7, 5, 3 \n"
1934 /* CR6 bit 0 = low less and high equal */
1935 "crand 6*4+0, 6*4+0, 7*4+2\n"
1936 /* CR7 bit 0 = (low less and high equal) or high less */
1937 "cror 7*4+0, 7*4+0, 6*4+0\n"
1938 "mfcr 4 \n"
1939 "rlwinm 4, 4, 29, 31, 31 \n"
1940 "li 3, 0 \n");
1941}
1942
1943/* Access the memory address in TOP in size of SIZE.
1944 Zero-extend the read value. */
1945
1946static void
1947ppc_emit_ref (int size)
1948{
1949 switch (size)
1950 {
1951 case 1:
1952 EMIT_ASM ("lbz 4, 0(4)\n"
1953 "li 3, 0");
1954 break;
1955 case 2:
1956 EMIT_ASM ("lhz 4, 0(4)\n"
1957 "li 3, 0");
1958 break;
1959 case 4:
1960 EMIT_ASM ("lwz 4, 0(4)\n"
1961 "li 3, 0");
1962 break;
1963 case 8:
1964 if (__BYTE_ORDER == __LITTLE_ENDIAN)
1965 EMIT_ASM ("lwz 3, 4(4)\n"
1966 "lwz 4, 0(4)");
1967 else
1968 EMIT_ASM ("lwz 3, 0(4)\n"
1969 "lwz 4, 4(4)");
1970 break;
1971 }
1972}
1973
1974/* TOP = NUM */
1975
1976static void
1977ppc_emit_const (LONGEST num)
1978{
1979 uint32_t buf[10];
1980 uint32_t *p = buf;
1981
1982 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
1983 p += gen_limm (p, 4, num & 0xffffffff, 0);
1984
1985 emit_insns (buf, p - buf);
1986 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
1987}
1988
1989/* Set TOP to the value of register REG by calling get_raw_reg function
1990 with two argument, collected buffer and register number. */
1991
1992static void
1993ppc_emit_reg (int reg)
1994{
1995 uint32_t buf[13];
1996 uint32_t *p = buf;
1997
1998 /* fctx->regs is passed in r3 and then saved in -16(31). */
1999 p += GEN_LWZ (p, 3, 31, -16);
2000 p += GEN_LI (p, 4, reg); /* li r4, reg */
2001 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
2002
2003 emit_insns (buf, p - buf);
2004 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2005
2006 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2007 {
2008 EMIT_ASM ("mr 5, 4\n"
2009 "mr 4, 3\n"
2010 "mr 3, 5\n");
2011 }
2012}
2013
2014/* TOP = stack[--sp] */
2015
2016static void
2017ppc_emit_pop (void)
2018{
2019 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
2020 "lwz " TOP_SECOND ", 4(30) \n");
2021}
2022
2023/* stack[sp++] = TOP
2024
2025 Because we may use up bytecode stack, expand 8 doublewords more
2026 if needed. */
2027
2028static void
2029ppc_emit_stack_flush (void)
2030{
2031 /* Make sure bytecode stack is big enough before push.
2032 Otherwise, expand 64-byte more. */
2033
2034 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2035 " stw " TOP_SECOND ", 4(30)\n"
2036 " addi 5, 30, -(8 + 8) \n"
2037 " cmpw 7, 5, 1 \n"
2038 " bgt 7, 1f \n"
2039 " stwu 31, -64(1) \n"
2040 "1:addi 30, 30, -8 \n");
2041}
2042
2043/* Swap TOP and stack[sp-1] */
2044
2045static void
2046ppc_emit_swap (void)
2047{
2048 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2049 "lwz " TMP_SECOND ", 12(30) \n"
2050 "stw " TOP_FIRST ", 8(30) \n"
2051 "stw " TOP_SECOND ", 12(30) \n"
2052 "mr 3, 5 \n"
2053 "mr 4, 6 \n");
2054}
2055
2056/* Discard N elements in the stack. Also used for ppc64. */
2057
2058static void
2059ppc_emit_stack_adjust (int n)
2060{
2061 uint32_t buf[6];
2062 uint32_t *p = buf;
2063
2064 n = n << 3;
2065 if ((n >> 15) != 0)
2066 {
2067 emit_error = 1;
2068 return;
2069 }
2070
2071 p += GEN_ADDI (p, 30, 30, n);
2072
2073 emit_insns (buf, p - buf);
2074 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2075}
2076
2077/* Call function FN. */
2078
2079static void
2080ppc_emit_call (CORE_ADDR fn)
2081{
2082 uint32_t buf[11];
2083 uint32_t *p = buf;
2084
2085 p += gen_call (p, fn, 0, 0);
2086
2087 emit_insns (buf, p - buf);
2088 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2089}
2090
2091/* FN's prototype is `LONGEST(*fn)(int)'.
2092 TOP = fn (arg1)
2093 */
2094
2095static void
2096ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2097{
2098 uint32_t buf[15];
2099 uint32_t *p = buf;
2100
2101 /* Setup argument. arg1 is a 16-bit value. */
2102 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2103 p += gen_call (p, fn, 0, 0);
2104
2105 emit_insns (buf, p - buf);
2106 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2107
2108 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2109 {
2110 EMIT_ASM ("mr 5, 4\n"
2111 "mr 4, 3\n"
2112 "mr 3, 5\n");
2113 }
2114}
2115
2116/* FN's prototype is `void(*fn)(int,LONGEST)'.
2117 fn (arg1, TOP)
2118
2119 TOP should be preserved/restored before/after the call. */
2120
2121static void
2122ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2123{
2124 uint32_t buf[21];
2125 uint32_t *p = buf;
2126
2127 /* Save TOP. 0(30) is next-empty. */
2128 p += GEN_STW (p, 3, 30, 0);
2129 p += GEN_STW (p, 4, 30, 4);
2130
2131 /* Setup argument. arg1 is a 16-bit value. */
2132 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2133 {
2134 p += GEN_MR (p, 5, 4);
2135 p += GEN_MR (p, 6, 3);
2136 }
2137 else
2138 {
2139 p += GEN_MR (p, 5, 3);
2140 p += GEN_MR (p, 6, 4);
2141 }
2142 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2143 p += gen_call (p, fn, 0, 0);
2144
2145 /* Restore TOP */
2146 p += GEN_LWZ (p, 3, 30, 0);
2147 p += GEN_LWZ (p, 4, 30, 4);
2148
2149 emit_insns (buf, p - buf);
2150 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2151}
2152
2153/* Note in the following goto ops:
2154
2155 When emitting goto, the target address is later relocated by
2156 write_goto_address. OFFSET_P is the offset of the branch instruction
2157 in the code sequence, and SIZE_P is how to relocate the instruction,
2158 recognized by ppc_write_goto_address. In current implementation,
2159 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2160 */
2161
2162/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2163
2164static void
2165ppc_emit_if_goto (int *offset_p, int *size_p)
2166{
2167 EMIT_ASM ("or. 3, 3, 4 \n"
2168 "lwzu " TOP_FIRST ", 8(30) \n"
2169 "lwz " TOP_SECOND ", 4(30) \n"
2170 "1:bne 0, 1b \n");
2171
2172 if (offset_p)
2173 *offset_p = 12;
2174 if (size_p)
2175 *size_p = 14;
2176}
2177
2178/* Unconditional goto. Also used for ppc64. */
2179
2180static void
2181ppc_emit_goto (int *offset_p, int *size_p)
2182{
2183 EMIT_ASM ("1:b 1b");
2184
2185 if (offset_p)
2186 *offset_p = 0;
2187 if (size_p)
2188 *size_p = 24;
2189}
2190
2191/* Goto if stack[--sp] == TOP */
2192
2193static void
2194ppc_emit_eq_goto (int *offset_p, int *size_p)
2195{
2196 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2197 "lwz " TMP_SECOND ", 4(30) \n"
2198 "xor 4, 6, 4 \n"
2199 "xor 3, 5, 3 \n"
2200 "or. 3, 3, 4 \n"
2201 "lwzu " TOP_FIRST ", 8(30) \n"
2202 "lwz " TOP_SECOND ", 4(30) \n"
2203 "1:beq 0, 1b \n");
2204
2205 if (offset_p)
2206 *offset_p = 28;
2207 if (size_p)
2208 *size_p = 14;
2209}
2210
2211/* Goto if stack[--sp] != TOP */
2212
2213static void
2214ppc_emit_ne_goto (int *offset_p, int *size_p)
2215{
2216 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2217 "lwz " TMP_SECOND ", 4(30) \n"
2218 "xor 4, 6, 4 \n"
2219 "xor 3, 5, 3 \n"
2220 "or. 3, 3, 4 \n"
2221 "lwzu " TOP_FIRST ", 8(30) \n"
2222 "lwz " TOP_SECOND ", 4(30) \n"
2223 "1:bne 0, 1b \n");
2224
2225 if (offset_p)
2226 *offset_p = 28;
2227 if (size_p)
2228 *size_p = 14;
2229}
2230
2231/* Goto if stack[--sp] < TOP */
2232
2233static void
2234ppc_emit_lt_goto (int *offset_p, int *size_p)
2235{
2236 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2237 "lwz " TMP_SECOND ", 4(30) \n"
2238 "cmplw 6, 6, 4 \n"
2239 "cmpw 7, 5, 3 \n"
2240 /* CR6 bit 0 = low less and high equal */
2241 "crand 6*4+0, 6*4+0, 7*4+2\n"
2242 /* CR7 bit 0 = (low less and high equal) or high less */
2243 "cror 7*4+0, 7*4+0, 6*4+0\n"
2244 "lwzu " TOP_FIRST ", 8(30) \n"
2245 "lwz " TOP_SECOND ", 4(30)\n"
2246 "1:blt 7, 1b \n");
2247
2248 if (offset_p)
2249 *offset_p = 32;
2250 if (size_p)
2251 *size_p = 14;
2252}
2253
2254/* Goto if stack[--sp] <= TOP */
2255
2256static void
2257ppc_emit_le_goto (int *offset_p, int *size_p)
2258{
2259 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2260 "lwz " TMP_SECOND ", 4(30) \n"
2261 "cmplw 6, 6, 4 \n"
2262 "cmpw 7, 5, 3 \n"
2263 /* CR6 bit 0 = low less/equal and high equal */
2264 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2265 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2266 "cror 7*4+0, 7*4+0, 6*4+0\n"
2267 "lwzu " TOP_FIRST ", 8(30) \n"
2268 "lwz " TOP_SECOND ", 4(30)\n"
2269 "1:blt 7, 1b \n");
2270
2271 if (offset_p)
2272 *offset_p = 32;
2273 if (size_p)
2274 *size_p = 14;
2275}
2276
2277/* Goto if stack[--sp] > TOP */
2278
2279static void
2280ppc_emit_gt_goto (int *offset_p, int *size_p)
2281{
2282 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2283 "lwz " TMP_SECOND ", 4(30) \n"
2284 "cmplw 6, 6, 4 \n"
2285 "cmpw 7, 5, 3 \n"
2286 /* CR6 bit 0 = low greater and high equal */
2287 "crand 6*4+0, 6*4+1, 7*4+2\n"
2288 /* CR7 bit 0 = (low greater and high equal) or high greater */
2289 "cror 7*4+0, 7*4+1, 6*4+0\n"
2290 "lwzu " TOP_FIRST ", 8(30) \n"
2291 "lwz " TOP_SECOND ", 4(30)\n"
2292 "1:blt 7, 1b \n");
2293
2294 if (offset_p)
2295 *offset_p = 32;
2296 if (size_p)
2297 *size_p = 14;
2298}
2299
2300/* Goto if stack[--sp] >= TOP */
2301
2302static void
2303ppc_emit_ge_goto (int *offset_p, int *size_p)
2304{
2305 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2306 "lwz " TMP_SECOND ", 4(30) \n"
2307 "cmplw 6, 6, 4 \n"
2308 "cmpw 7, 5, 3 \n"
2309 /* CR6 bit 0 = low ge and high equal */
2310 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2311 /* CR7 bit 0 = (low ge and high equal) or high greater */
2312 "cror 7*4+0, 7*4+1, 6*4+0\n"
2313 "lwzu " TOP_FIRST ", 8(30)\n"
2314 "lwz " TOP_SECOND ", 4(30)\n"
2315 "1:blt 7, 1b \n");
2316
2317 if (offset_p)
2318 *offset_p = 32;
2319 if (size_p)
2320 *size_p = 14;
2321}
2322
2323/* Relocate previous emitted branch instruction. FROM is the address
2324 of the branch instruction, TO is the goto target address, and SIZE
2325 if the value we set by *SIZE_P before. Currently, it is either
2326 24 or 14 of branch and conditional-branch instruction.
2327 Also used for ppc64. */
2328
2329static void
2330ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2331{
2332 long rel = to - from;
2333 uint32_t insn;
2334 int opcd;
2335
2336 read_inferior_memory (from, (unsigned char *) &insn, 4);
2337 opcd = (insn >> 26) & 0x3f;
2338
2339 switch (size)
2340 {
2341 case 14:
2342 if (opcd != 16
2343 || (rel >= (1 << 15) || rel < -(1 << 15)))
2344 emit_error = 1;
2345 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2346 break;
2347 case 24:
2348 if (opcd != 18
2349 || (rel >= (1 << 25) || rel < -(1 << 25)))
2350 emit_error = 1;
2351 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2352 break;
2353 default:
2354 emit_error = 1;
2355 }
2356
2357 if (!emit_error)
2358 write_inferior_memory (from, (unsigned char *) &insn, 4);
2359}
2360
2361/* Table of emit ops for 32-bit. */
2362
2363static struct emit_ops ppc_emit_ops_impl =
2364{
2365 ppc_emit_prologue,
2366 ppc_emit_epilogue,
2367 ppc_emit_add,
2368 ppc_emit_sub,
2369 ppc_emit_mul,
2370 ppc_emit_lsh,
2371 ppc_emit_rsh_signed,
2372 ppc_emit_rsh_unsigned,
2373 ppc_emit_ext,
2374 ppc_emit_log_not,
2375 ppc_emit_bit_and,
2376 ppc_emit_bit_or,
2377 ppc_emit_bit_xor,
2378 ppc_emit_bit_not,
2379 ppc_emit_equal,
2380 ppc_emit_less_signed,
2381 ppc_emit_less_unsigned,
2382 ppc_emit_ref,
2383 ppc_emit_if_goto,
2384 ppc_emit_goto,
2385 ppc_write_goto_address,
2386 ppc_emit_const,
2387 ppc_emit_call,
2388 ppc_emit_reg,
2389 ppc_emit_pop,
2390 ppc_emit_stack_flush,
2391 ppc_emit_zero_ext,
2392 ppc_emit_swap,
2393 ppc_emit_stack_adjust,
2394 ppc_emit_int_call_1,
2395 ppc_emit_void_call_2,
2396 ppc_emit_eq_goto,
2397 ppc_emit_ne_goto,
2398 ppc_emit_lt_goto,
2399 ppc_emit_le_goto,
2400 ppc_emit_gt_goto,
2401 ppc_emit_ge_goto
2402};
2403
2404#ifdef __powerpc64__
2405
2406/*
2407
2408 Bytecode execution stack frame - 64-bit
2409
2410 | LR save area (SP + 16)
2411 | CR save area (SP + 8)
2412 SP' -> +- Back chain (SP + 0)
2413 | Save r31 for access saved arguments
2414 | Save r30 for bytecode stack pointer
2415 | Save r4 for incoming argument *value
2416 | Save r3 for incoming argument regs
2417 r30 -> +- Bytecode execution stack
2418 |
2419 | 64-byte (8 doublewords) at initial.
2420 | Expand stack as needed.
2421 |
2422 +-
2423 | Some padding for minimum stack frame.
2424 | 112 for ELFv1.
2425 SP +- Back-chain (SP')
2426
2427 initial frame size
2428 = 112 + (4 * 8) + 64
2429 = 208
2430
2431 r30 is the stack-pointer for bytecode machine.
2432 It should point to next-empty, so we can use LDU for pop.
2433 r3 is used for cache of TOP value.
2434 It was the first argument, pointer to regs.
2435 r4 is the second argument, pointer to the result.
2436 We should set *result = TOP after leaving this function.
2437
2438 Note:
2439 * To restore stack at epilogue
2440 => sp = r31
2441 * To check stack is big enough for bytecode execution.
2442 => r30 - 8 > SP + 112
2443 * To return execution result.
2444 => 0(r4) = TOP
2445
2446 */
2447
2448/* Emit prologue in inferior memory. See above comments. */
2449
2450static void
2451ppc64v1_emit_prologue (void)
2452{
2453 /* On ELFv1, function pointers really point to function descriptor,
2454 so emit one here. We don't care about contents of words 1 and 2,
2455 so let them just overlap out code. */
2456 uint64_t opd = current_insn_ptr + 8;
2457 uint32_t buf[2];
2458
2459 /* Mind the strict aliasing rules. */
2460 memcpy (buf, &opd, sizeof buf);
2461 emit_insns(buf, 2);
2462 EMIT_ASM (/* Save return address. */
2463 "mflr 0 \n"
2464 "std 0, 16(1) \n"
2465 /* Save r30 and incoming arguments. */
2466 "std 31, -8(1) \n"
2467 "std 30, -16(1) \n"
2468 "std 4, -24(1) \n"
2469 "std 3, -32(1) \n"
2470 /* Point r31 to current r1 for access arguments. */
2471 "mr 31, 1 \n"
2472 /* Adjust SP. 208 is the initial frame size. */
2473 "stdu 1, -208(1) \n"
2474 /* Set r30 to pointing stack-top. */
2475 "addi 30, 1, 168 \n"
2476 /* Initial r3/TOP to 0. */
2477 "li 3, 0 \n");
2478}
2479
2480/* Emit prologue in inferior memory. See above comments. */
2481
2482static void
2483ppc64v2_emit_prologue (void)
2484{
2485 EMIT_ASM (/* Save return address. */
2486 "mflr 0 \n"
2487 "std 0, 16(1) \n"
2488 /* Save r30 and incoming arguments. */
2489 "std 31, -8(1) \n"
2490 "std 30, -16(1) \n"
2491 "std 4, -24(1) \n"
2492 "std 3, -32(1) \n"
2493 /* Point r31 to current r1 for access arguments. */
2494 "mr 31, 1 \n"
2495 /* Adjust SP. 208 is the initial frame size. */
2496 "stdu 1, -208(1) \n"
2497 /* Set r30 to pointing stack-top. */
2498 "addi 30, 1, 168 \n"
2499 /* Initial r3/TOP to 0. */
2500 "li 3, 0 \n");
2501}
2502
2503/* Emit epilogue in inferior memory. See above comments. */
2504
2505static void
2506ppc64_emit_epilogue (void)
2507{
2508 EMIT_ASM (/* Restore SP. */
2509 "ld 1, 0(1) \n"
2510 /* *result = TOP */
2511 "ld 4, -24(1) \n"
2512 "std 3, 0(4) \n"
2513 /* Restore registers. */
2514 "ld 31, -8(1) \n"
2515 "ld 30, -16(1) \n"
2516 /* Restore LR. */
2517 "ld 0, 16(1) \n"
2518 /* Return 0 for no-error. */
2519 "li 3, 0 \n"
2520 "mtlr 0 \n"
2521 "blr \n");
2522}
2523
2524/* TOP = stack[--sp] + TOP */
2525
2526static void
2527ppc64_emit_add (void)
2528{
2529 EMIT_ASM ("ldu 4, 8(30) \n"
2530 "add 3, 4, 3 \n");
2531}
2532
2533/* TOP = stack[--sp] - TOP */
2534
2535static void
2536ppc64_emit_sub (void)
2537{
2538 EMIT_ASM ("ldu 4, 8(30) \n"
2539 "sub 3, 4, 3 \n");
2540}
2541
2542/* TOP = stack[--sp] * TOP */
2543
2544static void
2545ppc64_emit_mul (void)
2546{
2547 EMIT_ASM ("ldu 4, 8(30) \n"
2548 "mulld 3, 4, 3 \n");
2549}
2550
2551/* TOP = stack[--sp] << TOP */
2552
2553static void
2554ppc64_emit_lsh (void)
2555{
2556 EMIT_ASM ("ldu 4, 8(30) \n"
2557 "sld 3, 4, 3 \n");
2558}
2559
2560/* Top = stack[--sp] >> TOP
2561 (Arithmetic shift right) */
2562
2563static void
2564ppc64_emit_rsh_signed (void)
2565{
2566 EMIT_ASM ("ldu 4, 8(30) \n"
2567 "srad 3, 4, 3 \n");
2568}
2569
2570/* Top = stack[--sp] >> TOP
2571 (Logical shift right) */
2572
2573static void
2574ppc64_emit_rsh_unsigned (void)
2575{
2576 EMIT_ASM ("ldu 4, 8(30) \n"
2577 "srd 3, 4, 3 \n");
2578}
2579
2580/* Emit code for signed-extension specified by ARG. */
2581
2582static void
2583ppc64_emit_ext (int arg)
2584{
2585 switch (arg)
2586 {
2587 case 8:
2588 EMIT_ASM ("extsb 3, 3");
2589 break;
2590 case 16:
2591 EMIT_ASM ("extsh 3, 3");
2592 break;
2593 case 32:
2594 EMIT_ASM ("extsw 3, 3");
2595 break;
2596 default:
2597 emit_error = 1;
2598 }
2599}
2600
2601/* Emit code for zero-extension specified by ARG. */
2602
2603static void
2604ppc64_emit_zero_ext (int arg)
2605{
2606 switch (arg)
2607 {
2608 case 8:
2609 EMIT_ASM ("rldicl 3,3,0,56");
2610 break;
2611 case 16:
2612 EMIT_ASM ("rldicl 3,3,0,48");
2613 break;
2614 case 32:
2615 EMIT_ASM ("rldicl 3,3,0,32");
2616 break;
2617 default:
2618 emit_error = 1;
2619 }
2620}
2621
2622/* TOP = !TOP
2623 i.e., TOP = (TOP == 0) ? 1 : 0; */
2624
2625static void
2626ppc64_emit_log_not (void)
2627{
2628 EMIT_ASM ("cntlzd 3, 3 \n"
2629 "srdi 3, 3, 6 \n");
2630}
2631
2632/* TOP = stack[--sp] & TOP */
2633
2634static void
2635ppc64_emit_bit_and (void)
2636{
2637 EMIT_ASM ("ldu 4, 8(30) \n"
2638 "and 3, 4, 3 \n");
2639}
2640
2641/* TOP = stack[--sp] | TOP */
2642
2643static void
2644ppc64_emit_bit_or (void)
2645{
2646 EMIT_ASM ("ldu 4, 8(30) \n"
2647 "or 3, 4, 3 \n");
2648}
2649
2650/* TOP = stack[--sp] ^ TOP */
2651
2652static void
2653ppc64_emit_bit_xor (void)
2654{
2655 EMIT_ASM ("ldu 4, 8(30) \n"
2656 "xor 3, 4, 3 \n");
2657}
2658
2659/* TOP = ~TOP
2660 i.e., TOP = ~(TOP | TOP) */
2661
2662static void
2663ppc64_emit_bit_not (void)
2664{
2665 EMIT_ASM ("nor 3, 3, 3 \n");
2666}
2667
2668/* TOP = stack[--sp] == TOP */
2669
2670static void
2671ppc64_emit_equal (void)
2672{
2673 EMIT_ASM ("ldu 4, 8(30) \n"
2674 "xor 3, 3, 4 \n"
2675 "cntlzd 3, 3 \n"
2676 "srdi 3, 3, 6 \n");
2677}
2678
2679/* TOP = stack[--sp] < TOP
2680 (Signed comparison) */
2681
2682static void
2683ppc64_emit_less_signed (void)
2684{
2685 EMIT_ASM ("ldu 4, 8(30) \n"
2686 "cmpd 7, 4, 3 \n"
2687 "mfcr 3 \n"
2688 "rlwinm 3, 3, 29, 31, 31 \n");
2689}
2690
2691/* TOP = stack[--sp] < TOP
2692 (Unsigned comparison) */
2693
2694static void
2695ppc64_emit_less_unsigned (void)
2696{
2697 EMIT_ASM ("ldu 4, 8(30) \n"
2698 "cmpld 7, 4, 3 \n"
2699 "mfcr 3 \n"
2700 "rlwinm 3, 3, 29, 31, 31 \n");
2701}
2702
2703/* Access the memory address in TOP in size of SIZE.
2704 Zero-extend the read value. */
2705
2706static void
2707ppc64_emit_ref (int size)
2708{
2709 switch (size)
2710 {
2711 case 1:
2712 EMIT_ASM ("lbz 3, 0(3)");
2713 break;
2714 case 2:
2715 EMIT_ASM ("lhz 3, 0(3)");
2716 break;
2717 case 4:
2718 EMIT_ASM ("lwz 3, 0(3)");
2719 break;
2720 case 8:
2721 EMIT_ASM ("ld 3, 0(3)");
2722 break;
2723 }
2724}
2725
2726/* TOP = NUM */
2727
2728static void
2729ppc64_emit_const (LONGEST num)
2730{
2731 uint32_t buf[5];
2732 uint32_t *p = buf;
2733
2734 p += gen_limm (p, 3, num, 1);
2735
2736 emit_insns (buf, p - buf);
2737 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2738}
2739
2740/* Set TOP to the value of register REG by calling get_raw_reg function
2741 with two argument, collected buffer and register number. */
2742
2743static void
2744ppc64v1_emit_reg (int reg)
2745{
2746 uint32_t buf[15];
2747 uint32_t *p = buf;
2748
2749 /* fctx->regs is passed in r3 and then saved in 176(1). */
2750 p += GEN_LD (p, 3, 31, -32);
2751 p += GEN_LI (p, 4, reg);
2752 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2753 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
2754 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2755
2756 emit_insns (buf, p - buf);
2757 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2758}
2759
2760/* Likewise, for ELFv2. */
2761
2762static void
2763ppc64v2_emit_reg (int reg)
2764{
2765 uint32_t buf[12];
2766 uint32_t *p = buf;
2767
2768 /* fctx->regs is passed in r3 and then saved in 176(1). */
2769 p += GEN_LD (p, 3, 31, -32);
2770 p += GEN_LI (p, 4, reg);
2771 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2772 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
2773 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2774
2775 emit_insns (buf, p - buf);
2776 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2777}
2778
2779/* TOP = stack[--sp] */
2780
2781static void
2782ppc64_emit_pop (void)
2783{
2784 EMIT_ASM ("ldu 3, 8(30)");
2785}
2786
2787/* stack[sp++] = TOP
2788
2789 Because we may use up bytecode stack, expand 8 doublewords more
2790 if needed. */
2791
2792static void
2793ppc64_emit_stack_flush (void)
2794{
2795 /* Make sure bytecode stack is big enough before push.
2796 Otherwise, expand 64-byte more. */
2797
2798 EMIT_ASM (" std 3, 0(30) \n"
2799 " addi 4, 30, -(112 + 8) \n"
2800 " cmpd 7, 4, 1 \n"
2801 " bgt 7, 1f \n"
2802 " stdu 31, -64(1) \n"
2803 "1:addi 30, 30, -8 \n");
2804}
2805
2806/* Swap TOP and stack[sp-1] */
2807
2808static void
2809ppc64_emit_swap (void)
2810{
2811 EMIT_ASM ("ld 4, 8(30) \n"
2812 "std 3, 8(30) \n"
2813 "mr 3, 4 \n");
2814}
2815
2816/* Call function FN - ELFv1. */
2817
2818static void
2819ppc64v1_emit_call (CORE_ADDR fn)
2820{
2821 uint32_t buf[13];
2822 uint32_t *p = buf;
2823
2824 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2825 p += gen_call (p, fn, 1, 1);
2826 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2827
2828 emit_insns (buf, p - buf);
2829 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2830}
2831
2832/* Call function FN - ELFv2. */
2833
2834static void
2835ppc64v2_emit_call (CORE_ADDR fn)
2836{
2837 uint32_t buf[10];
2838 uint32_t *p = buf;
2839
2840 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2841 p += gen_call (p, fn, 1, 0);
2842 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2843
2844 emit_insns (buf, p - buf);
2845 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2846}
2847
2848/* FN's prototype is `LONGEST(*fn)(int)'.
2849 TOP = fn (arg1)
2850 */
2851
2852static void
2853ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
2854{
2855 uint32_t buf[13];
2856 uint32_t *p = buf;
2857
2858 /* Setup argument. arg1 is a 16-bit value. */
2859 p += gen_limm (p, 3, arg1, 1);
2860 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2861 p += gen_call (p, fn, 1, 1);
2862 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2863
2864 emit_insns (buf, p - buf);
2865 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2866}
2867
2868/* Likewise for ELFv2. */
2869
2870static void
2871ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
2872{
2873 uint32_t buf[10];
2874 uint32_t *p = buf;
2875
2876 /* Setup argument. arg1 is a 16-bit value. */
2877 p += gen_limm (p, 3, arg1, 1);
2878 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2879 p += gen_call (p, fn, 1, 0);
2880 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2881
2882 emit_insns (buf, p - buf);
2883 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2884}
2885
2886/* FN's prototype is `void(*fn)(int,LONGEST)'.
2887 fn (arg1, TOP)
2888
2889 TOP should be preserved/restored before/after the call. */
2890
2891static void
2892ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
2893{
2894 uint32_t buf[17];
2895 uint32_t *p = buf;
2896
2897 /* Save TOP. 0(30) is next-empty. */
2898 p += GEN_STD (p, 3, 30, 0);
2899
2900 /* Setup argument. arg1 is a 16-bit value. */
2901 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
2902 p += gen_limm (p, 3, arg1, 1);
2903 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2904 p += gen_call (p, fn, 1, 1);
2905 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2906
2907 /* Restore TOP */
2908 p += GEN_LD (p, 3, 30, 0);
2909
2910 emit_insns (buf, p - buf);
2911 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2912}
2913
2914/* Likewise for ELFv2. */
2915
2916static void
2917ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
2918{
2919 uint32_t buf[14];
2920 uint32_t *p = buf;
2921
2922 /* Save TOP. 0(30) is next-empty. */
2923 p += GEN_STD (p, 3, 30, 0);
2924
2925 /* Setup argument. arg1 is a 16-bit value. */
2926 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
2927 p += gen_limm (p, 3, arg1, 1);
2928 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2929 p += gen_call (p, fn, 1, 0);
2930 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2931
2932 /* Restore TOP */
2933 p += GEN_LD (p, 3, 30, 0);
2934
2935 emit_insns (buf, p - buf);
2936 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2937}
2938
2939/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2940
2941static void
2942ppc64_emit_if_goto (int *offset_p, int *size_p)
2943{
2944 EMIT_ASM ("cmpdi 7, 3, 0 \n"
2945 "ldu 3, 8(30) \n"
2946 "1:bne 7, 1b \n");
2947
2948 if (offset_p)
2949 *offset_p = 8;
2950 if (size_p)
2951 *size_p = 14;
2952}
2953
2954/* Goto if stack[--sp] == TOP */
2955
2956static void
2957ppc64_emit_eq_goto (int *offset_p, int *size_p)
2958{
2959 EMIT_ASM ("ldu 4, 8(30) \n"
2960 "cmpd 7, 4, 3 \n"
2961 "ldu 3, 8(30) \n"
2962 "1:beq 7, 1b \n");
2963
2964 if (offset_p)
2965 *offset_p = 12;
2966 if (size_p)
2967 *size_p = 14;
2968}
2969
2970/* Goto if stack[--sp] != TOP */
2971
2972static void
2973ppc64_emit_ne_goto (int *offset_p, int *size_p)
2974{
2975 EMIT_ASM ("ldu 4, 8(30) \n"
2976 "cmpd 7, 4, 3 \n"
2977 "ldu 3, 8(30) \n"
2978 "1:bne 7, 1b \n");
2979
2980 if (offset_p)
2981 *offset_p = 12;
2982 if (size_p)
2983 *size_p = 14;
2984}
2985
2986/* Goto if stack[--sp] < TOP */
2987
2988static void
2989ppc64_emit_lt_goto (int *offset_p, int *size_p)
2990{
2991 EMIT_ASM ("ldu 4, 8(30) \n"
2992 "cmpd 7, 4, 3 \n"
2993 "ldu 3, 8(30) \n"
2994 "1:blt 7, 1b \n");
2995
2996 if (offset_p)
2997 *offset_p = 12;
2998 if (size_p)
2999 *size_p = 14;
3000}
3001
3002/* Goto if stack[--sp] <= TOP */
3003
3004static void
3005ppc64_emit_le_goto (int *offset_p, int *size_p)
3006{
3007 EMIT_ASM ("ldu 4, 8(30) \n"
3008 "cmpd 7, 4, 3 \n"
3009 "ldu 3, 8(30) \n"
3010 "1:ble 7, 1b \n");
3011
3012 if (offset_p)
3013 *offset_p = 12;
3014 if (size_p)
3015 *size_p = 14;
3016}
3017
3018/* Goto if stack[--sp] > TOP */
3019
3020static void
3021ppc64_emit_gt_goto (int *offset_p, int *size_p)
3022{
3023 EMIT_ASM ("ldu 4, 8(30) \n"
3024 "cmpd 7, 4, 3 \n"
3025 "ldu 3, 8(30) \n"
3026 "1:bgt 7, 1b \n");
3027
3028 if (offset_p)
3029 *offset_p = 12;
3030 if (size_p)
3031 *size_p = 14;
3032}
3033
3034/* Goto if stack[--sp] >= TOP */
3035
3036static void
3037ppc64_emit_ge_goto (int *offset_p, int *size_p)
3038{
3039 EMIT_ASM ("ldu 4, 8(30) \n"
3040 "cmpd 7, 4, 3 \n"
3041 "ldu 3, 8(30) \n"
3042 "1:bge 7, 1b \n");
3043
3044 if (offset_p)
3045 *offset_p = 12;
3046 if (size_p)
3047 *size_p = 14;
3048}
3049
3050/* Table of emit ops for 64-bit ELFv1. */
3051
3052static struct emit_ops ppc64v1_emit_ops_impl =
3053{
3054 ppc64v1_emit_prologue,
3055 ppc64_emit_epilogue,
3056 ppc64_emit_add,
3057 ppc64_emit_sub,
3058 ppc64_emit_mul,
3059 ppc64_emit_lsh,
3060 ppc64_emit_rsh_signed,
3061 ppc64_emit_rsh_unsigned,
3062 ppc64_emit_ext,
3063 ppc64_emit_log_not,
3064 ppc64_emit_bit_and,
3065 ppc64_emit_bit_or,
3066 ppc64_emit_bit_xor,
3067 ppc64_emit_bit_not,
3068 ppc64_emit_equal,
3069 ppc64_emit_less_signed,
3070 ppc64_emit_less_unsigned,
3071 ppc64_emit_ref,
3072 ppc64_emit_if_goto,
3073 ppc_emit_goto,
3074 ppc_write_goto_address,
3075 ppc64_emit_const,
3076 ppc64v1_emit_call,
3077 ppc64v1_emit_reg,
3078 ppc64_emit_pop,
3079 ppc64_emit_stack_flush,
3080 ppc64_emit_zero_ext,
3081 ppc64_emit_swap,
3082 ppc_emit_stack_adjust,
3083 ppc64v1_emit_int_call_1,
3084 ppc64v1_emit_void_call_2,
3085 ppc64_emit_eq_goto,
3086 ppc64_emit_ne_goto,
3087 ppc64_emit_lt_goto,
3088 ppc64_emit_le_goto,
3089 ppc64_emit_gt_goto,
3090 ppc64_emit_ge_goto
3091};
3092
3093/* Table of emit ops for 64-bit ELFv2. */
3094
3095static struct emit_ops ppc64v2_emit_ops_impl =
3096{
3097 ppc64v2_emit_prologue,
3098 ppc64_emit_epilogue,
3099 ppc64_emit_add,
3100 ppc64_emit_sub,
3101 ppc64_emit_mul,
3102 ppc64_emit_lsh,
3103 ppc64_emit_rsh_signed,
3104 ppc64_emit_rsh_unsigned,
3105 ppc64_emit_ext,
3106 ppc64_emit_log_not,
3107 ppc64_emit_bit_and,
3108 ppc64_emit_bit_or,
3109 ppc64_emit_bit_xor,
3110 ppc64_emit_bit_not,
3111 ppc64_emit_equal,
3112 ppc64_emit_less_signed,
3113 ppc64_emit_less_unsigned,
3114 ppc64_emit_ref,
3115 ppc64_emit_if_goto,
3116 ppc_emit_goto,
3117 ppc_write_goto_address,
3118 ppc64_emit_const,
3119 ppc64v2_emit_call,
3120 ppc64v2_emit_reg,
3121 ppc64_emit_pop,
3122 ppc64_emit_stack_flush,
3123 ppc64_emit_zero_ext,
3124 ppc64_emit_swap,
3125 ppc_emit_stack_adjust,
3126 ppc64v2_emit_int_call_1,
3127 ppc64v2_emit_void_call_2,
3128 ppc64_emit_eq_goto,
3129 ppc64_emit_ne_goto,
3130 ppc64_emit_lt_goto,
3131 ppc64_emit_le_goto,
3132 ppc64_emit_gt_goto,
3133 ppc64_emit_ge_goto
3134};
3135
3136#endif
3137
3138/* Implementation of linux_target_ops method "emit_ops". */
3139
3140static struct emit_ops *
3141ppc_emit_ops (void)
3142{
3143#ifdef __powerpc64__
3144 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3145
3146 if (register_size (regcache->tdesc, 0) == 8)
3147 {
3148 if (is_elfv2_inferior ())
3149 return &ppc64v2_emit_ops_impl;
3150 else
3151 return &ppc64v1_emit_ops_impl;
3152 }
3153#endif
3154 return &ppc_emit_ops_impl;
3155}
3156
a2174ba4
MK		 3157/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3158
3159static int
3160ppc_get_ipa_tdesc_idx (void)
3161{
3162 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3163 const struct target_desc *tdesc = regcache->tdesc;
3164
3165#ifdef __powerpc64__
3166 if (tdesc == tdesc_powerpc_64l)
3167 return PPC_TDESC_BASE;
3168 if (tdesc == tdesc_powerpc_altivec64l)
3169 return PPC_TDESC_ALTIVEC;
3170 if (tdesc == tdesc_powerpc_cell64l)
3171 return PPC_TDESC_CELL;
3172 if (tdesc == tdesc_powerpc_vsx64l)
3173 return PPC_TDESC_VSX;
3174 if (tdesc == tdesc_powerpc_isa205_64l)
3175 return PPC_TDESC_ISA205;
3176 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3177 return PPC_TDESC_ISA205_ALTIVEC;
3178 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3179 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3180 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3181 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3182 if (tdesc == tdesc_powerpc_isa207_vsx64l)
3183 return PPC_TDESC_ISA207_VSX;
a2174ba4
MK		 3184#endif
3185
3186 if (tdesc == tdesc_powerpc_32l)
3187 return PPC_TDESC_BASE;
3188 if (tdesc == tdesc_powerpc_altivec32l)
3189 return PPC_TDESC_ALTIVEC;
3190 if (tdesc == tdesc_powerpc_cell32l)
3191 return PPC_TDESC_CELL;
3192 if (tdesc == tdesc_powerpc_vsx32l)
3193 return PPC_TDESC_VSX;
3194 if (tdesc == tdesc_powerpc_isa205_32l)
3195 return PPC_TDESC_ISA205;
3196 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3197 return PPC_TDESC_ISA205_ALTIVEC;
3198 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3199 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3200 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3201 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3202 if (tdesc == tdesc_powerpc_isa207_vsx32l)
3203 return PPC_TDESC_ISA207_VSX;
a2174ba4
MK		 3204 if (tdesc == tdesc_powerpc_e500l)
3205 return PPC_TDESC_E500;
3206
3207 return 0;
3208}
3209
2ec06d2e 3210struct linux_target_ops the_low_target = {
6fe305f7 3211 ppc_arch_setup,
3aee8918 3212 ppc_regs_info,
2ec06d2e
DJ		 3213 ppc_cannot_fetch_register,
3214 ppc_cannot_store_register,
c14dfd32 3215 NULL, /* fetch_register */
0d62e5e8
DJ		 3216 ppc_get_pc,
3217 ppc_set_pc,
dd373349
AT		 3218 NULL, /* breakpoint_kind_from_pc */
3219 ppc_sw_breakpoint_from_kind,
0d62e5e8
DJ		 3220 NULL,
3221 0,
3222 ppc_breakpoint_at,
657f9cde
WW		 3223 ppc_supports_z_point_type,
3224 ppc_insert_point,
3225 ppc_remove_point,
5b0a002e
UW		 3226 NULL,
3227 NULL,
3228 ppc_collect_ptrace_register,
3229 ppc_supply_ptrace_register,
7d00775e
AT		 3230 NULL, /* siginfo_fixup */
3231 NULL, /* new_process */
04ec7890 3232 NULL, /* delete_process */
7d00775e 3233 NULL, /* new_thread */
466eecee 3234 NULL, /* delete_thread */
7d00775e
AT		 3235 NULL, /* new_fork */
3236 NULL, /* prepare_to_resume */
3237 NULL, /* process_qsupported */
b04fd3be 3238 ppc_supports_tracepoints,
a2174ba4
MK		 3239 ppc_get_thread_area,
3240 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3241 ppc_emit_ops,
a2174ba4 3242 ppc_get_min_fast_tracepoint_insn_len,
7d00775e
AT		 3243 NULL, /* supports_range_stepping */
3244 NULL, /* breakpoint_kind_from_current_state */
3245 ppc_supports_hardware_single_step,
a2174ba4
MK		 3246 NULL, /* get_syscall_trapinfo */
3247 ppc_get_ipa_tdesc_idx,
2ec06d2e 3248};
3aee8918
PA		 3249
3250void
3251initialize_low_arch (void)
3252{
3253 /* Initialize the Linux target descriptions. */
3254
3255 init_registers_powerpc_32l ();
3256 init_registers_powerpc_altivec32l ();
3257 init_registers_powerpc_cell32l ();
3258 init_registers_powerpc_vsx32l ();
3259 init_registers_powerpc_isa205_32l ();
3260 init_registers_powerpc_isa205_altivec32l ();
3261 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3262 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
f2cf6173 3263 init_registers_powerpc_isa207_vsx32l ();
3aee8918 3264 init_registers_powerpc_e500l ();
a2174ba4 3265#if __powerpc64__
3aee8918
PA		 3266 init_registers_powerpc_64l ();
3267 init_registers_powerpc_altivec64l ();
3268 init_registers_powerpc_cell64l ();
3269 init_registers_powerpc_vsx64l ();
3270 init_registers_powerpc_isa205_64l ();
3271 init_registers_powerpc_isa205_altivec64l ();
3272 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3273 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
f2cf6173 3274 init_registers_powerpc_isa207_vsx64l ();
a2174ba4 3275#endif
3aee8918
PA		 3276
3277 initialize_regsets_info (&ppc_regsets_info);
3278}
GDB Binutils - Deliverables
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