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Fix typo in spelling of author's name.
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-x86-low.c
CommitLineData
d0722149
DE		 1/* GNU/Linux/x86-64 specific low level interface, for the remote server
2 for GDB.
32d0add0 3 Copyright (C) 2002-2015 Free Software Foundation, Inc.
d0722149
DE		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
d41f6d8e 20#include "server.h"
d0722149 21#include <signal.h>
6a271cae 22#include <limits.h>
f4647387 23#include <inttypes.h>
d0722149
DE		 24#include "linux-low.h"
25#include "i387-fp.h"
df7e5265
GB		 26#include "x86-low.h"
27#include "x86-xstate.h"
5826e159 28#include "nat/gdb_ptrace.h"
d0722149
DE		 29
30#include "gdb_proc_service.h"
b5737fa9
PA		 31/* Don't include elf/common.h if linux/elf.h got included by
32 gdb_proc_service.h. */
33#ifndef ELFMAG0
34#include "elf/common.h"
35#endif
36
58b4daa5 37#include "agent.h"
3aee8918 38#include "tdesc.h"
c144c7a0 39#include "tracepoint.h"
f699aaba 40#include "ax.h"
7b669087 41#include "nat/linux-nat.h"
4b134ca1 42#include "nat/x86-linux.h"
8e5d4070 43#include "nat/x86-linux-dregs.h"
d0722149 44
3aee8918 45#ifdef __x86_64__
90884b2b
L		 46/* Defined in auto-generated file amd64-linux.c. */
47void init_registers_amd64_linux (void);
3aee8918
PA		 48extern const struct target_desc *tdesc_amd64_linux;
49
1570b33e
L		 50/* Defined in auto-generated file amd64-avx-linux.c. */
51void init_registers_amd64_avx_linux (void);
3aee8918
PA		 52extern const struct target_desc *tdesc_amd64_avx_linux;
53
01f9f808
MS		 54/* Defined in auto-generated file amd64-avx512-linux.c. */
55void init_registers_amd64_avx512_linux (void);
56extern const struct target_desc *tdesc_amd64_avx512_linux;
57
a196ebeb
WT		 58/* Defined in auto-generated file amd64-mpx-linux.c. */
59void init_registers_amd64_mpx_linux (void);
60extern const struct target_desc *tdesc_amd64_mpx_linux;
61
4d47af5c
L		 62/* Defined in auto-generated file x32-linux.c. */
63void init_registers_x32_linux (void);
3aee8918
PA		 64extern const struct target_desc *tdesc_x32_linux;
65
4d47af5c
L		 66/* Defined in auto-generated file x32-avx-linux.c. */
67void init_registers_x32_avx_linux (void);
3aee8918 68extern const struct target_desc *tdesc_x32_avx_linux;
a196ebeb 69
01f9f808
MS		 70/* Defined in auto-generated file x32-avx512-linux.c. */
71void init_registers_x32_avx512_linux (void);
72extern const struct target_desc *tdesc_x32_avx512_linux;
73
3aee8918
PA		 74#endif
75
76/* Defined in auto-generated file i386-linux.c. */
77void init_registers_i386_linux (void);
78extern const struct target_desc *tdesc_i386_linux;
79
80/* Defined in auto-generated file i386-mmx-linux.c. */
81void init_registers_i386_mmx_linux (void);
82extern const struct target_desc *tdesc_i386_mmx_linux;
83
84/* Defined in auto-generated file i386-avx-linux.c. */
85void init_registers_i386_avx_linux (void);
86extern const struct target_desc *tdesc_i386_avx_linux;
87
01f9f808
MS		 88/* Defined in auto-generated file i386-avx512-linux.c. */
89void init_registers_i386_avx512_linux (void);
90extern const struct target_desc *tdesc_i386_avx512_linux;
91
a196ebeb
WT		 92/* Defined in auto-generated file i386-mpx-linux.c. */
93void init_registers_i386_mpx_linux (void);
94extern const struct target_desc *tdesc_i386_mpx_linux;
95
3aee8918
PA		 96#ifdef __x86_64__
97static struct target_desc *tdesc_amd64_linux_no_xml;
98#endif
99static struct target_desc *tdesc_i386_linux_no_xml;
100
1570b33e 101
fa593d66 102static unsigned char jump_insn[] = { 0xe9, 0, 0, 0, 0 };
405f8e94 103static unsigned char small_jump_insn[] = { 0x66, 0xe9, 0, 0 };
fa593d66 104
1570b33e
L		 105/* Backward compatibility for gdb without XML support. */
106
107static const char *xmltarget_i386_linux_no_xml = "@<target>\
108<architecture>i386</architecture>\
109<osabi>GNU/Linux</osabi>\
110</target>";
f6d1620c
L		 111
112#ifdef __x86_64__
1570b33e
L		 113static const char *xmltarget_amd64_linux_no_xml = "@<target>\
114<architecture>i386:x86-64</architecture>\
115<osabi>GNU/Linux</osabi>\
116</target>";
f6d1620c 117#endif
d0722149
DE		 118
119#include <sys/reg.h>
120#include <sys/procfs.h>
5826e159 121#include "nat/gdb_ptrace.h"
1570b33e
L		 122#include <sys/uio.h>
123
d0722149
DE		 124#ifndef PTRACE_GET_THREAD_AREA
125#define PTRACE_GET_THREAD_AREA 25
126#endif
127
128/* This definition comes from prctl.h, but some kernels may not have it. */
129#ifndef PTRACE_ARCH_PRCTL
130#define PTRACE_ARCH_PRCTL 30
131#endif
132
133/* The following definitions come from prctl.h, but may be absent
134 for certain configurations. */
135#ifndef ARCH_GET_FS
136#define ARCH_SET_GS 0x1001
137#define ARCH_SET_FS 0x1002
138#define ARCH_GET_FS 0x1003
139#define ARCH_GET_GS 0x1004
140#endif
141
aa5ca48f
DE		 142/* Per-process arch-specific data we want to keep. */
143
144struct arch_process_info
145{
df7e5265 146 struct x86_debug_reg_state debug_reg_state;
aa5ca48f
DE		 147};
148
d0722149
DE		 149#ifdef __x86_64__
150
151/* Mapping between the general-purpose registers in `struct user'
152 format and GDB's register array layout.
153 Note that the transfer layout uses 64-bit regs. */
154static /*const*/ int i386_regmap[] =
155{
156 RAX * 8, RCX * 8, RDX * 8, RBX * 8,
157 RSP * 8, RBP * 8, RSI * 8, RDI * 8,
158 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
159 DS * 8, ES * 8, FS * 8, GS * 8
160};
161
162#define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
163
164/* So code below doesn't have to care, i386 or amd64. */
165#define ORIG_EAX ORIG_RAX
bc9540e8 166#define REGSIZE 8
d0722149
DE		 167
168static const int x86_64_regmap[] =
169{
170 RAX * 8, RBX * 8, RCX * 8, RDX * 8,
171 RSI * 8, RDI * 8, RBP * 8, RSP * 8,
172 R8 * 8, R9 * 8, R10 * 8, R11 * 8,
173 R12 * 8, R13 * 8, R14 * 8, R15 * 8,
174 RIP * 8, EFLAGS * 8, CS * 8, SS * 8,
175 DS * 8, ES * 8, FS * 8, GS * 8,
176 -1, -1, -1, -1, -1, -1, -1, -1,
177 -1, -1, -1, -1, -1, -1, -1, -1,
178 -1, -1, -1, -1, -1, -1, -1, -1,
a196ebeb
WT		 179 -1,
180 -1, -1, -1, -1, -1, -1, -1, -1,
181 ORIG_RAX * 8,
182 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
01f9f808
MS		 183 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
184 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
185 -1, -1, -1, -1, -1, -1, -1, -1,
186 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
187 -1, -1, -1, -1, -1, -1, -1, -1,
188 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
189 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
190 -1, -1, -1, -1, -1, -1, -1, -1,
191 -1, -1, -1, -1, -1, -1, -1, -1,
192 -1, -1, -1, -1, -1, -1, -1, -1
d0722149
DE		 193};
194
195#define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
9e0aa64f 196#define X86_64_USER_REGS (GS + 1)
d0722149
DE		 197
198#else /* ! __x86_64__ */
199
200/* Mapping between the general-purpose registers in `struct user'
201 format and GDB's register array layout. */
202static /*const*/ int i386_regmap[] =
203{
204 EAX * 4, ECX * 4, EDX * 4, EBX * 4,
205 UESP * 4, EBP * 4, ESI * 4, EDI * 4,
206 EIP * 4, EFL * 4, CS * 4, SS * 4,
207 DS * 4, ES * 4, FS * 4, GS * 4
208};
209
210#define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
211
bc9540e8
PA		 212#define REGSIZE 4
213
d0722149 214#endif
3aee8918
PA		 215
216#ifdef __x86_64__
217
218/* Returns true if the current inferior belongs to a x86-64 process,
219 per the tdesc. */
220
221static int
222is_64bit_tdesc (void)
223{
0bfdf32f 224 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3aee8918
PA		 225
226 return register_size (regcache->tdesc, 0) == 8;
227}
228
229#endif
230
d0722149
DE		 231\f
232/* Called by libthread_db. */
233
234ps_err_e
235ps_get_thread_area (const struct ps_prochandle *ph,
236 lwpid_t lwpid, int idx, void **base)
237{
238#ifdef __x86_64__
3aee8918 239 int use_64bit = is_64bit_tdesc ();
d0722149
DE		 240
241 if (use_64bit)
242 {
243 switch (idx)
244 {
245 case FS:
246 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0)
247 return PS_OK;
248 break;
249 case GS:
250 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0)
251 return PS_OK;
252 break;
253 default:
254 return PS_BADADDR;
255 }
256 return PS_ERR;
257 }
258#endif
259
260 {
261 unsigned int desc[4];
262
263 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid,
264 (void *) (intptr_t) idx, (unsigned long) &desc) < 0)
265 return PS_ERR;
266
d1ec4ce7
DE		 267 /* Ensure we properly extend the value to 64-bits for x86_64. */
268 *base = (void *) (uintptr_t) desc[1];
d0722149
DE		 269 return PS_OK;
270 }
271}
fa593d66
PA		 272
273/* Get the thread area address. This is used to recognize which
274 thread is which when tracing with the in-process agent library. We
275 don't read anything from the address, and treat it as opaque; it's
276 the address itself that we assume is unique per-thread. */
277
278static int
279x86_get_thread_area (int lwpid, CORE_ADDR *addr)
280{
281#ifdef __x86_64__
3aee8918 282 int use_64bit = is_64bit_tdesc ();
fa593d66
PA		 283
284 if (use_64bit)
285 {
286 void *base;
287 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0)
288 {
289 *addr = (CORE_ADDR) (uintptr_t) base;
290 return 0;
291 }
292
293 return -1;
294 }
295#endif
296
297 {
298 struct lwp_info *lwp = find_lwp_pid (pid_to_ptid (lwpid));
d86d4aaf
DE		 299 struct thread_info *thr = get_lwp_thread (lwp);
300 struct regcache *regcache = get_thread_regcache (thr, 1);
fa593d66
PA		 301 unsigned int desc[4];
302 ULONGEST gs = 0;
303 const int reg_thread_area = 3; /* bits to scale down register value. */
304 int idx;
305
306 collect_register_by_name (regcache, "gs", &gs);
307
308 idx = gs >> reg_thread_area;
309
310 if (ptrace (PTRACE_GET_THREAD_AREA,
d86d4aaf 311 lwpid_of (thr),
493e2a69 312 (void *) (long) idx, (unsigned long) &desc) < 0)
fa593d66
PA		 313 return -1;
314
315 *addr = desc[1];
316 return 0;
317 }
318}
319
320
d0722149
DE		 321\f
322static int
3aee8918 323x86_cannot_store_register (int regno)
d0722149 324{
3aee8918
PA		 325#ifdef __x86_64__
326 if (is_64bit_tdesc ())
327 return 0;
328#endif
329
d0722149
DE		 330 return regno >= I386_NUM_REGS;
331}
332
333static int
3aee8918 334x86_cannot_fetch_register (int regno)
d0722149 335{
3aee8918
PA		 336#ifdef __x86_64__
337 if (is_64bit_tdesc ())
338 return 0;
339#endif
340
d0722149
DE		 341 return regno >= I386_NUM_REGS;
342}
343
344static void
442ea881 345x86_fill_gregset (struct regcache *regcache, void *buf)
d0722149
DE		 346{
347 int i;
348
349#ifdef __x86_64__
3aee8918 350 if (register_size (regcache->tdesc, 0) == 8)
d0722149
DE		 351 {
352 for (i = 0; i < X86_64_NUM_REGS; i++)
353 if (x86_64_regmap[i] != -1)
442ea881 354 collect_register (regcache, i, ((char *) buf) + x86_64_regmap[i]);
d0722149
DE		 355 return;
356 }
9e0aa64f
JK		 357
358 /* 32-bit inferior registers need to be zero-extended.
359 Callers would read uninitialized memory otherwise. */
360 memset (buf, 0x00, X86_64_USER_REGS * 8);
d0722149
DE		 361#endif
362
363 for (i = 0; i < I386_NUM_REGS; i++)
442ea881 364 collect_register (regcache, i, ((char *) buf) + i386_regmap[i]);
d0722149 365
442ea881 366 collect_register_by_name (regcache, "orig_eax",
bc9540e8 367 ((char *) buf) + ORIG_EAX * REGSIZE);
d0722149
DE		 368}
369
370static void
442ea881 371x86_store_gregset (struct regcache *regcache, const void *buf)
d0722149
DE		 372{
373 int i;
374
375#ifdef __x86_64__
3aee8918 376 if (register_size (regcache->tdesc, 0) == 8)
d0722149
DE		 377 {
378 for (i = 0; i < X86_64_NUM_REGS; i++)
379 if (x86_64_regmap[i] != -1)
442ea881 380 supply_register (regcache, i, ((char *) buf) + x86_64_regmap[i]);
d0722149
DE		 381 return;
382 }
383#endif
384
385 for (i = 0; i < I386_NUM_REGS; i++)
442ea881 386 supply_register (regcache, i, ((char *) buf) + i386_regmap[i]);
d0722149 387
442ea881 388 supply_register_by_name (regcache, "orig_eax",
bc9540e8 389 ((char *) buf) + ORIG_EAX * REGSIZE);
d0722149
DE		 390}
391
392static void
442ea881 393x86_fill_fpregset (struct regcache *regcache, void *buf)
d0722149
DE		 394{
395#ifdef __x86_64__
442ea881 396 i387_cache_to_fxsave (regcache, buf);
d0722149 397#else
442ea881 398 i387_cache_to_fsave (regcache, buf);
d0722149
DE		 399#endif
400}
401
402static void
442ea881 403x86_store_fpregset (struct regcache *regcache, const void *buf)
d0722149
DE		 404{
405#ifdef __x86_64__
442ea881 406 i387_fxsave_to_cache (regcache, buf);
d0722149 407#else
442ea881 408 i387_fsave_to_cache (regcache, buf);
d0722149
DE		 409#endif
410}
411
412#ifndef __x86_64__
413
414static void
442ea881 415x86_fill_fpxregset (struct regcache *regcache, void *buf)
d0722149 416{
442ea881 417 i387_cache_to_fxsave (regcache, buf);
d0722149
DE		 418}
419
420static void
442ea881 421x86_store_fpxregset (struct regcache *regcache, const void *buf)
d0722149 422{
442ea881 423 i387_fxsave_to_cache (regcache, buf);
d0722149
DE		 424}
425
426#endif
427
1570b33e
L		 428static void
429x86_fill_xstateregset (struct regcache *regcache, void *buf)
430{
431 i387_cache_to_xsave (regcache, buf);
432}
433
434static void
435x86_store_xstateregset (struct regcache *regcache, const void *buf)
436{
437 i387_xsave_to_cache (regcache, buf);
438}
439
d0722149
DE		 440/* ??? The non-biarch i386 case stores all the i387 regs twice.
441 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
442 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
443 doesn't work. IWBN to avoid the duplication in the case where it
444 does work. Maybe the arch_setup routine could check whether it works
3aee8918 445 and update the supported regsets accordingly. */
d0722149 446
3aee8918 447static struct regset_info x86_regsets[] =
d0722149
DE		 448{
449#ifdef HAVE_PTRACE_GETREGS
1570b33e 450 { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t),
d0722149
DE		 451 GENERAL_REGS,
452 x86_fill_gregset, x86_store_gregset },
1570b33e
L		 453 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_X86_XSTATE, 0,
454 EXTENDED_REGS, x86_fill_xstateregset, x86_store_xstateregset },
d0722149
DE		 455# ifndef __x86_64__
456# ifdef HAVE_PTRACE_GETFPXREGS
1570b33e 457 { PTRACE_GETFPXREGS, PTRACE_SETFPXREGS, 0, sizeof (elf_fpxregset_t),
d0722149
DE		 458 EXTENDED_REGS,
459 x86_fill_fpxregset, x86_store_fpxregset },
460# endif
461# endif
1570b33e 462 { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, sizeof (elf_fpregset_t),
d0722149
DE		 463 FP_REGS,
464 x86_fill_fpregset, x86_store_fpregset },
465#endif /* HAVE_PTRACE_GETREGS */
1570b33e 466 { 0, 0, 0, -1, -1, NULL, NULL }
d0722149
DE		 467};
468
469static CORE_ADDR
442ea881 470x86_get_pc (struct regcache *regcache)
d0722149 471{
3aee8918 472 int use_64bit = register_size (regcache->tdesc, 0) == 8;
d0722149
DE		 473
474 if (use_64bit)
475 {
476 unsigned long pc;
442ea881 477 collect_register_by_name (regcache, "rip", &pc);
d0722149
DE		 478 return (CORE_ADDR) pc;
479 }
480 else
481 {
482 unsigned int pc;
442ea881 483 collect_register_by_name (regcache, "eip", &pc);
d0722149
DE		 484 return (CORE_ADDR) pc;
485 }
486}
487
488static void
442ea881 489x86_set_pc (struct regcache *regcache, CORE_ADDR pc)
d0722149 490{
3aee8918 491 int use_64bit = register_size (regcache->tdesc, 0) == 8;
d0722149
DE		 492
493 if (use_64bit)
494 {
495 unsigned long newpc = pc;
442ea881 496 supply_register_by_name (regcache, "rip", &newpc);
d0722149
DE		 497 }
498 else
499 {
500 unsigned int newpc = pc;
442ea881 501 supply_register_by_name (regcache, "eip", &newpc);
d0722149
DE		 502 }
503}
504\f
505static const unsigned char x86_breakpoint[] = { 0xCC };
506#define x86_breakpoint_len 1
507
508static int
509x86_breakpoint_at (CORE_ADDR pc)
510{
511 unsigned char c;
512
fc7238bb 513 (*the_target->read_memory) (pc, &c, 1);
d0722149
DE		 514 if (c == 0xCC)
515 return 1;
516
517 return 0;
518}
519\f
42995dbd 520/* Low-level function vector. */
df7e5265 521struct x86_dr_low_type x86_dr_low =
42995dbd 522 {
d33472ad
GB		 523 x86_linux_dr_set_control,
524 x86_linux_dr_set_addr,
525 x86_linux_dr_get_addr,
526 x86_linux_dr_get_status,
527 x86_linux_dr_get_control,
42995dbd
GB		 528 sizeof (void *),
529 };
aa5ca48f 530\f
90d74c30 531/* Breakpoint/Watchpoint support. */
aa5ca48f
DE		 532
533static int
802e8e6d
PA		 534x86_supports_z_point_type (char z_type)
535{
536 switch (z_type)
537 {
538 case Z_PACKET_SW_BP:
539 case Z_PACKET_HW_BP:
540 case Z_PACKET_WRITE_WP:
541 case Z_PACKET_ACCESS_WP:
542 return 1;
543 default:
544 return 0;
545 }
546}
547
548static int
549x86_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
550 int size, struct raw_breakpoint *bp)
aa5ca48f
DE		 551{
552 struct process_info *proc = current_process ();
802e8e6d 553
aa5ca48f
DE		 554 switch (type)
555 {
802e8e6d
PA		 556 case raw_bkpt_type_hw:
557 case raw_bkpt_type_write_wp:
558 case raw_bkpt_type_access_wp:
a4165e94 559 {
802e8e6d
PA		 560 enum target_hw_bp_type hw_type
561 = raw_bkpt_type_to_target_hw_bp_type (type);
df7e5265 562 struct x86_debug_reg_state *state
fe978cb0 563 = &proc->priv->arch_private->debug_reg_state;
a4165e94 564
df7e5265 565 return x86_dr_insert_watchpoint (state, hw_type, addr, size);
a4165e94 566 }
961bd387 567
aa5ca48f
DE		 568 default:
569 /* Unsupported. */
570 return 1;
571 }
572}
573
574static int
802e8e6d
PA		 575x86_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
576 int size, struct raw_breakpoint *bp)
aa5ca48f
DE		 577{
578 struct process_info *proc = current_process ();
802e8e6d 579
aa5ca48f
DE		 580 switch (type)
581 {
802e8e6d
PA		 582 case raw_bkpt_type_hw:
583 case raw_bkpt_type_write_wp:
584 case raw_bkpt_type_access_wp:
a4165e94 585 {
802e8e6d
PA		 586 enum target_hw_bp_type hw_type
587 = raw_bkpt_type_to_target_hw_bp_type (type);
df7e5265 588 struct x86_debug_reg_state *state
fe978cb0 589 = &proc->priv->arch_private->debug_reg_state;
a4165e94 590
df7e5265 591 return x86_dr_remove_watchpoint (state, hw_type, addr, size);
a4165e94 592 }
aa5ca48f
DE		 593 default:
594 /* Unsupported. */
595 return 1;
596 }
597}
598
599static int
600x86_stopped_by_watchpoint (void)
601{
602 struct process_info *proc = current_process ();
fe978cb0 603 return x86_dr_stopped_by_watchpoint (&proc->priv->arch_private->debug_reg_state);
aa5ca48f
DE		 604}
605
606static CORE_ADDR
607x86_stopped_data_address (void)
608{
609 struct process_info *proc = current_process ();
610 CORE_ADDR addr;
fe978cb0 611 if (x86_dr_stopped_data_address (&proc->priv->arch_private->debug_reg_state,
df7e5265 612 &addr))
aa5ca48f
DE		 613 return addr;
614 return 0;
615}
616\f
617/* Called when a new process is created. */
618
619static struct arch_process_info *
620x86_linux_new_process (void)
621{
ed859da7 622 struct arch_process_info *info = XCNEW (struct arch_process_info);
aa5ca48f 623
df7e5265 624 x86_low_init_dregs (&info->debug_reg_state);
aa5ca48f
DE		 625
626 return info;
627}
628
3a8a0396
DB		 629/* Target routine for linux_new_fork. */
630
631static void
632x86_linux_new_fork (struct process_info *parent, struct process_info *child)
633{
634 /* These are allocated by linux_add_process. */
635 gdb_assert (parent->priv != NULL
636 && parent->priv->arch_private != NULL);
637 gdb_assert (child->priv != NULL
638 && child->priv->arch_private != NULL);
639
640 /* Linux kernel before 2.6.33 commit
641 72f674d203cd230426437cdcf7dd6f681dad8b0d
642 will inherit hardware debug registers from parent
643 on fork/vfork/clone. Newer Linux kernels create such tasks with
644 zeroed debug registers.
645
646 GDB core assumes the child inherits the watchpoints/hw
647 breakpoints of the parent, and will remove them all from the
648 forked off process. Copy the debug registers mirrors into the
649 new process so that all breakpoints and watchpoints can be
650 removed together. The debug registers mirror will become zeroed
651 in the end before detaching the forked off process, thus making
652 this compatible with older Linux kernels too. */
653
654 *child->priv->arch_private = *parent->priv->arch_private;
655}
656
70a0bb6b
GB		 657/* See nat/x86-dregs.h. */
658
659struct x86_debug_reg_state *
660x86_debug_reg_state (pid_t pid)
661{
662 struct process_info *proc = find_process_pid (pid);
663
664 return &proc->priv->arch_private->debug_reg_state;
665}
aa5ca48f 666\f
d0722149
DE		 667/* When GDBSERVER is built as a 64-bit application on linux, the
668 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
669 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
670 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
671 conversion in-place ourselves. */
672
673/* These types below (compat_*) define a siginfo type that is layout
674 compatible with the siginfo type exported by the 32-bit userspace
675 support. */
676
677#ifdef __x86_64__
678
679typedef int compat_int_t;
680typedef unsigned int compat_uptr_t;
681
682typedef int compat_time_t;
683typedef int compat_timer_t;
684typedef int compat_clock_t;
685
686struct compat_timeval
687{
688 compat_time_t tv_sec;
689 int tv_usec;
690};
691
692typedef union compat_sigval
693{
694 compat_int_t sival_int;
695 compat_uptr_t sival_ptr;
696} compat_sigval_t;
697
698typedef struct compat_siginfo
699{
700 int si_signo;
701 int si_errno;
702 int si_code;
703
704 union
705 {
706 int _pad[((128 / sizeof (int)) - 3)];
707
708 /* kill() */
709 struct
710 {
711 unsigned int _pid;
712 unsigned int _uid;
713 } _kill;
714
715 /* POSIX.1b timers */
716 struct
717 {
718 compat_timer_t _tid;
719 int _overrun;
720 compat_sigval_t _sigval;
721 } _timer;
722
723 /* POSIX.1b signals */
724 struct
725 {
726 unsigned int _pid;
727 unsigned int _uid;
728 compat_sigval_t _sigval;
729 } _rt;
730
731 /* SIGCHLD */
732 struct
733 {
734 unsigned int _pid;
735 unsigned int _uid;
736 int _status;
737 compat_clock_t _utime;
738 compat_clock_t _stime;
739 } _sigchld;
740
741 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
742 struct
743 {
744 unsigned int _addr;
745 } _sigfault;
746
747 /* SIGPOLL */
748 struct
749 {
750 int _band;
751 int _fd;
752 } _sigpoll;
753 } _sifields;
754} compat_siginfo_t;
755
c92b5177
L		 756/* For x32, clock_t in _sigchld is 64bit aligned at 4 bytes. */
757typedef long __attribute__ ((__aligned__ (4))) compat_x32_clock_t;
758
759typedef struct compat_x32_siginfo
760{
761 int si_signo;
762 int si_errno;
763 int si_code;
764
765 union
766 {
767 int _pad[((128 / sizeof (int)) - 3)];
768
769 /* kill() */
770 struct
771 {
772 unsigned int _pid;
773 unsigned int _uid;
774 } _kill;
775
776 /* POSIX.1b timers */
777 struct
778 {
779 compat_timer_t _tid;
780 int _overrun;
781 compat_sigval_t _sigval;
782 } _timer;
783
784 /* POSIX.1b signals */
785 struct
786 {
787 unsigned int _pid;
788 unsigned int _uid;
789 compat_sigval_t _sigval;
790 } _rt;
791
792 /* SIGCHLD */
793 struct
794 {
795 unsigned int _pid;
796 unsigned int _uid;
797 int _status;
798 compat_x32_clock_t _utime;
799 compat_x32_clock_t _stime;
800 } _sigchld;
801
802 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
803 struct
804 {
805 unsigned int _addr;
806 } _sigfault;
807
808 /* SIGPOLL */
809 struct
810 {
811 int _band;
812 int _fd;
813 } _sigpoll;
814 } _sifields;
815} compat_x32_siginfo_t __attribute__ ((__aligned__ (8)));
816
d0722149
DE		 817#define cpt_si_pid _sifields._kill._pid
818#define cpt_si_uid _sifields._kill._uid
819#define cpt_si_timerid _sifields._timer._tid
820#define cpt_si_overrun _sifields._timer._overrun
821#define cpt_si_status _sifields._sigchld._status
822#define cpt_si_utime _sifields._sigchld._utime
823#define cpt_si_stime _sifields._sigchld._stime
824#define cpt_si_ptr _sifields._rt._sigval.sival_ptr
825#define cpt_si_addr _sifields._sigfault._addr
826#define cpt_si_band _sifields._sigpoll._band
827#define cpt_si_fd _sifields._sigpoll._fd
828
829/* glibc at least up to 2.3.2 doesn't have si_timerid, si_overrun.
830 In their place is si_timer1,si_timer2. */
831#ifndef si_timerid
832#define si_timerid si_timer1
833#endif
834#ifndef si_overrun
835#define si_overrun si_timer2
836#endif
837
838static void
839compat_siginfo_from_siginfo (compat_siginfo_t *to, siginfo_t *from)
840{
841 memset (to, 0, sizeof (*to));
842
843 to->si_signo = from->si_signo;
844 to->si_errno = from->si_errno;
845 to->si_code = from->si_code;
846
b53a1623 847 if (to->si_code == SI_TIMER)
d0722149 848 {
b53a1623
PA		 849 to->cpt_si_timerid = from->si_timerid;
850 to->cpt_si_overrun = from->si_overrun;
d0722149
DE		 851 to->cpt_si_ptr = (intptr_t) from->si_ptr;
852 }
853 else if (to->si_code == SI_USER)
854 {
855 to->cpt_si_pid = from->si_pid;
856 to->cpt_si_uid = from->si_uid;
857 }
b53a1623 858 else if (to->si_code < 0)
d0722149 859 {
b53a1623
PA		 860 to->cpt_si_pid = from->si_pid;
861 to->cpt_si_uid = from->si_uid;
d0722149
DE		 862 to->cpt_si_ptr = (intptr_t) from->si_ptr;
863 }
864 else
865 {
866 switch (to->si_signo)
867 {
868 case SIGCHLD:
869 to->cpt_si_pid = from->si_pid;
870 to->cpt_si_uid = from->si_uid;
871 to->cpt_si_status = from->si_status;
872 to->cpt_si_utime = from->si_utime;
873 to->cpt_si_stime = from->si_stime;
874 break;
875 case SIGILL:
876 case SIGFPE:
877 case SIGSEGV:
878 case SIGBUS:
879 to->cpt_si_addr = (intptr_t) from->si_addr;
880 break;
881 case SIGPOLL:
882 to->cpt_si_band = from->si_band;
883 to->cpt_si_fd = from->si_fd;
884 break;
885 default:
886 to->cpt_si_pid = from->si_pid;
887 to->cpt_si_uid = from->si_uid;
888 to->cpt_si_ptr = (intptr_t) from->si_ptr;
889 break;
890 }
891 }
892}
893
894static void
895siginfo_from_compat_siginfo (siginfo_t *to, compat_siginfo_t *from)
896{
897 memset (to, 0, sizeof (*to));
898
899 to->si_signo = from->si_signo;
900 to->si_errno = from->si_errno;
901 to->si_code = from->si_code;
902
b53a1623 903 if (to->si_code == SI_TIMER)
d0722149 904 {
b53a1623
PA		 905 to->si_timerid = from->cpt_si_timerid;
906 to->si_overrun = from->cpt_si_overrun;
d0722149
DE		 907 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
908 }
909 else if (to->si_code == SI_USER)
910 {
911 to->si_pid = from->cpt_si_pid;
912 to->si_uid = from->cpt_si_uid;
913 }
b53a1623 914 else if (to->si_code < 0)
d0722149 915 {
b53a1623
PA		 916 to->si_pid = from->cpt_si_pid;
917 to->si_uid = from->cpt_si_uid;
d0722149
DE		 918 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
919 }
920 else
921 {
922 switch (to->si_signo)
923 {
924 case SIGCHLD:
925 to->si_pid = from->cpt_si_pid;
926 to->si_uid = from->cpt_si_uid;
927 to->si_status = from->cpt_si_status;
928 to->si_utime = from->cpt_si_utime;
929 to->si_stime = from->cpt_si_stime;
930 break;
931 case SIGILL:
932 case SIGFPE:
933 case SIGSEGV:
934 case SIGBUS:
935 to->si_addr = (void *) (intptr_t) from->cpt_si_addr;
936 break;
937 case SIGPOLL:
938 to->si_band = from->cpt_si_band;
939 to->si_fd = from->cpt_si_fd;
940 break;
941 default:
942 to->si_pid = from->cpt_si_pid;
943 to->si_uid = from->cpt_si_uid;
944 to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr;
945 break;
946 }
947 }
948}
949
c92b5177
L		 950static void
951compat_x32_siginfo_from_siginfo (compat_x32_siginfo_t *to,
952 siginfo_t *from)
953{
954 memset (to, 0, sizeof (*to));
955
956 to->si_signo = from->si_signo;
957 to->si_errno = from->si_errno;
958 to->si_code = from->si_code;
959
960 if (to->si_code == SI_TIMER)
961 {
962 to->cpt_si_timerid = from->si_timerid;
963 to->cpt_si_overrun = from->si_overrun;
964 to->cpt_si_ptr = (intptr_t) from->si_ptr;
965 }
966 else if (to->si_code == SI_USER)
967 {
968 to->cpt_si_pid = from->si_pid;
969 to->cpt_si_uid = from->si_uid;
970 }
971 else if (to->si_code < 0)
972 {
973 to->cpt_si_pid = from->si_pid;
974 to->cpt_si_uid = from->si_uid;
975 to->cpt_si_ptr = (intptr_t) from->si_ptr;
976 }
977 else
978 {
979 switch (to->si_signo)
980 {
981 case SIGCHLD:
982 to->cpt_si_pid = from->si_pid;
983 to->cpt_si_uid = from->si_uid;
984 to->cpt_si_status = from->si_status;
985 to->cpt_si_utime = from->si_utime;
986 to->cpt_si_stime = from->si_stime;
987 break;
988 case SIGILL:
989 case SIGFPE:
990 case SIGSEGV:
991 case SIGBUS:
992 to->cpt_si_addr = (intptr_t) from->si_addr;
993 break;
994 case SIGPOLL:
995 to->cpt_si_band = from->si_band;
996 to->cpt_si_fd = from->si_fd;
997 break;
998 default:
999 to->cpt_si_pid = from->si_pid;
1000 to->cpt_si_uid = from->si_uid;
1001 to->cpt_si_ptr = (intptr_t) from->si_ptr;
1002 break;
1003 }
1004 }
1005}
1006
1007static void
1008siginfo_from_compat_x32_siginfo (siginfo_t *to,
1009 compat_x32_siginfo_t *from)
1010{
1011 memset (to, 0, sizeof (*to));
1012
1013 to->si_signo = from->si_signo;
1014 to->si_errno = from->si_errno;
1015 to->si_code = from->si_code;
1016
1017 if (to->si_code == SI_TIMER)
1018 {
1019 to->si_timerid = from->cpt_si_timerid;
1020 to->si_overrun = from->cpt_si_overrun;
1021 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1022 }
1023 else if (to->si_code == SI_USER)
1024 {
1025 to->si_pid = from->cpt_si_pid;
1026 to->si_uid = from->cpt_si_uid;
1027 }
1028 else if (to->si_code < 0)
1029 {
1030 to->si_pid = from->cpt_si_pid;
1031 to->si_uid = from->cpt_si_uid;
1032 to->si_ptr = (void *) (intptr_t) from->cpt_si_ptr;
1033 }
1034 else
1035 {
1036 switch (to->si_signo)
1037 {
1038 case SIGCHLD:
1039 to->si_pid = from->cpt_si_pid;
1040 to->si_uid = from->cpt_si_uid;
1041 to->si_status = from->cpt_si_status;
1042 to->si_utime = from->cpt_si_utime;
1043 to->si_stime = from->cpt_si_stime;
1044 break;
1045 case SIGILL:
1046 case SIGFPE:
1047 case SIGSEGV:
1048 case SIGBUS:
1049 to->si_addr = (void *) (intptr_t) from->cpt_si_addr;
1050 break;
1051 case SIGPOLL:
1052 to->si_band = from->cpt_si_band;
1053 to->si_fd = from->cpt_si_fd;
1054 break;
1055 default:
1056 to->si_pid = from->cpt_si_pid;
1057 to->si_uid = from->cpt_si_uid;
1058 to->si_ptr = (void* ) (intptr_t) from->cpt_si_ptr;
1059 break;
1060 }
1061 }
1062}
1063
d0722149
DE		 1064#endif /* __x86_64__ */
1065
1066/* Convert a native/host siginfo object, into/from the siginfo in the
1067 layout of the inferiors' architecture. Returns true if any
1068 conversion was done; false otherwise. If DIRECTION is 1, then copy
1069 from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to
1070 INF. */
1071
1072static int
a5362b9a 1073x86_siginfo_fixup (siginfo_t *native, void *inf, int direction)
d0722149
DE		 1074{
1075#ifdef __x86_64__
760256f9 1076 unsigned int machine;
0bfdf32f 1077 int tid = lwpid_of (current_thread);
760256f9
PA		 1078 int is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
1079
d0722149 1080 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
3aee8918 1081 if (!is_64bit_tdesc ())
d0722149 1082 {
38e08fca 1083 gdb_assert (sizeof (siginfo_t) == sizeof (compat_siginfo_t));
d0722149
DE		 1084
1085 if (direction == 0)
1086 compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, native);
1087 else
1088 siginfo_from_compat_siginfo (native, (struct compat_siginfo *) inf);
1089
c92b5177
L		 1090 return 1;
1091 }
1092 /* No fixup for native x32 GDB. */
760256f9 1093 else if (!is_elf64 && sizeof (void *) == 8)
c92b5177 1094 {
38e08fca 1095 gdb_assert (sizeof (siginfo_t) == sizeof (compat_x32_siginfo_t));
c92b5177
L		 1096
1097 if (direction == 0)
1098 compat_x32_siginfo_from_siginfo ((struct compat_x32_siginfo *) inf,
1099 native);
1100 else
1101 siginfo_from_compat_x32_siginfo (native,
1102 (struct compat_x32_siginfo *) inf);
1103
d0722149
DE		 1104 return 1;
1105 }
1106#endif
1107
1108 return 0;
1109}
1110\f
1570b33e
L		 1111static int use_xml;
1112
3aee8918
PA		 1113/* Format of XSAVE extended state is:
1114 struct
1115 {
1116 fxsave_bytes[0..463]
1117 sw_usable_bytes[464..511]
1118 xstate_hdr_bytes[512..575]
1119 avx_bytes[576..831]
1120 future_state etc
1121 };
1122
1123 Same memory layout will be used for the coredump NT_X86_XSTATE
1124 representing the XSAVE extended state registers.
1125
1126 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
1127 extended state mask, which is the same as the extended control register
1128 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
1129 together with the mask saved in the xstate_hdr_bytes to determine what
1130 states the processor/OS supports and what state, used or initialized,
1131 the process/thread is in. */
1132#define I386_LINUX_XSAVE_XCR0_OFFSET 464
1133
1134/* Does the current host support the GETFPXREGS request? The header
1135 file may or may not define it, and even if it is defined, the
1136 kernel will return EIO if it's running on a pre-SSE processor. */
1137int have_ptrace_getfpxregs =
1138#ifdef HAVE_PTRACE_GETFPXREGS
1139 -1
1140#else
1141 0
1142#endif
1143;
1570b33e 1144
3aee8918
PA		 1145/* Get Linux/x86 target description from running target. */
1146
1147static const struct target_desc *
1148x86_linux_read_description (void)
1570b33e 1149{
3aee8918
PA		 1150 unsigned int machine;
1151 int is_elf64;
a196ebeb 1152 int xcr0_features;
3aee8918
PA		 1153 int tid;
1154 static uint64_t xcr0;
3a13a53b 1155 struct regset_info *regset;
1570b33e 1156
0bfdf32f 1157 tid = lwpid_of (current_thread);
1570b33e 1158
3aee8918 1159 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
45ba0d02 1160
3aee8918 1161 if (sizeof (void *) == 4)
3a13a53b 1162 {
3aee8918
PA		 1163 if (is_elf64 > 0)
1164 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
1165#ifndef __x86_64__
1166 else if (machine == EM_X86_64)
1167 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
1168#endif
1169 }
3a13a53b 1170
3aee8918
PA		 1171#if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
1172 if (machine == EM_386 && have_ptrace_getfpxregs == -1)
1173 {
1174 elf_fpxregset_t fpxregs;
3a13a53b 1175
3aee8918 1176 if (ptrace (PTRACE_GETFPXREGS, tid, 0, (long) &fpxregs) < 0)
3a13a53b 1177 {
3aee8918
PA		 1178 have_ptrace_getfpxregs = 0;
1179 have_ptrace_getregset = 0;
1180 return tdesc_i386_mmx_linux;
3a13a53b 1181 }
3aee8918
PA		 1182 else
1183 have_ptrace_getfpxregs = 1;
3a13a53b 1184 }
1570b33e
L		 1185#endif
1186
1187 if (!use_xml)
1188 {
df7e5265 1189 x86_xcr0 = X86_XSTATE_SSE_MASK;
3aee8918 1190
1570b33e
L		 1191 /* Don't use XML. */
1192#ifdef __x86_64__
3aee8918
PA		 1193 if (machine == EM_X86_64)
1194 return tdesc_amd64_linux_no_xml;
1570b33e 1195 else
1570b33e 1196#endif
3aee8918 1197 return tdesc_i386_linux_no_xml;
1570b33e
L		 1198 }
1199
1570b33e
L		 1200 if (have_ptrace_getregset == -1)
1201 {
df7e5265 1202 uint64_t xstateregs[(X86_XSTATE_SSE_SIZE / sizeof (uint64_t))];
1570b33e 1203 struct iovec iov;
1570b33e
L		 1204
1205 iov.iov_base = xstateregs;
1206 iov.iov_len = sizeof (xstateregs);
1207
1208 /* Check if PTRACE_GETREGSET works. */
3aee8918
PA		 1209 if (ptrace (PTRACE_GETREGSET, tid,
1210 (unsigned int) NT_X86_XSTATE, (long) &iov) < 0)
1211 have_ptrace_getregset = 0;
1212 else
1570b33e 1213 {
3aee8918
PA		 1214 have_ptrace_getregset = 1;
1215
1216 /* Get XCR0 from XSAVE extended state. */
1217 xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET
1218 / sizeof (uint64_t))];
1219
1220 /* Use PTRACE_GETREGSET if it is available. */
1221 for (regset = x86_regsets;
1222 regset->fill_function != NULL; regset++)
1223 if (regset->get_request == PTRACE_GETREGSET)
df7e5265 1224 regset->size = X86_XSTATE_SIZE (xcr0);
3aee8918
PA		 1225 else if (regset->type != GENERAL_REGS)
1226 regset->size = 0;
1570b33e 1227 }
1570b33e
L		 1228 }
1229
3aee8918 1230 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
a196ebeb 1231 xcr0_features = (have_ptrace_getregset
df7e5265 1232 && (xcr0 & X86_XSTATE_ALL_MASK));
3aee8918 1233
a196ebeb 1234 if (xcr0_features)
3aee8918 1235 x86_xcr0 = xcr0;
1570b33e 1236
3aee8918
PA		 1237 if (machine == EM_X86_64)
1238 {
1570b33e 1239#ifdef __x86_64__
a196ebeb 1240 if (is_elf64)
3aee8918 1241 {
a196ebeb
WT		 1242 if (xcr0_features)
1243 {
df7e5265 1244 switch (xcr0 & X86_XSTATE_ALL_MASK)
a196ebeb 1245 {
df7e5265 1246 case X86_XSTATE_AVX512_MASK:
01f9f808
MS		 1247 return tdesc_amd64_avx512_linux;
1248
df7e5265 1249 case X86_XSTATE_MPX_MASK:
a196ebeb
WT		 1250 return tdesc_amd64_mpx_linux;
1251
df7e5265 1252 case X86_XSTATE_AVX_MASK:
a196ebeb
WT		 1253 return tdesc_amd64_avx_linux;
1254
1255 default:
1256 return tdesc_amd64_linux;
1257 }
1258 }
4d47af5c 1259 else
a196ebeb 1260 return tdesc_amd64_linux;
3aee8918
PA		 1261 }
1262 else
1263 {
a196ebeb
WT		 1264 if (xcr0_features)
1265 {
df7e5265 1266 switch (xcr0 & X86_XSTATE_ALL_MASK)
a196ebeb 1267 {
df7e5265 1268 case X86_XSTATE_AVX512_MASK:
01f9f808
MS		 1269 return tdesc_x32_avx512_linux;
1270
df7e5265
GB		 1271 case X86_XSTATE_MPX_MASK: /* No MPX on x32. */
1272 case X86_XSTATE_AVX_MASK:
a196ebeb
WT		 1273 return tdesc_x32_avx_linux;
1274
1275 default:
1276 return tdesc_x32_linux;
1277 }
1278 }
3aee8918 1279 else
a196ebeb 1280 return tdesc_x32_linux;
1570b33e 1281 }
3aee8918 1282#endif
1570b33e 1283 }
3aee8918
PA		 1284 else
1285 {
a196ebeb
WT		 1286 if (xcr0_features)
1287 {
df7e5265 1288 switch (xcr0 & X86_XSTATE_ALL_MASK)
a196ebeb 1289 {
df7e5265 1290 case (X86_XSTATE_AVX512_MASK):
01f9f808
MS		 1291 return tdesc_i386_avx512_linux;
1292
df7e5265 1293 case (X86_XSTATE_MPX_MASK):
a196ebeb
WT		 1294 return tdesc_i386_mpx_linux;
1295
df7e5265 1296 case (X86_XSTATE_AVX_MASK):
a196ebeb
WT		 1297 return tdesc_i386_avx_linux;
1298
1299 default:
1300 return tdesc_i386_linux;
1301 }
1302 }
3aee8918
PA		 1303 else
1304 return tdesc_i386_linux;
1305 }
1306
1307 gdb_assert_not_reached ("failed to return tdesc");
1308}
1309
1310/* Callback for find_inferior. Stops iteration when a thread with a
1311 given PID is found. */
1312
1313static int
1314same_process_callback (struct inferior_list_entry *entry, void *data)
1315{
1316 int pid = *(int *) data;
1317
1318 return (ptid_get_pid (entry->id) == pid);
1319}
1320
1321/* Callback for for_each_inferior. Calls the arch_setup routine for
1322 each process. */
1323
1324static void
1325x86_arch_setup_process_callback (struct inferior_list_entry *entry)
1326{
1327 int pid = ptid_get_pid (entry->id);
1328
1329 /* Look up any thread of this processes. */
0bfdf32f 1330 current_thread
3aee8918
PA		 1331 = (struct thread_info *) find_inferior (&all_threads,
1332 same_process_callback, &pid);
1333
1334 the_low_target.arch_setup ();
1335}
1336
1337/* Update all the target description of all processes; a new GDB
1338 connected, and it may or not support xml target descriptions. */
1339
1340static void
1341x86_linux_update_xmltarget (void)
1342{
0bfdf32f 1343 struct thread_info *saved_thread = current_thread;
3aee8918
PA		 1344
1345 /* Before changing the register cache's internal layout, flush the
1346 contents of the current valid caches back to the threads, and
1347 release the current regcache objects. */
1348 regcache_release ();
1349
1350 for_each_inferior (&all_processes, x86_arch_setup_process_callback);
1351
0bfdf32f 1352 current_thread = saved_thread;
1570b33e
L		 1353}
1354
1355/* Process qSupported query, "xmlRegisters=". Update the buffer size for
1356 PTRACE_GETREGSET. */
1357
1358static void
1359x86_linux_process_qsupported (const char *query)
1360{
1361 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
1362 with "i386" in qSupported query, it supports x86 XML target
1363 descriptions. */
1364 use_xml = 0;
61012eef 1365 if (query != NULL && startswith (query, "xmlRegisters="))
1570b33e
L		 1366 {
1367 char *copy = xstrdup (query + 13);
1368 char *p;
1369
1370 for (p = strtok (copy, ","); p != NULL; p = strtok (NULL, ","))
1371 {
1372 if (strcmp (p, "i386") == 0)
1373 {
1374 use_xml = 1;
1375 break;
1376 }
1377 }
1378
1379 free (copy);
1380 }
1381
1382 x86_linux_update_xmltarget ();
1383}
1384
3aee8918 1385/* Common for x86/x86-64. */
d0722149 1386
3aee8918
PA		 1387static struct regsets_info x86_regsets_info =
1388 {
1389 x86_regsets, /* regsets */
1390 0, /* num_regsets */
1391 NULL, /* disabled_regsets */
1392 };
214d508e
L		 1393
1394#ifdef __x86_64__
3aee8918
PA		 1395static struct regs_info amd64_linux_regs_info =
1396 {
1397 NULL, /* regset_bitmap */
1398 NULL, /* usrregs_info */
1399 &x86_regsets_info
1400 };
d0722149 1401#endif
3aee8918
PA		 1402static struct usrregs_info i386_linux_usrregs_info =
1403 {
1404 I386_NUM_REGS,
1405 i386_regmap,
1406 };
d0722149 1407
3aee8918
PA		 1408static struct regs_info i386_linux_regs_info =
1409 {
1410 NULL, /* regset_bitmap */
1411 &i386_linux_usrregs_info,
1412 &x86_regsets_info
1413 };
d0722149 1414
3aee8918
PA		 1415const struct regs_info *
1416x86_linux_regs_info (void)
1417{
1418#ifdef __x86_64__
1419 if (is_64bit_tdesc ())
1420 return &amd64_linux_regs_info;
1421 else
1422#endif
1423 return &i386_linux_regs_info;
1424}
d0722149 1425
3aee8918
PA		 1426/* Initialize the target description for the architecture of the
1427 inferior. */
1570b33e 1428
3aee8918
PA		 1429static void
1430x86_arch_setup (void)
1431{
1432 current_process ()->tdesc = x86_linux_read_description ();
d0722149
DE		 1433}
1434
219f2f23
PA		 1435static int
1436x86_supports_tracepoints (void)
1437{
1438 return 1;
1439}
1440
fa593d66
PA		 1441static void
1442append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf)
1443{
1444 write_inferior_memory (*to, buf, len);
1445 *to += len;
1446}
1447
1448static int
1449push_opcode (unsigned char *buf, char *op)
1450{
1451 unsigned char *buf_org = buf;
1452
1453 while (1)
1454 {
1455 char *endptr;
1456 unsigned long ul = strtoul (op, &endptr, 16);
1457
1458 if (endptr == op)
1459 break;
1460
1461 *buf++ = ul;
1462 op = endptr;
1463 }
1464
1465 return buf - buf_org;
1466}
1467
1468#ifdef __x86_64__
1469
1470/* Build a jump pad that saves registers and calls a collection
1471 function. Writes a jump instruction to the jump pad to
1472 JJUMPAD_INSN. The caller is responsible to write it in at the
1473 tracepoint address. */
1474
1475static int
1476amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1477 CORE_ADDR collector,
1478 CORE_ADDR lockaddr,
1479 ULONGEST orig_size,
1480 CORE_ADDR *jump_entry,
405f8e94
SS		 1481 CORE_ADDR *trampoline,
1482 ULONGEST *trampoline_size,
fa593d66
PA		 1483 unsigned char *jjump_pad_insn,
1484 ULONGEST *jjump_pad_insn_size,
1485 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1486 CORE_ADDR *adjusted_insn_addr_end,
1487 char *err)
fa593d66
PA		 1488{
1489 unsigned char buf[40];
1490 int i, offset;
f4647387
YQ		 1491 int64_t loffset;
1492
fa593d66
PA		 1493 CORE_ADDR buildaddr = *jump_entry;
1494
1495 /* Build the jump pad. */
1496
1497 /* First, do tracepoint data collection. Save registers. */
1498 i = 0;
1499 /* Need to ensure stack pointer saved first. */
1500 buf[i++] = 0x54; /* push %rsp */
1501 buf[i++] = 0x55; /* push %rbp */
1502 buf[i++] = 0x57; /* push %rdi */
1503 buf[i++] = 0x56; /* push %rsi */
1504 buf[i++] = 0x52; /* push %rdx */
1505 buf[i++] = 0x51; /* push %rcx */
1506 buf[i++] = 0x53; /* push %rbx */
1507 buf[i++] = 0x50; /* push %rax */
1508 buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */
1509 buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */
1510 buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */
1511 buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */
1512 buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */
1513 buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */
1514 buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */
1515 buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */
1516 buf[i++] = 0x9c; /* pushfq */
1517 buf[i++] = 0x48; /* movl <addr>,%rdi */
1518 buf[i++] = 0xbf;
1519 *((unsigned long *)(buf + i)) = (unsigned long) tpaddr;
1520 i += sizeof (unsigned long);
1521 buf[i++] = 0x57; /* push %rdi */
1522 append_insns (&buildaddr, i, buf);
1523
1524 /* Stack space for the collecting_t object. */
1525 i = 0;
1526 i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */
1527 i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */
1528 memcpy (buf + i, &tpoint, 8);
1529 i += 8;
1530 i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */
1531 i += push_opcode (&buf[i],
1532 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1533 i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1534 append_insns (&buildaddr, i, buf);
1535
1536 /* spin-lock. */
1537 i = 0;
1538 i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */
1539 memcpy (&buf[i], (void *) &lockaddr, 8);
1540 i += 8;
1541 i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */
1542 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1543 i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1544 i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */
1545 i += push_opcode (&buf[i], "75 f4"); /* jne <again> */
1546 append_insns (&buildaddr, i, buf);
1547
1548 /* Set up the gdb_collect call. */
1549 /* At this point, (stack pointer + 0x18) is the base of our saved
1550 register block. */
1551
1552 i = 0;
1553 i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */
1554 i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */
1555
1556 /* tpoint address may be 64-bit wide. */
1557 i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */
1558 memcpy (buf + i, &tpoint, 8);
1559 i += 8;
1560 append_insns (&buildaddr, i, buf);
1561
1562 /* The collector function being in the shared library, may be
1563 >31-bits away off the jump pad. */
1564 i = 0;
1565 i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */
1566 memcpy (buf + i, &collector, 8);
1567 i += 8;
1568 i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */
1569 append_insns (&buildaddr, i, buf);
1570
1571 /* Clear the spin-lock. */
1572 i = 0;
1573 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1574 i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */
1575 memcpy (buf + i, &lockaddr, 8);
1576 i += 8;
1577 append_insns (&buildaddr, i, buf);
1578
1579 /* Remove stack that had been used for the collect_t object. */
1580 i = 0;
1581 i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */
1582 append_insns (&buildaddr, i, buf);
1583
1584 /* Restore register state. */
1585 i = 0;
1586 buf[i++] = 0x48; /* add $0x8,%rsp */
1587 buf[i++] = 0x83;
1588 buf[i++] = 0xc4;
1589 buf[i++] = 0x08;
1590 buf[i++] = 0x9d; /* popfq */
1591 buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */
1592 buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */
1593 buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */
1594 buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */
1595 buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */
1596 buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */
1597 buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */
1598 buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */
1599 buf[i++] = 0x58; /* pop %rax */
1600 buf[i++] = 0x5b; /* pop %rbx */
1601 buf[i++] = 0x59; /* pop %rcx */
1602 buf[i++] = 0x5a; /* pop %rdx */
1603 buf[i++] = 0x5e; /* pop %rsi */
1604 buf[i++] = 0x5f; /* pop %rdi */
1605 buf[i++] = 0x5d; /* pop %rbp */
1606 buf[i++] = 0x5c; /* pop %rsp */
1607 append_insns (&buildaddr, i, buf);
1608
1609 /* Now, adjust the original instruction to execute in the jump
1610 pad. */
1611 *adjusted_insn_addr = buildaddr;
1612 relocate_instruction (&buildaddr, tpaddr);
1613 *adjusted_insn_addr_end = buildaddr;
1614
1615 /* Finally, write a jump back to the program. */
f4647387
YQ		 1616
1617 loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
1618 if (loffset > INT_MAX || loffset < INT_MIN)
1619 {
1620 sprintf (err,
1621 "E.Jump back from jump pad too far from tracepoint "
1622 "(offset 0x%" PRIx64 " > int32).", loffset);
1623 return 1;
1624 }
1625
1626 offset = (int) loffset;
fa593d66
PA		 1627 memcpy (buf, jump_insn, sizeof (jump_insn));
1628 memcpy (buf + 1, &offset, 4);
1629 append_insns (&buildaddr, sizeof (jump_insn), buf);
1630
1631 /* The jump pad is now built. Wire in a jump to our jump pad. This
1632 is always done last (by our caller actually), so that we can
1633 install fast tracepoints with threads running. This relies on
1634 the agent's atomic write support. */
f4647387
YQ		 1635 loffset = *jump_entry - (tpaddr + sizeof (jump_insn));
1636 if (loffset > INT_MAX || loffset < INT_MIN)
1637 {
1638 sprintf (err,
1639 "E.Jump pad too far from tracepoint "
1640 "(offset 0x%" PRIx64 " > int32).", loffset);
1641 return 1;
1642 }
1643
1644 offset = (int) loffset;
1645
fa593d66
PA		 1646 memcpy (buf, jump_insn, sizeof (jump_insn));
1647 memcpy (buf + 1, &offset, 4);
1648 memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
1649 *jjump_pad_insn_size = sizeof (jump_insn);
1650
1651 /* Return the end address of our pad. */
1652 *jump_entry = buildaddr;
1653
1654 return 0;
1655}
1656
1657#endif /* __x86_64__ */
1658
1659/* Build a jump pad that saves registers and calls a collection
1660 function. Writes a jump instruction to the jump pad to
1661 JJUMPAD_INSN. The caller is responsible to write it in at the
1662 tracepoint address. */
1663
1664static int
1665i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1666 CORE_ADDR collector,
1667 CORE_ADDR lockaddr,
1668 ULONGEST orig_size,
1669 CORE_ADDR *jump_entry,
405f8e94
SS		 1670 CORE_ADDR *trampoline,
1671 ULONGEST *trampoline_size,
fa593d66
PA		 1672 unsigned char *jjump_pad_insn,
1673 ULONGEST *jjump_pad_insn_size,
1674 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1675 CORE_ADDR *adjusted_insn_addr_end,
1676 char *err)
fa593d66
PA		 1677{
1678 unsigned char buf[0x100];
1679 int i, offset;
1680 CORE_ADDR buildaddr = *jump_entry;
1681
1682 /* Build the jump pad. */
1683
1684 /* First, do tracepoint data collection. Save registers. */
1685 i = 0;
1686 buf[i++] = 0x60; /* pushad */
1687 buf[i++] = 0x68; /* push tpaddr aka $pc */
1688 *((int *)(buf + i)) = (int) tpaddr;
1689 i += 4;
1690 buf[i++] = 0x9c; /* pushf */
1691 buf[i++] = 0x1e; /* push %ds */
1692 buf[i++] = 0x06; /* push %es */
1693 buf[i++] = 0x0f; /* push %fs */
1694 buf[i++] = 0xa0;
1695 buf[i++] = 0x0f; /* push %gs */
1696 buf[i++] = 0xa8;
1697 buf[i++] = 0x16; /* push %ss */
1698 buf[i++] = 0x0e; /* push %cs */
1699 append_insns (&buildaddr, i, buf);
1700
1701 /* Stack space for the collecting_t object. */
1702 i = 0;
1703 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
1704
1705 /* Build the object. */
1706 i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */
1707 memcpy (buf + i, &tpoint, 4);
1708 i += 4;
1709 i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */
1710
1711 i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1712 i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1713 append_insns (&buildaddr, i, buf);
1714
1715 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1716 If we cared for it, this could be using xchg alternatively. */
1717
1718 i = 0;
1719 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1720 i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg
1721 %esp,<lockaddr> */
1722 memcpy (&buf[i], (void *) &lockaddr, 4);
1723 i += 4;
1724 i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */
1725 i += push_opcode (&buf[i], "75 f2"); /* jne <again> */
1726 append_insns (&buildaddr, i, buf);
1727
1728
1729 /* Set up arguments to the gdb_collect call. */
1730 i = 0;
1731 i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */
1732 i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */
1733 i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1734 append_insns (&buildaddr, i, buf);
1735
1736 i = 0;
1737 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */
1738 append_insns (&buildaddr, i, buf);
1739
1740 i = 0;
1741 i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */
1742 memcpy (&buf[i], (void *) &tpoint, 4);
1743 i += 4;
1744 append_insns (&buildaddr, i, buf);
1745
1746 buf[0] = 0xe8; /* call <reladdr> */
1747 offset = collector - (buildaddr + sizeof (jump_insn));
1748 memcpy (buf + 1, &offset, 4);
1749 append_insns (&buildaddr, 5, buf);
1750 /* Clean up after the call. */
1751 buf[0] = 0x83; /* add $0x8,%esp */
1752 buf[1] = 0xc4;
1753 buf[2] = 0x08;
1754 append_insns (&buildaddr, 3, buf);
1755
1756
1757 /* Clear the spin-lock. This would need the LOCK prefix on older
1758 broken archs. */
1759 i = 0;
1760 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */
1761 i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */
1762 memcpy (buf + i, &lockaddr, 4);
1763 i += 4;
1764 append_insns (&buildaddr, i, buf);
1765
1766
1767 /* Remove stack that had been used for the collect_t object. */
1768 i = 0;
1769 i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */
1770 append_insns (&buildaddr, i, buf);
1771
1772 i = 0;
1773 buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1774 buf[i++] = 0xc4;
1775 buf[i++] = 0x04;
1776 buf[i++] = 0x17; /* pop %ss */
1777 buf[i++] = 0x0f; /* pop %gs */
1778 buf[i++] = 0xa9;
1779 buf[i++] = 0x0f; /* pop %fs */
1780 buf[i++] = 0xa1;
1781 buf[i++] = 0x07; /* pop %es */
405f8e94 1782 buf[i++] = 0x1f; /* pop %ds */
fa593d66
PA		 1783 buf[i++] = 0x9d; /* popf */
1784 buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1785 buf[i++] = 0xc4;
1786 buf[i++] = 0x04;
1787 buf[i++] = 0x61; /* popad */
1788 append_insns (&buildaddr, i, buf);
1789
1790 /* Now, adjust the original instruction to execute in the jump
1791 pad. */
1792 *adjusted_insn_addr = buildaddr;
1793 relocate_instruction (&buildaddr, tpaddr);
1794 *adjusted_insn_addr_end = buildaddr;
1795
1796 /* Write the jump back to the program. */
1797 offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn));
1798 memcpy (buf, jump_insn, sizeof (jump_insn));
1799 memcpy (buf + 1, &offset, 4);
1800 append_insns (&buildaddr, sizeof (jump_insn), buf);
1801
1802 /* The jump pad is now built. Wire in a jump to our jump pad. This
1803 is always done last (by our caller actually), so that we can
1804 install fast tracepoints with threads running. This relies on
1805 the agent's atomic write support. */
405f8e94
SS		 1806 if (orig_size == 4)
1807 {
1808 /* Create a trampoline. */
1809 *trampoline_size = sizeof (jump_insn);
1810 if (!claim_trampoline_space (*trampoline_size, trampoline))
1811 {
1812 /* No trampoline space available. */
1813 strcpy (err,
1814 "E.Cannot allocate trampoline space needed for fast "
1815 "tracepoints on 4-byte instructions.");
1816 return 1;
1817 }
1818
1819 offset = *jump_entry - (*trampoline + sizeof (jump_insn));
1820 memcpy (buf, jump_insn, sizeof (jump_insn));
1821 memcpy (buf + 1, &offset, 4);
1822 write_inferior_memory (*trampoline, buf, sizeof (jump_insn));
1823
1824 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1825 offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff;
1826 memcpy (buf, small_jump_insn, sizeof (small_jump_insn));
1827 memcpy (buf + 2, &offset, 2);
1828 memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn));
1829 *jjump_pad_insn_size = sizeof (small_jump_insn);
1830 }
1831 else
1832 {
1833 /* Else use a 32-bit relative jump instruction. */
1834 offset = *jump_entry - (tpaddr + sizeof (jump_insn));
1835 memcpy (buf, jump_insn, sizeof (jump_insn));
1836 memcpy (buf + 1, &offset, 4);
1837 memcpy (jjump_pad_insn, buf, sizeof (jump_insn));
1838 *jjump_pad_insn_size = sizeof (jump_insn);
1839 }
fa593d66
PA		 1840
1841 /* Return the end address of our pad. */
1842 *jump_entry = buildaddr;
1843
1844 return 0;
1845}
1846
1847static int
1848x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1849 CORE_ADDR collector,
1850 CORE_ADDR lockaddr,
1851 ULONGEST orig_size,
1852 CORE_ADDR *jump_entry,
405f8e94
SS		 1853 CORE_ADDR *trampoline,
1854 ULONGEST *trampoline_size,
fa593d66
PA		 1855 unsigned char *jjump_pad_insn,
1856 ULONGEST *jjump_pad_insn_size,
1857 CORE_ADDR *adjusted_insn_addr,
405f8e94
SS		 1858 CORE_ADDR *adjusted_insn_addr_end,
1859 char *err)
fa593d66
PA		 1860{
1861#ifdef __x86_64__
3aee8918 1862 if (is_64bit_tdesc ())
fa593d66
PA		 1863 return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
1864 collector, lockaddr,
1865 orig_size, jump_entry,
405f8e94 1866 trampoline, trampoline_size,
fa593d66
PA		 1867 jjump_pad_insn,
1868 jjump_pad_insn_size,
1869 adjusted_insn_addr,
405f8e94
SS		 1870 adjusted_insn_addr_end,
1871 err);
fa593d66
PA		 1872#endif
1873
1874 return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr,
1875 collector, lockaddr,
1876 orig_size, jump_entry,
405f8e94 1877 trampoline, trampoline_size,
fa593d66
PA		 1878 jjump_pad_insn,
1879 jjump_pad_insn_size,
1880 adjusted_insn_addr,
405f8e94
SS		 1881 adjusted_insn_addr_end,
1882 err);
1883}
1884
1885/* Return the minimum instruction length for fast tracepoints on x86/x86-64
1886 architectures. */
1887
1888static int
1889x86_get_min_fast_tracepoint_insn_len (void)
1890{
1891 static int warned_about_fast_tracepoints = 0;
1892
1893#ifdef __x86_64__
1894 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1895 used for fast tracepoints. */
3aee8918 1896 if (is_64bit_tdesc ())
405f8e94
SS		 1897 return 5;
1898#endif
1899
58b4daa5 1900 if (agent_loaded_p ())
405f8e94
SS		 1901 {
1902 char errbuf[IPA_BUFSIZ];
1903
1904 errbuf[0] = '\0';
1905
1906 /* On x86, if trampolines are available, then 4-byte jump instructions
1907 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1908 with a 4-byte offset are used instead. */
1909 if (have_fast_tracepoint_trampoline_buffer (errbuf))
1910 return 4;
1911 else
1912 {
1913 /* GDB has no channel to explain to user why a shorter fast
1914 tracepoint is not possible, but at least make GDBserver
1915 mention that something has gone awry. */
1916 if (!warned_about_fast_tracepoints)
1917 {
1918 warning ("4-byte fast tracepoints not available; %s\n", errbuf);
1919 warned_about_fast_tracepoints = 1;
1920 }
1921 return 5;
1922 }
1923 }
1924 else
1925 {
1926 /* Indicate that the minimum length is currently unknown since the IPA
1927 has not loaded yet. */
1928 return 0;
1929 }
fa593d66
PA		 1930}
1931
6a271cae
PA		 1932static void
1933add_insns (unsigned char *start, int len)
1934{
1935 CORE_ADDR buildaddr = current_insn_ptr;
1936
1937 if (debug_threads)
87ce2a04
DE		 1938 debug_printf ("Adding %d bytes of insn at %s\n",
1939 len, paddress (buildaddr));
6a271cae
PA		 1940
1941 append_insns (&buildaddr, len, start);
1942 current_insn_ptr = buildaddr;
1943}
1944
6a271cae
PA		 1945/* Our general strategy for emitting code is to avoid specifying raw
1946 bytes whenever possible, and instead copy a block of inline asm
1947 that is embedded in the function. This is a little messy, because
1948 we need to keep the compiler from discarding what looks like dead
1949 code, plus suppress various warnings. */
1950
9e4344e5
PA		 1951#define EMIT_ASM(NAME, INSNS) \
1952 do \
1953 { \
1954 extern unsigned char start_ ## NAME, end_ ## NAME; \
1955 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
493e2a69 1956 __asm__ ("jmp end_" #NAME "\n" \
9e4344e5
PA		 1957 "\t" "start_" #NAME ":" \
1958 "\t" INSNS "\n" \
1959 "\t" "end_" #NAME ":"); \
1960 } while (0)
6a271cae
PA		 1961
1962#ifdef __x86_64__
1963
1964#define EMIT_ASM32(NAME,INSNS) \
9e4344e5
PA		 1965 do \
1966 { \
1967 extern unsigned char start_ ## NAME, end_ ## NAME; \
1968 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1969 __asm__ (".code32\n" \
1970 "\t" "jmp end_" #NAME "\n" \
1971 "\t" "start_" #NAME ":\n" \
1972 "\t" INSNS "\n" \
1973 "\t" "end_" #NAME ":\n" \
1974 ".code64\n"); \
1975 } while (0)
6a271cae
PA		 1976
1977#else
1978
1979#define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1980
1981#endif
1982
1983#ifdef __x86_64__
1984
1985static void
1986amd64_emit_prologue (void)
1987{
1988 EMIT_ASM (amd64_prologue,
1989 "pushq %rbp\n\t"
1990 "movq %rsp,%rbp\n\t"
1991 "sub $0x20,%rsp\n\t"
1992 "movq %rdi,-8(%rbp)\n\t"
1993 "movq %rsi,-16(%rbp)");
1994}
1995
1996
1997static void
1998amd64_emit_epilogue (void)
1999{
2000 EMIT_ASM (amd64_epilogue,
2001 "movq -16(%rbp),%rdi\n\t"
2002 "movq %rax,(%rdi)\n\t"
2003 "xor %rax,%rax\n\t"
2004 "leave\n\t"
2005 "ret");
2006}
2007
2008static void
2009amd64_emit_add (void)
2010{
2011 EMIT_ASM (amd64_add,
2012 "add (%rsp),%rax\n\t"
2013 "lea 0x8(%rsp),%rsp");
2014}
2015
2016static void
2017amd64_emit_sub (void)
2018{
2019 EMIT_ASM (amd64_sub,
2020 "sub %rax,(%rsp)\n\t"
2021 "pop %rax");
2022}
2023
2024static void
2025amd64_emit_mul (void)
2026{
2027 emit_error = 1;
2028}
2029
2030static void
2031amd64_emit_lsh (void)
2032{
2033 emit_error = 1;
2034}
2035
2036static void
2037amd64_emit_rsh_signed (void)
2038{
2039 emit_error = 1;
2040}
2041
2042static void
2043amd64_emit_rsh_unsigned (void)
2044{
2045 emit_error = 1;
2046}
2047
2048static void
2049amd64_emit_ext (int arg)
2050{
2051 switch (arg)
2052 {
2053 case 8:
2054 EMIT_ASM (amd64_ext_8,
2055 "cbtw\n\t"
2056 "cwtl\n\t"
2057 "cltq");
2058 break;
2059 case 16:
2060 EMIT_ASM (amd64_ext_16,
2061 "cwtl\n\t"
2062 "cltq");
2063 break;
2064 case 32:
2065 EMIT_ASM (amd64_ext_32,
2066 "cltq");
2067 break;
2068 default:
2069 emit_error = 1;
2070 }
2071}
2072
2073static void
2074amd64_emit_log_not (void)
2075{
2076 EMIT_ASM (amd64_log_not,
2077 "test %rax,%rax\n\t"
2078 "sete %cl\n\t"
2079 "movzbq %cl,%rax");
2080}
2081
2082static void
2083amd64_emit_bit_and (void)
2084{
2085 EMIT_ASM (amd64_and,
2086 "and (%rsp),%rax\n\t"
2087 "lea 0x8(%rsp),%rsp");
2088}
2089
2090static void
2091amd64_emit_bit_or (void)
2092{
2093 EMIT_ASM (amd64_or,
2094 "or (%rsp),%rax\n\t"
2095 "lea 0x8(%rsp),%rsp");
2096}
2097
2098static void
2099amd64_emit_bit_xor (void)
2100{
2101 EMIT_ASM (amd64_xor,
2102 "xor (%rsp),%rax\n\t"
2103 "lea 0x8(%rsp),%rsp");
2104}
2105
2106static void
2107amd64_emit_bit_not (void)
2108{
2109 EMIT_ASM (amd64_bit_not,
2110 "xorq $0xffffffffffffffff,%rax");
2111}
2112
2113static void
2114amd64_emit_equal (void)
2115{
2116 EMIT_ASM (amd64_equal,
2117 "cmp %rax,(%rsp)\n\t"
2118 "je .Lamd64_equal_true\n\t"
2119 "xor %rax,%rax\n\t"
2120 "jmp .Lamd64_equal_end\n\t"
2121 ".Lamd64_equal_true:\n\t"
2122 "mov $0x1,%rax\n\t"
2123 ".Lamd64_equal_end:\n\t"
2124 "lea 0x8(%rsp),%rsp");
2125}
2126
2127static void
2128amd64_emit_less_signed (void)
2129{
2130 EMIT_ASM (amd64_less_signed,
2131 "cmp %rax,(%rsp)\n\t"
2132 "jl .Lamd64_less_signed_true\n\t"
2133 "xor %rax,%rax\n\t"
2134 "jmp .Lamd64_less_signed_end\n\t"
2135 ".Lamd64_less_signed_true:\n\t"
2136 "mov $1,%rax\n\t"
2137 ".Lamd64_less_signed_end:\n\t"
2138 "lea 0x8(%rsp),%rsp");
2139}
2140
2141static void
2142amd64_emit_less_unsigned (void)
2143{
2144 EMIT_ASM (amd64_less_unsigned,
2145 "cmp %rax,(%rsp)\n\t"
2146 "jb .Lamd64_less_unsigned_true\n\t"
2147 "xor %rax,%rax\n\t"
2148 "jmp .Lamd64_less_unsigned_end\n\t"
2149 ".Lamd64_less_unsigned_true:\n\t"
2150 "mov $1,%rax\n\t"
2151 ".Lamd64_less_unsigned_end:\n\t"
2152 "lea 0x8(%rsp),%rsp");
2153}
2154
2155static void
2156amd64_emit_ref (int size)
2157{
2158 switch (size)
2159 {
2160 case 1:
2161 EMIT_ASM (amd64_ref1,
2162 "movb (%rax),%al");
2163 break;
2164 case 2:
2165 EMIT_ASM (amd64_ref2,
2166 "movw (%rax),%ax");
2167 break;
2168 case 4:
2169 EMIT_ASM (amd64_ref4,
2170 "movl (%rax),%eax");
2171 break;
2172 case 8:
2173 EMIT_ASM (amd64_ref8,
2174 "movq (%rax),%rax");
2175 break;
2176 }
2177}
2178
2179static void
2180amd64_emit_if_goto (int *offset_p, int *size_p)
2181{
2182 EMIT_ASM (amd64_if_goto,
2183 "mov %rax,%rcx\n\t"
2184 "pop %rax\n\t"
2185 "cmp $0,%rcx\n\t"
2186 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2187 if (offset_p)
2188 *offset_p = 10;
2189 if (size_p)
2190 *size_p = 4;
2191}
2192
2193static void
2194amd64_emit_goto (int *offset_p, int *size_p)
2195{
2196 EMIT_ASM (amd64_goto,
2197 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2198 if (offset_p)
2199 *offset_p = 1;
2200 if (size_p)
2201 *size_p = 4;
2202}
2203
2204static void
2205amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2206{
2207 int diff = (to - (from + size));
2208 unsigned char buf[sizeof (int)];
2209
2210 if (size != 4)
2211 {
2212 emit_error = 1;
2213 return;
2214 }
2215
2216 memcpy (buf, &diff, sizeof (int));
2217 write_inferior_memory (from, buf, sizeof (int));
2218}
2219
2220static void
4e29fb54 2221amd64_emit_const (LONGEST num)
6a271cae
PA		 2222{
2223 unsigned char buf[16];
2224 int i;
2225 CORE_ADDR buildaddr = current_insn_ptr;
2226
2227 i = 0;
2228 buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */
b00ad6ff 2229 memcpy (&buf[i], &num, sizeof (num));
6a271cae
PA		 2230 i += 8;
2231 append_insns (&buildaddr, i, buf);
2232 current_insn_ptr = buildaddr;
2233}
2234
2235static void
2236amd64_emit_call (CORE_ADDR fn)
2237{
2238 unsigned char buf[16];
2239 int i;
2240 CORE_ADDR buildaddr;
4e29fb54 2241 LONGEST offset64;
6a271cae
PA		 2242
2243 /* The destination function being in the shared library, may be
2244 >31-bits away off the compiled code pad. */
2245
2246 buildaddr = current_insn_ptr;
2247
2248 offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */);
2249
2250 i = 0;
2251
2252 if (offset64 > INT_MAX || offset64 < INT_MIN)
2253 {
2254 /* Offset is too large for a call. Use callq, but that requires
2255 a register, so avoid it if possible. Use r10, since it is
2256 call-clobbered, we don't have to push/pop it. */
2257 buf[i++] = 0x48; /* mov $fn,%r10 */
2258 buf[i++] = 0xba;
2259 memcpy (buf + i, &fn, 8);
2260 i += 8;
2261 buf[i++] = 0xff; /* callq *%r10 */
2262 buf[i++] = 0xd2;
2263 }
2264 else
2265 {
2266 int offset32 = offset64; /* we know we can't overflow here. */
2267 memcpy (buf + i, &offset32, 4);
2268 i += 4;
2269 }
2270
2271 append_insns (&buildaddr, i, buf);
2272 current_insn_ptr = buildaddr;
2273}
2274
2275static void
2276amd64_emit_reg (int reg)
2277{
2278 unsigned char buf[16];
2279 int i;
2280 CORE_ADDR buildaddr;
2281
2282 /* Assume raw_regs is still in %rdi. */
2283 buildaddr = current_insn_ptr;
2284 i = 0;
2285 buf[i++] = 0xbe; /* mov $<n>,%esi */
b00ad6ff 2286 memcpy (&buf[i], &reg, sizeof (reg));
6a271cae
PA		 2287 i += 4;
2288 append_insns (&buildaddr, i, buf);
2289 current_insn_ptr = buildaddr;
2290 amd64_emit_call (get_raw_reg_func_addr ());
2291}
2292
2293static void
2294amd64_emit_pop (void)
2295{
2296 EMIT_ASM (amd64_pop,
2297 "pop %rax");
2298}
2299
2300static void
2301amd64_emit_stack_flush (void)
2302{
2303 EMIT_ASM (amd64_stack_flush,
2304 "push %rax");
2305}
2306
2307static void
2308amd64_emit_zero_ext (int arg)
2309{
2310 switch (arg)
2311 {
2312 case 8:
2313 EMIT_ASM (amd64_zero_ext_8,
2314 "and $0xff,%rax");
2315 break;
2316 case 16:
2317 EMIT_ASM (amd64_zero_ext_16,
2318 "and $0xffff,%rax");
2319 break;
2320 case 32:
2321 EMIT_ASM (amd64_zero_ext_32,
2322 "mov $0xffffffff,%rcx\n\t"
2323 "and %rcx,%rax");
2324 break;
2325 default:
2326 emit_error = 1;
2327 }
2328}
2329
2330static void
2331amd64_emit_swap (void)
2332{
2333 EMIT_ASM (amd64_swap,
2334 "mov %rax,%rcx\n\t"
2335 "pop %rax\n\t"
2336 "push %rcx");
2337}
2338
2339static void
2340amd64_emit_stack_adjust (int n)
2341{
2342 unsigned char buf[16];
2343 int i;
2344 CORE_ADDR buildaddr = current_insn_ptr;
2345
2346 i = 0;
2347 buf[i++] = 0x48; /* lea $<n>(%rsp),%rsp */
2348 buf[i++] = 0x8d;
2349 buf[i++] = 0x64;
2350 buf[i++] = 0x24;
2351 /* This only handles adjustments up to 16, but we don't expect any more. */
2352 buf[i++] = n * 8;
2353 append_insns (&buildaddr, i, buf);
2354 current_insn_ptr = buildaddr;
2355}
2356
2357/* FN's prototype is `LONGEST(*fn)(int)'. */
2358
2359static void
2360amd64_emit_int_call_1 (CORE_ADDR fn, int arg1)
2361{
2362 unsigned char buf[16];
2363 int i;
2364 CORE_ADDR buildaddr;
2365
2366 buildaddr = current_insn_ptr;
2367 i = 0;
2368 buf[i++] = 0xbf; /* movl $<n>,%edi */
b00ad6ff 2369 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2370 i += 4;
2371 append_insns (&buildaddr, i, buf);
2372 current_insn_ptr = buildaddr;
2373 amd64_emit_call (fn);
2374}
2375
4e29fb54 2376/* FN's prototype is `void(*fn)(int,LONGEST)'. */
6a271cae
PA		 2377
2378static void
2379amd64_emit_void_call_2 (CORE_ADDR fn, int arg1)
2380{
2381 unsigned char buf[16];
2382 int i;
2383 CORE_ADDR buildaddr;
2384
2385 buildaddr = current_insn_ptr;
2386 i = 0;
2387 buf[i++] = 0xbf; /* movl $<n>,%edi */
b00ad6ff 2388 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2389 i += 4;
2390 append_insns (&buildaddr, i, buf);
2391 current_insn_ptr = buildaddr;
2392 EMIT_ASM (amd64_void_call_2_a,
2393 /* Save away a copy of the stack top. */
2394 "push %rax\n\t"
2395 /* Also pass top as the second argument. */
2396 "mov %rax,%rsi");
2397 amd64_emit_call (fn);
2398 EMIT_ASM (amd64_void_call_2_b,
2399 /* Restore the stack top, %rax may have been trashed. */
2400 "pop %rax");
2401}
2402
6b9801d4
SS		 2403void
2404amd64_emit_eq_goto (int *offset_p, int *size_p)
2405{
2406 EMIT_ASM (amd64_eq,
2407 "cmp %rax,(%rsp)\n\t"
2408 "jne .Lamd64_eq_fallthru\n\t"
2409 "lea 0x8(%rsp),%rsp\n\t"
2410 "pop %rax\n\t"
2411 /* jmp, but don't trust the assembler to choose the right jump */
2412 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2413 ".Lamd64_eq_fallthru:\n\t"
2414 "lea 0x8(%rsp),%rsp\n\t"
2415 "pop %rax");
2416
2417 if (offset_p)
2418 *offset_p = 13;
2419 if (size_p)
2420 *size_p = 4;
2421}
2422
2423void
2424amd64_emit_ne_goto (int *offset_p, int *size_p)
2425{
2426 EMIT_ASM (amd64_ne,
2427 "cmp %rax,(%rsp)\n\t"
2428 "je .Lamd64_ne_fallthru\n\t"
2429 "lea 0x8(%rsp),%rsp\n\t"
2430 "pop %rax\n\t"
2431 /* jmp, but don't trust the assembler to choose the right jump */
2432 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2433 ".Lamd64_ne_fallthru:\n\t"
2434 "lea 0x8(%rsp),%rsp\n\t"
2435 "pop %rax");
2436
2437 if (offset_p)
2438 *offset_p = 13;
2439 if (size_p)
2440 *size_p = 4;
2441}
2442
2443void
2444amd64_emit_lt_goto (int *offset_p, int *size_p)
2445{
2446 EMIT_ASM (amd64_lt,
2447 "cmp %rax,(%rsp)\n\t"
2448 "jnl .Lamd64_lt_fallthru\n\t"
2449 "lea 0x8(%rsp),%rsp\n\t"
2450 "pop %rax\n\t"
2451 /* jmp, but don't trust the assembler to choose the right jump */
2452 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2453 ".Lamd64_lt_fallthru:\n\t"
2454 "lea 0x8(%rsp),%rsp\n\t"
2455 "pop %rax");
2456
2457 if (offset_p)
2458 *offset_p = 13;
2459 if (size_p)
2460 *size_p = 4;
2461}
2462
2463void
2464amd64_emit_le_goto (int *offset_p, int *size_p)
2465{
2466 EMIT_ASM (amd64_le,
2467 "cmp %rax,(%rsp)\n\t"
2468 "jnle .Lamd64_le_fallthru\n\t"
2469 "lea 0x8(%rsp),%rsp\n\t"
2470 "pop %rax\n\t"
2471 /* jmp, but don't trust the assembler to choose the right jump */
2472 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2473 ".Lamd64_le_fallthru:\n\t"
2474 "lea 0x8(%rsp),%rsp\n\t"
2475 "pop %rax");
2476
2477 if (offset_p)
2478 *offset_p = 13;
2479 if (size_p)
2480 *size_p = 4;
2481}
2482
2483void
2484amd64_emit_gt_goto (int *offset_p, int *size_p)
2485{
2486 EMIT_ASM (amd64_gt,
2487 "cmp %rax,(%rsp)\n\t"
2488 "jng .Lamd64_gt_fallthru\n\t"
2489 "lea 0x8(%rsp),%rsp\n\t"
2490 "pop %rax\n\t"
2491 /* jmp, but don't trust the assembler to choose the right jump */
2492 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2493 ".Lamd64_gt_fallthru:\n\t"
2494 "lea 0x8(%rsp),%rsp\n\t"
2495 "pop %rax");
2496
2497 if (offset_p)
2498 *offset_p = 13;
2499 if (size_p)
2500 *size_p = 4;
2501}
2502
2503void
2504amd64_emit_ge_goto (int *offset_p, int *size_p)
2505{
2506 EMIT_ASM (amd64_ge,
2507 "cmp %rax,(%rsp)\n\t"
2508 "jnge .Lamd64_ge_fallthru\n\t"
2509 ".Lamd64_ge_jump:\n\t"
2510 "lea 0x8(%rsp),%rsp\n\t"
2511 "pop %rax\n\t"
2512 /* jmp, but don't trust the assembler to choose the right jump */
2513 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2514 ".Lamd64_ge_fallthru:\n\t"
2515 "lea 0x8(%rsp),%rsp\n\t"
2516 "pop %rax");
2517
2518 if (offset_p)
2519 *offset_p = 13;
2520 if (size_p)
2521 *size_p = 4;
2522}
2523
6a271cae
PA		 2524struct emit_ops amd64_emit_ops =
2525 {
2526 amd64_emit_prologue,
2527 amd64_emit_epilogue,
2528 amd64_emit_add,
2529 amd64_emit_sub,
2530 amd64_emit_mul,
2531 amd64_emit_lsh,
2532 amd64_emit_rsh_signed,
2533 amd64_emit_rsh_unsigned,
2534 amd64_emit_ext,
2535 amd64_emit_log_not,
2536 amd64_emit_bit_and,
2537 amd64_emit_bit_or,
2538 amd64_emit_bit_xor,
2539 amd64_emit_bit_not,
2540 amd64_emit_equal,
2541 amd64_emit_less_signed,
2542 amd64_emit_less_unsigned,
2543 amd64_emit_ref,
2544 amd64_emit_if_goto,
2545 amd64_emit_goto,
2546 amd64_write_goto_address,
2547 amd64_emit_const,
2548 amd64_emit_call,
2549 amd64_emit_reg,
2550 amd64_emit_pop,
2551 amd64_emit_stack_flush,
2552 amd64_emit_zero_ext,
2553 amd64_emit_swap,
2554 amd64_emit_stack_adjust,
2555 amd64_emit_int_call_1,
6b9801d4
SS		 2556 amd64_emit_void_call_2,
2557 amd64_emit_eq_goto,
2558 amd64_emit_ne_goto,
2559 amd64_emit_lt_goto,
2560 amd64_emit_le_goto,
2561 amd64_emit_gt_goto,
2562 amd64_emit_ge_goto
6a271cae
PA		 2563 };
2564
2565#endif /* __x86_64__ */
2566
2567static void
2568i386_emit_prologue (void)
2569{
2570 EMIT_ASM32 (i386_prologue,
2571 "push %ebp\n\t"
bf15cbda
SS		 2572 "mov %esp,%ebp\n\t"
2573 "push %ebx");
6a271cae
PA		 2574 /* At this point, the raw regs base address is at 8(%ebp), and the
2575 value pointer is at 12(%ebp). */
2576}
2577
2578static void
2579i386_emit_epilogue (void)
2580{
2581 EMIT_ASM32 (i386_epilogue,
2582 "mov 12(%ebp),%ecx\n\t"
2583 "mov %eax,(%ecx)\n\t"
2584 "mov %ebx,0x4(%ecx)\n\t"
2585 "xor %eax,%eax\n\t"
bf15cbda 2586 "pop %ebx\n\t"
6a271cae
PA		 2587 "pop %ebp\n\t"
2588 "ret");
2589}
2590
2591static void
2592i386_emit_add (void)
2593{
2594 EMIT_ASM32 (i386_add,
2595 "add (%esp),%eax\n\t"
2596 "adc 0x4(%esp),%ebx\n\t"
2597 "lea 0x8(%esp),%esp");
2598}
2599
2600static void
2601i386_emit_sub (void)
2602{
2603 EMIT_ASM32 (i386_sub,
2604 "subl %eax,(%esp)\n\t"
2605 "sbbl %ebx,4(%esp)\n\t"
2606 "pop %eax\n\t"
2607 "pop %ebx\n\t");
2608}
2609
2610static void
2611i386_emit_mul (void)
2612{
2613 emit_error = 1;
2614}
2615
2616static void
2617i386_emit_lsh (void)
2618{
2619 emit_error = 1;
2620}
2621
2622static void
2623i386_emit_rsh_signed (void)
2624{
2625 emit_error = 1;
2626}
2627
2628static void
2629i386_emit_rsh_unsigned (void)
2630{
2631 emit_error = 1;
2632}
2633
2634static void
2635i386_emit_ext (int arg)
2636{
2637 switch (arg)
2638 {
2639 case 8:
2640 EMIT_ASM32 (i386_ext_8,
2641 "cbtw\n\t"
2642 "cwtl\n\t"
2643 "movl %eax,%ebx\n\t"
2644 "sarl $31,%ebx");
2645 break;
2646 case 16:
2647 EMIT_ASM32 (i386_ext_16,
2648 "cwtl\n\t"
2649 "movl %eax,%ebx\n\t"
2650 "sarl $31,%ebx");
2651 break;
2652 case 32:
2653 EMIT_ASM32 (i386_ext_32,
2654 "movl %eax,%ebx\n\t"
2655 "sarl $31,%ebx");
2656 break;
2657 default:
2658 emit_error = 1;
2659 }
2660}
2661
2662static void
2663i386_emit_log_not (void)
2664{
2665 EMIT_ASM32 (i386_log_not,
2666 "or %ebx,%eax\n\t"
2667 "test %eax,%eax\n\t"
2668 "sete %cl\n\t"
2669 "xor %ebx,%ebx\n\t"
2670 "movzbl %cl,%eax");
2671}
2672
2673static void
2674i386_emit_bit_and (void)
2675{
2676 EMIT_ASM32 (i386_and,
2677 "and (%esp),%eax\n\t"
2678 "and 0x4(%esp),%ebx\n\t"
2679 "lea 0x8(%esp),%esp");
2680}
2681
2682static void
2683i386_emit_bit_or (void)
2684{
2685 EMIT_ASM32 (i386_or,
2686 "or (%esp),%eax\n\t"
2687 "or 0x4(%esp),%ebx\n\t"
2688 "lea 0x8(%esp),%esp");
2689}
2690
2691static void
2692i386_emit_bit_xor (void)
2693{
2694 EMIT_ASM32 (i386_xor,
2695 "xor (%esp),%eax\n\t"
2696 "xor 0x4(%esp),%ebx\n\t"
2697 "lea 0x8(%esp),%esp");
2698}
2699
2700static void
2701i386_emit_bit_not (void)
2702{
2703 EMIT_ASM32 (i386_bit_not,
2704 "xor $0xffffffff,%eax\n\t"
2705 "xor $0xffffffff,%ebx\n\t");
2706}
2707
2708static void
2709i386_emit_equal (void)
2710{
2711 EMIT_ASM32 (i386_equal,
2712 "cmpl %ebx,4(%esp)\n\t"
2713 "jne .Li386_equal_false\n\t"
2714 "cmpl %eax,(%esp)\n\t"
2715 "je .Li386_equal_true\n\t"
2716 ".Li386_equal_false:\n\t"
2717 "xor %eax,%eax\n\t"
2718 "jmp .Li386_equal_end\n\t"
2719 ".Li386_equal_true:\n\t"
2720 "mov $1,%eax\n\t"
2721 ".Li386_equal_end:\n\t"
2722 "xor %ebx,%ebx\n\t"
2723 "lea 0x8(%esp),%esp");
2724}
2725
2726static void
2727i386_emit_less_signed (void)
2728{
2729 EMIT_ASM32 (i386_less_signed,
2730 "cmpl %ebx,4(%esp)\n\t"
2731 "jl .Li386_less_signed_true\n\t"
2732 "jne .Li386_less_signed_false\n\t"
2733 "cmpl %eax,(%esp)\n\t"
2734 "jl .Li386_less_signed_true\n\t"
2735 ".Li386_less_signed_false:\n\t"
2736 "xor %eax,%eax\n\t"
2737 "jmp .Li386_less_signed_end\n\t"
2738 ".Li386_less_signed_true:\n\t"
2739 "mov $1,%eax\n\t"
2740 ".Li386_less_signed_end:\n\t"
2741 "xor %ebx,%ebx\n\t"
2742 "lea 0x8(%esp),%esp");
2743}
2744
2745static void
2746i386_emit_less_unsigned (void)
2747{
2748 EMIT_ASM32 (i386_less_unsigned,
2749 "cmpl %ebx,4(%esp)\n\t"
2750 "jb .Li386_less_unsigned_true\n\t"
2751 "jne .Li386_less_unsigned_false\n\t"
2752 "cmpl %eax,(%esp)\n\t"
2753 "jb .Li386_less_unsigned_true\n\t"
2754 ".Li386_less_unsigned_false:\n\t"
2755 "xor %eax,%eax\n\t"
2756 "jmp .Li386_less_unsigned_end\n\t"
2757 ".Li386_less_unsigned_true:\n\t"
2758 "mov $1,%eax\n\t"
2759 ".Li386_less_unsigned_end:\n\t"
2760 "xor %ebx,%ebx\n\t"
2761 "lea 0x8(%esp),%esp");
2762}
2763
2764static void
2765i386_emit_ref (int size)
2766{
2767 switch (size)
2768 {
2769 case 1:
2770 EMIT_ASM32 (i386_ref1,
2771 "movb (%eax),%al");
2772 break;
2773 case 2:
2774 EMIT_ASM32 (i386_ref2,
2775 "movw (%eax),%ax");
2776 break;
2777 case 4:
2778 EMIT_ASM32 (i386_ref4,
2779 "movl (%eax),%eax");
2780 break;
2781 case 8:
2782 EMIT_ASM32 (i386_ref8,
2783 "movl 4(%eax),%ebx\n\t"
2784 "movl (%eax),%eax");
2785 break;
2786 }
2787}
2788
2789static void
2790i386_emit_if_goto (int *offset_p, int *size_p)
2791{
2792 EMIT_ASM32 (i386_if_goto,
2793 "mov %eax,%ecx\n\t"
2794 "or %ebx,%ecx\n\t"
2795 "pop %eax\n\t"
2796 "pop %ebx\n\t"
2797 "cmpl $0,%ecx\n\t"
2798 /* Don't trust the assembler to choose the right jump */
2799 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2800
2801 if (offset_p)
2802 *offset_p = 11; /* be sure that this matches the sequence above */
2803 if (size_p)
2804 *size_p = 4;
2805}
2806
2807static void
2808i386_emit_goto (int *offset_p, int *size_p)
2809{
2810 EMIT_ASM32 (i386_goto,
2811 /* Don't trust the assembler to choose the right jump */
2812 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2813 if (offset_p)
2814 *offset_p = 1;
2815 if (size_p)
2816 *size_p = 4;
2817}
2818
2819static void
2820i386_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2821{
2822 int diff = (to - (from + size));
2823 unsigned char buf[sizeof (int)];
2824
2825 /* We're only doing 4-byte sizes at the moment. */
2826 if (size != 4)
2827 {
2828 emit_error = 1;
2829 return;
2830 }
2831
2832 memcpy (buf, &diff, sizeof (int));
2833 write_inferior_memory (from, buf, sizeof (int));
2834}
2835
2836static void
4e29fb54 2837i386_emit_const (LONGEST num)
6a271cae
PA		 2838{
2839 unsigned char buf[16];
b00ad6ff 2840 int i, hi, lo;
6a271cae
PA		 2841 CORE_ADDR buildaddr = current_insn_ptr;
2842
2843 i = 0;
2844 buf[i++] = 0xb8; /* mov $<n>,%eax */
b00ad6ff
NF		 2845 lo = num & 0xffffffff;
2846 memcpy (&buf[i], &lo, sizeof (lo));
6a271cae
PA		 2847 i += 4;
2848 hi = ((num >> 32) & 0xffffffff);
2849 if (hi)
2850 {
2851 buf[i++] = 0xbb; /* mov $<n>,%ebx */
b00ad6ff 2852 memcpy (&buf[i], &hi, sizeof (hi));
6a271cae
PA		 2853 i += 4;
2854 }
2855 else
2856 {
2857 buf[i++] = 0x31; buf[i++] = 0xdb; /* xor %ebx,%ebx */
2858 }
2859 append_insns (&buildaddr, i, buf);
2860 current_insn_ptr = buildaddr;
2861}
2862
2863static void
2864i386_emit_call (CORE_ADDR fn)
2865{
2866 unsigned char buf[16];
2867 int i, offset;
2868 CORE_ADDR buildaddr;
2869
2870 buildaddr = current_insn_ptr;
2871 i = 0;
2872 buf[i++] = 0xe8; /* call <reladdr> */
2873 offset = ((int) fn) - (buildaddr + 5);
2874 memcpy (buf + 1, &offset, 4);
2875 append_insns (&buildaddr, 5, buf);
2876 current_insn_ptr = buildaddr;
2877}
2878
2879static void
2880i386_emit_reg (int reg)
2881{
2882 unsigned char buf[16];
2883 int i;
2884 CORE_ADDR buildaddr;
2885
2886 EMIT_ASM32 (i386_reg_a,
2887 "sub $0x8,%esp");
2888 buildaddr = current_insn_ptr;
2889 i = 0;
2890 buf[i++] = 0xb8; /* mov $<n>,%eax */
b00ad6ff 2891 memcpy (&buf[i], &reg, sizeof (reg));
6a271cae
PA		 2892 i += 4;
2893 append_insns (&buildaddr, i, buf);
2894 current_insn_ptr = buildaddr;
2895 EMIT_ASM32 (i386_reg_b,
2896 "mov %eax,4(%esp)\n\t"
2897 "mov 8(%ebp),%eax\n\t"
2898 "mov %eax,(%esp)");
2899 i386_emit_call (get_raw_reg_func_addr ());
2900 EMIT_ASM32 (i386_reg_c,
2901 "xor %ebx,%ebx\n\t"
2902 "lea 0x8(%esp),%esp");
2903}
2904
2905static void
2906i386_emit_pop (void)
2907{
2908 EMIT_ASM32 (i386_pop,
2909 "pop %eax\n\t"
2910 "pop %ebx");
2911}
2912
2913static void
2914i386_emit_stack_flush (void)
2915{
2916 EMIT_ASM32 (i386_stack_flush,
2917 "push %ebx\n\t"
2918 "push %eax");
2919}
2920
2921static void
2922i386_emit_zero_ext (int arg)
2923{
2924 switch (arg)
2925 {
2926 case 8:
2927 EMIT_ASM32 (i386_zero_ext_8,
2928 "and $0xff,%eax\n\t"
2929 "xor %ebx,%ebx");
2930 break;
2931 case 16:
2932 EMIT_ASM32 (i386_zero_ext_16,
2933 "and $0xffff,%eax\n\t"
2934 "xor %ebx,%ebx");
2935 break;
2936 case 32:
2937 EMIT_ASM32 (i386_zero_ext_32,
2938 "xor %ebx,%ebx");
2939 break;
2940 default:
2941 emit_error = 1;
2942 }
2943}
2944
2945static void
2946i386_emit_swap (void)
2947{
2948 EMIT_ASM32 (i386_swap,
2949 "mov %eax,%ecx\n\t"
2950 "mov %ebx,%edx\n\t"
2951 "pop %eax\n\t"
2952 "pop %ebx\n\t"
2953 "push %edx\n\t"
2954 "push %ecx");
2955}
2956
2957static void
2958i386_emit_stack_adjust (int n)
2959{
2960 unsigned char buf[16];
2961 int i;
2962 CORE_ADDR buildaddr = current_insn_ptr;
2963
2964 i = 0;
2965 buf[i++] = 0x8d; /* lea $<n>(%esp),%esp */
2966 buf[i++] = 0x64;
2967 buf[i++] = 0x24;
2968 buf[i++] = n * 8;
2969 append_insns (&buildaddr, i, buf);
2970 current_insn_ptr = buildaddr;
2971}
2972
2973/* FN's prototype is `LONGEST(*fn)(int)'. */
2974
2975static void
2976i386_emit_int_call_1 (CORE_ADDR fn, int arg1)
2977{
2978 unsigned char buf[16];
2979 int i;
2980 CORE_ADDR buildaddr;
2981
2982 EMIT_ASM32 (i386_int_call_1_a,
2983 /* Reserve a bit of stack space. */
2984 "sub $0x8,%esp");
2985 /* Put the one argument on the stack. */
2986 buildaddr = current_insn_ptr;
2987 i = 0;
2988 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */
2989 buf[i++] = 0x04;
2990 buf[i++] = 0x24;
b00ad6ff 2991 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 2992 i += 4;
2993 append_insns (&buildaddr, i, buf);
2994 current_insn_ptr = buildaddr;
2995 i386_emit_call (fn);
2996 EMIT_ASM32 (i386_int_call_1_c,
2997 "mov %edx,%ebx\n\t"
2998 "lea 0x8(%esp),%esp");
2999}
3000
4e29fb54 3001/* FN's prototype is `void(*fn)(int,LONGEST)'. */
6a271cae
PA		 3002
3003static void
3004i386_emit_void_call_2 (CORE_ADDR fn, int arg1)
3005{
3006 unsigned char buf[16];
3007 int i;
3008 CORE_ADDR buildaddr;
3009
3010 EMIT_ASM32 (i386_void_call_2_a,
3011 /* Preserve %eax only; we don't have to worry about %ebx. */
3012 "push %eax\n\t"
3013 /* Reserve a bit of stack space for arguments. */
3014 "sub $0x10,%esp\n\t"
3015 /* Copy "top" to the second argument position. (Note that
3016 we can't assume function won't scribble on its
3017 arguments, so don't try to restore from this.) */
3018 "mov %eax,4(%esp)\n\t"
3019 "mov %ebx,8(%esp)");
3020 /* Put the first argument on the stack. */
3021 buildaddr = current_insn_ptr;
3022 i = 0;
3023 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */
3024 buf[i++] = 0x04;
3025 buf[i++] = 0x24;
b00ad6ff 3026 memcpy (&buf[i], &arg1, sizeof (arg1));
6a271cae
PA		 3027 i += 4;
3028 append_insns (&buildaddr, i, buf);
3029 current_insn_ptr = buildaddr;
3030 i386_emit_call (fn);
3031 EMIT_ASM32 (i386_void_call_2_b,
3032 "lea 0x10(%esp),%esp\n\t"
3033 /* Restore original stack top. */
3034 "pop %eax");
3035}
3036
6b9801d4
SS		 3037
3038void
3039i386_emit_eq_goto (int *offset_p, int *size_p)
3040{
3041 EMIT_ASM32 (eq,
3042 /* Check low half first, more likely to be decider */
3043 "cmpl %eax,(%esp)\n\t"
3044 "jne .Leq_fallthru\n\t"
3045 "cmpl %ebx,4(%esp)\n\t"
3046 "jne .Leq_fallthru\n\t"
3047 "lea 0x8(%esp),%esp\n\t"
3048 "pop %eax\n\t"
3049 "pop %ebx\n\t"
3050 /* jmp, but don't trust the assembler to choose the right jump */
3051 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3052 ".Leq_fallthru:\n\t"
3053 "lea 0x8(%esp),%esp\n\t"
3054 "pop %eax\n\t"
3055 "pop %ebx");
3056
3057 if (offset_p)
3058 *offset_p = 18;
3059 if (size_p)
3060 *size_p = 4;
3061}
3062
3063void
3064i386_emit_ne_goto (int *offset_p, int *size_p)
3065{
3066 EMIT_ASM32 (ne,
3067 /* Check low half first, more likely to be decider */
3068 "cmpl %eax,(%esp)\n\t"
3069 "jne .Lne_jump\n\t"
3070 "cmpl %ebx,4(%esp)\n\t"
3071 "je .Lne_fallthru\n\t"
3072 ".Lne_jump:\n\t"
3073 "lea 0x8(%esp),%esp\n\t"
3074 "pop %eax\n\t"
3075 "pop %ebx\n\t"
3076 /* jmp, but don't trust the assembler to choose the right jump */
3077 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3078 ".Lne_fallthru:\n\t"
3079 "lea 0x8(%esp),%esp\n\t"
3080 "pop %eax\n\t"
3081 "pop %ebx");
3082
3083 if (offset_p)
3084 *offset_p = 18;
3085 if (size_p)
3086 *size_p = 4;
3087}
3088
3089void
3090i386_emit_lt_goto (int *offset_p, int *size_p)
3091{
3092 EMIT_ASM32 (lt,
3093 "cmpl %ebx,4(%esp)\n\t"
3094 "jl .Llt_jump\n\t"
3095 "jne .Llt_fallthru\n\t"
3096 "cmpl %eax,(%esp)\n\t"
3097 "jnl .Llt_fallthru\n\t"
3098 ".Llt_jump:\n\t"
3099 "lea 0x8(%esp),%esp\n\t"
3100 "pop %eax\n\t"
3101 "pop %ebx\n\t"
3102 /* jmp, but don't trust the assembler to choose the right jump */
3103 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3104 ".Llt_fallthru:\n\t"
3105 "lea 0x8(%esp),%esp\n\t"
3106 "pop %eax\n\t"
3107 "pop %ebx");
3108
3109 if (offset_p)
3110 *offset_p = 20;
3111 if (size_p)
3112 *size_p = 4;
3113}
3114
3115void
3116i386_emit_le_goto (int *offset_p, int *size_p)
3117{
3118 EMIT_ASM32 (le,
3119 "cmpl %ebx,4(%esp)\n\t"
3120 "jle .Lle_jump\n\t"
3121 "jne .Lle_fallthru\n\t"
3122 "cmpl %eax,(%esp)\n\t"
3123 "jnle .Lle_fallthru\n\t"
3124 ".Lle_jump:\n\t"
3125 "lea 0x8(%esp),%esp\n\t"
3126 "pop %eax\n\t"
3127 "pop %ebx\n\t"
3128 /* jmp, but don't trust the assembler to choose the right jump */
3129 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3130 ".Lle_fallthru:\n\t"
3131 "lea 0x8(%esp),%esp\n\t"
3132 "pop %eax\n\t"
3133 "pop %ebx");
3134
3135 if (offset_p)
3136 *offset_p = 20;
3137 if (size_p)
3138 *size_p = 4;
3139}
3140
3141void
3142i386_emit_gt_goto (int *offset_p, int *size_p)
3143{
3144 EMIT_ASM32 (gt,
3145 "cmpl %ebx,4(%esp)\n\t"
3146 "jg .Lgt_jump\n\t"
3147 "jne .Lgt_fallthru\n\t"
3148 "cmpl %eax,(%esp)\n\t"
3149 "jng .Lgt_fallthru\n\t"
3150 ".Lgt_jump:\n\t"
3151 "lea 0x8(%esp),%esp\n\t"
3152 "pop %eax\n\t"
3153 "pop %ebx\n\t"
3154 /* jmp, but don't trust the assembler to choose the right jump */
3155 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3156 ".Lgt_fallthru:\n\t"
3157 "lea 0x8(%esp),%esp\n\t"
3158 "pop %eax\n\t"
3159 "pop %ebx");
3160
3161 if (offset_p)
3162 *offset_p = 20;
3163 if (size_p)
3164 *size_p = 4;
3165}
3166
3167void
3168i386_emit_ge_goto (int *offset_p, int *size_p)
3169{
3170 EMIT_ASM32 (ge,
3171 "cmpl %ebx,4(%esp)\n\t"
3172 "jge .Lge_jump\n\t"
3173 "jne .Lge_fallthru\n\t"
3174 "cmpl %eax,(%esp)\n\t"
3175 "jnge .Lge_fallthru\n\t"
3176 ".Lge_jump:\n\t"
3177 "lea 0x8(%esp),%esp\n\t"
3178 "pop %eax\n\t"
3179 "pop %ebx\n\t"
3180 /* jmp, but don't trust the assembler to choose the right jump */
3181 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
3182 ".Lge_fallthru:\n\t"
3183 "lea 0x8(%esp),%esp\n\t"
3184 "pop %eax\n\t"
3185 "pop %ebx");
3186
3187 if (offset_p)
3188 *offset_p = 20;
3189 if (size_p)
3190 *size_p = 4;
3191}
3192
6a271cae
PA		 3193struct emit_ops i386_emit_ops =
3194 {
3195 i386_emit_prologue,
3196 i386_emit_epilogue,
3197 i386_emit_add,
3198 i386_emit_sub,
3199 i386_emit_mul,
3200 i386_emit_lsh,
3201 i386_emit_rsh_signed,
3202 i386_emit_rsh_unsigned,
3203 i386_emit_ext,
3204 i386_emit_log_not,
3205 i386_emit_bit_and,
3206 i386_emit_bit_or,
3207 i386_emit_bit_xor,
3208 i386_emit_bit_not,
3209 i386_emit_equal,
3210 i386_emit_less_signed,
3211 i386_emit_less_unsigned,
3212 i386_emit_ref,
3213 i386_emit_if_goto,
3214 i386_emit_goto,
3215 i386_write_goto_address,
3216 i386_emit_const,
3217 i386_emit_call,
3218 i386_emit_reg,
3219 i386_emit_pop,
3220 i386_emit_stack_flush,
3221 i386_emit_zero_ext,
3222 i386_emit_swap,
3223 i386_emit_stack_adjust,
3224 i386_emit_int_call_1,
6b9801d4
SS		 3225 i386_emit_void_call_2,
3226 i386_emit_eq_goto,
3227 i386_emit_ne_goto,
3228 i386_emit_lt_goto,
3229 i386_emit_le_goto,
3230 i386_emit_gt_goto,
3231 i386_emit_ge_goto
6a271cae
PA		 3232 };
3233
3234
3235static struct emit_ops *
3236x86_emit_ops (void)
3237{
3238#ifdef __x86_64__
3aee8918 3239 if (is_64bit_tdesc ())
6a271cae
PA		 3240 return &amd64_emit_ops;
3241 else
3242#endif
3243 return &i386_emit_ops;
3244}
3245
c2d6af84
PA		 3246static int
3247x86_supports_range_stepping (void)
3248{
3249 return 1;
3250}
3251
d0722149
DE		 3252/* This is initialized assuming an amd64 target.
3253 x86_arch_setup will correct it for i386 or amd64 targets. */
3254
3255struct linux_target_ops the_low_target =
3256{
3257 x86_arch_setup,
3aee8918
PA		 3258 x86_linux_regs_info,
3259 x86_cannot_fetch_register,
3260 x86_cannot_store_register,
c14dfd32 3261 NULL, /* fetch_register */
d0722149
DE		 3262 x86_get_pc,
3263 x86_set_pc,
3264 x86_breakpoint,
3265 x86_breakpoint_len,
3266 NULL,
3267 1,
3268 x86_breakpoint_at,
802e8e6d 3269 x86_supports_z_point_type,
aa5ca48f
DE		 3270 x86_insert_point,
3271 x86_remove_point,
3272 x86_stopped_by_watchpoint,
3273 x86_stopped_data_address,
d0722149
DE		 3274 /* collect_ptrace_register/supply_ptrace_register are not needed in the
3275 native i386 case (no registers smaller than an xfer unit), and are not
3276 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
3277 NULL,
3278 NULL,
3279 /* need to fix up i386 siginfo if host is amd64 */
3280 x86_siginfo_fixup,
aa5ca48f
DE		 3281 x86_linux_new_process,
3282 x86_linux_new_thread,
3a8a0396 3283 x86_linux_new_fork,
1570b33e 3284 x86_linux_prepare_to_resume,
219f2f23 3285 x86_linux_process_qsupported,
fa593d66
PA		 3286 x86_supports_tracepoints,
3287 x86_get_thread_area,
6a271cae 3288 x86_install_fast_tracepoint_jump_pad,
405f8e94
SS		 3289 x86_emit_ops,
3290 x86_get_min_fast_tracepoint_insn_len,
c2d6af84 3291 x86_supports_range_stepping,
d0722149 3292};
3aee8918
PA		 3293
3294void
3295initialize_low_arch (void)
3296{
3297 /* Initialize the Linux target descriptions. */
3298#ifdef __x86_64__
3299 init_registers_amd64_linux ();
3300 init_registers_amd64_avx_linux ();
01f9f808 3301 init_registers_amd64_avx512_linux ();
a196ebeb
WT		 3302 init_registers_amd64_mpx_linux ();
3303
3aee8918 3304 init_registers_x32_linux ();
7e5aaa09 3305 init_registers_x32_avx_linux ();
01f9f808 3306 init_registers_x32_avx512_linux ();
3aee8918 3307
8d749320 3308 tdesc_amd64_linux_no_xml = XNEW (struct target_desc);
3aee8918
PA		 3309 copy_target_description (tdesc_amd64_linux_no_xml, tdesc_amd64_linux);
3310 tdesc_amd64_linux_no_xml->xmltarget = xmltarget_amd64_linux_no_xml;
3311#endif
3312 init_registers_i386_linux ();
3313 init_registers_i386_mmx_linux ();
3314 init_registers_i386_avx_linux ();
01f9f808 3315 init_registers_i386_avx512_linux ();
a196ebeb 3316 init_registers_i386_mpx_linux ();
3aee8918 3317
8d749320 3318 tdesc_i386_linux_no_xml = XNEW (struct target_desc);
3aee8918
PA		 3319 copy_target_description (tdesc_i386_linux_no_xml, tdesc_i386_linux);
3320 tdesc_i386_linux_no_xml->xmltarget = xmltarget_i386_linux_no_xml;
3321
3322 initialize_regsets_info (&x86_regsets_info);
3323}
GDB Binutils - Deliverables
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