Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
7b6bb8da | 5 | 2010, 2011 Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
7a697b8d | 46 | #include "disasm.h" |
c8d5aac9 | 47 | #include "remote.h" |
acd5c798 | 48 | |
3d261580 | 49 | #include "gdb_assert.h" |
acd5c798 | 50 | #include "gdb_string.h" |
3d261580 | 51 | |
d2a7c97a | 52 | #include "i386-tdep.h" |
61113f8b | 53 | #include "i387-tdep.h" |
c131fcee | 54 | #include "i386-xstate.h" |
d2a7c97a | 55 | |
7ad10968 HZ |
56 | #include "record.h" |
57 | #include <stdint.h> | |
58 | ||
90884b2b | 59 | #include "features/i386/i386.c" |
c131fcee | 60 | #include "features/i386/i386-avx.c" |
3a13a53b | 61 | #include "features/i386/i386-mmx.c" |
90884b2b | 62 | |
c4fc7f1b | 63 | /* Register names. */ |
c40e1eab | 64 | |
90884b2b | 65 | static const char *i386_register_names[] = |
fc633446 MK |
66 | { |
67 | "eax", "ecx", "edx", "ebx", | |
68 | "esp", "ebp", "esi", "edi", | |
69 | "eip", "eflags", "cs", "ss", | |
70 | "ds", "es", "fs", "gs", | |
71 | "st0", "st1", "st2", "st3", | |
72 | "st4", "st5", "st6", "st7", | |
73 | "fctrl", "fstat", "ftag", "fiseg", | |
74 | "fioff", "foseg", "fooff", "fop", | |
75 | "xmm0", "xmm1", "xmm2", "xmm3", | |
76 | "xmm4", "xmm5", "xmm6", "xmm7", | |
77 | "mxcsr" | |
78 | }; | |
79 | ||
c131fcee L |
80 | static const char *i386_ymm_names[] = |
81 | { | |
82 | "ymm0", "ymm1", "ymm2", "ymm3", | |
83 | "ymm4", "ymm5", "ymm6", "ymm7", | |
84 | }; | |
85 | ||
86 | static const char *i386_ymmh_names[] = | |
87 | { | |
88 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
89 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
90 | }; | |
91 | ||
c4fc7f1b | 92 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 93 | |
90884b2b | 94 | static const char *i386_mmx_names[] = |
28fc6740 AC |
95 | { |
96 | "mm0", "mm1", "mm2", "mm3", | |
97 | "mm4", "mm5", "mm6", "mm7" | |
98 | }; | |
c40e1eab | 99 | |
1ba53b71 L |
100 | /* Register names for byte pseudo-registers. */ |
101 | ||
102 | static const char *i386_byte_names[] = | |
103 | { | |
104 | "al", "cl", "dl", "bl", | |
105 | "ah", "ch", "dh", "bh" | |
106 | }; | |
107 | ||
108 | /* Register names for word pseudo-registers. */ | |
109 | ||
110 | static const char *i386_word_names[] = | |
111 | { | |
112 | "ax", "cx", "dx", "bx", | |
9cad29ac | 113 | "", "bp", "si", "di" |
1ba53b71 L |
114 | }; |
115 | ||
116 | /* MMX register? */ | |
c40e1eab | 117 | |
28fc6740 | 118 | static int |
5716833c | 119 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 120 | { |
1ba53b71 L |
121 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
122 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
123 | |
124 | if (mm0_regnum < 0) | |
125 | return 0; | |
126 | ||
1ba53b71 L |
127 | regnum -= mm0_regnum; |
128 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
129 | } | |
130 | ||
131 | /* Byte register? */ | |
132 | ||
133 | int | |
134 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
135 | { | |
136 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
137 | ||
138 | regnum -= tdep->al_regnum; | |
139 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
140 | } | |
141 | ||
142 | /* Word register? */ | |
143 | ||
144 | int | |
145 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
146 | { | |
147 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
148 | ||
149 | regnum -= tdep->ax_regnum; | |
150 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
151 | } | |
152 | ||
153 | /* Dword register? */ | |
154 | ||
155 | int | |
156 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
157 | { | |
158 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
159 | int eax_regnum = tdep->eax_regnum; | |
160 | ||
161 | if (eax_regnum < 0) | |
162 | return 0; | |
163 | ||
164 | regnum -= eax_regnum; | |
165 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
166 | } |
167 | ||
9191d390 | 168 | static int |
c131fcee L |
169 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
170 | { | |
171 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
172 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
173 | ||
174 | if (ymm0h_regnum < 0) | |
175 | return 0; | |
176 | ||
177 | regnum -= ymm0h_regnum; | |
178 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
179 | } | |
180 | ||
181 | /* AVX register? */ | |
182 | ||
183 | int | |
184 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
185 | { | |
186 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
187 | int ymm0_regnum = tdep->ymm0_regnum; | |
188 | ||
189 | if (ymm0_regnum < 0) | |
190 | return 0; | |
191 | ||
192 | regnum -= ymm0_regnum; | |
193 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
194 | } | |
195 | ||
5716833c | 196 | /* SSE register? */ |
23a34459 | 197 | |
c131fcee L |
198 | int |
199 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 200 | { |
5716833c | 201 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 202 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 203 | |
c131fcee | 204 | if (num_xmm_regs == 0) |
5716833c MK |
205 | return 0; |
206 | ||
c131fcee L |
207 | regnum -= I387_XMM0_REGNUM (tdep); |
208 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
209 | } |
210 | ||
5716833c MK |
211 | static int |
212 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 213 | { |
5716833c MK |
214 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
215 | ||
20a6ec49 | 216 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
217 | return 0; |
218 | ||
20a6ec49 | 219 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
220 | } |
221 | ||
5716833c | 222 | /* FP register? */ |
23a34459 AC |
223 | |
224 | int | |
20a6ec49 | 225 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 226 | { |
20a6ec49 MD |
227 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
228 | ||
229 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
230 | return 0; |
231 | ||
20a6ec49 MD |
232 | return (I387_ST0_REGNUM (tdep) <= regnum |
233 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
234 | } |
235 | ||
236 | int | |
20a6ec49 | 237 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 238 | { |
20a6ec49 MD |
239 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
240 | ||
241 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
242 | return 0; |
243 | ||
20a6ec49 MD |
244 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
245 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
246 | } |
247 | ||
c131fcee L |
248 | /* Return the name of register REGNUM, or the empty string if it is |
249 | an anonymous register. */ | |
250 | ||
251 | static const char * | |
252 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
253 | { | |
254 | /* Hide the upper YMM registers. */ | |
255 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
256 | return ""; | |
257 | ||
258 | return tdesc_register_name (gdbarch, regnum); | |
259 | } | |
260 | ||
30b0e2d8 | 261 | /* Return the name of register REGNUM. */ |
fc633446 | 262 | |
1ba53b71 | 263 | const char * |
90884b2b | 264 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 265 | { |
1ba53b71 L |
266 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
267 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
268 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
269 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
270 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
271 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
272 | return i386_byte_names[regnum - tdep->al_regnum]; | |
273 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
274 | return i386_word_names[regnum - tdep->ax_regnum]; | |
275 | ||
276 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
277 | } |
278 | ||
c4fc7f1b | 279 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
280 | number used by GDB. */ |
281 | ||
8201327c | 282 | static int |
d3f73121 | 283 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 284 | { |
20a6ec49 MD |
285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
286 | ||
c4fc7f1b MK |
287 | /* This implements what GCC calls the "default" register map |
288 | (dbx_register_map[]). */ | |
289 | ||
85540d8c MK |
290 | if (reg >= 0 && reg <= 7) |
291 | { | |
9872ad24 JB |
292 | /* General-purpose registers. The debug info calls %ebp |
293 | register 4, and %esp register 5. */ | |
294 | if (reg == 4) | |
295 | return 5; | |
296 | else if (reg == 5) | |
297 | return 4; | |
298 | else return reg; | |
85540d8c MK |
299 | } |
300 | else if (reg >= 12 && reg <= 19) | |
301 | { | |
302 | /* Floating-point registers. */ | |
20a6ec49 | 303 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
304 | } |
305 | else if (reg >= 21 && reg <= 28) | |
306 | { | |
307 | /* SSE registers. */ | |
c131fcee L |
308 | int ymm0_regnum = tdep->ymm0_regnum; |
309 | ||
310 | if (ymm0_regnum >= 0 | |
311 | && i386_xmm_regnum_p (gdbarch, reg)) | |
312 | return reg - 21 + ymm0_regnum; | |
313 | else | |
314 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
315 | } |
316 | else if (reg >= 29 && reg <= 36) | |
317 | { | |
318 | /* MMX registers. */ | |
20a6ec49 | 319 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
320 | } |
321 | ||
322 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 323 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
324 | } |
325 | ||
c4fc7f1b MK |
326 | /* Convert SVR4 register number REG to the appropriate register number |
327 | used by GDB. */ | |
85540d8c | 328 | |
8201327c | 329 | static int |
d3f73121 | 330 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 331 | { |
20a6ec49 MD |
332 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
333 | ||
c4fc7f1b MK |
334 | /* This implements the GCC register map that tries to be compatible |
335 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
336 | ||
337 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
338 | numbers the floating point registers differently. */ |
339 | if (reg >= 0 && reg <= 9) | |
340 | { | |
acd5c798 | 341 | /* General-purpose registers. */ |
85540d8c MK |
342 | return reg; |
343 | } | |
344 | else if (reg >= 11 && reg <= 18) | |
345 | { | |
346 | /* Floating-point registers. */ | |
20a6ec49 | 347 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 348 | } |
c6f4c129 | 349 | else if (reg >= 21 && reg <= 36) |
85540d8c | 350 | { |
c4fc7f1b | 351 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 352 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
353 | } |
354 | ||
c6f4c129 JB |
355 | switch (reg) |
356 | { | |
20a6ec49 MD |
357 | case 37: return I387_FCTRL_REGNUM (tdep); |
358 | case 38: return I387_FSTAT_REGNUM (tdep); | |
359 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
360 | case 40: return I386_ES_REGNUM; |
361 | case 41: return I386_CS_REGNUM; | |
362 | case 42: return I386_SS_REGNUM; | |
363 | case 43: return I386_DS_REGNUM; | |
364 | case 44: return I386_FS_REGNUM; | |
365 | case 45: return I386_GS_REGNUM; | |
366 | } | |
367 | ||
85540d8c | 368 | /* This will hopefully provoke a warning. */ |
d3f73121 | 369 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 370 | } |
5716833c | 371 | |
fc338970 | 372 | \f |
917317f4 | 373 | |
fc338970 MK |
374 | /* This is the variable that is set with "set disassembly-flavor", and |
375 | its legitimate values. */ | |
53904c9e AC |
376 | static const char att_flavor[] = "att"; |
377 | static const char intel_flavor[] = "intel"; | |
378 | static const char *valid_flavors[] = | |
c5aa993b | 379 | { |
c906108c SS |
380 | att_flavor, |
381 | intel_flavor, | |
382 | NULL | |
383 | }; | |
53904c9e | 384 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 385 | \f |
c906108c | 386 | |
acd5c798 MK |
387 | /* Use the program counter to determine the contents and size of a |
388 | breakpoint instruction. Return a pointer to a string of bytes that | |
389 | encode a breakpoint instruction, store the length of the string in | |
390 | *LEN and optionally adjust *PC to point to the correct memory | |
391 | location for inserting the breakpoint. | |
c906108c | 392 | |
acd5c798 MK |
393 | On the i386 we have a single breakpoint that fits in a single byte |
394 | and can be inserted anywhere. | |
c906108c | 395 | |
acd5c798 | 396 | This function is 64-bit safe. */ |
63c0089f MK |
397 | |
398 | static const gdb_byte * | |
67d57894 | 399 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 400 | { |
63c0089f MK |
401 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
402 | ||
acd5c798 MK |
403 | *len = sizeof (break_insn); |
404 | return break_insn; | |
c906108c | 405 | } |
237fc4c9 PA |
406 | \f |
407 | /* Displaced instruction handling. */ | |
408 | ||
1903f0e6 DE |
409 | /* Skip the legacy instruction prefixes in INSN. |
410 | Not all prefixes are valid for any particular insn | |
411 | but we needn't care, the insn will fault if it's invalid. | |
412 | The result is a pointer to the first opcode byte, | |
413 | or NULL if we run off the end of the buffer. */ | |
414 | ||
415 | static gdb_byte * | |
416 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
417 | { | |
418 | gdb_byte *end = insn + max_len; | |
419 | ||
420 | while (insn < end) | |
421 | { | |
422 | switch (*insn) | |
423 | { | |
424 | case DATA_PREFIX_OPCODE: | |
425 | case ADDR_PREFIX_OPCODE: | |
426 | case CS_PREFIX_OPCODE: | |
427 | case DS_PREFIX_OPCODE: | |
428 | case ES_PREFIX_OPCODE: | |
429 | case FS_PREFIX_OPCODE: | |
430 | case GS_PREFIX_OPCODE: | |
431 | case SS_PREFIX_OPCODE: | |
432 | case LOCK_PREFIX_OPCODE: | |
433 | case REPE_PREFIX_OPCODE: | |
434 | case REPNE_PREFIX_OPCODE: | |
435 | ++insn; | |
436 | continue; | |
437 | default: | |
438 | return insn; | |
439 | } | |
440 | } | |
441 | ||
442 | return NULL; | |
443 | } | |
237fc4c9 PA |
444 | |
445 | static int | |
1903f0e6 | 446 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 447 | { |
1777feb0 | 448 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
449 | if (insn[0] == 0xea) |
450 | return 1; | |
451 | ||
452 | if (insn[0] == 0xff) | |
453 | { | |
1777feb0 | 454 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
455 | if ((insn[1] & 0x38) == 0x20) |
456 | return 1; | |
457 | ||
1777feb0 | 458 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
459 | if ((insn[1] & 0x38) == 0x28) |
460 | return 1; | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static int | |
1903f0e6 | 467 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 468 | { |
1777feb0 | 469 | /* call far, absolute. */ |
237fc4c9 PA |
470 | if (insn[0] == 0x9a) |
471 | return 1; | |
472 | ||
473 | if (insn[0] == 0xff) | |
474 | { | |
1777feb0 | 475 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
476 | if ((insn[1] & 0x38) == 0x10) |
477 | return 1; | |
478 | ||
1777feb0 | 479 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
480 | if ((insn[1] & 0x38) == 0x18) |
481 | return 1; | |
482 | } | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static int | |
1903f0e6 | 488 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
489 | { |
490 | switch (insn[0]) | |
491 | { | |
1777feb0 | 492 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 493 | case 0xc3: /* ret near */ |
1777feb0 | 494 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
495 | case 0xcb: /* ret far */ |
496 | case 0xcf: /* iret */ | |
497 | return 1; | |
498 | ||
499 | default: | |
500 | return 0; | |
501 | } | |
502 | } | |
503 | ||
504 | static int | |
1903f0e6 | 505 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
506 | { |
507 | if (i386_absolute_call_p (insn)) | |
508 | return 1; | |
509 | ||
1777feb0 | 510 | /* call near, relative. */ |
237fc4c9 PA |
511 | if (insn[0] == 0xe8) |
512 | return 1; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
237fc4c9 PA |
517 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
518 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 519 | |
237fc4c9 | 520 | static int |
b55078be | 521 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 PA |
522 | { |
523 | if (insn[0] == 0xcd) | |
524 | { | |
525 | *lengthp = 2; | |
526 | return 1; | |
527 | } | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
b55078be DE |
532 | /* Some kernels may run one past a syscall insn, so we have to cope. |
533 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
534 | ||
535 | struct displaced_step_closure * | |
536 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
537 | CORE_ADDR from, CORE_ADDR to, | |
538 | struct regcache *regs) | |
539 | { | |
540 | size_t len = gdbarch_max_insn_length (gdbarch); | |
541 | gdb_byte *buf = xmalloc (len); | |
542 | ||
543 | read_memory (from, buf, len); | |
544 | ||
545 | /* GDB may get control back after the insn after the syscall. | |
546 | Presumably this is a kernel bug. | |
547 | If this is a syscall, make sure there's a nop afterwards. */ | |
548 | { | |
549 | int syscall_length; | |
550 | gdb_byte *insn; | |
551 | ||
552 | insn = i386_skip_prefixes (buf, len); | |
553 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
554 | insn[syscall_length] = NOP_OPCODE; | |
555 | } | |
556 | ||
557 | write_memory (to, buf, len); | |
558 | ||
559 | if (debug_displaced) | |
560 | { | |
561 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
562 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
563 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
564 | } | |
565 | ||
566 | return (struct displaced_step_closure *) buf; | |
567 | } | |
568 | ||
237fc4c9 PA |
569 | /* Fix up the state of registers and memory after having single-stepped |
570 | a displaced instruction. */ | |
1903f0e6 | 571 | |
237fc4c9 PA |
572 | void |
573 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
574 | struct displaced_step_closure *closure, | |
575 | CORE_ADDR from, CORE_ADDR to, | |
576 | struct regcache *regs) | |
577 | { | |
e17a4113 UW |
578 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
579 | ||
237fc4c9 PA |
580 | /* The offset we applied to the instruction's address. |
581 | This could well be negative (when viewed as a signed 32-bit | |
582 | value), but ULONGEST won't reflect that, so take care when | |
583 | applying it. */ | |
584 | ULONGEST insn_offset = to - from; | |
585 | ||
586 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
587 | copy of the instruction. */ | |
588 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
589 | /* The start of the insn, needed in case we see some prefixes. */ |
590 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
591 | |
592 | if (debug_displaced) | |
593 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 594 | "displaced: fixup (%s, %s), " |
237fc4c9 | 595 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
596 | paddress (gdbarch, from), paddress (gdbarch, to), |
597 | insn[0], insn[1]); | |
237fc4c9 PA |
598 | |
599 | /* The list of issues to contend with here is taken from | |
600 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
601 | Yay for Free Software! */ | |
602 | ||
603 | /* Relocate the %eip, if necessary. */ | |
604 | ||
1903f0e6 DE |
605 | /* The instruction recognizers we use assume any leading prefixes |
606 | have been skipped. */ | |
607 | { | |
608 | /* This is the size of the buffer in closure. */ | |
609 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
610 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
611 | /* If there are too many prefixes, just ignore the insn. | |
612 | It will fault when run. */ | |
613 | if (opcode != NULL) | |
614 | insn = opcode; | |
615 | } | |
616 | ||
237fc4c9 PA |
617 | /* Except in the case of absolute or indirect jump or call |
618 | instructions, or a return instruction, the new eip is relative to | |
619 | the displaced instruction; make it relative. Well, signal | |
620 | handler returns don't need relocation either, but we use the | |
621 | value of %eip to recognize those; see below. */ | |
622 | if (! i386_absolute_jmp_p (insn) | |
623 | && ! i386_absolute_call_p (insn) | |
624 | && ! i386_ret_p (insn)) | |
625 | { | |
626 | ULONGEST orig_eip; | |
b55078be | 627 | int insn_len; |
237fc4c9 PA |
628 | |
629 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
630 | ||
631 | /* A signal trampoline system call changes the %eip, resuming | |
632 | execution of the main program after the signal handler has | |
633 | returned. That makes them like 'return' instructions; we | |
634 | shouldn't relocate %eip. | |
635 | ||
636 | But most system calls don't, and we do need to relocate %eip. | |
637 | ||
638 | Our heuristic for distinguishing these cases: if stepping | |
639 | over the system call instruction left control directly after | |
640 | the instruction, the we relocate --- control almost certainly | |
641 | doesn't belong in the displaced copy. Otherwise, we assume | |
642 | the instruction has put control where it belongs, and leave | |
643 | it unrelocated. Goodness help us if there are PC-relative | |
644 | system calls. */ | |
645 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
646 | && orig_eip != to + (insn - insn_start) + insn_len |
647 | /* GDB can get control back after the insn after the syscall. | |
648 | Presumably this is a kernel bug. | |
649 | i386_displaced_step_copy_insn ensures its a nop, | |
650 | we add one to the length for it. */ | |
651 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
652 | { |
653 | if (debug_displaced) | |
654 | fprintf_unfiltered (gdb_stdlog, | |
655 | "displaced: syscall changed %%eip; " | |
656 | "not relocating\n"); | |
657 | } | |
658 | else | |
659 | { | |
660 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
661 | ||
1903f0e6 DE |
662 | /* If we just stepped over a breakpoint insn, we don't backup |
663 | the pc on purpose; this is to match behaviour without | |
664 | stepping. */ | |
237fc4c9 PA |
665 | |
666 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
667 | ||
668 | if (debug_displaced) | |
669 | fprintf_unfiltered (gdb_stdlog, | |
670 | "displaced: " | |
5af949e3 UW |
671 | "relocated %%eip from %s to %s\n", |
672 | paddress (gdbarch, orig_eip), | |
673 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
674 | } |
675 | } | |
676 | ||
677 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
678 | pushed value, and should be cleared. We'll leave this for later, | |
679 | since GDB already messes up the TF flag when stepping over a | |
680 | pushfl. */ | |
681 | ||
682 | /* If the instruction was a call, the return address now atop the | |
683 | stack is the address following the copied instruction. We need | |
684 | to make it the address following the original instruction. */ | |
685 | if (i386_call_p (insn)) | |
686 | { | |
687 | ULONGEST esp; | |
688 | ULONGEST retaddr; | |
689 | const ULONGEST retaddr_len = 4; | |
690 | ||
691 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 692 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 693 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 694 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
695 | |
696 | if (debug_displaced) | |
697 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
698 | "displaced: relocated return addr at %s to %s\n", |
699 | paddress (gdbarch, esp), | |
700 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
701 | } |
702 | } | |
dde08ee1 PA |
703 | |
704 | static void | |
705 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
706 | { | |
707 | target_write_memory (*to, buf, len); | |
708 | *to += len; | |
709 | } | |
710 | ||
711 | static void | |
712 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
713 | CORE_ADDR *to, CORE_ADDR oldloc) | |
714 | { | |
715 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
716 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
717 | int offset = 0, rel32, newrel; | |
718 | int insn_length; | |
719 | gdb_byte *insn = buf; | |
720 | ||
721 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
722 | ||
723 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
724 | I386_MAX_INSN_LEN, oldloc); | |
725 | ||
726 | /* Get past the prefixes. */ | |
727 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
728 | ||
729 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
730 | the address pushed being the location where the original call in | |
731 | the user program would return to. */ | |
732 | if (insn[0] == 0xe8) | |
733 | { | |
734 | gdb_byte push_buf[16]; | |
735 | unsigned int ret_addr; | |
736 | ||
737 | /* Where "ret" in the original code will return to. */ | |
738 | ret_addr = oldloc + insn_length; | |
1777feb0 | 739 | push_buf[0] = 0x68; /* pushq $... */ |
dde08ee1 PA |
740 | memcpy (&push_buf[1], &ret_addr, 4); |
741 | /* Push the push. */ | |
742 | append_insns (to, 5, push_buf); | |
743 | ||
744 | /* Convert the relative call to a relative jump. */ | |
745 | insn[0] = 0xe9; | |
746 | ||
747 | /* Adjust the destination offset. */ | |
748 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
749 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
750 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
751 | ||
752 | if (debug_displaced) | |
753 | fprintf_unfiltered (gdb_stdlog, | |
754 | "Adjusted insn rel32=%s at %s to" | |
755 | " rel32=%s at %s\n", | |
756 | hex_string (rel32), paddress (gdbarch, oldloc), | |
757 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
758 | |
759 | /* Write the adjusted jump into its displaced location. */ | |
760 | append_insns (to, 5, insn); | |
761 | return; | |
762 | } | |
763 | ||
764 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
765 | handled above. */ | |
766 | if (insn[0] == 0xe9) | |
767 | offset = 1; | |
768 | /* Adjust conditional jumps. */ | |
769 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
770 | offset = 2; | |
771 | ||
772 | if (offset) | |
773 | { | |
774 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
775 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 776 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
777 | if (debug_displaced) |
778 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
779 | "Adjusted insn rel32=%s at %s to" |
780 | " rel32=%s at %s\n", | |
dde08ee1 PA |
781 | hex_string (rel32), paddress (gdbarch, oldloc), |
782 | hex_string (newrel), paddress (gdbarch, *to)); | |
783 | } | |
784 | ||
785 | /* Write the adjusted instructions into their displaced | |
786 | location. */ | |
787 | append_insns (to, insn_length, buf); | |
788 | } | |
789 | ||
fc338970 | 790 | \f |
acd5c798 MK |
791 | #ifdef I386_REGNO_TO_SYMMETRY |
792 | #error "The Sequent Symmetry is no longer supported." | |
793 | #endif | |
c906108c | 794 | |
acd5c798 MK |
795 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
796 | and %esp "belong" to the calling function. Therefore these | |
797 | registers should be saved if they're going to be modified. */ | |
c906108c | 798 | |
acd5c798 MK |
799 | /* The maximum number of saved registers. This should include all |
800 | registers mentioned above, and %eip. */ | |
a3386186 | 801 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
802 | |
803 | struct i386_frame_cache | |
c906108c | 804 | { |
acd5c798 MK |
805 | /* Base address. */ |
806 | CORE_ADDR base; | |
772562f8 | 807 | LONGEST sp_offset; |
acd5c798 MK |
808 | CORE_ADDR pc; |
809 | ||
fd13a04a AC |
810 | /* Saved registers. */ |
811 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 812 | CORE_ADDR saved_sp; |
e0c62198 | 813 | int saved_sp_reg; |
acd5c798 MK |
814 | int pc_in_eax; |
815 | ||
816 | /* Stack space reserved for local variables. */ | |
817 | long locals; | |
818 | }; | |
819 | ||
820 | /* Allocate and initialize a frame cache. */ | |
821 | ||
822 | static struct i386_frame_cache * | |
fd13a04a | 823 | i386_alloc_frame_cache (void) |
acd5c798 MK |
824 | { |
825 | struct i386_frame_cache *cache; | |
826 | int i; | |
827 | ||
828 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
829 | ||
830 | /* Base address. */ | |
831 | cache->base = 0; | |
832 | cache->sp_offset = -4; | |
833 | cache->pc = 0; | |
834 | ||
fd13a04a AC |
835 | /* Saved registers. We initialize these to -1 since zero is a valid |
836 | offset (that's where %ebp is supposed to be stored). */ | |
837 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
838 | cache->saved_regs[i] = -1; | |
acd5c798 | 839 | cache->saved_sp = 0; |
e0c62198 | 840 | cache->saved_sp_reg = -1; |
acd5c798 MK |
841 | cache->pc_in_eax = 0; |
842 | ||
843 | /* Frameless until proven otherwise. */ | |
844 | cache->locals = -1; | |
845 | ||
846 | return cache; | |
847 | } | |
c906108c | 848 | |
acd5c798 MK |
849 | /* If the instruction at PC is a jump, return the address of its |
850 | target. Otherwise, return PC. */ | |
c906108c | 851 | |
acd5c798 | 852 | static CORE_ADDR |
e17a4113 | 853 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 854 | { |
e17a4113 | 855 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 856 | gdb_byte op; |
acd5c798 MK |
857 | long delta = 0; |
858 | int data16 = 0; | |
c906108c | 859 | |
3dcabaa8 MS |
860 | if (target_read_memory (pc, &op, 1)) |
861 | return pc; | |
862 | ||
acd5c798 | 863 | if (op == 0x66) |
c906108c | 864 | { |
c906108c | 865 | data16 = 1; |
e17a4113 | 866 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
867 | } |
868 | ||
acd5c798 | 869 | switch (op) |
c906108c SS |
870 | { |
871 | case 0xe9: | |
fc338970 | 872 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
873 | if (data16) |
874 | { | |
e17a4113 | 875 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 876 | |
fc338970 MK |
877 | /* Include the size of the jmp instruction (including the |
878 | 0x66 prefix). */ | |
acd5c798 | 879 | delta += 4; |
c906108c SS |
880 | } |
881 | else | |
882 | { | |
e17a4113 | 883 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 884 | |
acd5c798 MK |
885 | /* Include the size of the jmp instruction. */ |
886 | delta += 5; | |
c906108c SS |
887 | } |
888 | break; | |
889 | case 0xeb: | |
fc338970 | 890 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 891 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 892 | |
acd5c798 | 893 | delta += data16 + 2; |
c906108c SS |
894 | break; |
895 | } | |
c906108c | 896 | |
acd5c798 MK |
897 | return pc + delta; |
898 | } | |
fc338970 | 899 | |
acd5c798 MK |
900 | /* Check whether PC points at a prologue for a function returning a |
901 | structure or union. If so, it updates CACHE and returns the | |
902 | address of the first instruction after the code sequence that | |
903 | removes the "hidden" argument from the stack or CURRENT_PC, | |
904 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 905 | |
acd5c798 MK |
906 | static CORE_ADDR |
907 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
908 | struct i386_frame_cache *cache) | |
c906108c | 909 | { |
acd5c798 MK |
910 | /* Functions that return a structure or union start with: |
911 | ||
912 | popl %eax 0x58 | |
913 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
914 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
915 | ||
916 | (the System V compiler puts out the second `xchg' instruction, | |
917 | and the assembler doesn't try to optimize it, so the 'sib' form | |
918 | gets generated). This sequence is used to get the address of the | |
919 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
920 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
921 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
922 | gdb_byte buf[4]; | |
923 | gdb_byte op; | |
c906108c | 924 | |
acd5c798 MK |
925 | if (current_pc <= pc) |
926 | return pc; | |
927 | ||
3dcabaa8 MS |
928 | if (target_read_memory (pc, &op, 1)) |
929 | return pc; | |
c906108c | 930 | |
acd5c798 MK |
931 | if (op != 0x58) /* popl %eax */ |
932 | return pc; | |
c906108c | 933 | |
3dcabaa8 MS |
934 | if (target_read_memory (pc + 1, buf, 4)) |
935 | return pc; | |
936 | ||
acd5c798 MK |
937 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
938 | return pc; | |
c906108c | 939 | |
acd5c798 | 940 | if (current_pc == pc) |
c906108c | 941 | { |
acd5c798 MK |
942 | cache->sp_offset += 4; |
943 | return current_pc; | |
c906108c SS |
944 | } |
945 | ||
acd5c798 | 946 | if (current_pc == pc + 1) |
c906108c | 947 | { |
acd5c798 MK |
948 | cache->pc_in_eax = 1; |
949 | return current_pc; | |
950 | } | |
951 | ||
952 | if (buf[1] == proto1[1]) | |
953 | return pc + 4; | |
954 | else | |
955 | return pc + 5; | |
956 | } | |
957 | ||
958 | static CORE_ADDR | |
959 | i386_skip_probe (CORE_ADDR pc) | |
960 | { | |
961 | /* A function may start with | |
fc338970 | 962 | |
acd5c798 MK |
963 | pushl constant |
964 | call _probe | |
965 | addl $4, %esp | |
fc338970 | 966 | |
acd5c798 MK |
967 | followed by |
968 | ||
969 | pushl %ebp | |
fc338970 | 970 | |
acd5c798 | 971 | etc. */ |
63c0089f MK |
972 | gdb_byte buf[8]; |
973 | gdb_byte op; | |
fc338970 | 974 | |
3dcabaa8 MS |
975 | if (target_read_memory (pc, &op, 1)) |
976 | return pc; | |
acd5c798 MK |
977 | |
978 | if (op == 0x68 || op == 0x6a) | |
979 | { | |
980 | int delta; | |
c906108c | 981 | |
acd5c798 MK |
982 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
983 | four-byte operand, depending on the opcode. */ | |
c906108c | 984 | if (op == 0x68) |
acd5c798 | 985 | delta = 5; |
c906108c | 986 | else |
acd5c798 | 987 | delta = 2; |
c906108c | 988 | |
acd5c798 MK |
989 | /* Read the following 8 bytes, which should be `call _probe' (6 |
990 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
991 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 992 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 993 | pc += delta + sizeof (buf); |
c906108c SS |
994 | } |
995 | ||
acd5c798 MK |
996 | return pc; |
997 | } | |
998 | ||
92dd43fa MK |
999 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1000 | stack pointer. Check whether PC points to such code, and update | |
1001 | CACHE accordingly. Return the first instruction after the code | |
1002 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1003 | recognize the code, return PC. */ | |
1004 | ||
1005 | static CORE_ADDR | |
1006 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1007 | struct i386_frame_cache *cache) | |
1008 | { | |
e0c62198 L |
1009 | /* There are 2 code sequences to re-align stack before the frame |
1010 | gets set up: | |
1011 | ||
1012 | 1. Use a caller-saved saved register: | |
1013 | ||
1014 | leal 4(%esp), %reg | |
1015 | andl $-XXX, %esp | |
1016 | pushl -4(%reg) | |
1017 | ||
1018 | 2. Use a callee-saved saved register: | |
1019 | ||
1020 | pushl %reg | |
1021 | leal 8(%esp), %reg | |
1022 | andl $-XXX, %esp | |
1023 | pushl -4(%reg) | |
1024 | ||
1025 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1026 | ||
1027 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1028 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1029 | */ | |
1030 | ||
1031 | gdb_byte buf[14]; | |
1032 | int reg; | |
1033 | int offset, offset_and; | |
1034 | static int regnums[8] = { | |
1035 | I386_EAX_REGNUM, /* %eax */ | |
1036 | I386_ECX_REGNUM, /* %ecx */ | |
1037 | I386_EDX_REGNUM, /* %edx */ | |
1038 | I386_EBX_REGNUM, /* %ebx */ | |
1039 | I386_ESP_REGNUM, /* %esp */ | |
1040 | I386_EBP_REGNUM, /* %ebp */ | |
1041 | I386_ESI_REGNUM, /* %esi */ | |
1042 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1043 | }; |
92dd43fa | 1044 | |
e0c62198 L |
1045 | if (target_read_memory (pc, buf, sizeof buf)) |
1046 | return pc; | |
1047 | ||
1048 | /* Check caller-saved saved register. The first instruction has | |
1049 | to be "leal 4(%esp), %reg". */ | |
1050 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1051 | { | |
1052 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1053 | if ((buf[1] & 0xc7) != 0x44) | |
1054 | return pc; | |
1055 | ||
1056 | /* REG has register number. */ | |
1057 | reg = (buf[1] >> 3) & 7; | |
1058 | offset = 4; | |
1059 | } | |
1060 | else | |
1061 | { | |
1062 | /* Check callee-saved saved register. The first instruction | |
1063 | has to be "pushl %reg". */ | |
1064 | if ((buf[0] & 0xf8) != 0x50) | |
1065 | return pc; | |
1066 | ||
1067 | /* Get register. */ | |
1068 | reg = buf[0] & 0x7; | |
1069 | ||
1070 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1071 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1072 | return pc; | |
1073 | ||
1074 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1075 | if ((buf[2] & 0xc7) != 0x44) | |
1076 | return pc; | |
1077 | ||
1078 | /* REG has register number. Registers in pushl and leal have to | |
1079 | be the same. */ | |
1080 | if (reg != ((buf[2] >> 3) & 7)) | |
1081 | return pc; | |
1082 | ||
1083 | offset = 5; | |
1084 | } | |
1085 | ||
1086 | /* Rigister can't be %esp nor %ebp. */ | |
1087 | if (reg == 4 || reg == 5) | |
1088 | return pc; | |
1089 | ||
1090 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1091 | if (buf[offset + 1] != 0xe4 | |
1092 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1093 | return pc; | |
1094 | ||
1095 | offset_and = offset; | |
1096 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1097 | ||
1098 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1099 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1100 | if (buf[offset] != 0xff | |
1101 | || buf[offset + 2] != 0xfc | |
1102 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1103 | return pc; | |
1104 | ||
1105 | /* R/M has register. Registers in leal and pushl have to be the | |
1106 | same. */ | |
1107 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1108 | return pc; |
1109 | ||
e0c62198 L |
1110 | if (current_pc > pc + offset_and) |
1111 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1112 | |
e0c62198 | 1113 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1114 | } |
1115 | ||
37bdc87e | 1116 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1117 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1118 | |
1119 | /* Instruction description. */ | |
1120 | struct i386_insn | |
1121 | { | |
1122 | size_t len; | |
237fc4c9 PA |
1123 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1124 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1125 | }; |
1126 | ||
1127 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
1128 | the first instruction description that matches. Otherwise, return | |
1129 | NULL. */ | |
1130 | ||
1131 | static struct i386_insn * | |
1132 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
1133 | { | |
1134 | struct i386_insn *insn; | |
63c0089f | 1135 | gdb_byte op; |
37bdc87e | 1136 | |
3dcabaa8 MS |
1137 | if (target_read_memory (pc, &op, 1)) |
1138 | return NULL; | |
37bdc87e MK |
1139 | |
1140 | for (insn = skip_insns; insn->len > 0; insn++) | |
1141 | { | |
1142 | if ((op & insn->mask[0]) == insn->insn[0]) | |
1143 | { | |
237fc4c9 | 1144 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 1145 | int insn_matched = 1; |
37bdc87e MK |
1146 | size_t i; |
1147 | ||
1148 | gdb_assert (insn->len > 1); | |
237fc4c9 | 1149 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 1150 | |
3dcabaa8 MS |
1151 | if (target_read_memory (pc + 1, buf, insn->len - 1)) |
1152 | return NULL; | |
1153 | ||
37bdc87e MK |
1154 | for (i = 1; i < insn->len; i++) |
1155 | { | |
1156 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 1157 | insn_matched = 0; |
37bdc87e | 1158 | } |
613e8135 MK |
1159 | |
1160 | if (insn_matched) | |
1161 | return insn; | |
37bdc87e MK |
1162 | } |
1163 | } | |
1164 | ||
1165 | return NULL; | |
1166 | } | |
1167 | ||
1168 | /* Some special instructions that might be migrated by GCC into the | |
1169 | part of the prologue that sets up the new stack frame. Because the | |
1170 | stack frame hasn't been setup yet, no registers have been saved | |
1171 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1172 | touched. */ | |
1173 | ||
1174 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1175 | { | |
1777feb0 | 1176 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1177 | |
1178 | ??? Should we handle 16-bit operand-sizes here? */ | |
1179 | ||
1180 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1181 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1182 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1183 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1184 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1185 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1186 | { 5, { 0xb8 }, { 0xfe } }, | |
1187 | /* `movl imm32, %edx' */ | |
1188 | { 5, { 0xba }, { 0xff } }, | |
1189 | ||
1190 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1191 | encoding for `mov m32, %eax'. | |
1192 | ||
1193 | ??? Should we handle SIB adressing here? | |
1194 | ??? Should we handle 16-bit operand-sizes here? */ | |
1195 | ||
1196 | /* `movl m32, %eax' */ | |
1197 | { 5, { 0xa1 }, { 0xff } }, | |
1198 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1199 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1200 | /* `movl m32, %edx' */ | |
1201 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1202 | ||
1203 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1204 | Because of the symmetry, there are actually two ways to encode | |
1205 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1206 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1207 | ||
1208 | /* `subl %eax, %eax' */ | |
1209 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1210 | /* `subl %ecx, %ecx' */ | |
1211 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1212 | /* `subl %edx, %edx' */ | |
1213 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1214 | /* `xorl %eax, %eax' */ | |
1215 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1216 | /* `xorl %ecx, %ecx' */ | |
1217 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1218 | /* `xorl %edx, %edx' */ | |
1219 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1220 | { 0 } | |
1221 | }; | |
1222 | ||
e11481da PM |
1223 | |
1224 | /* Check whether PC points to a no-op instruction. */ | |
1225 | static CORE_ADDR | |
1226 | i386_skip_noop (CORE_ADDR pc) | |
1227 | { | |
1228 | gdb_byte op; | |
1229 | int check = 1; | |
1230 | ||
3dcabaa8 MS |
1231 | if (target_read_memory (pc, &op, 1)) |
1232 | return pc; | |
e11481da PM |
1233 | |
1234 | while (check) | |
1235 | { | |
1236 | check = 0; | |
1237 | /* Ignore `nop' instruction. */ | |
1238 | if (op == 0x90) | |
1239 | { | |
1240 | pc += 1; | |
3dcabaa8 MS |
1241 | if (target_read_memory (pc, &op, 1)) |
1242 | return pc; | |
e11481da PM |
1243 | check = 1; |
1244 | } | |
1245 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1246 | Microsoft system dlls often start with | |
1247 | a `mov %edi,%edi' instruction. | |
1248 | The 5 bytes before the function start are | |
1249 | filled with `nop' instructions. | |
1250 | This pattern can be used for hot-patching: | |
1251 | The `mov %edi, %edi' instruction can be replaced by a | |
1252 | near jump to the location of the 5 `nop' instructions | |
1253 | which can be replaced by a 32-bit jump to anywhere | |
1254 | in the 32-bit address space. */ | |
1255 | ||
1256 | else if (op == 0x8b) | |
1257 | { | |
3dcabaa8 MS |
1258 | if (target_read_memory (pc + 1, &op, 1)) |
1259 | return pc; | |
1260 | ||
e11481da PM |
1261 | if (op == 0xff) |
1262 | { | |
1263 | pc += 2; | |
3dcabaa8 MS |
1264 | if (target_read_memory (pc, &op, 1)) |
1265 | return pc; | |
1266 | ||
e11481da PM |
1267 | check = 1; |
1268 | } | |
1269 | } | |
1270 | } | |
1271 | return pc; | |
1272 | } | |
1273 | ||
acd5c798 MK |
1274 | /* Check whether PC points at a code that sets up a new stack frame. |
1275 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1276 | instruction after the sequence that sets up the frame or LIMIT, |
1277 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1278 | |
1279 | static CORE_ADDR | |
e17a4113 UW |
1280 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1281 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1282 | struct i386_frame_cache *cache) |
1283 | { | |
e17a4113 | 1284 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1285 | struct i386_insn *insn; |
63c0089f | 1286 | gdb_byte op; |
26604a34 | 1287 | int skip = 0; |
acd5c798 | 1288 | |
37bdc87e MK |
1289 | if (limit <= pc) |
1290 | return limit; | |
acd5c798 | 1291 | |
3dcabaa8 MS |
1292 | if (target_read_memory (pc, &op, 1)) |
1293 | return pc; | |
acd5c798 | 1294 | |
c906108c | 1295 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1296 | { |
acd5c798 MK |
1297 | /* Take into account that we've executed the `pushl %ebp' that |
1298 | starts this instruction sequence. */ | |
fd13a04a | 1299 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1300 | cache->sp_offset += 4; |
37bdc87e | 1301 | pc++; |
acd5c798 MK |
1302 | |
1303 | /* If that's all, return now. */ | |
37bdc87e MK |
1304 | if (limit <= pc) |
1305 | return limit; | |
26604a34 | 1306 | |
b4632131 | 1307 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1308 | GCC into the prologue and skip them. At this point in the |
1309 | prologue, code should only touch the scratch registers %eax, | |
1310 | %ecx and %edx, so while the number of posibilities is sheer, | |
1311 | it is limited. | |
5daa5b4e | 1312 | |
26604a34 MK |
1313 | Make sure we only skip these instructions if we later see the |
1314 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1315 | while (pc + skip < limit) |
26604a34 | 1316 | { |
37bdc87e MK |
1317 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1318 | if (insn == NULL) | |
1319 | break; | |
b4632131 | 1320 | |
37bdc87e | 1321 | skip += insn->len; |
26604a34 MK |
1322 | } |
1323 | ||
37bdc87e MK |
1324 | /* If that's all, return now. */ |
1325 | if (limit <= pc + skip) | |
1326 | return limit; | |
1327 | ||
3dcabaa8 MS |
1328 | if (target_read_memory (pc + skip, &op, 1)) |
1329 | return pc + skip; | |
37bdc87e | 1330 | |
26604a34 | 1331 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1332 | switch (op) |
c906108c SS |
1333 | { |
1334 | case 0x8b: | |
e17a4113 UW |
1335 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1336 | != 0xec) | |
37bdc87e | 1337 | return pc; |
c906108c SS |
1338 | break; |
1339 | case 0x89: | |
e17a4113 UW |
1340 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1341 | != 0xe5) | |
37bdc87e | 1342 | return pc; |
c906108c SS |
1343 | break; |
1344 | default: | |
37bdc87e | 1345 | return pc; |
c906108c | 1346 | } |
acd5c798 | 1347 | |
26604a34 MK |
1348 | /* OK, we actually have a frame. We just don't know how large |
1349 | it is yet. Set its size to zero. We'll adjust it if | |
1350 | necessary. We also now commit to skipping the special | |
1351 | instructions mentioned before. */ | |
acd5c798 | 1352 | cache->locals = 0; |
37bdc87e | 1353 | pc += (skip + 2); |
acd5c798 MK |
1354 | |
1355 | /* If that's all, return now. */ | |
37bdc87e MK |
1356 | if (limit <= pc) |
1357 | return limit; | |
acd5c798 | 1358 | |
fc338970 MK |
1359 | /* Check for stack adjustment |
1360 | ||
acd5c798 | 1361 | subl $XXX, %esp |
fc338970 | 1362 | |
fd35795f | 1363 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1364 | reg, so we don't have to worry about a data16 prefix. */ |
3dcabaa8 MS |
1365 | if (target_read_memory (pc, &op, 1)) |
1366 | return pc; | |
c906108c SS |
1367 | if (op == 0x83) |
1368 | { | |
fd35795f | 1369 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1370 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1371 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1372 | return pc; |
acd5c798 | 1373 | |
37bdc87e MK |
1374 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1375 | make sense to be negative). */ | |
e17a4113 | 1376 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1377 | return pc + 3; |
c906108c SS |
1378 | } |
1379 | else if (op == 0x81) | |
1380 | { | |
fd35795f | 1381 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1382 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1383 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1384 | return pc; |
acd5c798 | 1385 | |
fd35795f | 1386 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1387 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1388 | return pc + 6; |
c906108c SS |
1389 | } |
1390 | else | |
1391 | { | |
acd5c798 | 1392 | /* Some instruction other than `subl'. */ |
37bdc87e | 1393 | return pc; |
c906108c SS |
1394 | } |
1395 | } | |
37bdc87e | 1396 | else if (op == 0xc8) /* enter */ |
c906108c | 1397 | { |
e17a4113 | 1398 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1399 | return pc + 4; |
c906108c | 1400 | } |
21d0e8a4 | 1401 | |
acd5c798 | 1402 | return pc; |
21d0e8a4 MK |
1403 | } |
1404 | ||
acd5c798 MK |
1405 | /* Check whether PC points at code that saves registers on the stack. |
1406 | If so, it updates CACHE and returns the address of the first | |
1407 | instruction after the register saves or CURRENT_PC, whichever is | |
1408 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1409 | |
1410 | static CORE_ADDR | |
acd5c798 MK |
1411 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1412 | struct i386_frame_cache *cache) | |
6bff26de | 1413 | { |
99ab4326 | 1414 | CORE_ADDR offset = 0; |
63c0089f | 1415 | gdb_byte op; |
99ab4326 | 1416 | int i; |
c0d1d883 | 1417 | |
99ab4326 MK |
1418 | if (cache->locals > 0) |
1419 | offset -= cache->locals; | |
1420 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1421 | { | |
3dcabaa8 MS |
1422 | if (target_read_memory (pc, &op, 1)) |
1423 | return pc; | |
99ab4326 MK |
1424 | if (op < 0x50 || op > 0x57) |
1425 | break; | |
0d17c81d | 1426 | |
99ab4326 MK |
1427 | offset -= 4; |
1428 | cache->saved_regs[op - 0x50] = offset; | |
1429 | cache->sp_offset += 4; | |
1430 | pc++; | |
6bff26de MK |
1431 | } |
1432 | ||
acd5c798 | 1433 | return pc; |
22797942 AC |
1434 | } |
1435 | ||
acd5c798 MK |
1436 | /* Do a full analysis of the prologue at PC and update CACHE |
1437 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1438 | address where the analysis stopped. | |
ed84f6c1 | 1439 | |
fc338970 MK |
1440 | We handle these cases: |
1441 | ||
1442 | The startup sequence can be at the start of the function, or the | |
1443 | function can start with a branch to startup code at the end. | |
1444 | ||
1445 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1446 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1447 | once used in the System V compiler). | |
1448 | ||
1449 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1450 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1451 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1452 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1453 | |
1454 | Next, the registers used by this function are pushed. With the | |
1455 | System V compiler they will always be in the order: %edi, %esi, | |
1456 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1457 | restore %eax); however, the code below is willing to see the pushes | |
1458 | in any order, and will handle up to 8 of them. | |
1459 | ||
1460 | If the setup sequence is at the end of the function, then the next | |
1461 | instruction will be a branch back to the start. */ | |
c906108c | 1462 | |
acd5c798 | 1463 | static CORE_ADDR |
e17a4113 UW |
1464 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1465 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1466 | struct i386_frame_cache *cache) |
c906108c | 1467 | { |
e11481da | 1468 | pc = i386_skip_noop (pc); |
e17a4113 | 1469 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1470 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1471 | pc = i386_skip_probe (pc); | |
92dd43fa | 1472 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1473 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1474 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1475 | } |
1476 | ||
fc338970 | 1477 | /* Return PC of first real instruction. */ |
c906108c | 1478 | |
3a1e71e3 | 1479 | static CORE_ADDR |
6093d2eb | 1480 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1481 | { |
e17a4113 UW |
1482 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1483 | ||
63c0089f | 1484 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1485 | { |
1486 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1487 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1488 | }; |
acd5c798 MK |
1489 | struct i386_frame_cache cache; |
1490 | CORE_ADDR pc; | |
63c0089f | 1491 | gdb_byte op; |
acd5c798 | 1492 | int i; |
c5aa993b | 1493 | |
acd5c798 | 1494 | cache.locals = -1; |
e17a4113 | 1495 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1496 | if (cache.locals < 0) |
1497 | return start_pc; | |
c5aa993b | 1498 | |
acd5c798 | 1499 | /* Found valid frame setup. */ |
c906108c | 1500 | |
fc338970 MK |
1501 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1502 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1503 | %ebx: |
1504 | ||
fc338970 MK |
1505 | call 0x0 |
1506 | popl %ebx | |
1507 | movl %ebx,x(%ebp) (optional) | |
1508 | addl y,%ebx | |
1509 | ||
c906108c SS |
1510 | This code is with the rest of the prologue (at the end of the |
1511 | function), so we have to skip it to get to the first real | |
1512 | instruction at the start of the function. */ | |
c5aa993b | 1513 | |
c906108c SS |
1514 | for (i = 0; i < 6; i++) |
1515 | { | |
3dcabaa8 MS |
1516 | if (target_read_memory (pc + i, &op, 1)) |
1517 | return pc; | |
1518 | ||
c5aa993b | 1519 | if (pic_pat[i] != op) |
c906108c SS |
1520 | break; |
1521 | } | |
1522 | if (i == 6) | |
1523 | { | |
acd5c798 MK |
1524 | int delta = 6; |
1525 | ||
3dcabaa8 MS |
1526 | if (target_read_memory (pc + delta, &op, 1)) |
1527 | return pc; | |
c906108c | 1528 | |
c5aa993b | 1529 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1530 | { |
e17a4113 | 1531 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1532 | |
fc338970 | 1533 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1534 | delta += 3; |
fc338970 | 1535 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1536 | delta += 6; |
fc338970 | 1537 | else /* Unexpected instruction. */ |
acd5c798 MK |
1538 | delta = 0; |
1539 | ||
3dcabaa8 MS |
1540 | if (target_read_memory (pc + delta, &op, 1)) |
1541 | return pc; | |
c906108c | 1542 | } |
acd5c798 | 1543 | |
c5aa993b | 1544 | /* addl y,%ebx */ |
acd5c798 | 1545 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1546 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1547 | == 0xc3) | |
c906108c | 1548 | { |
acd5c798 | 1549 | pc += delta + 6; |
c906108c SS |
1550 | } |
1551 | } | |
c5aa993b | 1552 | |
e63bbc88 MK |
1553 | /* If the function starts with a branch (to startup code at the end) |
1554 | the last instruction should bring us back to the first | |
1555 | instruction of the real code. */ | |
e17a4113 UW |
1556 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1557 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1558 | |
1559 | return pc; | |
c906108c SS |
1560 | } |
1561 | ||
4309257c PM |
1562 | /* Check that the code pointed to by PC corresponds to a call to |
1563 | __main, skip it if so. Return PC otherwise. */ | |
1564 | ||
1565 | CORE_ADDR | |
1566 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1567 | { | |
e17a4113 | 1568 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1569 | gdb_byte op; |
1570 | ||
3dcabaa8 MS |
1571 | if (target_read_memory (pc, &op, 1)) |
1572 | return pc; | |
4309257c PM |
1573 | if (op == 0xe8) |
1574 | { | |
1575 | gdb_byte buf[4]; | |
1576 | ||
1577 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1578 | { | |
1579 | /* Make sure address is computed correctly as a 32bit | |
1580 | integer even if CORE_ADDR is 64 bit wide. */ | |
1581 | struct minimal_symbol *s; | |
e17a4113 | 1582 | CORE_ADDR call_dest; |
4309257c | 1583 | |
e17a4113 | 1584 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1585 | call_dest = call_dest & 0xffffffffU; |
1586 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1587 | if (s != NULL | |
1588 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1589 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1590 | pc += 5; | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | return pc; | |
1595 | } | |
1596 | ||
acd5c798 | 1597 | /* This function is 64-bit safe. */ |
93924b6b | 1598 | |
acd5c798 MK |
1599 | static CORE_ADDR |
1600 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1601 | { |
63c0089f | 1602 | gdb_byte buf[8]; |
acd5c798 | 1603 | |
875f8d0e | 1604 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1605 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1606 | } |
acd5c798 | 1607 | \f |
93924b6b | 1608 | |
acd5c798 | 1609 | /* Normal frames. */ |
c5aa993b | 1610 | |
acd5c798 | 1611 | static struct i386_frame_cache * |
10458914 | 1612 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1613 | { |
e17a4113 UW |
1614 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1615 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1616 | struct i386_frame_cache *cache; |
63c0089f | 1617 | gdb_byte buf[4]; |
acd5c798 MK |
1618 | int i; |
1619 | ||
1620 | if (*this_cache) | |
1621 | return *this_cache; | |
1622 | ||
fd13a04a | 1623 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1624 | *this_cache = cache; |
1625 | ||
1626 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1627 | which holds the base address for the current stack frame. | |
1628 | However, for functions that don't need it, the frame pointer is | |
1629 | optional. For these "frameless" functions the frame pointer is | |
1630 | actually the frame pointer of the calling frame. Signal | |
1631 | trampolines are just a special case of a "frameless" function. | |
1632 | They (usually) share their frame pointer with the frame that was | |
1633 | in progress when the signal occurred. */ | |
1634 | ||
10458914 | 1635 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1636 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 MK |
1637 | if (cache->base == 0) |
1638 | return cache; | |
1639 | ||
1640 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1641 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1642 | |
10458914 | 1643 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1644 | if (cache->pc != 0) |
e17a4113 UW |
1645 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1646 | cache); | |
acd5c798 | 1647 | |
e0c62198 | 1648 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1649 | { |
e0c62198 L |
1650 | /* Saved stack pointer has been saved. */ |
1651 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
e17a4113 | 1652 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
92dd43fa MK |
1653 | } |
1654 | ||
acd5c798 MK |
1655 | if (cache->locals < 0) |
1656 | { | |
1657 | /* We didn't find a valid frame, which means that CACHE->base | |
1658 | currently holds the frame pointer for our calling frame. If | |
1659 | we're at the start of a function, or somewhere half-way its | |
1660 | prologue, the function's frame probably hasn't been fully | |
1661 | setup yet. Try to reconstruct the base address for the stack | |
1662 | frame by looking at the stack pointer. For truly "frameless" | |
1663 | functions this might work too. */ | |
1664 | ||
e0c62198 | 1665 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1666 | { |
1667 | /* We're halfway aligning the stack. */ | |
1668 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1669 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1670 | ||
1671 | /* This will be added back below. */ | |
1672 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1673 | } | |
7618e12b DJ |
1674 | else if (cache->pc != 0 |
1675 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1676 | { |
7618e12b DJ |
1677 | /* We're in a known function, but did not find a frame |
1678 | setup. Assume that the function does not use %ebp. | |
1679 | Alternatively, we may have jumped to an invalid | |
1680 | address; in that case there is definitely no new | |
1681 | frame in %ebp. */ | |
10458914 | 1682 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1683 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1684 | + cache->sp_offset; | |
92dd43fa | 1685 | } |
7618e12b DJ |
1686 | else |
1687 | /* We're in an unknown function. We could not find the start | |
1688 | of the function to analyze the prologue; our best option is | |
1689 | to assume a typical frame layout with the caller's %ebp | |
1690 | saved. */ | |
1691 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1692 | } |
1693 | ||
1694 | /* Now that we have the base address for the stack frame we can | |
1695 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1696 | if (cache->saved_sp == 0) |
1697 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1698 | |
acd5c798 MK |
1699 | /* Adjust all the saved registers such that they contain addresses |
1700 | instead of offsets. */ | |
1701 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1702 | if (cache->saved_regs[i] != -1) |
1703 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1704 | |
1705 | return cache; | |
a7769679 MK |
1706 | } |
1707 | ||
3a1e71e3 | 1708 | static void |
10458914 | 1709 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1710 | struct frame_id *this_id) |
c906108c | 1711 | { |
10458914 | 1712 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1713 | |
1714 | /* This marks the outermost frame. */ | |
1715 | if (cache->base == 0) | |
1716 | return; | |
1717 | ||
3e210248 | 1718 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1719 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1720 | } | |
1721 | ||
10458914 DJ |
1722 | static struct value * |
1723 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1724 | int regnum) | |
acd5c798 | 1725 | { |
10458914 | 1726 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1727 | |
1728 | gdb_assert (regnum >= 0); | |
1729 | ||
1730 | /* The System V ABI says that: | |
1731 | ||
1732 | "The flags register contains the system flags, such as the | |
1733 | direction flag and the carry flag. The direction flag must be | |
1734 | set to the forward (that is, zero) direction before entry and | |
1735 | upon exit from a function. Other user flags have no specified | |
1736 | role in the standard calling sequence and are not preserved." | |
1737 | ||
1738 | To guarantee the "upon exit" part of that statement we fake a | |
1739 | saved flags register that has its direction flag cleared. | |
1740 | ||
1741 | Note that GCC doesn't seem to rely on the fact that the direction | |
1742 | flag is cleared after a function return; it always explicitly | |
1743 | clears the flag before operations where it matters. | |
1744 | ||
1745 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1746 | right thing to do. The way we fake the flags register here makes | |
1747 | it impossible to change it. */ | |
1748 | ||
1749 | if (regnum == I386_EFLAGS_REGNUM) | |
1750 | { | |
10458914 | 1751 | ULONGEST val; |
c5aa993b | 1752 | |
10458914 DJ |
1753 | val = get_frame_register_unsigned (this_frame, regnum); |
1754 | val &= ~(1 << 10); | |
1755 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1756 | } |
1211c4e4 | 1757 | |
acd5c798 | 1758 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1759 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1760 | |
1761 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1762 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1763 | |
fd13a04a | 1764 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1765 | return frame_unwind_got_memory (this_frame, regnum, |
1766 | cache->saved_regs[regnum]); | |
fd13a04a | 1767 | |
10458914 | 1768 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1769 | } |
1770 | ||
1771 | static const struct frame_unwind i386_frame_unwind = | |
1772 | { | |
1773 | NORMAL_FRAME, | |
1774 | i386_frame_this_id, | |
10458914 DJ |
1775 | i386_frame_prev_register, |
1776 | NULL, | |
1777 | default_frame_sniffer | |
acd5c798 | 1778 | }; |
06da04c6 MS |
1779 | |
1780 | /* Normal frames, but in a function epilogue. */ | |
1781 | ||
1782 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1783 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1784 | the function's stack frame. */ | |
1785 | ||
1786 | static int | |
1787 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1788 | { | |
1789 | gdb_byte insn; | |
1790 | ||
1791 | if (target_read_memory (pc, &insn, 1)) | |
1792 | return 0; /* Can't read memory at pc. */ | |
1793 | ||
1794 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1795 | return 0; | |
1796 | ||
1797 | return 1; | |
1798 | } | |
1799 | ||
1800 | static int | |
1801 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1802 | struct frame_info *this_frame, | |
1803 | void **this_prologue_cache) | |
1804 | { | |
1805 | if (frame_relative_level (this_frame) == 0) | |
1806 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1807 | get_frame_pc (this_frame)); | |
1808 | else | |
1809 | return 0; | |
1810 | } | |
1811 | ||
1812 | static struct i386_frame_cache * | |
1813 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1814 | { | |
1815 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1816 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1817 | struct i386_frame_cache *cache; | |
1818 | gdb_byte buf[4]; | |
1819 | ||
1820 | if (*this_cache) | |
1821 | return *this_cache; | |
1822 | ||
1823 | cache = i386_alloc_frame_cache (); | |
1824 | *this_cache = cache; | |
1825 | ||
1826 | /* Cache base will be %esp plus cache->sp_offset (-4). */ | |
1827 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); | |
1828 | cache->base = extract_unsigned_integer (buf, 4, | |
1829 | byte_order) + cache->sp_offset; | |
1830 | ||
1831 | /* Cache pc will be the frame func. */ | |
1832 | cache->pc = get_frame_pc (this_frame); | |
1833 | ||
1834 | /* The saved %esp will be at cache->base plus 8. */ | |
1835 | cache->saved_sp = cache->base + 8; | |
1836 | ||
1837 | /* The saved %eip will be at cache->base plus 4. */ | |
1838 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; | |
1839 | ||
1840 | return cache; | |
1841 | } | |
1842 | ||
1843 | static void | |
1844 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1845 | void **this_cache, | |
1846 | struct frame_id *this_id) | |
1847 | { | |
1848 | struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, | |
1849 | this_cache); | |
1850 | ||
1851 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
1852 | } | |
1853 | ||
1854 | static const struct frame_unwind i386_epilogue_frame_unwind = | |
1855 | { | |
1856 | NORMAL_FRAME, | |
1857 | i386_epilogue_frame_this_id, | |
1858 | i386_frame_prev_register, | |
1859 | NULL, | |
1860 | i386_epilogue_frame_sniffer | |
1861 | }; | |
acd5c798 MK |
1862 | \f |
1863 | ||
1864 | /* Signal trampolines. */ | |
1865 | ||
1866 | static struct i386_frame_cache * | |
10458914 | 1867 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1868 | { |
e17a4113 UW |
1869 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1870 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1871 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1872 | struct i386_frame_cache *cache; |
acd5c798 | 1873 | CORE_ADDR addr; |
63c0089f | 1874 | gdb_byte buf[4]; |
acd5c798 MK |
1875 | |
1876 | if (*this_cache) | |
1877 | return *this_cache; | |
1878 | ||
fd13a04a | 1879 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1880 | |
10458914 | 1881 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1882 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
acd5c798 | 1883 | |
10458914 | 1884 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1885 | if (tdep->sc_reg_offset) |
1886 | { | |
1887 | int i; | |
1888 | ||
1889 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1890 | ||
1891 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1892 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1893 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1894 | } |
1895 | else | |
1896 | { | |
fd13a04a AC |
1897 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1898 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1899 | } |
acd5c798 MK |
1900 | |
1901 | *this_cache = cache; | |
1902 | return cache; | |
1903 | } | |
1904 | ||
1905 | static void | |
10458914 | 1906 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1907 | struct frame_id *this_id) |
1908 | { | |
1909 | struct i386_frame_cache *cache = | |
10458914 | 1910 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1911 | |
3e210248 | 1912 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1913 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1914 | } |
1915 | ||
10458914 DJ |
1916 | static struct value * |
1917 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1918 | void **this_cache, int regnum) | |
acd5c798 MK |
1919 | { |
1920 | /* Make sure we've initialized the cache. */ | |
10458914 | 1921 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1922 | |
10458914 | 1923 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1924 | } |
c0d1d883 | 1925 | |
10458914 DJ |
1926 | static int |
1927 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1928 | struct frame_info *this_frame, | |
1929 | void **this_prologue_cache) | |
acd5c798 | 1930 | { |
10458914 | 1931 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1932 | |
911bc6ee MK |
1933 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1934 | handler. */ | |
1935 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1936 | return 0; |
1c3545ae | 1937 | |
911bc6ee MK |
1938 | if (tdep->sigtramp_p != NULL) |
1939 | { | |
10458914 DJ |
1940 | if (tdep->sigtramp_p (this_frame)) |
1941 | return 1; | |
911bc6ee MK |
1942 | } |
1943 | ||
1944 | if (tdep->sigtramp_start != 0) | |
1945 | { | |
10458914 | 1946 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1947 | |
1948 | gdb_assert (tdep->sigtramp_end != 0); | |
1949 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1950 | return 1; |
911bc6ee | 1951 | } |
acd5c798 | 1952 | |
10458914 | 1953 | return 0; |
acd5c798 | 1954 | } |
10458914 DJ |
1955 | |
1956 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1957 | { | |
1958 | SIGTRAMP_FRAME, | |
1959 | i386_sigtramp_frame_this_id, | |
1960 | i386_sigtramp_frame_prev_register, | |
1961 | NULL, | |
1962 | i386_sigtramp_frame_sniffer | |
1963 | }; | |
acd5c798 MK |
1964 | \f |
1965 | ||
1966 | static CORE_ADDR | |
10458914 | 1967 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1968 | { |
10458914 | 1969 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1970 | |
1971 | return cache->base; | |
1972 | } | |
1973 | ||
1974 | static const struct frame_base i386_frame_base = | |
1975 | { | |
1976 | &i386_frame_unwind, | |
1977 | i386_frame_base_address, | |
1978 | i386_frame_base_address, | |
1979 | i386_frame_base_address | |
1980 | }; | |
1981 | ||
acd5c798 | 1982 | static struct frame_id |
10458914 | 1983 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1984 | { |
acd5c798 MK |
1985 | CORE_ADDR fp; |
1986 | ||
10458914 | 1987 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1988 | |
3e210248 | 1989 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1990 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1991 | } |
fc338970 | 1992 | \f |
c906108c | 1993 | |
fc338970 MK |
1994 | /* Figure out where the longjmp will land. Slurp the args out of the |
1995 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1996 | structure from which we extract the address that we will land at. |
28bcfd30 | 1997 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1998 | success. */ |
c906108c | 1999 | |
8201327c | 2000 | static int |
60ade65d | 2001 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2002 | { |
436675d3 | 2003 | gdb_byte buf[4]; |
c906108c | 2004 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2005 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2006 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2007 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2008 | |
8201327c MK |
2009 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2010 | longjmp will land. */ | |
2011 | if (jb_pc_offset == -1) | |
c906108c SS |
2012 | return 0; |
2013 | ||
436675d3 | 2014 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2015 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2016 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2017 | return 0; |
2018 | ||
e17a4113 | 2019 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2020 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2021 | return 0; |
c906108c | 2022 | |
e17a4113 | 2023 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2024 | return 1; |
2025 | } | |
fc338970 | 2026 | \f |
c906108c | 2027 | |
7ccc1c74 JM |
2028 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2029 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2030 | unions containing such types must be 16-byte-aligned; other | |
2031 | arguments are 4-byte-aligned. */ | |
2032 | ||
2033 | static int | |
2034 | i386_16_byte_align_p (struct type *type) | |
2035 | { | |
2036 | type = check_typedef (type); | |
2037 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2038 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2039 | && TYPE_LENGTH (type) == 16) | |
2040 | return 1; | |
2041 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2042 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2043 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2044 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2045 | { | |
2046 | int i; | |
2047 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2048 | { | |
2049 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2050 | return 1; | |
2051 | } | |
2052 | } | |
2053 | return 0; | |
2054 | } | |
2055 | ||
3a1e71e3 | 2056 | static CORE_ADDR |
7d9b040b | 2057 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2058 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2059 | struct value **args, CORE_ADDR sp, int struct_return, | |
2060 | CORE_ADDR struct_addr) | |
22f8ba57 | 2061 | { |
e17a4113 | 2062 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2063 | gdb_byte buf[4]; |
acd5c798 | 2064 | int i; |
7ccc1c74 JM |
2065 | int write_pass; |
2066 | int args_space = 0; | |
acd5c798 | 2067 | |
7ccc1c74 JM |
2068 | /* Determine the total space required for arguments and struct |
2069 | return address in a first pass (allowing for 16-byte-aligned | |
2070 | arguments), then push arguments in a second pass. */ | |
2071 | ||
2072 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2073 | { |
7ccc1c74 JM |
2074 | int args_space_used = 0; |
2075 | int have_16_byte_aligned_arg = 0; | |
2076 | ||
2077 | if (struct_return) | |
2078 | { | |
2079 | if (write_pass) | |
2080 | { | |
2081 | /* Push value address. */ | |
e17a4113 | 2082 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2083 | write_memory (sp, buf, 4); |
2084 | args_space_used += 4; | |
2085 | } | |
2086 | else | |
2087 | args_space += 4; | |
2088 | } | |
2089 | ||
2090 | for (i = 0; i < nargs; i++) | |
2091 | { | |
2092 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2093 | |
7ccc1c74 JM |
2094 | if (write_pass) |
2095 | { | |
2096 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2097 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2098 | |
7ccc1c74 JM |
2099 | write_memory (sp + args_space_used, |
2100 | value_contents_all (args[i]), len); | |
2101 | /* The System V ABI says that: | |
acd5c798 | 2102 | |
7ccc1c74 JM |
2103 | "An argument's size is increased, if necessary, to make it a |
2104 | multiple of [32-bit] words. This may require tail padding, | |
2105 | depending on the size of the argument." | |
22f8ba57 | 2106 | |
7ccc1c74 JM |
2107 | This makes sure the stack stays word-aligned. */ |
2108 | args_space_used += align_up (len, 4); | |
2109 | } | |
2110 | else | |
2111 | { | |
2112 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2113 | { | |
2114 | args_space = align_up (args_space, 16); | |
2115 | have_16_byte_aligned_arg = 1; | |
2116 | } | |
2117 | args_space += align_up (len, 4); | |
2118 | } | |
2119 | } | |
2120 | ||
2121 | if (!write_pass) | |
2122 | { | |
2123 | if (have_16_byte_aligned_arg) | |
2124 | args_space = align_up (args_space, 16); | |
2125 | sp -= args_space; | |
2126 | } | |
22f8ba57 MK |
2127 | } |
2128 | ||
acd5c798 MK |
2129 | /* Store return address. */ |
2130 | sp -= 4; | |
e17a4113 | 2131 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2132 | write_memory (sp, buf, 4); |
2133 | ||
2134 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2135 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2136 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2137 | ||
2138 | /* ...and fake a frame pointer. */ | |
2139 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2140 | ||
3e210248 AC |
2141 | /* MarkK wrote: This "+ 8" is all over the place: |
2142 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2143 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2144 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2145 | definition of the stack address of a frame. Otherwise frame id |
2146 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2147 | stack address *before* the function call as a frame's CFA. On |
2148 | the i386, when %ebp is used as a frame pointer, the offset | |
2149 | between the contents %ebp and the CFA as defined by GCC. */ | |
2150 | return sp + 8; | |
22f8ba57 MK |
2151 | } |
2152 | ||
1a309862 MK |
2153 | /* These registers are used for returning integers (and on some |
2154 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2155 | size and alignment match an integer type). */ |
acd5c798 MK |
2156 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2157 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2158 | |
c5e656c1 MK |
2159 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2160 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2161 | |
3a1e71e3 | 2162 | static void |
c5e656c1 | 2163 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2164 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2165 | { |
c5e656c1 | 2166 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2167 | int len = TYPE_LENGTH (type); |
63c0089f | 2168 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2169 | |
1e8d0a7b | 2170 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2171 | { |
5716833c | 2172 | if (tdep->st0_regnum < 0) |
1a309862 | 2173 | { |
8a3fe4f8 | 2174 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2175 | memset (valbuf, 0, len); |
ef9dff19 | 2176 | return; |
1a309862 MK |
2177 | } |
2178 | ||
c6ba6f0d MK |
2179 | /* Floating-point return values can be found in %st(0). Convert |
2180 | its contents to the desired type. This is probably not | |
2181 | exactly how it would happen on the target itself, but it is | |
2182 | the best we can do. */ | |
acd5c798 | 2183 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2184 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2185 | } |
2186 | else | |
c5aa993b | 2187 | { |
875f8d0e UW |
2188 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2189 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2190 | |
2191 | if (len <= low_size) | |
00f8375e | 2192 | { |
0818c12a | 2193 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2194 | memcpy (valbuf, buf, len); |
2195 | } | |
d4f3574e SS |
2196 | else if (len <= (low_size + high_size)) |
2197 | { | |
0818c12a | 2198 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2199 | memcpy (valbuf, buf, low_size); |
0818c12a | 2200 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2201 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2202 | } |
2203 | else | |
8e65ff28 | 2204 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2205 | _("Cannot extract return value of %d bytes long."), |
2206 | len); | |
c906108c SS |
2207 | } |
2208 | } | |
2209 | ||
c5e656c1 MK |
2210 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2211 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2212 | |
3a1e71e3 | 2213 | static void |
c5e656c1 | 2214 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2215 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2216 | { |
c5e656c1 | 2217 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2218 | int len = TYPE_LENGTH (type); |
2219 | ||
1e8d0a7b | 2220 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2221 | { |
3d7f4f49 | 2222 | ULONGEST fstat; |
63c0089f | 2223 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2224 | |
5716833c | 2225 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2226 | { |
8a3fe4f8 | 2227 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2228 | return; |
2229 | } | |
2230 | ||
635b0cc1 MK |
2231 | /* Returning floating-point values is a bit tricky. Apart from |
2232 | storing the return value in %st(0), we have to simulate the | |
2233 | state of the FPU at function return point. */ | |
2234 | ||
c6ba6f0d MK |
2235 | /* Convert the value found in VALBUF to the extended |
2236 | floating-point format used by the FPU. This is probably | |
2237 | not exactly how it would happen on the target itself, but | |
2238 | it is the best we can do. */ | |
27067745 | 2239 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2240 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2241 | |
635b0cc1 MK |
2242 | /* Set the top of the floating-point register stack to 7. The |
2243 | actual value doesn't really matter, but 7 is what a normal | |
2244 | function return would end up with if the program started out | |
2245 | with a freshly initialized FPU. */ | |
20a6ec49 | 2246 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2247 | fstat |= (7 << 11); |
20a6ec49 | 2248 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2249 | |
635b0cc1 MK |
2250 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2251 | the floating-point register stack to 7, the appropriate value | |
2252 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2253 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2254 | } |
2255 | else | |
2256 | { | |
875f8d0e UW |
2257 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2258 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2259 | |
2260 | if (len <= low_size) | |
3d7f4f49 | 2261 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2262 | else if (len <= (low_size + high_size)) |
2263 | { | |
3d7f4f49 MK |
2264 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2265 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2266 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2267 | } |
2268 | else | |
8e65ff28 | 2269 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2270 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2271 | } |
2272 | } | |
fc338970 | 2273 | \f |
ef9dff19 | 2274 | |
8201327c MK |
2275 | /* This is the variable that is set with "set struct-convention", and |
2276 | its legitimate values. */ | |
2277 | static const char default_struct_convention[] = "default"; | |
2278 | static const char pcc_struct_convention[] = "pcc"; | |
2279 | static const char reg_struct_convention[] = "reg"; | |
2280 | static const char *valid_conventions[] = | |
2281 | { | |
2282 | default_struct_convention, | |
2283 | pcc_struct_convention, | |
2284 | reg_struct_convention, | |
2285 | NULL | |
2286 | }; | |
2287 | static const char *struct_convention = default_struct_convention; | |
2288 | ||
0e4377e1 JB |
2289 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2290 | a union type, or an array type, should be returned in registers | |
2291 | for architecture GDBARCH. */ | |
c5e656c1 | 2292 | |
8201327c | 2293 | static int |
c5e656c1 | 2294 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2295 | { |
c5e656c1 MK |
2296 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2297 | enum type_code code = TYPE_CODE (type); | |
2298 | int len = TYPE_LENGTH (type); | |
8201327c | 2299 | |
0e4377e1 JB |
2300 | gdb_assert (code == TYPE_CODE_STRUCT |
2301 | || code == TYPE_CODE_UNION | |
2302 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2303 | |
2304 | if (struct_convention == pcc_struct_convention | |
2305 | || (struct_convention == default_struct_convention | |
2306 | && tdep->struct_return == pcc_struct_return)) | |
2307 | return 0; | |
2308 | ||
9edde48e MK |
2309 | /* Structures consisting of a single `float', `double' or 'long |
2310 | double' member are returned in %st(0). */ | |
2311 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2312 | { | |
2313 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2314 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2315 | return (len == 4 || len == 8 || len == 12); | |
2316 | } | |
2317 | ||
c5e656c1 MK |
2318 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2319 | } | |
2320 | ||
2321 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2322 | should be returned. If it is supposed to be returned in registers, | |
2323 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2324 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2325 | from WRITEBUF into REGCACHE. */ | |
2326 | ||
2327 | static enum return_value_convention | |
c055b101 CV |
2328 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2329 | struct type *type, struct regcache *regcache, | |
2330 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2331 | { |
2332 | enum type_code code = TYPE_CODE (type); | |
2333 | ||
5daa78cc TJB |
2334 | if (((code == TYPE_CODE_STRUCT |
2335 | || code == TYPE_CODE_UNION | |
2336 | || code == TYPE_CODE_ARRAY) | |
2337 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2338 | /* 128-bit decimal float uses the struct return convention. */ | |
2339 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2340 | { |
2341 | /* The System V ABI says that: | |
2342 | ||
2343 | "A function that returns a structure or union also sets %eax | |
2344 | to the value of the original address of the caller's area | |
2345 | before it returns. Thus when the caller receives control | |
2346 | again, the address of the returned object resides in register | |
2347 | %eax and can be used to access the object." | |
2348 | ||
2349 | So the ABI guarantees that we can always find the return | |
2350 | value just after the function has returned. */ | |
2351 | ||
0e4377e1 JB |
2352 | /* Note that the ABI doesn't mention functions returning arrays, |
2353 | which is something possible in certain languages such as Ada. | |
2354 | In this case, the value is returned as if it was wrapped in | |
2355 | a record, so the convention applied to records also applies | |
2356 | to arrays. */ | |
2357 | ||
31db7b6c MK |
2358 | if (readbuf) |
2359 | { | |
2360 | ULONGEST addr; | |
2361 | ||
2362 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2363 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2364 | } | |
2365 | ||
2366 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2367 | } | |
c5e656c1 MK |
2368 | |
2369 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2370 | `float', `double' or 'long double' member. These structures are |
2371 | returned in %st(0). For these structures, we call ourselves | |
2372 | recursively, changing TYPE into the type of the first member of | |
2373 | the structure. Since that should work for all structures that | |
2374 | have only one member, we don't bother to check the member's type | |
2375 | here. */ | |
c5e656c1 MK |
2376 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2377 | { | |
2378 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2379 | return i386_return_value (gdbarch, func_type, type, regcache, |
2380 | readbuf, writebuf); | |
c5e656c1 MK |
2381 | } |
2382 | ||
2383 | if (readbuf) | |
2384 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2385 | if (writebuf) | |
2386 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2387 | |
c5e656c1 | 2388 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2389 | } |
2390 | \f | |
2391 | ||
27067745 UW |
2392 | struct type * |
2393 | i387_ext_type (struct gdbarch *gdbarch) | |
2394 | { | |
2395 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2396 | ||
2397 | if (!tdep->i387_ext_type) | |
90884b2b L |
2398 | { |
2399 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2400 | gdb_assert (tdep->i387_ext_type != NULL); | |
2401 | } | |
27067745 UW |
2402 | |
2403 | return tdep->i387_ext_type; | |
2404 | } | |
2405 | ||
c131fcee L |
2406 | /* Construct vector type for pseudo YMM registers. We can't use |
2407 | tdesc_find_type since YMM isn't described in target description. */ | |
2408 | ||
2409 | static struct type * | |
2410 | i386_ymm_type (struct gdbarch *gdbarch) | |
2411 | { | |
2412 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2413 | ||
2414 | if (!tdep->i386_ymm_type) | |
2415 | { | |
2416 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2417 | ||
2418 | /* The type we're building is this: */ | |
2419 | #if 0 | |
2420 | union __gdb_builtin_type_vec256i | |
2421 | { | |
2422 | int128_t uint128[2]; | |
2423 | int64_t v2_int64[4]; | |
2424 | int32_t v4_int32[8]; | |
2425 | int16_t v8_int16[16]; | |
2426 | int8_t v16_int8[32]; | |
2427 | double v2_double[4]; | |
2428 | float v4_float[8]; | |
2429 | }; | |
2430 | #endif | |
2431 | ||
2432 | struct type *t; | |
2433 | ||
2434 | t = arch_composite_type (gdbarch, | |
2435 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2436 | append_composite_type_field (t, "v8_float", | |
2437 | init_vector_type (bt->builtin_float, 8)); | |
2438 | append_composite_type_field (t, "v4_double", | |
2439 | init_vector_type (bt->builtin_double, 4)); | |
2440 | append_composite_type_field (t, "v32_int8", | |
2441 | init_vector_type (bt->builtin_int8, 32)); | |
2442 | append_composite_type_field (t, "v16_int16", | |
2443 | init_vector_type (bt->builtin_int16, 16)); | |
2444 | append_composite_type_field (t, "v8_int32", | |
2445 | init_vector_type (bt->builtin_int32, 8)); | |
2446 | append_composite_type_field (t, "v4_int64", | |
2447 | init_vector_type (bt->builtin_int64, 4)); | |
2448 | append_composite_type_field (t, "v2_int128", | |
2449 | init_vector_type (bt->builtin_int128, 2)); | |
2450 | ||
2451 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 2452 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
2453 | tdep->i386_ymm_type = t; |
2454 | } | |
2455 | ||
2456 | return tdep->i386_ymm_type; | |
2457 | } | |
2458 | ||
794ac428 | 2459 | /* Construct vector type for MMX registers. */ |
90884b2b | 2460 | static struct type * |
794ac428 UW |
2461 | i386_mmx_type (struct gdbarch *gdbarch) |
2462 | { | |
2463 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2464 | ||
2465 | if (!tdep->i386_mmx_type) | |
2466 | { | |
df4df182 UW |
2467 | const struct builtin_type *bt = builtin_type (gdbarch); |
2468 | ||
794ac428 UW |
2469 | /* The type we're building is this: */ |
2470 | #if 0 | |
2471 | union __gdb_builtin_type_vec64i | |
2472 | { | |
2473 | int64_t uint64; | |
2474 | int32_t v2_int32[2]; | |
2475 | int16_t v4_int16[4]; | |
2476 | int8_t v8_int8[8]; | |
2477 | }; | |
2478 | #endif | |
2479 | ||
2480 | struct type *t; | |
2481 | ||
e9bb382b UW |
2482 | t = arch_composite_type (gdbarch, |
2483 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2484 | |
2485 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2486 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2487 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2488 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2489 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2490 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2491 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2492 | |
876cecd0 | 2493 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2494 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2495 | tdep->i386_mmx_type = t; | |
2496 | } | |
2497 | ||
2498 | return tdep->i386_mmx_type; | |
2499 | } | |
2500 | ||
d7a0d72c | 2501 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 2502 | register REGNUM. */ |
d7a0d72c | 2503 | |
3a1e71e3 | 2504 | static struct type * |
90884b2b | 2505 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2506 | { |
1ba53b71 L |
2507 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2508 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2509 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2510 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2511 | else |
2512 | { | |
2513 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2514 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2515 | return bt->builtin_int8; | |
2516 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2517 | return bt->builtin_int16; | |
2518 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2519 | return bt->builtin_int32; | |
2520 | } | |
2521 | ||
2522 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2523 | } |
2524 | ||
28fc6740 | 2525 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2526 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2527 | |
2528 | static int | |
c86c27af | 2529 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2530 | { |
5716833c MK |
2531 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2532 | int mmxreg, fpreg; | |
28fc6740 AC |
2533 | ULONGEST fstat; |
2534 | int tos; | |
c86c27af | 2535 | |
5716833c | 2536 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2537 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2538 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2539 | fpreg = (mmxreg + tos) % 8; |
2540 | ||
20a6ec49 | 2541 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2542 | } |
2543 | ||
1ba53b71 | 2544 | void |
28fc6740 | 2545 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2546 | int regnum, gdb_byte *buf) |
28fc6740 | 2547 | { |
1ba53b71 L |
2548 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2549 | ||
5716833c | 2550 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2551 | { |
c86c27af MK |
2552 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2553 | ||
28fc6740 | 2554 | /* Extract (always little endian). */ |
1ba53b71 L |
2555 | regcache_raw_read (regcache, fpnum, raw_buf); |
2556 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2557 | } |
2558 | else | |
1ba53b71 L |
2559 | { |
2560 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2561 | ||
c131fcee L |
2562 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2563 | { | |
2564 | regnum -= tdep->ymm0_regnum; | |
2565 | ||
1777feb0 | 2566 | /* Extract (always little endian). Read lower 128bits. */ |
c131fcee L |
2567 | regcache_raw_read (regcache, |
2568 | I387_XMM0_REGNUM (tdep) + regnum, | |
2569 | raw_buf); | |
2570 | memcpy (buf, raw_buf, 16); | |
2571 | /* Read upper 128bits. */ | |
2572 | regcache_raw_read (regcache, | |
2573 | tdep->ymm0h_regnum + regnum, | |
2574 | raw_buf); | |
2575 | memcpy (buf + 16, raw_buf, 16); | |
2576 | } | |
2577 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2578 | { |
2579 | int gpnum = regnum - tdep->ax_regnum; | |
2580 | ||
2581 | /* Extract (always little endian). */ | |
2582 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2583 | memcpy (buf, raw_buf, 2); | |
2584 | } | |
2585 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2586 | { | |
2587 | /* Check byte pseudo registers last since this function will | |
2588 | be called from amd64_pseudo_register_read, which handles | |
2589 | byte pseudo registers differently. */ | |
2590 | int gpnum = regnum - tdep->al_regnum; | |
2591 | ||
2592 | /* Extract (always little endian). We read both lower and | |
2593 | upper registers. */ | |
2594 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2595 | if (gpnum >= 4) | |
2596 | memcpy (buf, raw_buf + 1, 1); | |
2597 | else | |
2598 | memcpy (buf, raw_buf, 1); | |
2599 | } | |
2600 | else | |
2601 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2602 | } | |
28fc6740 AC |
2603 | } |
2604 | ||
1ba53b71 | 2605 | void |
28fc6740 | 2606 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2607 | int regnum, const gdb_byte *buf) |
28fc6740 | 2608 | { |
1ba53b71 L |
2609 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2610 | ||
5716833c | 2611 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2612 | { |
c86c27af MK |
2613 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2614 | ||
28fc6740 | 2615 | /* Read ... */ |
1ba53b71 | 2616 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2617 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2618 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2619 | /* ... Write. */ |
1ba53b71 | 2620 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2621 | } |
2622 | else | |
1ba53b71 L |
2623 | { |
2624 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2625 | ||
c131fcee L |
2626 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2627 | { | |
2628 | regnum -= tdep->ymm0_regnum; | |
2629 | ||
2630 | /* ... Write lower 128bits. */ | |
2631 | regcache_raw_write (regcache, | |
2632 | I387_XMM0_REGNUM (tdep) + regnum, | |
2633 | buf); | |
2634 | /* ... Write upper 128bits. */ | |
2635 | regcache_raw_write (regcache, | |
2636 | tdep->ymm0h_regnum + regnum, | |
2637 | buf + 16); | |
2638 | } | |
2639 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2640 | { |
2641 | int gpnum = regnum - tdep->ax_regnum; | |
2642 | ||
2643 | /* Read ... */ | |
2644 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2645 | /* ... Modify ... (always little endian). */ | |
2646 | memcpy (raw_buf, buf, 2); | |
2647 | /* ... Write. */ | |
2648 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2649 | } | |
2650 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2651 | { | |
2652 | /* Check byte pseudo registers last since this function will | |
2653 | be called from amd64_pseudo_register_read, which handles | |
2654 | byte pseudo registers differently. */ | |
2655 | int gpnum = regnum - tdep->al_regnum; | |
2656 | ||
2657 | /* Read ... We read both lower and upper registers. */ | |
2658 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2659 | /* ... Modify ... (always little endian). */ | |
2660 | if (gpnum >= 4) | |
2661 | memcpy (raw_buf + 1, buf, 1); | |
2662 | else | |
2663 | memcpy (raw_buf, buf, 1); | |
2664 | /* ... Write. */ | |
2665 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
2666 | } | |
2667 | else | |
2668 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2669 | } | |
28fc6740 | 2670 | } |
ff2e87ac AC |
2671 | \f |
2672 | ||
ff2e87ac AC |
2673 | /* Return the register number of the register allocated by GCC after |
2674 | REGNUM, or -1 if there is no such register. */ | |
2675 | ||
2676 | static int | |
2677 | i386_next_regnum (int regnum) | |
2678 | { | |
2679 | /* GCC allocates the registers in the order: | |
2680 | ||
2681 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2682 | ||
2683 | Since storing a variable in %esp doesn't make any sense we return | |
2684 | -1 for %ebp and for %esp itself. */ | |
2685 | static int next_regnum[] = | |
2686 | { | |
2687 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2688 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2689 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2690 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2691 | -1, -1, /* Slots for %esp and %ebp. */ | |
2692 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2693 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2694 | }; | |
2695 | ||
de5b9bb9 | 2696 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2697 | return next_regnum[regnum]; |
28fc6740 | 2698 | |
ff2e87ac AC |
2699 | return -1; |
2700 | } | |
2701 | ||
2702 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2703 | needs any special handling. */ | |
d7a0d72c | 2704 | |
3a1e71e3 | 2705 | static int |
1777feb0 MS |
2706 | i386_convert_register_p (struct gdbarch *gdbarch, |
2707 | int regnum, struct type *type) | |
d7a0d72c | 2708 | { |
de5b9bb9 MK |
2709 | int len = TYPE_LENGTH (type); |
2710 | ||
ff2e87ac AC |
2711 | /* Values may be spread across multiple registers. Most debugging |
2712 | formats aren't expressive enough to specify the locations, so | |
2713 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2714 | have a length that is a multiple of the word size, since GCC |
2715 | doesn't seem to put any other types into registers. */ | |
2716 | if (len > 4 && len % 4 == 0) | |
2717 | { | |
2718 | int last_regnum = regnum; | |
2719 | ||
2720 | while (len > 4) | |
2721 | { | |
2722 | last_regnum = i386_next_regnum (last_regnum); | |
2723 | len -= 4; | |
2724 | } | |
2725 | ||
2726 | if (last_regnum != -1) | |
2727 | return 1; | |
2728 | } | |
ff2e87ac | 2729 | |
0abe36f5 | 2730 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2731 | } |
2732 | ||
ff2e87ac AC |
2733 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2734 | return its contents in TO. */ | |
ac27f131 | 2735 | |
3a1e71e3 | 2736 | static void |
ff2e87ac | 2737 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2738 | struct type *type, gdb_byte *to) |
ac27f131 | 2739 | { |
20a6ec49 | 2740 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2741 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2742 | |
ff2e87ac AC |
2743 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2744 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2745 | |
20a6ec49 | 2746 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2747 | { |
d532c08f MK |
2748 | i387_register_to_value (frame, regnum, type, to); |
2749 | return; | |
8d7f6b4a | 2750 | } |
ff2e87ac | 2751 | |
fd35795f | 2752 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2753 | |
2754 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2755 | |
de5b9bb9 MK |
2756 | while (len > 0) |
2757 | { | |
2758 | gdb_assert (regnum != -1); | |
20a6ec49 | 2759 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2760 | |
42835c2b | 2761 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2762 | regnum = i386_next_regnum (regnum); |
2763 | len -= 4; | |
42835c2b | 2764 | to += 4; |
de5b9bb9 | 2765 | } |
ac27f131 MK |
2766 | } |
2767 | ||
ff2e87ac AC |
2768 | /* Write the contents FROM of a value of type TYPE into register |
2769 | REGNUM in frame FRAME. */ | |
ac27f131 | 2770 | |
3a1e71e3 | 2771 | static void |
ff2e87ac | 2772 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2773 | struct type *type, const gdb_byte *from) |
ac27f131 | 2774 | { |
de5b9bb9 | 2775 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2776 | |
20a6ec49 | 2777 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2778 | { |
d532c08f MK |
2779 | i387_value_to_register (frame, regnum, type, from); |
2780 | return; | |
2781 | } | |
3d261580 | 2782 | |
fd35795f | 2783 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2784 | |
2785 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2786 | |
de5b9bb9 MK |
2787 | while (len > 0) |
2788 | { | |
2789 | gdb_assert (regnum != -1); | |
875f8d0e | 2790 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2791 | |
42835c2b | 2792 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2793 | regnum = i386_next_regnum (regnum); |
2794 | len -= 4; | |
42835c2b | 2795 | from += 4; |
de5b9bb9 | 2796 | } |
ac27f131 | 2797 | } |
ff2e87ac | 2798 | \f |
7fdafb5a MK |
2799 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2800 | in the general-purpose register set REGSET to register cache | |
2801 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2802 | |
20187ed5 | 2803 | void |
473f17b0 MK |
2804 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2805 | int regnum, const void *gregs, size_t len) | |
2806 | { | |
9ea75c57 | 2807 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2808 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2809 | int i; |
2810 | ||
2811 | gdb_assert (len == tdep->sizeof_gregset); | |
2812 | ||
2813 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2814 | { | |
2815 | if ((regnum == i || regnum == -1) | |
2816 | && tdep->gregset_reg_offset[i] != -1) | |
2817 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2818 | } | |
2819 | } | |
2820 | ||
7fdafb5a MK |
2821 | /* Collect register REGNUM from the register cache REGCACHE and store |
2822 | it in the buffer specified by GREGS and LEN as described by the | |
2823 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2824 | all registers in REGSET. */ | |
2825 | ||
2826 | void | |
2827 | i386_collect_gregset (const struct regset *regset, | |
2828 | const struct regcache *regcache, | |
2829 | int regnum, void *gregs, size_t len) | |
2830 | { | |
2831 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2832 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2833 | int i; |
2834 | ||
2835 | gdb_assert (len == tdep->sizeof_gregset); | |
2836 | ||
2837 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2838 | { | |
2839 | if ((regnum == i || regnum == -1) | |
2840 | && tdep->gregset_reg_offset[i] != -1) | |
2841 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2842 | } | |
2843 | } | |
2844 | ||
2845 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2846 | in the floating-point register set REGSET to register cache | |
2847 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2848 | |
2849 | static void | |
2850 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2851 | int regnum, const void *fpregs, size_t len) | |
2852 | { | |
9ea75c57 | 2853 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2854 | |
66a72d25 MK |
2855 | if (len == I387_SIZEOF_FXSAVE) |
2856 | { | |
2857 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2858 | return; | |
2859 | } | |
2860 | ||
473f17b0 MK |
2861 | gdb_assert (len == tdep->sizeof_fpregset); |
2862 | i387_supply_fsave (regcache, regnum, fpregs); | |
2863 | } | |
8446b36a | 2864 | |
2f305df1 MK |
2865 | /* Collect register REGNUM from the register cache REGCACHE and store |
2866 | it in the buffer specified by FPREGS and LEN as described by the | |
2867 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2868 | all registers in REGSET. */ | |
7fdafb5a MK |
2869 | |
2870 | static void | |
2871 | i386_collect_fpregset (const struct regset *regset, | |
2872 | const struct regcache *regcache, | |
2873 | int regnum, void *fpregs, size_t len) | |
2874 | { | |
2875 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2876 | ||
2877 | if (len == I387_SIZEOF_FXSAVE) | |
2878 | { | |
2879 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2880 | return; | |
2881 | } | |
2882 | ||
2883 | gdb_assert (len == tdep->sizeof_fpregset); | |
2884 | i387_collect_fsave (regcache, regnum, fpregs); | |
2885 | } | |
2886 | ||
c131fcee L |
2887 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
2888 | ||
2889 | static void | |
2890 | i386_supply_xstateregset (const struct regset *regset, | |
2891 | struct regcache *regcache, int regnum, | |
2892 | const void *xstateregs, size_t len) | |
2893 | { | |
c131fcee L |
2894 | i387_supply_xsave (regcache, regnum, xstateregs); |
2895 | } | |
2896 | ||
2897 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
2898 | ||
2899 | static void | |
2900 | i386_collect_xstateregset (const struct regset *regset, | |
2901 | const struct regcache *regcache, | |
2902 | int regnum, void *xstateregs, size_t len) | |
2903 | { | |
c131fcee L |
2904 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
2905 | } | |
2906 | ||
8446b36a MK |
2907 | /* Return the appropriate register set for the core section identified |
2908 | by SECT_NAME and SECT_SIZE. */ | |
2909 | ||
2910 | const struct regset * | |
2911 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2912 | const char *sect_name, size_t sect_size) | |
2913 | { | |
2914 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2915 | ||
2916 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2917 | { | |
2918 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2919 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2920 | i386_collect_gregset); | |
8446b36a MK |
2921 | return tdep->gregset; |
2922 | } | |
2923 | ||
66a72d25 MK |
2924 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2925 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2926 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2927 | { |
2928 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2929 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2930 | i386_collect_fpregset); | |
8446b36a MK |
2931 | return tdep->fpregset; |
2932 | } | |
2933 | ||
c131fcee L |
2934 | if (strcmp (sect_name, ".reg-xstate") == 0) |
2935 | { | |
2936 | if (tdep->xstateregset == NULL) | |
2937 | tdep->xstateregset = regset_alloc (gdbarch, | |
2938 | i386_supply_xstateregset, | |
2939 | i386_collect_xstateregset); | |
2940 | ||
2941 | return tdep->xstateregset; | |
2942 | } | |
2943 | ||
8446b36a MK |
2944 | return NULL; |
2945 | } | |
473f17b0 | 2946 | \f |
fc338970 | 2947 | |
fc338970 | 2948 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2949 | |
2950 | CORE_ADDR | |
e17a4113 UW |
2951 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
2952 | CORE_ADDR pc, char *name) | |
c906108c | 2953 | { |
e17a4113 UW |
2954 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2955 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2956 | ||
2957 | /* jmp *(dest) */ | |
2958 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 2959 | { |
e17a4113 UW |
2960 | unsigned long indirect = |
2961 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 2962 | struct minimal_symbol *indsym = |
fc338970 | 2963 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2964 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2965 | |
c5aa993b | 2966 | if (symname) |
c906108c | 2967 | { |
c5aa993b JM |
2968 | if (strncmp (symname, "__imp_", 6) == 0 |
2969 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
2970 | return name ? 1 : |
2971 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
2972 | } |
2973 | } | |
fc338970 | 2974 | return 0; /* Not a trampoline. */ |
c906108c | 2975 | } |
fc338970 MK |
2976 | \f |
2977 | ||
10458914 DJ |
2978 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2979 | routine. */ | |
8201327c | 2980 | |
4bd207ef | 2981 | int |
10458914 | 2982 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2983 | { |
10458914 | 2984 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2985 | char *name; |
2986 | ||
2987 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2988 | return (name && strcmp ("_sigtramp", name) == 0); |
2989 | } | |
2990 | \f | |
2991 | ||
fc338970 MK |
2992 | /* We have two flavours of disassembly. The machinery on this page |
2993 | deals with switching between those. */ | |
c906108c SS |
2994 | |
2995 | static int | |
a89aa300 | 2996 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2997 | { |
5e3397bb MK |
2998 | gdb_assert (disassembly_flavor == att_flavor |
2999 | || disassembly_flavor == intel_flavor); | |
3000 | ||
3001 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3002 | constified, cast to prevent a compiler warning. */ | |
3003 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3004 | |
3005 | return print_insn_i386 (pc, info); | |
7a292a7a | 3006 | } |
fc338970 | 3007 | \f |
3ce1502b | 3008 | |
8201327c MK |
3009 | /* There are a few i386 architecture variants that differ only |
3010 | slightly from the generic i386 target. For now, we don't give them | |
3011 | their own source file, but include them here. As a consequence, | |
3012 | they'll always be included. */ | |
3ce1502b | 3013 | |
8201327c | 3014 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3015 | |
10458914 DJ |
3016 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3017 | routine. */ | |
911bc6ee | 3018 | |
8201327c | 3019 | static int |
10458914 | 3020 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3021 | { |
10458914 | 3022 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
3023 | char *name; |
3024 | ||
acd5c798 MK |
3025 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
3026 | currently unknown. */ | |
911bc6ee | 3027 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
3028 | return (name && (strcmp ("_sigreturn", name) == 0 |
3029 | || strcmp ("_sigacthandler", name) == 0 | |
3030 | || strcmp ("sigvechandler", name) == 0)); | |
3031 | } | |
d2a7c97a | 3032 | |
10458914 DJ |
3033 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3034 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3035 | |
3a1e71e3 | 3036 | static CORE_ADDR |
10458914 | 3037 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3038 | { |
e17a4113 UW |
3039 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3040 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3041 | gdb_byte buf[4]; |
acd5c798 | 3042 | CORE_ADDR sp; |
3ce1502b | 3043 | |
10458914 | 3044 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3045 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3046 | |
e17a4113 | 3047 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
3048 | } |
3049 | \f | |
3ce1502b | 3050 | |
8201327c | 3051 | /* Generic ELF. */ |
d2a7c97a | 3052 | |
8201327c MK |
3053 | void |
3054 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3055 | { | |
c4fc7f1b MK |
3056 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
3057 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 3058 | } |
3ce1502b | 3059 | |
8201327c | 3060 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3061 | |
8201327c MK |
3062 | void |
3063 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3064 | { | |
3065 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 3066 | |
8201327c MK |
3067 | /* System V Release 4 uses ELF. */ |
3068 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 3069 | |
dfe01d39 | 3070 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
3071 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
3072 | ||
911bc6ee | 3073 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 3074 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3075 | tdep->sc_pc_offset = 36 + 14 * 4; |
3076 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3077 | |
8201327c | 3078 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3079 | } |
3080 | ||
8201327c | 3081 | /* DJGPP. */ |
3ce1502b | 3082 | |
3a1e71e3 | 3083 | static void |
8201327c | 3084 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3085 | { |
8201327c | 3086 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3087 | |
911bc6ee MK |
3088 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3089 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3090 | |
8201327c | 3091 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3092 | |
3093 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3094 | if (! tdesc_has_registers (info.target_desc)) |
3095 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3096 | |
3097 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3098 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3099 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3100 | set_gdbarch_sdb_reg_to_regnum. */ | |
3101 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3102 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3103 | |
3104 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3105 | } |
8201327c | 3106 | \f |
2acceee2 | 3107 | |
38c968cf AC |
3108 | /* i386 register groups. In addition to the normal groups, add "mmx" |
3109 | and "sse". */ | |
3110 | ||
3111 | static struct reggroup *i386_sse_reggroup; | |
3112 | static struct reggroup *i386_mmx_reggroup; | |
3113 | ||
3114 | static void | |
3115 | i386_init_reggroups (void) | |
3116 | { | |
3117 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
3118 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
3119 | } | |
3120 | ||
3121 | static void | |
3122 | i386_add_reggroups (struct gdbarch *gdbarch) | |
3123 | { | |
3124 | reggroup_add (gdbarch, i386_sse_reggroup); | |
3125 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
3126 | reggroup_add (gdbarch, general_reggroup); | |
3127 | reggroup_add (gdbarch, float_reggroup); | |
3128 | reggroup_add (gdbarch, all_reggroup); | |
3129 | reggroup_add (gdbarch, save_reggroup); | |
3130 | reggroup_add (gdbarch, restore_reggroup); | |
3131 | reggroup_add (gdbarch, vector_reggroup); | |
3132 | reggroup_add (gdbarch, system_reggroup); | |
3133 | } | |
3134 | ||
3135 | int | |
3136 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
3137 | struct reggroup *group) | |
3138 | { | |
c131fcee L |
3139 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3140 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
3141 | ymm_regnum_p, ymmh_regnum_p; | |
acd5c798 | 3142 | |
1ba53b71 L |
3143 | /* Don't include pseudo registers, except for MMX, in any register |
3144 | groups. */ | |
c131fcee | 3145 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3146 | return 0; |
3147 | ||
c131fcee | 3148 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3149 | return 0; |
3150 | ||
c131fcee | 3151 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3152 | return 0; |
3153 | ||
3154 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
3155 | if (group == i386_mmx_reggroup) |
3156 | return mmx_regnum_p; | |
1ba53b71 | 3157 | |
c131fcee L |
3158 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
3159 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 3160 | if (group == i386_sse_reggroup) |
c131fcee L |
3161 | return xmm_regnum_p || mxcsr_regnum_p; |
3162 | ||
3163 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 3164 | if (group == vector_reggroup) |
c131fcee L |
3165 | return (mmx_regnum_p |
3166 | || ymm_regnum_p | |
3167 | || mxcsr_regnum_p | |
3168 | || (xmm_regnum_p | |
3169 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
3170 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
3171 | |
3172 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
3173 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
3174 | if (group == float_reggroup) |
3175 | return fp_regnum_p; | |
1ba53b71 | 3176 | |
c131fcee L |
3177 | /* For "info reg all", don't include upper YMM registers nor XMM |
3178 | registers when AVX is supported. */ | |
3179 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
3180 | if (group == all_reggroup | |
3181 | && ((xmm_regnum_p | |
3182 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
3183 | || ymmh_regnum_p)) | |
3184 | return 0; | |
3185 | ||
38c968cf | 3186 | if (group == general_reggroup) |
1ba53b71 L |
3187 | return (!fp_regnum_p |
3188 | && !mmx_regnum_p | |
c131fcee L |
3189 | && !mxcsr_regnum_p |
3190 | && !xmm_regnum_p | |
3191 | && !ymm_regnum_p | |
3192 | && !ymmh_regnum_p); | |
acd5c798 | 3193 | |
38c968cf AC |
3194 | return default_register_reggroup_p (gdbarch, regnum, group); |
3195 | } | |
38c968cf | 3196 | \f |
acd5c798 | 3197 | |
f837910f MK |
3198 | /* Get the ARGIth function argument for the current function. */ |
3199 | ||
42c466d7 | 3200 | static CORE_ADDR |
143985b7 AF |
3201 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
3202 | struct type *type) | |
3203 | { | |
e17a4113 UW |
3204 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3205 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 3206 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 3207 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
3208 | } |
3209 | ||
514f746b AR |
3210 | static void |
3211 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
3212 | { | |
3213 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
3214 | ||
3215 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
3216 | adjust the PC in the regcache. */ | |
3217 | current_pc += 1; | |
3218 | regcache_write_pc (regcache, current_pc); | |
3219 | } | |
3220 | ||
3221 | ||
7ad10968 HZ |
3222 | #define PREFIX_REPZ 0x01 |
3223 | #define PREFIX_REPNZ 0x02 | |
3224 | #define PREFIX_LOCK 0x04 | |
3225 | #define PREFIX_DATA 0x08 | |
3226 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 3227 | |
7ad10968 HZ |
3228 | /* operand size */ |
3229 | enum | |
3230 | { | |
3231 | OT_BYTE = 0, | |
3232 | OT_WORD, | |
3233 | OT_LONG, | |
cf648174 | 3234 | OT_QUAD, |
a3c4230a | 3235 | OT_DQUAD, |
7ad10968 | 3236 | }; |
473f17b0 | 3237 | |
7ad10968 HZ |
3238 | /* i386 arith/logic operations */ |
3239 | enum | |
3240 | { | |
3241 | OP_ADDL, | |
3242 | OP_ORL, | |
3243 | OP_ADCL, | |
3244 | OP_SBBL, | |
3245 | OP_ANDL, | |
3246 | OP_SUBL, | |
3247 | OP_XORL, | |
3248 | OP_CMPL, | |
3249 | }; | |
5716833c | 3250 | |
7ad10968 HZ |
3251 | struct i386_record_s |
3252 | { | |
cf648174 | 3253 | struct gdbarch *gdbarch; |
7ad10968 | 3254 | struct regcache *regcache; |
df61f520 | 3255 | CORE_ADDR orig_addr; |
7ad10968 HZ |
3256 | CORE_ADDR addr; |
3257 | int aflag; | |
3258 | int dflag; | |
3259 | int override; | |
3260 | uint8_t modrm; | |
3261 | uint8_t mod, reg, rm; | |
3262 | int ot; | |
cf648174 HZ |
3263 | uint8_t rex_x; |
3264 | uint8_t rex_b; | |
3265 | int rip_offset; | |
3266 | int popl_esp_hack; | |
3267 | const int *regmap; | |
7ad10968 | 3268 | }; |
5716833c | 3269 | |
7ad10968 | 3270 | /* Parse "modrm" part in current memory address that irp->addr point to |
1777feb0 | 3271 | Return -1 if something wrong. */ |
5716833c | 3272 | |
7ad10968 HZ |
3273 | static int |
3274 | i386_record_modrm (struct i386_record_s *irp) | |
3275 | { | |
cf648174 | 3276 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 3277 | |
7ad10968 HZ |
3278 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
3279 | { | |
3280 | if (record_debug) | |
3281 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3282 | "addr %s len = 1.\n"), |
3283 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3284 | return -1; |
3285 | } | |
3286 | irp->addr++; | |
3287 | irp->mod = (irp->modrm >> 6) & 3; | |
3288 | irp->reg = (irp->modrm >> 3) & 7; | |
3289 | irp->rm = irp->modrm & 7; | |
5716833c | 3290 | |
7ad10968 HZ |
3291 | return 0; |
3292 | } | |
d2a7c97a | 3293 | |
7ad10968 HZ |
3294 | /* Get the memory address that current instruction write to and set it to |
3295 | the argument "addr". | |
1777feb0 | 3296 | Return -1 if something wrong. */ |
8201327c | 3297 | |
7ad10968 | 3298 | static int |
cf648174 | 3299 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 3300 | { |
cf648174 | 3301 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
3302 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3303 | gdb_byte buf[4]; | |
3304 | ULONGEST offset64; | |
21d0e8a4 | 3305 | |
7ad10968 HZ |
3306 | *addr = 0; |
3307 | if (irp->aflag) | |
3308 | { | |
3309 | /* 32 bits */ | |
3310 | int havesib = 0; | |
3311 | uint8_t scale = 0; | |
648d0c8b | 3312 | uint8_t byte; |
7ad10968 HZ |
3313 | uint8_t index = 0; |
3314 | uint8_t base = irp->rm; | |
896fb97d | 3315 | |
7ad10968 HZ |
3316 | if (base == 4) |
3317 | { | |
3318 | havesib = 1; | |
648d0c8b | 3319 | if (target_read_memory (irp->addr, &byte, 1)) |
7ad10968 HZ |
3320 | { |
3321 | if (record_debug) | |
3322 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3323 | "at addr %s len = 1.\n"), |
3324 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3325 | return -1; |
3326 | } | |
3327 | irp->addr++; | |
648d0c8b MS |
3328 | scale = (byte >> 6) & 3; |
3329 | index = ((byte >> 3) & 7) | irp->rex_x; | |
3330 | base = (byte & 7); | |
7ad10968 | 3331 | } |
cf648174 | 3332 | base |= irp->rex_b; |
21d0e8a4 | 3333 | |
7ad10968 HZ |
3334 | switch (irp->mod) |
3335 | { | |
3336 | case 0: | |
3337 | if ((base & 7) == 5) | |
3338 | { | |
3339 | base = 0xff; | |
60a1502a | 3340 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3341 | { |
3342 | if (record_debug) | |
3343 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3344 | "memory at addr %s len = 4.\n"), |
3345 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3346 | return -1; |
3347 | } | |
3348 | irp->addr += 4; | |
60a1502a | 3349 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
3350 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
3351 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 3352 | } |
7ad10968 HZ |
3353 | break; |
3354 | case 1: | |
60a1502a | 3355 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3356 | { |
3357 | if (record_debug) | |
3358 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3359 | "at addr %s len = 1.\n"), |
3360 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3361 | return -1; |
3362 | } | |
3363 | irp->addr++; | |
60a1502a | 3364 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3365 | break; |
3366 | case 2: | |
60a1502a | 3367 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3368 | { |
3369 | if (record_debug) | |
3370 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3371 | "at addr %s len = 4.\n"), |
3372 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3373 | return -1; |
3374 | } | |
60a1502a | 3375 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
3376 | irp->addr += 4; |
3377 | break; | |
3378 | } | |
356a6b3e | 3379 | |
60a1502a | 3380 | offset64 = 0; |
7ad10968 | 3381 | if (base != 0xff) |
cf648174 HZ |
3382 | { |
3383 | if (base == 4 && irp->popl_esp_hack) | |
3384 | *addr += irp->popl_esp_hack; | |
3385 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 3386 | &offset64); |
7ad10968 | 3387 | } |
cf648174 HZ |
3388 | if (irp->aflag == 2) |
3389 | { | |
60a1502a | 3390 | *addr += offset64; |
cf648174 HZ |
3391 | } |
3392 | else | |
60a1502a | 3393 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 3394 | |
7ad10968 HZ |
3395 | if (havesib && (index != 4 || scale != 0)) |
3396 | { | |
cf648174 | 3397 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 3398 | &offset64); |
cf648174 | 3399 | if (irp->aflag == 2) |
60a1502a | 3400 | *addr += offset64 << scale; |
cf648174 | 3401 | else |
60a1502a | 3402 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
3403 | } |
3404 | } | |
3405 | else | |
3406 | { | |
3407 | /* 16 bits */ | |
3408 | switch (irp->mod) | |
3409 | { | |
3410 | case 0: | |
3411 | if (irp->rm == 6) | |
3412 | { | |
60a1502a | 3413 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3414 | { |
3415 | if (record_debug) | |
3416 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3417 | "memory at addr %s len = 2.\n"), |
3418 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3419 | return -1; |
3420 | } | |
3421 | irp->addr += 2; | |
60a1502a | 3422 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3423 | irp->rm = 0; |
3424 | goto no_rm; | |
3425 | } | |
7ad10968 HZ |
3426 | break; |
3427 | case 1: | |
60a1502a | 3428 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3429 | { |
3430 | if (record_debug) | |
3431 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3432 | "at addr %s len = 1.\n"), |
3433 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3434 | return -1; |
3435 | } | |
3436 | irp->addr++; | |
60a1502a | 3437 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3438 | break; |
3439 | case 2: | |
60a1502a | 3440 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3441 | { |
3442 | if (record_debug) | |
3443 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3444 | "at addr %s len = 2.\n"), |
3445 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3446 | return -1; |
3447 | } | |
3448 | irp->addr += 2; | |
60a1502a | 3449 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3450 | break; |
3451 | } | |
c4fc7f1b | 3452 | |
7ad10968 HZ |
3453 | switch (irp->rm) |
3454 | { | |
3455 | case 0: | |
cf648174 HZ |
3456 | regcache_raw_read_unsigned (irp->regcache, |
3457 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3458 | &offset64); |
3459 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3460 | regcache_raw_read_unsigned (irp->regcache, |
3461 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3462 | &offset64); |
3463 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3464 | break; |
3465 | case 1: | |
cf648174 HZ |
3466 | regcache_raw_read_unsigned (irp->regcache, |
3467 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3468 | &offset64); |
3469 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3470 | regcache_raw_read_unsigned (irp->regcache, |
3471 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3472 | &offset64); |
3473 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3474 | break; |
3475 | case 2: | |
cf648174 HZ |
3476 | regcache_raw_read_unsigned (irp->regcache, |
3477 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3478 | &offset64); |
3479 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3480 | regcache_raw_read_unsigned (irp->regcache, |
3481 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3482 | &offset64); |
3483 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3484 | break; |
3485 | case 3: | |
cf648174 HZ |
3486 | regcache_raw_read_unsigned (irp->regcache, |
3487 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3488 | &offset64); |
3489 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3490 | regcache_raw_read_unsigned (irp->regcache, |
3491 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3492 | &offset64); |
3493 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3494 | break; |
3495 | case 4: | |
cf648174 HZ |
3496 | regcache_raw_read_unsigned (irp->regcache, |
3497 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3498 | &offset64); |
3499 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3500 | break; |
3501 | case 5: | |
cf648174 HZ |
3502 | regcache_raw_read_unsigned (irp->regcache, |
3503 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3504 | &offset64); |
3505 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3506 | break; |
3507 | case 6: | |
cf648174 HZ |
3508 | regcache_raw_read_unsigned (irp->regcache, |
3509 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3510 | &offset64); |
3511 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3512 | break; |
3513 | case 7: | |
cf648174 HZ |
3514 | regcache_raw_read_unsigned (irp->regcache, |
3515 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3516 | &offset64); |
3517 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3518 | break; |
3519 | } | |
3520 | *addr &= 0xffff; | |
3521 | } | |
c4fc7f1b | 3522 | |
01fe1b41 | 3523 | no_rm: |
7ad10968 HZ |
3524 | return 0; |
3525 | } | |
c4fc7f1b | 3526 | |
7ad10968 HZ |
3527 | /* Record the value of the memory that willbe changed in current instruction |
3528 | to "record_arch_list". | |
1777feb0 | 3529 | Return -1 if something wrong. */ |
356a6b3e | 3530 | |
7ad10968 HZ |
3531 | static int |
3532 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3533 | { | |
cf648174 HZ |
3534 | struct gdbarch *gdbarch = irp->gdbarch; |
3535 | uint64_t addr; | |
356a6b3e | 3536 | |
d7877f7e | 3537 | if (irp->override >= 0) |
7ad10968 | 3538 | { |
bb08c432 HZ |
3539 | if (record_memory_query) |
3540 | { | |
3541 | int q; | |
3542 | ||
3543 | target_terminal_ours (); | |
3544 | q = yquery (_("\ | |
3545 | Process record ignores the memory change of instruction at address %s\n\ | |
3546 | because it can't get the value of the segment register.\n\ | |
3547 | Do you want to stop the program?"), | |
3548 | paddress (gdbarch, irp->orig_addr)); | |
3549 | target_terminal_inferior (); | |
3550 | if (q) | |
3551 | return -1; | |
3552 | } | |
3553 | ||
7ad10968 HZ |
3554 | return 0; |
3555 | } | |
61113f8b | 3556 | |
7ad10968 HZ |
3557 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3558 | return -1; | |
96297dab | 3559 | |
7ad10968 HZ |
3560 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3561 | return -1; | |
a62cc96e | 3562 | |
7ad10968 HZ |
3563 | return 0; |
3564 | } | |
b6197528 | 3565 | |
cf648174 | 3566 | /* Record the push operation to "record_arch_list". |
1777feb0 | 3567 | Return -1 if something wrong. */ |
cf648174 HZ |
3568 | |
3569 | static int | |
3570 | i386_record_push (struct i386_record_s *irp, int size) | |
3571 | { | |
648d0c8b | 3572 | ULONGEST addr; |
cf648174 HZ |
3573 | |
3574 | if (record_arch_list_add_reg (irp->regcache, | |
3575 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3576 | return -1; | |
3577 | regcache_raw_read_unsigned (irp->regcache, | |
3578 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
3579 | &addr); |
3580 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
3581 | return -1; |
3582 | ||
3583 | return 0; | |
3584 | } | |
3585 | ||
0289bdd7 MS |
3586 | |
3587 | /* Defines contents to record. */ | |
3588 | #define I386_SAVE_FPU_REGS 0xfffd | |
3589 | #define I386_SAVE_FPU_ENV 0xfffe | |
3590 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3591 | ||
1777feb0 MS |
3592 | /* Record the value of floating point registers which will be changed |
3593 | by the current instruction to "record_arch_list". Return -1 if | |
3594 | something is wrong. */ | |
0289bdd7 MS |
3595 | |
3596 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3597 | struct i386_record_s *ir, | |
3598 | uint32_t iregnum) | |
3599 | { | |
3600 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3601 | int i; | |
3602 | ||
3603 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3604 | happen. Currently we store st0-st7 registers, but we need not store all | |
3605 | registers all the time, in future we use ftag register and record only | |
3606 | those who are not marked as an empty. */ | |
3607 | ||
3608 | if (I386_SAVE_FPU_REGS == iregnum) | |
3609 | { | |
3610 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3611 | { | |
3612 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3613 | return -1; | |
3614 | } | |
3615 | } | |
3616 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3617 | { | |
3618 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3619 | { | |
3620 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3621 | return -1; | |
3622 | } | |
3623 | } | |
3624 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3625 | { | |
3626 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3627 | { | |
3628 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3629 | return -1; | |
3630 | } | |
3631 | } | |
3632 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3633 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3634 | { | |
3635 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3636 | return -1; | |
3637 | } | |
3638 | else | |
3639 | { | |
3640 | /* Parameter error. */ | |
3641 | return -1; | |
3642 | } | |
3643 | if(I386_SAVE_FPU_ENV != iregnum) | |
3644 | { | |
3645 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3646 | { | |
3647 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3648 | return -1; | |
3649 | } | |
3650 | } | |
3651 | return 0; | |
3652 | } | |
3653 | ||
7ad10968 HZ |
3654 | /* Parse the current instruction and record the values of the registers and |
3655 | memory that will be changed in current instruction to "record_arch_list". | |
1777feb0 | 3656 | Return -1 if something wrong. */ |
8201327c | 3657 | |
cf648174 HZ |
3658 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3659 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3660 | ||
a6b808b4 | 3661 | int |
7ad10968 | 3662 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 3663 | CORE_ADDR input_addr) |
7ad10968 | 3664 | { |
60a1502a | 3665 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 3666 | int prefixes = 0; |
580879fc | 3667 | int regnum = 0; |
425b824a MS |
3668 | uint32_t opcode; |
3669 | uint8_t opcode8; | |
648d0c8b | 3670 | ULONGEST addr; |
60a1502a | 3671 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 3672 | struct i386_record_s ir; |
0289bdd7 | 3673 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3674 | int rex = 0; |
3675 | uint8_t rex_w = -1; | |
3676 | uint8_t rex_r = 0; | |
7ad10968 | 3677 | |
8408d274 | 3678 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 3679 | ir.regcache = regcache; |
648d0c8b MS |
3680 | ir.addr = input_addr; |
3681 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
3682 | ir.aflag = 1; |
3683 | ir.dflag = 1; | |
cf648174 HZ |
3684 | ir.override = -1; |
3685 | ir.popl_esp_hack = 0; | |
a3c4230a | 3686 | ir.regmap = tdep->record_regmap; |
cf648174 | 3687 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
3688 | |
3689 | if (record_debug > 1) | |
3690 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
3691 | "addr = %s\n", |
3692 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3693 | |
3694 | /* prefixes */ | |
3695 | while (1) | |
3696 | { | |
425b824a | 3697 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3698 | { |
3699 | if (record_debug) | |
3700 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3701 | "addr %s len = 1.\n"), |
3702 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3703 | return -1; |
3704 | } | |
3705 | ir.addr++; | |
425b824a | 3706 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 3707 | { |
01fe1b41 | 3708 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
3709 | prefixes |= PREFIX_REPZ; |
3710 | break; | |
01fe1b41 | 3711 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
3712 | prefixes |= PREFIX_REPNZ; |
3713 | break; | |
01fe1b41 | 3714 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
3715 | prefixes |= PREFIX_LOCK; |
3716 | break; | |
01fe1b41 | 3717 | case CS_PREFIX_OPCODE: |
cf648174 | 3718 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 3719 | break; |
01fe1b41 | 3720 | case SS_PREFIX_OPCODE: |
cf648174 | 3721 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 3722 | break; |
01fe1b41 | 3723 | case DS_PREFIX_OPCODE: |
cf648174 | 3724 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 3725 | break; |
01fe1b41 | 3726 | case ES_PREFIX_OPCODE: |
cf648174 | 3727 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 3728 | break; |
01fe1b41 | 3729 | case FS_PREFIX_OPCODE: |
cf648174 | 3730 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 3731 | break; |
01fe1b41 | 3732 | case GS_PREFIX_OPCODE: |
cf648174 | 3733 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 3734 | break; |
01fe1b41 | 3735 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
3736 | prefixes |= PREFIX_DATA; |
3737 | break; | |
01fe1b41 | 3738 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
3739 | prefixes |= PREFIX_ADDR; |
3740 | break; | |
d691bec7 MS |
3741 | case 0x40: /* i386 inc %eax */ |
3742 | case 0x41: /* i386 inc %ecx */ | |
3743 | case 0x42: /* i386 inc %edx */ | |
3744 | case 0x43: /* i386 inc %ebx */ | |
3745 | case 0x44: /* i386 inc %esp */ | |
3746 | case 0x45: /* i386 inc %ebp */ | |
3747 | case 0x46: /* i386 inc %esi */ | |
3748 | case 0x47: /* i386 inc %edi */ | |
3749 | case 0x48: /* i386 dec %eax */ | |
3750 | case 0x49: /* i386 dec %ecx */ | |
3751 | case 0x4a: /* i386 dec %edx */ | |
3752 | case 0x4b: /* i386 dec %ebx */ | |
3753 | case 0x4c: /* i386 dec %esp */ | |
3754 | case 0x4d: /* i386 dec %ebp */ | |
3755 | case 0x4e: /* i386 dec %esi */ | |
3756 | case 0x4f: /* i386 dec %edi */ | |
3757 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
3758 | { |
3759 | /* REX */ | |
3760 | rex = 1; | |
425b824a MS |
3761 | rex_w = (opcode8 >> 3) & 1; |
3762 | rex_r = (opcode8 & 0x4) << 1; | |
3763 | ir.rex_x = (opcode8 & 0x2) << 2; | |
3764 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 3765 | } |
d691bec7 MS |
3766 | else /* 32 bit target */ |
3767 | goto out_prefixes; | |
cf648174 | 3768 | break; |
7ad10968 HZ |
3769 | default: |
3770 | goto out_prefixes; | |
3771 | break; | |
3772 | } | |
3773 | } | |
01fe1b41 | 3774 | out_prefixes: |
cf648174 HZ |
3775 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
3776 | { | |
3777 | ir.dflag = 2; | |
3778 | } | |
3779 | else | |
3780 | { | |
3781 | if (prefixes & PREFIX_DATA) | |
3782 | ir.dflag ^= 1; | |
3783 | } | |
7ad10968 HZ |
3784 | if (prefixes & PREFIX_ADDR) |
3785 | ir.aflag ^= 1; | |
cf648174 HZ |
3786 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3787 | ir.aflag = 2; | |
7ad10968 | 3788 | |
1777feb0 | 3789 | /* Now check op code. */ |
425b824a | 3790 | opcode = (uint32_t) opcode8; |
01fe1b41 | 3791 | reswitch: |
7ad10968 HZ |
3792 | switch (opcode) |
3793 | { | |
3794 | case 0x0f: | |
425b824a | 3795 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3796 | { |
3797 | if (record_debug) | |
3798 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3799 | "addr %s len = 1.\n"), |
3800 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3801 | return -1; |
3802 | } | |
3803 | ir.addr++; | |
a3c4230a | 3804 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
3805 | goto reswitch; |
3806 | break; | |
93924b6b | 3807 | |
a38bba38 | 3808 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
3809 | case 0x01: |
3810 | case 0x02: | |
3811 | case 0x03: | |
3812 | case 0x04: | |
3813 | case 0x05: | |
3814 | case 0x08: | |
3815 | case 0x09: | |
3816 | case 0x0a: | |
3817 | case 0x0b: | |
3818 | case 0x0c: | |
3819 | case 0x0d: | |
3820 | case 0x10: | |
3821 | case 0x11: | |
3822 | case 0x12: | |
3823 | case 0x13: | |
3824 | case 0x14: | |
3825 | case 0x15: | |
3826 | case 0x18: | |
3827 | case 0x19: | |
3828 | case 0x1a: | |
3829 | case 0x1b: | |
3830 | case 0x1c: | |
3831 | case 0x1d: | |
3832 | case 0x20: | |
3833 | case 0x21: | |
3834 | case 0x22: | |
3835 | case 0x23: | |
3836 | case 0x24: | |
3837 | case 0x25: | |
3838 | case 0x28: | |
3839 | case 0x29: | |
3840 | case 0x2a: | |
3841 | case 0x2b: | |
3842 | case 0x2c: | |
3843 | case 0x2d: | |
3844 | case 0x30: | |
3845 | case 0x31: | |
3846 | case 0x32: | |
3847 | case 0x33: | |
3848 | case 0x34: | |
3849 | case 0x35: | |
3850 | case 0x38: | |
3851 | case 0x39: | |
3852 | case 0x3a: | |
3853 | case 0x3b: | |
3854 | case 0x3c: | |
3855 | case 0x3d: | |
3856 | if (((opcode >> 3) & 7) != OP_CMPL) | |
3857 | { | |
3858 | if ((opcode & 1) == 0) | |
3859 | ir.ot = OT_BYTE; | |
3860 | else | |
3861 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 3862 | |
7ad10968 HZ |
3863 | switch ((opcode >> 1) & 3) |
3864 | { | |
a38bba38 | 3865 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
3866 | if (i386_record_modrm (&ir)) |
3867 | return -1; | |
3868 | if (ir.mod != 3) | |
3869 | { | |
3870 | if (i386_record_lea_modrm (&ir)) | |
3871 | return -1; | |
3872 | } | |
3873 | else | |
3874 | { | |
cf648174 HZ |
3875 | ir.rm |= ir.rex_b; |
3876 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3877 | ir.rm &= 0x3; |
cf648174 | 3878 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3879 | } |
3880 | break; | |
a38bba38 | 3881 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
3882 | if (i386_record_modrm (&ir)) |
3883 | return -1; | |
cf648174 HZ |
3884 | ir.reg |= rex_r; |
3885 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3886 | ir.reg &= 0x3; |
cf648174 | 3887 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3888 | break; |
a38bba38 | 3889 | case 2: /* OP A, Iv */ |
cf648174 | 3890 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3891 | break; |
3892 | } | |
3893 | } | |
cf648174 | 3894 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3895 | break; |
42fdc8df | 3896 | |
a38bba38 | 3897 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
3898 | case 0x81: |
3899 | case 0x82: | |
3900 | case 0x83: | |
3901 | if (i386_record_modrm (&ir)) | |
3902 | return -1; | |
8201327c | 3903 | |
7ad10968 HZ |
3904 | if (ir.reg != OP_CMPL) |
3905 | { | |
3906 | if ((opcode & 1) == 0) | |
3907 | ir.ot = OT_BYTE; | |
3908 | else | |
3909 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 3910 | |
7ad10968 HZ |
3911 | if (ir.mod != 3) |
3912 | { | |
cf648174 HZ |
3913 | if (opcode == 0x83) |
3914 | ir.rip_offset = 1; | |
3915 | else | |
3916 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3917 | if (i386_record_lea_modrm (&ir)) |
3918 | return -1; | |
3919 | } | |
3920 | else | |
cf648174 | 3921 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 3922 | } |
cf648174 | 3923 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3924 | break; |
5e3397bb | 3925 | |
a38bba38 | 3926 | case 0x40: /* inc */ |
7ad10968 HZ |
3927 | case 0x41: |
3928 | case 0x42: | |
3929 | case 0x43: | |
3930 | case 0x44: | |
3931 | case 0x45: | |
3932 | case 0x46: | |
3933 | case 0x47: | |
a38bba38 MS |
3934 | |
3935 | case 0x48: /* dec */ | |
7ad10968 HZ |
3936 | case 0x49: |
3937 | case 0x4a: | |
3938 | case 0x4b: | |
3939 | case 0x4c: | |
3940 | case 0x4d: | |
3941 | case 0x4e: | |
3942 | case 0x4f: | |
a38bba38 | 3943 | |
cf648174 HZ |
3944 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
3945 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 3946 | break; |
acd5c798 | 3947 | |
a38bba38 | 3948 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
3949 | case 0xf7: |
3950 | if ((opcode & 1) == 0) | |
3951 | ir.ot = OT_BYTE; | |
3952 | else | |
3953 | ir.ot = ir.dflag + OT_WORD; | |
3954 | if (i386_record_modrm (&ir)) | |
3955 | return -1; | |
acd5c798 | 3956 | |
cf648174 HZ |
3957 | if (ir.mod != 3 && ir.reg == 0) |
3958 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3959 | ||
7ad10968 HZ |
3960 | switch (ir.reg) |
3961 | { | |
a38bba38 | 3962 | case 0: /* test */ |
cf648174 | 3963 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3964 | break; |
a38bba38 MS |
3965 | case 2: /* not */ |
3966 | case 3: /* neg */ | |
7ad10968 HZ |
3967 | if (ir.mod != 3) |
3968 | { | |
3969 | if (i386_record_lea_modrm (&ir)) | |
3970 | return -1; | |
3971 | } | |
3972 | else | |
3973 | { | |
cf648174 HZ |
3974 | ir.rm |= ir.rex_b; |
3975 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3976 | ir.rm &= 0x3; |
cf648174 | 3977 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3978 | } |
a38bba38 | 3979 | if (ir.reg == 3) /* neg */ |
cf648174 | 3980 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3981 | break; |
a38bba38 MS |
3982 | case 4: /* mul */ |
3983 | case 5: /* imul */ | |
3984 | case 6: /* div */ | |
3985 | case 7: /* idiv */ | |
cf648174 | 3986 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 3987 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
3988 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
3989 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3990 | break; |
3991 | default: | |
3992 | ir.addr -= 2; | |
3993 | opcode = opcode << 8 | ir.modrm; | |
3994 | goto no_support; | |
3995 | break; | |
3996 | } | |
3997 | break; | |
3998 | ||
a38bba38 MS |
3999 | case 0xfe: /* GRP4 */ |
4000 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
4001 | if (i386_record_modrm (&ir)) |
4002 | return -1; | |
4003 | if (ir.reg >= 2 && opcode == 0xfe) | |
4004 | { | |
4005 | ir.addr -= 2; | |
4006 | opcode = opcode << 8 | ir.modrm; | |
4007 | goto no_support; | |
4008 | } | |
7ad10968 HZ |
4009 | switch (ir.reg) |
4010 | { | |
a38bba38 MS |
4011 | case 0: /* inc */ |
4012 | case 1: /* dec */ | |
cf648174 HZ |
4013 | if ((opcode & 1) == 0) |
4014 | ir.ot = OT_BYTE; | |
4015 | else | |
4016 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4017 | if (ir.mod != 3) |
4018 | { | |
4019 | if (i386_record_lea_modrm (&ir)) | |
4020 | return -1; | |
4021 | } | |
4022 | else | |
4023 | { | |
cf648174 HZ |
4024 | ir.rm |= ir.rex_b; |
4025 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4026 | ir.rm &= 0x3; |
cf648174 | 4027 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4028 | } |
cf648174 | 4029 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4030 | break; |
a38bba38 | 4031 | case 2: /* call */ |
cf648174 HZ |
4032 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4033 | ir.dflag = 2; | |
4034 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4035 | return -1; |
cf648174 | 4036 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4037 | break; |
a38bba38 | 4038 | case 3: /* lcall */ |
cf648174 HZ |
4039 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4040 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4041 | return -1; |
cf648174 | 4042 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4043 | break; |
a38bba38 MS |
4044 | case 4: /* jmp */ |
4045 | case 5: /* ljmp */ | |
cf648174 HZ |
4046 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4047 | break; | |
a38bba38 | 4048 | case 6: /* push */ |
cf648174 HZ |
4049 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4050 | ir.dflag = 2; | |
4051 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4052 | return -1; | |
7ad10968 HZ |
4053 | break; |
4054 | default: | |
4055 | ir.addr -= 2; | |
4056 | opcode = opcode << 8 | ir.modrm; | |
4057 | goto no_support; | |
4058 | break; | |
4059 | } | |
4060 | break; | |
4061 | ||
a38bba38 | 4062 | case 0x84: /* test */ |
7ad10968 HZ |
4063 | case 0x85: |
4064 | case 0xa8: | |
4065 | case 0xa9: | |
cf648174 | 4066 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4067 | break; |
4068 | ||
a38bba38 | 4069 | case 0x98: /* CWDE/CBW */ |
cf648174 | 4070 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4071 | break; |
4072 | ||
a38bba38 | 4073 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
4074 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4075 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4076 | break; |
4077 | ||
a38bba38 | 4078 | case 0x0faf: /* imul */ |
7ad10968 HZ |
4079 | case 0x69: |
4080 | case 0x6b: | |
4081 | ir.ot = ir.dflag + OT_WORD; | |
4082 | if (i386_record_modrm (&ir)) | |
4083 | return -1; | |
cf648174 HZ |
4084 | if (opcode == 0x69) |
4085 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4086 | else if (opcode == 0x6b) | |
4087 | ir.rip_offset = 1; | |
4088 | ir.reg |= rex_r; | |
4089 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4090 | ir.reg &= 0x3; |
cf648174 HZ |
4091 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4092 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4093 | break; |
4094 | ||
a38bba38 | 4095 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4096 | case 0x0fc1: |
4097 | if ((opcode & 1) == 0) | |
4098 | ir.ot = OT_BYTE; | |
4099 | else | |
4100 | ir.ot = ir.dflag + OT_WORD; | |
4101 | if (i386_record_modrm (&ir)) | |
4102 | return -1; | |
cf648174 | 4103 | ir.reg |= rex_r; |
7ad10968 HZ |
4104 | if (ir.mod == 3) |
4105 | { | |
cf648174 | 4106 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4107 | ir.reg &= 0x3; |
cf648174 HZ |
4108 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4109 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4110 | ir.rm &= 0x3; |
cf648174 | 4111 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4112 | } |
4113 | else | |
4114 | { | |
4115 | if (i386_record_lea_modrm (&ir)) | |
4116 | return -1; | |
cf648174 | 4117 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4118 | ir.reg &= 0x3; |
cf648174 | 4119 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4120 | } |
cf648174 | 4121 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4122 | break; |
4123 | ||
a38bba38 | 4124 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4125 | case 0x0fb1: |
4126 | if ((opcode & 1) == 0) | |
4127 | ir.ot = OT_BYTE; | |
4128 | else | |
4129 | ir.ot = ir.dflag + OT_WORD; | |
4130 | if (i386_record_modrm (&ir)) | |
4131 | return -1; | |
4132 | if (ir.mod == 3) | |
4133 | { | |
cf648174 HZ |
4134 | ir.reg |= rex_r; |
4135 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4136 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4137 | ir.reg &= 0x3; |
cf648174 | 4138 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4139 | } |
4140 | else | |
4141 | { | |
cf648174 | 4142 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4143 | if (i386_record_lea_modrm (&ir)) |
4144 | return -1; | |
4145 | } | |
cf648174 | 4146 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4147 | break; |
4148 | ||
a38bba38 | 4149 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4150 | if (i386_record_modrm (&ir)) |
4151 | return -1; | |
4152 | if (ir.mod == 3) | |
4153 | { | |
4154 | ir.addr -= 2; | |
4155 | opcode = opcode << 8 | ir.modrm; | |
4156 | goto no_support; | |
4157 | } | |
cf648174 HZ |
4158 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4159 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4160 | if (i386_record_lea_modrm (&ir)) |
4161 | return -1; | |
cf648174 | 4162 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4163 | break; |
4164 | ||
a38bba38 | 4165 | case 0x50: /* push */ |
7ad10968 HZ |
4166 | case 0x51: |
4167 | case 0x52: | |
4168 | case 0x53: | |
4169 | case 0x54: | |
4170 | case 0x55: | |
4171 | case 0x56: | |
4172 | case 0x57: | |
4173 | case 0x68: | |
4174 | case 0x6a: | |
cf648174 HZ |
4175 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4176 | ir.dflag = 2; | |
4177 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4178 | return -1; | |
4179 | break; | |
4180 | ||
a38bba38 MS |
4181 | case 0x06: /* push es */ |
4182 | case 0x0e: /* push cs */ | |
4183 | case 0x16: /* push ss */ | |
4184 | case 0x1e: /* push ds */ | |
cf648174 HZ |
4185 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4186 | { | |
4187 | ir.addr -= 1; | |
4188 | goto no_support; | |
4189 | } | |
4190 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4191 | return -1; | |
4192 | break; | |
4193 | ||
a38bba38 MS |
4194 | case 0x0fa0: /* push fs */ |
4195 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
4196 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4197 | { | |
4198 | ir.addr -= 2; | |
4199 | goto no_support; | |
4200 | } | |
4201 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4202 | return -1; |
cf648174 HZ |
4203 | break; |
4204 | ||
a38bba38 | 4205 | case 0x60: /* pusha */ |
cf648174 HZ |
4206 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4207 | { | |
4208 | ir.addr -= 1; | |
4209 | goto no_support; | |
4210 | } | |
4211 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
4212 | return -1; |
4213 | break; | |
4214 | ||
a38bba38 | 4215 | case 0x58: /* pop */ |
7ad10968 HZ |
4216 | case 0x59: |
4217 | case 0x5a: | |
4218 | case 0x5b: | |
4219 | case 0x5c: | |
4220 | case 0x5d: | |
4221 | case 0x5e: | |
4222 | case 0x5f: | |
cf648174 HZ |
4223 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4224 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
4225 | break; |
4226 | ||
a38bba38 | 4227 | case 0x61: /* popa */ |
cf648174 HZ |
4228 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4229 | { | |
4230 | ir.addr -= 1; | |
4231 | goto no_support; | |
7ad10968 | 4232 | } |
425b824a MS |
4233 | for (regnum = X86_RECORD_REAX_REGNUM; |
4234 | regnum <= X86_RECORD_REDI_REGNUM; | |
4235 | regnum++) | |
4236 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
4237 | break; |
4238 | ||
a38bba38 | 4239 | case 0x8f: /* pop */ |
cf648174 HZ |
4240 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4241 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
4242 | else | |
4243 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4244 | if (i386_record_modrm (&ir)) |
4245 | return -1; | |
4246 | if (ir.mod == 3) | |
cf648174 | 4247 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
4248 | else |
4249 | { | |
cf648174 | 4250 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
4251 | if (i386_record_lea_modrm (&ir)) |
4252 | return -1; | |
4253 | } | |
cf648174 | 4254 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
4255 | break; |
4256 | ||
a38bba38 | 4257 | case 0xc8: /* enter */ |
cf648174 HZ |
4258 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
4259 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4260 | ir.dflag = 2; | |
4261 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
4262 | return -1; |
4263 | break; | |
4264 | ||
a38bba38 | 4265 | case 0xc9: /* leave */ |
cf648174 HZ |
4266 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4267 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
4268 | break; |
4269 | ||
a38bba38 | 4270 | case 0x07: /* pop es */ |
cf648174 HZ |
4271 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4272 | { | |
4273 | ir.addr -= 1; | |
4274 | goto no_support; | |
4275 | } | |
4276 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4277 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
4278 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4279 | break; |
4280 | ||
a38bba38 | 4281 | case 0x17: /* pop ss */ |
cf648174 HZ |
4282 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4283 | { | |
4284 | ir.addr -= 1; | |
4285 | goto no_support; | |
4286 | } | |
4287 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4288 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
4289 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4290 | break; |
4291 | ||
a38bba38 | 4292 | case 0x1f: /* pop ds */ |
cf648174 HZ |
4293 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4294 | { | |
4295 | ir.addr -= 1; | |
4296 | goto no_support; | |
4297 | } | |
4298 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4299 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
4300 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4301 | break; |
4302 | ||
a38bba38 | 4303 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
4304 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4305 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
4306 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4307 | break; |
4308 | ||
a38bba38 | 4309 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
4310 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4311 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
4312 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4313 | break; |
4314 | ||
a38bba38 | 4315 | case 0x88: /* mov */ |
7ad10968 HZ |
4316 | case 0x89: |
4317 | case 0xc6: | |
4318 | case 0xc7: | |
4319 | if ((opcode & 1) == 0) | |
4320 | ir.ot = OT_BYTE; | |
4321 | else | |
4322 | ir.ot = ir.dflag + OT_WORD; | |
4323 | ||
4324 | if (i386_record_modrm (&ir)) | |
4325 | return -1; | |
4326 | ||
4327 | if (ir.mod != 3) | |
4328 | { | |
cf648174 HZ |
4329 | if (opcode == 0xc6 || opcode == 0xc7) |
4330 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4331 | if (i386_record_lea_modrm (&ir)) |
4332 | return -1; | |
4333 | } | |
4334 | else | |
4335 | { | |
cf648174 HZ |
4336 | if (opcode == 0xc6 || opcode == 0xc7) |
4337 | ir.rm |= ir.rex_b; | |
4338 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4339 | ir.rm &= 0x3; |
cf648174 | 4340 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4341 | } |
7ad10968 | 4342 | break; |
cf648174 | 4343 | |
a38bba38 | 4344 | case 0x8a: /* mov */ |
7ad10968 HZ |
4345 | case 0x8b: |
4346 | if ((opcode & 1) == 0) | |
4347 | ir.ot = OT_BYTE; | |
4348 | else | |
4349 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4350 | if (i386_record_modrm (&ir)) |
4351 | return -1; | |
cf648174 HZ |
4352 | ir.reg |= rex_r; |
4353 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4354 | ir.reg &= 0x3; |
cf648174 HZ |
4355 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4356 | break; | |
7ad10968 | 4357 | |
a38bba38 | 4358 | case 0x8c: /* mov seg */ |
cf648174 | 4359 | if (i386_record_modrm (&ir)) |
7ad10968 | 4360 | return -1; |
cf648174 HZ |
4361 | if (ir.reg > 5) |
4362 | { | |
4363 | ir.addr -= 2; | |
4364 | opcode = opcode << 8 | ir.modrm; | |
4365 | goto no_support; | |
4366 | } | |
4367 | ||
4368 | if (ir.mod == 3) | |
4369 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
4370 | else | |
4371 | { | |
4372 | ir.ot = OT_WORD; | |
4373 | if (i386_record_lea_modrm (&ir)) | |
4374 | return -1; | |
4375 | } | |
7ad10968 HZ |
4376 | break; |
4377 | ||
a38bba38 | 4378 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4379 | if (i386_record_modrm (&ir)) |
4380 | return -1; | |
7ad10968 HZ |
4381 | switch (ir.reg) |
4382 | { | |
4383 | case 0: | |
425b824a | 4384 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4385 | break; |
4386 | case 2: | |
425b824a | 4387 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4388 | break; |
4389 | case 3: | |
425b824a | 4390 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4391 | break; |
4392 | case 4: | |
425b824a | 4393 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4394 | break; |
4395 | case 5: | |
425b824a | 4396 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4397 | break; |
4398 | default: | |
4399 | ir.addr -= 2; | |
4400 | opcode = opcode << 8 | ir.modrm; | |
4401 | goto no_support; | |
4402 | break; | |
4403 | } | |
425b824a | 4404 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 4405 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4406 | break; |
4407 | ||
a38bba38 MS |
4408 | case 0x0fb6: /* movzbS */ |
4409 | case 0x0fb7: /* movzwS */ | |
4410 | case 0x0fbe: /* movsbS */ | |
4411 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
4412 | if (i386_record_modrm (&ir)) |
4413 | return -1; | |
cf648174 | 4414 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4415 | break; |
4416 | ||
a38bba38 | 4417 | case 0x8d: /* lea */ |
7ad10968 HZ |
4418 | if (i386_record_modrm (&ir)) |
4419 | return -1; | |
4420 | if (ir.mod == 3) | |
4421 | { | |
4422 | ir.addr -= 2; | |
4423 | opcode = opcode << 8 | ir.modrm; | |
4424 | goto no_support; | |
4425 | } | |
7ad10968 | 4426 | ir.ot = ir.dflag; |
cf648174 HZ |
4427 | ir.reg |= rex_r; |
4428 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4429 | ir.reg &= 0x3; |
cf648174 | 4430 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4431 | break; |
4432 | ||
a38bba38 | 4433 | case 0xa0: /* mov EAX */ |
7ad10968 | 4434 | case 0xa1: |
a38bba38 MS |
4435 | |
4436 | case 0xd7: /* xlat */ | |
cf648174 | 4437 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4438 | break; |
4439 | ||
a38bba38 | 4440 | case 0xa2: /* mov EAX */ |
7ad10968 | 4441 | case 0xa3: |
d7877f7e | 4442 | if (ir.override >= 0) |
cf648174 | 4443 | { |
bb08c432 HZ |
4444 | if (record_memory_query) |
4445 | { | |
4446 | int q; | |
4447 | ||
4448 | target_terminal_ours (); | |
4449 | q = yquery (_("\ | |
4450 | Process record ignores the memory change of instruction at address %s\n\ | |
4451 | because it can't get the value of the segment register.\n\ | |
4452 | Do you want to stop the program?"), | |
4453 | paddress (gdbarch, ir.orig_addr)); | |
4454 | target_terminal_inferior (); | |
4455 | if (q) | |
4456 | return -1; | |
4457 | } | |
cf648174 HZ |
4458 | } |
4459 | else | |
4460 | { | |
4461 | if ((opcode & 1) == 0) | |
4462 | ir.ot = OT_BYTE; | |
4463 | else | |
4464 | ir.ot = ir.dflag + OT_WORD; | |
4465 | if (ir.aflag == 2) | |
4466 | { | |
60a1502a | 4467 | if (target_read_memory (ir.addr, buf, 8)) |
cf648174 HZ |
4468 | { |
4469 | if (record_debug) | |
4470 | printf_unfiltered (_("Process record: error reading " | |
4471 | "memory at addr 0x%s len = 8.\n"), | |
4472 | paddress (gdbarch, ir.addr)); | |
4473 | return -1; | |
4474 | } | |
4475 | ir.addr += 8; | |
60a1502a | 4476 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
4477 | } |
4478 | else if (ir.aflag) | |
4479 | { | |
60a1502a | 4480 | if (target_read_memory (ir.addr, buf, 4)) |
cf648174 HZ |
4481 | { |
4482 | if (record_debug) | |
4483 | printf_unfiltered (_("Process record: error reading " | |
4484 | "memory at addr 0x%s len = 4.\n"), | |
4485 | paddress (gdbarch, ir.addr)); | |
4486 | return -1; | |
4487 | } | |
4488 | ir.addr += 4; | |
60a1502a | 4489 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
4490 | } |
4491 | else | |
4492 | { | |
60a1502a | 4493 | if (target_read_memory (ir.addr, buf, 2)) |
cf648174 HZ |
4494 | { |
4495 | if (record_debug) | |
4496 | printf_unfiltered (_("Process record: error reading " | |
4497 | "memory at addr 0x%s len = 2.\n"), | |
4498 | paddress (gdbarch, ir.addr)); | |
4499 | return -1; | |
4500 | } | |
4501 | ir.addr += 2; | |
60a1502a | 4502 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 4503 | } |
648d0c8b | 4504 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
4505 | return -1; |
4506 | } | |
7ad10968 HZ |
4507 | break; |
4508 | ||
a38bba38 | 4509 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
4510 | case 0xb1: |
4511 | case 0xb2: | |
4512 | case 0xb3: | |
4513 | case 0xb4: | |
4514 | case 0xb5: | |
4515 | case 0xb6: | |
4516 | case 0xb7: | |
cf648174 HZ |
4517 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4518 | ? ((opcode & 0x7) | ir.rex_b) | |
4519 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4520 | break; |
4521 | ||
a38bba38 | 4522 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
4523 | case 0xb9: |
4524 | case 0xba: | |
4525 | case 0xbb: | |
4526 | case 0xbc: | |
4527 | case 0xbd: | |
4528 | case 0xbe: | |
4529 | case 0xbf: | |
cf648174 | 4530 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4531 | break; |
4532 | ||
a38bba38 | 4533 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4534 | case 0x92: |
4535 | case 0x93: | |
4536 | case 0x94: | |
4537 | case 0x95: | |
4538 | case 0x96: | |
4539 | case 0x97: | |
cf648174 HZ |
4540 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4541 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4542 | break; |
4543 | ||
a38bba38 | 4544 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4545 | case 0x87: |
4546 | if ((opcode & 1) == 0) | |
4547 | ir.ot = OT_BYTE; | |
4548 | else | |
4549 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4550 | if (i386_record_modrm (&ir)) |
4551 | return -1; | |
7ad10968 HZ |
4552 | if (ir.mod == 3) |
4553 | { | |
86839d38 | 4554 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4555 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4556 | ir.rm &= 0x3; | |
4557 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4558 | } |
4559 | else | |
4560 | { | |
4561 | if (i386_record_lea_modrm (&ir)) | |
4562 | return -1; | |
4563 | } | |
cf648174 HZ |
4564 | ir.reg |= rex_r; |
4565 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4566 | ir.reg &= 0x3; |
cf648174 | 4567 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4568 | break; |
4569 | ||
a38bba38 MS |
4570 | case 0xc4: /* les Gv */ |
4571 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4572 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4573 | { | |
4574 | ir.addr -= 1; | |
4575 | goto no_support; | |
4576 | } | |
d3f323f3 | 4577 | /* FALLTHROUGH */ |
a38bba38 MS |
4578 | case 0x0fb2: /* lss Gv */ |
4579 | case 0x0fb4: /* lfs Gv */ | |
4580 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4581 | if (i386_record_modrm (&ir)) |
4582 | return -1; | |
4583 | if (ir.mod == 3) | |
4584 | { | |
4585 | if (opcode > 0xff) | |
4586 | ir.addr -= 3; | |
4587 | else | |
4588 | ir.addr -= 2; | |
4589 | opcode = opcode << 8 | ir.modrm; | |
4590 | goto no_support; | |
4591 | } | |
7ad10968 HZ |
4592 | switch (opcode) |
4593 | { | |
a38bba38 | 4594 | case 0xc4: /* les Gv */ |
425b824a | 4595 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 4596 | break; |
a38bba38 | 4597 | case 0xc5: /* lds Gv */ |
425b824a | 4598 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 4599 | break; |
a38bba38 | 4600 | case 0x0fb2: /* lss Gv */ |
425b824a | 4601 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 4602 | break; |
a38bba38 | 4603 | case 0x0fb4: /* lfs Gv */ |
425b824a | 4604 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 4605 | break; |
a38bba38 | 4606 | case 0x0fb5: /* lgs Gv */ |
425b824a | 4607 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4608 | break; |
4609 | } | |
425b824a | 4610 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
4611 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4612 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4613 | break; |
4614 | ||
a38bba38 | 4615 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4616 | case 0xc1: |
4617 | case 0xd0: | |
4618 | case 0xd1: | |
4619 | case 0xd2: | |
4620 | case 0xd3: | |
4621 | if ((opcode & 1) == 0) | |
4622 | ir.ot = OT_BYTE; | |
4623 | else | |
4624 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4625 | if (i386_record_modrm (&ir)) |
4626 | return -1; | |
7ad10968 HZ |
4627 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4628 | { | |
4629 | if (i386_record_lea_modrm (&ir)) | |
4630 | return -1; | |
4631 | } | |
4632 | else | |
4633 | { | |
cf648174 HZ |
4634 | ir.rm |= ir.rex_b; |
4635 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4636 | ir.rm &= 0x3; |
cf648174 | 4637 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4638 | } |
cf648174 | 4639 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4640 | break; |
4641 | ||
4642 | case 0x0fa4: | |
4643 | case 0x0fa5: | |
4644 | case 0x0fac: | |
4645 | case 0x0fad: | |
4646 | if (i386_record_modrm (&ir)) | |
4647 | return -1; | |
4648 | if (ir.mod == 3) | |
4649 | { | |
4650 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4651 | return -1; | |
4652 | } | |
4653 | else | |
4654 | { | |
4655 | if (i386_record_lea_modrm (&ir)) | |
4656 | return -1; | |
4657 | } | |
4658 | break; | |
4659 | ||
a38bba38 | 4660 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4661 | case 0xd9: |
4662 | case 0xda: | |
4663 | case 0xdb: | |
4664 | case 0xdc: | |
4665 | case 0xdd: | |
4666 | case 0xde: | |
4667 | case 0xdf: | |
4668 | if (i386_record_modrm (&ir)) | |
4669 | return -1; | |
4670 | ir.reg |= ((opcode & 7) << 3); | |
4671 | if (ir.mod != 3) | |
4672 | { | |
1777feb0 | 4673 | /* Memory. */ |
955db0c0 | 4674 | uint64_t addr64; |
7ad10968 | 4675 | |
955db0c0 | 4676 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
4677 | return -1; |
4678 | switch (ir.reg) | |
4679 | { | |
7ad10968 | 4680 | case 0x02: |
0289bdd7 MS |
4681 | case 0x12: |
4682 | case 0x22: | |
4683 | case 0x32: | |
4684 | /* For fcom, ficom nothing to do. */ | |
4685 | break; | |
7ad10968 | 4686 | case 0x03: |
0289bdd7 MS |
4687 | case 0x13: |
4688 | case 0x23: | |
4689 | case 0x33: | |
4690 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
4691 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4692 | return -1; | |
4693 | break; | |
4694 | case 0x00: | |
4695 | case 0x01: | |
7ad10968 HZ |
4696 | case 0x04: |
4697 | case 0x05: | |
4698 | case 0x06: | |
4699 | case 0x07: | |
4700 | case 0x10: | |
4701 | case 0x11: | |
7ad10968 HZ |
4702 | case 0x14: |
4703 | case 0x15: | |
4704 | case 0x16: | |
4705 | case 0x17: | |
4706 | case 0x20: | |
4707 | case 0x21: | |
7ad10968 HZ |
4708 | case 0x24: |
4709 | case 0x25: | |
4710 | case 0x26: | |
4711 | case 0x27: | |
4712 | case 0x30: | |
4713 | case 0x31: | |
7ad10968 HZ |
4714 | case 0x34: |
4715 | case 0x35: | |
4716 | case 0x36: | |
4717 | case 0x37: | |
0289bdd7 MS |
4718 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
4719 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
4720 | of code, always affects st(0) register. */ | |
4721 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4722 | return -1; | |
7ad10968 HZ |
4723 | break; |
4724 | case 0x08: | |
4725 | case 0x0a: | |
4726 | case 0x0b: | |
4727 | case 0x18: | |
4728 | case 0x19: | |
4729 | case 0x1a: | |
4730 | case 0x1b: | |
0289bdd7 | 4731 | case 0x1d: |
7ad10968 HZ |
4732 | case 0x28: |
4733 | case 0x29: | |
4734 | case 0x2a: | |
4735 | case 0x2b: | |
4736 | case 0x38: | |
4737 | case 0x39: | |
4738 | case 0x3a: | |
4739 | case 0x3b: | |
0289bdd7 MS |
4740 | case 0x3c: |
4741 | case 0x3d: | |
7ad10968 HZ |
4742 | switch (ir.reg & 7) |
4743 | { | |
4744 | case 0: | |
0289bdd7 MS |
4745 | /* Handling fld, fild. */ |
4746 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4747 | return -1; | |
7ad10968 HZ |
4748 | break; |
4749 | case 1: | |
4750 | switch (ir.reg >> 4) | |
4751 | { | |
4752 | case 0: | |
955db0c0 | 4753 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
4754 | return -1; |
4755 | break; | |
4756 | case 2: | |
955db0c0 | 4757 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
4758 | return -1; |
4759 | break; | |
4760 | case 3: | |
0289bdd7 | 4761 | break; |
7ad10968 | 4762 | default: |
955db0c0 | 4763 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
4764 | return -1; |
4765 | break; | |
4766 | } | |
4767 | break; | |
4768 | default: | |
4769 | switch (ir.reg >> 4) | |
4770 | { | |
4771 | case 0: | |
955db0c0 | 4772 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
4773 | return -1; |
4774 | if (3 == (ir.reg & 7)) | |
4775 | { | |
4776 | /* For fstp m32fp. */ | |
4777 | if (i386_record_floats (gdbarch, &ir, | |
4778 | I386_SAVE_FPU_REGS)) | |
4779 | return -1; | |
4780 | } | |
4781 | break; | |
7ad10968 | 4782 | case 1: |
955db0c0 | 4783 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 4784 | return -1; |
0289bdd7 MS |
4785 | if ((3 == (ir.reg & 7)) |
4786 | || (5 == (ir.reg & 7)) | |
4787 | || (7 == (ir.reg & 7))) | |
4788 | { | |
4789 | /* For fstp insn. */ | |
4790 | if (i386_record_floats (gdbarch, &ir, | |
4791 | I386_SAVE_FPU_REGS)) | |
4792 | return -1; | |
4793 | } | |
7ad10968 HZ |
4794 | break; |
4795 | case 2: | |
955db0c0 | 4796 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 4797 | return -1; |
0289bdd7 MS |
4798 | if (3 == (ir.reg & 7)) |
4799 | { | |
4800 | /* For fstp m64fp. */ | |
4801 | if (i386_record_floats (gdbarch, &ir, | |
4802 | I386_SAVE_FPU_REGS)) | |
4803 | return -1; | |
4804 | } | |
7ad10968 HZ |
4805 | break; |
4806 | case 3: | |
0289bdd7 MS |
4807 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
4808 | { | |
4809 | /* For fistp, fbld, fild, fbstp. */ | |
4810 | if (i386_record_floats (gdbarch, &ir, | |
4811 | I386_SAVE_FPU_REGS)) | |
4812 | return -1; | |
4813 | } | |
4814 | /* Fall through */ | |
7ad10968 | 4815 | default: |
955db0c0 | 4816 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
4817 | return -1; |
4818 | break; | |
4819 | } | |
4820 | break; | |
4821 | } | |
4822 | break; | |
4823 | case 0x0c: | |
0289bdd7 MS |
4824 | /* Insn fldenv. */ |
4825 | if (i386_record_floats (gdbarch, &ir, | |
4826 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4827 | return -1; | |
4828 | break; | |
7ad10968 | 4829 | case 0x0d: |
0289bdd7 MS |
4830 | /* Insn fldcw. */ |
4831 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
4832 | return -1; | |
4833 | break; | |
7ad10968 | 4834 | case 0x2c: |
0289bdd7 MS |
4835 | /* Insn frstor. */ |
4836 | if (i386_record_floats (gdbarch, &ir, | |
4837 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4838 | return -1; | |
7ad10968 HZ |
4839 | break; |
4840 | case 0x0e: | |
4841 | if (ir.dflag) | |
4842 | { | |
955db0c0 | 4843 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
4844 | return -1; |
4845 | } | |
4846 | else | |
4847 | { | |
955db0c0 | 4848 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
4849 | return -1; |
4850 | } | |
4851 | break; | |
4852 | case 0x0f: | |
4853 | case 0x2f: | |
955db0c0 | 4854 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 4855 | return -1; |
0289bdd7 MS |
4856 | /* Insn fstp, fbstp. */ |
4857 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4858 | return -1; | |
7ad10968 HZ |
4859 | break; |
4860 | case 0x1f: | |
4861 | case 0x3e: | |
955db0c0 | 4862 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
4863 | return -1; |
4864 | break; | |
4865 | case 0x2e: | |
4866 | if (ir.dflag) | |
4867 | { | |
955db0c0 | 4868 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 4869 | return -1; |
955db0c0 | 4870 | addr64 += 28; |
7ad10968 HZ |
4871 | } |
4872 | else | |
4873 | { | |
955db0c0 | 4874 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 4875 | return -1; |
955db0c0 | 4876 | addr64 += 14; |
7ad10968 | 4877 | } |
955db0c0 | 4878 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 4879 | return -1; |
0289bdd7 MS |
4880 | /* Insn fsave. */ |
4881 | if (i386_record_floats (gdbarch, &ir, | |
4882 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4883 | return -1; | |
7ad10968 HZ |
4884 | break; |
4885 | case 0x3f: | |
955db0c0 | 4886 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 4887 | return -1; |
0289bdd7 MS |
4888 | /* Insn fistp. */ |
4889 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4890 | return -1; | |
7ad10968 HZ |
4891 | break; |
4892 | default: | |
4893 | ir.addr -= 2; | |
4894 | opcode = opcode << 8 | ir.modrm; | |
4895 | goto no_support; | |
4896 | break; | |
4897 | } | |
4898 | } | |
0289bdd7 MS |
4899 | /* Opcode is an extension of modR/M byte. */ |
4900 | else | |
4901 | { | |
4902 | switch (opcode) | |
4903 | { | |
4904 | case 0xd8: | |
4905 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4906 | return -1; | |
4907 | break; | |
4908 | case 0xd9: | |
4909 | if (0x0c == (ir.modrm >> 4)) | |
4910 | { | |
4911 | if ((ir.modrm & 0x0f) <= 7) | |
4912 | { | |
4913 | if (i386_record_floats (gdbarch, &ir, | |
4914 | I386_SAVE_FPU_REGS)) | |
4915 | return -1; | |
4916 | } | |
4917 | else | |
4918 | { | |
4919 | if (i386_record_floats (gdbarch, &ir, | |
4920 | I387_ST0_REGNUM (tdep))) | |
4921 | return -1; | |
4922 | /* If only st(0) is changing, then we have already | |
4923 | recorded. */ | |
4924 | if ((ir.modrm & 0x0f) - 0x08) | |
4925 | { | |
4926 | if (i386_record_floats (gdbarch, &ir, | |
4927 | I387_ST0_REGNUM (tdep) + | |
4928 | ((ir.modrm & 0x0f) - 0x08))) | |
4929 | return -1; | |
4930 | } | |
4931 | } | |
4932 | } | |
4933 | else | |
4934 | { | |
4935 | switch (ir.modrm) | |
4936 | { | |
4937 | case 0xe0: | |
4938 | case 0xe1: | |
4939 | case 0xf0: | |
4940 | case 0xf5: | |
4941 | case 0xf8: | |
4942 | case 0xfa: | |
4943 | case 0xfc: | |
4944 | case 0xfe: | |
4945 | case 0xff: | |
4946 | if (i386_record_floats (gdbarch, &ir, | |
4947 | I387_ST0_REGNUM (tdep))) | |
4948 | return -1; | |
4949 | break; | |
4950 | case 0xf1: | |
4951 | case 0xf2: | |
4952 | case 0xf3: | |
4953 | case 0xf4: | |
4954 | case 0xf6: | |
4955 | case 0xf7: | |
4956 | case 0xe8: | |
4957 | case 0xe9: | |
4958 | case 0xea: | |
4959 | case 0xeb: | |
4960 | case 0xec: | |
4961 | case 0xed: | |
4962 | case 0xee: | |
4963 | case 0xf9: | |
4964 | case 0xfb: | |
4965 | if (i386_record_floats (gdbarch, &ir, | |
4966 | I386_SAVE_FPU_REGS)) | |
4967 | return -1; | |
4968 | break; | |
4969 | case 0xfd: | |
4970 | if (i386_record_floats (gdbarch, &ir, | |
4971 | I387_ST0_REGNUM (tdep))) | |
4972 | return -1; | |
4973 | if (i386_record_floats (gdbarch, &ir, | |
4974 | I387_ST0_REGNUM (tdep) + 1)) | |
4975 | return -1; | |
4976 | break; | |
4977 | } | |
4978 | } | |
4979 | break; | |
4980 | case 0xda: | |
4981 | if (0xe9 == ir.modrm) | |
4982 | { | |
4983 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4984 | return -1; | |
4985 | } | |
4986 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4987 | { | |
4988 | if (i386_record_floats (gdbarch, &ir, | |
4989 | I387_ST0_REGNUM (tdep))) | |
4990 | return -1; | |
4991 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4992 | { | |
4993 | if (i386_record_floats (gdbarch, &ir, | |
4994 | I387_ST0_REGNUM (tdep) + | |
4995 | (ir.modrm & 0x0f))) | |
4996 | return -1; | |
4997 | } | |
4998 | else if ((ir.modrm & 0x0f) - 0x08) | |
4999 | { | |
5000 | if (i386_record_floats (gdbarch, &ir, | |
5001 | I387_ST0_REGNUM (tdep) + | |
5002 | ((ir.modrm & 0x0f) - 0x08))) | |
5003 | return -1; | |
5004 | } | |
5005 | } | |
5006 | break; | |
5007 | case 0xdb: | |
5008 | if (0xe3 == ir.modrm) | |
5009 | { | |
5010 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
5011 | return -1; | |
5012 | } | |
5013 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5014 | { | |
5015 | if (i386_record_floats (gdbarch, &ir, | |
5016 | I387_ST0_REGNUM (tdep))) | |
5017 | return -1; | |
5018 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5019 | { | |
5020 | if (i386_record_floats (gdbarch, &ir, | |
5021 | I387_ST0_REGNUM (tdep) + | |
5022 | (ir.modrm & 0x0f))) | |
5023 | return -1; | |
5024 | } | |
5025 | else if ((ir.modrm & 0x0f) - 0x08) | |
5026 | { | |
5027 | if (i386_record_floats (gdbarch, &ir, | |
5028 | I387_ST0_REGNUM (tdep) + | |
5029 | ((ir.modrm & 0x0f) - 0x08))) | |
5030 | return -1; | |
5031 | } | |
5032 | } | |
5033 | break; | |
5034 | case 0xdc: | |
5035 | if ((0x0c == ir.modrm >> 4) | |
5036 | || (0x0d == ir.modrm >> 4) | |
5037 | || (0x0f == ir.modrm >> 4)) | |
5038 | { | |
5039 | if ((ir.modrm & 0x0f) <= 7) | |
5040 | { | |
5041 | if (i386_record_floats (gdbarch, &ir, | |
5042 | I387_ST0_REGNUM (tdep) + | |
5043 | (ir.modrm & 0x0f))) | |
5044 | return -1; | |
5045 | } | |
5046 | else | |
5047 | { | |
5048 | if (i386_record_floats (gdbarch, &ir, | |
5049 | I387_ST0_REGNUM (tdep) + | |
5050 | ((ir.modrm & 0x0f) - 0x08))) | |
5051 | return -1; | |
5052 | } | |
5053 | } | |
5054 | break; | |
5055 | case 0xdd: | |
5056 | if (0x0c == ir.modrm >> 4) | |
5057 | { | |
5058 | if (i386_record_floats (gdbarch, &ir, | |
5059 | I387_FTAG_REGNUM (tdep))) | |
5060 | return -1; | |
5061 | } | |
5062 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5063 | { | |
5064 | if ((ir.modrm & 0x0f) <= 7) | |
5065 | { | |
5066 | if (i386_record_floats (gdbarch, &ir, | |
5067 | I387_ST0_REGNUM (tdep) + | |
5068 | (ir.modrm & 0x0f))) | |
5069 | return -1; | |
5070 | } | |
5071 | else | |
5072 | { | |
5073 | if (i386_record_floats (gdbarch, &ir, | |
5074 | I386_SAVE_FPU_REGS)) | |
5075 | return -1; | |
5076 | } | |
5077 | } | |
5078 | break; | |
5079 | case 0xde: | |
5080 | if ((0x0c == ir.modrm >> 4) | |
5081 | || (0x0e == ir.modrm >> 4) | |
5082 | || (0x0f == ir.modrm >> 4) | |
5083 | || (0xd9 == ir.modrm)) | |
5084 | { | |
5085 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5086 | return -1; | |
5087 | } | |
5088 | break; | |
5089 | case 0xdf: | |
5090 | if (0xe0 == ir.modrm) | |
5091 | { | |
5092 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
5093 | return -1; | |
5094 | } | |
5095 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5096 | { | |
5097 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5098 | return -1; | |
5099 | } | |
5100 | break; | |
5101 | } | |
5102 | } | |
7ad10968 | 5103 | break; |
7ad10968 | 5104 | /* string ops */ |
a38bba38 | 5105 | case 0xa4: /* movsS */ |
7ad10968 | 5106 | case 0xa5: |
a38bba38 | 5107 | case 0xaa: /* stosS */ |
7ad10968 | 5108 | case 0xab: |
a38bba38 | 5109 | case 0x6c: /* insS */ |
7ad10968 | 5110 | case 0x6d: |
cf648174 | 5111 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5112 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5113 | &addr); |
5114 | if (addr) | |
cf648174 | 5115 | { |
77d7dc92 HZ |
5116 | ULONGEST es, ds; |
5117 | ||
5118 | if ((opcode & 1) == 0) | |
5119 | ir.ot = OT_BYTE; | |
5120 | else | |
5121 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5122 | regcache_raw_read_unsigned (ir.regcache, |
5123 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5124 | &addr); |
77d7dc92 | 5125 | |
d7877f7e HZ |
5126 | regcache_raw_read_unsigned (ir.regcache, |
5127 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5128 | &es); | |
5129 | regcache_raw_read_unsigned (ir.regcache, | |
5130 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5131 | &ds); | |
5132 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5133 | { |
5134 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
bb08c432 HZ |
5135 | if (record_memory_query) |
5136 | { | |
5137 | int q; | |
5138 | ||
5139 | target_terminal_ours (); | |
5140 | q = yquery (_("\ | |
5141 | Process record ignores the memory change of instruction at address %s\n\ | |
5142 | because it can't get the value of the segment register.\n\ | |
5143 | Do you want to stop the program?"), | |
5144 | paddress (gdbarch, ir.orig_addr)); | |
5145 | target_terminal_inferior (); | |
5146 | if (q) | |
5147 | return -1; | |
5148 | } | |
df61f520 HZ |
5149 | } |
5150 | else | |
5151 | { | |
648d0c8b | 5152 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5153 | return -1; |
77d7dc92 HZ |
5154 | } |
5155 | ||
5156 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5157 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
5158 | if (opcode == 0xa4 || opcode == 0xa5) |
5159 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5160 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5161 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5162 | } | |
cf648174 | 5163 | break; |
7ad10968 | 5164 | |
a38bba38 | 5165 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
5166 | case 0xa7: |
5167 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5168 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5169 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5170 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5171 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5172 | break; |
5173 | ||
a38bba38 | 5174 | case 0xac: /* lodsS */ |
7ad10968 | 5175 | case 0xad: |
cf648174 HZ |
5176 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5177 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5178 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5179 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5180 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5181 | break; |
5182 | ||
a38bba38 | 5183 | case 0xae: /* scasS */ |
7ad10968 | 5184 | case 0xaf: |
cf648174 | 5185 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 5186 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5187 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5188 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5189 | break; |
5190 | ||
a38bba38 | 5191 | case 0x6e: /* outsS */ |
cf648174 HZ |
5192 | case 0x6f: |
5193 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5194 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5195 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5196 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5197 | break; |
5198 | ||
a38bba38 | 5199 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
5200 | case 0xe5: |
5201 | case 0xec: | |
5202 | case 0xed: | |
cf648174 HZ |
5203 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5204 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5205 | break; |
5206 | ||
5207 | case 0xe6: | |
5208 | case 0xe7: | |
5209 | case 0xee: | |
5210 | case 0xef: | |
5211 | break; | |
5212 | ||
5213 | /* control */ | |
a38bba38 MS |
5214 | case 0xc2: /* ret im */ |
5215 | case 0xc3: /* ret */ | |
cf648174 HZ |
5216 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5217 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5218 | break; | |
5219 | ||
a38bba38 MS |
5220 | case 0xca: /* lret im */ |
5221 | case 0xcb: /* lret */ | |
5222 | case 0xcf: /* iret */ | |
cf648174 HZ |
5223 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
5224 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5225 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5226 | break; |
5227 | ||
a38bba38 | 5228 | case 0xe8: /* call im */ |
cf648174 HZ |
5229 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5230 | ir.dflag = 2; | |
5231 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5232 | return -1; | |
7ad10968 HZ |
5233 | break; |
5234 | ||
a38bba38 | 5235 | case 0x9a: /* lcall im */ |
cf648174 HZ |
5236 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5237 | { | |
5238 | ir.addr -= 1; | |
5239 | goto no_support; | |
5240 | } | |
5241 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
5242 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5243 | return -1; | |
7ad10968 HZ |
5244 | break; |
5245 | ||
a38bba38 MS |
5246 | case 0xe9: /* jmp im */ |
5247 | case 0xea: /* ljmp im */ | |
5248 | case 0xeb: /* jmp Jb */ | |
5249 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
5250 | case 0x71: |
5251 | case 0x72: | |
5252 | case 0x73: | |
5253 | case 0x74: | |
5254 | case 0x75: | |
5255 | case 0x76: | |
5256 | case 0x77: | |
5257 | case 0x78: | |
5258 | case 0x79: | |
5259 | case 0x7a: | |
5260 | case 0x7b: | |
5261 | case 0x7c: | |
5262 | case 0x7d: | |
5263 | case 0x7e: | |
5264 | case 0x7f: | |
a38bba38 | 5265 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
5266 | case 0x0f81: |
5267 | case 0x0f82: | |
5268 | case 0x0f83: | |
5269 | case 0x0f84: | |
5270 | case 0x0f85: | |
5271 | case 0x0f86: | |
5272 | case 0x0f87: | |
5273 | case 0x0f88: | |
5274 | case 0x0f89: | |
5275 | case 0x0f8a: | |
5276 | case 0x0f8b: | |
5277 | case 0x0f8c: | |
5278 | case 0x0f8d: | |
5279 | case 0x0f8e: | |
5280 | case 0x0f8f: | |
5281 | break; | |
5282 | ||
a38bba38 | 5283 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
5284 | case 0x0f91: |
5285 | case 0x0f92: | |
5286 | case 0x0f93: | |
5287 | case 0x0f94: | |
5288 | case 0x0f95: | |
5289 | case 0x0f96: | |
5290 | case 0x0f97: | |
5291 | case 0x0f98: | |
5292 | case 0x0f99: | |
5293 | case 0x0f9a: | |
5294 | case 0x0f9b: | |
5295 | case 0x0f9c: | |
5296 | case 0x0f9d: | |
5297 | case 0x0f9e: | |
5298 | case 0x0f9f: | |
cf648174 | 5299 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5300 | ir.ot = OT_BYTE; |
5301 | if (i386_record_modrm (&ir)) | |
5302 | return -1; | |
5303 | if (ir.mod == 3) | |
cf648174 HZ |
5304 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
5305 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
5306 | else |
5307 | { | |
5308 | if (i386_record_lea_modrm (&ir)) | |
5309 | return -1; | |
5310 | } | |
5311 | break; | |
5312 | ||
a38bba38 | 5313 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
5314 | case 0x0f41: |
5315 | case 0x0f42: | |
5316 | case 0x0f43: | |
5317 | case 0x0f44: | |
5318 | case 0x0f45: | |
5319 | case 0x0f46: | |
5320 | case 0x0f47: | |
5321 | case 0x0f48: | |
5322 | case 0x0f49: | |
5323 | case 0x0f4a: | |
5324 | case 0x0f4b: | |
5325 | case 0x0f4c: | |
5326 | case 0x0f4d: | |
5327 | case 0x0f4e: | |
5328 | case 0x0f4f: | |
5329 | if (i386_record_modrm (&ir)) | |
5330 | return -1; | |
cf648174 | 5331 | ir.reg |= rex_r; |
7ad10968 HZ |
5332 | if (ir.dflag == OT_BYTE) |
5333 | ir.reg &= 0x3; | |
cf648174 | 5334 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5335 | break; |
5336 | ||
5337 | /* flags */ | |
a38bba38 | 5338 | case 0x9c: /* pushf */ |
cf648174 HZ |
5339 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5340 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
5341 | ir.dflag = 2; | |
5342 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5343 | return -1; | |
7ad10968 HZ |
5344 | break; |
5345 | ||
a38bba38 | 5346 | case 0x9d: /* popf */ |
cf648174 HZ |
5347 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5348 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5349 | break; |
5350 | ||
a38bba38 | 5351 | case 0x9e: /* sahf */ |
cf648174 HZ |
5352 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5353 | { | |
5354 | ir.addr -= 1; | |
5355 | goto no_support; | |
5356 | } | |
d3f323f3 | 5357 | /* FALLTHROUGH */ |
a38bba38 MS |
5358 | case 0xf5: /* cmc */ |
5359 | case 0xf8: /* clc */ | |
5360 | case 0xf9: /* stc */ | |
5361 | case 0xfc: /* cld */ | |
5362 | case 0xfd: /* std */ | |
cf648174 | 5363 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5364 | break; |
5365 | ||
a38bba38 | 5366 | case 0x9f: /* lahf */ |
cf648174 HZ |
5367 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5368 | { | |
5369 | ir.addr -= 1; | |
5370 | goto no_support; | |
5371 | } | |
5372 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5373 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5374 | break; |
5375 | ||
5376 | /* bit operations */ | |
a38bba38 | 5377 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
5378 | ir.ot = ir.dflag + OT_WORD; |
5379 | if (i386_record_modrm (&ir)) | |
5380 | return -1; | |
5381 | if (ir.reg < 4) | |
5382 | { | |
cf648174 | 5383 | ir.addr -= 2; |
7ad10968 HZ |
5384 | opcode = opcode << 8 | ir.modrm; |
5385 | goto no_support; | |
5386 | } | |
cf648174 | 5387 | if (ir.reg != 4) |
7ad10968 | 5388 | { |
cf648174 HZ |
5389 | if (ir.mod == 3) |
5390 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
5391 | else |
5392 | { | |
cf648174 | 5393 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
5394 | return -1; |
5395 | } | |
5396 | } | |
cf648174 | 5397 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5398 | break; |
5399 | ||
a38bba38 | 5400 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5401 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5402 | break; | |
5403 | ||
a38bba38 MS |
5404 | case 0x0fab: /* bts */ |
5405 | case 0x0fb3: /* btr */ | |
5406 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5407 | ir.ot = ir.dflag + OT_WORD; |
5408 | if (i386_record_modrm (&ir)) | |
5409 | return -1; | |
5410 | if (ir.mod == 3) | |
5411 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
5412 | else | |
5413 | { | |
955db0c0 MS |
5414 | uint64_t addr64; |
5415 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
5416 | return -1; |
5417 | regcache_raw_read_unsigned (ir.regcache, | |
5418 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 5419 | &addr); |
cf648174 HZ |
5420 | switch (ir.dflag) |
5421 | { | |
5422 | case 0: | |
648d0c8b | 5423 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
5424 | break; |
5425 | case 1: | |
648d0c8b | 5426 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
5427 | break; |
5428 | case 2: | |
648d0c8b | 5429 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
5430 | break; |
5431 | } | |
955db0c0 | 5432 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
5433 | return -1; |
5434 | if (i386_record_lea_modrm (&ir)) | |
5435 | return -1; | |
5436 | } | |
5437 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5438 | break; |
5439 | ||
a38bba38 MS |
5440 | case 0x0fbc: /* bsf */ |
5441 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
5442 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5443 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5444 | break; |
5445 | ||
5446 | /* bcd */ | |
a38bba38 MS |
5447 | case 0x27: /* daa */ |
5448 | case 0x2f: /* das */ | |
5449 | case 0x37: /* aaa */ | |
5450 | case 0x3f: /* aas */ | |
5451 | case 0xd4: /* aam */ | |
5452 | case 0xd5: /* aad */ | |
cf648174 HZ |
5453 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5454 | { | |
5455 | ir.addr -= 1; | |
5456 | goto no_support; | |
5457 | } | |
5458 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5459 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5460 | break; |
5461 | ||
5462 | /* misc */ | |
a38bba38 | 5463 | case 0x90: /* nop */ |
7ad10968 HZ |
5464 | if (prefixes & PREFIX_LOCK) |
5465 | { | |
5466 | ir.addr -= 1; | |
5467 | goto no_support; | |
5468 | } | |
5469 | break; | |
5470 | ||
a38bba38 | 5471 | case 0x9b: /* fwait */ |
425b824a | 5472 | if (target_read_memory (ir.addr, &opcode8, 1)) |
0289bdd7 MS |
5473 | { |
5474 | if (record_debug) | |
5475 | printf_unfiltered (_("Process record: error reading memory at " | |
5476 | "addr 0x%s len = 1.\n"), | |
5477 | paddress (gdbarch, ir.addr)); | |
5478 | return -1; | |
5479 | } | |
425b824a | 5480 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
5481 | ir.addr++; |
5482 | goto reswitch; | |
7ad10968 HZ |
5483 | break; |
5484 | ||
7ad10968 | 5485 | /* XXX */ |
a38bba38 | 5486 | case 0xcc: /* int3 */ |
a3c4230a | 5487 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
5488 | "int3.\n")); |
5489 | ir.addr -= 1; | |
5490 | goto no_support; | |
5491 | break; | |
5492 | ||
7ad10968 | 5493 | /* XXX */ |
a38bba38 | 5494 | case 0xcd: /* int */ |
7ad10968 HZ |
5495 | { |
5496 | int ret; | |
425b824a MS |
5497 | uint8_t interrupt; |
5498 | if (target_read_memory (ir.addr, &interrupt, 1)) | |
7ad10968 HZ |
5499 | { |
5500 | if (record_debug) | |
5501 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
5502 | "at addr %s len = 1.\n"), |
5503 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5504 | return -1; |
5505 | } | |
5506 | ir.addr++; | |
425b824a | 5507 | if (interrupt != 0x80 |
a3c4230a | 5508 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 5509 | { |
a3c4230a | 5510 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 5511 | "instruction int 0x%02x.\n"), |
425b824a | 5512 | interrupt); |
7ad10968 HZ |
5513 | ir.addr -= 2; |
5514 | goto no_support; | |
5515 | } | |
a3c4230a | 5516 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
5517 | if (ret) |
5518 | return ret; | |
5519 | } | |
5520 | break; | |
5521 | ||
7ad10968 | 5522 | /* XXX */ |
a38bba38 | 5523 | case 0xce: /* into */ |
a3c4230a | 5524 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5525 | "instruction into.\n")); |
5526 | ir.addr -= 1; | |
5527 | goto no_support; | |
5528 | break; | |
5529 | ||
a38bba38 MS |
5530 | case 0xfa: /* cli */ |
5531 | case 0xfb: /* sti */ | |
7ad10968 HZ |
5532 | break; |
5533 | ||
a38bba38 | 5534 | case 0x62: /* bound */ |
a3c4230a | 5535 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5536 | "instruction bound.\n")); |
5537 | ir.addr -= 1; | |
5538 | goto no_support; | |
5539 | break; | |
5540 | ||
a38bba38 | 5541 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5542 | case 0x0fc9: |
5543 | case 0x0fca: | |
5544 | case 0x0fcb: | |
5545 | case 0x0fcc: | |
5546 | case 0x0fcd: | |
5547 | case 0x0fce: | |
5548 | case 0x0fcf: | |
cf648174 | 5549 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5550 | break; |
5551 | ||
a38bba38 | 5552 | case 0xd6: /* salc */ |
cf648174 HZ |
5553 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5554 | { | |
5555 | ir.addr -= 1; | |
5556 | goto no_support; | |
5557 | } | |
5558 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5559 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5560 | break; |
5561 | ||
a38bba38 MS |
5562 | case 0xe0: /* loopnz */ |
5563 | case 0xe1: /* loopz */ | |
5564 | case 0xe2: /* loop */ | |
5565 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5566 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5567 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5568 | break; |
5569 | ||
a38bba38 | 5570 | case 0x0f30: /* wrmsr */ |
a3c4230a | 5571 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5572 | "instruction wrmsr.\n")); |
5573 | ir.addr -= 2; | |
5574 | goto no_support; | |
5575 | break; | |
5576 | ||
a38bba38 | 5577 | case 0x0f32: /* rdmsr */ |
a3c4230a | 5578 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5579 | "instruction rdmsr.\n")); |
5580 | ir.addr -= 2; | |
5581 | goto no_support; | |
5582 | break; | |
5583 | ||
a38bba38 | 5584 | case 0x0f31: /* rdtsc */ |
f8c4f480 HZ |
5585 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5586 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5587 | break; |
5588 | ||
a38bba38 | 5589 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5590 | { |
5591 | int ret; | |
cf648174 HZ |
5592 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5593 | { | |
5594 | ir.addr -= 2; | |
5595 | goto no_support; | |
5596 | } | |
a3c4230a | 5597 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 5598 | { |
a3c4230a | 5599 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5600 | "instruction sysenter.\n")); |
5601 | ir.addr -= 2; | |
5602 | goto no_support; | |
5603 | } | |
a3c4230a | 5604 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
5605 | if (ret) |
5606 | return ret; | |
5607 | } | |
5608 | break; | |
5609 | ||
a38bba38 | 5610 | case 0x0f35: /* sysexit */ |
a3c4230a | 5611 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5612 | "instruction sysexit.\n")); |
5613 | ir.addr -= 2; | |
5614 | goto no_support; | |
5615 | break; | |
5616 | ||
a38bba38 | 5617 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5618 | { |
5619 | int ret; | |
a3c4230a | 5620 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 5621 | { |
a3c4230a | 5622 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5623 | "instruction syscall.\n")); |
5624 | ir.addr -= 2; | |
5625 | goto no_support; | |
5626 | } | |
a3c4230a | 5627 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
5628 | if (ret) |
5629 | return ret; | |
5630 | } | |
5631 | break; | |
5632 | ||
a38bba38 | 5633 | case 0x0f07: /* sysret */ |
a3c4230a | 5634 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5635 | "instruction sysret.\n")); |
5636 | ir.addr -= 2; | |
5637 | goto no_support; | |
5638 | break; | |
5639 | ||
a38bba38 | 5640 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5641 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5642 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5643 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5644 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5645 | break; |
5646 | ||
a38bba38 | 5647 | case 0xf4: /* hlt */ |
a3c4230a | 5648 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5649 | "instruction hlt.\n")); |
5650 | ir.addr -= 1; | |
5651 | goto no_support; | |
5652 | break; | |
5653 | ||
5654 | case 0x0f00: | |
5655 | if (i386_record_modrm (&ir)) | |
5656 | return -1; | |
5657 | switch (ir.reg) | |
5658 | { | |
a38bba38 MS |
5659 | case 0: /* sldt */ |
5660 | case 1: /* str */ | |
7ad10968 | 5661 | if (ir.mod == 3) |
cf648174 | 5662 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5663 | else |
5664 | { | |
5665 | ir.ot = OT_WORD; | |
5666 | if (i386_record_lea_modrm (&ir)) | |
5667 | return -1; | |
5668 | } | |
5669 | break; | |
a38bba38 MS |
5670 | case 2: /* lldt */ |
5671 | case 3: /* ltr */ | |
7ad10968 | 5672 | break; |
a38bba38 MS |
5673 | case 4: /* verr */ |
5674 | case 5: /* verw */ | |
cf648174 | 5675 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5676 | break; |
5677 | default: | |
5678 | ir.addr -= 3; | |
5679 | opcode = opcode << 8 | ir.modrm; | |
5680 | goto no_support; | |
5681 | break; | |
5682 | } | |
5683 | break; | |
5684 | ||
5685 | case 0x0f01: | |
5686 | if (i386_record_modrm (&ir)) | |
5687 | return -1; | |
5688 | switch (ir.reg) | |
5689 | { | |
a38bba38 | 5690 | case 0: /* sgdt */ |
7ad10968 | 5691 | { |
955db0c0 | 5692 | uint64_t addr64; |
7ad10968 HZ |
5693 | |
5694 | if (ir.mod == 3) | |
5695 | { | |
5696 | ir.addr -= 3; | |
5697 | opcode = opcode << 8 | ir.modrm; | |
5698 | goto no_support; | |
5699 | } | |
d7877f7e | 5700 | if (ir.override >= 0) |
7ad10968 | 5701 | { |
bb08c432 HZ |
5702 | if (record_memory_query) |
5703 | { | |
5704 | int q; | |
5705 | ||
5706 | target_terminal_ours (); | |
5707 | q = yquery (_("\ | |
5708 | Process record ignores the memory change of instruction at address %s\n\ | |
5709 | because it can't get the value of the segment register.\n\ | |
5710 | Do you want to stop the program?"), | |
5711 | paddress (gdbarch, ir.orig_addr)); | |
5712 | target_terminal_inferior (); | |
5713 | if (q) | |
5714 | return -1; | |
5715 | } | |
7ad10968 HZ |
5716 | } |
5717 | else | |
5718 | { | |
955db0c0 | 5719 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5720 | return -1; |
955db0c0 | 5721 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5722 | return -1; |
955db0c0 | 5723 | addr64 += 2; |
cf648174 HZ |
5724 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5725 | { | |
955db0c0 | 5726 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5727 | return -1; |
5728 | } | |
5729 | else | |
5730 | { | |
955db0c0 | 5731 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5732 | return -1; |
5733 | } | |
7ad10968 HZ |
5734 | } |
5735 | } | |
5736 | break; | |
5737 | case 1: | |
5738 | if (ir.mod == 3) | |
5739 | { | |
5740 | switch (ir.rm) | |
5741 | { | |
a38bba38 | 5742 | case 0: /* monitor */ |
7ad10968 | 5743 | break; |
a38bba38 | 5744 | case 1: /* mwait */ |
cf648174 | 5745 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5746 | break; |
5747 | default: | |
5748 | ir.addr -= 3; | |
5749 | opcode = opcode << 8 | ir.modrm; | |
5750 | goto no_support; | |
5751 | break; | |
5752 | } | |
5753 | } | |
5754 | else | |
5755 | { | |
5756 | /* sidt */ | |
d7877f7e | 5757 | if (ir.override >= 0) |
7ad10968 | 5758 | { |
bb08c432 HZ |
5759 | if (record_memory_query) |
5760 | { | |
5761 | int q; | |
5762 | ||
5763 | target_terminal_ours (); | |
5764 | q = yquery (_("\ | |
5765 | Process record ignores the memory change of instruction at address %s\n\ | |
5766 | because it can't get the value of the segment register.\n\ | |
5767 | Do you want to stop the program?"), | |
5768 | paddress (gdbarch, ir.orig_addr)); | |
5769 | target_terminal_inferior (); | |
5770 | if (q) | |
5771 | return -1; | |
5772 | } | |
7ad10968 HZ |
5773 | } |
5774 | else | |
5775 | { | |
955db0c0 | 5776 | uint64_t addr64; |
7ad10968 | 5777 | |
955db0c0 | 5778 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5779 | return -1; |
955db0c0 | 5780 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5781 | return -1; |
955db0c0 | 5782 | addr64 += 2; |
cf648174 HZ |
5783 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5784 | { | |
955db0c0 | 5785 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5786 | return -1; |
5787 | } | |
5788 | else | |
5789 | { | |
955db0c0 | 5790 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5791 | return -1; |
5792 | } | |
7ad10968 HZ |
5793 | } |
5794 | } | |
5795 | break; | |
a38bba38 | 5796 | case 2: /* lgdt */ |
3800e645 MS |
5797 | if (ir.mod == 3) |
5798 | { | |
5799 | /* xgetbv */ | |
5800 | if (ir.rm == 0) | |
5801 | { | |
5802 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5803 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5804 | break; | |
5805 | } | |
5806 | /* xsetbv */ | |
5807 | else if (ir.rm == 1) | |
5808 | break; | |
5809 | } | |
a38bba38 | 5810 | case 3: /* lidt */ |
7ad10968 HZ |
5811 | if (ir.mod == 3) |
5812 | { | |
5813 | ir.addr -= 3; | |
5814 | opcode = opcode << 8 | ir.modrm; | |
5815 | goto no_support; | |
5816 | } | |
5817 | break; | |
a38bba38 | 5818 | case 4: /* smsw */ |
7ad10968 HZ |
5819 | if (ir.mod == 3) |
5820 | { | |
cf648174 | 5821 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
5822 | return -1; |
5823 | } | |
5824 | else | |
5825 | { | |
5826 | ir.ot = OT_WORD; | |
5827 | if (i386_record_lea_modrm (&ir)) | |
5828 | return -1; | |
5829 | } | |
cf648174 | 5830 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5831 | break; |
a38bba38 | 5832 | case 6: /* lmsw */ |
cf648174 HZ |
5833 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5834 | break; | |
a38bba38 | 5835 | case 7: /* invlpg */ |
cf648174 HZ |
5836 | if (ir.mod == 3) |
5837 | { | |
5838 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
5839 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5840 | else | |
5841 | { | |
5842 | ir.addr -= 3; | |
5843 | opcode = opcode << 8 | ir.modrm; | |
5844 | goto no_support; | |
5845 | } | |
5846 | } | |
5847 | else | |
5848 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5849 | break; | |
5850 | default: | |
5851 | ir.addr -= 3; | |
5852 | opcode = opcode << 8 | ir.modrm; | |
5853 | goto no_support; | |
7ad10968 HZ |
5854 | break; |
5855 | } | |
5856 | break; | |
5857 | ||
a38bba38 MS |
5858 | case 0x0f08: /* invd */ |
5859 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
5860 | break; |
5861 | ||
a38bba38 | 5862 | case 0x63: /* arpl */ |
7ad10968 HZ |
5863 | if (i386_record_modrm (&ir)) |
5864 | return -1; | |
cf648174 HZ |
5865 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
5866 | { | |
5867 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
5868 | ? (ir.reg | rex_r) : ir.rm); | |
5869 | } | |
7ad10968 | 5870 | else |
cf648174 HZ |
5871 | { |
5872 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
5873 | if (i386_record_lea_modrm (&ir)) | |
5874 | return -1; | |
5875 | } | |
5876 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
5877 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5878 | break; |
5879 | ||
a38bba38 MS |
5880 | case 0x0f02: /* lar */ |
5881 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
5882 | if (i386_record_modrm (&ir)) |
5883 | return -1; | |
cf648174 HZ |
5884 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5885 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5886 | break; |
5887 | ||
5888 | case 0x0f18: | |
cf648174 HZ |
5889 | if (i386_record_modrm (&ir)) |
5890 | return -1; | |
5891 | if (ir.mod == 3 && ir.reg == 3) | |
5892 | { | |
5893 | ir.addr -= 3; | |
5894 | opcode = opcode << 8 | ir.modrm; | |
5895 | goto no_support; | |
5896 | } | |
7ad10968 HZ |
5897 | break; |
5898 | ||
7ad10968 HZ |
5899 | case 0x0f19: |
5900 | case 0x0f1a: | |
5901 | case 0x0f1b: | |
5902 | case 0x0f1c: | |
5903 | case 0x0f1d: | |
5904 | case 0x0f1e: | |
5905 | case 0x0f1f: | |
a38bba38 | 5906 | /* nop (multi byte) */ |
7ad10968 HZ |
5907 | break; |
5908 | ||
a38bba38 MS |
5909 | case 0x0f20: /* mov reg, crN */ |
5910 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
5911 | if (i386_record_modrm (&ir)) |
5912 | return -1; | |
5913 | if ((ir.modrm & 0xc0) != 0xc0) | |
5914 | { | |
cf648174 | 5915 | ir.addr -= 3; |
7ad10968 HZ |
5916 | opcode = opcode << 8 | ir.modrm; |
5917 | goto no_support; | |
5918 | } | |
5919 | switch (ir.reg) | |
5920 | { | |
5921 | case 0: | |
5922 | case 2: | |
5923 | case 3: | |
5924 | case 4: | |
5925 | case 8: | |
5926 | if (opcode & 2) | |
cf648174 | 5927 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5928 | else |
cf648174 | 5929 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5930 | break; |
5931 | default: | |
cf648174 | 5932 | ir.addr -= 3; |
7ad10968 HZ |
5933 | opcode = opcode << 8 | ir.modrm; |
5934 | goto no_support; | |
5935 | break; | |
5936 | } | |
5937 | break; | |
5938 | ||
a38bba38 MS |
5939 | case 0x0f21: /* mov reg, drN */ |
5940 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
5941 | if (i386_record_modrm (&ir)) |
5942 | return -1; | |
5943 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
5944 | || ir.reg == 5 || ir.reg >= 8) | |
5945 | { | |
cf648174 | 5946 | ir.addr -= 3; |
7ad10968 HZ |
5947 | opcode = opcode << 8 | ir.modrm; |
5948 | goto no_support; | |
5949 | } | |
5950 | if (opcode & 2) | |
cf648174 | 5951 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5952 | else |
cf648174 | 5953 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5954 | break; |
5955 | ||
a38bba38 | 5956 | case 0x0f06: /* clts */ |
cf648174 | 5957 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5958 | break; |
5959 | ||
a3c4230a HZ |
5960 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
5961 | ||
5962 | case 0x0f0d: /* 3DNow! prefetch */ | |
5963 | break; | |
5964 | ||
5965 | case 0x0f0e: /* 3DNow! femms */ | |
5966 | case 0x0f77: /* emms */ | |
5967 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
5968 | goto no_support; | |
5969 | record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); | |
5970 | break; | |
5971 | ||
5972 | case 0x0f0f: /* 3DNow! data */ | |
5973 | if (i386_record_modrm (&ir)) | |
5974 | return -1; | |
5975 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
5976 | { | |
5977 | printf_unfiltered (_("Process record: error reading memory at " | |
5978 | "addr %s len = 1.\n"), | |
5979 | paddress (gdbarch, ir.addr)); | |
5980 | return -1; | |
5981 | } | |
5982 | ir.addr++; | |
5983 | switch (opcode8) | |
5984 | { | |
5985 | case 0x0c: /* 3DNow! pi2fw */ | |
5986 | case 0x0d: /* 3DNow! pi2fd */ | |
5987 | case 0x1c: /* 3DNow! pf2iw */ | |
5988 | case 0x1d: /* 3DNow! pf2id */ | |
5989 | case 0x8a: /* 3DNow! pfnacc */ | |
5990 | case 0x8e: /* 3DNow! pfpnacc */ | |
5991 | case 0x90: /* 3DNow! pfcmpge */ | |
5992 | case 0x94: /* 3DNow! pfmin */ | |
5993 | case 0x96: /* 3DNow! pfrcp */ | |
5994 | case 0x97: /* 3DNow! pfrsqrt */ | |
5995 | case 0x9a: /* 3DNow! pfsub */ | |
5996 | case 0x9e: /* 3DNow! pfadd */ | |
5997 | case 0xa0: /* 3DNow! pfcmpgt */ | |
5998 | case 0xa4: /* 3DNow! pfmax */ | |
5999 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
6000 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
6001 | case 0xaa: /* 3DNow! pfsubr */ | |
6002 | case 0xae: /* 3DNow! pfacc */ | |
6003 | case 0xb0: /* 3DNow! pfcmpeq */ | |
6004 | case 0xb4: /* 3DNow! pfmul */ | |
6005 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
6006 | case 0xb7: /* 3DNow! pmulhrw */ | |
6007 | case 0xbb: /* 3DNow! pswapd */ | |
6008 | case 0xbf: /* 3DNow! pavgusb */ | |
6009 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6010 | goto no_support_3dnow_data; | |
6011 | record_arch_list_add_reg (ir.regcache, ir.reg); | |
6012 | break; | |
6013 | ||
6014 | default: | |
6015 | no_support_3dnow_data: | |
6016 | opcode = (opcode << 8) | opcode8; | |
6017 | goto no_support; | |
6018 | break; | |
6019 | } | |
6020 | break; | |
6021 | ||
6022 | case 0x0faa: /* rsm */ | |
6023 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6024 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6025 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6026 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6027 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
6028 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6029 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
6030 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6031 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6032 | break; | |
6033 | ||
6034 | case 0x0fae: | |
6035 | if (i386_record_modrm (&ir)) | |
6036 | return -1; | |
6037 | switch(ir.reg) | |
6038 | { | |
6039 | case 0: /* fxsave */ | |
6040 | { | |
6041 | uint64_t tmpu64; | |
6042 | ||
6043 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6044 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
6045 | return -1; | |
6046 | if (record_arch_list_add_mem (tmpu64, 512)) | |
6047 | return -1; | |
6048 | } | |
6049 | break; | |
6050 | ||
6051 | case 1: /* fxrstor */ | |
6052 | { | |
6053 | int i; | |
6054 | ||
6055 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6056 | ||
6057 | for (i = I387_MM0_REGNUM (tdep); | |
6058 | i386_mmx_regnum_p (gdbarch, i); i++) | |
6059 | record_arch_list_add_reg (ir.regcache, i); | |
6060 | ||
6061 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 6062 | i386_xmm_regnum_p (gdbarch, i); i++) |
a3c4230a HZ |
6063 | record_arch_list_add_reg (ir.regcache, i); |
6064 | ||
6065 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6066 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6067 | ||
6068 | for (i = I387_ST0_REGNUM (tdep); | |
6069 | i386_fp_regnum_p (gdbarch, i); i++) | |
6070 | record_arch_list_add_reg (ir.regcache, i); | |
6071 | ||
6072 | for (i = I387_FCTRL_REGNUM (tdep); | |
6073 | i386_fpc_regnum_p (gdbarch, i); i++) | |
6074 | record_arch_list_add_reg (ir.regcache, i); | |
6075 | } | |
6076 | break; | |
6077 | ||
6078 | case 2: /* ldmxcsr */ | |
6079 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6080 | goto no_support; | |
6081 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6082 | break; | |
6083 | ||
6084 | case 3: /* stmxcsr */ | |
6085 | ir.ot = OT_LONG; | |
6086 | if (i386_record_lea_modrm (&ir)) | |
6087 | return -1; | |
6088 | break; | |
6089 | ||
6090 | case 5: /* lfence */ | |
6091 | case 6: /* mfence */ | |
6092 | case 7: /* sfence clflush */ | |
6093 | break; | |
6094 | ||
6095 | default: | |
6096 | opcode = (opcode << 8) | ir.modrm; | |
6097 | goto no_support; | |
6098 | break; | |
6099 | } | |
6100 | break; | |
6101 | ||
6102 | case 0x0fc3: /* movnti */ | |
6103 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
6104 | if (i386_record_modrm (&ir)) | |
6105 | return -1; | |
6106 | if (ir.mod == 3) | |
6107 | goto no_support; | |
6108 | ir.reg |= rex_r; | |
6109 | if (i386_record_lea_modrm (&ir)) | |
6110 | return -1; | |
6111 | break; | |
6112 | ||
6113 | /* Add prefix to opcode. */ | |
6114 | case 0x0f10: | |
6115 | case 0x0f11: | |
6116 | case 0x0f12: | |
6117 | case 0x0f13: | |
6118 | case 0x0f14: | |
6119 | case 0x0f15: | |
6120 | case 0x0f16: | |
6121 | case 0x0f17: | |
6122 | case 0x0f28: | |
6123 | case 0x0f29: | |
6124 | case 0x0f2a: | |
6125 | case 0x0f2b: | |
6126 | case 0x0f2c: | |
6127 | case 0x0f2d: | |
6128 | case 0x0f2e: | |
6129 | case 0x0f2f: | |
6130 | case 0x0f38: | |
6131 | case 0x0f39: | |
6132 | case 0x0f3a: | |
6133 | case 0x0f50: | |
6134 | case 0x0f51: | |
6135 | case 0x0f52: | |
6136 | case 0x0f53: | |
6137 | case 0x0f54: | |
6138 | case 0x0f55: | |
6139 | case 0x0f56: | |
6140 | case 0x0f57: | |
6141 | case 0x0f58: | |
6142 | case 0x0f59: | |
6143 | case 0x0f5a: | |
6144 | case 0x0f5b: | |
6145 | case 0x0f5c: | |
6146 | case 0x0f5d: | |
6147 | case 0x0f5e: | |
6148 | case 0x0f5f: | |
6149 | case 0x0f60: | |
6150 | case 0x0f61: | |
6151 | case 0x0f62: | |
6152 | case 0x0f63: | |
6153 | case 0x0f64: | |
6154 | case 0x0f65: | |
6155 | case 0x0f66: | |
6156 | case 0x0f67: | |
6157 | case 0x0f68: | |
6158 | case 0x0f69: | |
6159 | case 0x0f6a: | |
6160 | case 0x0f6b: | |
6161 | case 0x0f6c: | |
6162 | case 0x0f6d: | |
6163 | case 0x0f6e: | |
6164 | case 0x0f6f: | |
6165 | case 0x0f70: | |
6166 | case 0x0f71: | |
6167 | case 0x0f72: | |
6168 | case 0x0f73: | |
6169 | case 0x0f74: | |
6170 | case 0x0f75: | |
6171 | case 0x0f76: | |
6172 | case 0x0f7c: | |
6173 | case 0x0f7d: | |
6174 | case 0x0f7e: | |
6175 | case 0x0f7f: | |
6176 | case 0x0fb8: | |
6177 | case 0x0fc2: | |
6178 | case 0x0fc4: | |
6179 | case 0x0fc5: | |
6180 | case 0x0fc6: | |
6181 | case 0x0fd0: | |
6182 | case 0x0fd1: | |
6183 | case 0x0fd2: | |
6184 | case 0x0fd3: | |
6185 | case 0x0fd4: | |
6186 | case 0x0fd5: | |
6187 | case 0x0fd6: | |
6188 | case 0x0fd7: | |
6189 | case 0x0fd8: | |
6190 | case 0x0fd9: | |
6191 | case 0x0fda: | |
6192 | case 0x0fdb: | |
6193 | case 0x0fdc: | |
6194 | case 0x0fdd: | |
6195 | case 0x0fde: | |
6196 | case 0x0fdf: | |
6197 | case 0x0fe0: | |
6198 | case 0x0fe1: | |
6199 | case 0x0fe2: | |
6200 | case 0x0fe3: | |
6201 | case 0x0fe4: | |
6202 | case 0x0fe5: | |
6203 | case 0x0fe6: | |
6204 | case 0x0fe7: | |
6205 | case 0x0fe8: | |
6206 | case 0x0fe9: | |
6207 | case 0x0fea: | |
6208 | case 0x0feb: | |
6209 | case 0x0fec: | |
6210 | case 0x0fed: | |
6211 | case 0x0fee: | |
6212 | case 0x0fef: | |
6213 | case 0x0ff0: | |
6214 | case 0x0ff1: | |
6215 | case 0x0ff2: | |
6216 | case 0x0ff3: | |
6217 | case 0x0ff4: | |
6218 | case 0x0ff5: | |
6219 | case 0x0ff6: | |
6220 | case 0x0ff7: | |
6221 | case 0x0ff8: | |
6222 | case 0x0ff9: | |
6223 | case 0x0ffa: | |
6224 | case 0x0ffb: | |
6225 | case 0x0ffc: | |
6226 | case 0x0ffd: | |
6227 | case 0x0ffe: | |
6228 | switch (prefixes) | |
6229 | { | |
6230 | case PREFIX_REPNZ: | |
6231 | opcode |= 0xf20000; | |
6232 | break; | |
6233 | case PREFIX_DATA: | |
6234 | opcode |= 0x660000; | |
6235 | break; | |
6236 | case PREFIX_REPZ: | |
6237 | opcode |= 0xf30000; | |
6238 | break; | |
6239 | } | |
6240 | reswitch_prefix_add: | |
6241 | switch (opcode) | |
6242 | { | |
6243 | case 0x0f38: | |
6244 | case 0x660f38: | |
6245 | case 0xf20f38: | |
6246 | case 0x0f3a: | |
6247 | case 0x660f3a: | |
6248 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6249 | { | |
6250 | printf_unfiltered (_("Process record: error reading memory at " | |
6251 | "addr %s len = 1.\n"), | |
6252 | paddress (gdbarch, ir.addr)); | |
6253 | return -1; | |
6254 | } | |
6255 | ir.addr++; | |
6256 | opcode = (uint32_t) opcode8 | opcode << 8; | |
6257 | goto reswitch_prefix_add; | |
6258 | break; | |
6259 | ||
6260 | case 0x0f10: /* movups */ | |
6261 | case 0x660f10: /* movupd */ | |
6262 | case 0xf30f10: /* movss */ | |
6263 | case 0xf20f10: /* movsd */ | |
6264 | case 0x0f12: /* movlps */ | |
6265 | case 0x660f12: /* movlpd */ | |
6266 | case 0xf30f12: /* movsldup */ | |
6267 | case 0xf20f12: /* movddup */ | |
6268 | case 0x0f14: /* unpcklps */ | |
6269 | case 0x660f14: /* unpcklpd */ | |
6270 | case 0x0f15: /* unpckhps */ | |
6271 | case 0x660f15: /* unpckhpd */ | |
6272 | case 0x0f16: /* movhps */ | |
6273 | case 0x660f16: /* movhpd */ | |
6274 | case 0xf30f16: /* movshdup */ | |
6275 | case 0x0f28: /* movaps */ | |
6276 | case 0x660f28: /* movapd */ | |
6277 | case 0x0f2a: /* cvtpi2ps */ | |
6278 | case 0x660f2a: /* cvtpi2pd */ | |
6279 | case 0xf30f2a: /* cvtsi2ss */ | |
6280 | case 0xf20f2a: /* cvtsi2sd */ | |
6281 | case 0x0f2c: /* cvttps2pi */ | |
6282 | case 0x660f2c: /* cvttpd2pi */ | |
6283 | case 0x0f2d: /* cvtps2pi */ | |
6284 | case 0x660f2d: /* cvtpd2pi */ | |
6285 | case 0x660f3800: /* pshufb */ | |
6286 | case 0x660f3801: /* phaddw */ | |
6287 | case 0x660f3802: /* phaddd */ | |
6288 | case 0x660f3803: /* phaddsw */ | |
6289 | case 0x660f3804: /* pmaddubsw */ | |
6290 | case 0x660f3805: /* phsubw */ | |
6291 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 6292 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
6293 | case 0x660f3808: /* psignb */ |
6294 | case 0x660f3809: /* psignw */ | |
6295 | case 0x660f380a: /* psignd */ | |
6296 | case 0x660f380b: /* pmulhrsw */ | |
6297 | case 0x660f3810: /* pblendvb */ | |
6298 | case 0x660f3814: /* blendvps */ | |
6299 | case 0x660f3815: /* blendvpd */ | |
6300 | case 0x660f381c: /* pabsb */ | |
6301 | case 0x660f381d: /* pabsw */ | |
6302 | case 0x660f381e: /* pabsd */ | |
6303 | case 0x660f3820: /* pmovsxbw */ | |
6304 | case 0x660f3821: /* pmovsxbd */ | |
6305 | case 0x660f3822: /* pmovsxbq */ | |
6306 | case 0x660f3823: /* pmovsxwd */ | |
6307 | case 0x660f3824: /* pmovsxwq */ | |
6308 | case 0x660f3825: /* pmovsxdq */ | |
6309 | case 0x660f3828: /* pmuldq */ | |
6310 | case 0x660f3829: /* pcmpeqq */ | |
6311 | case 0x660f382a: /* movntdqa */ | |
6312 | case 0x660f3a08: /* roundps */ | |
6313 | case 0x660f3a09: /* roundpd */ | |
6314 | case 0x660f3a0a: /* roundss */ | |
6315 | case 0x660f3a0b: /* roundsd */ | |
6316 | case 0x660f3a0c: /* blendps */ | |
6317 | case 0x660f3a0d: /* blendpd */ | |
6318 | case 0x660f3a0e: /* pblendw */ | |
6319 | case 0x660f3a0f: /* palignr */ | |
6320 | case 0x660f3a20: /* pinsrb */ | |
6321 | case 0x660f3a21: /* insertps */ | |
6322 | case 0x660f3a22: /* pinsrd pinsrq */ | |
6323 | case 0x660f3a40: /* dpps */ | |
6324 | case 0x660f3a41: /* dppd */ | |
6325 | case 0x660f3a42: /* mpsadbw */ | |
6326 | case 0x660f3a60: /* pcmpestrm */ | |
6327 | case 0x660f3a61: /* pcmpestri */ | |
6328 | case 0x660f3a62: /* pcmpistrm */ | |
6329 | case 0x660f3a63: /* pcmpistri */ | |
6330 | case 0x0f51: /* sqrtps */ | |
6331 | case 0x660f51: /* sqrtpd */ | |
6332 | case 0xf20f51: /* sqrtsd */ | |
6333 | case 0xf30f51: /* sqrtss */ | |
6334 | case 0x0f52: /* rsqrtps */ | |
6335 | case 0xf30f52: /* rsqrtss */ | |
6336 | case 0x0f53: /* rcpps */ | |
6337 | case 0xf30f53: /* rcpss */ | |
6338 | case 0x0f54: /* andps */ | |
6339 | case 0x660f54: /* andpd */ | |
6340 | case 0x0f55: /* andnps */ | |
6341 | case 0x660f55: /* andnpd */ | |
6342 | case 0x0f56: /* orps */ | |
6343 | case 0x660f56: /* orpd */ | |
6344 | case 0x0f57: /* xorps */ | |
6345 | case 0x660f57: /* xorpd */ | |
6346 | case 0x0f58: /* addps */ | |
6347 | case 0x660f58: /* addpd */ | |
6348 | case 0xf20f58: /* addsd */ | |
6349 | case 0xf30f58: /* addss */ | |
6350 | case 0x0f59: /* mulps */ | |
6351 | case 0x660f59: /* mulpd */ | |
6352 | case 0xf20f59: /* mulsd */ | |
6353 | case 0xf30f59: /* mulss */ | |
6354 | case 0x0f5a: /* cvtps2pd */ | |
6355 | case 0x660f5a: /* cvtpd2ps */ | |
6356 | case 0xf20f5a: /* cvtsd2ss */ | |
6357 | case 0xf30f5a: /* cvtss2sd */ | |
6358 | case 0x0f5b: /* cvtdq2ps */ | |
6359 | case 0x660f5b: /* cvtps2dq */ | |
6360 | case 0xf30f5b: /* cvttps2dq */ | |
6361 | case 0x0f5c: /* subps */ | |
6362 | case 0x660f5c: /* subpd */ | |
6363 | case 0xf20f5c: /* subsd */ | |
6364 | case 0xf30f5c: /* subss */ | |
6365 | case 0x0f5d: /* minps */ | |
6366 | case 0x660f5d: /* minpd */ | |
6367 | case 0xf20f5d: /* minsd */ | |
6368 | case 0xf30f5d: /* minss */ | |
6369 | case 0x0f5e: /* divps */ | |
6370 | case 0x660f5e: /* divpd */ | |
6371 | case 0xf20f5e: /* divsd */ | |
6372 | case 0xf30f5e: /* divss */ | |
6373 | case 0x0f5f: /* maxps */ | |
6374 | case 0x660f5f: /* maxpd */ | |
6375 | case 0xf20f5f: /* maxsd */ | |
6376 | case 0xf30f5f: /* maxss */ | |
6377 | case 0x660f60: /* punpcklbw */ | |
6378 | case 0x660f61: /* punpcklwd */ | |
6379 | case 0x660f62: /* punpckldq */ | |
6380 | case 0x660f63: /* packsswb */ | |
6381 | case 0x660f64: /* pcmpgtb */ | |
6382 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 6383 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
6384 | case 0x660f67: /* packuswb */ |
6385 | case 0x660f68: /* punpckhbw */ | |
6386 | case 0x660f69: /* punpckhwd */ | |
6387 | case 0x660f6a: /* punpckhdq */ | |
6388 | case 0x660f6b: /* packssdw */ | |
6389 | case 0x660f6c: /* punpcklqdq */ | |
6390 | case 0x660f6d: /* punpckhqdq */ | |
6391 | case 0x660f6e: /* movd */ | |
6392 | case 0x660f6f: /* movdqa */ | |
6393 | case 0xf30f6f: /* movdqu */ | |
6394 | case 0x660f70: /* pshufd */ | |
6395 | case 0xf20f70: /* pshuflw */ | |
6396 | case 0xf30f70: /* pshufhw */ | |
6397 | case 0x660f74: /* pcmpeqb */ | |
6398 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 6399 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
6400 | case 0x660f7c: /* haddpd */ |
6401 | case 0xf20f7c: /* haddps */ | |
6402 | case 0x660f7d: /* hsubpd */ | |
6403 | case 0xf20f7d: /* hsubps */ | |
6404 | case 0xf30f7e: /* movq */ | |
6405 | case 0x0fc2: /* cmpps */ | |
6406 | case 0x660fc2: /* cmppd */ | |
6407 | case 0xf20fc2: /* cmpsd */ | |
6408 | case 0xf30fc2: /* cmpss */ | |
6409 | case 0x660fc4: /* pinsrw */ | |
6410 | case 0x0fc6: /* shufps */ | |
6411 | case 0x660fc6: /* shufpd */ | |
6412 | case 0x660fd0: /* addsubpd */ | |
6413 | case 0xf20fd0: /* addsubps */ | |
6414 | case 0x660fd1: /* psrlw */ | |
6415 | case 0x660fd2: /* psrld */ | |
6416 | case 0x660fd3: /* psrlq */ | |
6417 | case 0x660fd4: /* paddq */ | |
6418 | case 0x660fd5: /* pmullw */ | |
6419 | case 0xf30fd6: /* movq2dq */ | |
6420 | case 0x660fd8: /* psubusb */ | |
6421 | case 0x660fd9: /* psubusw */ | |
6422 | case 0x660fda: /* pminub */ | |
6423 | case 0x660fdb: /* pand */ | |
6424 | case 0x660fdc: /* paddusb */ | |
6425 | case 0x660fdd: /* paddusw */ | |
6426 | case 0x660fde: /* pmaxub */ | |
6427 | case 0x660fdf: /* pandn */ | |
6428 | case 0x660fe0: /* pavgb */ | |
6429 | case 0x660fe1: /* psraw */ | |
6430 | case 0x660fe2: /* psrad */ | |
6431 | case 0x660fe3: /* pavgw */ | |
6432 | case 0x660fe4: /* pmulhuw */ | |
6433 | case 0x660fe5: /* pmulhw */ | |
6434 | case 0x660fe6: /* cvttpd2dq */ | |
6435 | case 0xf20fe6: /* cvtpd2dq */ | |
6436 | case 0xf30fe6: /* cvtdq2pd */ | |
6437 | case 0x660fe8: /* psubsb */ | |
6438 | case 0x660fe9: /* psubsw */ | |
6439 | case 0x660fea: /* pminsw */ | |
6440 | case 0x660feb: /* por */ | |
6441 | case 0x660fec: /* paddsb */ | |
6442 | case 0x660fed: /* paddsw */ | |
6443 | case 0x660fee: /* pmaxsw */ | |
6444 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 6445 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
6446 | case 0x660ff1: /* psllw */ |
6447 | case 0x660ff2: /* pslld */ | |
6448 | case 0x660ff3: /* psllq */ | |
6449 | case 0x660ff4: /* pmuludq */ | |
6450 | case 0x660ff5: /* pmaddwd */ | |
6451 | case 0x660ff6: /* psadbw */ | |
6452 | case 0x660ff8: /* psubb */ | |
6453 | case 0x660ff9: /* psubw */ | |
56d2815c | 6454 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
6455 | case 0x660ffb: /* psubq */ |
6456 | case 0x660ffc: /* paddb */ | |
6457 | case 0x660ffd: /* paddw */ | |
56d2815c | 6458 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
6459 | if (i386_record_modrm (&ir)) |
6460 | return -1; | |
6461 | ir.reg |= rex_r; | |
c131fcee | 6462 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a HZ |
6463 | goto no_support; |
6464 | record_arch_list_add_reg (ir.regcache, | |
6465 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
6466 | if ((opcode & 0xfffffffc) == 0x660f3a60) | |
6467 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6468 | break; | |
6469 | ||
6470 | case 0x0f11: /* movups */ | |
6471 | case 0x660f11: /* movupd */ | |
6472 | case 0xf30f11: /* movss */ | |
6473 | case 0xf20f11: /* movsd */ | |
6474 | case 0x0f13: /* movlps */ | |
6475 | case 0x660f13: /* movlpd */ | |
6476 | case 0x0f17: /* movhps */ | |
6477 | case 0x660f17: /* movhpd */ | |
6478 | case 0x0f29: /* movaps */ | |
6479 | case 0x660f29: /* movapd */ | |
6480 | case 0x660f3a14: /* pextrb */ | |
6481 | case 0x660f3a15: /* pextrw */ | |
6482 | case 0x660f3a16: /* pextrd pextrq */ | |
6483 | case 0x660f3a17: /* extractps */ | |
6484 | case 0x660f7f: /* movdqa */ | |
6485 | case 0xf30f7f: /* movdqu */ | |
6486 | if (i386_record_modrm (&ir)) | |
6487 | return -1; | |
6488 | if (ir.mod == 3) | |
6489 | { | |
6490 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
6491 | || opcode == 0x0f17 || opcode == 0x660f17) | |
6492 | goto no_support; | |
6493 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
6494 | if (!i386_xmm_regnum_p (gdbarch, |
6495 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
6496 | goto no_support; |
6497 | record_arch_list_add_reg (ir.regcache, | |
6498 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6499 | } | |
6500 | else | |
6501 | { | |
6502 | switch (opcode) | |
6503 | { | |
6504 | case 0x660f3a14: | |
6505 | ir.ot = OT_BYTE; | |
6506 | break; | |
6507 | case 0x660f3a15: | |
6508 | ir.ot = OT_WORD; | |
6509 | break; | |
6510 | case 0x660f3a16: | |
6511 | ir.ot = OT_LONG; | |
6512 | break; | |
6513 | case 0x660f3a17: | |
6514 | ir.ot = OT_QUAD; | |
6515 | break; | |
6516 | default: | |
6517 | ir.ot = OT_DQUAD; | |
6518 | break; | |
6519 | } | |
6520 | if (i386_record_lea_modrm (&ir)) | |
6521 | return -1; | |
6522 | } | |
6523 | break; | |
6524 | ||
6525 | case 0x0f2b: /* movntps */ | |
6526 | case 0x660f2b: /* movntpd */ | |
6527 | case 0x0fe7: /* movntq */ | |
6528 | case 0x660fe7: /* movntdq */ | |
6529 | if (ir.mod == 3) | |
6530 | goto no_support; | |
6531 | if (opcode == 0x0fe7) | |
6532 | ir.ot = OT_QUAD; | |
6533 | else | |
6534 | ir.ot = OT_DQUAD; | |
6535 | if (i386_record_lea_modrm (&ir)) | |
6536 | return -1; | |
6537 | break; | |
6538 | ||
6539 | case 0xf30f2c: /* cvttss2si */ | |
6540 | case 0xf20f2c: /* cvttsd2si */ | |
6541 | case 0xf30f2d: /* cvtss2si */ | |
6542 | case 0xf20f2d: /* cvtsd2si */ | |
6543 | case 0xf20f38f0: /* crc32 */ | |
6544 | case 0xf20f38f1: /* crc32 */ | |
6545 | case 0x0f50: /* movmskps */ | |
6546 | case 0x660f50: /* movmskpd */ | |
6547 | case 0x0fc5: /* pextrw */ | |
6548 | case 0x660fc5: /* pextrw */ | |
6549 | case 0x0fd7: /* pmovmskb */ | |
6550 | case 0x660fd7: /* pmovmskb */ | |
6551 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
6552 | break; | |
6553 | ||
6554 | case 0x0f3800: /* pshufb */ | |
6555 | case 0x0f3801: /* phaddw */ | |
6556 | case 0x0f3802: /* phaddd */ | |
6557 | case 0x0f3803: /* phaddsw */ | |
6558 | case 0x0f3804: /* pmaddubsw */ | |
6559 | case 0x0f3805: /* phsubw */ | |
6560 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 6561 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
6562 | case 0x0f3808: /* psignb */ |
6563 | case 0x0f3809: /* psignw */ | |
6564 | case 0x0f380a: /* psignd */ | |
6565 | case 0x0f380b: /* pmulhrsw */ | |
6566 | case 0x0f381c: /* pabsb */ | |
6567 | case 0x0f381d: /* pabsw */ | |
6568 | case 0x0f381e: /* pabsd */ | |
6569 | case 0x0f382b: /* packusdw */ | |
6570 | case 0x0f3830: /* pmovzxbw */ | |
6571 | case 0x0f3831: /* pmovzxbd */ | |
6572 | case 0x0f3832: /* pmovzxbq */ | |
6573 | case 0x0f3833: /* pmovzxwd */ | |
6574 | case 0x0f3834: /* pmovzxwq */ | |
6575 | case 0x0f3835: /* pmovzxdq */ | |
6576 | case 0x0f3837: /* pcmpgtq */ | |
6577 | case 0x0f3838: /* pminsb */ | |
6578 | case 0x0f3839: /* pminsd */ | |
6579 | case 0x0f383a: /* pminuw */ | |
6580 | case 0x0f383b: /* pminud */ | |
6581 | case 0x0f383c: /* pmaxsb */ | |
6582 | case 0x0f383d: /* pmaxsd */ | |
6583 | case 0x0f383e: /* pmaxuw */ | |
6584 | case 0x0f383f: /* pmaxud */ | |
6585 | case 0x0f3840: /* pmulld */ | |
6586 | case 0x0f3841: /* phminposuw */ | |
6587 | case 0x0f3a0f: /* palignr */ | |
6588 | case 0x0f60: /* punpcklbw */ | |
6589 | case 0x0f61: /* punpcklwd */ | |
6590 | case 0x0f62: /* punpckldq */ | |
6591 | case 0x0f63: /* packsswb */ | |
6592 | case 0x0f64: /* pcmpgtb */ | |
6593 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 6594 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
6595 | case 0x0f67: /* packuswb */ |
6596 | case 0x0f68: /* punpckhbw */ | |
6597 | case 0x0f69: /* punpckhwd */ | |
6598 | case 0x0f6a: /* punpckhdq */ | |
6599 | case 0x0f6b: /* packssdw */ | |
6600 | case 0x0f6e: /* movd */ | |
6601 | case 0x0f6f: /* movq */ | |
6602 | case 0x0f70: /* pshufw */ | |
6603 | case 0x0f74: /* pcmpeqb */ | |
6604 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 6605 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
6606 | case 0x0fc4: /* pinsrw */ |
6607 | case 0x0fd1: /* psrlw */ | |
6608 | case 0x0fd2: /* psrld */ | |
6609 | case 0x0fd3: /* psrlq */ | |
6610 | case 0x0fd4: /* paddq */ | |
6611 | case 0x0fd5: /* pmullw */ | |
6612 | case 0xf20fd6: /* movdq2q */ | |
6613 | case 0x0fd8: /* psubusb */ | |
6614 | case 0x0fd9: /* psubusw */ | |
6615 | case 0x0fda: /* pminub */ | |
6616 | case 0x0fdb: /* pand */ | |
6617 | case 0x0fdc: /* paddusb */ | |
6618 | case 0x0fdd: /* paddusw */ | |
6619 | case 0x0fde: /* pmaxub */ | |
6620 | case 0x0fdf: /* pandn */ | |
6621 | case 0x0fe0: /* pavgb */ | |
6622 | case 0x0fe1: /* psraw */ | |
6623 | case 0x0fe2: /* psrad */ | |
6624 | case 0x0fe3: /* pavgw */ | |
6625 | case 0x0fe4: /* pmulhuw */ | |
6626 | case 0x0fe5: /* pmulhw */ | |
6627 | case 0x0fe8: /* psubsb */ | |
6628 | case 0x0fe9: /* psubsw */ | |
6629 | case 0x0fea: /* pminsw */ | |
6630 | case 0x0feb: /* por */ | |
6631 | case 0x0fec: /* paddsb */ | |
6632 | case 0x0fed: /* paddsw */ | |
6633 | case 0x0fee: /* pmaxsw */ | |
6634 | case 0x0fef: /* pxor */ | |
6635 | case 0x0ff1: /* psllw */ | |
6636 | case 0x0ff2: /* pslld */ | |
6637 | case 0x0ff3: /* psllq */ | |
6638 | case 0x0ff4: /* pmuludq */ | |
6639 | case 0x0ff5: /* pmaddwd */ | |
6640 | case 0x0ff6: /* psadbw */ | |
6641 | case 0x0ff8: /* psubb */ | |
6642 | case 0x0ff9: /* psubw */ | |
56d2815c | 6643 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
6644 | case 0x0ffb: /* psubq */ |
6645 | case 0x0ffc: /* paddb */ | |
6646 | case 0x0ffd: /* paddw */ | |
56d2815c | 6647 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
6648 | if (i386_record_modrm (&ir)) |
6649 | return -1; | |
6650 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6651 | goto no_support; | |
6652 | record_arch_list_add_reg (ir.regcache, | |
6653 | I387_MM0_REGNUM (tdep) + ir.reg); | |
6654 | break; | |
6655 | ||
6656 | case 0x0f71: /* psllw */ | |
6657 | case 0x0f72: /* pslld */ | |
6658 | case 0x0f73: /* psllq */ | |
6659 | if (i386_record_modrm (&ir)) | |
6660 | return -1; | |
6661 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
6662 | goto no_support; | |
6663 | record_arch_list_add_reg (ir.regcache, | |
6664 | I387_MM0_REGNUM (tdep) + ir.rm); | |
6665 | break; | |
6666 | ||
6667 | case 0x660f71: /* psllw */ | |
6668 | case 0x660f72: /* pslld */ | |
6669 | case 0x660f73: /* psllq */ | |
6670 | if (i386_record_modrm (&ir)) | |
6671 | return -1; | |
6672 | ir.rm |= ir.rex_b; | |
c131fcee | 6673 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
6674 | goto no_support; |
6675 | record_arch_list_add_reg (ir.regcache, | |
6676 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6677 | break; | |
6678 | ||
6679 | case 0x0f7e: /* movd */ | |
6680 | case 0x660f7e: /* movd */ | |
6681 | if (i386_record_modrm (&ir)) | |
6682 | return -1; | |
6683 | if (ir.mod == 3) | |
6684 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
6685 | else | |
6686 | { | |
6687 | if (ir.dflag == 2) | |
6688 | ir.ot = OT_QUAD; | |
6689 | else | |
6690 | ir.ot = OT_LONG; | |
6691 | if (i386_record_lea_modrm (&ir)) | |
6692 | return -1; | |
6693 | } | |
6694 | break; | |
6695 | ||
6696 | case 0x0f7f: /* movq */ | |
6697 | if (i386_record_modrm (&ir)) | |
6698 | return -1; | |
6699 | if (ir.mod == 3) | |
6700 | { | |
6701 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
6702 | goto no_support; | |
6703 | record_arch_list_add_reg (ir.regcache, | |
6704 | I387_MM0_REGNUM (tdep) + ir.rm); | |
6705 | } | |
6706 | else | |
6707 | { | |
6708 | ir.ot = OT_QUAD; | |
6709 | if (i386_record_lea_modrm (&ir)) | |
6710 | return -1; | |
6711 | } | |
6712 | break; | |
6713 | ||
6714 | case 0xf30fb8: /* popcnt */ | |
6715 | if (i386_record_modrm (&ir)) | |
6716 | return -1; | |
6717 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); | |
6718 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6719 | break; | |
6720 | ||
6721 | case 0x660fd6: /* movq */ | |
6722 | if (i386_record_modrm (&ir)) | |
6723 | return -1; | |
6724 | if (ir.mod == 3) | |
6725 | { | |
6726 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
6727 | if (!i386_xmm_regnum_p (gdbarch, |
6728 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
6729 | goto no_support; |
6730 | record_arch_list_add_reg (ir.regcache, | |
6731 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6732 | } | |
6733 | else | |
6734 | { | |
6735 | ir.ot = OT_QUAD; | |
6736 | if (i386_record_lea_modrm (&ir)) | |
6737 | return -1; | |
6738 | } | |
6739 | break; | |
6740 | ||
6741 | case 0x660f3817: /* ptest */ | |
6742 | case 0x0f2e: /* ucomiss */ | |
6743 | case 0x660f2e: /* ucomisd */ | |
6744 | case 0x0f2f: /* comiss */ | |
6745 | case 0x660f2f: /* comisd */ | |
6746 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6747 | break; | |
6748 | ||
6749 | case 0x0ff7: /* maskmovq */ | |
6750 | regcache_raw_read_unsigned (ir.regcache, | |
6751 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
6752 | &addr); | |
6753 | if (record_arch_list_add_mem (addr, 64)) | |
6754 | return -1; | |
6755 | break; | |
6756 | ||
6757 | case 0x660ff7: /* maskmovdqu */ | |
6758 | regcache_raw_read_unsigned (ir.regcache, | |
6759 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
6760 | &addr); | |
6761 | if (record_arch_list_add_mem (addr, 128)) | |
6762 | return -1; | |
6763 | break; | |
6764 | ||
6765 | default: | |
6766 | goto no_support; | |
6767 | break; | |
6768 | } | |
6769 | break; | |
7ad10968 HZ |
6770 | |
6771 | default: | |
7ad10968 HZ |
6772 | goto no_support; |
6773 | break; | |
6774 | } | |
6775 | ||
cf648174 HZ |
6776 | /* In the future, maybe still need to deal with need_dasm. */ |
6777 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
6778 | if (record_arch_list_add_end ()) |
6779 | return -1; | |
6780 | ||
6781 | return 0; | |
6782 | ||
01fe1b41 | 6783 | no_support: |
a3c4230a HZ |
6784 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
6785 | "at address %s.\n"), | |
6786 | (unsigned int) (opcode), | |
6787 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
6788 | return -1; |
6789 | } | |
6790 | ||
cf648174 HZ |
6791 | static const int i386_record_regmap[] = |
6792 | { | |
6793 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
6794 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
6795 | 0, 0, 0, 0, 0, 0, 0, 0, | |
6796 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
6797 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
6798 | }; | |
6799 | ||
7a697b8d SS |
6800 | /* Check that the given address appears suitable for a fast |
6801 | tracepoint, which on x86 means that we need an instruction of at | |
6802 | least 5 bytes, so that we can overwrite it with a 4-byte-offset | |
6803 | jump and not have to worry about program jumps to an address in the | |
6804 | middle of the tracepoint jump. Returns 1 if OK, and writes a size | |
6805 | of instruction to replace, and 0 if not, plus an explanatory | |
6806 | string. */ | |
6807 | ||
6808 | static int | |
6809 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
6810 | CORE_ADDR addr, int *isize, char **msg) | |
6811 | { | |
6812 | int len, jumplen; | |
6813 | static struct ui_file *gdb_null = NULL; | |
6814 | ||
6815 | /* This is based on the target agent using a 4-byte relative jump. | |
6816 | Alternate future possibilities include 8-byte offset for x86-84, | |
6817 | or 3-byte jumps if the program has trampoline space close by. */ | |
6818 | jumplen = 5; | |
6819 | ||
6820 | /* Dummy file descriptor for the disassembler. */ | |
6821 | if (!gdb_null) | |
6822 | gdb_null = ui_file_new (); | |
6823 | ||
6824 | /* Check for fit. */ | |
6825 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
6826 | if (len < jumplen) | |
6827 | { | |
6828 | /* Return a bit of target-specific detail to add to the caller's | |
6829 | generic failure message. */ | |
6830 | if (msg) | |
1777feb0 MS |
6831 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
6832 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
6833 | len, jumplen); |
6834 | return 0; | |
6835 | } | |
6836 | ||
6837 | if (isize) | |
6838 | *isize = len; | |
6839 | if (msg) | |
6840 | *msg = NULL; | |
6841 | return 1; | |
6842 | } | |
6843 | ||
90884b2b L |
6844 | static int |
6845 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
6846 | struct tdesc_arch_data *tdesc_data) | |
6847 | { | |
6848 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee L |
6849 | const struct tdesc_feature *feature_core; |
6850 | const struct tdesc_feature *feature_sse, *feature_avx; | |
90884b2b L |
6851 | int i, num_regs, valid_p; |
6852 | ||
6853 | if (! tdesc_has_registers (tdesc)) | |
6854 | return 0; | |
6855 | ||
6856 | /* Get core registers. */ | |
6857 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
6858 | if (feature_core == NULL) |
6859 | return 0; | |
90884b2b L |
6860 | |
6861 | /* Get SSE registers. */ | |
c131fcee | 6862 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 6863 | |
c131fcee L |
6864 | /* Try AVX registers. */ |
6865 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
6866 | ||
90884b2b L |
6867 | valid_p = 1; |
6868 | ||
c131fcee L |
6869 | /* The XCR0 bits. */ |
6870 | if (feature_avx) | |
6871 | { | |
3a13a53b L |
6872 | /* AVX register description requires SSE register description. */ |
6873 | if (!feature_sse) | |
6874 | return 0; | |
6875 | ||
c131fcee L |
6876 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
6877 | ||
6878 | /* It may have been set by OSABI initialization function. */ | |
6879 | if (tdep->num_ymm_regs == 0) | |
6880 | { | |
6881 | tdep->ymmh_register_names = i386_ymmh_names; | |
6882 | tdep->num_ymm_regs = 8; | |
6883 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
6884 | } | |
6885 | ||
6886 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
6887 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
6888 | tdep->ymm0h_regnum + i, | |
6889 | tdep->ymmh_register_names[i]); | |
6890 | } | |
3a13a53b | 6891 | else if (feature_sse) |
c131fcee | 6892 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
6893 | else |
6894 | { | |
6895 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
6896 | tdep->num_xmm_regs = 0; | |
6897 | } | |
c131fcee | 6898 | |
90884b2b L |
6899 | num_regs = tdep->num_core_regs; |
6900 | for (i = 0; i < num_regs; i++) | |
6901 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
6902 | tdep->register_names[i]); | |
6903 | ||
3a13a53b L |
6904 | if (feature_sse) |
6905 | { | |
6906 | /* Need to include %mxcsr, so add one. */ | |
6907 | num_regs += tdep->num_xmm_regs + 1; | |
6908 | for (; i < num_regs; i++) | |
6909 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
6910 | tdep->register_names[i]); | |
6911 | } | |
90884b2b L |
6912 | |
6913 | return valid_p; | |
6914 | } | |
6915 | ||
7ad10968 HZ |
6916 | \f |
6917 | static struct gdbarch * | |
6918 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
6919 | { | |
6920 | struct gdbarch_tdep *tdep; | |
6921 | struct gdbarch *gdbarch; | |
90884b2b L |
6922 | struct tdesc_arch_data *tdesc_data; |
6923 | const struct target_desc *tdesc; | |
1ba53b71 | 6924 | int mm0_regnum; |
c131fcee | 6925 | int ymm0_regnum; |
7ad10968 HZ |
6926 | |
6927 | /* If there is already a candidate, use it. */ | |
6928 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
6929 | if (arches != NULL) | |
6930 | return arches->gdbarch; | |
6931 | ||
6932 | /* Allocate space for the new architecture. */ | |
6933 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
6934 | gdbarch = gdbarch_alloc (&info, tdep); | |
6935 | ||
6936 | /* General-purpose registers. */ | |
6937 | tdep->gregset = NULL; | |
6938 | tdep->gregset_reg_offset = NULL; | |
6939 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
6940 | tdep->sizeof_gregset = 0; | |
6941 | ||
6942 | /* Floating-point registers. */ | |
6943 | tdep->fpregset = NULL; | |
6944 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
6945 | ||
c131fcee L |
6946 | tdep->xstateregset = NULL; |
6947 | ||
7ad10968 HZ |
6948 | /* The default settings include the FPU registers, the MMX registers |
6949 | and the SSE registers. This can be overridden for a specific ABI | |
6950 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
6951 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 6952 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
6953 | |
6954 | tdep->st0_regnum = I386_ST0_REGNUM; | |
6955 | ||
7ad10968 HZ |
6956 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
6957 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
6958 | ||
6959 | tdep->jb_pc_offset = -1; | |
6960 | tdep->struct_return = pcc_struct_return; | |
6961 | tdep->sigtramp_start = 0; | |
6962 | tdep->sigtramp_end = 0; | |
6963 | tdep->sigtramp_p = i386_sigtramp_p; | |
6964 | tdep->sigcontext_addr = NULL; | |
6965 | tdep->sc_reg_offset = NULL; | |
6966 | tdep->sc_pc_offset = -1; | |
6967 | tdep->sc_sp_offset = -1; | |
6968 | ||
c131fcee L |
6969 | tdep->xsave_xcr0_offset = -1; |
6970 | ||
cf648174 HZ |
6971 | tdep->record_regmap = i386_record_regmap; |
6972 | ||
7ad10968 HZ |
6973 | /* The format used for `long double' on almost all i386 targets is |
6974 | the i387 extended floating-point format. In fact, of all targets | |
6975 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
6976 | on having a `long double' that's not `long' at all. */ | |
6977 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
6978 | ||
6979 | /* Although the i387 extended floating-point has only 80 significant | |
6980 | bits, a `long double' actually takes up 96, probably to enforce | |
6981 | alignment. */ | |
6982 | set_gdbarch_long_double_bit (gdbarch, 96); | |
6983 | ||
7ad10968 HZ |
6984 | /* Register numbers of various important registers. */ |
6985 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
6986 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
6987 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
6988 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
6989 | ||
6990 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
6991 | numbering schemes on the i386: dbx and SVR4. These schemes | |
6992 | differ in how they number %ebp, %esp, %eflags, and the | |
6993 | floating-point registers, and are implemented by the arrays | |
6994 | dbx_register_map[] and svr4_dbx_register_map in | |
6995 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
6996 | gcc/config/i386.c, which it designates as the "default" register | |
6997 | map used in 64bit mode. This last register numbering scheme is | |
6998 | implemented in dbx64_register_map, and is used for AMD64; see | |
6999 | amd64-tdep.c. | |
7000 | ||
7001 | Currently, each GCC i386 target always uses the same register | |
7002 | numbering scheme across all its supported debugging formats | |
7003 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
7004 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
7005 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
7006 | respective config header in a manner independent of the requested | |
7007 | output debugging format. | |
7008 | ||
7009 | This does not match the arrangement below, which presumes that | |
7010 | the SDB and stabs numbering schemes differ from the DWARF and | |
7011 | DWARF 2 ones. The reason for this arrangement is that it is | |
7012 | likely to get the numbering scheme for the target's | |
7013 | default/native debug format right. For targets where GCC is the | |
7014 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
7015 | targets where the native toolchain uses a different numbering | |
7016 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
7017 | the defaults below will have to be overridden, like | |
7018 | i386_elf_init_abi() does. */ | |
7019 | ||
7020 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
7021 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7022 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7023 | ||
7024 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
7025 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
7026 | ||
7027 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
7028 | be in use on any of the supported i386 targets. */ | |
7029 | ||
7030 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
7031 | ||
7032 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
7033 | ||
7034 | /* Call dummy code. */ | |
7035 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
7036 | ||
7037 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
7038 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
7039 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
7040 | ||
7041 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
7042 | ||
7043 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
7044 | ||
7045 | /* Stack grows downward. */ | |
7046 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7047 | ||
7048 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
7049 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
7050 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
7051 | ||
7052 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
7053 | ||
7ad10968 HZ |
7054 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
7055 | ||
7056 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
7057 | ||
7058 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
7059 | ||
7060 | /* Add the i386 register groups. */ | |
7061 | i386_add_reggroups (gdbarch); | |
90884b2b | 7062 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 7063 | |
143985b7 AF |
7064 | /* Helper for function argument information. */ |
7065 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
7066 | ||
06da04c6 MS |
7067 | /* Hook the function epilogue frame unwinder. This unwinder is |
7068 | appended to the list first, so that it supercedes the Dwarf | |
7069 | unwinder in function epilogues (where the Dwarf unwinder | |
7070 | currently fails). */ | |
7071 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
7072 | ||
7073 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
7074 | to the list before the prologue-based unwinders, so that Dwarf | |
7075 | CFI info will be used if it is available. */ | |
10458914 | 7076 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 7077 | |
acd5c798 | 7078 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 7079 | |
1ba53b71 | 7080 | /* Pseudo registers may be changed by amd64_init_abi. */ |
90884b2b L |
7081 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
7082 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
7083 | ||
7084 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
7085 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
7086 | ||
c131fcee L |
7087 | /* Override the normal target description method to make the AVX |
7088 | upper halves anonymous. */ | |
7089 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
7090 | ||
7091 | /* Even though the default ABI only includes general-purpose registers, | |
7092 | floating-point registers and the SSE registers, we have to leave a | |
7093 | gap for the upper AVX registers. */ | |
7094 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); | |
90884b2b L |
7095 | |
7096 | /* Get the x86 target description from INFO. */ | |
7097 | tdesc = info.target_desc; | |
7098 | if (! tdesc_has_registers (tdesc)) | |
7099 | tdesc = tdesc_i386; | |
7100 | tdep->tdesc = tdesc; | |
7101 | ||
7102 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
7103 | tdep->register_names = i386_register_names; | |
7104 | ||
c131fcee L |
7105 | /* No upper YMM registers. */ |
7106 | tdep->ymmh_register_names = NULL; | |
7107 | tdep->ymm0h_regnum = -1; | |
7108 | ||
1ba53b71 L |
7109 | tdep->num_byte_regs = 8; |
7110 | tdep->num_word_regs = 8; | |
7111 | tdep->num_dword_regs = 0; | |
7112 | tdep->num_mmx_regs = 8; | |
c131fcee | 7113 | tdep->num_ymm_regs = 0; |
1ba53b71 | 7114 | |
90884b2b L |
7115 | tdesc_data = tdesc_data_alloc (); |
7116 | ||
dde08ee1 PA |
7117 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
7118 | ||
3ce1502b | 7119 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 7120 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 7121 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 7122 | |
c131fcee L |
7123 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
7124 | { | |
7125 | tdesc_data_cleanup (tdesc_data); | |
7126 | xfree (tdep); | |
7127 | gdbarch_free (gdbarch); | |
7128 | return NULL; | |
7129 | } | |
7130 | ||
1ba53b71 L |
7131 | /* Wire in pseudo registers. Number of pseudo registers may be |
7132 | changed. */ | |
7133 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
7134 | + tdep->num_word_regs | |
7135 | + tdep->num_dword_regs | |
c131fcee L |
7136 | + tdep->num_mmx_regs |
7137 | + tdep->num_ymm_regs)); | |
1ba53b71 | 7138 | |
90884b2b L |
7139 | /* Target description may be changed. */ |
7140 | tdesc = tdep->tdesc; | |
7141 | ||
90884b2b L |
7142 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
7143 | ||
7144 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
7145 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
7146 | ||
1ba53b71 L |
7147 | /* Make %al the first pseudo-register. */ |
7148 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
7149 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
7150 | ||
c131fcee | 7151 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
7152 | if (tdep->num_dword_regs) |
7153 | { | |
1c6272a6 | 7154 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
7155 | tdep->eax_regnum = ymm0_regnum; |
7156 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
7157 | } |
7158 | else | |
7159 | tdep->eax_regnum = -1; | |
7160 | ||
c131fcee L |
7161 | mm0_regnum = ymm0_regnum; |
7162 | if (tdep->num_ymm_regs) | |
7163 | { | |
1c6272a6 | 7164 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
7165 | tdep->ymm0_regnum = ymm0_regnum; |
7166 | mm0_regnum += tdep->num_ymm_regs; | |
7167 | } | |
7168 | else | |
7169 | tdep->ymm0_regnum = -1; | |
7170 | ||
1ba53b71 L |
7171 | if (tdep->num_mmx_regs != 0) |
7172 | { | |
1c6272a6 | 7173 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 L |
7174 | tdep->mm0_regnum = mm0_regnum; |
7175 | } | |
7176 | else | |
7177 | tdep->mm0_regnum = -1; | |
7178 | ||
06da04c6 | 7179 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
10458914 DJ |
7180 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
7181 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 7182 | |
8446b36a MK |
7183 | /* If we have a register mapping, enable the generic core file |
7184 | support, unless it has already been enabled. */ | |
7185 | if (tdep->gregset_reg_offset | |
7186 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
7187 | set_gdbarch_regset_from_core_section (gdbarch, | |
7188 | i386_regset_from_core_section); | |
7189 | ||
514f746b AR |
7190 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
7191 | i386_skip_permanent_breakpoint); | |
7192 | ||
7a697b8d SS |
7193 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
7194 | i386_fast_tracepoint_valid_at); | |
7195 | ||
a62cc96e AC |
7196 | return gdbarch; |
7197 | } | |
7198 | ||
8201327c MK |
7199 | static enum gdb_osabi |
7200 | i386_coff_osabi_sniffer (bfd *abfd) | |
7201 | { | |
762c5349 MK |
7202 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
7203 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
7204 | return GDB_OSABI_GO32; |
7205 | ||
7206 | return GDB_OSABI_UNKNOWN; | |
7207 | } | |
8201327c MK |
7208 | \f |
7209 | ||
28e9e0f0 MK |
7210 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
7211 | void _initialize_i386_tdep (void); | |
7212 | ||
c906108c | 7213 | void |
fba45db2 | 7214 | _initialize_i386_tdep (void) |
c906108c | 7215 | { |
a62cc96e AC |
7216 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
7217 | ||
fc338970 | 7218 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
7219 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
7220 | &disassembly_flavor, _("\ | |
7221 | Set the disassembly flavor."), _("\ | |
7222 | Show the disassembly flavor."), _("\ | |
7223 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
7224 | NULL, | |
7225 | NULL, /* FIXME: i18n: */ | |
7226 | &setlist, &showlist); | |
8201327c MK |
7227 | |
7228 | /* Add the variable that controls the convention for returning | |
7229 | structs. */ | |
7ab04401 AC |
7230 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
7231 | &struct_convention, _("\ | |
7232 | Set the convention for returning small structs."), _("\ | |
7233 | Show the convention for returning small structs."), _("\ | |
7234 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
7235 | is \"default\"."), | |
7236 | NULL, | |
7237 | NULL, /* FIXME: i18n: */ | |
7238 | &setlist, &showlist); | |
8201327c MK |
7239 | |
7240 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
7241 | i386_coff_osabi_sniffer); | |
8201327c | 7242 | |
05816f70 | 7243 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 7244 | i386_svr4_init_abi); |
05816f70 | 7245 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 7246 | i386_go32_init_abi); |
38c968cf | 7247 | |
209bd28e | 7248 | /* Initialize the i386-specific register groups. */ |
38c968cf | 7249 | i386_init_reggroups (); |
90884b2b L |
7250 | |
7251 | /* Initialize the standard target descriptions. */ | |
7252 | initialize_tdesc_i386 (); | |
3a13a53b | 7253 | initialize_tdesc_i386_mmx (); |
c131fcee | 7254 | initialize_tdesc_i386_avx (); |
c8d5aac9 L |
7255 | |
7256 | /* Tell remote stub that we support XML target description. */ | |
7257 | register_remote_support_xml ("i386"); | |
c906108c | 7258 | } |