Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
fd0407d6 | 42 | #include "value.h" |
a89aa300 | 43 | #include "dis-asm.h" |
7a697b8d | 44 | #include "disasm.h" |
c8d5aac9 | 45 | #include "remote.h" |
8fbca658 | 46 | #include "exceptions.h" |
3d261580 | 47 | #include "gdb_assert.h" |
acd5c798 | 48 | #include "gdb_string.h" |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
c131fcee | 52 | #include "i386-xstate.h" |
d2a7c97a | 53 | |
7ad10968 HZ |
54 | #include "record.h" |
55 | #include <stdint.h> | |
56 | ||
90884b2b | 57 | #include "features/i386/i386.c" |
c131fcee | 58 | #include "features/i386/i386-avx.c" |
3a13a53b | 59 | #include "features/i386/i386-mmx.c" |
90884b2b | 60 | |
6710bf39 SS |
61 | #include "ax.h" |
62 | #include "ax-gdb.h" | |
63 | ||
55aa24fb SDJ |
64 | #include "stap-probe.h" |
65 | #include "user-regs.h" | |
66 | #include "cli/cli-utils.h" | |
67 | #include "expression.h" | |
68 | #include "parser-defs.h" | |
69 | #include <ctype.h> | |
70 | ||
c4fc7f1b | 71 | /* Register names. */ |
c40e1eab | 72 | |
90884b2b | 73 | static const char *i386_register_names[] = |
fc633446 MK |
74 | { |
75 | "eax", "ecx", "edx", "ebx", | |
76 | "esp", "ebp", "esi", "edi", | |
77 | "eip", "eflags", "cs", "ss", | |
78 | "ds", "es", "fs", "gs", | |
79 | "st0", "st1", "st2", "st3", | |
80 | "st4", "st5", "st6", "st7", | |
81 | "fctrl", "fstat", "ftag", "fiseg", | |
82 | "fioff", "foseg", "fooff", "fop", | |
83 | "xmm0", "xmm1", "xmm2", "xmm3", | |
84 | "xmm4", "xmm5", "xmm6", "xmm7", | |
85 | "mxcsr" | |
86 | }; | |
87 | ||
c131fcee L |
88 | static const char *i386_ymm_names[] = |
89 | { | |
90 | "ymm0", "ymm1", "ymm2", "ymm3", | |
91 | "ymm4", "ymm5", "ymm6", "ymm7", | |
92 | }; | |
93 | ||
94 | static const char *i386_ymmh_names[] = | |
95 | { | |
96 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
97 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
98 | }; | |
99 | ||
c4fc7f1b | 100 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 101 | |
90884b2b | 102 | static const char *i386_mmx_names[] = |
28fc6740 AC |
103 | { |
104 | "mm0", "mm1", "mm2", "mm3", | |
105 | "mm4", "mm5", "mm6", "mm7" | |
106 | }; | |
c40e1eab | 107 | |
1ba53b71 L |
108 | /* Register names for byte pseudo-registers. */ |
109 | ||
110 | static const char *i386_byte_names[] = | |
111 | { | |
112 | "al", "cl", "dl", "bl", | |
113 | "ah", "ch", "dh", "bh" | |
114 | }; | |
115 | ||
116 | /* Register names for word pseudo-registers. */ | |
117 | ||
118 | static const char *i386_word_names[] = | |
119 | { | |
120 | "ax", "cx", "dx", "bx", | |
9cad29ac | 121 | "", "bp", "si", "di" |
1ba53b71 L |
122 | }; |
123 | ||
124 | /* MMX register? */ | |
c40e1eab | 125 | |
28fc6740 | 126 | static int |
5716833c | 127 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 128 | { |
1ba53b71 L |
129 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
130 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
131 | |
132 | if (mm0_regnum < 0) | |
133 | return 0; | |
134 | ||
1ba53b71 L |
135 | regnum -= mm0_regnum; |
136 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
137 | } | |
138 | ||
139 | /* Byte register? */ | |
140 | ||
141 | int | |
142 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
143 | { | |
144 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
145 | ||
146 | regnum -= tdep->al_regnum; | |
147 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
148 | } | |
149 | ||
150 | /* Word register? */ | |
151 | ||
152 | int | |
153 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
154 | { | |
155 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156 | ||
157 | regnum -= tdep->ax_regnum; | |
158 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
159 | } | |
160 | ||
161 | /* Dword register? */ | |
162 | ||
163 | int | |
164 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
165 | { | |
166 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
167 | int eax_regnum = tdep->eax_regnum; | |
168 | ||
169 | if (eax_regnum < 0) | |
170 | return 0; | |
171 | ||
172 | regnum -= eax_regnum; | |
173 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
174 | } |
175 | ||
9191d390 | 176 | static int |
c131fcee L |
177 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
178 | { | |
179 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
180 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
181 | ||
182 | if (ymm0h_regnum < 0) | |
183 | return 0; | |
184 | ||
185 | regnum -= ymm0h_regnum; | |
186 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
187 | } | |
188 | ||
189 | /* AVX register? */ | |
190 | ||
191 | int | |
192 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
193 | { | |
194 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
195 | int ymm0_regnum = tdep->ymm0_regnum; | |
196 | ||
197 | if (ymm0_regnum < 0) | |
198 | return 0; | |
199 | ||
200 | regnum -= ymm0_regnum; | |
201 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
202 | } | |
203 | ||
5716833c | 204 | /* SSE register? */ |
23a34459 | 205 | |
c131fcee L |
206 | int |
207 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 208 | { |
5716833c | 209 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 210 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 211 | |
c131fcee | 212 | if (num_xmm_regs == 0) |
5716833c MK |
213 | return 0; |
214 | ||
c131fcee L |
215 | regnum -= I387_XMM0_REGNUM (tdep); |
216 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
217 | } |
218 | ||
5716833c MK |
219 | static int |
220 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 221 | { |
5716833c MK |
222 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
223 | ||
20a6ec49 | 224 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
225 | return 0; |
226 | ||
20a6ec49 | 227 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
228 | } |
229 | ||
5716833c | 230 | /* FP register? */ |
23a34459 AC |
231 | |
232 | int | |
20a6ec49 | 233 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 234 | { |
20a6ec49 MD |
235 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
236 | ||
237 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
238 | return 0; |
239 | ||
20a6ec49 MD |
240 | return (I387_ST0_REGNUM (tdep) <= regnum |
241 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
242 | } |
243 | ||
244 | int | |
20a6ec49 | 245 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 246 | { |
20a6ec49 MD |
247 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
248 | ||
249 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
250 | return 0; |
251 | ||
20a6ec49 MD |
252 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
253 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
254 | } |
255 | ||
c131fcee L |
256 | /* Return the name of register REGNUM, or the empty string if it is |
257 | an anonymous register. */ | |
258 | ||
259 | static const char * | |
260 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
261 | { | |
262 | /* Hide the upper YMM registers. */ | |
263 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
264 | return ""; | |
265 | ||
266 | return tdesc_register_name (gdbarch, regnum); | |
267 | } | |
268 | ||
30b0e2d8 | 269 | /* Return the name of register REGNUM. */ |
fc633446 | 270 | |
1ba53b71 | 271 | const char * |
90884b2b | 272 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 273 | { |
1ba53b71 L |
274 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
275 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
276 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
277 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
278 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
279 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
280 | return i386_byte_names[regnum - tdep->al_regnum]; | |
281 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
282 | return i386_word_names[regnum - tdep->ax_regnum]; | |
283 | ||
284 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
285 | } |
286 | ||
c4fc7f1b | 287 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
288 | number used by GDB. */ |
289 | ||
8201327c | 290 | static int |
d3f73121 | 291 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 292 | { |
20a6ec49 MD |
293 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
294 | ||
c4fc7f1b MK |
295 | /* This implements what GCC calls the "default" register map |
296 | (dbx_register_map[]). */ | |
297 | ||
85540d8c MK |
298 | if (reg >= 0 && reg <= 7) |
299 | { | |
9872ad24 JB |
300 | /* General-purpose registers. The debug info calls %ebp |
301 | register 4, and %esp register 5. */ | |
302 | if (reg == 4) | |
303 | return 5; | |
304 | else if (reg == 5) | |
305 | return 4; | |
306 | else return reg; | |
85540d8c MK |
307 | } |
308 | else if (reg >= 12 && reg <= 19) | |
309 | { | |
310 | /* Floating-point registers. */ | |
20a6ec49 | 311 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
312 | } |
313 | else if (reg >= 21 && reg <= 28) | |
314 | { | |
315 | /* SSE registers. */ | |
c131fcee L |
316 | int ymm0_regnum = tdep->ymm0_regnum; |
317 | ||
318 | if (ymm0_regnum >= 0 | |
319 | && i386_xmm_regnum_p (gdbarch, reg)) | |
320 | return reg - 21 + ymm0_regnum; | |
321 | else | |
322 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
323 | } |
324 | else if (reg >= 29 && reg <= 36) | |
325 | { | |
326 | /* MMX registers. */ | |
20a6ec49 | 327 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
328 | } |
329 | ||
330 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 331 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
332 | } |
333 | ||
c4fc7f1b MK |
334 | /* Convert SVR4 register number REG to the appropriate register number |
335 | used by GDB. */ | |
85540d8c | 336 | |
8201327c | 337 | static int |
d3f73121 | 338 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 339 | { |
20a6ec49 MD |
340 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
341 | ||
c4fc7f1b MK |
342 | /* This implements the GCC register map that tries to be compatible |
343 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
344 | ||
345 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
346 | numbers the floating point registers differently. */ |
347 | if (reg >= 0 && reg <= 9) | |
348 | { | |
acd5c798 | 349 | /* General-purpose registers. */ |
85540d8c MK |
350 | return reg; |
351 | } | |
352 | else if (reg >= 11 && reg <= 18) | |
353 | { | |
354 | /* Floating-point registers. */ | |
20a6ec49 | 355 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 356 | } |
c6f4c129 | 357 | else if (reg >= 21 && reg <= 36) |
85540d8c | 358 | { |
c4fc7f1b | 359 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 360 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
361 | } |
362 | ||
c6f4c129 JB |
363 | switch (reg) |
364 | { | |
20a6ec49 MD |
365 | case 37: return I387_FCTRL_REGNUM (tdep); |
366 | case 38: return I387_FSTAT_REGNUM (tdep); | |
367 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
368 | case 40: return I386_ES_REGNUM; |
369 | case 41: return I386_CS_REGNUM; | |
370 | case 42: return I386_SS_REGNUM; | |
371 | case 43: return I386_DS_REGNUM; | |
372 | case 44: return I386_FS_REGNUM; | |
373 | case 45: return I386_GS_REGNUM; | |
374 | } | |
375 | ||
85540d8c | 376 | /* This will hopefully provoke a warning. */ |
d3f73121 | 377 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 378 | } |
5716833c | 379 | |
fc338970 | 380 | \f |
917317f4 | 381 | |
fc338970 MK |
382 | /* This is the variable that is set with "set disassembly-flavor", and |
383 | its legitimate values. */ | |
53904c9e AC |
384 | static const char att_flavor[] = "att"; |
385 | static const char intel_flavor[] = "intel"; | |
40478521 | 386 | static const char *const valid_flavors[] = |
c5aa993b | 387 | { |
c906108c SS |
388 | att_flavor, |
389 | intel_flavor, | |
390 | NULL | |
391 | }; | |
53904c9e | 392 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 393 | \f |
c906108c | 394 | |
acd5c798 MK |
395 | /* Use the program counter to determine the contents and size of a |
396 | breakpoint instruction. Return a pointer to a string of bytes that | |
397 | encode a breakpoint instruction, store the length of the string in | |
398 | *LEN and optionally adjust *PC to point to the correct memory | |
399 | location for inserting the breakpoint. | |
c906108c | 400 | |
acd5c798 MK |
401 | On the i386 we have a single breakpoint that fits in a single byte |
402 | and can be inserted anywhere. | |
c906108c | 403 | |
acd5c798 | 404 | This function is 64-bit safe. */ |
63c0089f MK |
405 | |
406 | static const gdb_byte * | |
67d57894 | 407 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 408 | { |
63c0089f MK |
409 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
410 | ||
acd5c798 MK |
411 | *len = sizeof (break_insn); |
412 | return break_insn; | |
c906108c | 413 | } |
237fc4c9 PA |
414 | \f |
415 | /* Displaced instruction handling. */ | |
416 | ||
1903f0e6 DE |
417 | /* Skip the legacy instruction prefixes in INSN. |
418 | Not all prefixes are valid for any particular insn | |
419 | but we needn't care, the insn will fault if it's invalid. | |
420 | The result is a pointer to the first opcode byte, | |
421 | or NULL if we run off the end of the buffer. */ | |
422 | ||
423 | static gdb_byte * | |
424 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
425 | { | |
426 | gdb_byte *end = insn + max_len; | |
427 | ||
428 | while (insn < end) | |
429 | { | |
430 | switch (*insn) | |
431 | { | |
432 | case DATA_PREFIX_OPCODE: | |
433 | case ADDR_PREFIX_OPCODE: | |
434 | case CS_PREFIX_OPCODE: | |
435 | case DS_PREFIX_OPCODE: | |
436 | case ES_PREFIX_OPCODE: | |
437 | case FS_PREFIX_OPCODE: | |
438 | case GS_PREFIX_OPCODE: | |
439 | case SS_PREFIX_OPCODE: | |
440 | case LOCK_PREFIX_OPCODE: | |
441 | case REPE_PREFIX_OPCODE: | |
442 | case REPNE_PREFIX_OPCODE: | |
443 | ++insn; | |
444 | continue; | |
445 | default: | |
446 | return insn; | |
447 | } | |
448 | } | |
449 | ||
450 | return NULL; | |
451 | } | |
237fc4c9 PA |
452 | |
453 | static int | |
1903f0e6 | 454 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 455 | { |
1777feb0 | 456 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
457 | if (insn[0] == 0xea) |
458 | return 1; | |
459 | ||
460 | if (insn[0] == 0xff) | |
461 | { | |
1777feb0 | 462 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
463 | if ((insn[1] & 0x38) == 0x20) |
464 | return 1; | |
465 | ||
1777feb0 | 466 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
467 | if ((insn[1] & 0x38) == 0x28) |
468 | return 1; | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | static int | |
1903f0e6 | 475 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 476 | { |
1777feb0 | 477 | /* call far, absolute. */ |
237fc4c9 PA |
478 | if (insn[0] == 0x9a) |
479 | return 1; | |
480 | ||
481 | if (insn[0] == 0xff) | |
482 | { | |
1777feb0 | 483 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
484 | if ((insn[1] & 0x38) == 0x10) |
485 | return 1; | |
486 | ||
1777feb0 | 487 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
488 | if ((insn[1] & 0x38) == 0x18) |
489 | return 1; | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | static int | |
1903f0e6 | 496 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
497 | { |
498 | switch (insn[0]) | |
499 | { | |
1777feb0 | 500 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 501 | case 0xc3: /* ret near */ |
1777feb0 | 502 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
503 | case 0xcb: /* ret far */ |
504 | case 0xcf: /* iret */ | |
505 | return 1; | |
506 | ||
507 | default: | |
508 | return 0; | |
509 | } | |
510 | } | |
511 | ||
512 | static int | |
1903f0e6 | 513 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
514 | { |
515 | if (i386_absolute_call_p (insn)) | |
516 | return 1; | |
517 | ||
1777feb0 | 518 | /* call near, relative. */ |
237fc4c9 PA |
519 | if (insn[0] == 0xe8) |
520 | return 1; | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
237fc4c9 PA |
525 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
526 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 527 | |
237fc4c9 | 528 | static int |
b55078be | 529 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 530 | { |
9a7f938f JK |
531 | /* Is it 'int $0x80'? */ |
532 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
533 | /* Or is it 'sysenter'? */ | |
534 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
535 | /* Or is it 'syscall'? */ | |
536 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
537 | { |
538 | *lengthp = 2; | |
539 | return 1; | |
540 | } | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
b55078be DE |
545 | /* Some kernels may run one past a syscall insn, so we have to cope. |
546 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
547 | ||
548 | struct displaced_step_closure * | |
549 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
550 | CORE_ADDR from, CORE_ADDR to, | |
551 | struct regcache *regs) | |
552 | { | |
553 | size_t len = gdbarch_max_insn_length (gdbarch); | |
554 | gdb_byte *buf = xmalloc (len); | |
555 | ||
556 | read_memory (from, buf, len); | |
557 | ||
558 | /* GDB may get control back after the insn after the syscall. | |
559 | Presumably this is a kernel bug. | |
560 | If this is a syscall, make sure there's a nop afterwards. */ | |
561 | { | |
562 | int syscall_length; | |
563 | gdb_byte *insn; | |
564 | ||
565 | insn = i386_skip_prefixes (buf, len); | |
566 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
567 | insn[syscall_length] = NOP_OPCODE; | |
568 | } | |
569 | ||
570 | write_memory (to, buf, len); | |
571 | ||
572 | if (debug_displaced) | |
573 | { | |
574 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
575 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
576 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
577 | } | |
578 | ||
579 | return (struct displaced_step_closure *) buf; | |
580 | } | |
581 | ||
237fc4c9 PA |
582 | /* Fix up the state of registers and memory after having single-stepped |
583 | a displaced instruction. */ | |
1903f0e6 | 584 | |
237fc4c9 PA |
585 | void |
586 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
587 | struct displaced_step_closure *closure, | |
588 | CORE_ADDR from, CORE_ADDR to, | |
589 | struct regcache *regs) | |
590 | { | |
e17a4113 UW |
591 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
592 | ||
237fc4c9 PA |
593 | /* The offset we applied to the instruction's address. |
594 | This could well be negative (when viewed as a signed 32-bit | |
595 | value), but ULONGEST won't reflect that, so take care when | |
596 | applying it. */ | |
597 | ULONGEST insn_offset = to - from; | |
598 | ||
599 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
600 | copy of the instruction. */ | |
601 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
602 | /* The start of the insn, needed in case we see some prefixes. */ |
603 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
604 | |
605 | if (debug_displaced) | |
606 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 607 | "displaced: fixup (%s, %s), " |
237fc4c9 | 608 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
609 | paddress (gdbarch, from), paddress (gdbarch, to), |
610 | insn[0], insn[1]); | |
237fc4c9 PA |
611 | |
612 | /* The list of issues to contend with here is taken from | |
613 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
614 | Yay for Free Software! */ | |
615 | ||
616 | /* Relocate the %eip, if necessary. */ | |
617 | ||
1903f0e6 DE |
618 | /* The instruction recognizers we use assume any leading prefixes |
619 | have been skipped. */ | |
620 | { | |
621 | /* This is the size of the buffer in closure. */ | |
622 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
623 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
624 | /* If there are too many prefixes, just ignore the insn. | |
625 | It will fault when run. */ | |
626 | if (opcode != NULL) | |
627 | insn = opcode; | |
628 | } | |
629 | ||
237fc4c9 PA |
630 | /* Except in the case of absolute or indirect jump or call |
631 | instructions, or a return instruction, the new eip is relative to | |
632 | the displaced instruction; make it relative. Well, signal | |
633 | handler returns don't need relocation either, but we use the | |
634 | value of %eip to recognize those; see below. */ | |
635 | if (! i386_absolute_jmp_p (insn) | |
636 | && ! i386_absolute_call_p (insn) | |
637 | && ! i386_ret_p (insn)) | |
638 | { | |
639 | ULONGEST orig_eip; | |
b55078be | 640 | int insn_len; |
237fc4c9 PA |
641 | |
642 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
643 | ||
644 | /* A signal trampoline system call changes the %eip, resuming | |
645 | execution of the main program after the signal handler has | |
646 | returned. That makes them like 'return' instructions; we | |
647 | shouldn't relocate %eip. | |
648 | ||
649 | But most system calls don't, and we do need to relocate %eip. | |
650 | ||
651 | Our heuristic for distinguishing these cases: if stepping | |
652 | over the system call instruction left control directly after | |
653 | the instruction, the we relocate --- control almost certainly | |
654 | doesn't belong in the displaced copy. Otherwise, we assume | |
655 | the instruction has put control where it belongs, and leave | |
656 | it unrelocated. Goodness help us if there are PC-relative | |
657 | system calls. */ | |
658 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
659 | && orig_eip != to + (insn - insn_start) + insn_len |
660 | /* GDB can get control back after the insn after the syscall. | |
661 | Presumably this is a kernel bug. | |
662 | i386_displaced_step_copy_insn ensures its a nop, | |
663 | we add one to the length for it. */ | |
664 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
665 | { |
666 | if (debug_displaced) | |
667 | fprintf_unfiltered (gdb_stdlog, | |
668 | "displaced: syscall changed %%eip; " | |
669 | "not relocating\n"); | |
670 | } | |
671 | else | |
672 | { | |
673 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
674 | ||
1903f0e6 DE |
675 | /* If we just stepped over a breakpoint insn, we don't backup |
676 | the pc on purpose; this is to match behaviour without | |
677 | stepping. */ | |
237fc4c9 PA |
678 | |
679 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
680 | ||
681 | if (debug_displaced) | |
682 | fprintf_unfiltered (gdb_stdlog, | |
683 | "displaced: " | |
5af949e3 UW |
684 | "relocated %%eip from %s to %s\n", |
685 | paddress (gdbarch, orig_eip), | |
686 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
687 | } |
688 | } | |
689 | ||
690 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
691 | pushed value, and should be cleared. We'll leave this for later, | |
692 | since GDB already messes up the TF flag when stepping over a | |
693 | pushfl. */ | |
694 | ||
695 | /* If the instruction was a call, the return address now atop the | |
696 | stack is the address following the copied instruction. We need | |
697 | to make it the address following the original instruction. */ | |
698 | if (i386_call_p (insn)) | |
699 | { | |
700 | ULONGEST esp; | |
701 | ULONGEST retaddr; | |
702 | const ULONGEST retaddr_len = 4; | |
703 | ||
704 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 705 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 706 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 707 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
708 | |
709 | if (debug_displaced) | |
710 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
711 | "displaced: relocated return addr at %s to %s\n", |
712 | paddress (gdbarch, esp), | |
713 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
714 | } |
715 | } | |
dde08ee1 PA |
716 | |
717 | static void | |
718 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
719 | { | |
720 | target_write_memory (*to, buf, len); | |
721 | *to += len; | |
722 | } | |
723 | ||
724 | static void | |
725 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
726 | CORE_ADDR *to, CORE_ADDR oldloc) | |
727 | { | |
728 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
729 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
730 | int offset = 0, rel32, newrel; | |
731 | int insn_length; | |
732 | gdb_byte *insn = buf; | |
733 | ||
734 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
735 | ||
736 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
737 | I386_MAX_INSN_LEN, oldloc); | |
738 | ||
739 | /* Get past the prefixes. */ | |
740 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
741 | ||
742 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
743 | the address pushed being the location where the original call in | |
744 | the user program would return to. */ | |
745 | if (insn[0] == 0xe8) | |
746 | { | |
747 | gdb_byte push_buf[16]; | |
748 | unsigned int ret_addr; | |
749 | ||
750 | /* Where "ret" in the original code will return to. */ | |
751 | ret_addr = oldloc + insn_length; | |
1777feb0 | 752 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 753 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
754 | /* Push the push. */ |
755 | append_insns (to, 5, push_buf); | |
756 | ||
757 | /* Convert the relative call to a relative jump. */ | |
758 | insn[0] = 0xe9; | |
759 | ||
760 | /* Adjust the destination offset. */ | |
761 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
762 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
763 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
764 | ||
765 | if (debug_displaced) | |
766 | fprintf_unfiltered (gdb_stdlog, | |
767 | "Adjusted insn rel32=%s at %s to" | |
768 | " rel32=%s at %s\n", | |
769 | hex_string (rel32), paddress (gdbarch, oldloc), | |
770 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
771 | |
772 | /* Write the adjusted jump into its displaced location. */ | |
773 | append_insns (to, 5, insn); | |
774 | return; | |
775 | } | |
776 | ||
777 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
778 | handled above. */ | |
779 | if (insn[0] == 0xe9) | |
780 | offset = 1; | |
781 | /* Adjust conditional jumps. */ | |
782 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
783 | offset = 2; | |
784 | ||
785 | if (offset) | |
786 | { | |
787 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
788 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 789 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
790 | if (debug_displaced) |
791 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
792 | "Adjusted insn rel32=%s at %s to" |
793 | " rel32=%s at %s\n", | |
dde08ee1 PA |
794 | hex_string (rel32), paddress (gdbarch, oldloc), |
795 | hex_string (newrel), paddress (gdbarch, *to)); | |
796 | } | |
797 | ||
798 | /* Write the adjusted instructions into their displaced | |
799 | location. */ | |
800 | append_insns (to, insn_length, buf); | |
801 | } | |
802 | ||
fc338970 | 803 | \f |
acd5c798 MK |
804 | #ifdef I386_REGNO_TO_SYMMETRY |
805 | #error "The Sequent Symmetry is no longer supported." | |
806 | #endif | |
c906108c | 807 | |
acd5c798 MK |
808 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
809 | and %esp "belong" to the calling function. Therefore these | |
810 | registers should be saved if they're going to be modified. */ | |
c906108c | 811 | |
acd5c798 MK |
812 | /* The maximum number of saved registers. This should include all |
813 | registers mentioned above, and %eip. */ | |
a3386186 | 814 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
815 | |
816 | struct i386_frame_cache | |
c906108c | 817 | { |
acd5c798 MK |
818 | /* Base address. */ |
819 | CORE_ADDR base; | |
8fbca658 | 820 | int base_p; |
772562f8 | 821 | LONGEST sp_offset; |
acd5c798 MK |
822 | CORE_ADDR pc; |
823 | ||
fd13a04a AC |
824 | /* Saved registers. */ |
825 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 826 | CORE_ADDR saved_sp; |
e0c62198 | 827 | int saved_sp_reg; |
acd5c798 MK |
828 | int pc_in_eax; |
829 | ||
830 | /* Stack space reserved for local variables. */ | |
831 | long locals; | |
832 | }; | |
833 | ||
834 | /* Allocate and initialize a frame cache. */ | |
835 | ||
836 | static struct i386_frame_cache * | |
fd13a04a | 837 | i386_alloc_frame_cache (void) |
acd5c798 MK |
838 | { |
839 | struct i386_frame_cache *cache; | |
840 | int i; | |
841 | ||
842 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
843 | ||
844 | /* Base address. */ | |
8fbca658 | 845 | cache->base_p = 0; |
acd5c798 MK |
846 | cache->base = 0; |
847 | cache->sp_offset = -4; | |
848 | cache->pc = 0; | |
849 | ||
fd13a04a AC |
850 | /* Saved registers. We initialize these to -1 since zero is a valid |
851 | offset (that's where %ebp is supposed to be stored). */ | |
852 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
853 | cache->saved_regs[i] = -1; | |
acd5c798 | 854 | cache->saved_sp = 0; |
e0c62198 | 855 | cache->saved_sp_reg = -1; |
acd5c798 MK |
856 | cache->pc_in_eax = 0; |
857 | ||
858 | /* Frameless until proven otherwise. */ | |
859 | cache->locals = -1; | |
860 | ||
861 | return cache; | |
862 | } | |
c906108c | 863 | |
acd5c798 MK |
864 | /* If the instruction at PC is a jump, return the address of its |
865 | target. Otherwise, return PC. */ | |
c906108c | 866 | |
acd5c798 | 867 | static CORE_ADDR |
e17a4113 | 868 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 869 | { |
e17a4113 | 870 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 871 | gdb_byte op; |
acd5c798 MK |
872 | long delta = 0; |
873 | int data16 = 0; | |
c906108c | 874 | |
3dcabaa8 MS |
875 | if (target_read_memory (pc, &op, 1)) |
876 | return pc; | |
877 | ||
acd5c798 | 878 | if (op == 0x66) |
c906108c | 879 | { |
c906108c | 880 | data16 = 1; |
e17a4113 | 881 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
882 | } |
883 | ||
acd5c798 | 884 | switch (op) |
c906108c SS |
885 | { |
886 | case 0xe9: | |
fc338970 | 887 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
888 | if (data16) |
889 | { | |
e17a4113 | 890 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 891 | |
fc338970 MK |
892 | /* Include the size of the jmp instruction (including the |
893 | 0x66 prefix). */ | |
acd5c798 | 894 | delta += 4; |
c906108c SS |
895 | } |
896 | else | |
897 | { | |
e17a4113 | 898 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 899 | |
acd5c798 MK |
900 | /* Include the size of the jmp instruction. */ |
901 | delta += 5; | |
c906108c SS |
902 | } |
903 | break; | |
904 | case 0xeb: | |
fc338970 | 905 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 906 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 907 | |
acd5c798 | 908 | delta += data16 + 2; |
c906108c SS |
909 | break; |
910 | } | |
c906108c | 911 | |
acd5c798 MK |
912 | return pc + delta; |
913 | } | |
fc338970 | 914 | |
acd5c798 MK |
915 | /* Check whether PC points at a prologue for a function returning a |
916 | structure or union. If so, it updates CACHE and returns the | |
917 | address of the first instruction after the code sequence that | |
918 | removes the "hidden" argument from the stack or CURRENT_PC, | |
919 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 920 | |
acd5c798 MK |
921 | static CORE_ADDR |
922 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
923 | struct i386_frame_cache *cache) | |
c906108c | 924 | { |
acd5c798 MK |
925 | /* Functions that return a structure or union start with: |
926 | ||
927 | popl %eax 0x58 | |
928 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
929 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
930 | ||
931 | (the System V compiler puts out the second `xchg' instruction, | |
932 | and the assembler doesn't try to optimize it, so the 'sib' form | |
933 | gets generated). This sequence is used to get the address of the | |
934 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
935 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
936 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
937 | gdb_byte buf[4]; | |
938 | gdb_byte op; | |
c906108c | 939 | |
acd5c798 MK |
940 | if (current_pc <= pc) |
941 | return pc; | |
942 | ||
3dcabaa8 MS |
943 | if (target_read_memory (pc, &op, 1)) |
944 | return pc; | |
c906108c | 945 | |
acd5c798 MK |
946 | if (op != 0x58) /* popl %eax */ |
947 | return pc; | |
c906108c | 948 | |
3dcabaa8 MS |
949 | if (target_read_memory (pc + 1, buf, 4)) |
950 | return pc; | |
951 | ||
acd5c798 MK |
952 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
953 | return pc; | |
c906108c | 954 | |
acd5c798 | 955 | if (current_pc == pc) |
c906108c | 956 | { |
acd5c798 MK |
957 | cache->sp_offset += 4; |
958 | return current_pc; | |
c906108c SS |
959 | } |
960 | ||
acd5c798 | 961 | if (current_pc == pc + 1) |
c906108c | 962 | { |
acd5c798 MK |
963 | cache->pc_in_eax = 1; |
964 | return current_pc; | |
965 | } | |
966 | ||
967 | if (buf[1] == proto1[1]) | |
968 | return pc + 4; | |
969 | else | |
970 | return pc + 5; | |
971 | } | |
972 | ||
973 | static CORE_ADDR | |
974 | i386_skip_probe (CORE_ADDR pc) | |
975 | { | |
976 | /* A function may start with | |
fc338970 | 977 | |
acd5c798 MK |
978 | pushl constant |
979 | call _probe | |
980 | addl $4, %esp | |
fc338970 | 981 | |
acd5c798 MK |
982 | followed by |
983 | ||
984 | pushl %ebp | |
fc338970 | 985 | |
acd5c798 | 986 | etc. */ |
63c0089f MK |
987 | gdb_byte buf[8]; |
988 | gdb_byte op; | |
fc338970 | 989 | |
3dcabaa8 MS |
990 | if (target_read_memory (pc, &op, 1)) |
991 | return pc; | |
acd5c798 MK |
992 | |
993 | if (op == 0x68 || op == 0x6a) | |
994 | { | |
995 | int delta; | |
c906108c | 996 | |
acd5c798 MK |
997 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
998 | four-byte operand, depending on the opcode. */ | |
c906108c | 999 | if (op == 0x68) |
acd5c798 | 1000 | delta = 5; |
c906108c | 1001 | else |
acd5c798 | 1002 | delta = 2; |
c906108c | 1003 | |
acd5c798 MK |
1004 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1005 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1006 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1007 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1008 | pc += delta + sizeof (buf); |
c906108c SS |
1009 | } |
1010 | ||
acd5c798 MK |
1011 | return pc; |
1012 | } | |
1013 | ||
92dd43fa MK |
1014 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1015 | stack pointer. Check whether PC points to such code, and update | |
1016 | CACHE accordingly. Return the first instruction after the code | |
1017 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1018 | recognize the code, return PC. */ | |
1019 | ||
1020 | static CORE_ADDR | |
1021 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1022 | struct i386_frame_cache *cache) | |
1023 | { | |
e0c62198 L |
1024 | /* There are 2 code sequences to re-align stack before the frame |
1025 | gets set up: | |
1026 | ||
1027 | 1. Use a caller-saved saved register: | |
1028 | ||
1029 | leal 4(%esp), %reg | |
1030 | andl $-XXX, %esp | |
1031 | pushl -4(%reg) | |
1032 | ||
1033 | 2. Use a callee-saved saved register: | |
1034 | ||
1035 | pushl %reg | |
1036 | leal 8(%esp), %reg | |
1037 | andl $-XXX, %esp | |
1038 | pushl -4(%reg) | |
1039 | ||
1040 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1041 | ||
1042 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1043 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1044 | */ | |
1045 | ||
1046 | gdb_byte buf[14]; | |
1047 | int reg; | |
1048 | int offset, offset_and; | |
1049 | static int regnums[8] = { | |
1050 | I386_EAX_REGNUM, /* %eax */ | |
1051 | I386_ECX_REGNUM, /* %ecx */ | |
1052 | I386_EDX_REGNUM, /* %edx */ | |
1053 | I386_EBX_REGNUM, /* %ebx */ | |
1054 | I386_ESP_REGNUM, /* %esp */ | |
1055 | I386_EBP_REGNUM, /* %ebp */ | |
1056 | I386_ESI_REGNUM, /* %esi */ | |
1057 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1058 | }; |
92dd43fa | 1059 | |
e0c62198 L |
1060 | if (target_read_memory (pc, buf, sizeof buf)) |
1061 | return pc; | |
1062 | ||
1063 | /* Check caller-saved saved register. The first instruction has | |
1064 | to be "leal 4(%esp), %reg". */ | |
1065 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1066 | { | |
1067 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1068 | if ((buf[1] & 0xc7) != 0x44) | |
1069 | return pc; | |
1070 | ||
1071 | /* REG has register number. */ | |
1072 | reg = (buf[1] >> 3) & 7; | |
1073 | offset = 4; | |
1074 | } | |
1075 | else | |
1076 | { | |
1077 | /* Check callee-saved saved register. The first instruction | |
1078 | has to be "pushl %reg". */ | |
1079 | if ((buf[0] & 0xf8) != 0x50) | |
1080 | return pc; | |
1081 | ||
1082 | /* Get register. */ | |
1083 | reg = buf[0] & 0x7; | |
1084 | ||
1085 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1086 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1087 | return pc; | |
1088 | ||
1089 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1090 | if ((buf[2] & 0xc7) != 0x44) | |
1091 | return pc; | |
1092 | ||
1093 | /* REG has register number. Registers in pushl and leal have to | |
1094 | be the same. */ | |
1095 | if (reg != ((buf[2] >> 3) & 7)) | |
1096 | return pc; | |
1097 | ||
1098 | offset = 5; | |
1099 | } | |
1100 | ||
1101 | /* Rigister can't be %esp nor %ebp. */ | |
1102 | if (reg == 4 || reg == 5) | |
1103 | return pc; | |
1104 | ||
1105 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1106 | if (buf[offset + 1] != 0xe4 | |
1107 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1108 | return pc; | |
1109 | ||
1110 | offset_and = offset; | |
1111 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1112 | ||
1113 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1114 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1115 | if (buf[offset] != 0xff | |
1116 | || buf[offset + 2] != 0xfc | |
1117 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1118 | return pc; | |
1119 | ||
1120 | /* R/M has register. Registers in leal and pushl have to be the | |
1121 | same. */ | |
1122 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1123 | return pc; |
1124 | ||
e0c62198 L |
1125 | if (current_pc > pc + offset_and) |
1126 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1127 | |
e0c62198 | 1128 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1129 | } |
1130 | ||
37bdc87e | 1131 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1132 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1133 | |
1134 | /* Instruction description. */ | |
1135 | struct i386_insn | |
1136 | { | |
1137 | size_t len; | |
237fc4c9 PA |
1138 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1139 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1140 | }; |
1141 | ||
a3fcb948 | 1142 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1143 | |
a3fcb948 JG |
1144 | static int |
1145 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1146 | { |
63c0089f | 1147 | gdb_byte op; |
37bdc87e | 1148 | |
3dcabaa8 | 1149 | if (target_read_memory (pc, &op, 1)) |
a3fcb948 | 1150 | return 0; |
37bdc87e | 1151 | |
a3fcb948 | 1152 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1153 | { |
a3fcb948 JG |
1154 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1155 | int insn_matched = 1; | |
1156 | size_t i; | |
37bdc87e | 1157 | |
a3fcb948 JG |
1158 | gdb_assert (pattern.len > 1); |
1159 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1160 | |
a3fcb948 JG |
1161 | if (target_read_memory (pc + 1, buf, pattern.len - 1)) |
1162 | return 0; | |
613e8135 | 1163 | |
a3fcb948 JG |
1164 | for (i = 1; i < pattern.len; i++) |
1165 | { | |
1166 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1167 | insn_matched = 0; | |
37bdc87e | 1168 | } |
a3fcb948 JG |
1169 | return insn_matched; |
1170 | } | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1175 | the first instruction description that matches. Otherwise, return | |
1176 | NULL. */ | |
1177 | ||
1178 | static struct i386_insn * | |
1179 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1180 | { | |
1181 | struct i386_insn *pattern; | |
1182 | ||
1183 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1184 | { | |
1185 | if (i386_match_pattern (pc, *pattern)) | |
1186 | return pattern; | |
37bdc87e MK |
1187 | } |
1188 | ||
1189 | return NULL; | |
1190 | } | |
1191 | ||
a3fcb948 JG |
1192 | /* Return whether PC points inside a sequence of instructions that |
1193 | matches INSN_PATTERNS. */ | |
1194 | ||
1195 | static int | |
1196 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1197 | { | |
1198 | CORE_ADDR current_pc; | |
1199 | int ix, i; | |
a3fcb948 JG |
1200 | struct i386_insn *insn; |
1201 | ||
1202 | insn = i386_match_insn (pc, insn_patterns); | |
1203 | if (insn == NULL) | |
1204 | return 0; | |
1205 | ||
8bbdd3f4 | 1206 | current_pc = pc; |
a3fcb948 JG |
1207 | ix = insn - insn_patterns; |
1208 | for (i = ix - 1; i >= 0; i--) | |
1209 | { | |
8bbdd3f4 MK |
1210 | current_pc -= insn_patterns[i].len; |
1211 | ||
a3fcb948 JG |
1212 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1213 | return 0; | |
a3fcb948 JG |
1214 | } |
1215 | ||
1216 | current_pc = pc + insn->len; | |
1217 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1218 | { | |
1219 | if (!i386_match_pattern (current_pc, *insn)) | |
1220 | return 0; | |
1221 | ||
1222 | current_pc += insn->len; | |
1223 | } | |
1224 | ||
1225 | return 1; | |
1226 | } | |
1227 | ||
37bdc87e MK |
1228 | /* Some special instructions that might be migrated by GCC into the |
1229 | part of the prologue that sets up the new stack frame. Because the | |
1230 | stack frame hasn't been setup yet, no registers have been saved | |
1231 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1232 | touched. */ | |
1233 | ||
1234 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1235 | { | |
1777feb0 | 1236 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1237 | |
1238 | ??? Should we handle 16-bit operand-sizes here? */ | |
1239 | ||
1240 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1241 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1242 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1243 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1244 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1245 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1246 | { 5, { 0xb8 }, { 0xfe } }, | |
1247 | /* `movl imm32, %edx' */ | |
1248 | { 5, { 0xba }, { 0xff } }, | |
1249 | ||
1250 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1251 | encoding for `mov m32, %eax'. | |
1252 | ||
1253 | ??? Should we handle SIB adressing here? | |
1254 | ??? Should we handle 16-bit operand-sizes here? */ | |
1255 | ||
1256 | /* `movl m32, %eax' */ | |
1257 | { 5, { 0xa1 }, { 0xff } }, | |
1258 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1259 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1260 | /* `movl m32, %edx' */ | |
1261 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1262 | ||
1263 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1264 | Because of the symmetry, there are actually two ways to encode | |
1265 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1266 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1267 | ||
1268 | /* `subl %eax, %eax' */ | |
1269 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1270 | /* `subl %ecx, %ecx' */ | |
1271 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1272 | /* `subl %edx, %edx' */ | |
1273 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1274 | /* `xorl %eax, %eax' */ | |
1275 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1276 | /* `xorl %ecx, %ecx' */ | |
1277 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1278 | /* `xorl %edx, %edx' */ | |
1279 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1280 | { 0 } | |
1281 | }; | |
1282 | ||
e11481da PM |
1283 | |
1284 | /* Check whether PC points to a no-op instruction. */ | |
1285 | static CORE_ADDR | |
1286 | i386_skip_noop (CORE_ADDR pc) | |
1287 | { | |
1288 | gdb_byte op; | |
1289 | int check = 1; | |
1290 | ||
3dcabaa8 MS |
1291 | if (target_read_memory (pc, &op, 1)) |
1292 | return pc; | |
e11481da PM |
1293 | |
1294 | while (check) | |
1295 | { | |
1296 | check = 0; | |
1297 | /* Ignore `nop' instruction. */ | |
1298 | if (op == 0x90) | |
1299 | { | |
1300 | pc += 1; | |
3dcabaa8 MS |
1301 | if (target_read_memory (pc, &op, 1)) |
1302 | return pc; | |
e11481da PM |
1303 | check = 1; |
1304 | } | |
1305 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1306 | Microsoft system dlls often start with | |
1307 | a `mov %edi,%edi' instruction. | |
1308 | The 5 bytes before the function start are | |
1309 | filled with `nop' instructions. | |
1310 | This pattern can be used for hot-patching: | |
1311 | The `mov %edi, %edi' instruction can be replaced by a | |
1312 | near jump to the location of the 5 `nop' instructions | |
1313 | which can be replaced by a 32-bit jump to anywhere | |
1314 | in the 32-bit address space. */ | |
1315 | ||
1316 | else if (op == 0x8b) | |
1317 | { | |
3dcabaa8 MS |
1318 | if (target_read_memory (pc + 1, &op, 1)) |
1319 | return pc; | |
1320 | ||
e11481da PM |
1321 | if (op == 0xff) |
1322 | { | |
1323 | pc += 2; | |
3dcabaa8 MS |
1324 | if (target_read_memory (pc, &op, 1)) |
1325 | return pc; | |
1326 | ||
e11481da PM |
1327 | check = 1; |
1328 | } | |
1329 | } | |
1330 | } | |
1331 | return pc; | |
1332 | } | |
1333 | ||
acd5c798 MK |
1334 | /* Check whether PC points at a code that sets up a new stack frame. |
1335 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1336 | instruction after the sequence that sets up the frame or LIMIT, |
1337 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1338 | |
1339 | static CORE_ADDR | |
e17a4113 UW |
1340 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1341 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1342 | struct i386_frame_cache *cache) |
1343 | { | |
e17a4113 | 1344 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1345 | struct i386_insn *insn; |
63c0089f | 1346 | gdb_byte op; |
26604a34 | 1347 | int skip = 0; |
acd5c798 | 1348 | |
37bdc87e MK |
1349 | if (limit <= pc) |
1350 | return limit; | |
acd5c798 | 1351 | |
3dcabaa8 MS |
1352 | if (target_read_memory (pc, &op, 1)) |
1353 | return pc; | |
acd5c798 | 1354 | |
c906108c | 1355 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1356 | { |
acd5c798 MK |
1357 | /* Take into account that we've executed the `pushl %ebp' that |
1358 | starts this instruction sequence. */ | |
fd13a04a | 1359 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1360 | cache->sp_offset += 4; |
37bdc87e | 1361 | pc++; |
acd5c798 MK |
1362 | |
1363 | /* If that's all, return now. */ | |
37bdc87e MK |
1364 | if (limit <= pc) |
1365 | return limit; | |
26604a34 | 1366 | |
b4632131 | 1367 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1368 | GCC into the prologue and skip them. At this point in the |
1369 | prologue, code should only touch the scratch registers %eax, | |
1370 | %ecx and %edx, so while the number of posibilities is sheer, | |
1371 | it is limited. | |
5daa5b4e | 1372 | |
26604a34 MK |
1373 | Make sure we only skip these instructions if we later see the |
1374 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1375 | while (pc + skip < limit) |
26604a34 | 1376 | { |
37bdc87e MK |
1377 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1378 | if (insn == NULL) | |
1379 | break; | |
b4632131 | 1380 | |
37bdc87e | 1381 | skip += insn->len; |
26604a34 MK |
1382 | } |
1383 | ||
37bdc87e MK |
1384 | /* If that's all, return now. */ |
1385 | if (limit <= pc + skip) | |
1386 | return limit; | |
1387 | ||
3dcabaa8 MS |
1388 | if (target_read_memory (pc + skip, &op, 1)) |
1389 | return pc + skip; | |
37bdc87e | 1390 | |
26604a34 | 1391 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1392 | switch (op) |
c906108c SS |
1393 | { |
1394 | case 0x8b: | |
e17a4113 UW |
1395 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1396 | != 0xec) | |
37bdc87e | 1397 | return pc; |
c906108c SS |
1398 | break; |
1399 | case 0x89: | |
e17a4113 UW |
1400 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1401 | != 0xe5) | |
37bdc87e | 1402 | return pc; |
c906108c SS |
1403 | break; |
1404 | default: | |
37bdc87e | 1405 | return pc; |
c906108c | 1406 | } |
acd5c798 | 1407 | |
26604a34 MK |
1408 | /* OK, we actually have a frame. We just don't know how large |
1409 | it is yet. Set its size to zero. We'll adjust it if | |
1410 | necessary. We also now commit to skipping the special | |
1411 | instructions mentioned before. */ | |
acd5c798 | 1412 | cache->locals = 0; |
37bdc87e | 1413 | pc += (skip + 2); |
acd5c798 MK |
1414 | |
1415 | /* If that's all, return now. */ | |
37bdc87e MK |
1416 | if (limit <= pc) |
1417 | return limit; | |
acd5c798 | 1418 | |
fc338970 MK |
1419 | /* Check for stack adjustment |
1420 | ||
acd5c798 | 1421 | subl $XXX, %esp |
fc338970 | 1422 | |
fd35795f | 1423 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1424 | reg, so we don't have to worry about a data16 prefix. */ |
3dcabaa8 MS |
1425 | if (target_read_memory (pc, &op, 1)) |
1426 | return pc; | |
c906108c SS |
1427 | if (op == 0x83) |
1428 | { | |
fd35795f | 1429 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1430 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1431 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1432 | return pc; |
acd5c798 | 1433 | |
37bdc87e MK |
1434 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1435 | make sense to be negative). */ | |
e17a4113 | 1436 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1437 | return pc + 3; |
c906108c SS |
1438 | } |
1439 | else if (op == 0x81) | |
1440 | { | |
fd35795f | 1441 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1442 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1443 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1444 | return pc; |
acd5c798 | 1445 | |
fd35795f | 1446 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1447 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1448 | return pc + 6; |
c906108c SS |
1449 | } |
1450 | else | |
1451 | { | |
acd5c798 | 1452 | /* Some instruction other than `subl'. */ |
37bdc87e | 1453 | return pc; |
c906108c SS |
1454 | } |
1455 | } | |
37bdc87e | 1456 | else if (op == 0xc8) /* enter */ |
c906108c | 1457 | { |
e17a4113 | 1458 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1459 | return pc + 4; |
c906108c | 1460 | } |
21d0e8a4 | 1461 | |
acd5c798 | 1462 | return pc; |
21d0e8a4 MK |
1463 | } |
1464 | ||
acd5c798 MK |
1465 | /* Check whether PC points at code that saves registers on the stack. |
1466 | If so, it updates CACHE and returns the address of the first | |
1467 | instruction after the register saves or CURRENT_PC, whichever is | |
1468 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1469 | |
1470 | static CORE_ADDR | |
acd5c798 MK |
1471 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1472 | struct i386_frame_cache *cache) | |
6bff26de | 1473 | { |
99ab4326 | 1474 | CORE_ADDR offset = 0; |
63c0089f | 1475 | gdb_byte op; |
99ab4326 | 1476 | int i; |
c0d1d883 | 1477 | |
99ab4326 MK |
1478 | if (cache->locals > 0) |
1479 | offset -= cache->locals; | |
1480 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1481 | { | |
3dcabaa8 MS |
1482 | if (target_read_memory (pc, &op, 1)) |
1483 | return pc; | |
99ab4326 MK |
1484 | if (op < 0x50 || op > 0x57) |
1485 | break; | |
0d17c81d | 1486 | |
99ab4326 MK |
1487 | offset -= 4; |
1488 | cache->saved_regs[op - 0x50] = offset; | |
1489 | cache->sp_offset += 4; | |
1490 | pc++; | |
6bff26de MK |
1491 | } |
1492 | ||
acd5c798 | 1493 | return pc; |
22797942 AC |
1494 | } |
1495 | ||
acd5c798 MK |
1496 | /* Do a full analysis of the prologue at PC and update CACHE |
1497 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1498 | address where the analysis stopped. | |
ed84f6c1 | 1499 | |
fc338970 MK |
1500 | We handle these cases: |
1501 | ||
1502 | The startup sequence can be at the start of the function, or the | |
1503 | function can start with a branch to startup code at the end. | |
1504 | ||
1505 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1506 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1507 | once used in the System V compiler). | |
1508 | ||
1509 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1510 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1511 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1512 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1513 | |
1514 | Next, the registers used by this function are pushed. With the | |
1515 | System V compiler they will always be in the order: %edi, %esi, | |
1516 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1517 | restore %eax); however, the code below is willing to see the pushes | |
1518 | in any order, and will handle up to 8 of them. | |
1519 | ||
1520 | If the setup sequence is at the end of the function, then the next | |
1521 | instruction will be a branch back to the start. */ | |
c906108c | 1522 | |
acd5c798 | 1523 | static CORE_ADDR |
e17a4113 UW |
1524 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1525 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1526 | struct i386_frame_cache *cache) |
c906108c | 1527 | { |
e11481da | 1528 | pc = i386_skip_noop (pc); |
e17a4113 | 1529 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1530 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1531 | pc = i386_skip_probe (pc); | |
92dd43fa | 1532 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1533 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1534 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1535 | } |
1536 | ||
fc338970 | 1537 | /* Return PC of first real instruction. */ |
c906108c | 1538 | |
3a1e71e3 | 1539 | static CORE_ADDR |
6093d2eb | 1540 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1541 | { |
e17a4113 UW |
1542 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1543 | ||
63c0089f | 1544 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1545 | { |
1546 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1547 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1548 | }; |
acd5c798 MK |
1549 | struct i386_frame_cache cache; |
1550 | CORE_ADDR pc; | |
63c0089f | 1551 | gdb_byte op; |
acd5c798 | 1552 | int i; |
c5aa993b | 1553 | |
acd5c798 | 1554 | cache.locals = -1; |
e17a4113 | 1555 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1556 | if (cache.locals < 0) |
1557 | return start_pc; | |
c5aa993b | 1558 | |
acd5c798 | 1559 | /* Found valid frame setup. */ |
c906108c | 1560 | |
fc338970 MK |
1561 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1562 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1563 | %ebx: |
1564 | ||
fc338970 MK |
1565 | call 0x0 |
1566 | popl %ebx | |
1567 | movl %ebx,x(%ebp) (optional) | |
1568 | addl y,%ebx | |
1569 | ||
c906108c SS |
1570 | This code is with the rest of the prologue (at the end of the |
1571 | function), so we have to skip it to get to the first real | |
1572 | instruction at the start of the function. */ | |
c5aa993b | 1573 | |
c906108c SS |
1574 | for (i = 0; i < 6; i++) |
1575 | { | |
3dcabaa8 MS |
1576 | if (target_read_memory (pc + i, &op, 1)) |
1577 | return pc; | |
1578 | ||
c5aa993b | 1579 | if (pic_pat[i] != op) |
c906108c SS |
1580 | break; |
1581 | } | |
1582 | if (i == 6) | |
1583 | { | |
acd5c798 MK |
1584 | int delta = 6; |
1585 | ||
3dcabaa8 MS |
1586 | if (target_read_memory (pc + delta, &op, 1)) |
1587 | return pc; | |
c906108c | 1588 | |
c5aa993b | 1589 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1590 | { |
e17a4113 | 1591 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1592 | |
fc338970 | 1593 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1594 | delta += 3; |
fc338970 | 1595 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1596 | delta += 6; |
fc338970 | 1597 | else /* Unexpected instruction. */ |
acd5c798 MK |
1598 | delta = 0; |
1599 | ||
3dcabaa8 MS |
1600 | if (target_read_memory (pc + delta, &op, 1)) |
1601 | return pc; | |
c906108c | 1602 | } |
acd5c798 | 1603 | |
c5aa993b | 1604 | /* addl y,%ebx */ |
acd5c798 | 1605 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1606 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1607 | == 0xc3) | |
c906108c | 1608 | { |
acd5c798 | 1609 | pc += delta + 6; |
c906108c SS |
1610 | } |
1611 | } | |
c5aa993b | 1612 | |
e63bbc88 MK |
1613 | /* If the function starts with a branch (to startup code at the end) |
1614 | the last instruction should bring us back to the first | |
1615 | instruction of the real code. */ | |
e17a4113 UW |
1616 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1617 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1618 | |
1619 | return pc; | |
c906108c SS |
1620 | } |
1621 | ||
4309257c PM |
1622 | /* Check that the code pointed to by PC corresponds to a call to |
1623 | __main, skip it if so. Return PC otherwise. */ | |
1624 | ||
1625 | CORE_ADDR | |
1626 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1627 | { | |
e17a4113 | 1628 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1629 | gdb_byte op; |
1630 | ||
3dcabaa8 MS |
1631 | if (target_read_memory (pc, &op, 1)) |
1632 | return pc; | |
4309257c PM |
1633 | if (op == 0xe8) |
1634 | { | |
1635 | gdb_byte buf[4]; | |
1636 | ||
1637 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1638 | { | |
1639 | /* Make sure address is computed correctly as a 32bit | |
1640 | integer even if CORE_ADDR is 64 bit wide. */ | |
1641 | struct minimal_symbol *s; | |
e17a4113 | 1642 | CORE_ADDR call_dest; |
4309257c | 1643 | |
e17a4113 | 1644 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1645 | call_dest = call_dest & 0xffffffffU; |
1646 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1647 | if (s != NULL | |
1648 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1649 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1650 | pc += 5; | |
1651 | } | |
1652 | } | |
1653 | ||
1654 | return pc; | |
1655 | } | |
1656 | ||
acd5c798 | 1657 | /* This function is 64-bit safe. */ |
93924b6b | 1658 | |
acd5c798 MK |
1659 | static CORE_ADDR |
1660 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1661 | { |
63c0089f | 1662 | gdb_byte buf[8]; |
acd5c798 | 1663 | |
875f8d0e | 1664 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1665 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1666 | } |
acd5c798 | 1667 | \f |
93924b6b | 1668 | |
acd5c798 | 1669 | /* Normal frames. */ |
c5aa993b | 1670 | |
8fbca658 PA |
1671 | static void |
1672 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1673 | struct i386_frame_cache *cache) | |
a7769679 | 1674 | { |
e17a4113 UW |
1675 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1676 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1677 | gdb_byte buf[4]; |
acd5c798 MK |
1678 | int i; |
1679 | ||
8fbca658 | 1680 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1681 | |
1682 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1683 | which holds the base address for the current stack frame. | |
1684 | However, for functions that don't need it, the frame pointer is | |
1685 | optional. For these "frameless" functions the frame pointer is | |
1686 | actually the frame pointer of the calling frame. Signal | |
1687 | trampolines are just a special case of a "frameless" function. | |
1688 | They (usually) share their frame pointer with the frame that was | |
1689 | in progress when the signal occurred. */ | |
1690 | ||
10458914 | 1691 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1692 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1693 | if (cache->base == 0) |
620fa63a PA |
1694 | { |
1695 | cache->base_p = 1; | |
1696 | return; | |
1697 | } | |
acd5c798 MK |
1698 | |
1699 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1700 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1701 | |
acd5c798 | 1702 | if (cache->pc != 0) |
e17a4113 UW |
1703 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1704 | cache); | |
acd5c798 MK |
1705 | |
1706 | if (cache->locals < 0) | |
1707 | { | |
1708 | /* We didn't find a valid frame, which means that CACHE->base | |
1709 | currently holds the frame pointer for our calling frame. If | |
1710 | we're at the start of a function, or somewhere half-way its | |
1711 | prologue, the function's frame probably hasn't been fully | |
1712 | setup yet. Try to reconstruct the base address for the stack | |
1713 | frame by looking at the stack pointer. For truly "frameless" | |
1714 | functions this might work too. */ | |
1715 | ||
e0c62198 | 1716 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1717 | { |
8fbca658 PA |
1718 | /* Saved stack pointer has been saved. */ |
1719 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1720 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1721 | ||
92dd43fa MK |
1722 | /* We're halfway aligning the stack. */ |
1723 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1724 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1725 | ||
1726 | /* This will be added back below. */ | |
1727 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1728 | } | |
7618e12b DJ |
1729 | else if (cache->pc != 0 |
1730 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1731 | { |
7618e12b DJ |
1732 | /* We're in a known function, but did not find a frame |
1733 | setup. Assume that the function does not use %ebp. | |
1734 | Alternatively, we may have jumped to an invalid | |
1735 | address; in that case there is definitely no new | |
1736 | frame in %ebp. */ | |
10458914 | 1737 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1738 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1739 | + cache->sp_offset; | |
92dd43fa | 1740 | } |
7618e12b DJ |
1741 | else |
1742 | /* We're in an unknown function. We could not find the start | |
1743 | of the function to analyze the prologue; our best option is | |
1744 | to assume a typical frame layout with the caller's %ebp | |
1745 | saved. */ | |
1746 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1747 | } |
1748 | ||
8fbca658 PA |
1749 | if (cache->saved_sp_reg != -1) |
1750 | { | |
1751 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
1752 | register may be unavailable). */ | |
1753 | if (cache->saved_sp == 0 | |
1754 | && frame_register_read (this_frame, cache->saved_sp_reg, buf)) | |
1755 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1756 | } | |
acd5c798 MK |
1757 | /* Now that we have the base address for the stack frame we can |
1758 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 1759 | else if (cache->saved_sp == 0) |
92dd43fa | 1760 | cache->saved_sp = cache->base + 8; |
a7769679 | 1761 | |
acd5c798 MK |
1762 | /* Adjust all the saved registers such that they contain addresses |
1763 | instead of offsets. */ | |
1764 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1765 | if (cache->saved_regs[i] != -1) |
1766 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 1767 | |
8fbca658 PA |
1768 | cache->base_p = 1; |
1769 | } | |
1770 | ||
1771 | static struct i386_frame_cache * | |
1772 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1773 | { | |
1774 | volatile struct gdb_exception ex; | |
1775 | struct i386_frame_cache *cache; | |
1776 | ||
1777 | if (*this_cache) | |
1778 | return *this_cache; | |
1779 | ||
1780 | cache = i386_alloc_frame_cache (); | |
1781 | *this_cache = cache; | |
1782 | ||
1783 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
1784 | { | |
1785 | i386_frame_cache_1 (this_frame, cache); | |
1786 | } | |
1787 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1788 | throw_exception (ex); | |
1789 | ||
acd5c798 | 1790 | return cache; |
a7769679 MK |
1791 | } |
1792 | ||
3a1e71e3 | 1793 | static void |
10458914 | 1794 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1795 | struct frame_id *this_id) |
c906108c | 1796 | { |
10458914 | 1797 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1798 | |
1799 | /* This marks the outermost frame. */ | |
1800 | if (cache->base == 0) | |
1801 | return; | |
1802 | ||
3e210248 | 1803 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1804 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1805 | } | |
1806 | ||
8fbca658 PA |
1807 | static enum unwind_stop_reason |
1808 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1809 | void **this_cache) | |
1810 | { | |
1811 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
1812 | ||
1813 | if (!cache->base_p) | |
1814 | return UNWIND_UNAVAILABLE; | |
1815 | ||
1816 | /* This marks the outermost frame. */ | |
1817 | if (cache->base == 0) | |
1818 | return UNWIND_OUTERMOST; | |
1819 | ||
1820 | return UNWIND_NO_REASON; | |
1821 | } | |
1822 | ||
10458914 DJ |
1823 | static struct value * |
1824 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1825 | int regnum) | |
acd5c798 | 1826 | { |
10458914 | 1827 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1828 | |
1829 | gdb_assert (regnum >= 0); | |
1830 | ||
1831 | /* The System V ABI says that: | |
1832 | ||
1833 | "The flags register contains the system flags, such as the | |
1834 | direction flag and the carry flag. The direction flag must be | |
1835 | set to the forward (that is, zero) direction before entry and | |
1836 | upon exit from a function. Other user flags have no specified | |
1837 | role in the standard calling sequence and are not preserved." | |
1838 | ||
1839 | To guarantee the "upon exit" part of that statement we fake a | |
1840 | saved flags register that has its direction flag cleared. | |
1841 | ||
1842 | Note that GCC doesn't seem to rely on the fact that the direction | |
1843 | flag is cleared after a function return; it always explicitly | |
1844 | clears the flag before operations where it matters. | |
1845 | ||
1846 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1847 | right thing to do. The way we fake the flags register here makes | |
1848 | it impossible to change it. */ | |
1849 | ||
1850 | if (regnum == I386_EFLAGS_REGNUM) | |
1851 | { | |
10458914 | 1852 | ULONGEST val; |
c5aa993b | 1853 | |
10458914 DJ |
1854 | val = get_frame_register_unsigned (this_frame, regnum); |
1855 | val &= ~(1 << 10); | |
1856 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1857 | } |
1211c4e4 | 1858 | |
acd5c798 | 1859 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1860 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 1861 | |
fcf250e2 UW |
1862 | if (regnum == I386_ESP_REGNUM |
1863 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
1864 | { |
1865 | /* If the SP has been saved, but we don't know where, then this | |
1866 | means that SAVED_SP_REG register was found unavailable back | |
1867 | when we built the cache. */ | |
fcf250e2 | 1868 | if (cache->saved_sp == 0) |
8fbca658 PA |
1869 | return frame_unwind_got_register (this_frame, regnum, |
1870 | cache->saved_sp_reg); | |
1871 | else | |
1872 | return frame_unwind_got_constant (this_frame, regnum, | |
1873 | cache->saved_sp); | |
1874 | } | |
acd5c798 | 1875 | |
fd13a04a | 1876 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1877 | return frame_unwind_got_memory (this_frame, regnum, |
1878 | cache->saved_regs[regnum]); | |
fd13a04a | 1879 | |
10458914 | 1880 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1881 | } |
1882 | ||
1883 | static const struct frame_unwind i386_frame_unwind = | |
1884 | { | |
1885 | NORMAL_FRAME, | |
8fbca658 | 1886 | i386_frame_unwind_stop_reason, |
acd5c798 | 1887 | i386_frame_this_id, |
10458914 DJ |
1888 | i386_frame_prev_register, |
1889 | NULL, | |
1890 | default_frame_sniffer | |
acd5c798 | 1891 | }; |
06da04c6 MS |
1892 | |
1893 | /* Normal frames, but in a function epilogue. */ | |
1894 | ||
1895 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1896 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1897 | the function's stack frame. */ | |
1898 | ||
1899 | static int | |
1900 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1901 | { | |
1902 | gdb_byte insn; | |
e0d00bc7 JK |
1903 | struct symtab *symtab; |
1904 | ||
1905 | symtab = find_pc_symtab (pc); | |
1906 | if (symtab && symtab->epilogue_unwind_valid) | |
1907 | return 0; | |
06da04c6 MS |
1908 | |
1909 | if (target_read_memory (pc, &insn, 1)) | |
1910 | return 0; /* Can't read memory at pc. */ | |
1911 | ||
1912 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1913 | return 0; | |
1914 | ||
1915 | return 1; | |
1916 | } | |
1917 | ||
1918 | static int | |
1919 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1920 | struct frame_info *this_frame, | |
1921 | void **this_prologue_cache) | |
1922 | { | |
1923 | if (frame_relative_level (this_frame) == 0) | |
1924 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1925 | get_frame_pc (this_frame)); | |
1926 | else | |
1927 | return 0; | |
1928 | } | |
1929 | ||
1930 | static struct i386_frame_cache * | |
1931 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1932 | { | |
8fbca658 | 1933 | volatile struct gdb_exception ex; |
06da04c6 | 1934 | struct i386_frame_cache *cache; |
0d6c2135 | 1935 | CORE_ADDR sp; |
06da04c6 MS |
1936 | |
1937 | if (*this_cache) | |
1938 | return *this_cache; | |
1939 | ||
1940 | cache = i386_alloc_frame_cache (); | |
1941 | *this_cache = cache; | |
1942 | ||
8fbca658 PA |
1943 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
1944 | { | |
0d6c2135 | 1945 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 1946 | |
0d6c2135 MK |
1947 | /* At this point the stack looks as if we just entered the |
1948 | function, with the return address at the top of the | |
1949 | stack. */ | |
1950 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
1951 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 1952 | cache->saved_sp = cache->base + 8; |
8fbca658 | 1953 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 1954 | |
8fbca658 PA |
1955 | cache->base_p = 1; |
1956 | } | |
1957 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1958 | throw_exception (ex); | |
06da04c6 MS |
1959 | |
1960 | return cache; | |
1961 | } | |
1962 | ||
8fbca658 PA |
1963 | static enum unwind_stop_reason |
1964 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1965 | void **this_cache) | |
1966 | { | |
0d6c2135 MK |
1967 | struct i386_frame_cache *cache = |
1968 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
1969 | |
1970 | if (!cache->base_p) | |
1971 | return UNWIND_UNAVAILABLE; | |
1972 | ||
1973 | return UNWIND_NO_REASON; | |
1974 | } | |
1975 | ||
06da04c6 MS |
1976 | static void |
1977 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1978 | void **this_cache, | |
1979 | struct frame_id *this_id) | |
1980 | { | |
0d6c2135 MK |
1981 | struct i386_frame_cache *cache = |
1982 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 1983 | |
8fbca658 PA |
1984 | if (!cache->base_p) |
1985 | return; | |
1986 | ||
06da04c6 MS |
1987 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1988 | } | |
1989 | ||
0d6c2135 MK |
1990 | static struct value * |
1991 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
1992 | void **this_cache, int regnum) | |
1993 | { | |
1994 | /* Make sure we've initialized the cache. */ | |
1995 | i386_epilogue_frame_cache (this_frame, this_cache); | |
1996 | ||
1997 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
1998 | } | |
1999 | ||
06da04c6 MS |
2000 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2001 | { | |
2002 | NORMAL_FRAME, | |
8fbca658 | 2003 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2004 | i386_epilogue_frame_this_id, |
0d6c2135 | 2005 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2006 | NULL, |
2007 | i386_epilogue_frame_sniffer | |
2008 | }; | |
acd5c798 MK |
2009 | \f |
2010 | ||
a3fcb948 JG |
2011 | /* Stack-based trampolines. */ |
2012 | ||
2013 | /* These trampolines are used on cross x86 targets, when taking the | |
2014 | address of a nested function. When executing these trampolines, | |
2015 | no stack frame is set up, so we are in a similar situation as in | |
2016 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2017 | ||
2018 | /* Static chain passed in register. */ | |
2019 | ||
2020 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2021 | { | |
2022 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2023 | { 5, { 0xb8 }, { 0xfe } }, | |
2024 | ||
2025 | /* `jmp imm32' */ | |
2026 | { 5, { 0xe9 }, { 0xff } }, | |
2027 | ||
2028 | {0} | |
2029 | }; | |
2030 | ||
2031 | /* Static chain passed on stack (when regparm=3). */ | |
2032 | ||
2033 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2034 | { | |
2035 | /* `push imm32' */ | |
2036 | { 5, { 0x68 }, { 0xff } }, | |
2037 | ||
2038 | /* `jmp imm32' */ | |
2039 | { 5, { 0xe9 }, { 0xff } }, | |
2040 | ||
2041 | {0} | |
2042 | }; | |
2043 | ||
2044 | /* Return whether PC points inside a stack trampoline. */ | |
2045 | ||
2046 | static int | |
2047 | i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2048 | { | |
2049 | gdb_byte insn; | |
2c02bd72 | 2050 | const char *name; |
a3fcb948 JG |
2051 | |
2052 | /* A stack trampoline is detected if no name is associated | |
2053 | to the current pc and if it points inside a trampoline | |
2054 | sequence. */ | |
2055 | ||
2056 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2057 | if (name) | |
2058 | return 0; | |
2059 | ||
2060 | if (target_read_memory (pc, &insn, 1)) | |
2061 | return 0; | |
2062 | ||
2063 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2064 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2065 | return 0; | |
2066 | ||
2067 | return 1; | |
2068 | } | |
2069 | ||
2070 | static int | |
2071 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2072 | struct frame_info *this_frame, |
2073 | void **this_cache) | |
a3fcb948 JG |
2074 | { |
2075 | if (frame_relative_level (this_frame) == 0) | |
2076 | return i386_in_stack_tramp_p (get_frame_arch (this_frame), | |
2077 | get_frame_pc (this_frame)); | |
2078 | else | |
2079 | return 0; | |
2080 | } | |
2081 | ||
2082 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2083 | { | |
2084 | NORMAL_FRAME, | |
2085 | i386_epilogue_frame_unwind_stop_reason, | |
2086 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2087 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2088 | NULL, |
2089 | i386_stack_tramp_frame_sniffer | |
2090 | }; | |
2091 | \f | |
6710bf39 SS |
2092 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2093 | ||
2094 | static void | |
2095 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2096 | struct agent_expr *ax, struct axs_value *value, | |
2097 | CORE_ADDR scope) | |
2098 | { | |
2099 | /* The following sequence assumes the traditional use of the base | |
2100 | register. */ | |
2101 | ax_reg (ax, I386_EBP_REGNUM); | |
2102 | ax_const_l (ax, 4); | |
2103 | ax_simple (ax, aop_add); | |
2104 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2105 | value->kind = axs_lvalue_memory; | |
2106 | } | |
2107 | \f | |
a3fcb948 | 2108 | |
acd5c798 MK |
2109 | /* Signal trampolines. */ |
2110 | ||
2111 | static struct i386_frame_cache * | |
10458914 | 2112 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2113 | { |
e17a4113 UW |
2114 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2115 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2116 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2117 | volatile struct gdb_exception ex; |
acd5c798 | 2118 | struct i386_frame_cache *cache; |
acd5c798 | 2119 | CORE_ADDR addr; |
63c0089f | 2120 | gdb_byte buf[4]; |
acd5c798 MK |
2121 | |
2122 | if (*this_cache) | |
2123 | return *this_cache; | |
2124 | ||
fd13a04a | 2125 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2126 | |
8fbca658 | 2127 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2128 | { |
8fbca658 PA |
2129 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2130 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2131 | |
8fbca658 PA |
2132 | addr = tdep->sigcontext_addr (this_frame); |
2133 | if (tdep->sc_reg_offset) | |
2134 | { | |
2135 | int i; | |
a3386186 | 2136 | |
8fbca658 PA |
2137 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2138 | ||
2139 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2140 | if (tdep->sc_reg_offset[i] != -1) | |
2141 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2142 | } | |
2143 | else | |
2144 | { | |
2145 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2146 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2147 | } | |
2148 | ||
2149 | cache->base_p = 1; | |
a3386186 | 2150 | } |
8fbca658 PA |
2151 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2152 | throw_exception (ex); | |
acd5c798 MK |
2153 | |
2154 | *this_cache = cache; | |
2155 | return cache; | |
2156 | } | |
2157 | ||
8fbca658 PA |
2158 | static enum unwind_stop_reason |
2159 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2160 | void **this_cache) | |
2161 | { | |
2162 | struct i386_frame_cache *cache = | |
2163 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2164 | ||
2165 | if (!cache->base_p) | |
2166 | return UNWIND_UNAVAILABLE; | |
2167 | ||
2168 | return UNWIND_NO_REASON; | |
2169 | } | |
2170 | ||
acd5c798 | 2171 | static void |
10458914 | 2172 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2173 | struct frame_id *this_id) |
2174 | { | |
2175 | struct i386_frame_cache *cache = | |
10458914 | 2176 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2177 | |
8fbca658 PA |
2178 | if (!cache->base_p) |
2179 | return; | |
2180 | ||
3e210248 | 2181 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2182 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
2183 | } |
2184 | ||
10458914 DJ |
2185 | static struct value * |
2186 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2187 | void **this_cache, int regnum) | |
acd5c798 MK |
2188 | { |
2189 | /* Make sure we've initialized the cache. */ | |
10458914 | 2190 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2191 | |
10458914 | 2192 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2193 | } |
c0d1d883 | 2194 | |
10458914 DJ |
2195 | static int |
2196 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2197 | struct frame_info *this_frame, | |
2198 | void **this_prologue_cache) | |
acd5c798 | 2199 | { |
10458914 | 2200 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2201 | |
911bc6ee MK |
2202 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2203 | handler. */ | |
2204 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2205 | return 0; |
1c3545ae | 2206 | |
911bc6ee MK |
2207 | if (tdep->sigtramp_p != NULL) |
2208 | { | |
10458914 DJ |
2209 | if (tdep->sigtramp_p (this_frame)) |
2210 | return 1; | |
911bc6ee MK |
2211 | } |
2212 | ||
2213 | if (tdep->sigtramp_start != 0) | |
2214 | { | |
10458914 | 2215 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2216 | |
2217 | gdb_assert (tdep->sigtramp_end != 0); | |
2218 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2219 | return 1; |
911bc6ee | 2220 | } |
acd5c798 | 2221 | |
10458914 | 2222 | return 0; |
acd5c798 | 2223 | } |
10458914 DJ |
2224 | |
2225 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2226 | { | |
2227 | SIGTRAMP_FRAME, | |
8fbca658 | 2228 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2229 | i386_sigtramp_frame_this_id, |
2230 | i386_sigtramp_frame_prev_register, | |
2231 | NULL, | |
2232 | i386_sigtramp_frame_sniffer | |
2233 | }; | |
acd5c798 MK |
2234 | \f |
2235 | ||
2236 | static CORE_ADDR | |
10458914 | 2237 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2238 | { |
10458914 | 2239 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2240 | |
2241 | return cache->base; | |
2242 | } | |
2243 | ||
2244 | static const struct frame_base i386_frame_base = | |
2245 | { | |
2246 | &i386_frame_unwind, | |
2247 | i386_frame_base_address, | |
2248 | i386_frame_base_address, | |
2249 | i386_frame_base_address | |
2250 | }; | |
2251 | ||
acd5c798 | 2252 | static struct frame_id |
10458914 | 2253 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2254 | { |
acd5c798 MK |
2255 | CORE_ADDR fp; |
2256 | ||
10458914 | 2257 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2258 | |
3e210248 | 2259 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2260 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2261 | } |
e04e5beb JM |
2262 | |
2263 | /* _Decimal128 function return values need 16-byte alignment on the | |
2264 | stack. */ | |
2265 | ||
2266 | static CORE_ADDR | |
2267 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2268 | { | |
2269 | return sp & -(CORE_ADDR)16; | |
2270 | } | |
fc338970 | 2271 | \f |
c906108c | 2272 | |
fc338970 MK |
2273 | /* Figure out where the longjmp will land. Slurp the args out of the |
2274 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2275 | structure from which we extract the address that we will land at. |
28bcfd30 | 2276 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2277 | success. */ |
c906108c | 2278 | |
8201327c | 2279 | static int |
60ade65d | 2280 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2281 | { |
436675d3 | 2282 | gdb_byte buf[4]; |
c906108c | 2283 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2284 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2285 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2286 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2287 | |
8201327c MK |
2288 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2289 | longjmp will land. */ | |
2290 | if (jb_pc_offset == -1) | |
c906108c SS |
2291 | return 0; |
2292 | ||
436675d3 | 2293 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2294 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2295 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2296 | return 0; |
2297 | ||
e17a4113 | 2298 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2299 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2300 | return 0; |
c906108c | 2301 | |
e17a4113 | 2302 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2303 | return 1; |
2304 | } | |
fc338970 | 2305 | \f |
c906108c | 2306 | |
7ccc1c74 JM |
2307 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2308 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2309 | unions containing such types must be 16-byte-aligned; other | |
2310 | arguments are 4-byte-aligned. */ | |
2311 | ||
2312 | static int | |
2313 | i386_16_byte_align_p (struct type *type) | |
2314 | { | |
2315 | type = check_typedef (type); | |
2316 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2317 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2318 | && TYPE_LENGTH (type) == 16) | |
2319 | return 1; | |
2320 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2321 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2322 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2323 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2324 | { | |
2325 | int i; | |
2326 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2327 | { | |
2328 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2329 | return 1; | |
2330 | } | |
2331 | } | |
2332 | return 0; | |
2333 | } | |
2334 | ||
a9b8d892 JK |
2335 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2336 | ||
2337 | static CORE_ADDR | |
2338 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2339 | struct value **args, int nargs, struct type *value_type, | |
2340 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2341 | struct regcache *regcache) | |
2342 | { | |
2343 | /* Use 0xcc breakpoint - 1 byte. */ | |
2344 | *bp_addr = sp - 1; | |
2345 | *real_pc = funaddr; | |
2346 | ||
2347 | /* Keep the stack aligned. */ | |
2348 | return sp - 16; | |
2349 | } | |
2350 | ||
3a1e71e3 | 2351 | static CORE_ADDR |
7d9b040b | 2352 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2353 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2354 | struct value **args, CORE_ADDR sp, int struct_return, | |
2355 | CORE_ADDR struct_addr) | |
22f8ba57 | 2356 | { |
e17a4113 | 2357 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2358 | gdb_byte buf[4]; |
acd5c798 | 2359 | int i; |
7ccc1c74 JM |
2360 | int write_pass; |
2361 | int args_space = 0; | |
acd5c798 | 2362 | |
7ccc1c74 JM |
2363 | /* Determine the total space required for arguments and struct |
2364 | return address in a first pass (allowing for 16-byte-aligned | |
2365 | arguments), then push arguments in a second pass. */ | |
2366 | ||
2367 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2368 | { |
7ccc1c74 | 2369 | int args_space_used = 0; |
7ccc1c74 JM |
2370 | |
2371 | if (struct_return) | |
2372 | { | |
2373 | if (write_pass) | |
2374 | { | |
2375 | /* Push value address. */ | |
e17a4113 | 2376 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2377 | write_memory (sp, buf, 4); |
2378 | args_space_used += 4; | |
2379 | } | |
2380 | else | |
2381 | args_space += 4; | |
2382 | } | |
2383 | ||
2384 | for (i = 0; i < nargs; i++) | |
2385 | { | |
2386 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2387 | |
7ccc1c74 JM |
2388 | if (write_pass) |
2389 | { | |
2390 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2391 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2392 | |
7ccc1c74 JM |
2393 | write_memory (sp + args_space_used, |
2394 | value_contents_all (args[i]), len); | |
2395 | /* The System V ABI says that: | |
acd5c798 | 2396 | |
7ccc1c74 JM |
2397 | "An argument's size is increased, if necessary, to make it a |
2398 | multiple of [32-bit] words. This may require tail padding, | |
2399 | depending on the size of the argument." | |
22f8ba57 | 2400 | |
7ccc1c74 JM |
2401 | This makes sure the stack stays word-aligned. */ |
2402 | args_space_used += align_up (len, 4); | |
2403 | } | |
2404 | else | |
2405 | { | |
2406 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2407 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2408 | args_space += align_up (len, 4); |
2409 | } | |
2410 | } | |
2411 | ||
2412 | if (!write_pass) | |
2413 | { | |
7ccc1c74 | 2414 | sp -= args_space; |
284c5a60 MK |
2415 | |
2416 | /* The original System V ABI only requires word alignment, | |
2417 | but modern incarnations need 16-byte alignment in order | |
2418 | to support SSE. Since wasting a few bytes here isn't | |
2419 | harmful we unconditionally enforce 16-byte alignment. */ | |
2420 | sp &= ~0xf; | |
7ccc1c74 | 2421 | } |
22f8ba57 MK |
2422 | } |
2423 | ||
acd5c798 MK |
2424 | /* Store return address. */ |
2425 | sp -= 4; | |
e17a4113 | 2426 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2427 | write_memory (sp, buf, 4); |
2428 | ||
2429 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2430 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2431 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2432 | ||
2433 | /* ...and fake a frame pointer. */ | |
2434 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2435 | ||
3e210248 AC |
2436 | /* MarkK wrote: This "+ 8" is all over the place: |
2437 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2438 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2439 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2440 | definition of the stack address of a frame. Otherwise frame id |
2441 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2442 | stack address *before* the function call as a frame's CFA. On |
2443 | the i386, when %ebp is used as a frame pointer, the offset | |
2444 | between the contents %ebp and the CFA as defined by GCC. */ | |
2445 | return sp + 8; | |
22f8ba57 MK |
2446 | } |
2447 | ||
1a309862 MK |
2448 | /* These registers are used for returning integers (and on some |
2449 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2450 | size and alignment match an integer type). */ |
acd5c798 MK |
2451 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2452 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2453 | |
c5e656c1 MK |
2454 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2455 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2456 | |
3a1e71e3 | 2457 | static void |
c5e656c1 | 2458 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2459 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2460 | { |
c5e656c1 | 2461 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2462 | int len = TYPE_LENGTH (type); |
63c0089f | 2463 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2464 | |
1e8d0a7b | 2465 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2466 | { |
5716833c | 2467 | if (tdep->st0_regnum < 0) |
1a309862 | 2468 | { |
8a3fe4f8 | 2469 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2470 | memset (valbuf, 0, len); |
ef9dff19 | 2471 | return; |
1a309862 MK |
2472 | } |
2473 | ||
c6ba6f0d MK |
2474 | /* Floating-point return values can be found in %st(0). Convert |
2475 | its contents to the desired type. This is probably not | |
2476 | exactly how it would happen on the target itself, but it is | |
2477 | the best we can do. */ | |
acd5c798 | 2478 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2479 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2480 | } |
2481 | else | |
c5aa993b | 2482 | { |
875f8d0e UW |
2483 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2484 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2485 | |
2486 | if (len <= low_size) | |
00f8375e | 2487 | { |
0818c12a | 2488 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2489 | memcpy (valbuf, buf, len); |
2490 | } | |
d4f3574e SS |
2491 | else if (len <= (low_size + high_size)) |
2492 | { | |
0818c12a | 2493 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2494 | memcpy (valbuf, buf, low_size); |
0818c12a | 2495 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2496 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2497 | } |
2498 | else | |
8e65ff28 | 2499 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2500 | _("Cannot extract return value of %d bytes long."), |
2501 | len); | |
c906108c SS |
2502 | } |
2503 | } | |
2504 | ||
c5e656c1 MK |
2505 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2506 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2507 | |
3a1e71e3 | 2508 | static void |
c5e656c1 | 2509 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2510 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2511 | { |
c5e656c1 | 2512 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2513 | int len = TYPE_LENGTH (type); |
2514 | ||
1e8d0a7b | 2515 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2516 | { |
3d7f4f49 | 2517 | ULONGEST fstat; |
63c0089f | 2518 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2519 | |
5716833c | 2520 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2521 | { |
8a3fe4f8 | 2522 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2523 | return; |
2524 | } | |
2525 | ||
635b0cc1 MK |
2526 | /* Returning floating-point values is a bit tricky. Apart from |
2527 | storing the return value in %st(0), we have to simulate the | |
2528 | state of the FPU at function return point. */ | |
2529 | ||
c6ba6f0d MK |
2530 | /* Convert the value found in VALBUF to the extended |
2531 | floating-point format used by the FPU. This is probably | |
2532 | not exactly how it would happen on the target itself, but | |
2533 | it is the best we can do. */ | |
27067745 | 2534 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2535 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2536 | |
635b0cc1 MK |
2537 | /* Set the top of the floating-point register stack to 7. The |
2538 | actual value doesn't really matter, but 7 is what a normal | |
2539 | function return would end up with if the program started out | |
2540 | with a freshly initialized FPU. */ | |
20a6ec49 | 2541 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2542 | fstat |= (7 << 11); |
20a6ec49 | 2543 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2544 | |
635b0cc1 MK |
2545 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2546 | the floating-point register stack to 7, the appropriate value | |
2547 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2548 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2549 | } |
2550 | else | |
2551 | { | |
875f8d0e UW |
2552 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2553 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2554 | |
2555 | if (len <= low_size) | |
3d7f4f49 | 2556 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2557 | else if (len <= (low_size + high_size)) |
2558 | { | |
3d7f4f49 MK |
2559 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2560 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2561 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2562 | } |
2563 | else | |
8e65ff28 | 2564 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2565 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2566 | } |
2567 | } | |
fc338970 | 2568 | \f |
ef9dff19 | 2569 | |
8201327c MK |
2570 | /* This is the variable that is set with "set struct-convention", and |
2571 | its legitimate values. */ | |
2572 | static const char default_struct_convention[] = "default"; | |
2573 | static const char pcc_struct_convention[] = "pcc"; | |
2574 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2575 | static const char *const valid_conventions[] = |
8201327c MK |
2576 | { |
2577 | default_struct_convention, | |
2578 | pcc_struct_convention, | |
2579 | reg_struct_convention, | |
2580 | NULL | |
2581 | }; | |
2582 | static const char *struct_convention = default_struct_convention; | |
2583 | ||
0e4377e1 JB |
2584 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2585 | a union type, or an array type, should be returned in registers | |
2586 | for architecture GDBARCH. */ | |
c5e656c1 | 2587 | |
8201327c | 2588 | static int |
c5e656c1 | 2589 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2590 | { |
c5e656c1 MK |
2591 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2592 | enum type_code code = TYPE_CODE (type); | |
2593 | int len = TYPE_LENGTH (type); | |
8201327c | 2594 | |
0e4377e1 JB |
2595 | gdb_assert (code == TYPE_CODE_STRUCT |
2596 | || code == TYPE_CODE_UNION | |
2597 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2598 | |
2599 | if (struct_convention == pcc_struct_convention | |
2600 | || (struct_convention == default_struct_convention | |
2601 | && tdep->struct_return == pcc_struct_return)) | |
2602 | return 0; | |
2603 | ||
9edde48e MK |
2604 | /* Structures consisting of a single `float', `double' or 'long |
2605 | double' member are returned in %st(0). */ | |
2606 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2607 | { | |
2608 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2609 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2610 | return (len == 4 || len == 8 || len == 12); | |
2611 | } | |
2612 | ||
c5e656c1 MK |
2613 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2614 | } | |
2615 | ||
2616 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2617 | should be returned. If it is supposed to be returned in registers, | |
2618 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2619 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2620 | from WRITEBUF into REGCACHE. */ | |
2621 | ||
2622 | static enum return_value_convention | |
6a3a010b | 2623 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2624 | struct type *type, struct regcache *regcache, |
2625 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2626 | { |
2627 | enum type_code code = TYPE_CODE (type); | |
2628 | ||
5daa78cc TJB |
2629 | if (((code == TYPE_CODE_STRUCT |
2630 | || code == TYPE_CODE_UNION | |
2631 | || code == TYPE_CODE_ARRAY) | |
2632 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2633 | /* Complex double and long double uses the struct return covention. */ |
2634 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2635 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2636 | /* 128-bit decimal float uses the struct return convention. */ |
2637 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2638 | { |
2639 | /* The System V ABI says that: | |
2640 | ||
2641 | "A function that returns a structure or union also sets %eax | |
2642 | to the value of the original address of the caller's area | |
2643 | before it returns. Thus when the caller receives control | |
2644 | again, the address of the returned object resides in register | |
2645 | %eax and can be used to access the object." | |
2646 | ||
2647 | So the ABI guarantees that we can always find the return | |
2648 | value just after the function has returned. */ | |
2649 | ||
0e4377e1 JB |
2650 | /* Note that the ABI doesn't mention functions returning arrays, |
2651 | which is something possible in certain languages such as Ada. | |
2652 | In this case, the value is returned as if it was wrapped in | |
2653 | a record, so the convention applied to records also applies | |
2654 | to arrays. */ | |
2655 | ||
31db7b6c MK |
2656 | if (readbuf) |
2657 | { | |
2658 | ULONGEST addr; | |
2659 | ||
2660 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2661 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2662 | } | |
2663 | ||
2664 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2665 | } | |
c5e656c1 MK |
2666 | |
2667 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2668 | `float', `double' or 'long double' member. These structures are |
2669 | returned in %st(0). For these structures, we call ourselves | |
2670 | recursively, changing TYPE into the type of the first member of | |
2671 | the structure. Since that should work for all structures that | |
2672 | have only one member, we don't bother to check the member's type | |
2673 | here. */ | |
c5e656c1 MK |
2674 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2675 | { | |
2676 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 2677 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 2678 | readbuf, writebuf); |
c5e656c1 MK |
2679 | } |
2680 | ||
2681 | if (readbuf) | |
2682 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2683 | if (writebuf) | |
2684 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2685 | |
c5e656c1 | 2686 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2687 | } |
2688 | \f | |
2689 | ||
27067745 UW |
2690 | struct type * |
2691 | i387_ext_type (struct gdbarch *gdbarch) | |
2692 | { | |
2693 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2694 | ||
2695 | if (!tdep->i387_ext_type) | |
90884b2b L |
2696 | { |
2697 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2698 | gdb_assert (tdep->i387_ext_type != NULL); | |
2699 | } | |
27067745 UW |
2700 | |
2701 | return tdep->i387_ext_type; | |
2702 | } | |
2703 | ||
c131fcee L |
2704 | /* Construct vector type for pseudo YMM registers. We can't use |
2705 | tdesc_find_type since YMM isn't described in target description. */ | |
2706 | ||
2707 | static struct type * | |
2708 | i386_ymm_type (struct gdbarch *gdbarch) | |
2709 | { | |
2710 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2711 | ||
2712 | if (!tdep->i386_ymm_type) | |
2713 | { | |
2714 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2715 | ||
2716 | /* The type we're building is this: */ | |
2717 | #if 0 | |
2718 | union __gdb_builtin_type_vec256i | |
2719 | { | |
2720 | int128_t uint128[2]; | |
2721 | int64_t v2_int64[4]; | |
2722 | int32_t v4_int32[8]; | |
2723 | int16_t v8_int16[16]; | |
2724 | int8_t v16_int8[32]; | |
2725 | double v2_double[4]; | |
2726 | float v4_float[8]; | |
2727 | }; | |
2728 | #endif | |
2729 | ||
2730 | struct type *t; | |
2731 | ||
2732 | t = arch_composite_type (gdbarch, | |
2733 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2734 | append_composite_type_field (t, "v8_float", | |
2735 | init_vector_type (bt->builtin_float, 8)); | |
2736 | append_composite_type_field (t, "v4_double", | |
2737 | init_vector_type (bt->builtin_double, 4)); | |
2738 | append_composite_type_field (t, "v32_int8", | |
2739 | init_vector_type (bt->builtin_int8, 32)); | |
2740 | append_composite_type_field (t, "v16_int16", | |
2741 | init_vector_type (bt->builtin_int16, 16)); | |
2742 | append_composite_type_field (t, "v8_int32", | |
2743 | init_vector_type (bt->builtin_int32, 8)); | |
2744 | append_composite_type_field (t, "v4_int64", | |
2745 | init_vector_type (bt->builtin_int64, 4)); | |
2746 | append_composite_type_field (t, "v2_int128", | |
2747 | init_vector_type (bt->builtin_int128, 2)); | |
2748 | ||
2749 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 2750 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
2751 | tdep->i386_ymm_type = t; |
2752 | } | |
2753 | ||
2754 | return tdep->i386_ymm_type; | |
2755 | } | |
2756 | ||
794ac428 | 2757 | /* Construct vector type for MMX registers. */ |
90884b2b | 2758 | static struct type * |
794ac428 UW |
2759 | i386_mmx_type (struct gdbarch *gdbarch) |
2760 | { | |
2761 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2762 | ||
2763 | if (!tdep->i386_mmx_type) | |
2764 | { | |
df4df182 UW |
2765 | const struct builtin_type *bt = builtin_type (gdbarch); |
2766 | ||
794ac428 UW |
2767 | /* The type we're building is this: */ |
2768 | #if 0 | |
2769 | union __gdb_builtin_type_vec64i | |
2770 | { | |
2771 | int64_t uint64; | |
2772 | int32_t v2_int32[2]; | |
2773 | int16_t v4_int16[4]; | |
2774 | int8_t v8_int8[8]; | |
2775 | }; | |
2776 | #endif | |
2777 | ||
2778 | struct type *t; | |
2779 | ||
e9bb382b UW |
2780 | t = arch_composite_type (gdbarch, |
2781 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2782 | |
2783 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2784 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2785 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2786 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2787 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2788 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2789 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2790 | |
876cecd0 | 2791 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2792 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2793 | tdep->i386_mmx_type = t; | |
2794 | } | |
2795 | ||
2796 | return tdep->i386_mmx_type; | |
2797 | } | |
2798 | ||
d7a0d72c | 2799 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 2800 | register REGNUM. */ |
d7a0d72c | 2801 | |
fff4548b | 2802 | struct type * |
90884b2b | 2803 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2804 | { |
1ba53b71 L |
2805 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2806 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2807 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2808 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2809 | else |
2810 | { | |
2811 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2812 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2813 | return bt->builtin_int8; | |
2814 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2815 | return bt->builtin_int16; | |
2816 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2817 | return bt->builtin_int32; | |
2818 | } | |
2819 | ||
2820 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2821 | } |
2822 | ||
28fc6740 | 2823 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2824 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2825 | |
2826 | static int | |
c86c27af | 2827 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2828 | { |
5716833c MK |
2829 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2830 | int mmxreg, fpreg; | |
28fc6740 AC |
2831 | ULONGEST fstat; |
2832 | int tos; | |
c86c27af | 2833 | |
5716833c | 2834 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2835 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2836 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2837 | fpreg = (mmxreg + tos) % 8; |
2838 | ||
20a6ec49 | 2839 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2840 | } |
2841 | ||
3543a589 TT |
2842 | /* A helper function for us by i386_pseudo_register_read_value and |
2843 | amd64_pseudo_register_read_value. It does all the work but reads | |
2844 | the data into an already-allocated value. */ | |
2845 | ||
2846 | void | |
2847 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
2848 | struct regcache *regcache, | |
2849 | int regnum, | |
2850 | struct value *result_value) | |
28fc6740 | 2851 | { |
1ba53b71 | 2852 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 2853 | enum register_status status; |
3543a589 | 2854 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 2855 | |
5716833c | 2856 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2857 | { |
c86c27af MK |
2858 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2859 | ||
28fc6740 | 2860 | /* Extract (always little endian). */ |
05d1431c PA |
2861 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
2862 | if (status != REG_VALID) | |
3543a589 TT |
2863 | mark_value_bytes_unavailable (result_value, 0, |
2864 | TYPE_LENGTH (value_type (result_value))); | |
2865 | else | |
2866 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2867 | } |
2868 | else | |
1ba53b71 L |
2869 | { |
2870 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2871 | ||
c131fcee L |
2872 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2873 | { | |
2874 | regnum -= tdep->ymm0_regnum; | |
2875 | ||
1777feb0 | 2876 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
2877 | status = regcache_raw_read (regcache, |
2878 | I387_XMM0_REGNUM (tdep) + regnum, | |
2879 | raw_buf); | |
2880 | if (status != REG_VALID) | |
3543a589 TT |
2881 | mark_value_bytes_unavailable (result_value, 0, 16); |
2882 | else | |
2883 | memcpy (buf, raw_buf, 16); | |
c131fcee | 2884 | /* Read upper 128bits. */ |
05d1431c PA |
2885 | status = regcache_raw_read (regcache, |
2886 | tdep->ymm0h_regnum + regnum, | |
2887 | raw_buf); | |
2888 | if (status != REG_VALID) | |
3543a589 TT |
2889 | mark_value_bytes_unavailable (result_value, 16, 32); |
2890 | else | |
2891 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee L |
2892 | } |
2893 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2894 | { |
2895 | int gpnum = regnum - tdep->ax_regnum; | |
2896 | ||
2897 | /* Extract (always little endian). */ | |
05d1431c PA |
2898 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
2899 | if (status != REG_VALID) | |
3543a589 TT |
2900 | mark_value_bytes_unavailable (result_value, 0, |
2901 | TYPE_LENGTH (value_type (result_value))); | |
2902 | else | |
2903 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
2904 | } |
2905 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2906 | { | |
2907 | /* Check byte pseudo registers last since this function will | |
2908 | be called from amd64_pseudo_register_read, which handles | |
2909 | byte pseudo registers differently. */ | |
2910 | int gpnum = regnum - tdep->al_regnum; | |
2911 | ||
2912 | /* Extract (always little endian). We read both lower and | |
2913 | upper registers. */ | |
05d1431c PA |
2914 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
2915 | if (status != REG_VALID) | |
3543a589 TT |
2916 | mark_value_bytes_unavailable (result_value, 0, |
2917 | TYPE_LENGTH (value_type (result_value))); | |
2918 | else if (gpnum >= 4) | |
1ba53b71 L |
2919 | memcpy (buf, raw_buf + 1, 1); |
2920 | else | |
2921 | memcpy (buf, raw_buf, 1); | |
2922 | } | |
2923 | else | |
2924 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2925 | } | |
3543a589 TT |
2926 | } |
2927 | ||
2928 | static struct value * | |
2929 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
2930 | struct regcache *regcache, | |
2931 | int regnum) | |
2932 | { | |
2933 | struct value *result; | |
2934 | ||
2935 | result = allocate_value (register_type (gdbarch, regnum)); | |
2936 | VALUE_LVAL (result) = lval_register; | |
2937 | VALUE_REGNUM (result) = regnum; | |
2938 | ||
2939 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 2940 | |
3543a589 | 2941 | return result; |
28fc6740 AC |
2942 | } |
2943 | ||
1ba53b71 | 2944 | void |
28fc6740 | 2945 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2946 | int regnum, const gdb_byte *buf) |
28fc6740 | 2947 | { |
1ba53b71 L |
2948 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2949 | ||
5716833c | 2950 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2951 | { |
c86c27af MK |
2952 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2953 | ||
28fc6740 | 2954 | /* Read ... */ |
1ba53b71 | 2955 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2956 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2957 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2958 | /* ... Write. */ |
1ba53b71 | 2959 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2960 | } |
2961 | else | |
1ba53b71 L |
2962 | { |
2963 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2964 | ||
c131fcee L |
2965 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2966 | { | |
2967 | regnum -= tdep->ymm0_regnum; | |
2968 | ||
2969 | /* ... Write lower 128bits. */ | |
2970 | regcache_raw_write (regcache, | |
2971 | I387_XMM0_REGNUM (tdep) + regnum, | |
2972 | buf); | |
2973 | /* ... Write upper 128bits. */ | |
2974 | regcache_raw_write (regcache, | |
2975 | tdep->ymm0h_regnum + regnum, | |
2976 | buf + 16); | |
2977 | } | |
2978 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2979 | { |
2980 | int gpnum = regnum - tdep->ax_regnum; | |
2981 | ||
2982 | /* Read ... */ | |
2983 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2984 | /* ... Modify ... (always little endian). */ | |
2985 | memcpy (raw_buf, buf, 2); | |
2986 | /* ... Write. */ | |
2987 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2988 | } | |
2989 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2990 | { | |
2991 | /* Check byte pseudo registers last since this function will | |
2992 | be called from amd64_pseudo_register_read, which handles | |
2993 | byte pseudo registers differently. */ | |
2994 | int gpnum = regnum - tdep->al_regnum; | |
2995 | ||
2996 | /* Read ... We read both lower and upper registers. */ | |
2997 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2998 | /* ... Modify ... (always little endian). */ | |
2999 | if (gpnum >= 4) | |
3000 | memcpy (raw_buf + 1, buf, 1); | |
3001 | else | |
3002 | memcpy (raw_buf, buf, 1); | |
3003 | /* ... Write. */ | |
3004 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3005 | } | |
3006 | else | |
3007 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3008 | } | |
28fc6740 | 3009 | } |
ff2e87ac AC |
3010 | \f |
3011 | ||
ff2e87ac AC |
3012 | /* Return the register number of the register allocated by GCC after |
3013 | REGNUM, or -1 if there is no such register. */ | |
3014 | ||
3015 | static int | |
3016 | i386_next_regnum (int regnum) | |
3017 | { | |
3018 | /* GCC allocates the registers in the order: | |
3019 | ||
3020 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3021 | ||
3022 | Since storing a variable in %esp doesn't make any sense we return | |
3023 | -1 for %ebp and for %esp itself. */ | |
3024 | static int next_regnum[] = | |
3025 | { | |
3026 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3027 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3028 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3029 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3030 | -1, -1, /* Slots for %esp and %ebp. */ | |
3031 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3032 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3033 | }; | |
3034 | ||
de5b9bb9 | 3035 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3036 | return next_regnum[regnum]; |
28fc6740 | 3037 | |
ff2e87ac AC |
3038 | return -1; |
3039 | } | |
3040 | ||
3041 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3042 | needs any special handling. */ | |
d7a0d72c | 3043 | |
3a1e71e3 | 3044 | static int |
1777feb0 MS |
3045 | i386_convert_register_p (struct gdbarch *gdbarch, |
3046 | int regnum, struct type *type) | |
d7a0d72c | 3047 | { |
de5b9bb9 MK |
3048 | int len = TYPE_LENGTH (type); |
3049 | ||
ff2e87ac AC |
3050 | /* Values may be spread across multiple registers. Most debugging |
3051 | formats aren't expressive enough to specify the locations, so | |
3052 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3053 | have a length that is a multiple of the word size, since GCC |
3054 | doesn't seem to put any other types into registers. */ | |
3055 | if (len > 4 && len % 4 == 0) | |
3056 | { | |
3057 | int last_regnum = regnum; | |
3058 | ||
3059 | while (len > 4) | |
3060 | { | |
3061 | last_regnum = i386_next_regnum (last_regnum); | |
3062 | len -= 4; | |
3063 | } | |
3064 | ||
3065 | if (last_regnum != -1) | |
3066 | return 1; | |
3067 | } | |
ff2e87ac | 3068 | |
0abe36f5 | 3069 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3070 | } |
3071 | ||
ff2e87ac AC |
3072 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3073 | return its contents in TO. */ | |
ac27f131 | 3074 | |
8dccd430 | 3075 | static int |
ff2e87ac | 3076 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3077 | struct type *type, gdb_byte *to, |
3078 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3079 | { |
20a6ec49 | 3080 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3081 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3082 | |
20a6ec49 | 3083 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3084 | return i387_register_to_value (frame, regnum, type, to, |
3085 | optimizedp, unavailablep); | |
ff2e87ac | 3086 | |
fd35795f | 3087 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3088 | |
3089 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3090 | |
de5b9bb9 MK |
3091 | while (len > 0) |
3092 | { | |
3093 | gdb_assert (regnum != -1); | |
20a6ec49 | 3094 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3095 | |
8dccd430 PA |
3096 | if (!get_frame_register_bytes (frame, regnum, 0, |
3097 | register_size (gdbarch, regnum), | |
3098 | to, optimizedp, unavailablep)) | |
3099 | return 0; | |
3100 | ||
de5b9bb9 MK |
3101 | regnum = i386_next_regnum (regnum); |
3102 | len -= 4; | |
42835c2b | 3103 | to += 4; |
de5b9bb9 | 3104 | } |
8dccd430 PA |
3105 | |
3106 | *optimizedp = *unavailablep = 0; | |
3107 | return 1; | |
ac27f131 MK |
3108 | } |
3109 | ||
ff2e87ac AC |
3110 | /* Write the contents FROM of a value of type TYPE into register |
3111 | REGNUM in frame FRAME. */ | |
ac27f131 | 3112 | |
3a1e71e3 | 3113 | static void |
ff2e87ac | 3114 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3115 | struct type *type, const gdb_byte *from) |
ac27f131 | 3116 | { |
de5b9bb9 | 3117 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3118 | |
20a6ec49 | 3119 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3120 | { |
d532c08f MK |
3121 | i387_value_to_register (frame, regnum, type, from); |
3122 | return; | |
3123 | } | |
3d261580 | 3124 | |
fd35795f | 3125 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3126 | |
3127 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3128 | |
de5b9bb9 MK |
3129 | while (len > 0) |
3130 | { | |
3131 | gdb_assert (regnum != -1); | |
875f8d0e | 3132 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3133 | |
42835c2b | 3134 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3135 | regnum = i386_next_regnum (regnum); |
3136 | len -= 4; | |
42835c2b | 3137 | from += 4; |
de5b9bb9 | 3138 | } |
ac27f131 | 3139 | } |
ff2e87ac | 3140 | \f |
7fdafb5a MK |
3141 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3142 | in the general-purpose register set REGSET to register cache | |
3143 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3144 | |
20187ed5 | 3145 | void |
473f17b0 MK |
3146 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3147 | int regnum, const void *gregs, size_t len) | |
3148 | { | |
9ea75c57 | 3149 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 3150 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3151 | int i; |
3152 | ||
3153 | gdb_assert (len == tdep->sizeof_gregset); | |
3154 | ||
3155 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3156 | { | |
3157 | if ((regnum == i || regnum == -1) | |
3158 | && tdep->gregset_reg_offset[i] != -1) | |
3159 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3160 | } | |
3161 | } | |
3162 | ||
7fdafb5a MK |
3163 | /* Collect register REGNUM from the register cache REGCACHE and store |
3164 | it in the buffer specified by GREGS and LEN as described by the | |
3165 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3166 | all registers in REGSET. */ | |
3167 | ||
3168 | void | |
3169 | i386_collect_gregset (const struct regset *regset, | |
3170 | const struct regcache *regcache, | |
3171 | int regnum, void *gregs, size_t len) | |
3172 | { | |
3173 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 3174 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3175 | int i; |
3176 | ||
3177 | gdb_assert (len == tdep->sizeof_gregset); | |
3178 | ||
3179 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3180 | { | |
3181 | if ((regnum == i || regnum == -1) | |
3182 | && tdep->gregset_reg_offset[i] != -1) | |
3183 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3184 | } | |
3185 | } | |
3186 | ||
3187 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3188 | in the floating-point register set REGSET to register cache | |
3189 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3190 | |
3191 | static void | |
3192 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3193 | int regnum, const void *fpregs, size_t len) | |
3194 | { | |
9ea75c57 | 3195 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 3196 | |
66a72d25 MK |
3197 | if (len == I387_SIZEOF_FXSAVE) |
3198 | { | |
3199 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3200 | return; | |
3201 | } | |
3202 | ||
473f17b0 MK |
3203 | gdb_assert (len == tdep->sizeof_fpregset); |
3204 | i387_supply_fsave (regcache, regnum, fpregs); | |
3205 | } | |
8446b36a | 3206 | |
2f305df1 MK |
3207 | /* Collect register REGNUM from the register cache REGCACHE and store |
3208 | it in the buffer specified by FPREGS and LEN as described by the | |
3209 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3210 | all registers in REGSET. */ | |
7fdafb5a MK |
3211 | |
3212 | static void | |
3213 | i386_collect_fpregset (const struct regset *regset, | |
3214 | const struct regcache *regcache, | |
3215 | int regnum, void *fpregs, size_t len) | |
3216 | { | |
3217 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
3218 | ||
3219 | if (len == I387_SIZEOF_FXSAVE) | |
3220 | { | |
3221 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3222 | return; | |
3223 | } | |
3224 | ||
3225 | gdb_assert (len == tdep->sizeof_fpregset); | |
3226 | i387_collect_fsave (regcache, regnum, fpregs); | |
3227 | } | |
3228 | ||
c131fcee L |
3229 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3230 | ||
3231 | static void | |
3232 | i386_supply_xstateregset (const struct regset *regset, | |
3233 | struct regcache *regcache, int regnum, | |
3234 | const void *xstateregs, size_t len) | |
3235 | { | |
c131fcee L |
3236 | i387_supply_xsave (regcache, regnum, xstateregs); |
3237 | } | |
3238 | ||
3239 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3240 | ||
3241 | static void | |
3242 | i386_collect_xstateregset (const struct regset *regset, | |
3243 | const struct regcache *regcache, | |
3244 | int regnum, void *xstateregs, size_t len) | |
3245 | { | |
c131fcee L |
3246 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3247 | } | |
3248 | ||
8446b36a MK |
3249 | /* Return the appropriate register set for the core section identified |
3250 | by SECT_NAME and SECT_SIZE. */ | |
3251 | ||
3252 | const struct regset * | |
3253 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3254 | const char *sect_name, size_t sect_size) | |
3255 | { | |
3256 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3257 | ||
3258 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
3259 | { | |
3260 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
3261 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
3262 | i386_collect_gregset); | |
8446b36a MK |
3263 | return tdep->gregset; |
3264 | } | |
3265 | ||
66a72d25 MK |
3266 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3267 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3268 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
3269 | { |
3270 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
3271 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
3272 | i386_collect_fpregset); | |
8446b36a MK |
3273 | return tdep->fpregset; |
3274 | } | |
3275 | ||
c131fcee L |
3276 | if (strcmp (sect_name, ".reg-xstate") == 0) |
3277 | { | |
3278 | if (tdep->xstateregset == NULL) | |
3279 | tdep->xstateregset = regset_alloc (gdbarch, | |
3280 | i386_supply_xstateregset, | |
3281 | i386_collect_xstateregset); | |
3282 | ||
3283 | return tdep->xstateregset; | |
3284 | } | |
3285 | ||
8446b36a MK |
3286 | return NULL; |
3287 | } | |
473f17b0 | 3288 | \f |
fc338970 | 3289 | |
fc338970 | 3290 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3291 | |
3292 | CORE_ADDR | |
e17a4113 UW |
3293 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3294 | CORE_ADDR pc, char *name) | |
c906108c | 3295 | { |
e17a4113 UW |
3296 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3297 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3298 | ||
3299 | /* jmp *(dest) */ | |
3300 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3301 | { |
e17a4113 UW |
3302 | unsigned long indirect = |
3303 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3304 | struct minimal_symbol *indsym = |
fc338970 | 3305 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
0d5cff50 | 3306 | const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3307 | |
c5aa993b | 3308 | if (symname) |
c906108c | 3309 | { |
c5aa993b JM |
3310 | if (strncmp (symname, "__imp_", 6) == 0 |
3311 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3312 | return name ? 1 : |
3313 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3314 | } |
3315 | } | |
fc338970 | 3316 | return 0; /* Not a trampoline. */ |
c906108c | 3317 | } |
fc338970 MK |
3318 | \f |
3319 | ||
10458914 DJ |
3320 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3321 | routine. */ | |
8201327c | 3322 | |
4bd207ef | 3323 | int |
10458914 | 3324 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3325 | { |
10458914 | 3326 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3327 | const char *name; |
911bc6ee MK |
3328 | |
3329 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3330 | return (name && strcmp ("_sigtramp", name) == 0); |
3331 | } | |
3332 | \f | |
3333 | ||
fc338970 MK |
3334 | /* We have two flavours of disassembly. The machinery on this page |
3335 | deals with switching between those. */ | |
c906108c SS |
3336 | |
3337 | static int | |
a89aa300 | 3338 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3339 | { |
5e3397bb MK |
3340 | gdb_assert (disassembly_flavor == att_flavor |
3341 | || disassembly_flavor == intel_flavor); | |
3342 | ||
3343 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3344 | constified, cast to prevent a compiler warning. */ | |
3345 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3346 | |
3347 | return print_insn_i386 (pc, info); | |
7a292a7a | 3348 | } |
fc338970 | 3349 | \f |
3ce1502b | 3350 | |
8201327c MK |
3351 | /* There are a few i386 architecture variants that differ only |
3352 | slightly from the generic i386 target. For now, we don't give them | |
3353 | their own source file, but include them here. As a consequence, | |
3354 | they'll always be included. */ | |
3ce1502b | 3355 | |
8201327c | 3356 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3357 | |
10458914 DJ |
3358 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3359 | routine. */ | |
911bc6ee | 3360 | |
8201327c | 3361 | static int |
10458914 | 3362 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3363 | { |
10458914 | 3364 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3365 | const char *name; |
911bc6ee | 3366 | |
acd5c798 MK |
3367 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
3368 | currently unknown. */ | |
911bc6ee | 3369 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
3370 | return (name && (strcmp ("_sigreturn", name) == 0 |
3371 | || strcmp ("_sigacthandler", name) == 0 | |
3372 | || strcmp ("sigvechandler", name) == 0)); | |
3373 | } | |
d2a7c97a | 3374 | |
10458914 DJ |
3375 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3376 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3377 | |
3a1e71e3 | 3378 | static CORE_ADDR |
10458914 | 3379 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3380 | { |
e17a4113 UW |
3381 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3382 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3383 | gdb_byte buf[4]; |
acd5c798 | 3384 | CORE_ADDR sp; |
3ce1502b | 3385 | |
10458914 | 3386 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3387 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3388 | |
e17a4113 | 3389 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 3390 | } |
55aa24fb SDJ |
3391 | |
3392 | \f | |
3393 | ||
3394 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
3395 | gdbarch.h. */ | |
3396 | ||
3397 | int | |
3398 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
3399 | { | |
3400 | return (*s == '$' /* Literal number. */ | |
3401 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
3402 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
3403 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
3404 | } | |
3405 | ||
3406 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in | |
3407 | gdbarch.h. */ | |
3408 | ||
3409 | int | |
3410 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
3411 | struct stap_parse_info *p) | |
3412 | { | |
55aa24fb SDJ |
3413 | /* In order to parse special tokens, we use a state-machine that go |
3414 | through every known token and try to get a match. */ | |
3415 | enum | |
3416 | { | |
3417 | TRIPLET, | |
3418 | THREE_ARG_DISPLACEMENT, | |
3419 | DONE | |
3420 | } current_state; | |
3421 | ||
3422 | current_state = TRIPLET; | |
3423 | ||
3424 | /* The special tokens to be parsed here are: | |
3425 | ||
3426 | - `register base + (register index * size) + offset', as represented | |
3427 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
3428 | ||
3429 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
3430 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
3431 | ||
3432 | while (current_state != DONE) | |
3433 | { | |
3434 | const char *s = p->arg; | |
3435 | ||
3436 | switch (current_state) | |
3437 | { | |
3438 | case TRIPLET: | |
3439 | { | |
3440 | if (isdigit (*s) || *s == '-' || *s == '+') | |
3441 | { | |
3442 | int got_minus[3]; | |
3443 | int i; | |
3444 | long displacements[3]; | |
3445 | const char *start; | |
3446 | char *regname; | |
3447 | int len; | |
3448 | struct stoken str; | |
3449 | ||
3450 | got_minus[0] = 0; | |
3451 | if (*s == '+') | |
3452 | ++s; | |
3453 | else if (*s == '-') | |
3454 | { | |
3455 | ++s; | |
3456 | got_minus[0] = 1; | |
3457 | } | |
3458 | ||
3459 | displacements[0] = strtol (s, (char **) &s, 10); | |
3460 | ||
3461 | if (*s != '+' && *s != '-') | |
3462 | { | |
3463 | /* We are not dealing with a triplet. */ | |
3464 | break; | |
3465 | } | |
3466 | ||
3467 | got_minus[1] = 0; | |
3468 | if (*s == '+') | |
3469 | ++s; | |
3470 | else | |
3471 | { | |
3472 | ++s; | |
3473 | got_minus[1] = 1; | |
3474 | } | |
3475 | ||
3476 | displacements[1] = strtol (s, (char **) &s, 10); | |
3477 | ||
3478 | if (*s != '+' && *s != '-') | |
3479 | { | |
3480 | /* We are not dealing with a triplet. */ | |
3481 | break; | |
3482 | } | |
3483 | ||
3484 | got_minus[2] = 0; | |
3485 | if (*s == '+') | |
3486 | ++s; | |
3487 | else | |
3488 | { | |
3489 | ++s; | |
3490 | got_minus[2] = 1; | |
3491 | } | |
3492 | ||
3493 | displacements[2] = strtol (s, (char **) &s, 10); | |
3494 | ||
3495 | if (*s != '(' || s[1] != '%') | |
3496 | break; | |
3497 | ||
3498 | s += 2; | |
3499 | start = s; | |
3500 | ||
3501 | while (isalnum (*s)) | |
3502 | ++s; | |
3503 | ||
3504 | if (*s++ != ')') | |
3505 | break; | |
3506 | ||
3507 | len = s - start; | |
3508 | regname = alloca (len + 1); | |
3509 | ||
3510 | strncpy (regname, start, len); | |
3511 | regname[len] = '\0'; | |
3512 | ||
3513 | if (user_reg_map_name_to_regnum (gdbarch, | |
3514 | regname, len) == -1) | |
3515 | error (_("Invalid register name `%s' " | |
3516 | "on expression `%s'."), | |
3517 | regname, p->saved_arg); | |
3518 | ||
3519 | for (i = 0; i < 3; i++) | |
3520 | { | |
3521 | write_exp_elt_opcode (OP_LONG); | |
3522 | write_exp_elt_type | |
3523 | (builtin_type (gdbarch)->builtin_long); | |
3524 | write_exp_elt_longcst (displacements[i]); | |
3525 | write_exp_elt_opcode (OP_LONG); | |
3526 | if (got_minus[i]) | |
3527 | write_exp_elt_opcode (UNOP_NEG); | |
3528 | } | |
3529 | ||
3530 | write_exp_elt_opcode (OP_REGISTER); | |
3531 | str.ptr = regname; | |
3532 | str.length = len; | |
3533 | write_exp_string (str); | |
3534 | write_exp_elt_opcode (OP_REGISTER); | |
3535 | ||
3536 | write_exp_elt_opcode (UNOP_CAST); | |
3537 | write_exp_elt_type (builtin_type (gdbarch)->builtin_data_ptr); | |
3538 | write_exp_elt_opcode (UNOP_CAST); | |
3539 | ||
3540 | write_exp_elt_opcode (BINOP_ADD); | |
3541 | write_exp_elt_opcode (BINOP_ADD); | |
3542 | write_exp_elt_opcode (BINOP_ADD); | |
3543 | ||
3544 | write_exp_elt_opcode (UNOP_CAST); | |
3545 | write_exp_elt_type (lookup_pointer_type (p->arg_type)); | |
3546 | write_exp_elt_opcode (UNOP_CAST); | |
3547 | ||
3548 | write_exp_elt_opcode (UNOP_IND); | |
3549 | ||
3550 | p->arg = s; | |
3551 | ||
3552 | return 1; | |
3553 | } | |
3554 | break; | |
3555 | } | |
3556 | case THREE_ARG_DISPLACEMENT: | |
3557 | { | |
3558 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
3559 | { | |
3560 | int offset_minus = 0; | |
3561 | long offset = 0; | |
3562 | int size_minus = 0; | |
3563 | long size = 0; | |
3564 | const char *start; | |
3565 | char *base; | |
3566 | int len_base; | |
3567 | char *index; | |
3568 | int len_index; | |
3569 | struct stoken base_token, index_token; | |
3570 | ||
3571 | if (*s == '+') | |
3572 | ++s; | |
3573 | else if (*s == '-') | |
3574 | { | |
3575 | ++s; | |
3576 | offset_minus = 1; | |
3577 | } | |
3578 | ||
3579 | if (offset_minus && !isdigit (*s)) | |
3580 | break; | |
3581 | ||
3582 | if (isdigit (*s)) | |
3583 | offset = strtol (s, (char **) &s, 10); | |
3584 | ||
3585 | if (*s != '(' || s[1] != '%') | |
3586 | break; | |
3587 | ||
3588 | s += 2; | |
3589 | start = s; | |
3590 | ||
3591 | while (isalnum (*s)) | |
3592 | ++s; | |
3593 | ||
3594 | if (*s != ',' || s[1] != '%') | |
3595 | break; | |
3596 | ||
3597 | len_base = s - start; | |
3598 | base = alloca (len_base + 1); | |
3599 | strncpy (base, start, len_base); | |
3600 | base[len_base] = '\0'; | |
3601 | ||
3602 | if (user_reg_map_name_to_regnum (gdbarch, | |
3603 | base, len_base) == -1) | |
3604 | error (_("Invalid register name `%s' " | |
3605 | "on expression `%s'."), | |
3606 | base, p->saved_arg); | |
3607 | ||
3608 | s += 2; | |
3609 | start = s; | |
3610 | ||
3611 | while (isalnum (*s)) | |
3612 | ++s; | |
3613 | ||
3614 | len_index = s - start; | |
3615 | index = alloca (len_index + 1); | |
3616 | strncpy (index, start, len_index); | |
3617 | index[len_index] = '\0'; | |
3618 | ||
3619 | if (user_reg_map_name_to_regnum (gdbarch, | |
3620 | index, len_index) == -1) | |
3621 | error (_("Invalid register name `%s' " | |
3622 | "on expression `%s'."), | |
3623 | index, p->saved_arg); | |
3624 | ||
3625 | if (*s != ',' && *s != ')') | |
3626 | break; | |
3627 | ||
3628 | if (*s == ',') | |
3629 | { | |
3630 | ++s; | |
3631 | if (*s == '+') | |
3632 | ++s; | |
3633 | else if (*s == '-') | |
3634 | { | |
3635 | ++s; | |
3636 | size_minus = 1; | |
3637 | } | |
3638 | ||
3639 | size = strtol (s, (char **) &s, 10); | |
3640 | ||
3641 | if (*s != ')') | |
3642 | break; | |
3643 | } | |
3644 | ||
3645 | ++s; | |
3646 | ||
3647 | if (offset) | |
3648 | { | |
3649 | write_exp_elt_opcode (OP_LONG); | |
3650 | write_exp_elt_type | |
3651 | (builtin_type (gdbarch)->builtin_long); | |
3652 | write_exp_elt_longcst (offset); | |
3653 | write_exp_elt_opcode (OP_LONG); | |
3654 | if (offset_minus) | |
3655 | write_exp_elt_opcode (UNOP_NEG); | |
3656 | } | |
3657 | ||
3658 | write_exp_elt_opcode (OP_REGISTER); | |
3659 | base_token.ptr = base; | |
3660 | base_token.length = len_base; | |
3661 | write_exp_string (base_token); | |
3662 | write_exp_elt_opcode (OP_REGISTER); | |
3663 | ||
3664 | if (offset) | |
3665 | write_exp_elt_opcode (BINOP_ADD); | |
3666 | ||
3667 | write_exp_elt_opcode (OP_REGISTER); | |
3668 | index_token.ptr = index; | |
3669 | index_token.length = len_index; | |
3670 | write_exp_string (index_token); | |
3671 | write_exp_elt_opcode (OP_REGISTER); | |
3672 | ||
3673 | if (size) | |
3674 | { | |
3675 | write_exp_elt_opcode (OP_LONG); | |
3676 | write_exp_elt_type | |
3677 | (builtin_type (gdbarch)->builtin_long); | |
3678 | write_exp_elt_longcst (size); | |
3679 | write_exp_elt_opcode (OP_LONG); | |
3680 | if (size_minus) | |
3681 | write_exp_elt_opcode (UNOP_NEG); | |
3682 | write_exp_elt_opcode (BINOP_MUL); | |
3683 | } | |
3684 | ||
3685 | write_exp_elt_opcode (BINOP_ADD); | |
3686 | ||
3687 | write_exp_elt_opcode (UNOP_CAST); | |
3688 | write_exp_elt_type (lookup_pointer_type (p->arg_type)); | |
3689 | write_exp_elt_opcode (UNOP_CAST); | |
3690 | ||
3691 | write_exp_elt_opcode (UNOP_IND); | |
3692 | ||
3693 | p->arg = s; | |
3694 | ||
3695 | return 1; | |
3696 | } | |
3697 | break; | |
3698 | } | |
3699 | } | |
3700 | ||
3701 | /* Advancing to the next state. */ | |
3702 | ++current_state; | |
3703 | } | |
3704 | ||
3705 | return 0; | |
3706 | } | |
3707 | ||
8201327c | 3708 | \f |
3ce1502b | 3709 | |
8201327c | 3710 | /* Generic ELF. */ |
d2a7c97a | 3711 | |
8201327c MK |
3712 | void |
3713 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3714 | { | |
c4fc7f1b MK |
3715 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
3716 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
3717 | |
3718 | /* Registering SystemTap handlers. */ | |
3719 | set_gdbarch_stap_integer_prefix (gdbarch, "$"); | |
3720 | set_gdbarch_stap_register_prefix (gdbarch, "%"); | |
3721 | set_gdbarch_stap_register_indirection_prefix (gdbarch, "("); | |
3722 | set_gdbarch_stap_register_indirection_suffix (gdbarch, ")"); | |
3723 | set_gdbarch_stap_is_single_operand (gdbarch, | |
3724 | i386_stap_is_single_operand); | |
3725 | set_gdbarch_stap_parse_special_token (gdbarch, | |
3726 | i386_stap_parse_special_token); | |
8201327c | 3727 | } |
3ce1502b | 3728 | |
8201327c | 3729 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3730 | |
8201327c MK |
3731 | void |
3732 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3733 | { | |
3734 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 3735 | |
8201327c MK |
3736 | /* System V Release 4 uses ELF. */ |
3737 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 3738 | |
dfe01d39 | 3739 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
3740 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
3741 | ||
911bc6ee | 3742 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 3743 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3744 | tdep->sc_pc_offset = 36 + 14 * 4; |
3745 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3746 | |
8201327c | 3747 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3748 | } |
3749 | ||
8201327c | 3750 | /* DJGPP. */ |
3ce1502b | 3751 | |
3a1e71e3 | 3752 | static void |
8201327c | 3753 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3754 | { |
8201327c | 3755 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3756 | |
911bc6ee MK |
3757 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3758 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3759 | |
8201327c | 3760 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3761 | |
3762 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3763 | if (! tdesc_has_registers (info.target_desc)) |
3764 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3765 | |
3766 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3767 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3768 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3769 | set_gdbarch_sdb_reg_to_regnum. */ | |
3770 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3771 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3772 | |
3773 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3774 | } |
8201327c | 3775 | \f |
2acceee2 | 3776 | |
38c968cf AC |
3777 | /* i386 register groups. In addition to the normal groups, add "mmx" |
3778 | and "sse". */ | |
3779 | ||
3780 | static struct reggroup *i386_sse_reggroup; | |
3781 | static struct reggroup *i386_mmx_reggroup; | |
3782 | ||
3783 | static void | |
3784 | i386_init_reggroups (void) | |
3785 | { | |
3786 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
3787 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
3788 | } | |
3789 | ||
3790 | static void | |
3791 | i386_add_reggroups (struct gdbarch *gdbarch) | |
3792 | { | |
3793 | reggroup_add (gdbarch, i386_sse_reggroup); | |
3794 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
3795 | reggroup_add (gdbarch, general_reggroup); | |
3796 | reggroup_add (gdbarch, float_reggroup); | |
3797 | reggroup_add (gdbarch, all_reggroup); | |
3798 | reggroup_add (gdbarch, save_reggroup); | |
3799 | reggroup_add (gdbarch, restore_reggroup); | |
3800 | reggroup_add (gdbarch, vector_reggroup); | |
3801 | reggroup_add (gdbarch, system_reggroup); | |
3802 | } | |
3803 | ||
3804 | int | |
3805 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
3806 | struct reggroup *group) | |
3807 | { | |
c131fcee L |
3808 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3809 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
3810 | ymm_regnum_p, ymmh_regnum_p; | |
acd5c798 | 3811 | |
1ba53b71 L |
3812 | /* Don't include pseudo registers, except for MMX, in any register |
3813 | groups. */ | |
c131fcee | 3814 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3815 | return 0; |
3816 | ||
c131fcee | 3817 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3818 | return 0; |
3819 | ||
c131fcee | 3820 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3821 | return 0; |
3822 | ||
3823 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
3824 | if (group == i386_mmx_reggroup) |
3825 | return mmx_regnum_p; | |
1ba53b71 | 3826 | |
c131fcee L |
3827 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
3828 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 3829 | if (group == i386_sse_reggroup) |
c131fcee L |
3830 | return xmm_regnum_p || mxcsr_regnum_p; |
3831 | ||
3832 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 3833 | if (group == vector_reggroup) |
c131fcee L |
3834 | return (mmx_regnum_p |
3835 | || ymm_regnum_p | |
3836 | || mxcsr_regnum_p | |
3837 | || (xmm_regnum_p | |
3838 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
3839 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
3840 | |
3841 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
3842 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
3843 | if (group == float_reggroup) |
3844 | return fp_regnum_p; | |
1ba53b71 | 3845 | |
c131fcee L |
3846 | /* For "info reg all", don't include upper YMM registers nor XMM |
3847 | registers when AVX is supported. */ | |
3848 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
3849 | if (group == all_reggroup | |
3850 | && ((xmm_regnum_p | |
3851 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
3852 | || ymmh_regnum_p)) | |
3853 | return 0; | |
3854 | ||
38c968cf | 3855 | if (group == general_reggroup) |
1ba53b71 L |
3856 | return (!fp_regnum_p |
3857 | && !mmx_regnum_p | |
c131fcee L |
3858 | && !mxcsr_regnum_p |
3859 | && !xmm_regnum_p | |
3860 | && !ymm_regnum_p | |
3861 | && !ymmh_regnum_p); | |
acd5c798 | 3862 | |
38c968cf AC |
3863 | return default_register_reggroup_p (gdbarch, regnum, group); |
3864 | } | |
38c968cf | 3865 | \f |
acd5c798 | 3866 | |
f837910f MK |
3867 | /* Get the ARGIth function argument for the current function. */ |
3868 | ||
42c466d7 | 3869 | static CORE_ADDR |
143985b7 AF |
3870 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
3871 | struct type *type) | |
3872 | { | |
e17a4113 UW |
3873 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3874 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 3875 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 3876 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
3877 | } |
3878 | ||
514f746b AR |
3879 | static void |
3880 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
3881 | { | |
3882 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
3883 | ||
3884 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
3885 | adjust the PC in the regcache. */ | |
3886 | current_pc += 1; | |
3887 | regcache_write_pc (regcache, current_pc); | |
3888 | } | |
3889 | ||
3890 | ||
7ad10968 HZ |
3891 | #define PREFIX_REPZ 0x01 |
3892 | #define PREFIX_REPNZ 0x02 | |
3893 | #define PREFIX_LOCK 0x04 | |
3894 | #define PREFIX_DATA 0x08 | |
3895 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 3896 | |
7ad10968 HZ |
3897 | /* operand size */ |
3898 | enum | |
3899 | { | |
3900 | OT_BYTE = 0, | |
3901 | OT_WORD, | |
3902 | OT_LONG, | |
cf648174 | 3903 | OT_QUAD, |
a3c4230a | 3904 | OT_DQUAD, |
7ad10968 | 3905 | }; |
473f17b0 | 3906 | |
7ad10968 HZ |
3907 | /* i386 arith/logic operations */ |
3908 | enum | |
3909 | { | |
3910 | OP_ADDL, | |
3911 | OP_ORL, | |
3912 | OP_ADCL, | |
3913 | OP_SBBL, | |
3914 | OP_ANDL, | |
3915 | OP_SUBL, | |
3916 | OP_XORL, | |
3917 | OP_CMPL, | |
3918 | }; | |
5716833c | 3919 | |
7ad10968 HZ |
3920 | struct i386_record_s |
3921 | { | |
cf648174 | 3922 | struct gdbarch *gdbarch; |
7ad10968 | 3923 | struct regcache *regcache; |
df61f520 | 3924 | CORE_ADDR orig_addr; |
7ad10968 HZ |
3925 | CORE_ADDR addr; |
3926 | int aflag; | |
3927 | int dflag; | |
3928 | int override; | |
3929 | uint8_t modrm; | |
3930 | uint8_t mod, reg, rm; | |
3931 | int ot; | |
cf648174 HZ |
3932 | uint8_t rex_x; |
3933 | uint8_t rex_b; | |
3934 | int rip_offset; | |
3935 | int popl_esp_hack; | |
3936 | const int *regmap; | |
7ad10968 | 3937 | }; |
5716833c | 3938 | |
99c1624c PA |
3939 | /* Parse the "modrm" part of the memory address irp->addr points at. |
3940 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 3941 | |
7ad10968 HZ |
3942 | static int |
3943 | i386_record_modrm (struct i386_record_s *irp) | |
3944 | { | |
cf648174 | 3945 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 3946 | |
4ffa4fc7 PA |
3947 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
3948 | return -1; | |
3949 | ||
7ad10968 HZ |
3950 | irp->addr++; |
3951 | irp->mod = (irp->modrm >> 6) & 3; | |
3952 | irp->reg = (irp->modrm >> 3) & 7; | |
3953 | irp->rm = irp->modrm & 7; | |
5716833c | 3954 | |
7ad10968 HZ |
3955 | return 0; |
3956 | } | |
d2a7c97a | 3957 | |
99c1624c PA |
3958 | /* Extract the memory address that the current instruction writes to, |
3959 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 3960 | |
7ad10968 | 3961 | static int |
cf648174 | 3962 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 3963 | { |
cf648174 | 3964 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
3965 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3966 | gdb_byte buf[4]; | |
3967 | ULONGEST offset64; | |
21d0e8a4 | 3968 | |
7ad10968 HZ |
3969 | *addr = 0; |
3970 | if (irp->aflag) | |
3971 | { | |
3972 | /* 32 bits */ | |
3973 | int havesib = 0; | |
3974 | uint8_t scale = 0; | |
648d0c8b | 3975 | uint8_t byte; |
7ad10968 HZ |
3976 | uint8_t index = 0; |
3977 | uint8_t base = irp->rm; | |
896fb97d | 3978 | |
7ad10968 HZ |
3979 | if (base == 4) |
3980 | { | |
3981 | havesib = 1; | |
4ffa4fc7 PA |
3982 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
3983 | return -1; | |
7ad10968 | 3984 | irp->addr++; |
648d0c8b MS |
3985 | scale = (byte >> 6) & 3; |
3986 | index = ((byte >> 3) & 7) | irp->rex_x; | |
3987 | base = (byte & 7); | |
7ad10968 | 3988 | } |
cf648174 | 3989 | base |= irp->rex_b; |
21d0e8a4 | 3990 | |
7ad10968 HZ |
3991 | switch (irp->mod) |
3992 | { | |
3993 | case 0: | |
3994 | if ((base & 7) == 5) | |
3995 | { | |
3996 | base = 0xff; | |
4ffa4fc7 PA |
3997 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
3998 | return -1; | |
7ad10968 | 3999 | irp->addr += 4; |
60a1502a | 4000 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4001 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4002 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4003 | } |
7ad10968 HZ |
4004 | break; |
4005 | case 1: | |
4ffa4fc7 PA |
4006 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4007 | return -1; | |
7ad10968 | 4008 | irp->addr++; |
60a1502a | 4009 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4010 | break; |
4011 | case 2: | |
4ffa4fc7 PA |
4012 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4013 | return -1; | |
60a1502a | 4014 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4015 | irp->addr += 4; |
4016 | break; | |
4017 | } | |
356a6b3e | 4018 | |
60a1502a | 4019 | offset64 = 0; |
7ad10968 | 4020 | if (base != 0xff) |
cf648174 HZ |
4021 | { |
4022 | if (base == 4 && irp->popl_esp_hack) | |
4023 | *addr += irp->popl_esp_hack; | |
4024 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4025 | &offset64); |
7ad10968 | 4026 | } |
cf648174 HZ |
4027 | if (irp->aflag == 2) |
4028 | { | |
60a1502a | 4029 | *addr += offset64; |
cf648174 HZ |
4030 | } |
4031 | else | |
60a1502a | 4032 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4033 | |
7ad10968 HZ |
4034 | if (havesib && (index != 4 || scale != 0)) |
4035 | { | |
cf648174 | 4036 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4037 | &offset64); |
cf648174 | 4038 | if (irp->aflag == 2) |
60a1502a | 4039 | *addr += offset64 << scale; |
cf648174 | 4040 | else |
60a1502a | 4041 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
4042 | } |
4043 | } | |
4044 | else | |
4045 | { | |
4046 | /* 16 bits */ | |
4047 | switch (irp->mod) | |
4048 | { | |
4049 | case 0: | |
4050 | if (irp->rm == 6) | |
4051 | { | |
4ffa4fc7 PA |
4052 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4053 | return -1; | |
7ad10968 | 4054 | irp->addr += 2; |
60a1502a | 4055 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4056 | irp->rm = 0; |
4057 | goto no_rm; | |
4058 | } | |
7ad10968 HZ |
4059 | break; |
4060 | case 1: | |
4ffa4fc7 PA |
4061 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4062 | return -1; | |
7ad10968 | 4063 | irp->addr++; |
60a1502a | 4064 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4065 | break; |
4066 | case 2: | |
4ffa4fc7 PA |
4067 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4068 | return -1; | |
7ad10968 | 4069 | irp->addr += 2; |
60a1502a | 4070 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4071 | break; |
4072 | } | |
c4fc7f1b | 4073 | |
7ad10968 HZ |
4074 | switch (irp->rm) |
4075 | { | |
4076 | case 0: | |
cf648174 HZ |
4077 | regcache_raw_read_unsigned (irp->regcache, |
4078 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4079 | &offset64); |
4080 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4081 | regcache_raw_read_unsigned (irp->regcache, |
4082 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4083 | &offset64); |
4084 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4085 | break; |
4086 | case 1: | |
cf648174 HZ |
4087 | regcache_raw_read_unsigned (irp->regcache, |
4088 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4089 | &offset64); |
4090 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4091 | regcache_raw_read_unsigned (irp->regcache, |
4092 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4093 | &offset64); |
4094 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4095 | break; |
4096 | case 2: | |
cf648174 HZ |
4097 | regcache_raw_read_unsigned (irp->regcache, |
4098 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4099 | &offset64); |
4100 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4101 | regcache_raw_read_unsigned (irp->regcache, |
4102 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4103 | &offset64); |
4104 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4105 | break; |
4106 | case 3: | |
cf648174 HZ |
4107 | regcache_raw_read_unsigned (irp->regcache, |
4108 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4109 | &offset64); |
4110 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4111 | regcache_raw_read_unsigned (irp->regcache, |
4112 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4113 | &offset64); |
4114 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4115 | break; |
4116 | case 4: | |
cf648174 HZ |
4117 | regcache_raw_read_unsigned (irp->regcache, |
4118 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4119 | &offset64); |
4120 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4121 | break; |
4122 | case 5: | |
cf648174 HZ |
4123 | regcache_raw_read_unsigned (irp->regcache, |
4124 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4125 | &offset64); |
4126 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4127 | break; |
4128 | case 6: | |
cf648174 HZ |
4129 | regcache_raw_read_unsigned (irp->regcache, |
4130 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4131 | &offset64); |
4132 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4133 | break; |
4134 | case 7: | |
cf648174 HZ |
4135 | regcache_raw_read_unsigned (irp->regcache, |
4136 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4137 | &offset64); |
4138 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4139 | break; |
4140 | } | |
4141 | *addr &= 0xffff; | |
4142 | } | |
c4fc7f1b | 4143 | |
01fe1b41 | 4144 | no_rm: |
7ad10968 HZ |
4145 | return 0; |
4146 | } | |
c4fc7f1b | 4147 | |
99c1624c PA |
4148 | /* Record the address and contents of the memory that will be changed |
4149 | by the current instruction. Return -1 if something goes wrong, 0 | |
4150 | otherwise. */ | |
356a6b3e | 4151 | |
7ad10968 HZ |
4152 | static int |
4153 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4154 | { | |
cf648174 HZ |
4155 | struct gdbarch *gdbarch = irp->gdbarch; |
4156 | uint64_t addr; | |
356a6b3e | 4157 | |
d7877f7e | 4158 | if (irp->override >= 0) |
7ad10968 | 4159 | { |
bb08c432 HZ |
4160 | if (record_memory_query) |
4161 | { | |
4162 | int q; | |
4163 | ||
4164 | target_terminal_ours (); | |
4165 | q = yquery (_("\ | |
4166 | Process record ignores the memory change of instruction at address %s\n\ | |
4167 | because it can't get the value of the segment register.\n\ | |
4168 | Do you want to stop the program?"), | |
4169 | paddress (gdbarch, irp->orig_addr)); | |
4170 | target_terminal_inferior (); | |
4171 | if (q) | |
4172 | return -1; | |
4173 | } | |
4174 | ||
7ad10968 HZ |
4175 | return 0; |
4176 | } | |
61113f8b | 4177 | |
7ad10968 HZ |
4178 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4179 | return -1; | |
96297dab | 4180 | |
7ad10968 HZ |
4181 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
4182 | return -1; | |
a62cc96e | 4183 | |
7ad10968 HZ |
4184 | return 0; |
4185 | } | |
b6197528 | 4186 | |
99c1624c PA |
4187 | /* Record the effects of a push operation. Return -1 if something |
4188 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4189 | |
4190 | static int | |
4191 | i386_record_push (struct i386_record_s *irp, int size) | |
4192 | { | |
648d0c8b | 4193 | ULONGEST addr; |
cf648174 HZ |
4194 | |
4195 | if (record_arch_list_add_reg (irp->regcache, | |
4196 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
4197 | return -1; | |
4198 | regcache_raw_read_unsigned (irp->regcache, | |
4199 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
4200 | &addr); |
4201 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
4202 | return -1; |
4203 | ||
4204 | return 0; | |
4205 | } | |
4206 | ||
0289bdd7 MS |
4207 | |
4208 | /* Defines contents to record. */ | |
4209 | #define I386_SAVE_FPU_REGS 0xfffd | |
4210 | #define I386_SAVE_FPU_ENV 0xfffe | |
4211 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4212 | ||
99c1624c PA |
4213 | /* Record the values of the floating point registers which will be |
4214 | changed by the current instruction. Returns -1 if something is | |
4215 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4216 | |
4217 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4218 | struct i386_record_s *ir, | |
4219 | uint32_t iregnum) | |
4220 | { | |
4221 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4222 | int i; | |
4223 | ||
4224 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4225 | happen. Currently we store st0-st7 registers, but we need not store all | |
4226 | registers all the time, in future we use ftag register and record only | |
4227 | those who are not marked as an empty. */ | |
4228 | ||
4229 | if (I386_SAVE_FPU_REGS == iregnum) | |
4230 | { | |
4231 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4232 | { | |
4233 | if (record_arch_list_add_reg (ir->regcache, i)) | |
4234 | return -1; | |
4235 | } | |
4236 | } | |
4237 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4238 | { | |
4239 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4240 | { | |
4241 | if (record_arch_list_add_reg (ir->regcache, i)) | |
4242 | return -1; | |
4243 | } | |
4244 | } | |
4245 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4246 | { | |
4247 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4248 | { | |
4249 | if (record_arch_list_add_reg (ir->regcache, i)) | |
4250 | return -1; | |
4251 | } | |
4252 | } | |
4253 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
4254 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
4255 | { | |
4256 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
4257 | return -1; | |
4258 | } | |
4259 | else | |
4260 | { | |
4261 | /* Parameter error. */ | |
4262 | return -1; | |
4263 | } | |
4264 | if(I386_SAVE_FPU_ENV != iregnum) | |
4265 | { | |
4266 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4267 | { | |
4268 | if (record_arch_list_add_reg (ir->regcache, i)) | |
4269 | return -1; | |
4270 | } | |
4271 | } | |
4272 | return 0; | |
4273 | } | |
4274 | ||
99c1624c PA |
4275 | /* Parse the current instruction, and record the values of the |
4276 | registers and memory that will be changed by the current | |
4277 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 4278 | |
cf648174 HZ |
4279 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
4280 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
4281 | ||
a6b808b4 | 4282 | int |
7ad10968 | 4283 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 4284 | CORE_ADDR input_addr) |
7ad10968 | 4285 | { |
60a1502a | 4286 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 4287 | int prefixes = 0; |
580879fc | 4288 | int regnum = 0; |
425b824a | 4289 | uint32_t opcode; |
f4644a3f | 4290 | uint8_t opcode8; |
648d0c8b | 4291 | ULONGEST addr; |
60a1502a | 4292 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 4293 | struct i386_record_s ir; |
0289bdd7 | 4294 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
4295 | int rex = 0; |
4296 | uint8_t rex_w = -1; | |
4297 | uint8_t rex_r = 0; | |
7ad10968 | 4298 | |
8408d274 | 4299 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 4300 | ir.regcache = regcache; |
648d0c8b MS |
4301 | ir.addr = input_addr; |
4302 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
4303 | ir.aflag = 1; |
4304 | ir.dflag = 1; | |
cf648174 HZ |
4305 | ir.override = -1; |
4306 | ir.popl_esp_hack = 0; | |
a3c4230a | 4307 | ir.regmap = tdep->record_regmap; |
cf648174 | 4308 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
4309 | |
4310 | if (record_debug > 1) | |
4311 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
4312 | "addr = %s\n", |
4313 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4314 | |
4315 | /* prefixes */ | |
4316 | while (1) | |
4317 | { | |
4ffa4fc7 PA |
4318 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
4319 | return -1; | |
7ad10968 | 4320 | ir.addr++; |
425b824a | 4321 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 4322 | { |
01fe1b41 | 4323 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
4324 | prefixes |= PREFIX_REPZ; |
4325 | break; | |
01fe1b41 | 4326 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
4327 | prefixes |= PREFIX_REPNZ; |
4328 | break; | |
01fe1b41 | 4329 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
4330 | prefixes |= PREFIX_LOCK; |
4331 | break; | |
01fe1b41 | 4332 | case CS_PREFIX_OPCODE: |
cf648174 | 4333 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 4334 | break; |
01fe1b41 | 4335 | case SS_PREFIX_OPCODE: |
cf648174 | 4336 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 4337 | break; |
01fe1b41 | 4338 | case DS_PREFIX_OPCODE: |
cf648174 | 4339 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 4340 | break; |
01fe1b41 | 4341 | case ES_PREFIX_OPCODE: |
cf648174 | 4342 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 4343 | break; |
01fe1b41 | 4344 | case FS_PREFIX_OPCODE: |
cf648174 | 4345 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 4346 | break; |
01fe1b41 | 4347 | case GS_PREFIX_OPCODE: |
cf648174 | 4348 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 4349 | break; |
01fe1b41 | 4350 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
4351 | prefixes |= PREFIX_DATA; |
4352 | break; | |
01fe1b41 | 4353 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
4354 | prefixes |= PREFIX_ADDR; |
4355 | break; | |
d691bec7 MS |
4356 | case 0x40: /* i386 inc %eax */ |
4357 | case 0x41: /* i386 inc %ecx */ | |
4358 | case 0x42: /* i386 inc %edx */ | |
4359 | case 0x43: /* i386 inc %ebx */ | |
4360 | case 0x44: /* i386 inc %esp */ | |
4361 | case 0x45: /* i386 inc %ebp */ | |
4362 | case 0x46: /* i386 inc %esi */ | |
4363 | case 0x47: /* i386 inc %edi */ | |
4364 | case 0x48: /* i386 dec %eax */ | |
4365 | case 0x49: /* i386 dec %ecx */ | |
4366 | case 0x4a: /* i386 dec %edx */ | |
4367 | case 0x4b: /* i386 dec %ebx */ | |
4368 | case 0x4c: /* i386 dec %esp */ | |
4369 | case 0x4d: /* i386 dec %ebp */ | |
4370 | case 0x4e: /* i386 dec %esi */ | |
4371 | case 0x4f: /* i386 dec %edi */ | |
4372 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
4373 | { |
4374 | /* REX */ | |
4375 | rex = 1; | |
425b824a MS |
4376 | rex_w = (opcode8 >> 3) & 1; |
4377 | rex_r = (opcode8 & 0x4) << 1; | |
4378 | ir.rex_x = (opcode8 & 0x2) << 2; | |
4379 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 4380 | } |
d691bec7 MS |
4381 | else /* 32 bit target */ |
4382 | goto out_prefixes; | |
cf648174 | 4383 | break; |
7ad10968 HZ |
4384 | default: |
4385 | goto out_prefixes; | |
4386 | break; | |
4387 | } | |
4388 | } | |
01fe1b41 | 4389 | out_prefixes: |
cf648174 HZ |
4390 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
4391 | { | |
4392 | ir.dflag = 2; | |
4393 | } | |
4394 | else | |
4395 | { | |
4396 | if (prefixes & PREFIX_DATA) | |
4397 | ir.dflag ^= 1; | |
4398 | } | |
7ad10968 HZ |
4399 | if (prefixes & PREFIX_ADDR) |
4400 | ir.aflag ^= 1; | |
cf648174 HZ |
4401 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4402 | ir.aflag = 2; | |
7ad10968 | 4403 | |
1777feb0 | 4404 | /* Now check op code. */ |
425b824a | 4405 | opcode = (uint32_t) opcode8; |
01fe1b41 | 4406 | reswitch: |
7ad10968 HZ |
4407 | switch (opcode) |
4408 | { | |
4409 | case 0x0f: | |
4ffa4fc7 PA |
4410 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
4411 | return -1; | |
7ad10968 | 4412 | ir.addr++; |
a3c4230a | 4413 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
4414 | goto reswitch; |
4415 | break; | |
93924b6b | 4416 | |
a38bba38 | 4417 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
4418 | case 0x01: |
4419 | case 0x02: | |
4420 | case 0x03: | |
4421 | case 0x04: | |
4422 | case 0x05: | |
4423 | case 0x08: | |
4424 | case 0x09: | |
4425 | case 0x0a: | |
4426 | case 0x0b: | |
4427 | case 0x0c: | |
4428 | case 0x0d: | |
4429 | case 0x10: | |
4430 | case 0x11: | |
4431 | case 0x12: | |
4432 | case 0x13: | |
4433 | case 0x14: | |
4434 | case 0x15: | |
4435 | case 0x18: | |
4436 | case 0x19: | |
4437 | case 0x1a: | |
4438 | case 0x1b: | |
4439 | case 0x1c: | |
4440 | case 0x1d: | |
4441 | case 0x20: | |
4442 | case 0x21: | |
4443 | case 0x22: | |
4444 | case 0x23: | |
4445 | case 0x24: | |
4446 | case 0x25: | |
4447 | case 0x28: | |
4448 | case 0x29: | |
4449 | case 0x2a: | |
4450 | case 0x2b: | |
4451 | case 0x2c: | |
4452 | case 0x2d: | |
4453 | case 0x30: | |
4454 | case 0x31: | |
4455 | case 0x32: | |
4456 | case 0x33: | |
4457 | case 0x34: | |
4458 | case 0x35: | |
4459 | case 0x38: | |
4460 | case 0x39: | |
4461 | case 0x3a: | |
4462 | case 0x3b: | |
4463 | case 0x3c: | |
4464 | case 0x3d: | |
4465 | if (((opcode >> 3) & 7) != OP_CMPL) | |
4466 | { | |
4467 | if ((opcode & 1) == 0) | |
4468 | ir.ot = OT_BYTE; | |
4469 | else | |
4470 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 4471 | |
7ad10968 HZ |
4472 | switch ((opcode >> 1) & 3) |
4473 | { | |
a38bba38 | 4474 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
4475 | if (i386_record_modrm (&ir)) |
4476 | return -1; | |
4477 | if (ir.mod != 3) | |
4478 | { | |
4479 | if (i386_record_lea_modrm (&ir)) | |
4480 | return -1; | |
4481 | } | |
4482 | else | |
4483 | { | |
cf648174 HZ |
4484 | ir.rm |= ir.rex_b; |
4485 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4486 | ir.rm &= 0x3; |
cf648174 | 4487 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4488 | } |
4489 | break; | |
a38bba38 | 4490 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
4491 | if (i386_record_modrm (&ir)) |
4492 | return -1; | |
cf648174 HZ |
4493 | ir.reg |= rex_r; |
4494 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4495 | ir.reg &= 0x3; |
cf648174 | 4496 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4497 | break; |
a38bba38 | 4498 | case 2: /* OP A, Iv */ |
cf648174 | 4499 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4500 | break; |
4501 | } | |
4502 | } | |
cf648174 | 4503 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4504 | break; |
42fdc8df | 4505 | |
a38bba38 | 4506 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
4507 | case 0x81: |
4508 | case 0x82: | |
4509 | case 0x83: | |
4510 | if (i386_record_modrm (&ir)) | |
4511 | return -1; | |
8201327c | 4512 | |
7ad10968 HZ |
4513 | if (ir.reg != OP_CMPL) |
4514 | { | |
4515 | if ((opcode & 1) == 0) | |
4516 | ir.ot = OT_BYTE; | |
4517 | else | |
4518 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 4519 | |
7ad10968 HZ |
4520 | if (ir.mod != 3) |
4521 | { | |
cf648174 HZ |
4522 | if (opcode == 0x83) |
4523 | ir.rip_offset = 1; | |
4524 | else | |
4525 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4526 | if (i386_record_lea_modrm (&ir)) |
4527 | return -1; | |
4528 | } | |
4529 | else | |
cf648174 | 4530 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 4531 | } |
cf648174 | 4532 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4533 | break; |
5e3397bb | 4534 | |
a38bba38 | 4535 | case 0x40: /* inc */ |
7ad10968 HZ |
4536 | case 0x41: |
4537 | case 0x42: | |
4538 | case 0x43: | |
4539 | case 0x44: | |
4540 | case 0x45: | |
4541 | case 0x46: | |
4542 | case 0x47: | |
a38bba38 MS |
4543 | |
4544 | case 0x48: /* dec */ | |
7ad10968 HZ |
4545 | case 0x49: |
4546 | case 0x4a: | |
4547 | case 0x4b: | |
4548 | case 0x4c: | |
4549 | case 0x4d: | |
4550 | case 0x4e: | |
4551 | case 0x4f: | |
a38bba38 | 4552 | |
cf648174 HZ |
4553 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
4554 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 4555 | break; |
acd5c798 | 4556 | |
a38bba38 | 4557 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
4558 | case 0xf7: |
4559 | if ((opcode & 1) == 0) | |
4560 | ir.ot = OT_BYTE; | |
4561 | else | |
4562 | ir.ot = ir.dflag + OT_WORD; | |
4563 | if (i386_record_modrm (&ir)) | |
4564 | return -1; | |
acd5c798 | 4565 | |
cf648174 HZ |
4566 | if (ir.mod != 3 && ir.reg == 0) |
4567 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4568 | ||
7ad10968 HZ |
4569 | switch (ir.reg) |
4570 | { | |
a38bba38 | 4571 | case 0: /* test */ |
cf648174 | 4572 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4573 | break; |
a38bba38 MS |
4574 | case 2: /* not */ |
4575 | case 3: /* neg */ | |
7ad10968 HZ |
4576 | if (ir.mod != 3) |
4577 | { | |
4578 | if (i386_record_lea_modrm (&ir)) | |
4579 | return -1; | |
4580 | } | |
4581 | else | |
4582 | { | |
cf648174 HZ |
4583 | ir.rm |= ir.rex_b; |
4584 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4585 | ir.rm &= 0x3; |
cf648174 | 4586 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4587 | } |
a38bba38 | 4588 | if (ir.reg == 3) /* neg */ |
cf648174 | 4589 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4590 | break; |
a38bba38 MS |
4591 | case 4: /* mul */ |
4592 | case 5: /* imul */ | |
4593 | case 6: /* div */ | |
4594 | case 7: /* idiv */ | |
cf648174 | 4595 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 4596 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
4597 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
4598 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4599 | break; |
4600 | default: | |
4601 | ir.addr -= 2; | |
4602 | opcode = opcode << 8 | ir.modrm; | |
4603 | goto no_support; | |
4604 | break; | |
4605 | } | |
4606 | break; | |
4607 | ||
a38bba38 MS |
4608 | case 0xfe: /* GRP4 */ |
4609 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
4610 | if (i386_record_modrm (&ir)) |
4611 | return -1; | |
4612 | if (ir.reg >= 2 && opcode == 0xfe) | |
4613 | { | |
4614 | ir.addr -= 2; | |
4615 | opcode = opcode << 8 | ir.modrm; | |
4616 | goto no_support; | |
4617 | } | |
7ad10968 HZ |
4618 | switch (ir.reg) |
4619 | { | |
a38bba38 MS |
4620 | case 0: /* inc */ |
4621 | case 1: /* dec */ | |
cf648174 HZ |
4622 | if ((opcode & 1) == 0) |
4623 | ir.ot = OT_BYTE; | |
4624 | else | |
4625 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4626 | if (ir.mod != 3) |
4627 | { | |
4628 | if (i386_record_lea_modrm (&ir)) | |
4629 | return -1; | |
4630 | } | |
4631 | else | |
4632 | { | |
cf648174 HZ |
4633 | ir.rm |= ir.rex_b; |
4634 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4635 | ir.rm &= 0x3; |
cf648174 | 4636 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4637 | } |
cf648174 | 4638 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4639 | break; |
a38bba38 | 4640 | case 2: /* call */ |
cf648174 HZ |
4641 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4642 | ir.dflag = 2; | |
4643 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4644 | return -1; |
cf648174 | 4645 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4646 | break; |
a38bba38 | 4647 | case 3: /* lcall */ |
cf648174 HZ |
4648 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4649 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4650 | return -1; |
cf648174 | 4651 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4652 | break; |
a38bba38 MS |
4653 | case 4: /* jmp */ |
4654 | case 5: /* ljmp */ | |
cf648174 HZ |
4655 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4656 | break; | |
a38bba38 | 4657 | case 6: /* push */ |
cf648174 HZ |
4658 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4659 | ir.dflag = 2; | |
4660 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4661 | return -1; | |
7ad10968 HZ |
4662 | break; |
4663 | default: | |
4664 | ir.addr -= 2; | |
4665 | opcode = opcode << 8 | ir.modrm; | |
4666 | goto no_support; | |
4667 | break; | |
4668 | } | |
4669 | break; | |
4670 | ||
a38bba38 | 4671 | case 0x84: /* test */ |
7ad10968 HZ |
4672 | case 0x85: |
4673 | case 0xa8: | |
4674 | case 0xa9: | |
cf648174 | 4675 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4676 | break; |
4677 | ||
a38bba38 | 4678 | case 0x98: /* CWDE/CBW */ |
cf648174 | 4679 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4680 | break; |
4681 | ||
a38bba38 | 4682 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
4683 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4684 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4685 | break; |
4686 | ||
a38bba38 | 4687 | case 0x0faf: /* imul */ |
7ad10968 HZ |
4688 | case 0x69: |
4689 | case 0x6b: | |
4690 | ir.ot = ir.dflag + OT_WORD; | |
4691 | if (i386_record_modrm (&ir)) | |
4692 | return -1; | |
cf648174 HZ |
4693 | if (opcode == 0x69) |
4694 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4695 | else if (opcode == 0x6b) | |
4696 | ir.rip_offset = 1; | |
4697 | ir.reg |= rex_r; | |
4698 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4699 | ir.reg &= 0x3; |
cf648174 HZ |
4700 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4701 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4702 | break; |
4703 | ||
a38bba38 | 4704 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4705 | case 0x0fc1: |
4706 | if ((opcode & 1) == 0) | |
4707 | ir.ot = OT_BYTE; | |
4708 | else | |
4709 | ir.ot = ir.dflag + OT_WORD; | |
4710 | if (i386_record_modrm (&ir)) | |
4711 | return -1; | |
cf648174 | 4712 | ir.reg |= rex_r; |
7ad10968 HZ |
4713 | if (ir.mod == 3) |
4714 | { | |
cf648174 | 4715 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4716 | ir.reg &= 0x3; |
cf648174 HZ |
4717 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4718 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4719 | ir.rm &= 0x3; |
cf648174 | 4720 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4721 | } |
4722 | else | |
4723 | { | |
4724 | if (i386_record_lea_modrm (&ir)) | |
4725 | return -1; | |
cf648174 | 4726 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4727 | ir.reg &= 0x3; |
cf648174 | 4728 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4729 | } |
cf648174 | 4730 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4731 | break; |
4732 | ||
a38bba38 | 4733 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4734 | case 0x0fb1: |
4735 | if ((opcode & 1) == 0) | |
4736 | ir.ot = OT_BYTE; | |
4737 | else | |
4738 | ir.ot = ir.dflag + OT_WORD; | |
4739 | if (i386_record_modrm (&ir)) | |
4740 | return -1; | |
4741 | if (ir.mod == 3) | |
4742 | { | |
cf648174 HZ |
4743 | ir.reg |= rex_r; |
4744 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4745 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4746 | ir.reg &= 0x3; |
cf648174 | 4747 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4748 | } |
4749 | else | |
4750 | { | |
cf648174 | 4751 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4752 | if (i386_record_lea_modrm (&ir)) |
4753 | return -1; | |
4754 | } | |
cf648174 | 4755 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4756 | break; |
4757 | ||
a38bba38 | 4758 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4759 | if (i386_record_modrm (&ir)) |
4760 | return -1; | |
4761 | if (ir.mod == 3) | |
4762 | { | |
4763 | ir.addr -= 2; | |
4764 | opcode = opcode << 8 | ir.modrm; | |
4765 | goto no_support; | |
4766 | } | |
cf648174 HZ |
4767 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4768 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4769 | if (i386_record_lea_modrm (&ir)) |
4770 | return -1; | |
cf648174 | 4771 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4772 | break; |
4773 | ||
a38bba38 | 4774 | case 0x50: /* push */ |
7ad10968 HZ |
4775 | case 0x51: |
4776 | case 0x52: | |
4777 | case 0x53: | |
4778 | case 0x54: | |
4779 | case 0x55: | |
4780 | case 0x56: | |
4781 | case 0x57: | |
4782 | case 0x68: | |
4783 | case 0x6a: | |
cf648174 HZ |
4784 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4785 | ir.dflag = 2; | |
4786 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4787 | return -1; | |
4788 | break; | |
4789 | ||
a38bba38 MS |
4790 | case 0x06: /* push es */ |
4791 | case 0x0e: /* push cs */ | |
4792 | case 0x16: /* push ss */ | |
4793 | case 0x1e: /* push ds */ | |
cf648174 HZ |
4794 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4795 | { | |
4796 | ir.addr -= 1; | |
4797 | goto no_support; | |
4798 | } | |
4799 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4800 | return -1; | |
4801 | break; | |
4802 | ||
a38bba38 MS |
4803 | case 0x0fa0: /* push fs */ |
4804 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
4805 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4806 | { | |
4807 | ir.addr -= 2; | |
4808 | goto no_support; | |
4809 | } | |
4810 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4811 | return -1; |
cf648174 HZ |
4812 | break; |
4813 | ||
a38bba38 | 4814 | case 0x60: /* pusha */ |
cf648174 HZ |
4815 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4816 | { | |
4817 | ir.addr -= 1; | |
4818 | goto no_support; | |
4819 | } | |
4820 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
4821 | return -1; |
4822 | break; | |
4823 | ||
a38bba38 | 4824 | case 0x58: /* pop */ |
7ad10968 HZ |
4825 | case 0x59: |
4826 | case 0x5a: | |
4827 | case 0x5b: | |
4828 | case 0x5c: | |
4829 | case 0x5d: | |
4830 | case 0x5e: | |
4831 | case 0x5f: | |
cf648174 HZ |
4832 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4833 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
4834 | break; |
4835 | ||
a38bba38 | 4836 | case 0x61: /* popa */ |
cf648174 HZ |
4837 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4838 | { | |
4839 | ir.addr -= 1; | |
4840 | goto no_support; | |
7ad10968 | 4841 | } |
425b824a MS |
4842 | for (regnum = X86_RECORD_REAX_REGNUM; |
4843 | regnum <= X86_RECORD_REDI_REGNUM; | |
4844 | regnum++) | |
4845 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
4846 | break; |
4847 | ||
a38bba38 | 4848 | case 0x8f: /* pop */ |
cf648174 HZ |
4849 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4850 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
4851 | else | |
4852 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4853 | if (i386_record_modrm (&ir)) |
4854 | return -1; | |
4855 | if (ir.mod == 3) | |
cf648174 | 4856 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
4857 | else |
4858 | { | |
cf648174 | 4859 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
4860 | if (i386_record_lea_modrm (&ir)) |
4861 | return -1; | |
4862 | } | |
cf648174 | 4863 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
4864 | break; |
4865 | ||
a38bba38 | 4866 | case 0xc8: /* enter */ |
cf648174 HZ |
4867 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
4868 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4869 | ir.dflag = 2; | |
4870 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
4871 | return -1; |
4872 | break; | |
4873 | ||
a38bba38 | 4874 | case 0xc9: /* leave */ |
cf648174 HZ |
4875 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4876 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
4877 | break; |
4878 | ||
a38bba38 | 4879 | case 0x07: /* pop es */ |
cf648174 HZ |
4880 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4881 | { | |
4882 | ir.addr -= 1; | |
4883 | goto no_support; | |
4884 | } | |
4885 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4886 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
4887 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4888 | break; |
4889 | ||
a38bba38 | 4890 | case 0x17: /* pop ss */ |
cf648174 HZ |
4891 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4892 | { | |
4893 | ir.addr -= 1; | |
4894 | goto no_support; | |
4895 | } | |
4896 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4897 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
4898 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4899 | break; |
4900 | ||
a38bba38 | 4901 | case 0x1f: /* pop ds */ |
cf648174 HZ |
4902 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4903 | { | |
4904 | ir.addr -= 1; | |
4905 | goto no_support; | |
4906 | } | |
4907 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4908 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
4909 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4910 | break; |
4911 | ||
a38bba38 | 4912 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
4913 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4914 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
4915 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4916 | break; |
4917 | ||
a38bba38 | 4918 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
4919 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4920 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
4921 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4922 | break; |
4923 | ||
a38bba38 | 4924 | case 0x88: /* mov */ |
7ad10968 HZ |
4925 | case 0x89: |
4926 | case 0xc6: | |
4927 | case 0xc7: | |
4928 | if ((opcode & 1) == 0) | |
4929 | ir.ot = OT_BYTE; | |
4930 | else | |
4931 | ir.ot = ir.dflag + OT_WORD; | |
4932 | ||
4933 | if (i386_record_modrm (&ir)) | |
4934 | return -1; | |
4935 | ||
4936 | if (ir.mod != 3) | |
4937 | { | |
cf648174 HZ |
4938 | if (opcode == 0xc6 || opcode == 0xc7) |
4939 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4940 | if (i386_record_lea_modrm (&ir)) |
4941 | return -1; | |
4942 | } | |
4943 | else | |
4944 | { | |
cf648174 HZ |
4945 | if (opcode == 0xc6 || opcode == 0xc7) |
4946 | ir.rm |= ir.rex_b; | |
4947 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4948 | ir.rm &= 0x3; |
cf648174 | 4949 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4950 | } |
7ad10968 | 4951 | break; |
cf648174 | 4952 | |
a38bba38 | 4953 | case 0x8a: /* mov */ |
7ad10968 HZ |
4954 | case 0x8b: |
4955 | if ((opcode & 1) == 0) | |
4956 | ir.ot = OT_BYTE; | |
4957 | else | |
4958 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4959 | if (i386_record_modrm (&ir)) |
4960 | return -1; | |
cf648174 HZ |
4961 | ir.reg |= rex_r; |
4962 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4963 | ir.reg &= 0x3; |
cf648174 HZ |
4964 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4965 | break; | |
7ad10968 | 4966 | |
a38bba38 | 4967 | case 0x8c: /* mov seg */ |
cf648174 | 4968 | if (i386_record_modrm (&ir)) |
7ad10968 | 4969 | return -1; |
cf648174 HZ |
4970 | if (ir.reg > 5) |
4971 | { | |
4972 | ir.addr -= 2; | |
4973 | opcode = opcode << 8 | ir.modrm; | |
4974 | goto no_support; | |
4975 | } | |
4976 | ||
4977 | if (ir.mod == 3) | |
4978 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
4979 | else | |
4980 | { | |
4981 | ir.ot = OT_WORD; | |
4982 | if (i386_record_lea_modrm (&ir)) | |
4983 | return -1; | |
4984 | } | |
7ad10968 HZ |
4985 | break; |
4986 | ||
a38bba38 | 4987 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4988 | if (i386_record_modrm (&ir)) |
4989 | return -1; | |
7ad10968 HZ |
4990 | switch (ir.reg) |
4991 | { | |
4992 | case 0: | |
425b824a | 4993 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4994 | break; |
4995 | case 2: | |
425b824a | 4996 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4997 | break; |
4998 | case 3: | |
425b824a | 4999 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5000 | break; |
5001 | case 4: | |
425b824a | 5002 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5003 | break; |
5004 | case 5: | |
425b824a | 5005 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5006 | break; |
5007 | default: | |
5008 | ir.addr -= 2; | |
5009 | opcode = opcode << 8 | ir.modrm; | |
5010 | goto no_support; | |
5011 | break; | |
5012 | } | |
425b824a | 5013 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 5014 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5015 | break; |
5016 | ||
a38bba38 MS |
5017 | case 0x0fb6: /* movzbS */ |
5018 | case 0x0fb7: /* movzwS */ | |
5019 | case 0x0fbe: /* movsbS */ | |
5020 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5021 | if (i386_record_modrm (&ir)) |
5022 | return -1; | |
cf648174 | 5023 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5024 | break; |
5025 | ||
a38bba38 | 5026 | case 0x8d: /* lea */ |
7ad10968 HZ |
5027 | if (i386_record_modrm (&ir)) |
5028 | return -1; | |
5029 | if (ir.mod == 3) | |
5030 | { | |
5031 | ir.addr -= 2; | |
5032 | opcode = opcode << 8 | ir.modrm; | |
5033 | goto no_support; | |
5034 | } | |
7ad10968 | 5035 | ir.ot = ir.dflag; |
cf648174 HZ |
5036 | ir.reg |= rex_r; |
5037 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5038 | ir.reg &= 0x3; |
cf648174 | 5039 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5040 | break; |
5041 | ||
a38bba38 | 5042 | case 0xa0: /* mov EAX */ |
7ad10968 | 5043 | case 0xa1: |
a38bba38 MS |
5044 | |
5045 | case 0xd7: /* xlat */ | |
cf648174 | 5046 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5047 | break; |
5048 | ||
a38bba38 | 5049 | case 0xa2: /* mov EAX */ |
7ad10968 | 5050 | case 0xa3: |
d7877f7e | 5051 | if (ir.override >= 0) |
cf648174 | 5052 | { |
bb08c432 HZ |
5053 | if (record_memory_query) |
5054 | { | |
5055 | int q; | |
5056 | ||
5057 | target_terminal_ours (); | |
5058 | q = yquery (_("\ | |
5059 | Process record ignores the memory change of instruction at address %s\n\ | |
5060 | because it can't get the value of the segment register.\n\ | |
5061 | Do you want to stop the program?"), | |
5062 | paddress (gdbarch, ir.orig_addr)); | |
5063 | target_terminal_inferior (); | |
5064 | if (q) | |
5065 | return -1; | |
5066 | } | |
cf648174 HZ |
5067 | } |
5068 | else | |
5069 | { | |
5070 | if ((opcode & 1) == 0) | |
5071 | ir.ot = OT_BYTE; | |
5072 | else | |
5073 | ir.ot = ir.dflag + OT_WORD; | |
5074 | if (ir.aflag == 2) | |
5075 | { | |
4ffa4fc7 PA |
5076 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5077 | return -1; | |
cf648174 | 5078 | ir.addr += 8; |
60a1502a | 5079 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5080 | } |
5081 | else if (ir.aflag) | |
5082 | { | |
4ffa4fc7 PA |
5083 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5084 | return -1; | |
cf648174 | 5085 | ir.addr += 4; |
60a1502a | 5086 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5087 | } |
5088 | else | |
5089 | { | |
4ffa4fc7 PA |
5090 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5091 | return -1; | |
cf648174 | 5092 | ir.addr += 2; |
60a1502a | 5093 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5094 | } |
648d0c8b | 5095 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5096 | return -1; |
5097 | } | |
7ad10968 HZ |
5098 | break; |
5099 | ||
a38bba38 | 5100 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5101 | case 0xb1: |
5102 | case 0xb2: | |
5103 | case 0xb3: | |
5104 | case 0xb4: | |
5105 | case 0xb5: | |
5106 | case 0xb6: | |
5107 | case 0xb7: | |
cf648174 HZ |
5108 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5109 | ? ((opcode & 0x7) | ir.rex_b) | |
5110 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5111 | break; |
5112 | ||
a38bba38 | 5113 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5114 | case 0xb9: |
5115 | case 0xba: | |
5116 | case 0xbb: | |
5117 | case 0xbc: | |
5118 | case 0xbd: | |
5119 | case 0xbe: | |
5120 | case 0xbf: | |
cf648174 | 5121 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5122 | break; |
5123 | ||
a38bba38 | 5124 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5125 | case 0x92: |
5126 | case 0x93: | |
5127 | case 0x94: | |
5128 | case 0x95: | |
5129 | case 0x96: | |
5130 | case 0x97: | |
cf648174 HZ |
5131 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5132 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5133 | break; |
5134 | ||
a38bba38 | 5135 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5136 | case 0x87: |
5137 | if ((opcode & 1) == 0) | |
5138 | ir.ot = OT_BYTE; | |
5139 | else | |
5140 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5141 | if (i386_record_modrm (&ir)) |
5142 | return -1; | |
7ad10968 HZ |
5143 | if (ir.mod == 3) |
5144 | { | |
86839d38 | 5145 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5146 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5147 | ir.rm &= 0x3; | |
5148 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
5149 | } |
5150 | else | |
5151 | { | |
5152 | if (i386_record_lea_modrm (&ir)) | |
5153 | return -1; | |
5154 | } | |
cf648174 HZ |
5155 | ir.reg |= rex_r; |
5156 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5157 | ir.reg &= 0x3; |
cf648174 | 5158 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5159 | break; |
5160 | ||
a38bba38 MS |
5161 | case 0xc4: /* les Gv */ |
5162 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5163 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5164 | { | |
5165 | ir.addr -= 1; | |
5166 | goto no_support; | |
5167 | } | |
d3f323f3 | 5168 | /* FALLTHROUGH */ |
a38bba38 MS |
5169 | case 0x0fb2: /* lss Gv */ |
5170 | case 0x0fb4: /* lfs Gv */ | |
5171 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5172 | if (i386_record_modrm (&ir)) |
5173 | return -1; | |
5174 | if (ir.mod == 3) | |
5175 | { | |
5176 | if (opcode > 0xff) | |
5177 | ir.addr -= 3; | |
5178 | else | |
5179 | ir.addr -= 2; | |
5180 | opcode = opcode << 8 | ir.modrm; | |
5181 | goto no_support; | |
5182 | } | |
7ad10968 HZ |
5183 | switch (opcode) |
5184 | { | |
a38bba38 | 5185 | case 0xc4: /* les Gv */ |
425b824a | 5186 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5187 | break; |
a38bba38 | 5188 | case 0xc5: /* lds Gv */ |
425b824a | 5189 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5190 | break; |
a38bba38 | 5191 | case 0x0fb2: /* lss Gv */ |
425b824a | 5192 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5193 | break; |
a38bba38 | 5194 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5195 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5196 | break; |
a38bba38 | 5197 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5198 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5199 | break; |
5200 | } | |
425b824a | 5201 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
5202 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5203 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5204 | break; |
5205 | ||
a38bba38 | 5206 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5207 | case 0xc1: |
5208 | case 0xd0: | |
5209 | case 0xd1: | |
5210 | case 0xd2: | |
5211 | case 0xd3: | |
5212 | if ((opcode & 1) == 0) | |
5213 | ir.ot = OT_BYTE; | |
5214 | else | |
5215 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5216 | if (i386_record_modrm (&ir)) |
5217 | return -1; | |
7ad10968 HZ |
5218 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5219 | { | |
5220 | if (i386_record_lea_modrm (&ir)) | |
5221 | return -1; | |
5222 | } | |
5223 | else | |
5224 | { | |
cf648174 HZ |
5225 | ir.rm |= ir.rex_b; |
5226 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5227 | ir.rm &= 0x3; |
cf648174 | 5228 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5229 | } |
cf648174 | 5230 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5231 | break; |
5232 | ||
5233 | case 0x0fa4: | |
5234 | case 0x0fa5: | |
5235 | case 0x0fac: | |
5236 | case 0x0fad: | |
5237 | if (i386_record_modrm (&ir)) | |
5238 | return -1; | |
5239 | if (ir.mod == 3) | |
5240 | { | |
5241 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
5242 | return -1; | |
5243 | } | |
5244 | else | |
5245 | { | |
5246 | if (i386_record_lea_modrm (&ir)) | |
5247 | return -1; | |
5248 | } | |
5249 | break; | |
5250 | ||
a38bba38 | 5251 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5252 | case 0xd9: |
5253 | case 0xda: | |
5254 | case 0xdb: | |
5255 | case 0xdc: | |
5256 | case 0xdd: | |
5257 | case 0xde: | |
5258 | case 0xdf: | |
5259 | if (i386_record_modrm (&ir)) | |
5260 | return -1; | |
5261 | ir.reg |= ((opcode & 7) << 3); | |
5262 | if (ir.mod != 3) | |
5263 | { | |
1777feb0 | 5264 | /* Memory. */ |
955db0c0 | 5265 | uint64_t addr64; |
7ad10968 | 5266 | |
955db0c0 | 5267 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
5268 | return -1; |
5269 | switch (ir.reg) | |
5270 | { | |
7ad10968 | 5271 | case 0x02: |
0289bdd7 MS |
5272 | case 0x12: |
5273 | case 0x22: | |
5274 | case 0x32: | |
5275 | /* For fcom, ficom nothing to do. */ | |
5276 | break; | |
7ad10968 | 5277 | case 0x03: |
0289bdd7 MS |
5278 | case 0x13: |
5279 | case 0x23: | |
5280 | case 0x33: | |
5281 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5282 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5283 | return -1; | |
5284 | break; | |
5285 | case 0x00: | |
5286 | case 0x01: | |
7ad10968 HZ |
5287 | case 0x04: |
5288 | case 0x05: | |
5289 | case 0x06: | |
5290 | case 0x07: | |
5291 | case 0x10: | |
5292 | case 0x11: | |
7ad10968 HZ |
5293 | case 0x14: |
5294 | case 0x15: | |
5295 | case 0x16: | |
5296 | case 0x17: | |
5297 | case 0x20: | |
5298 | case 0x21: | |
7ad10968 HZ |
5299 | case 0x24: |
5300 | case 0x25: | |
5301 | case 0x26: | |
5302 | case 0x27: | |
5303 | case 0x30: | |
5304 | case 0x31: | |
7ad10968 HZ |
5305 | case 0x34: |
5306 | case 0x35: | |
5307 | case 0x36: | |
5308 | case 0x37: | |
0289bdd7 MS |
5309 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5310 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5311 | of code, always affects st(0) register. */ | |
5312 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5313 | return -1; | |
7ad10968 HZ |
5314 | break; |
5315 | case 0x08: | |
5316 | case 0x0a: | |
5317 | case 0x0b: | |
5318 | case 0x18: | |
5319 | case 0x19: | |
5320 | case 0x1a: | |
5321 | case 0x1b: | |
0289bdd7 | 5322 | case 0x1d: |
7ad10968 HZ |
5323 | case 0x28: |
5324 | case 0x29: | |
5325 | case 0x2a: | |
5326 | case 0x2b: | |
5327 | case 0x38: | |
5328 | case 0x39: | |
5329 | case 0x3a: | |
5330 | case 0x3b: | |
0289bdd7 MS |
5331 | case 0x3c: |
5332 | case 0x3d: | |
7ad10968 HZ |
5333 | switch (ir.reg & 7) |
5334 | { | |
5335 | case 0: | |
0289bdd7 MS |
5336 | /* Handling fld, fild. */ |
5337 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5338 | return -1; | |
7ad10968 HZ |
5339 | break; |
5340 | case 1: | |
5341 | switch (ir.reg >> 4) | |
5342 | { | |
5343 | case 0: | |
955db0c0 | 5344 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
5345 | return -1; |
5346 | break; | |
5347 | case 2: | |
955db0c0 | 5348 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
5349 | return -1; |
5350 | break; | |
5351 | case 3: | |
0289bdd7 | 5352 | break; |
7ad10968 | 5353 | default: |
955db0c0 | 5354 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5355 | return -1; |
5356 | break; | |
5357 | } | |
5358 | break; | |
5359 | default: | |
5360 | switch (ir.reg >> 4) | |
5361 | { | |
5362 | case 0: | |
955db0c0 | 5363 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
5364 | return -1; |
5365 | if (3 == (ir.reg & 7)) | |
5366 | { | |
5367 | /* For fstp m32fp. */ | |
5368 | if (i386_record_floats (gdbarch, &ir, | |
5369 | I386_SAVE_FPU_REGS)) | |
5370 | return -1; | |
5371 | } | |
5372 | break; | |
7ad10968 | 5373 | case 1: |
955db0c0 | 5374 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 5375 | return -1; |
0289bdd7 MS |
5376 | if ((3 == (ir.reg & 7)) |
5377 | || (5 == (ir.reg & 7)) | |
5378 | || (7 == (ir.reg & 7))) | |
5379 | { | |
5380 | /* For fstp insn. */ | |
5381 | if (i386_record_floats (gdbarch, &ir, | |
5382 | I386_SAVE_FPU_REGS)) | |
5383 | return -1; | |
5384 | } | |
7ad10968 HZ |
5385 | break; |
5386 | case 2: | |
955db0c0 | 5387 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5388 | return -1; |
0289bdd7 MS |
5389 | if (3 == (ir.reg & 7)) |
5390 | { | |
5391 | /* For fstp m64fp. */ | |
5392 | if (i386_record_floats (gdbarch, &ir, | |
5393 | I386_SAVE_FPU_REGS)) | |
5394 | return -1; | |
5395 | } | |
7ad10968 HZ |
5396 | break; |
5397 | case 3: | |
0289bdd7 MS |
5398 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
5399 | { | |
5400 | /* For fistp, fbld, fild, fbstp. */ | |
5401 | if (i386_record_floats (gdbarch, &ir, | |
5402 | I386_SAVE_FPU_REGS)) | |
5403 | return -1; | |
5404 | } | |
5405 | /* Fall through */ | |
7ad10968 | 5406 | default: |
955db0c0 | 5407 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5408 | return -1; |
5409 | break; | |
5410 | } | |
5411 | break; | |
5412 | } | |
5413 | break; | |
5414 | case 0x0c: | |
0289bdd7 MS |
5415 | /* Insn fldenv. */ |
5416 | if (i386_record_floats (gdbarch, &ir, | |
5417 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5418 | return -1; | |
5419 | break; | |
7ad10968 | 5420 | case 0x0d: |
0289bdd7 MS |
5421 | /* Insn fldcw. */ |
5422 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
5423 | return -1; | |
5424 | break; | |
7ad10968 | 5425 | case 0x2c: |
0289bdd7 MS |
5426 | /* Insn frstor. */ |
5427 | if (i386_record_floats (gdbarch, &ir, | |
5428 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5429 | return -1; | |
7ad10968 HZ |
5430 | break; |
5431 | case 0x0e: | |
5432 | if (ir.dflag) | |
5433 | { | |
955db0c0 | 5434 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
5435 | return -1; |
5436 | } | |
5437 | else | |
5438 | { | |
955db0c0 | 5439 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
5440 | return -1; |
5441 | } | |
5442 | break; | |
5443 | case 0x0f: | |
5444 | case 0x2f: | |
955db0c0 | 5445 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5446 | return -1; |
0289bdd7 MS |
5447 | /* Insn fstp, fbstp. */ |
5448 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5449 | return -1; | |
7ad10968 HZ |
5450 | break; |
5451 | case 0x1f: | |
5452 | case 0x3e: | |
955db0c0 | 5453 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
5454 | return -1; |
5455 | break; | |
5456 | case 0x2e: | |
5457 | if (ir.dflag) | |
5458 | { | |
955db0c0 | 5459 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 5460 | return -1; |
955db0c0 | 5461 | addr64 += 28; |
7ad10968 HZ |
5462 | } |
5463 | else | |
5464 | { | |
955db0c0 | 5465 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 5466 | return -1; |
955db0c0 | 5467 | addr64 += 14; |
7ad10968 | 5468 | } |
955db0c0 | 5469 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 5470 | return -1; |
0289bdd7 MS |
5471 | /* Insn fsave. */ |
5472 | if (i386_record_floats (gdbarch, &ir, | |
5473 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5474 | return -1; | |
7ad10968 HZ |
5475 | break; |
5476 | case 0x3f: | |
955db0c0 | 5477 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5478 | return -1; |
0289bdd7 MS |
5479 | /* Insn fistp. */ |
5480 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5481 | return -1; | |
7ad10968 HZ |
5482 | break; |
5483 | default: | |
5484 | ir.addr -= 2; | |
5485 | opcode = opcode << 8 | ir.modrm; | |
5486 | goto no_support; | |
5487 | break; | |
5488 | } | |
5489 | } | |
0289bdd7 MS |
5490 | /* Opcode is an extension of modR/M byte. */ |
5491 | else | |
5492 | { | |
5493 | switch (opcode) | |
5494 | { | |
5495 | case 0xd8: | |
5496 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5497 | return -1; | |
5498 | break; | |
5499 | case 0xd9: | |
5500 | if (0x0c == (ir.modrm >> 4)) | |
5501 | { | |
5502 | if ((ir.modrm & 0x0f) <= 7) | |
5503 | { | |
5504 | if (i386_record_floats (gdbarch, &ir, | |
5505 | I386_SAVE_FPU_REGS)) | |
5506 | return -1; | |
5507 | } | |
5508 | else | |
5509 | { | |
5510 | if (i386_record_floats (gdbarch, &ir, | |
5511 | I387_ST0_REGNUM (tdep))) | |
5512 | return -1; | |
5513 | /* If only st(0) is changing, then we have already | |
5514 | recorded. */ | |
5515 | if ((ir.modrm & 0x0f) - 0x08) | |
5516 | { | |
5517 | if (i386_record_floats (gdbarch, &ir, | |
5518 | I387_ST0_REGNUM (tdep) + | |
5519 | ((ir.modrm & 0x0f) - 0x08))) | |
5520 | return -1; | |
5521 | } | |
5522 | } | |
5523 | } | |
5524 | else | |
5525 | { | |
5526 | switch (ir.modrm) | |
5527 | { | |
5528 | case 0xe0: | |
5529 | case 0xe1: | |
5530 | case 0xf0: | |
5531 | case 0xf5: | |
5532 | case 0xf8: | |
5533 | case 0xfa: | |
5534 | case 0xfc: | |
5535 | case 0xfe: | |
5536 | case 0xff: | |
5537 | if (i386_record_floats (gdbarch, &ir, | |
5538 | I387_ST0_REGNUM (tdep))) | |
5539 | return -1; | |
5540 | break; | |
5541 | case 0xf1: | |
5542 | case 0xf2: | |
5543 | case 0xf3: | |
5544 | case 0xf4: | |
5545 | case 0xf6: | |
5546 | case 0xf7: | |
5547 | case 0xe8: | |
5548 | case 0xe9: | |
5549 | case 0xea: | |
5550 | case 0xeb: | |
5551 | case 0xec: | |
5552 | case 0xed: | |
5553 | case 0xee: | |
5554 | case 0xf9: | |
5555 | case 0xfb: | |
5556 | if (i386_record_floats (gdbarch, &ir, | |
5557 | I386_SAVE_FPU_REGS)) | |
5558 | return -1; | |
5559 | break; | |
5560 | case 0xfd: | |
5561 | if (i386_record_floats (gdbarch, &ir, | |
5562 | I387_ST0_REGNUM (tdep))) | |
5563 | return -1; | |
5564 | if (i386_record_floats (gdbarch, &ir, | |
5565 | I387_ST0_REGNUM (tdep) + 1)) | |
5566 | return -1; | |
5567 | break; | |
5568 | } | |
5569 | } | |
5570 | break; | |
5571 | case 0xda: | |
5572 | if (0xe9 == ir.modrm) | |
5573 | { | |
5574 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5575 | return -1; | |
5576 | } | |
5577 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5578 | { | |
5579 | if (i386_record_floats (gdbarch, &ir, | |
5580 | I387_ST0_REGNUM (tdep))) | |
5581 | return -1; | |
5582 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5583 | { | |
5584 | if (i386_record_floats (gdbarch, &ir, | |
5585 | I387_ST0_REGNUM (tdep) + | |
5586 | (ir.modrm & 0x0f))) | |
5587 | return -1; | |
5588 | } | |
5589 | else if ((ir.modrm & 0x0f) - 0x08) | |
5590 | { | |
5591 | if (i386_record_floats (gdbarch, &ir, | |
5592 | I387_ST0_REGNUM (tdep) + | |
5593 | ((ir.modrm & 0x0f) - 0x08))) | |
5594 | return -1; | |
5595 | } | |
5596 | } | |
5597 | break; | |
5598 | case 0xdb: | |
5599 | if (0xe3 == ir.modrm) | |
5600 | { | |
5601 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
5602 | return -1; | |
5603 | } | |
5604 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5605 | { | |
5606 | if (i386_record_floats (gdbarch, &ir, | |
5607 | I387_ST0_REGNUM (tdep))) | |
5608 | return -1; | |
5609 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5610 | { | |
5611 | if (i386_record_floats (gdbarch, &ir, | |
5612 | I387_ST0_REGNUM (tdep) + | |
5613 | (ir.modrm & 0x0f))) | |
5614 | return -1; | |
5615 | } | |
5616 | else if ((ir.modrm & 0x0f) - 0x08) | |
5617 | { | |
5618 | if (i386_record_floats (gdbarch, &ir, | |
5619 | I387_ST0_REGNUM (tdep) + | |
5620 | ((ir.modrm & 0x0f) - 0x08))) | |
5621 | return -1; | |
5622 | } | |
5623 | } | |
5624 | break; | |
5625 | case 0xdc: | |
5626 | if ((0x0c == ir.modrm >> 4) | |
5627 | || (0x0d == ir.modrm >> 4) | |
5628 | || (0x0f == ir.modrm >> 4)) | |
5629 | { | |
5630 | if ((ir.modrm & 0x0f) <= 7) | |
5631 | { | |
5632 | if (i386_record_floats (gdbarch, &ir, | |
5633 | I387_ST0_REGNUM (tdep) + | |
5634 | (ir.modrm & 0x0f))) | |
5635 | return -1; | |
5636 | } | |
5637 | else | |
5638 | { | |
5639 | if (i386_record_floats (gdbarch, &ir, | |
5640 | I387_ST0_REGNUM (tdep) + | |
5641 | ((ir.modrm & 0x0f) - 0x08))) | |
5642 | return -1; | |
5643 | } | |
5644 | } | |
5645 | break; | |
5646 | case 0xdd: | |
5647 | if (0x0c == ir.modrm >> 4) | |
5648 | { | |
5649 | if (i386_record_floats (gdbarch, &ir, | |
5650 | I387_FTAG_REGNUM (tdep))) | |
5651 | return -1; | |
5652 | } | |
5653 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5654 | { | |
5655 | if ((ir.modrm & 0x0f) <= 7) | |
5656 | { | |
5657 | if (i386_record_floats (gdbarch, &ir, | |
5658 | I387_ST0_REGNUM (tdep) + | |
5659 | (ir.modrm & 0x0f))) | |
5660 | return -1; | |
5661 | } | |
5662 | else | |
5663 | { | |
5664 | if (i386_record_floats (gdbarch, &ir, | |
5665 | I386_SAVE_FPU_REGS)) | |
5666 | return -1; | |
5667 | } | |
5668 | } | |
5669 | break; | |
5670 | case 0xde: | |
5671 | if ((0x0c == ir.modrm >> 4) | |
5672 | || (0x0e == ir.modrm >> 4) | |
5673 | || (0x0f == ir.modrm >> 4) | |
5674 | || (0xd9 == ir.modrm)) | |
5675 | { | |
5676 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5677 | return -1; | |
5678 | } | |
5679 | break; | |
5680 | case 0xdf: | |
5681 | if (0xe0 == ir.modrm) | |
5682 | { | |
5683 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
5684 | return -1; | |
5685 | } | |
5686 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5687 | { | |
5688 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5689 | return -1; | |
5690 | } | |
5691 | break; | |
5692 | } | |
5693 | } | |
7ad10968 | 5694 | break; |
7ad10968 | 5695 | /* string ops */ |
a38bba38 | 5696 | case 0xa4: /* movsS */ |
7ad10968 | 5697 | case 0xa5: |
a38bba38 | 5698 | case 0xaa: /* stosS */ |
7ad10968 | 5699 | case 0xab: |
a38bba38 | 5700 | case 0x6c: /* insS */ |
7ad10968 | 5701 | case 0x6d: |
cf648174 | 5702 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5703 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5704 | &addr); |
5705 | if (addr) | |
cf648174 | 5706 | { |
77d7dc92 HZ |
5707 | ULONGEST es, ds; |
5708 | ||
5709 | if ((opcode & 1) == 0) | |
5710 | ir.ot = OT_BYTE; | |
5711 | else | |
5712 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5713 | regcache_raw_read_unsigned (ir.regcache, |
5714 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5715 | &addr); |
77d7dc92 | 5716 | |
d7877f7e HZ |
5717 | regcache_raw_read_unsigned (ir.regcache, |
5718 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5719 | &es); | |
5720 | regcache_raw_read_unsigned (ir.regcache, | |
5721 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5722 | &ds); | |
5723 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5724 | { |
5725 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
bb08c432 HZ |
5726 | if (record_memory_query) |
5727 | { | |
5728 | int q; | |
5729 | ||
5730 | target_terminal_ours (); | |
5731 | q = yquery (_("\ | |
5732 | Process record ignores the memory change of instruction at address %s\n\ | |
5733 | because it can't get the value of the segment register.\n\ | |
5734 | Do you want to stop the program?"), | |
5735 | paddress (gdbarch, ir.orig_addr)); | |
5736 | target_terminal_inferior (); | |
5737 | if (q) | |
5738 | return -1; | |
5739 | } | |
df61f520 HZ |
5740 | } |
5741 | else | |
5742 | { | |
648d0c8b | 5743 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5744 | return -1; |
77d7dc92 HZ |
5745 | } |
5746 | ||
5747 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5748 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
5749 | if (opcode == 0xa4 || opcode == 0xa5) |
5750 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5751 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5752 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5753 | } | |
cf648174 | 5754 | break; |
7ad10968 | 5755 | |
a38bba38 | 5756 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
5757 | case 0xa7: |
5758 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5759 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5760 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5761 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5762 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5763 | break; |
5764 | ||
a38bba38 | 5765 | case 0xac: /* lodsS */ |
7ad10968 | 5766 | case 0xad: |
cf648174 HZ |
5767 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5768 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5769 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5770 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5771 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5772 | break; |
5773 | ||
a38bba38 | 5774 | case 0xae: /* scasS */ |
7ad10968 | 5775 | case 0xaf: |
cf648174 | 5776 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 5777 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5778 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5779 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5780 | break; |
5781 | ||
a38bba38 | 5782 | case 0x6e: /* outsS */ |
cf648174 HZ |
5783 | case 0x6f: |
5784 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5785 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5786 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5787 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5788 | break; |
5789 | ||
a38bba38 | 5790 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
5791 | case 0xe5: |
5792 | case 0xec: | |
5793 | case 0xed: | |
cf648174 HZ |
5794 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5795 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5796 | break; |
5797 | ||
5798 | case 0xe6: | |
5799 | case 0xe7: | |
5800 | case 0xee: | |
5801 | case 0xef: | |
5802 | break; | |
5803 | ||
5804 | /* control */ | |
a38bba38 MS |
5805 | case 0xc2: /* ret im */ |
5806 | case 0xc3: /* ret */ | |
cf648174 HZ |
5807 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5808 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5809 | break; | |
5810 | ||
a38bba38 MS |
5811 | case 0xca: /* lret im */ |
5812 | case 0xcb: /* lret */ | |
5813 | case 0xcf: /* iret */ | |
cf648174 HZ |
5814 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
5815 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5816 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5817 | break; |
5818 | ||
a38bba38 | 5819 | case 0xe8: /* call im */ |
cf648174 HZ |
5820 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5821 | ir.dflag = 2; | |
5822 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5823 | return -1; | |
7ad10968 HZ |
5824 | break; |
5825 | ||
a38bba38 | 5826 | case 0x9a: /* lcall im */ |
cf648174 HZ |
5827 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5828 | { | |
5829 | ir.addr -= 1; | |
5830 | goto no_support; | |
5831 | } | |
5832 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
5833 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5834 | return -1; | |
7ad10968 HZ |
5835 | break; |
5836 | ||
a38bba38 MS |
5837 | case 0xe9: /* jmp im */ |
5838 | case 0xea: /* ljmp im */ | |
5839 | case 0xeb: /* jmp Jb */ | |
5840 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
5841 | case 0x71: |
5842 | case 0x72: | |
5843 | case 0x73: | |
5844 | case 0x74: | |
5845 | case 0x75: | |
5846 | case 0x76: | |
5847 | case 0x77: | |
5848 | case 0x78: | |
5849 | case 0x79: | |
5850 | case 0x7a: | |
5851 | case 0x7b: | |
5852 | case 0x7c: | |
5853 | case 0x7d: | |
5854 | case 0x7e: | |
5855 | case 0x7f: | |
a38bba38 | 5856 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
5857 | case 0x0f81: |
5858 | case 0x0f82: | |
5859 | case 0x0f83: | |
5860 | case 0x0f84: | |
5861 | case 0x0f85: | |
5862 | case 0x0f86: | |
5863 | case 0x0f87: | |
5864 | case 0x0f88: | |
5865 | case 0x0f89: | |
5866 | case 0x0f8a: | |
5867 | case 0x0f8b: | |
5868 | case 0x0f8c: | |
5869 | case 0x0f8d: | |
5870 | case 0x0f8e: | |
5871 | case 0x0f8f: | |
5872 | break; | |
5873 | ||
a38bba38 | 5874 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
5875 | case 0x0f91: |
5876 | case 0x0f92: | |
5877 | case 0x0f93: | |
5878 | case 0x0f94: | |
5879 | case 0x0f95: | |
5880 | case 0x0f96: | |
5881 | case 0x0f97: | |
5882 | case 0x0f98: | |
5883 | case 0x0f99: | |
5884 | case 0x0f9a: | |
5885 | case 0x0f9b: | |
5886 | case 0x0f9c: | |
5887 | case 0x0f9d: | |
5888 | case 0x0f9e: | |
5889 | case 0x0f9f: | |
cf648174 | 5890 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5891 | ir.ot = OT_BYTE; |
5892 | if (i386_record_modrm (&ir)) | |
5893 | return -1; | |
5894 | if (ir.mod == 3) | |
cf648174 HZ |
5895 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
5896 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
5897 | else |
5898 | { | |
5899 | if (i386_record_lea_modrm (&ir)) | |
5900 | return -1; | |
5901 | } | |
5902 | break; | |
5903 | ||
a38bba38 | 5904 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
5905 | case 0x0f41: |
5906 | case 0x0f42: | |
5907 | case 0x0f43: | |
5908 | case 0x0f44: | |
5909 | case 0x0f45: | |
5910 | case 0x0f46: | |
5911 | case 0x0f47: | |
5912 | case 0x0f48: | |
5913 | case 0x0f49: | |
5914 | case 0x0f4a: | |
5915 | case 0x0f4b: | |
5916 | case 0x0f4c: | |
5917 | case 0x0f4d: | |
5918 | case 0x0f4e: | |
5919 | case 0x0f4f: | |
5920 | if (i386_record_modrm (&ir)) | |
5921 | return -1; | |
cf648174 | 5922 | ir.reg |= rex_r; |
7ad10968 HZ |
5923 | if (ir.dflag == OT_BYTE) |
5924 | ir.reg &= 0x3; | |
cf648174 | 5925 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5926 | break; |
5927 | ||
5928 | /* flags */ | |
a38bba38 | 5929 | case 0x9c: /* pushf */ |
cf648174 HZ |
5930 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5931 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
5932 | ir.dflag = 2; | |
5933 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5934 | return -1; | |
7ad10968 HZ |
5935 | break; |
5936 | ||
a38bba38 | 5937 | case 0x9d: /* popf */ |
cf648174 HZ |
5938 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5939 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5940 | break; |
5941 | ||
a38bba38 | 5942 | case 0x9e: /* sahf */ |
cf648174 HZ |
5943 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5944 | { | |
5945 | ir.addr -= 1; | |
5946 | goto no_support; | |
5947 | } | |
d3f323f3 | 5948 | /* FALLTHROUGH */ |
a38bba38 MS |
5949 | case 0xf5: /* cmc */ |
5950 | case 0xf8: /* clc */ | |
5951 | case 0xf9: /* stc */ | |
5952 | case 0xfc: /* cld */ | |
5953 | case 0xfd: /* std */ | |
cf648174 | 5954 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5955 | break; |
5956 | ||
a38bba38 | 5957 | case 0x9f: /* lahf */ |
cf648174 HZ |
5958 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5959 | { | |
5960 | ir.addr -= 1; | |
5961 | goto no_support; | |
5962 | } | |
5963 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5964 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5965 | break; |
5966 | ||
5967 | /* bit operations */ | |
a38bba38 | 5968 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
5969 | ir.ot = ir.dflag + OT_WORD; |
5970 | if (i386_record_modrm (&ir)) | |
5971 | return -1; | |
5972 | if (ir.reg < 4) | |
5973 | { | |
cf648174 | 5974 | ir.addr -= 2; |
7ad10968 HZ |
5975 | opcode = opcode << 8 | ir.modrm; |
5976 | goto no_support; | |
5977 | } | |
cf648174 | 5978 | if (ir.reg != 4) |
7ad10968 | 5979 | { |
cf648174 HZ |
5980 | if (ir.mod == 3) |
5981 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
5982 | else |
5983 | { | |
cf648174 | 5984 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
5985 | return -1; |
5986 | } | |
5987 | } | |
cf648174 | 5988 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5989 | break; |
5990 | ||
a38bba38 | 5991 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5992 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5993 | break; | |
5994 | ||
a38bba38 MS |
5995 | case 0x0fab: /* bts */ |
5996 | case 0x0fb3: /* btr */ | |
5997 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5998 | ir.ot = ir.dflag + OT_WORD; |
5999 | if (i386_record_modrm (&ir)) | |
6000 | return -1; | |
6001 | if (ir.mod == 3) | |
6002 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
6003 | else | |
6004 | { | |
955db0c0 MS |
6005 | uint64_t addr64; |
6006 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6007 | return -1; |
6008 | regcache_raw_read_unsigned (ir.regcache, | |
6009 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6010 | &addr); |
cf648174 HZ |
6011 | switch (ir.dflag) |
6012 | { | |
6013 | case 0: | |
648d0c8b | 6014 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6015 | break; |
6016 | case 1: | |
648d0c8b | 6017 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6018 | break; |
6019 | case 2: | |
648d0c8b | 6020 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6021 | break; |
6022 | } | |
955db0c0 | 6023 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6024 | return -1; |
6025 | if (i386_record_lea_modrm (&ir)) | |
6026 | return -1; | |
6027 | } | |
6028 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6029 | break; |
6030 | ||
a38bba38 MS |
6031 | case 0x0fbc: /* bsf */ |
6032 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
6033 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6034 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6035 | break; |
6036 | ||
6037 | /* bcd */ | |
a38bba38 MS |
6038 | case 0x27: /* daa */ |
6039 | case 0x2f: /* das */ | |
6040 | case 0x37: /* aaa */ | |
6041 | case 0x3f: /* aas */ | |
6042 | case 0xd4: /* aam */ | |
6043 | case 0xd5: /* aad */ | |
cf648174 HZ |
6044 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6045 | { | |
6046 | ir.addr -= 1; | |
6047 | goto no_support; | |
6048 | } | |
6049 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6050 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6051 | break; |
6052 | ||
6053 | /* misc */ | |
a38bba38 | 6054 | case 0x90: /* nop */ |
7ad10968 HZ |
6055 | if (prefixes & PREFIX_LOCK) |
6056 | { | |
6057 | ir.addr -= 1; | |
6058 | goto no_support; | |
6059 | } | |
6060 | break; | |
6061 | ||
a38bba38 | 6062 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6063 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6064 | return -1; | |
425b824a | 6065 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6066 | ir.addr++; |
6067 | goto reswitch; | |
7ad10968 HZ |
6068 | break; |
6069 | ||
7ad10968 | 6070 | /* XXX */ |
a38bba38 | 6071 | case 0xcc: /* int3 */ |
a3c4230a | 6072 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6073 | "int3.\n")); |
6074 | ir.addr -= 1; | |
6075 | goto no_support; | |
6076 | break; | |
6077 | ||
7ad10968 | 6078 | /* XXX */ |
a38bba38 | 6079 | case 0xcd: /* int */ |
7ad10968 HZ |
6080 | { |
6081 | int ret; | |
425b824a | 6082 | uint8_t interrupt; |
4ffa4fc7 PA |
6083 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6084 | return -1; | |
7ad10968 | 6085 | ir.addr++; |
425b824a | 6086 | if (interrupt != 0x80 |
a3c4230a | 6087 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6088 | { |
a3c4230a | 6089 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6090 | "instruction int 0x%02x.\n"), |
425b824a | 6091 | interrupt); |
7ad10968 HZ |
6092 | ir.addr -= 2; |
6093 | goto no_support; | |
6094 | } | |
a3c4230a | 6095 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6096 | if (ret) |
6097 | return ret; | |
6098 | } | |
6099 | break; | |
6100 | ||
7ad10968 | 6101 | /* XXX */ |
a38bba38 | 6102 | case 0xce: /* into */ |
a3c4230a | 6103 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6104 | "instruction into.\n")); |
6105 | ir.addr -= 1; | |
6106 | goto no_support; | |
6107 | break; | |
6108 | ||
a38bba38 MS |
6109 | case 0xfa: /* cli */ |
6110 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6111 | break; |
6112 | ||
a38bba38 | 6113 | case 0x62: /* bound */ |
a3c4230a | 6114 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6115 | "instruction bound.\n")); |
6116 | ir.addr -= 1; | |
6117 | goto no_support; | |
6118 | break; | |
6119 | ||
a38bba38 | 6120 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6121 | case 0x0fc9: |
6122 | case 0x0fca: | |
6123 | case 0x0fcb: | |
6124 | case 0x0fcc: | |
6125 | case 0x0fcd: | |
6126 | case 0x0fce: | |
6127 | case 0x0fcf: | |
cf648174 | 6128 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6129 | break; |
6130 | ||
a38bba38 | 6131 | case 0xd6: /* salc */ |
cf648174 HZ |
6132 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6133 | { | |
6134 | ir.addr -= 1; | |
6135 | goto no_support; | |
6136 | } | |
6137 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6138 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6139 | break; |
6140 | ||
a38bba38 MS |
6141 | case 0xe0: /* loopnz */ |
6142 | case 0xe1: /* loopz */ | |
6143 | case 0xe2: /* loop */ | |
6144 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
6145 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6146 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6147 | break; |
6148 | ||
a38bba38 | 6149 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6150 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6151 | "instruction wrmsr.\n")); |
6152 | ir.addr -= 2; | |
6153 | goto no_support; | |
6154 | break; | |
6155 | ||
a38bba38 | 6156 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6157 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6158 | "instruction rdmsr.\n")); |
6159 | ir.addr -= 2; | |
6160 | goto no_support; | |
6161 | break; | |
6162 | ||
a38bba38 | 6163 | case 0x0f31: /* rdtsc */ |
f8c4f480 HZ |
6164 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6165 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6166 | break; |
6167 | ||
a38bba38 | 6168 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6169 | { |
6170 | int ret; | |
cf648174 HZ |
6171 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6172 | { | |
6173 | ir.addr -= 2; | |
6174 | goto no_support; | |
6175 | } | |
a3c4230a | 6176 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6177 | { |
a3c4230a | 6178 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6179 | "instruction sysenter.\n")); |
6180 | ir.addr -= 2; | |
6181 | goto no_support; | |
6182 | } | |
a3c4230a | 6183 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6184 | if (ret) |
6185 | return ret; | |
6186 | } | |
6187 | break; | |
6188 | ||
a38bba38 | 6189 | case 0x0f35: /* sysexit */ |
a3c4230a | 6190 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6191 | "instruction sysexit.\n")); |
6192 | ir.addr -= 2; | |
6193 | goto no_support; | |
6194 | break; | |
6195 | ||
a38bba38 | 6196 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6197 | { |
6198 | int ret; | |
a3c4230a | 6199 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6200 | { |
a3c4230a | 6201 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6202 | "instruction syscall.\n")); |
6203 | ir.addr -= 2; | |
6204 | goto no_support; | |
6205 | } | |
a3c4230a | 6206 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6207 | if (ret) |
6208 | return ret; | |
6209 | } | |
6210 | break; | |
6211 | ||
a38bba38 | 6212 | case 0x0f07: /* sysret */ |
a3c4230a | 6213 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6214 | "instruction sysret.\n")); |
6215 | ir.addr -= 2; | |
6216 | goto no_support; | |
6217 | break; | |
6218 | ||
a38bba38 | 6219 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
6220 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6221 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6222 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6223 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6224 | break; |
6225 | ||
a38bba38 | 6226 | case 0xf4: /* hlt */ |
a3c4230a | 6227 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6228 | "instruction hlt.\n")); |
6229 | ir.addr -= 1; | |
6230 | goto no_support; | |
6231 | break; | |
6232 | ||
6233 | case 0x0f00: | |
6234 | if (i386_record_modrm (&ir)) | |
6235 | return -1; | |
6236 | switch (ir.reg) | |
6237 | { | |
a38bba38 MS |
6238 | case 0: /* sldt */ |
6239 | case 1: /* str */ | |
7ad10968 | 6240 | if (ir.mod == 3) |
cf648174 | 6241 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6242 | else |
6243 | { | |
6244 | ir.ot = OT_WORD; | |
6245 | if (i386_record_lea_modrm (&ir)) | |
6246 | return -1; | |
6247 | } | |
6248 | break; | |
a38bba38 MS |
6249 | case 2: /* lldt */ |
6250 | case 3: /* ltr */ | |
7ad10968 | 6251 | break; |
a38bba38 MS |
6252 | case 4: /* verr */ |
6253 | case 5: /* verw */ | |
cf648174 | 6254 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6255 | break; |
6256 | default: | |
6257 | ir.addr -= 3; | |
6258 | opcode = opcode << 8 | ir.modrm; | |
6259 | goto no_support; | |
6260 | break; | |
6261 | } | |
6262 | break; | |
6263 | ||
6264 | case 0x0f01: | |
6265 | if (i386_record_modrm (&ir)) | |
6266 | return -1; | |
6267 | switch (ir.reg) | |
6268 | { | |
a38bba38 | 6269 | case 0: /* sgdt */ |
7ad10968 | 6270 | { |
955db0c0 | 6271 | uint64_t addr64; |
7ad10968 HZ |
6272 | |
6273 | if (ir.mod == 3) | |
6274 | { | |
6275 | ir.addr -= 3; | |
6276 | opcode = opcode << 8 | ir.modrm; | |
6277 | goto no_support; | |
6278 | } | |
d7877f7e | 6279 | if (ir.override >= 0) |
7ad10968 | 6280 | { |
bb08c432 HZ |
6281 | if (record_memory_query) |
6282 | { | |
6283 | int q; | |
6284 | ||
6285 | target_terminal_ours (); | |
6286 | q = yquery (_("\ | |
6287 | Process record ignores the memory change of instruction at address %s\n\ | |
6288 | because it can't get the value of the segment register.\n\ | |
6289 | Do you want to stop the program?"), | |
6290 | paddress (gdbarch, ir.orig_addr)); | |
6291 | target_terminal_inferior (); | |
6292 | if (q) | |
6293 | return -1; | |
6294 | } | |
7ad10968 HZ |
6295 | } |
6296 | else | |
6297 | { | |
955db0c0 | 6298 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6299 | return -1; |
955db0c0 | 6300 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6301 | return -1; |
955db0c0 | 6302 | addr64 += 2; |
cf648174 HZ |
6303 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6304 | { | |
955db0c0 | 6305 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6306 | return -1; |
6307 | } | |
6308 | else | |
6309 | { | |
955db0c0 | 6310 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6311 | return -1; |
6312 | } | |
7ad10968 HZ |
6313 | } |
6314 | } | |
6315 | break; | |
6316 | case 1: | |
6317 | if (ir.mod == 3) | |
6318 | { | |
6319 | switch (ir.rm) | |
6320 | { | |
a38bba38 | 6321 | case 0: /* monitor */ |
7ad10968 | 6322 | break; |
a38bba38 | 6323 | case 1: /* mwait */ |
cf648174 | 6324 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6325 | break; |
6326 | default: | |
6327 | ir.addr -= 3; | |
6328 | opcode = opcode << 8 | ir.modrm; | |
6329 | goto no_support; | |
6330 | break; | |
6331 | } | |
6332 | } | |
6333 | else | |
6334 | { | |
6335 | /* sidt */ | |
d7877f7e | 6336 | if (ir.override >= 0) |
7ad10968 | 6337 | { |
bb08c432 HZ |
6338 | if (record_memory_query) |
6339 | { | |
6340 | int q; | |
6341 | ||
6342 | target_terminal_ours (); | |
6343 | q = yquery (_("\ | |
6344 | Process record ignores the memory change of instruction at address %s\n\ | |
6345 | because it can't get the value of the segment register.\n\ | |
6346 | Do you want to stop the program?"), | |
6347 | paddress (gdbarch, ir.orig_addr)); | |
6348 | target_terminal_inferior (); | |
6349 | if (q) | |
6350 | return -1; | |
6351 | } | |
7ad10968 HZ |
6352 | } |
6353 | else | |
6354 | { | |
955db0c0 | 6355 | uint64_t addr64; |
7ad10968 | 6356 | |
955db0c0 | 6357 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6358 | return -1; |
955db0c0 | 6359 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6360 | return -1; |
955db0c0 | 6361 | addr64 += 2; |
cf648174 HZ |
6362 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6363 | { | |
955db0c0 | 6364 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6365 | return -1; |
6366 | } | |
6367 | else | |
6368 | { | |
955db0c0 | 6369 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6370 | return -1; |
6371 | } | |
7ad10968 HZ |
6372 | } |
6373 | } | |
6374 | break; | |
a38bba38 | 6375 | case 2: /* lgdt */ |
3800e645 MS |
6376 | if (ir.mod == 3) |
6377 | { | |
6378 | /* xgetbv */ | |
6379 | if (ir.rm == 0) | |
6380 | { | |
6381 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6382 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6383 | break; | |
6384 | } | |
6385 | /* xsetbv */ | |
6386 | else if (ir.rm == 1) | |
6387 | break; | |
6388 | } | |
a38bba38 | 6389 | case 3: /* lidt */ |
7ad10968 HZ |
6390 | if (ir.mod == 3) |
6391 | { | |
6392 | ir.addr -= 3; | |
6393 | opcode = opcode << 8 | ir.modrm; | |
6394 | goto no_support; | |
6395 | } | |
6396 | break; | |
a38bba38 | 6397 | case 4: /* smsw */ |
7ad10968 HZ |
6398 | if (ir.mod == 3) |
6399 | { | |
cf648174 | 6400 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
6401 | return -1; |
6402 | } | |
6403 | else | |
6404 | { | |
6405 | ir.ot = OT_WORD; | |
6406 | if (i386_record_lea_modrm (&ir)) | |
6407 | return -1; | |
6408 | } | |
cf648174 | 6409 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6410 | break; |
a38bba38 | 6411 | case 6: /* lmsw */ |
cf648174 HZ |
6412 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6413 | break; | |
a38bba38 | 6414 | case 7: /* invlpg */ |
cf648174 HZ |
6415 | if (ir.mod == 3) |
6416 | { | |
6417 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
6418 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
6419 | else | |
6420 | { | |
6421 | ir.addr -= 3; | |
6422 | opcode = opcode << 8 | ir.modrm; | |
6423 | goto no_support; | |
6424 | } | |
6425 | } | |
6426 | else | |
6427 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6428 | break; | |
6429 | default: | |
6430 | ir.addr -= 3; | |
6431 | opcode = opcode << 8 | ir.modrm; | |
6432 | goto no_support; | |
7ad10968 HZ |
6433 | break; |
6434 | } | |
6435 | break; | |
6436 | ||
a38bba38 MS |
6437 | case 0x0f08: /* invd */ |
6438 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
6439 | break; |
6440 | ||
a38bba38 | 6441 | case 0x63: /* arpl */ |
7ad10968 HZ |
6442 | if (i386_record_modrm (&ir)) |
6443 | return -1; | |
cf648174 HZ |
6444 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
6445 | { | |
6446 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
6447 | ? (ir.reg | rex_r) : ir.rm); | |
6448 | } | |
7ad10968 | 6449 | else |
cf648174 HZ |
6450 | { |
6451 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
6452 | if (i386_record_lea_modrm (&ir)) | |
6453 | return -1; | |
6454 | } | |
6455 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
6456 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6457 | break; |
6458 | ||
a38bba38 MS |
6459 | case 0x0f02: /* lar */ |
6460 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
6461 | if (i386_record_modrm (&ir)) |
6462 | return -1; | |
cf648174 HZ |
6463 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6464 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6465 | break; |
6466 | ||
6467 | case 0x0f18: | |
cf648174 HZ |
6468 | if (i386_record_modrm (&ir)) |
6469 | return -1; | |
6470 | if (ir.mod == 3 && ir.reg == 3) | |
6471 | { | |
6472 | ir.addr -= 3; | |
6473 | opcode = opcode << 8 | ir.modrm; | |
6474 | goto no_support; | |
6475 | } | |
7ad10968 HZ |
6476 | break; |
6477 | ||
7ad10968 HZ |
6478 | case 0x0f19: |
6479 | case 0x0f1a: | |
6480 | case 0x0f1b: | |
6481 | case 0x0f1c: | |
6482 | case 0x0f1d: | |
6483 | case 0x0f1e: | |
6484 | case 0x0f1f: | |
a38bba38 | 6485 | /* nop (multi byte) */ |
7ad10968 HZ |
6486 | break; |
6487 | ||
a38bba38 MS |
6488 | case 0x0f20: /* mov reg, crN */ |
6489 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
6490 | if (i386_record_modrm (&ir)) |
6491 | return -1; | |
6492 | if ((ir.modrm & 0xc0) != 0xc0) | |
6493 | { | |
cf648174 | 6494 | ir.addr -= 3; |
7ad10968 HZ |
6495 | opcode = opcode << 8 | ir.modrm; |
6496 | goto no_support; | |
6497 | } | |
6498 | switch (ir.reg) | |
6499 | { | |
6500 | case 0: | |
6501 | case 2: | |
6502 | case 3: | |
6503 | case 4: | |
6504 | case 8: | |
6505 | if (opcode & 2) | |
cf648174 | 6506 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6507 | else |
cf648174 | 6508 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6509 | break; |
6510 | default: | |
cf648174 | 6511 | ir.addr -= 3; |
7ad10968 HZ |
6512 | opcode = opcode << 8 | ir.modrm; |
6513 | goto no_support; | |
6514 | break; | |
6515 | } | |
6516 | break; | |
6517 | ||
a38bba38 MS |
6518 | case 0x0f21: /* mov reg, drN */ |
6519 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
6520 | if (i386_record_modrm (&ir)) |
6521 | return -1; | |
6522 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
6523 | || ir.reg == 5 || ir.reg >= 8) | |
6524 | { | |
cf648174 | 6525 | ir.addr -= 3; |
7ad10968 HZ |
6526 | opcode = opcode << 8 | ir.modrm; |
6527 | goto no_support; | |
6528 | } | |
6529 | if (opcode & 2) | |
cf648174 | 6530 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6531 | else |
cf648174 | 6532 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6533 | break; |
6534 | ||
a38bba38 | 6535 | case 0x0f06: /* clts */ |
cf648174 | 6536 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6537 | break; |
6538 | ||
a3c4230a HZ |
6539 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
6540 | ||
6541 | case 0x0f0d: /* 3DNow! prefetch */ | |
6542 | break; | |
6543 | ||
6544 | case 0x0f0e: /* 3DNow! femms */ | |
6545 | case 0x0f77: /* emms */ | |
6546 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
6547 | goto no_support; | |
6548 | record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); | |
6549 | break; | |
6550 | ||
6551 | case 0x0f0f: /* 3DNow! data */ | |
6552 | if (i386_record_modrm (&ir)) | |
6553 | return -1; | |
4ffa4fc7 PA |
6554 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6555 | return -1; | |
a3c4230a HZ |
6556 | ir.addr++; |
6557 | switch (opcode8) | |
6558 | { | |
6559 | case 0x0c: /* 3DNow! pi2fw */ | |
6560 | case 0x0d: /* 3DNow! pi2fd */ | |
6561 | case 0x1c: /* 3DNow! pf2iw */ | |
6562 | case 0x1d: /* 3DNow! pf2id */ | |
6563 | case 0x8a: /* 3DNow! pfnacc */ | |
6564 | case 0x8e: /* 3DNow! pfpnacc */ | |
6565 | case 0x90: /* 3DNow! pfcmpge */ | |
6566 | case 0x94: /* 3DNow! pfmin */ | |
6567 | case 0x96: /* 3DNow! pfrcp */ | |
6568 | case 0x97: /* 3DNow! pfrsqrt */ | |
6569 | case 0x9a: /* 3DNow! pfsub */ | |
6570 | case 0x9e: /* 3DNow! pfadd */ | |
6571 | case 0xa0: /* 3DNow! pfcmpgt */ | |
6572 | case 0xa4: /* 3DNow! pfmax */ | |
6573 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
6574 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
6575 | case 0xaa: /* 3DNow! pfsubr */ | |
6576 | case 0xae: /* 3DNow! pfacc */ | |
6577 | case 0xb0: /* 3DNow! pfcmpeq */ | |
6578 | case 0xb4: /* 3DNow! pfmul */ | |
6579 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
6580 | case 0xb7: /* 3DNow! pmulhrw */ | |
6581 | case 0xbb: /* 3DNow! pswapd */ | |
6582 | case 0xbf: /* 3DNow! pavgusb */ | |
6583 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6584 | goto no_support_3dnow_data; | |
6585 | record_arch_list_add_reg (ir.regcache, ir.reg); | |
6586 | break; | |
6587 | ||
6588 | default: | |
6589 | no_support_3dnow_data: | |
6590 | opcode = (opcode << 8) | opcode8; | |
6591 | goto no_support; | |
6592 | break; | |
6593 | } | |
6594 | break; | |
6595 | ||
6596 | case 0x0faa: /* rsm */ | |
6597 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6598 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6599 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6600 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6601 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
6602 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6603 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
6604 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6605 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6606 | break; | |
6607 | ||
6608 | case 0x0fae: | |
6609 | if (i386_record_modrm (&ir)) | |
6610 | return -1; | |
6611 | switch(ir.reg) | |
6612 | { | |
6613 | case 0: /* fxsave */ | |
6614 | { | |
6615 | uint64_t tmpu64; | |
6616 | ||
6617 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6618 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
6619 | return -1; | |
6620 | if (record_arch_list_add_mem (tmpu64, 512)) | |
6621 | return -1; | |
6622 | } | |
6623 | break; | |
6624 | ||
6625 | case 1: /* fxrstor */ | |
6626 | { | |
6627 | int i; | |
6628 | ||
6629 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6630 | ||
6631 | for (i = I387_MM0_REGNUM (tdep); | |
6632 | i386_mmx_regnum_p (gdbarch, i); i++) | |
6633 | record_arch_list_add_reg (ir.regcache, i); | |
6634 | ||
6635 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 6636 | i386_xmm_regnum_p (gdbarch, i); i++) |
a3c4230a HZ |
6637 | record_arch_list_add_reg (ir.regcache, i); |
6638 | ||
6639 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6640 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6641 | ||
6642 | for (i = I387_ST0_REGNUM (tdep); | |
6643 | i386_fp_regnum_p (gdbarch, i); i++) | |
6644 | record_arch_list_add_reg (ir.regcache, i); | |
6645 | ||
6646 | for (i = I387_FCTRL_REGNUM (tdep); | |
6647 | i386_fpc_regnum_p (gdbarch, i); i++) | |
6648 | record_arch_list_add_reg (ir.regcache, i); | |
6649 | } | |
6650 | break; | |
6651 | ||
6652 | case 2: /* ldmxcsr */ | |
6653 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6654 | goto no_support; | |
6655 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6656 | break; | |
6657 | ||
6658 | case 3: /* stmxcsr */ | |
6659 | ir.ot = OT_LONG; | |
6660 | if (i386_record_lea_modrm (&ir)) | |
6661 | return -1; | |
6662 | break; | |
6663 | ||
6664 | case 5: /* lfence */ | |
6665 | case 6: /* mfence */ | |
6666 | case 7: /* sfence clflush */ | |
6667 | break; | |
6668 | ||
6669 | default: | |
6670 | opcode = (opcode << 8) | ir.modrm; | |
6671 | goto no_support; | |
6672 | break; | |
6673 | } | |
6674 | break; | |
6675 | ||
6676 | case 0x0fc3: /* movnti */ | |
6677 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
6678 | if (i386_record_modrm (&ir)) | |
6679 | return -1; | |
6680 | if (ir.mod == 3) | |
6681 | goto no_support; | |
6682 | ir.reg |= rex_r; | |
6683 | if (i386_record_lea_modrm (&ir)) | |
6684 | return -1; | |
6685 | break; | |
6686 | ||
6687 | /* Add prefix to opcode. */ | |
6688 | case 0x0f10: | |
6689 | case 0x0f11: | |
6690 | case 0x0f12: | |
6691 | case 0x0f13: | |
6692 | case 0x0f14: | |
6693 | case 0x0f15: | |
6694 | case 0x0f16: | |
6695 | case 0x0f17: | |
6696 | case 0x0f28: | |
6697 | case 0x0f29: | |
6698 | case 0x0f2a: | |
6699 | case 0x0f2b: | |
6700 | case 0x0f2c: | |
6701 | case 0x0f2d: | |
6702 | case 0x0f2e: | |
6703 | case 0x0f2f: | |
6704 | case 0x0f38: | |
6705 | case 0x0f39: | |
6706 | case 0x0f3a: | |
6707 | case 0x0f50: | |
6708 | case 0x0f51: | |
6709 | case 0x0f52: | |
6710 | case 0x0f53: | |
6711 | case 0x0f54: | |
6712 | case 0x0f55: | |
6713 | case 0x0f56: | |
6714 | case 0x0f57: | |
6715 | case 0x0f58: | |
6716 | case 0x0f59: | |
6717 | case 0x0f5a: | |
6718 | case 0x0f5b: | |
6719 | case 0x0f5c: | |
6720 | case 0x0f5d: | |
6721 | case 0x0f5e: | |
6722 | case 0x0f5f: | |
6723 | case 0x0f60: | |
6724 | case 0x0f61: | |
6725 | case 0x0f62: | |
6726 | case 0x0f63: | |
6727 | case 0x0f64: | |
6728 | case 0x0f65: | |
6729 | case 0x0f66: | |
6730 | case 0x0f67: | |
6731 | case 0x0f68: | |
6732 | case 0x0f69: | |
6733 | case 0x0f6a: | |
6734 | case 0x0f6b: | |
6735 | case 0x0f6c: | |
6736 | case 0x0f6d: | |
6737 | case 0x0f6e: | |
6738 | case 0x0f6f: | |
6739 | case 0x0f70: | |
6740 | case 0x0f71: | |
6741 | case 0x0f72: | |
6742 | case 0x0f73: | |
6743 | case 0x0f74: | |
6744 | case 0x0f75: | |
6745 | case 0x0f76: | |
6746 | case 0x0f7c: | |
6747 | case 0x0f7d: | |
6748 | case 0x0f7e: | |
6749 | case 0x0f7f: | |
6750 | case 0x0fb8: | |
6751 | case 0x0fc2: | |
6752 | case 0x0fc4: | |
6753 | case 0x0fc5: | |
6754 | case 0x0fc6: | |
6755 | case 0x0fd0: | |
6756 | case 0x0fd1: | |
6757 | case 0x0fd2: | |
6758 | case 0x0fd3: | |
6759 | case 0x0fd4: | |
6760 | case 0x0fd5: | |
6761 | case 0x0fd6: | |
6762 | case 0x0fd7: | |
6763 | case 0x0fd8: | |
6764 | case 0x0fd9: | |
6765 | case 0x0fda: | |
6766 | case 0x0fdb: | |
6767 | case 0x0fdc: | |
6768 | case 0x0fdd: | |
6769 | case 0x0fde: | |
6770 | case 0x0fdf: | |
6771 | case 0x0fe0: | |
6772 | case 0x0fe1: | |
6773 | case 0x0fe2: | |
6774 | case 0x0fe3: | |
6775 | case 0x0fe4: | |
6776 | case 0x0fe5: | |
6777 | case 0x0fe6: | |
6778 | case 0x0fe7: | |
6779 | case 0x0fe8: | |
6780 | case 0x0fe9: | |
6781 | case 0x0fea: | |
6782 | case 0x0feb: | |
6783 | case 0x0fec: | |
6784 | case 0x0fed: | |
6785 | case 0x0fee: | |
6786 | case 0x0fef: | |
6787 | case 0x0ff0: | |
6788 | case 0x0ff1: | |
6789 | case 0x0ff2: | |
6790 | case 0x0ff3: | |
6791 | case 0x0ff4: | |
6792 | case 0x0ff5: | |
6793 | case 0x0ff6: | |
6794 | case 0x0ff7: | |
6795 | case 0x0ff8: | |
6796 | case 0x0ff9: | |
6797 | case 0x0ffa: | |
6798 | case 0x0ffb: | |
6799 | case 0x0ffc: | |
6800 | case 0x0ffd: | |
6801 | case 0x0ffe: | |
6802 | switch (prefixes) | |
6803 | { | |
6804 | case PREFIX_REPNZ: | |
6805 | opcode |= 0xf20000; | |
6806 | break; | |
6807 | case PREFIX_DATA: | |
6808 | opcode |= 0x660000; | |
6809 | break; | |
6810 | case PREFIX_REPZ: | |
6811 | opcode |= 0xf30000; | |
6812 | break; | |
6813 | } | |
6814 | reswitch_prefix_add: | |
6815 | switch (opcode) | |
6816 | { | |
6817 | case 0x0f38: | |
6818 | case 0x660f38: | |
6819 | case 0xf20f38: | |
6820 | case 0x0f3a: | |
6821 | case 0x660f3a: | |
4ffa4fc7 PA |
6822 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6823 | return -1; | |
a3c4230a HZ |
6824 | ir.addr++; |
6825 | opcode = (uint32_t) opcode8 | opcode << 8; | |
6826 | goto reswitch_prefix_add; | |
6827 | break; | |
6828 | ||
6829 | case 0x0f10: /* movups */ | |
6830 | case 0x660f10: /* movupd */ | |
6831 | case 0xf30f10: /* movss */ | |
6832 | case 0xf20f10: /* movsd */ | |
6833 | case 0x0f12: /* movlps */ | |
6834 | case 0x660f12: /* movlpd */ | |
6835 | case 0xf30f12: /* movsldup */ | |
6836 | case 0xf20f12: /* movddup */ | |
6837 | case 0x0f14: /* unpcklps */ | |
6838 | case 0x660f14: /* unpcklpd */ | |
6839 | case 0x0f15: /* unpckhps */ | |
6840 | case 0x660f15: /* unpckhpd */ | |
6841 | case 0x0f16: /* movhps */ | |
6842 | case 0x660f16: /* movhpd */ | |
6843 | case 0xf30f16: /* movshdup */ | |
6844 | case 0x0f28: /* movaps */ | |
6845 | case 0x660f28: /* movapd */ | |
6846 | case 0x0f2a: /* cvtpi2ps */ | |
6847 | case 0x660f2a: /* cvtpi2pd */ | |
6848 | case 0xf30f2a: /* cvtsi2ss */ | |
6849 | case 0xf20f2a: /* cvtsi2sd */ | |
6850 | case 0x0f2c: /* cvttps2pi */ | |
6851 | case 0x660f2c: /* cvttpd2pi */ | |
6852 | case 0x0f2d: /* cvtps2pi */ | |
6853 | case 0x660f2d: /* cvtpd2pi */ | |
6854 | case 0x660f3800: /* pshufb */ | |
6855 | case 0x660f3801: /* phaddw */ | |
6856 | case 0x660f3802: /* phaddd */ | |
6857 | case 0x660f3803: /* phaddsw */ | |
6858 | case 0x660f3804: /* pmaddubsw */ | |
6859 | case 0x660f3805: /* phsubw */ | |
6860 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 6861 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
6862 | case 0x660f3808: /* psignb */ |
6863 | case 0x660f3809: /* psignw */ | |
6864 | case 0x660f380a: /* psignd */ | |
6865 | case 0x660f380b: /* pmulhrsw */ | |
6866 | case 0x660f3810: /* pblendvb */ | |
6867 | case 0x660f3814: /* blendvps */ | |
6868 | case 0x660f3815: /* blendvpd */ | |
6869 | case 0x660f381c: /* pabsb */ | |
6870 | case 0x660f381d: /* pabsw */ | |
6871 | case 0x660f381e: /* pabsd */ | |
6872 | case 0x660f3820: /* pmovsxbw */ | |
6873 | case 0x660f3821: /* pmovsxbd */ | |
6874 | case 0x660f3822: /* pmovsxbq */ | |
6875 | case 0x660f3823: /* pmovsxwd */ | |
6876 | case 0x660f3824: /* pmovsxwq */ | |
6877 | case 0x660f3825: /* pmovsxdq */ | |
6878 | case 0x660f3828: /* pmuldq */ | |
6879 | case 0x660f3829: /* pcmpeqq */ | |
6880 | case 0x660f382a: /* movntdqa */ | |
6881 | case 0x660f3a08: /* roundps */ | |
6882 | case 0x660f3a09: /* roundpd */ | |
6883 | case 0x660f3a0a: /* roundss */ | |
6884 | case 0x660f3a0b: /* roundsd */ | |
6885 | case 0x660f3a0c: /* blendps */ | |
6886 | case 0x660f3a0d: /* blendpd */ | |
6887 | case 0x660f3a0e: /* pblendw */ | |
6888 | case 0x660f3a0f: /* palignr */ | |
6889 | case 0x660f3a20: /* pinsrb */ | |
6890 | case 0x660f3a21: /* insertps */ | |
6891 | case 0x660f3a22: /* pinsrd pinsrq */ | |
6892 | case 0x660f3a40: /* dpps */ | |
6893 | case 0x660f3a41: /* dppd */ | |
6894 | case 0x660f3a42: /* mpsadbw */ | |
6895 | case 0x660f3a60: /* pcmpestrm */ | |
6896 | case 0x660f3a61: /* pcmpestri */ | |
6897 | case 0x660f3a62: /* pcmpistrm */ | |
6898 | case 0x660f3a63: /* pcmpistri */ | |
6899 | case 0x0f51: /* sqrtps */ | |
6900 | case 0x660f51: /* sqrtpd */ | |
6901 | case 0xf20f51: /* sqrtsd */ | |
6902 | case 0xf30f51: /* sqrtss */ | |
6903 | case 0x0f52: /* rsqrtps */ | |
6904 | case 0xf30f52: /* rsqrtss */ | |
6905 | case 0x0f53: /* rcpps */ | |
6906 | case 0xf30f53: /* rcpss */ | |
6907 | case 0x0f54: /* andps */ | |
6908 | case 0x660f54: /* andpd */ | |
6909 | case 0x0f55: /* andnps */ | |
6910 | case 0x660f55: /* andnpd */ | |
6911 | case 0x0f56: /* orps */ | |
6912 | case 0x660f56: /* orpd */ | |
6913 | case 0x0f57: /* xorps */ | |
6914 | case 0x660f57: /* xorpd */ | |
6915 | case 0x0f58: /* addps */ | |
6916 | case 0x660f58: /* addpd */ | |
6917 | case 0xf20f58: /* addsd */ | |
6918 | case 0xf30f58: /* addss */ | |
6919 | case 0x0f59: /* mulps */ | |
6920 | case 0x660f59: /* mulpd */ | |
6921 | case 0xf20f59: /* mulsd */ | |
6922 | case 0xf30f59: /* mulss */ | |
6923 | case 0x0f5a: /* cvtps2pd */ | |
6924 | case 0x660f5a: /* cvtpd2ps */ | |
6925 | case 0xf20f5a: /* cvtsd2ss */ | |
6926 | case 0xf30f5a: /* cvtss2sd */ | |
6927 | case 0x0f5b: /* cvtdq2ps */ | |
6928 | case 0x660f5b: /* cvtps2dq */ | |
6929 | case 0xf30f5b: /* cvttps2dq */ | |
6930 | case 0x0f5c: /* subps */ | |
6931 | case 0x660f5c: /* subpd */ | |
6932 | case 0xf20f5c: /* subsd */ | |
6933 | case 0xf30f5c: /* subss */ | |
6934 | case 0x0f5d: /* minps */ | |
6935 | case 0x660f5d: /* minpd */ | |
6936 | case 0xf20f5d: /* minsd */ | |
6937 | case 0xf30f5d: /* minss */ | |
6938 | case 0x0f5e: /* divps */ | |
6939 | case 0x660f5e: /* divpd */ | |
6940 | case 0xf20f5e: /* divsd */ | |
6941 | case 0xf30f5e: /* divss */ | |
6942 | case 0x0f5f: /* maxps */ | |
6943 | case 0x660f5f: /* maxpd */ | |
6944 | case 0xf20f5f: /* maxsd */ | |
6945 | case 0xf30f5f: /* maxss */ | |
6946 | case 0x660f60: /* punpcklbw */ | |
6947 | case 0x660f61: /* punpcklwd */ | |
6948 | case 0x660f62: /* punpckldq */ | |
6949 | case 0x660f63: /* packsswb */ | |
6950 | case 0x660f64: /* pcmpgtb */ | |
6951 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 6952 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
6953 | case 0x660f67: /* packuswb */ |
6954 | case 0x660f68: /* punpckhbw */ | |
6955 | case 0x660f69: /* punpckhwd */ | |
6956 | case 0x660f6a: /* punpckhdq */ | |
6957 | case 0x660f6b: /* packssdw */ | |
6958 | case 0x660f6c: /* punpcklqdq */ | |
6959 | case 0x660f6d: /* punpckhqdq */ | |
6960 | case 0x660f6e: /* movd */ | |
6961 | case 0x660f6f: /* movdqa */ | |
6962 | case 0xf30f6f: /* movdqu */ | |
6963 | case 0x660f70: /* pshufd */ | |
6964 | case 0xf20f70: /* pshuflw */ | |
6965 | case 0xf30f70: /* pshufhw */ | |
6966 | case 0x660f74: /* pcmpeqb */ | |
6967 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 6968 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
6969 | case 0x660f7c: /* haddpd */ |
6970 | case 0xf20f7c: /* haddps */ | |
6971 | case 0x660f7d: /* hsubpd */ | |
6972 | case 0xf20f7d: /* hsubps */ | |
6973 | case 0xf30f7e: /* movq */ | |
6974 | case 0x0fc2: /* cmpps */ | |
6975 | case 0x660fc2: /* cmppd */ | |
6976 | case 0xf20fc2: /* cmpsd */ | |
6977 | case 0xf30fc2: /* cmpss */ | |
6978 | case 0x660fc4: /* pinsrw */ | |
6979 | case 0x0fc6: /* shufps */ | |
6980 | case 0x660fc6: /* shufpd */ | |
6981 | case 0x660fd0: /* addsubpd */ | |
6982 | case 0xf20fd0: /* addsubps */ | |
6983 | case 0x660fd1: /* psrlw */ | |
6984 | case 0x660fd2: /* psrld */ | |
6985 | case 0x660fd3: /* psrlq */ | |
6986 | case 0x660fd4: /* paddq */ | |
6987 | case 0x660fd5: /* pmullw */ | |
6988 | case 0xf30fd6: /* movq2dq */ | |
6989 | case 0x660fd8: /* psubusb */ | |
6990 | case 0x660fd9: /* psubusw */ | |
6991 | case 0x660fda: /* pminub */ | |
6992 | case 0x660fdb: /* pand */ | |
6993 | case 0x660fdc: /* paddusb */ | |
6994 | case 0x660fdd: /* paddusw */ | |
6995 | case 0x660fde: /* pmaxub */ | |
6996 | case 0x660fdf: /* pandn */ | |
6997 | case 0x660fe0: /* pavgb */ | |
6998 | case 0x660fe1: /* psraw */ | |
6999 | case 0x660fe2: /* psrad */ | |
7000 | case 0x660fe3: /* pavgw */ | |
7001 | case 0x660fe4: /* pmulhuw */ | |
7002 | case 0x660fe5: /* pmulhw */ | |
7003 | case 0x660fe6: /* cvttpd2dq */ | |
7004 | case 0xf20fe6: /* cvtpd2dq */ | |
7005 | case 0xf30fe6: /* cvtdq2pd */ | |
7006 | case 0x660fe8: /* psubsb */ | |
7007 | case 0x660fe9: /* psubsw */ | |
7008 | case 0x660fea: /* pminsw */ | |
7009 | case 0x660feb: /* por */ | |
7010 | case 0x660fec: /* paddsb */ | |
7011 | case 0x660fed: /* paddsw */ | |
7012 | case 0x660fee: /* pmaxsw */ | |
7013 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7014 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7015 | case 0x660ff1: /* psllw */ |
7016 | case 0x660ff2: /* pslld */ | |
7017 | case 0x660ff3: /* psllq */ | |
7018 | case 0x660ff4: /* pmuludq */ | |
7019 | case 0x660ff5: /* pmaddwd */ | |
7020 | case 0x660ff6: /* psadbw */ | |
7021 | case 0x660ff8: /* psubb */ | |
7022 | case 0x660ff9: /* psubw */ | |
56d2815c | 7023 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7024 | case 0x660ffb: /* psubq */ |
7025 | case 0x660ffc: /* paddb */ | |
7026 | case 0x660ffd: /* paddw */ | |
56d2815c | 7027 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7028 | if (i386_record_modrm (&ir)) |
7029 | return -1; | |
7030 | ir.reg |= rex_r; | |
c131fcee | 7031 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a HZ |
7032 | goto no_support; |
7033 | record_arch_list_add_reg (ir.regcache, | |
7034 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
7035 | if ((opcode & 0xfffffffc) == 0x660f3a60) | |
7036 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7037 | break; | |
7038 | ||
7039 | case 0x0f11: /* movups */ | |
7040 | case 0x660f11: /* movupd */ | |
7041 | case 0xf30f11: /* movss */ | |
7042 | case 0xf20f11: /* movsd */ | |
7043 | case 0x0f13: /* movlps */ | |
7044 | case 0x660f13: /* movlpd */ | |
7045 | case 0x0f17: /* movhps */ | |
7046 | case 0x660f17: /* movhpd */ | |
7047 | case 0x0f29: /* movaps */ | |
7048 | case 0x660f29: /* movapd */ | |
7049 | case 0x660f3a14: /* pextrb */ | |
7050 | case 0x660f3a15: /* pextrw */ | |
7051 | case 0x660f3a16: /* pextrd pextrq */ | |
7052 | case 0x660f3a17: /* extractps */ | |
7053 | case 0x660f7f: /* movdqa */ | |
7054 | case 0xf30f7f: /* movdqu */ | |
7055 | if (i386_record_modrm (&ir)) | |
7056 | return -1; | |
7057 | if (ir.mod == 3) | |
7058 | { | |
7059 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7060 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7061 | goto no_support; | |
7062 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7063 | if (!i386_xmm_regnum_p (gdbarch, |
7064 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
7065 | goto no_support; |
7066 | record_arch_list_add_reg (ir.regcache, | |
7067 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
7068 | } | |
7069 | else | |
7070 | { | |
7071 | switch (opcode) | |
7072 | { | |
7073 | case 0x660f3a14: | |
7074 | ir.ot = OT_BYTE; | |
7075 | break; | |
7076 | case 0x660f3a15: | |
7077 | ir.ot = OT_WORD; | |
7078 | break; | |
7079 | case 0x660f3a16: | |
7080 | ir.ot = OT_LONG; | |
7081 | break; | |
7082 | case 0x660f3a17: | |
7083 | ir.ot = OT_QUAD; | |
7084 | break; | |
7085 | default: | |
7086 | ir.ot = OT_DQUAD; | |
7087 | break; | |
7088 | } | |
7089 | if (i386_record_lea_modrm (&ir)) | |
7090 | return -1; | |
7091 | } | |
7092 | break; | |
7093 | ||
7094 | case 0x0f2b: /* movntps */ | |
7095 | case 0x660f2b: /* movntpd */ | |
7096 | case 0x0fe7: /* movntq */ | |
7097 | case 0x660fe7: /* movntdq */ | |
7098 | if (ir.mod == 3) | |
7099 | goto no_support; | |
7100 | if (opcode == 0x0fe7) | |
7101 | ir.ot = OT_QUAD; | |
7102 | else | |
7103 | ir.ot = OT_DQUAD; | |
7104 | if (i386_record_lea_modrm (&ir)) | |
7105 | return -1; | |
7106 | break; | |
7107 | ||
7108 | case 0xf30f2c: /* cvttss2si */ | |
7109 | case 0xf20f2c: /* cvttsd2si */ | |
7110 | case 0xf30f2d: /* cvtss2si */ | |
7111 | case 0xf20f2d: /* cvtsd2si */ | |
7112 | case 0xf20f38f0: /* crc32 */ | |
7113 | case 0xf20f38f1: /* crc32 */ | |
7114 | case 0x0f50: /* movmskps */ | |
7115 | case 0x660f50: /* movmskpd */ | |
7116 | case 0x0fc5: /* pextrw */ | |
7117 | case 0x660fc5: /* pextrw */ | |
7118 | case 0x0fd7: /* pmovmskb */ | |
7119 | case 0x660fd7: /* pmovmskb */ | |
7120 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
7121 | break; | |
7122 | ||
7123 | case 0x0f3800: /* pshufb */ | |
7124 | case 0x0f3801: /* phaddw */ | |
7125 | case 0x0f3802: /* phaddd */ | |
7126 | case 0x0f3803: /* phaddsw */ | |
7127 | case 0x0f3804: /* pmaddubsw */ | |
7128 | case 0x0f3805: /* phsubw */ | |
7129 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7130 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7131 | case 0x0f3808: /* psignb */ |
7132 | case 0x0f3809: /* psignw */ | |
7133 | case 0x0f380a: /* psignd */ | |
7134 | case 0x0f380b: /* pmulhrsw */ | |
7135 | case 0x0f381c: /* pabsb */ | |
7136 | case 0x0f381d: /* pabsw */ | |
7137 | case 0x0f381e: /* pabsd */ | |
7138 | case 0x0f382b: /* packusdw */ | |
7139 | case 0x0f3830: /* pmovzxbw */ | |
7140 | case 0x0f3831: /* pmovzxbd */ | |
7141 | case 0x0f3832: /* pmovzxbq */ | |
7142 | case 0x0f3833: /* pmovzxwd */ | |
7143 | case 0x0f3834: /* pmovzxwq */ | |
7144 | case 0x0f3835: /* pmovzxdq */ | |
7145 | case 0x0f3837: /* pcmpgtq */ | |
7146 | case 0x0f3838: /* pminsb */ | |
7147 | case 0x0f3839: /* pminsd */ | |
7148 | case 0x0f383a: /* pminuw */ | |
7149 | case 0x0f383b: /* pminud */ | |
7150 | case 0x0f383c: /* pmaxsb */ | |
7151 | case 0x0f383d: /* pmaxsd */ | |
7152 | case 0x0f383e: /* pmaxuw */ | |
7153 | case 0x0f383f: /* pmaxud */ | |
7154 | case 0x0f3840: /* pmulld */ | |
7155 | case 0x0f3841: /* phminposuw */ | |
7156 | case 0x0f3a0f: /* palignr */ | |
7157 | case 0x0f60: /* punpcklbw */ | |
7158 | case 0x0f61: /* punpcklwd */ | |
7159 | case 0x0f62: /* punpckldq */ | |
7160 | case 0x0f63: /* packsswb */ | |
7161 | case 0x0f64: /* pcmpgtb */ | |
7162 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7163 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7164 | case 0x0f67: /* packuswb */ |
7165 | case 0x0f68: /* punpckhbw */ | |
7166 | case 0x0f69: /* punpckhwd */ | |
7167 | case 0x0f6a: /* punpckhdq */ | |
7168 | case 0x0f6b: /* packssdw */ | |
7169 | case 0x0f6e: /* movd */ | |
7170 | case 0x0f6f: /* movq */ | |
7171 | case 0x0f70: /* pshufw */ | |
7172 | case 0x0f74: /* pcmpeqb */ | |
7173 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7174 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7175 | case 0x0fc4: /* pinsrw */ |
7176 | case 0x0fd1: /* psrlw */ | |
7177 | case 0x0fd2: /* psrld */ | |
7178 | case 0x0fd3: /* psrlq */ | |
7179 | case 0x0fd4: /* paddq */ | |
7180 | case 0x0fd5: /* pmullw */ | |
7181 | case 0xf20fd6: /* movdq2q */ | |
7182 | case 0x0fd8: /* psubusb */ | |
7183 | case 0x0fd9: /* psubusw */ | |
7184 | case 0x0fda: /* pminub */ | |
7185 | case 0x0fdb: /* pand */ | |
7186 | case 0x0fdc: /* paddusb */ | |
7187 | case 0x0fdd: /* paddusw */ | |
7188 | case 0x0fde: /* pmaxub */ | |
7189 | case 0x0fdf: /* pandn */ | |
7190 | case 0x0fe0: /* pavgb */ | |
7191 | case 0x0fe1: /* psraw */ | |
7192 | case 0x0fe2: /* psrad */ | |
7193 | case 0x0fe3: /* pavgw */ | |
7194 | case 0x0fe4: /* pmulhuw */ | |
7195 | case 0x0fe5: /* pmulhw */ | |
7196 | case 0x0fe8: /* psubsb */ | |
7197 | case 0x0fe9: /* psubsw */ | |
7198 | case 0x0fea: /* pminsw */ | |
7199 | case 0x0feb: /* por */ | |
7200 | case 0x0fec: /* paddsb */ | |
7201 | case 0x0fed: /* paddsw */ | |
7202 | case 0x0fee: /* pmaxsw */ | |
7203 | case 0x0fef: /* pxor */ | |
7204 | case 0x0ff1: /* psllw */ | |
7205 | case 0x0ff2: /* pslld */ | |
7206 | case 0x0ff3: /* psllq */ | |
7207 | case 0x0ff4: /* pmuludq */ | |
7208 | case 0x0ff5: /* pmaddwd */ | |
7209 | case 0x0ff6: /* psadbw */ | |
7210 | case 0x0ff8: /* psubb */ | |
7211 | case 0x0ff9: /* psubw */ | |
56d2815c | 7212 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7213 | case 0x0ffb: /* psubq */ |
7214 | case 0x0ffc: /* paddb */ | |
7215 | case 0x0ffd: /* paddw */ | |
56d2815c | 7216 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7217 | if (i386_record_modrm (&ir)) |
7218 | return -1; | |
7219 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7220 | goto no_support; | |
7221 | record_arch_list_add_reg (ir.regcache, | |
7222 | I387_MM0_REGNUM (tdep) + ir.reg); | |
7223 | break; | |
7224 | ||
7225 | case 0x0f71: /* psllw */ | |
7226 | case 0x0f72: /* pslld */ | |
7227 | case 0x0f73: /* psllq */ | |
7228 | if (i386_record_modrm (&ir)) | |
7229 | return -1; | |
7230 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7231 | goto no_support; | |
7232 | record_arch_list_add_reg (ir.regcache, | |
7233 | I387_MM0_REGNUM (tdep) + ir.rm); | |
7234 | break; | |
7235 | ||
7236 | case 0x660f71: /* psllw */ | |
7237 | case 0x660f72: /* pslld */ | |
7238 | case 0x660f73: /* psllq */ | |
7239 | if (i386_record_modrm (&ir)) | |
7240 | return -1; | |
7241 | ir.rm |= ir.rex_b; | |
c131fcee | 7242 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
7243 | goto no_support; |
7244 | record_arch_list_add_reg (ir.regcache, | |
7245 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
7246 | break; | |
7247 | ||
7248 | case 0x0f7e: /* movd */ | |
7249 | case 0x660f7e: /* movd */ | |
7250 | if (i386_record_modrm (&ir)) | |
7251 | return -1; | |
7252 | if (ir.mod == 3) | |
7253 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7254 | else | |
7255 | { | |
7256 | if (ir.dflag == 2) | |
7257 | ir.ot = OT_QUAD; | |
7258 | else | |
7259 | ir.ot = OT_LONG; | |
7260 | if (i386_record_lea_modrm (&ir)) | |
7261 | return -1; | |
7262 | } | |
7263 | break; | |
7264 | ||
7265 | case 0x0f7f: /* movq */ | |
7266 | if (i386_record_modrm (&ir)) | |
7267 | return -1; | |
7268 | if (ir.mod == 3) | |
7269 | { | |
7270 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7271 | goto no_support; | |
7272 | record_arch_list_add_reg (ir.regcache, | |
7273 | I387_MM0_REGNUM (tdep) + ir.rm); | |
7274 | } | |
7275 | else | |
7276 | { | |
7277 | ir.ot = OT_QUAD; | |
7278 | if (i386_record_lea_modrm (&ir)) | |
7279 | return -1; | |
7280 | } | |
7281 | break; | |
7282 | ||
7283 | case 0xf30fb8: /* popcnt */ | |
7284 | if (i386_record_modrm (&ir)) | |
7285 | return -1; | |
7286 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); | |
7287 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7288 | break; | |
7289 | ||
7290 | case 0x660fd6: /* movq */ | |
7291 | if (i386_record_modrm (&ir)) | |
7292 | return -1; | |
7293 | if (ir.mod == 3) | |
7294 | { | |
7295 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7296 | if (!i386_xmm_regnum_p (gdbarch, |
7297 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
7298 | goto no_support; |
7299 | record_arch_list_add_reg (ir.regcache, | |
7300 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
7301 | } | |
7302 | else | |
7303 | { | |
7304 | ir.ot = OT_QUAD; | |
7305 | if (i386_record_lea_modrm (&ir)) | |
7306 | return -1; | |
7307 | } | |
7308 | break; | |
7309 | ||
7310 | case 0x660f3817: /* ptest */ | |
7311 | case 0x0f2e: /* ucomiss */ | |
7312 | case 0x660f2e: /* ucomisd */ | |
7313 | case 0x0f2f: /* comiss */ | |
7314 | case 0x660f2f: /* comisd */ | |
7315 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7316 | break; | |
7317 | ||
7318 | case 0x0ff7: /* maskmovq */ | |
7319 | regcache_raw_read_unsigned (ir.regcache, | |
7320 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7321 | &addr); | |
7322 | if (record_arch_list_add_mem (addr, 64)) | |
7323 | return -1; | |
7324 | break; | |
7325 | ||
7326 | case 0x660ff7: /* maskmovdqu */ | |
7327 | regcache_raw_read_unsigned (ir.regcache, | |
7328 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7329 | &addr); | |
7330 | if (record_arch_list_add_mem (addr, 128)) | |
7331 | return -1; | |
7332 | break; | |
7333 | ||
7334 | default: | |
7335 | goto no_support; | |
7336 | break; | |
7337 | } | |
7338 | break; | |
7ad10968 HZ |
7339 | |
7340 | default: | |
7ad10968 HZ |
7341 | goto no_support; |
7342 | break; | |
7343 | } | |
7344 | ||
cf648174 HZ |
7345 | /* In the future, maybe still need to deal with need_dasm. */ |
7346 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
7347 | if (record_arch_list_add_end ()) |
7348 | return -1; | |
7349 | ||
7350 | return 0; | |
7351 | ||
01fe1b41 | 7352 | no_support: |
a3c4230a HZ |
7353 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
7354 | "at address %s.\n"), | |
7355 | (unsigned int) (opcode), | |
7356 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
7357 | return -1; |
7358 | } | |
7359 | ||
cf648174 HZ |
7360 | static const int i386_record_regmap[] = |
7361 | { | |
7362 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
7363 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
7364 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7365 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
7366 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
7367 | }; | |
7368 | ||
7a697b8d | 7369 | /* Check that the given address appears suitable for a fast |
405f8e94 | 7370 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
7371 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
7372 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
7373 | middle of the tracepoint jump. On x86, it may be possible to use |
7374 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
7375 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
7376 | of instruction to replace, and 0 if not, plus an explanatory |
7377 | string. */ | |
7378 | ||
7379 | static int | |
7380 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
7381 | CORE_ADDR addr, int *isize, char **msg) | |
7382 | { | |
7383 | int len, jumplen; | |
7384 | static struct ui_file *gdb_null = NULL; | |
7385 | ||
405f8e94 SS |
7386 | /* Ask the target for the minimum instruction length supported. */ |
7387 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
7388 | ||
7389 | if (jumplen < 0) | |
7390 | { | |
7391 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
7392 | operation, assume that fast tracepoints will always be implemented | |
7393 | using 4-byte relative jumps on both x86 and x86-64. */ | |
7394 | jumplen = 5; | |
7395 | } | |
7396 | else if (jumplen == 0) | |
7397 | { | |
7398 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
7399 | returns zero, then the IPA has not loaded yet. In this case, | |
7400 | we optimistically assume that truncated 2-byte relative jumps | |
7401 | will be available on x86, and compensate later if this assumption | |
7402 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
7403 | jumps will always be used. */ | |
7404 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
7405 | } | |
7a697b8d SS |
7406 | |
7407 | /* Dummy file descriptor for the disassembler. */ | |
7408 | if (!gdb_null) | |
7409 | gdb_null = ui_file_new (); | |
7410 | ||
7411 | /* Check for fit. */ | |
7412 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 SS |
7413 | if (isize) |
7414 | *isize = len; | |
7415 | ||
7a697b8d SS |
7416 | if (len < jumplen) |
7417 | { | |
7418 | /* Return a bit of target-specific detail to add to the caller's | |
7419 | generic failure message. */ | |
7420 | if (msg) | |
1777feb0 MS |
7421 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
7422 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
7423 | len, jumplen); |
7424 | return 0; | |
7425 | } | |
405f8e94 SS |
7426 | else |
7427 | { | |
7428 | if (msg) | |
7429 | *msg = NULL; | |
7430 | return 1; | |
7431 | } | |
7a697b8d SS |
7432 | } |
7433 | ||
90884b2b L |
7434 | static int |
7435 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
7436 | struct tdesc_arch_data *tdesc_data) | |
7437 | { | |
7438 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee L |
7439 | const struct tdesc_feature *feature_core; |
7440 | const struct tdesc_feature *feature_sse, *feature_avx; | |
90884b2b L |
7441 | int i, num_regs, valid_p; |
7442 | ||
7443 | if (! tdesc_has_registers (tdesc)) | |
7444 | return 0; | |
7445 | ||
7446 | /* Get core registers. */ | |
7447 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
7448 | if (feature_core == NULL) |
7449 | return 0; | |
90884b2b L |
7450 | |
7451 | /* Get SSE registers. */ | |
c131fcee | 7452 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 7453 | |
c131fcee L |
7454 | /* Try AVX registers. */ |
7455 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
7456 | ||
90884b2b L |
7457 | valid_p = 1; |
7458 | ||
c131fcee L |
7459 | /* The XCR0 bits. */ |
7460 | if (feature_avx) | |
7461 | { | |
3a13a53b L |
7462 | /* AVX register description requires SSE register description. */ |
7463 | if (!feature_sse) | |
7464 | return 0; | |
7465 | ||
c131fcee L |
7466 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
7467 | ||
7468 | /* It may have been set by OSABI initialization function. */ | |
7469 | if (tdep->num_ymm_regs == 0) | |
7470 | { | |
7471 | tdep->ymmh_register_names = i386_ymmh_names; | |
7472 | tdep->num_ymm_regs = 8; | |
7473 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
7474 | } | |
7475 | ||
7476 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
7477 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
7478 | tdep->ymm0h_regnum + i, | |
7479 | tdep->ymmh_register_names[i]); | |
7480 | } | |
3a13a53b | 7481 | else if (feature_sse) |
c131fcee | 7482 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
7483 | else |
7484 | { | |
7485 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
7486 | tdep->num_xmm_regs = 0; | |
7487 | } | |
c131fcee | 7488 | |
90884b2b L |
7489 | num_regs = tdep->num_core_regs; |
7490 | for (i = 0; i < num_regs; i++) | |
7491 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
7492 | tdep->register_names[i]); | |
7493 | ||
3a13a53b L |
7494 | if (feature_sse) |
7495 | { | |
7496 | /* Need to include %mxcsr, so add one. */ | |
7497 | num_regs += tdep->num_xmm_regs + 1; | |
7498 | for (; i < num_regs; i++) | |
7499 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
7500 | tdep->register_names[i]); | |
7501 | } | |
90884b2b L |
7502 | |
7503 | return valid_p; | |
7504 | } | |
7505 | ||
7ad10968 HZ |
7506 | \f |
7507 | static struct gdbarch * | |
7508 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
7509 | { | |
7510 | struct gdbarch_tdep *tdep; | |
7511 | struct gdbarch *gdbarch; | |
90884b2b L |
7512 | struct tdesc_arch_data *tdesc_data; |
7513 | const struct target_desc *tdesc; | |
1ba53b71 | 7514 | int mm0_regnum; |
c131fcee | 7515 | int ymm0_regnum; |
7ad10968 HZ |
7516 | |
7517 | /* If there is already a candidate, use it. */ | |
7518 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
7519 | if (arches != NULL) | |
7520 | return arches->gdbarch; | |
7521 | ||
7522 | /* Allocate space for the new architecture. */ | |
7523 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
7524 | gdbarch = gdbarch_alloc (&info, tdep); | |
7525 | ||
7526 | /* General-purpose registers. */ | |
7527 | tdep->gregset = NULL; | |
7528 | tdep->gregset_reg_offset = NULL; | |
7529 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
7530 | tdep->sizeof_gregset = 0; | |
7531 | ||
7532 | /* Floating-point registers. */ | |
7533 | tdep->fpregset = NULL; | |
7534 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
7535 | ||
c131fcee L |
7536 | tdep->xstateregset = NULL; |
7537 | ||
7ad10968 HZ |
7538 | /* The default settings include the FPU registers, the MMX registers |
7539 | and the SSE registers. This can be overridden for a specific ABI | |
7540 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
7541 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 7542 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
7543 | |
7544 | tdep->st0_regnum = I386_ST0_REGNUM; | |
7545 | ||
7ad10968 HZ |
7546 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
7547 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
7548 | ||
7549 | tdep->jb_pc_offset = -1; | |
7550 | tdep->struct_return = pcc_struct_return; | |
7551 | tdep->sigtramp_start = 0; | |
7552 | tdep->sigtramp_end = 0; | |
7553 | tdep->sigtramp_p = i386_sigtramp_p; | |
7554 | tdep->sigcontext_addr = NULL; | |
7555 | tdep->sc_reg_offset = NULL; | |
7556 | tdep->sc_pc_offset = -1; | |
7557 | tdep->sc_sp_offset = -1; | |
7558 | ||
c131fcee L |
7559 | tdep->xsave_xcr0_offset = -1; |
7560 | ||
cf648174 HZ |
7561 | tdep->record_regmap = i386_record_regmap; |
7562 | ||
205c306f DM |
7563 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
7564 | ||
7ad10968 HZ |
7565 | /* The format used for `long double' on almost all i386 targets is |
7566 | the i387 extended floating-point format. In fact, of all targets | |
7567 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
7568 | on having a `long double' that's not `long' at all. */ | |
7569 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
7570 | ||
7571 | /* Although the i387 extended floating-point has only 80 significant | |
7572 | bits, a `long double' actually takes up 96, probably to enforce | |
7573 | alignment. */ | |
7574 | set_gdbarch_long_double_bit (gdbarch, 96); | |
7575 | ||
7ad10968 HZ |
7576 | /* Register numbers of various important registers. */ |
7577 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
7578 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
7579 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
7580 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
7581 | ||
7582 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
7583 | numbering schemes on the i386: dbx and SVR4. These schemes | |
7584 | differ in how they number %ebp, %esp, %eflags, and the | |
7585 | floating-point registers, and are implemented by the arrays | |
7586 | dbx_register_map[] and svr4_dbx_register_map in | |
7587 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
7588 | gcc/config/i386.c, which it designates as the "default" register | |
7589 | map used in 64bit mode. This last register numbering scheme is | |
7590 | implemented in dbx64_register_map, and is used for AMD64; see | |
7591 | amd64-tdep.c. | |
7592 | ||
7593 | Currently, each GCC i386 target always uses the same register | |
7594 | numbering scheme across all its supported debugging formats | |
7595 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
7596 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
7597 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
7598 | respective config header in a manner independent of the requested | |
7599 | output debugging format. | |
7600 | ||
7601 | This does not match the arrangement below, which presumes that | |
7602 | the SDB and stabs numbering schemes differ from the DWARF and | |
7603 | DWARF 2 ones. The reason for this arrangement is that it is | |
7604 | likely to get the numbering scheme for the target's | |
7605 | default/native debug format right. For targets where GCC is the | |
7606 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
7607 | targets where the native toolchain uses a different numbering | |
7608 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
7609 | the defaults below will have to be overridden, like | |
7610 | i386_elf_init_abi() does. */ | |
7611 | ||
7612 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
7613 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7614 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7615 | ||
7616 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
7617 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
7618 | ||
7619 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
7620 | be in use on any of the supported i386 targets. */ | |
7621 | ||
7622 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
7623 | ||
7624 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
7625 | ||
7626 | /* Call dummy code. */ | |
a9b8d892 JK |
7627 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
7628 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 7629 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 7630 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
7631 | |
7632 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
7633 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
7634 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
7635 | ||
7636 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
7637 | ||
7638 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
7639 | ||
7640 | /* Stack grows downward. */ | |
7641 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7642 | ||
7643 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
7644 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
7645 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
7646 | ||
7647 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
7648 | ||
7ad10968 HZ |
7649 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
7650 | ||
7651 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
7652 | ||
7653 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
7654 | ||
7655 | /* Add the i386 register groups. */ | |
7656 | i386_add_reggroups (gdbarch); | |
90884b2b | 7657 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 7658 | |
143985b7 AF |
7659 | /* Helper for function argument information. */ |
7660 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
7661 | ||
06da04c6 | 7662 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
7663 | appended to the list first, so that it supercedes the DWARF |
7664 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
7665 | currently fails). */ |
7666 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
7667 | ||
7668 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 7669 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 7670 | CFI info will be used if it is available. */ |
10458914 | 7671 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 7672 | |
acd5c798 | 7673 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 7674 | |
1ba53b71 | 7675 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
7676 | set_gdbarch_pseudo_register_read_value (gdbarch, |
7677 | i386_pseudo_register_read_value); | |
90884b2b L |
7678 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
7679 | ||
7680 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
7681 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
7682 | ||
c131fcee L |
7683 | /* Override the normal target description method to make the AVX |
7684 | upper halves anonymous. */ | |
7685 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
7686 | ||
7687 | /* Even though the default ABI only includes general-purpose registers, | |
7688 | floating-point registers and the SSE registers, we have to leave a | |
7689 | gap for the upper AVX registers. */ | |
7690 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); | |
90884b2b L |
7691 | |
7692 | /* Get the x86 target description from INFO. */ | |
7693 | tdesc = info.target_desc; | |
7694 | if (! tdesc_has_registers (tdesc)) | |
7695 | tdesc = tdesc_i386; | |
7696 | tdep->tdesc = tdesc; | |
7697 | ||
7698 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
7699 | tdep->register_names = i386_register_names; | |
7700 | ||
c131fcee L |
7701 | /* No upper YMM registers. */ |
7702 | tdep->ymmh_register_names = NULL; | |
7703 | tdep->ymm0h_regnum = -1; | |
7704 | ||
1ba53b71 L |
7705 | tdep->num_byte_regs = 8; |
7706 | tdep->num_word_regs = 8; | |
7707 | tdep->num_dword_regs = 0; | |
7708 | tdep->num_mmx_regs = 8; | |
c131fcee | 7709 | tdep->num_ymm_regs = 0; |
1ba53b71 | 7710 | |
90884b2b L |
7711 | tdesc_data = tdesc_data_alloc (); |
7712 | ||
dde08ee1 PA |
7713 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
7714 | ||
6710bf39 SS |
7715 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
7716 | ||
3ce1502b | 7717 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 7718 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 7719 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 7720 | |
c131fcee L |
7721 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
7722 | { | |
7723 | tdesc_data_cleanup (tdesc_data); | |
7724 | xfree (tdep); | |
7725 | gdbarch_free (gdbarch); | |
7726 | return NULL; | |
7727 | } | |
7728 | ||
1ba53b71 L |
7729 | /* Wire in pseudo registers. Number of pseudo registers may be |
7730 | changed. */ | |
7731 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
7732 | + tdep->num_word_regs | |
7733 | + tdep->num_dword_regs | |
c131fcee L |
7734 | + tdep->num_mmx_regs |
7735 | + tdep->num_ymm_regs)); | |
1ba53b71 | 7736 | |
90884b2b L |
7737 | /* Target description may be changed. */ |
7738 | tdesc = tdep->tdesc; | |
7739 | ||
90884b2b L |
7740 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
7741 | ||
7742 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
7743 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
7744 | ||
1ba53b71 L |
7745 | /* Make %al the first pseudo-register. */ |
7746 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
7747 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
7748 | ||
c131fcee | 7749 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
7750 | if (tdep->num_dword_regs) |
7751 | { | |
1c6272a6 | 7752 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
7753 | tdep->eax_regnum = ymm0_regnum; |
7754 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
7755 | } |
7756 | else | |
7757 | tdep->eax_regnum = -1; | |
7758 | ||
c131fcee L |
7759 | mm0_regnum = ymm0_regnum; |
7760 | if (tdep->num_ymm_regs) | |
7761 | { | |
1c6272a6 | 7762 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
7763 | tdep->ymm0_regnum = ymm0_regnum; |
7764 | mm0_regnum += tdep->num_ymm_regs; | |
7765 | } | |
7766 | else | |
7767 | tdep->ymm0_regnum = -1; | |
7768 | ||
1ba53b71 L |
7769 | if (tdep->num_mmx_regs != 0) |
7770 | { | |
1c6272a6 | 7771 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 L |
7772 | tdep->mm0_regnum = mm0_regnum; |
7773 | } | |
7774 | else | |
7775 | tdep->mm0_regnum = -1; | |
7776 | ||
06da04c6 | 7777 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 7778 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
7779 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
7780 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 7781 | |
8446b36a MK |
7782 | /* If we have a register mapping, enable the generic core file |
7783 | support, unless it has already been enabled. */ | |
7784 | if (tdep->gregset_reg_offset | |
7785 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
7786 | set_gdbarch_regset_from_core_section (gdbarch, | |
7787 | i386_regset_from_core_section); | |
7788 | ||
514f746b AR |
7789 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
7790 | i386_skip_permanent_breakpoint); | |
7791 | ||
7a697b8d SS |
7792 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
7793 | i386_fast_tracepoint_valid_at); | |
7794 | ||
a62cc96e AC |
7795 | return gdbarch; |
7796 | } | |
7797 | ||
8201327c MK |
7798 | static enum gdb_osabi |
7799 | i386_coff_osabi_sniffer (bfd *abfd) | |
7800 | { | |
762c5349 MK |
7801 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
7802 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
7803 | return GDB_OSABI_GO32; |
7804 | ||
7805 | return GDB_OSABI_UNKNOWN; | |
7806 | } | |
8201327c MK |
7807 | \f |
7808 | ||
28e9e0f0 MK |
7809 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
7810 | void _initialize_i386_tdep (void); | |
7811 | ||
c906108c | 7812 | void |
fba45db2 | 7813 | _initialize_i386_tdep (void) |
c906108c | 7814 | { |
a62cc96e AC |
7815 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
7816 | ||
fc338970 | 7817 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
7818 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
7819 | &disassembly_flavor, _("\ | |
7820 | Set the disassembly flavor."), _("\ | |
7821 | Show the disassembly flavor."), _("\ | |
7822 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
7823 | NULL, | |
7824 | NULL, /* FIXME: i18n: */ | |
7825 | &setlist, &showlist); | |
8201327c MK |
7826 | |
7827 | /* Add the variable that controls the convention for returning | |
7828 | structs. */ | |
7ab04401 AC |
7829 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
7830 | &struct_convention, _("\ | |
7831 | Set the convention for returning small structs."), _("\ | |
7832 | Show the convention for returning small structs."), _("\ | |
7833 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
7834 | is \"default\"."), | |
7835 | NULL, | |
7836 | NULL, /* FIXME: i18n: */ | |
7837 | &setlist, &showlist); | |
8201327c MK |
7838 | |
7839 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
7840 | i386_coff_osabi_sniffer); | |
8201327c | 7841 | |
05816f70 | 7842 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 7843 | i386_svr4_init_abi); |
05816f70 | 7844 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 7845 | i386_go32_init_abi); |
38c968cf | 7846 | |
209bd28e | 7847 | /* Initialize the i386-specific register groups. */ |
38c968cf | 7848 | i386_init_reggroups (); |
90884b2b L |
7849 | |
7850 | /* Initialize the standard target descriptions. */ | |
7851 | initialize_tdesc_i386 (); | |
3a13a53b | 7852 | initialize_tdesc_i386_mmx (); |
c131fcee | 7853 | initialize_tdesc_i386_avx (); |
c8d5aac9 L |
7854 | |
7855 | /* Tell remote stub that we support XML target description. */ | |
7856 | register_remote_support_xml ("i386"); | |
c906108c | 7857 | } |