[deliverable/binutils-gdb.git] / gdb / i386-tdep.h

/* Target-dependent code for the i386.

   Copyright (C) 2001, 2002, 2003, 2004, 2006, 2007, 2008, 2009, 2010
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef I386_TDEP_H
#define I386_TDEP_H

struct frame_info;
struct gdbarch;
struct reggroup;
struct regset;
struct regcache;

/* GDB's i386 target supports both the 32-bit Intel Architecture
   (IA-32) and the 64-bit AMD x86-64 architecture.  Internally it uses
   a similar register layout for both.

   - General purpose registers
   - FPU data registers
   - FPU control registers
   - SSE data registers
   - SSE control register

   The general purpose registers for the x86-64 architecture are quite
   different from IA-32.  Therefore, gdbarch_fp0_regnum
   determines the register number at which the FPU data registers
   start.  The number of FPU data and control registers is the same
   for both architectures.  The number of SSE registers however,
   differs and is determined by the num_xmm_regs member of `struct
   gdbarch_tdep'.  */

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Register classes as defined in the AMD x86-64 psABI.  */

enum amd64_reg_class
{
  AMD64_INTEGER,
  AMD64_SSE,
  AMD64_SSEUP,
  AMD64_X87,
  AMD64_X87UP,
  AMD64_COMPLEX_X87,
  AMD64_NO_CLASS,
  AMD64_MEMORY
};

/* i386 architecture specific information.  */
struct gdbarch_tdep
{
  /* General-purpose registers.  */
  struct regset *gregset;
  int *gregset_reg_offset;
  int gregset_num_regs;
  size_t sizeof_gregset;

  /* The general-purpose registers used to pass integers when making
     function calls.  This only applies to amd64, as all parameters
     are passed through the stack on x86.  */
  int call_dummy_num_integer_regs;
  int *call_dummy_integer_regs;

  /* Used on amd64 only.  Classify TYPE according to calling conventions,
     and store the result in CLASS.  */
  void (*classify) (struct type *type, enum amd64_reg_class class[2]);

  /* Used on amd64 only.  Non-zero if the first few MEMORY arguments
     should be passed by pointer.

     More precisely, MEMORY arguments are passed through the stack.
     But certain architectures require that their address be passed
     by register as well, if there are still some integer registers
     available for argument passing.  */
  int memory_args_by_pointer;

  /* Used on amd64 only.

     If non-zero, then the callers of a function are expected to reserve
     some space in the stack just before the area where the PC is saved
     so that the callee may save the integer-parameter registers there.
     The amount of space is dependent on the list of registers used for
     integer parameter passing (see component call_dummy_num_integer_regs
     above).  */
  int integer_param_regs_saved_in_caller_frame;

  /* Floating-point registers.  */
  struct regset *fpregset;
  size_t sizeof_fpregset;

  /* Register number for %st(0).  The register numbers for the other
     registers follow from this one.  Set this to -1 to indicate the
     absence of an FPU.  */
  int st0_regnum;

  /* Register number for %mm0.  Set this to -1 to indicate the absence
     of MMX support.  */
  int mm0_regnum;

  /* Number of core registers.  */
  int num_core_regs;

  /* Number of SSE registers.  */
  int num_xmm_regs;

  /* Register names.  */
  const char **register_names;

  /* Target description.  */
  const struct target_desc *tdesc;

  /* Register group function.  */
  const void *register_reggroup_p;

  /* Offset of saved PC in jmp_buf.  */
  int jb_pc_offset;

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Address range where sigtramp lives.  */
  CORE_ADDR sigtramp_start;
  CORE_ADDR sigtramp_end;

  /* Detect sigtramp.  */
  int (*sigtramp_p) (struct frame_info *);

  /* Get address of sigcontext for sigtramp.  */
  CORE_ADDR (*sigcontext_addr) (struct frame_info *);

  /* Offset of registers in `struct sigcontext'.  */
  int *sc_reg_offset;
  int sc_num_regs;

  /* Offset of saved PC and SP in `struct sigcontext'.  Usage of these
     is deprecated, please use `sc_reg_offset' instead.  */
  int sc_pc_offset;
  int sc_sp_offset;

  /* ISA-specific data types.  */
  struct type *i386_mmx_type;
  struct type *i387_ext_type;

  /* Process record/replay target.  */
  /* The map for registers because the AMD64's registers order
     in GDB is not same as I386 instructions.  */
  const int *record_regmap;
  /* Parse intx80 args.  */
  int (*i386_intx80_record) (struct regcache *regcache);
  /* Parse sysenter args.  */
  int (*i386_sysenter_record) (struct regcache *regcache);
  /* Parse syscall args.  */
  int (*i386_syscall_record) (struct regcache *regcache);
};

/* Floating-point registers.  */

/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
   (at most) in the FPU, but are zero-extended to 32 bits in GDB's
   register cache.  */

/* Return non-zero if REGNUM matches the FP register and the FP
   register set is active.  */
extern int i386_fp_regnum_p (struct gdbarch *, int);
extern int i386_fpc_regnum_p (struct gdbarch *, int);

/* Register numbers of various important registers.  */

enum i386_regnum
{
  I386_EAX_REGNUM,		/* %eax */
  I386_ECX_REGNUM,		/* %ecx */
  I386_EDX_REGNUM,		/* %edx */
  I386_EBX_REGNUM,		/* %ebx */
  I386_ESP_REGNUM,		/* %esp */
  I386_EBP_REGNUM,		/* %ebp */
  I386_ESI_REGNUM,		/* %esi */
  I386_EDI_REGNUM,		/* %edi */
  I386_EIP_REGNUM,		/* %eip */
  I386_EFLAGS_REGNUM,		/* %eflags */
  I386_CS_REGNUM,		/* %cs */
  I386_SS_REGNUM,		/* %ss */
  I386_DS_REGNUM,		/* %ds */
  I386_ES_REGNUM,		/* %es */
  I386_FS_REGNUM,		/* %fs */
  I386_GS_REGNUM,		/* %gs */
  I386_ST0_REGNUM,		/* %st(0) */
  I386_MXCSR_REGNUM = 40	/* %mxcsr */ 
};

/* Register numbers of RECORD_REGMAP.  */

enum record_i386_regnum
{
  X86_RECORD_REAX_REGNUM,
  X86_RECORD_RECX_REGNUM,
  X86_RECORD_REDX_REGNUM,
  X86_RECORD_REBX_REGNUM,
  X86_RECORD_RESP_REGNUM,
  X86_RECORD_REBP_REGNUM,
  X86_RECORD_RESI_REGNUM,
  X86_RECORD_REDI_REGNUM,
  X86_RECORD_R8_REGNUM,
  X86_RECORD_R9_REGNUM,
  X86_RECORD_R10_REGNUM,
  X86_RECORD_R11_REGNUM,
  X86_RECORD_R12_REGNUM,
  X86_RECORD_R13_REGNUM,
  X86_RECORD_R14_REGNUM,
  X86_RECORD_R15_REGNUM,
  X86_RECORD_REIP_REGNUM,
  X86_RECORD_EFLAGS_REGNUM,
  X86_RECORD_CS_REGNUM,
  X86_RECORD_SS_REGNUM,
  X86_RECORD_DS_REGNUM,
  X86_RECORD_ES_REGNUM,
  X86_RECORD_FS_REGNUM,
  X86_RECORD_GS_REGNUM,
};

#define I386_NUM_GREGS	16
#define I386_NUM_XREGS  9

#define I386_SSE_NUM_REGS	(I386_MXCSR_REGNUM + 1)

/* Size of the largest register.  */
#define I386_MAX_REGISTER_SIZE	16

/* Types for i386-specific registers.  */
extern struct type *i387_ext_type (struct gdbarch *gdbarch);

/* Segment selectors.  */
#define I386_SEL_RPL	0x0003  /* Requester's Privilege Level mask.  */
#define I386_SEL_UPL	0x0003	/* User Privilige Level. */
#define I386_SEL_KPL	0x0000	/* Kernel Privilige Level. */

/* The length of the longest i386 instruction (according to
   include/asm-i386/kprobes.h in Linux 2.6.  */
#define I386_MAX_INSN_LEN (16)

/* Functions exported from i386-tdep.c.  */
extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
					       CORE_ADDR pc, char *name);
extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc);

/* Return whether the THIS_FRAME corresponds to a sigtramp routine.  */
extern int i386_sigtramp_p (struct frame_info *this_frame);

/* Return non-zero if REGNUM is a member of the specified group.  */
extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
				     struct reggroup *group);

/* Supply register REGNUM from the general-purpose register set REGSET
   to register cache REGCACHE.  If REGNUM is -1, do this for all
   registers in REGSET.  */
extern void i386_supply_gregset (const struct regset *regset,
				 struct regcache *regcache, int regnum,
				 const void *gregs, size_t len);

/* Collect register REGNUM from the register cache REGCACHE and store
   it in the buffer specified by GREGS and LEN as described by the
   general-purpose register set REGSET.  If REGNUM is -1, do this for
   all registers in REGSET.  */
extern void i386_collect_gregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *gregs, size_t len);

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */
extern const struct regset *
  i386_regset_from_core_section (struct gdbarch *gdbarch,
				 const char *sect_name, size_t sect_size);


extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
				       struct displaced_step_closure *closure,
				       CORE_ADDR from, CORE_ADDR to,
				       struct regcache *regs);

/* Initialize a basic ELF architecture variant.  */
extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);

/* Initialize a SVR4 architecture variant.  */
extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);

extern int i386_process_record (struct gdbarch *gdbarch,
                                struct regcache *regcache, CORE_ADDR addr);
\f

/* Functions and variables exported from i386bsd-tdep.c.  */

extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
extern CORE_ADDR i386fbsd_sigtramp_start_addr;
extern CORE_ADDR i386fbsd_sigtramp_end_addr;
extern CORE_ADDR i386obsd_sigtramp_start_addr;
extern CORE_ADDR i386obsd_sigtramp_end_addr;
extern int i386fbsd4_sc_reg_offset[];
extern int i386fbsd_sc_reg_offset[];
extern int i386nbsd_sc_reg_offset[];
extern int i386obsd_sc_reg_offset[];
extern int i386bsd_sc_reg_offset[];

#endif /* i386-tdep.h */
Commit	Line	Data
5716833c MK	1	/* Target-dependent code for the i386.
5716833c MK	2
4c38e0a4	3	Copyright (C) 2001, 2002, 2003, 2004, 2006, 2007, 2008, 2009, 2010
5ae96ec1	4	Free Software Foundation, Inc.
9a82579f JS	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
a9762ec7	10	the Free Software Foundation; either version 3 of the License, or
9a82579f JS	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
a9762ec7	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9a82579f JS	20
	21	#ifndef I386_TDEP_H
	22	#define I386_TDEP_H
	23
da3331ec	24	struct frame_info;
5716833c MK	25	struct gdbarch;
5716833c MK	26	struct reggroup;
c783cbd6	27	struct regset;
5439edaa	28	struct regcache;
da3331ec	29
96297dab MK	30	/* GDB's i386 target supports both the 32-bit Intel Architecture
	31	(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
	32	a similar register layout for both.
	33
	34	- General purpose registers
	35	- FPU data registers
	36	- FPU control registers
	37	- SSE data registers
	38	- SSE control register
	39
	40	The general purpose registers for the x86-64 architecture are quite
3e8c568d	41	different from IA-32. Therefore, gdbarch_fp0_regnum
96297dab MK	42	determines the register number at which the FPU data registers
	43	start. The number of FPU data and control registers is the same
	44	for both architectures. The number of SSE registers however,
	45	differs and is determined by the num_xmm_regs member of `struct
	46	gdbarch_tdep'. */
	47
8201327c	48	/* Convention for returning structures. */
3ce1502b	49
8201327c MK	50	enum struct_return
	51	{
	52	pcc_struct_return, /* Return "short" structures in memory. */
	53	reg_struct_return /* Return "short" structures in registers. */
3ce1502b MK	54	};
3ce1502b MK	55
ba581dc1 JB	56	/* Register classes as defined in the AMD x86-64 psABI. */
	57
	58	enum amd64_reg_class
	59	{
	60	AMD64_INTEGER,
	61	AMD64_SSE,
	62	AMD64_SSEUP,
	63	AMD64_X87,
	64	AMD64_X87UP,
	65	AMD64_COMPLEX_X87,
	66	AMD64_NO_CLASS,
	67	AMD64_MEMORY
	68	};
	69
96297dab MK	70	/* i386 architecture specific information. */
	71	struct gdbarch_tdep
	72	{
473f17b0 MK	73	/* General-purpose registers. */
	74	struct regset *gregset;
	75	int *gregset_reg_offset;
	76	int gregset_num_regs;
	77	size_t sizeof_gregset;
	78
ba581dc1 JB	79	/* The general-purpose registers used to pass integers when making
	80	function calls. This only applies to amd64, as all parameters
	81	are passed through the stack on x86. */
	82	int call_dummy_num_integer_regs;
	83	int *call_dummy_integer_regs;
	84
3af6ddfe JB	85	/* Used on amd64 only. Classify TYPE according to calling conventions,
3af6ddfe JB	86	and store the result in CLASS. */
ba581dc1 JB	87	void (classify) (struct type type, enum amd64_reg_class class[2]);
ba581dc1 JB	88
3af6ddfe JB	89	/* Used on amd64 only. Non-zero if the first few MEMORY arguments
3af6ddfe JB	90	should be passed by pointer.
80d19a06 JB	91
	92	More precisely, MEMORY arguments are passed through the stack.
	93	But certain architectures require that their address be passed
	94	by register as well, if there are still some integer registers
	95	available for argument passing. */
	96	int memory_args_by_pointer;
	97
3af6ddfe JB	98	/* Used on amd64 only.
	99
	100	If non-zero, then the callers of a function are expected to reserve
	101	some space in the stack just before the area where the PC is saved
	102	so that the callee may save the integer-parameter registers there.
	103	The amount of space is dependent on the list of registers used for
	104	integer parameter passing (see component call_dummy_num_integer_regs
	105	above). */
	106	int integer_param_regs_saved_in_caller_frame;
	107
473f17b0 MK	108	/* Floating-point registers. */
	109	struct regset *fpregset;
	110	size_t sizeof_fpregset;
	111
5716833c MK	112	/* Register number for %st(0). The register numbers for the other
	113	registers follow from this one. Set this to -1 to indicate the
	114	absence of an FPU. */
	115	int st0_regnum;
	116
	117	/* Register number for %mm0. Set this to -1 to indicate the absence
	118	of MMX support. */
	119	int mm0_regnum;
	120
90884b2b L	121	/* Number of core registers. */
	122	int num_core_regs;
	123
96297dab MK	124	/* Number of SSE registers. */
96297dab MK	125	int num_xmm_regs;
8201327c	126
90884b2b L	127	/* Register names. */
	128	const char **register_names;
	129
	130	/* Target description. */
	131	const struct target_desc *tdesc;
	132
	133	/* Register group function. */
	134	const void *register_reggroup_p;
	135
8201327c MK	136	/* Offset of saved PC in jmp_buf. */
	137	int jb_pc_offset;
	138
	139	/* Convention for returning structures. */
	140	enum struct_return struct_return;
	141
8201327c MK	142	/* Address range where sigtramp lives. */
	143	CORE_ADDR sigtramp_start;
	144	CORE_ADDR sigtramp_end;
	145
911bc6ee MK	146	/* Detect sigtramp. */
	147	int (sigtramp_p) (struct frame_info );
	148
21d0e8a4 MK	149	/* Get address of sigcontext for sigtramp. */
	150	CORE_ADDR (sigcontext_addr) (struct frame_info );
	151
a3386186 MK	152	/* Offset of registers in `struct sigcontext'. */
	153	int *sc_reg_offset;
	154	int sc_num_regs;
	155
	156	/* Offset of saved PC and SP in `struct sigcontext'. Usage of these
	157	is deprecated, please use `sc_reg_offset' instead. */
8201327c	158	int sc_pc_offset;
21d0e8a4	159	int sc_sp_offset;
794ac428 UW	160
	161	/* ISA-specific data types. */
	162	struct type *i386_mmx_type;
27067745	163	struct type *i387_ext_type;
7ad10968 HZ	164
7ad10968 HZ	165	/* Process record/replay target. */
cf648174 HZ	166	/* The map for registers because the AMD64's registers order
	167	in GDB is not same as I386 instructions. */
	168	const int *record_regmap;
7ad10968 HZ	169	/* Parse intx80 args. */
	170	int (i386_intx80_record) (struct regcache regcache);
	171	/* Parse sysenter args. */
	172	int (i386_sysenter_record) (struct regcache regcache);
cf648174 HZ	173	/* Parse syscall args. */
cf648174 HZ	174	int (i386_syscall_record) (struct regcache regcache);
96297dab MK	175	};
	176
	177	/* Floating-point registers. */
	178
96297dab MK	179	/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
	180	(at most) in the FPU, but are zero-extended to 32 bits in GDB's
	181	register cache. */
	182
23a34459 AC	183	/* Return non-zero if REGNUM matches the FP register and the FP
23a34459 AC	184	register set is active. */
20a6ec49 MD	185	extern int i386_fp_regnum_p (struct gdbarch *, int);
20a6ec49 MD	186	extern int i386_fpc_regnum_p (struct gdbarch *, int);
96297dab	187
a3386186 MK	188	/* Register numbers of various important registers. */
a3386186 MK	189
bcf48cc7 MK	190	enum i386_regnum
	191	{
	192	I386_EAX_REGNUM, /* %eax */
	193	I386_ECX_REGNUM, /* %ecx */
	194	I386_EDX_REGNUM, /* %edx */
	195	I386_EBX_REGNUM, /* %ebx */
	196	I386_ESP_REGNUM, /* %esp */
	197	I386_EBP_REGNUM, /* %ebp */
	198	I386_ESI_REGNUM, /* %esi */
	199	I386_EDI_REGNUM, /* %edi */
	200	I386_EIP_REGNUM, /* %eip */
	201	I386_EFLAGS_REGNUM, /* %eflags */
2666fb59 MK	202	I386_CS_REGNUM, /* %cs */
2666fb59 MK	203	I386_SS_REGNUM, /* %ss */
e9ff708b AC	204	I386_DS_REGNUM, /* %ds */
	205	I386_ES_REGNUM, /* %es */
	206	I386_FS_REGNUM, /* %fs */
	207	I386_GS_REGNUM, /* %gs */
90884b2b L	208	I386_ST0_REGNUM, /* %st(0) */
90884b2b L	209	I386_MXCSR_REGNUM = 40 /* %mxcsr */
bcf48cc7	210	};
a3386186	211
cf648174 HZ	212	/* Register numbers of RECORD_REGMAP. */
	213
	214	enum record_i386_regnum
	215	{
	216	X86_RECORD_REAX_REGNUM,
	217	X86_RECORD_RECX_REGNUM,
	218	X86_RECORD_REDX_REGNUM,
	219	X86_RECORD_REBX_REGNUM,
	220	X86_RECORD_RESP_REGNUM,
	221	X86_RECORD_REBP_REGNUM,
	222	X86_RECORD_RESI_REGNUM,
	223	X86_RECORD_REDI_REGNUM,
	224	X86_RECORD_R8_REGNUM,
	225	X86_RECORD_R9_REGNUM,
	226	X86_RECORD_R10_REGNUM,
	227	X86_RECORD_R11_REGNUM,
	228	X86_RECORD_R12_REGNUM,
	229	X86_RECORD_R13_REGNUM,
	230	X86_RECORD_R14_REGNUM,
	231	X86_RECORD_R15_REGNUM,
	232	X86_RECORD_REIP_REGNUM,
	233	X86_RECORD_EFLAGS_REGNUM,
	234	X86_RECORD_CS_REGNUM,
	235	X86_RECORD_SS_REGNUM,
	236	X86_RECORD_DS_REGNUM,
	237	X86_RECORD_ES_REGNUM,
	238	X86_RECORD_FS_REGNUM,
	239	X86_RECORD_GS_REGNUM,
	240	};
	241
8201327c	242	#define I386_NUM_GREGS 16
8201327c MK	243	#define I386_NUM_XREGS 9
8201327c MK	244
90884b2b	245	#define I386_SSE_NUM_REGS (I386_MXCSR_REGNUM + 1)
8201327c	246
00f8375e MK	247	/* Size of the largest register. */
	248	#define I386_MAX_REGISTER_SIZE 16
	249
5ae96ec1	250	/* Types for i386-specific registers. */
27067745	251	extern struct type i387_ext_type (struct gdbarch gdbarch);
794ac428	252
508fbfea MK	253	/* Segment selectors. */
	254	#define I386_SEL_RPL 0x0003 /* Requester's Privilege Level mask. */
	255	#define I386_SEL_UPL 0x0003 /* User Privilige Level. */
	256	#define I386_SEL_KPL 0x0000 /* Kernel Privilige Level. */
	257
237fc4c9 PA	258	/* The length of the longest i386 instruction (according to
	259	include/asm-i386/kprobes.h in Linux 2.6. */
	260	#define I386_MAX_INSN_LEN (16)
	261
1cce71eb	262	/* Functions exported from i386-tdep.c. */
e17a4113 UW	263	extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
e17a4113 UW	264	CORE_ADDR pc, char *name);
4309257c	265	extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc);
1cce71eb	266
4bd207ef TG	267	/* Return whether the THIS_FRAME corresponds to a sigtramp routine. */
	268	extern int i386_sigtramp_p (struct frame_info *this_frame);
	269
38c968cf AC	270	/* Return non-zero if REGNUM is a member of the specified group. */
	271	extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
	272	struct reggroup *group);
	273
20187ed5 MK	274	/* Supply register REGNUM from the general-purpose register set REGSET
	275	to register cache REGCACHE. If REGNUM is -1, do this for all
	276	registers in REGSET. */
	277	extern void i386_supply_gregset (const struct regset *regset,
	278	struct regcache *regcache, int regnum,
	279	const void *gregs, size_t len);
3d171c85 MK	280
	281	/* Collect register REGNUM from the register cache REGCACHE and store
	282	it in the buffer specified by GREGS and LEN as described by the
	283	general-purpose register set REGSET. If REGNUM is -1, do this for
	284	all registers in REGSET. */
	285	extern void i386_collect_gregset (const struct regset *regset,
	286	const struct regcache *regcache,
	287	int regnum, void *gregs, size_t len);
20187ed5	288
8446b36a MK	289	/* Return the appropriate register set for the core section identified
	290	by SECT_NAME and SECT_SIZE. */
	291	extern const struct regset *
	292	i386_regset_from_core_section (struct gdbarch *gdbarch,
	293	const char *sect_name, size_t sect_size);
	294
237fc4c9 PA	295
	296	extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
	297	struct displaced_step_closure *closure,
	298	CORE_ADDR from, CORE_ADDR to,
	299	struct regcache *regs);
	300
8201327c MK	301	/* Initialize a basic ELF architecture variant. */
	302	extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);
	303
	304	/* Initialize a SVR4 architecture variant. */
	305	extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
a6b808b4 HZ	306
	307	extern int i386_process_record (struct gdbarch *gdbarch,
	308	struct regcache *regcache, CORE_ADDR addr);
de0b6abb	309	\f
8201327c	310
de0b6abb	311	/* Functions and variables exported from i386bsd-tdep.c. */
8201327c	312
3cac699e	313	extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
5d93ae8c MK	314	extern CORE_ADDR i386fbsd_sigtramp_start_addr;
	315	extern CORE_ADDR i386fbsd_sigtramp_end_addr;
	316	extern CORE_ADDR i386obsd_sigtramp_start_addr;
	317	extern CORE_ADDR i386obsd_sigtramp_end_addr;
de0b6abb MK	318	extern int i386fbsd4_sc_reg_offset[];
	319	extern int i386fbsd_sc_reg_offset[];
	320	extern int i386nbsd_sc_reg_offset[];
	321	extern int i386obsd_sc_reg_offset[];
	322	extern int i386bsd_sc_reg_offset[];
3ce1502b	323
96297dab	324	#endif /* i386-tdep.h */