[deliverable/binutils-gdb.git] / gdb / i386-tdep.h

/* Target-dependent code for the i386.

   Copyright (C) 2001-2004, 2006-2012 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef I386_TDEP_H
#define I386_TDEP_H

struct frame_info;
struct gdbarch;
struct reggroup;
struct regset;
struct regcache;

/* GDB's i386 target supports both the 32-bit Intel Architecture
   (IA-32) and the 64-bit AMD x86-64 architecture.  Internally it uses
   a similar register layout for both.

   - General purpose registers
   - FPU data registers
   - FPU control registers
   - SSE data registers
   - SSE control register

   The general purpose registers for the x86-64 architecture are quite
   different from IA-32.  Therefore, gdbarch_fp0_regnum
   determines the register number at which the FPU data registers
   start.  The number of FPU data and control registers is the same
   for both architectures.  The number of SSE registers however,
   differs and is determined by the num_xmm_regs member of `struct
   gdbarch_tdep'.  */

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Register classes as defined in the AMD x86-64 psABI.  */

enum amd64_reg_class
{
  AMD64_INTEGER,
  AMD64_SSE,
  AMD64_SSEUP,
  AMD64_X87,
  AMD64_X87UP,
  AMD64_COMPLEX_X87,
  AMD64_NO_CLASS,
  AMD64_MEMORY
};

/* i386 architecture specific information.  */
struct gdbarch_tdep
{
  /* General-purpose registers.  */
  struct regset *gregset;
  int *gregset_reg_offset;
  int gregset_num_regs;
  size_t sizeof_gregset;

  /* The general-purpose registers used to pass integers when making
     function calls.  This only applies to amd64, as all parameters
     are passed through the stack on x86.  */
  int call_dummy_num_integer_regs;
  int *call_dummy_integer_regs;

  /* Used on amd64 only.  Classify TYPE according to calling conventions,
     and store the result in CLASS.  */
  void (*classify) (struct type *type, enum amd64_reg_class class[2]);

  /* Used on amd64 only.  Non-zero if the first few MEMORY arguments
     should be passed by pointer.

     More precisely, MEMORY arguments are passed through the stack.
     But certain architectures require that their address be passed
     by register as well, if there are still some integer registers
     available for argument passing.  */
  int memory_args_by_pointer;

  /* Used on amd64 only.

     If non-zero, then the callers of a function are expected to reserve
     some space in the stack just before the area where the PC is saved
     so that the callee may save the integer-parameter registers there.
     The amount of space is dependent on the list of registers used for
     integer parameter passing (see component call_dummy_num_integer_regs
     above).  */
  int integer_param_regs_saved_in_caller_frame;

  /* Floating-point registers.  */
  struct regset *fpregset;
  size_t sizeof_fpregset;

  /* XSAVE extended state.  */
  struct regset *xstateregset;

  /* Register number for %st(0).  The register numbers for the other
     registers follow from this one.  Set this to -1 to indicate the
     absence of an FPU.  */
  int st0_regnum;

  /* Number of MMX registers.  */
  int num_mmx_regs;

  /* Register number for %mm0.  Set this to -1 to indicate the absence
     of MMX support.  */
  int mm0_regnum;

  /* Number of pseudo YMM registers.  */
  int num_ymm_regs;

  /* Register number for %ymm0.  Set this to -1 to indicate the absence
     of pseudo YMM register support.  */
  int ymm0_regnum;

  /* Number of byte registers.  */
  int num_byte_regs;

  /* Register pseudo number for %al.  */
  int al_regnum;

  /* Number of pseudo word registers.  */
  int num_word_regs;

  /* Register number for %ax.  */
  int ax_regnum;

  /* Number of pseudo dword registers.  */
  int num_dword_regs;

  /* Register number for %eax.  Set this to -1 to indicate the absence
     of pseudo dword register support.  */
  int eax_regnum;

  /* Number of core registers.  */
  int num_core_regs;

  /* Number of SSE registers.  */
  int num_xmm_regs;

  /* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
     register), excluding the x87 bit, which are supported by this GDB.  */

  uint64_t xcr0;

  /* Offset of XCR0 in XSAVE extended state.  */
  int xsave_xcr0_offset;

  /* Register names.  */
  const char **register_names;

  /* Register number for %ymm0h.  Set this to -1 to indicate the absence
     of upper YMM register support.  */
  int ymm0h_regnum;

  /* Upper YMM register names.  Only used for tdesc_numbered_register.  */
  const char **ymmh_register_names;

  /* Target description.  */
  const struct target_desc *tdesc;

  /* Register group function.  */
  const void *register_reggroup_p;

  /* Offset of saved PC in jmp_buf.  */
  int jb_pc_offset;

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Address range where sigtramp lives.  */
  CORE_ADDR sigtramp_start;
  CORE_ADDR sigtramp_end;

  /* Detect sigtramp.  */
  int (*sigtramp_p) (struct frame_info *);

  /* Get address of sigcontext for sigtramp.  */
  CORE_ADDR (*sigcontext_addr) (struct frame_info *);

  /* Offset of registers in `struct sigcontext'.  */
  int *sc_reg_offset;
  int sc_num_regs;

  /* Offset of saved PC and SP in `struct sigcontext'.  Usage of these
     is deprecated, please use `sc_reg_offset' instead.  */
  int sc_pc_offset;
  int sc_sp_offset;

  /* ISA-specific data types.  */
  struct type *i386_mmx_type;
  struct type *i386_ymm_type;
  struct type *i387_ext_type;

  /* Process record/replay target.  */
  /* The map for registers because the AMD64's registers order
     in GDB is not same as I386 instructions.  */
  const int *record_regmap;
  /* Parse intx80 args.  */
  int (*i386_intx80_record) (struct regcache *regcache);
  /* Parse sysenter args.  */
  int (*i386_sysenter_record) (struct regcache *regcache);
  /* Parse syscall args.  */
  int (*i386_syscall_record) (struct regcache *regcache);
};

/* Floating-point registers.  */

/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
   (at most) in the FPU, but are zero-extended to 32 bits in GDB's
   register cache.  */

/* Return non-zero if REGNUM matches the FP register and the FP
   register set is active.  */
extern int i386_fp_regnum_p (struct gdbarch *, int);
extern int i386_fpc_regnum_p (struct gdbarch *, int);

/* Register numbers of various important registers.  */

enum i386_regnum
{
  I386_EAX_REGNUM,		/* %eax */
  I386_ECX_REGNUM,		/* %ecx */
  I386_EDX_REGNUM,		/* %edx */
  I386_EBX_REGNUM,		/* %ebx */
  I386_ESP_REGNUM,		/* %esp */
  I386_EBP_REGNUM,		/* %ebp */
  I386_ESI_REGNUM,		/* %esi */
  I386_EDI_REGNUM,		/* %edi */
  I386_EIP_REGNUM,		/* %eip */
  I386_EFLAGS_REGNUM,		/* %eflags */
  I386_CS_REGNUM,		/* %cs */
  I386_SS_REGNUM,		/* %ss */
  I386_DS_REGNUM,		/* %ds */
  I386_ES_REGNUM,		/* %es */
  I386_FS_REGNUM,		/* %fs */
  I386_GS_REGNUM,		/* %gs */
  I386_ST0_REGNUM,		/* %st(0) */
  I386_MXCSR_REGNUM = 40,	/* %mxcsr */ 
  I386_YMM0H_REGNUM,		/* %ymm0h */
  I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7
};

/* Register numbers of RECORD_REGMAP.  */

enum record_i386_regnum
{
  X86_RECORD_REAX_REGNUM,
  X86_RECORD_RECX_REGNUM,
  X86_RECORD_REDX_REGNUM,
  X86_RECORD_REBX_REGNUM,
  X86_RECORD_RESP_REGNUM,
  X86_RECORD_REBP_REGNUM,
  X86_RECORD_RESI_REGNUM,
  X86_RECORD_REDI_REGNUM,
  X86_RECORD_R8_REGNUM,
  X86_RECORD_R9_REGNUM,
  X86_RECORD_R10_REGNUM,
  X86_RECORD_R11_REGNUM,
  X86_RECORD_R12_REGNUM,
  X86_RECORD_R13_REGNUM,
  X86_RECORD_R14_REGNUM,
  X86_RECORD_R15_REGNUM,
  X86_RECORD_REIP_REGNUM,
  X86_RECORD_EFLAGS_REGNUM,
  X86_RECORD_CS_REGNUM,
  X86_RECORD_SS_REGNUM,
  X86_RECORD_DS_REGNUM,
  X86_RECORD_ES_REGNUM,
  X86_RECORD_FS_REGNUM,
  X86_RECORD_GS_REGNUM,
};

#define I386_NUM_GREGS	16
#define I386_NUM_XREGS  9

#define I386_SSE_NUM_REGS	(I386_MXCSR_REGNUM + 1)
#define I386_AVX_NUM_REGS	(I386_YMM7H_REGNUM + 1)

/* Size of the largest register.  */
#define I386_MAX_REGISTER_SIZE	16

/* Types for i386-specific registers.  */
extern struct type *i387_ext_type (struct gdbarch *gdbarch);

/* Checks of different pseudo-registers.  */
extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);

extern const char *i386_pseudo_register_name (struct gdbarch *gdbarch,
					      int regnum);

extern void i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
						  struct regcache *regcache,
						  int regnum,
						  struct value *result);

extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
					struct regcache *regcache,
					int regnum, const gdb_byte *buf);

/* Segment selectors.  */
#define I386_SEL_RPL	0x0003  /* Requester's Privilege Level mask.  */
#define I386_SEL_UPL	0x0003	/* User Privilige Level.  */
#define I386_SEL_KPL	0x0000	/* Kernel Privilige Level.  */

/* The length of the longest i386 instruction (according to
   include/asm-i386/kprobes.h in Linux 2.6.  */
#define I386_MAX_INSN_LEN (16)

/* Functions exported from i386-tdep.c.  */
extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
					       CORE_ADDR pc, char *name);
extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
					  CORE_ADDR pc);

/* Return whether the THIS_FRAME corresponds to a sigtramp routine.  */
extern int i386_sigtramp_p (struct frame_info *this_frame);

/* Return non-zero if REGNUM is a member of the specified group.  */
extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
				     struct reggroup *group);

/* Supply register REGNUM from the general-purpose register set REGSET
   to register cache REGCACHE.  If REGNUM is -1, do this for all
   registers in REGSET.  */
extern void i386_supply_gregset (const struct regset *regset,
				 struct regcache *regcache, int regnum,
				 const void *gregs, size_t len);

/* Collect register REGNUM from the register cache REGCACHE and store
   it in the buffer specified by GREGS and LEN as described by the
   general-purpose register set REGSET.  If REGNUM is -1, do this for
   all registers in REGSET.  */
extern void i386_collect_gregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *gregs, size_t len);

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */
extern const struct regset *
  i386_regset_from_core_section (struct gdbarch *gdbarch,
				 const char *sect_name, size_t sect_size);


extern struct displaced_step_closure *i386_displaced_step_copy_insn
  (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
   struct regcache *regs);
extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
				       struct displaced_step_closure *closure,
				       CORE_ADDR from, CORE_ADDR to,
				       struct regcache *regs);

/* Initialize a basic ELF architecture variant.  */
extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);

/* Initialize a SVR4 architecture variant.  */
extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);

extern int i386_process_record (struct gdbarch *gdbarch,
                                struct regcache *regcache, CORE_ADDR addr);

\f

/* Functions and variables exported from i386bsd-tdep.c.  */

extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
extern CORE_ADDR i386fbsd_sigtramp_start_addr;
extern CORE_ADDR i386fbsd_sigtramp_end_addr;
extern CORE_ADDR i386obsd_sigtramp_start_addr;
extern CORE_ADDR i386obsd_sigtramp_end_addr;
extern int i386fbsd4_sc_reg_offset[];
extern int i386fbsd_sc_reg_offset[];
extern int i386nbsd_sc_reg_offset[];
extern int i386obsd_sc_reg_offset[];
extern int i386bsd_sc_reg_offset[];

/* SystemTap related functions.  */

extern int i386_stap_is_single_operand (struct gdbarch *gdbarch,
					const char *s);

extern int i386_stap_parse_special_token (struct gdbarch *gdbarch,
					  struct stap_parse_info *p);

#endif /* i386-tdep.h */
Commit	Line	Data
5716833c MK	1	/* Target-dependent code for the i386.
5716833c MK	2
0b302171	3	Copyright (C) 2001-2004, 2006-2012 Free Software Foundation, Inc.
9a82579f JS	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
9a82579f JS	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9a82579f JS	19
	20	#ifndef I386_TDEP_H
	21	#define I386_TDEP_H
	22
da3331ec	23	struct frame_info;
5716833c MK	24	struct gdbarch;
5716833c MK	25	struct reggroup;
c783cbd6	26	struct regset;
5439edaa	27	struct regcache;
da3331ec	28
96297dab MK	29	/* GDB's i386 target supports both the 32-bit Intel Architecture
	30	(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
	31	a similar register layout for both.
	32
	33	- General purpose registers
	34	- FPU data registers
	35	- FPU control registers
	36	- SSE data registers
	37	- SSE control register
	38
	39	The general purpose registers for the x86-64 architecture are quite
3e8c568d	40	different from IA-32. Therefore, gdbarch_fp0_regnum
96297dab MK	41	determines the register number at which the FPU data registers
	42	start. The number of FPU data and control registers is the same
	43	for both architectures. The number of SSE registers however,
	44	differs and is determined by the num_xmm_regs member of `struct
	45	gdbarch_tdep'. */
	46
8201327c	47	/* Convention for returning structures. */
3ce1502b	48
8201327c MK	49	enum struct_return
	50	{
	51	pcc_struct_return, /* Return "short" structures in memory. */
	52	reg_struct_return /* Return "short" structures in registers. */
3ce1502b MK	53	};
3ce1502b MK	54
ba581dc1 JB	55	/* Register classes as defined in the AMD x86-64 psABI. */
	56
	57	enum amd64_reg_class
	58	{
	59	AMD64_INTEGER,
	60	AMD64_SSE,
	61	AMD64_SSEUP,
	62	AMD64_X87,
	63	AMD64_X87UP,
	64	AMD64_COMPLEX_X87,
	65	AMD64_NO_CLASS,
	66	AMD64_MEMORY
	67	};
	68
96297dab MK	69	/* i386 architecture specific information. */
	70	struct gdbarch_tdep
	71	{
473f17b0 MK	72	/* General-purpose registers. */
	73	struct regset *gregset;
	74	int *gregset_reg_offset;
	75	int gregset_num_regs;
	76	size_t sizeof_gregset;
	77
ba581dc1 JB	78	/* The general-purpose registers used to pass integers when making
	79	function calls. This only applies to amd64, as all parameters
	80	are passed through the stack on x86. */
	81	int call_dummy_num_integer_regs;
	82	int *call_dummy_integer_regs;
	83
3af6ddfe JB	84	/* Used on amd64 only. Classify TYPE according to calling conventions,
3af6ddfe JB	85	and store the result in CLASS. */
ba581dc1 JB	86	void (classify) (struct type type, enum amd64_reg_class class[2]);
ba581dc1 JB	87
3af6ddfe JB	88	/* Used on amd64 only. Non-zero if the first few MEMORY arguments
3af6ddfe JB	89	should be passed by pointer.
80d19a06 JB	90
	91	More precisely, MEMORY arguments are passed through the stack.
	92	But certain architectures require that their address be passed
	93	by register as well, if there are still some integer registers
	94	available for argument passing. */
	95	int memory_args_by_pointer;
	96
3af6ddfe JB	97	/* Used on amd64 only.
	98
	99	If non-zero, then the callers of a function are expected to reserve
	100	some space in the stack just before the area where the PC is saved
	101	so that the callee may save the integer-parameter registers there.
	102	The amount of space is dependent on the list of registers used for
	103	integer parameter passing (see component call_dummy_num_integer_regs
	104	above). */
	105	int integer_param_regs_saved_in_caller_frame;
	106
473f17b0 MK	107	/* Floating-point registers. */
	108	struct regset *fpregset;
	109	size_t sizeof_fpregset;
	110
c131fcee L	111	/* XSAVE extended state. */
	112	struct regset *xstateregset;
	113
5716833c MK	114	/* Register number for %st(0). The register numbers for the other
	115	registers follow from this one. Set this to -1 to indicate the
	116	absence of an FPU. */
	117	int st0_regnum;
	118
1ba53b71 L	119	/* Number of MMX registers. */
	120	int num_mmx_regs;
	121
5716833c MK	122	/* Register number for %mm0. Set this to -1 to indicate the absence
	123	of MMX support. */
	124	int mm0_regnum;
	125
c131fcee L	126	/* Number of pseudo YMM registers. */
	127	int num_ymm_regs;
	128
	129	/* Register number for %ymm0. Set this to -1 to indicate the absence
	130	of pseudo YMM register support. */
	131	int ymm0_regnum;
	132
1ba53b71 L	133	/* Number of byte registers. */
	134	int num_byte_regs;
	135
	136	/* Register pseudo number for %al. */
	137	int al_regnum;
	138
	139	/* Number of pseudo word registers. */
	140	int num_word_regs;
	141
	142	/* Register number for %ax. */
	143	int ax_regnum;
	144
	145	/* Number of pseudo dword registers. */
	146	int num_dword_regs;
	147
	148	/* Register number for %eax. Set this to -1 to indicate the absence
	149	of pseudo dword register support. */
	150	int eax_regnum;
	151
90884b2b L	152	/* Number of core registers. */
	153	int num_core_regs;
	154
96297dab MK	155	/* Number of SSE registers. */
96297dab MK	156	int num_xmm_regs;
8201327c	157
c131fcee	158	/* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
1777feb0 MS	159	register), excluding the x87 bit, which are supported by this GDB. */
1777feb0 MS	160
c131fcee L	161	uint64_t xcr0;
	162
	163	/* Offset of XCR0 in XSAVE extended state. */
	164	int xsave_xcr0_offset;
	165
90884b2b L	166	/* Register names. */
	167	const char **register_names;
	168
c131fcee L	169	/* Register number for %ymm0h. Set this to -1 to indicate the absence
	170	of upper YMM register support. */
	171	int ymm0h_regnum;
	172
	173	/* Upper YMM register names. Only used for tdesc_numbered_register. */
	174	const char **ymmh_register_names;
	175
90884b2b L	176	/* Target description. */
	177	const struct target_desc *tdesc;
	178
	179	/* Register group function. */
	180	const void *register_reggroup_p;
	181
8201327c MK	182	/* Offset of saved PC in jmp_buf. */
	183	int jb_pc_offset;
	184
	185	/* Convention for returning structures. */
	186	enum struct_return struct_return;
	187
8201327c MK	188	/* Address range where sigtramp lives. */
	189	CORE_ADDR sigtramp_start;
	190	CORE_ADDR sigtramp_end;
	191
911bc6ee MK	192	/* Detect sigtramp. */
	193	int (sigtramp_p) (struct frame_info );
	194
21d0e8a4 MK	195	/* Get address of sigcontext for sigtramp. */
	196	CORE_ADDR (sigcontext_addr) (struct frame_info );
	197
a3386186 MK	198	/* Offset of registers in `struct sigcontext'. */
	199	int *sc_reg_offset;
	200	int sc_num_regs;
	201
	202	/* Offset of saved PC and SP in `struct sigcontext'. Usage of these
	203	is deprecated, please use `sc_reg_offset' instead. */
8201327c	204	int sc_pc_offset;
21d0e8a4	205	int sc_sp_offset;
794ac428 UW	206
	207	/* ISA-specific data types. */
	208	struct type *i386_mmx_type;
c131fcee	209	struct type *i386_ymm_type;
27067745	210	struct type *i387_ext_type;
7ad10968 HZ	211
7ad10968 HZ	212	/* Process record/replay target. */
cf648174 HZ	213	/* The map for registers because the AMD64's registers order
	214	in GDB is not same as I386 instructions. */
	215	const int *record_regmap;
7ad10968 HZ	216	/* Parse intx80 args. */
	217	int (i386_intx80_record) (struct regcache regcache);
	218	/* Parse sysenter args. */
	219	int (i386_sysenter_record) (struct regcache regcache);
cf648174 HZ	220	/* Parse syscall args. */
cf648174 HZ	221	int (i386_syscall_record) (struct regcache regcache);
96297dab MK	222	};
	223
	224	/* Floating-point registers. */
	225
96297dab MK	226	/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
	227	(at most) in the FPU, but are zero-extended to 32 bits in GDB's
	228	register cache. */
	229
23a34459 AC	230	/* Return non-zero if REGNUM matches the FP register and the FP
23a34459 AC	231	register set is active. */
20a6ec49 MD	232	extern int i386_fp_regnum_p (struct gdbarch *, int);
20a6ec49 MD	233	extern int i386_fpc_regnum_p (struct gdbarch *, int);
96297dab	234
a3386186 MK	235	/* Register numbers of various important registers. */
a3386186 MK	236
bcf48cc7 MK	237	enum i386_regnum
	238	{
	239	I386_EAX_REGNUM, /* %eax */
	240	I386_ECX_REGNUM, /* %ecx */
	241	I386_EDX_REGNUM, /* %edx */
	242	I386_EBX_REGNUM, /* %ebx */
	243	I386_ESP_REGNUM, /* %esp */
	244	I386_EBP_REGNUM, /* %ebp */
	245	I386_ESI_REGNUM, /* %esi */
	246	I386_EDI_REGNUM, /* %edi */
	247	I386_EIP_REGNUM, /* %eip */
	248	I386_EFLAGS_REGNUM, /* %eflags */
2666fb59 MK	249	I386_CS_REGNUM, /* %cs */
2666fb59 MK	250	I386_SS_REGNUM, /* %ss */
e9ff708b AC	251	I386_DS_REGNUM, /* %ds */
	252	I386_ES_REGNUM, /* %es */
	253	I386_FS_REGNUM, /* %fs */
	254	I386_GS_REGNUM, /* %gs */
90884b2b	255	I386_ST0_REGNUM, /* %st(0) */
c131fcee L	256	I386_MXCSR_REGNUM = 40, /* %mxcsr */
	257	I386_YMM0H_REGNUM, /* %ymm0h */
	258	I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7
bcf48cc7	259	};
a3386186	260
cf648174 HZ	261	/* Register numbers of RECORD_REGMAP. */
	262
	263	enum record_i386_regnum
	264	{
	265	X86_RECORD_REAX_REGNUM,
	266	X86_RECORD_RECX_REGNUM,
	267	X86_RECORD_REDX_REGNUM,
	268	X86_RECORD_REBX_REGNUM,
	269	X86_RECORD_RESP_REGNUM,
	270	X86_RECORD_REBP_REGNUM,
	271	X86_RECORD_RESI_REGNUM,
	272	X86_RECORD_REDI_REGNUM,
	273	X86_RECORD_R8_REGNUM,
	274	X86_RECORD_R9_REGNUM,
	275	X86_RECORD_R10_REGNUM,
	276	X86_RECORD_R11_REGNUM,
	277	X86_RECORD_R12_REGNUM,
	278	X86_RECORD_R13_REGNUM,
	279	X86_RECORD_R14_REGNUM,
	280	X86_RECORD_R15_REGNUM,
	281	X86_RECORD_REIP_REGNUM,
	282	X86_RECORD_EFLAGS_REGNUM,
	283	X86_RECORD_CS_REGNUM,
	284	X86_RECORD_SS_REGNUM,
	285	X86_RECORD_DS_REGNUM,
	286	X86_RECORD_ES_REGNUM,
	287	X86_RECORD_FS_REGNUM,
	288	X86_RECORD_GS_REGNUM,
	289	};
	290
8201327c	291	#define I386_NUM_GREGS 16
8201327c MK	292	#define I386_NUM_XREGS 9
8201327c MK	293
90884b2b	294	#define I386_SSE_NUM_REGS (I386_MXCSR_REGNUM + 1)
c131fcee	295	#define I386_AVX_NUM_REGS (I386_YMM7H_REGNUM + 1)
8201327c	296
00f8375e MK	297	/* Size of the largest register. */
	298	#define I386_MAX_REGISTER_SIZE 16
	299
5ae96ec1	300	/* Types for i386-specific registers. */
27067745	301	extern struct type i387_ext_type (struct gdbarch gdbarch);
794ac428	302
1ba53b71 L	303	/* Checks of different pseudo-registers. */
	304	extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
	305	extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
	306	extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
c131fcee L	307	extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
c131fcee L	308	extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
1ba53b71 L	309
	310	extern const char i386_pseudo_register_name (struct gdbarch gdbarch,
	311	int regnum);
	312
3543a589 TT	313	extern void i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
	314	struct regcache *regcache,
	315	int regnum,
	316	struct value *result);
	317
1ba53b71 L	318	extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
	319	struct regcache *regcache,
	320	int regnum, const gdb_byte *buf);
	321
508fbfea MK	322	/* Segment selectors. */
508fbfea MK	323	#define I386_SEL_RPL 0x0003 /* Requester's Privilege Level mask. */
1777feb0 MS	324	#define I386_SEL_UPL 0x0003 /* User Privilige Level. */
1777feb0 MS	325	#define I386_SEL_KPL 0x0000 /* Kernel Privilige Level. */
508fbfea	326
237fc4c9 PA	327	/* The length of the longest i386 instruction (according to
	328	include/asm-i386/kprobes.h in Linux 2.6. */
	329	#define I386_MAX_INSN_LEN (16)
	330
1cce71eb	331	/* Functions exported from i386-tdep.c. */
e17a4113 UW	332	extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
e17a4113 UW	333	CORE_ADDR pc, char *name);
1777feb0 MS	334	extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
1777feb0 MS	335	CORE_ADDR pc);
1cce71eb	336
4bd207ef TG	337	/* Return whether the THIS_FRAME corresponds to a sigtramp routine. */
	338	extern int i386_sigtramp_p (struct frame_info *this_frame);
	339
38c968cf AC	340	/* Return non-zero if REGNUM is a member of the specified group. */
	341	extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
	342	struct reggroup *group);
	343
20187ed5 MK	344	/* Supply register REGNUM from the general-purpose register set REGSET
	345	to register cache REGCACHE. If REGNUM is -1, do this for all
	346	registers in REGSET. */
	347	extern void i386_supply_gregset (const struct regset *regset,
	348	struct regcache *regcache, int regnum,
	349	const void *gregs, size_t len);
3d171c85 MK	350
	351	/* Collect register REGNUM from the register cache REGCACHE and store
	352	it in the buffer specified by GREGS and LEN as described by the
	353	general-purpose register set REGSET. If REGNUM is -1, do this for
	354	all registers in REGSET. */
	355	extern void i386_collect_gregset (const struct regset *regset,
	356	const struct regcache *regcache,
	357	int regnum, void *gregs, size_t len);
20187ed5	358
8446b36a MK	359	/* Return the appropriate register set for the core section identified
	360	by SECT_NAME and SECT_SIZE. */
	361	extern const struct regset *
	362	i386_regset_from_core_section (struct gdbarch *gdbarch,
	363	const char *sect_name, size_t sect_size);
	364
237fc4c9	365
b55078be DE	366	extern struct displaced_step_closure *i386_displaced_step_copy_insn
	367	(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
	368	struct regcache *regs);
237fc4c9 PA	369	extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
	370	struct displaced_step_closure *closure,
	371	CORE_ADDR from, CORE_ADDR to,
	372	struct regcache *regs);
	373
8201327c MK	374	/* Initialize a basic ELF architecture variant. */
	375	extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);
	376
	377	/* Initialize a SVR4 architecture variant. */
	378	extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
a6b808b4 HZ	379
	380	extern int i386_process_record (struct gdbarch *gdbarch,
	381	struct regcache *regcache, CORE_ADDR addr);
55aa24fb	382
de0b6abb	383	\f
8201327c	384
de0b6abb	385	/* Functions and variables exported from i386bsd-tdep.c. */
8201327c	386
3cac699e	387	extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
5d93ae8c MK	388	extern CORE_ADDR i386fbsd_sigtramp_start_addr;
	389	extern CORE_ADDR i386fbsd_sigtramp_end_addr;
	390	extern CORE_ADDR i386obsd_sigtramp_start_addr;
	391	extern CORE_ADDR i386obsd_sigtramp_end_addr;
de0b6abb MK	392	extern int i386fbsd4_sc_reg_offset[];
	393	extern int i386fbsd_sc_reg_offset[];
	394	extern int i386nbsd_sc_reg_offset[];
	395	extern int i386obsd_sc_reg_offset[];
	396	extern int i386bsd_sc_reg_offset[];
3ce1502b	397
55aa24fb SDJ	398	/* SystemTap related functions. */
	399
	400	extern int i386_stap_is_single_operand (struct gdbarch *gdbarch,
	401	const char *s);
	402
	403	extern int i386_stap_parse_special_token (struct gdbarch *gdbarch,
	404	struct stap_parse_info *p);
	405
96297dab	406	#endif /* i386-tdep.h */