[deliverable/binutils-gdb.git] / gdb / i386-tdep.h

/* Target-dependent code for the i386.

   Copyright (C) 2001-2014 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef I386_TDEP_H
#define I386_TDEP_H

struct frame_info;
struct gdbarch;
struct reggroup;
struct regset;
struct regcache;

/* GDB's i386 target supports both the 32-bit Intel Architecture
   (IA-32) and the 64-bit AMD x86-64 architecture.  Internally it uses
   a similar register layout for both.

   - General purpose registers
   - FPU data registers
   - FPU control registers
   - SSE data registers
   - SSE control register

   The general purpose registers for the x86-64 architecture are quite
   different from IA-32.  Therefore, gdbarch_fp0_regnum
   determines the register number at which the FPU data registers
   start.  The number of FPU data and control registers is the same
   for both architectures.  The number of SSE registers however,
   differs and is determined by the num_xmm_regs member of `struct
   gdbarch_tdep'.  */

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* i386 architecture specific information.  */
struct gdbarch_tdep
{
  /* General-purpose registers.  */
  struct regset *gregset;
  int *gregset_reg_offset;
  int gregset_num_regs;
  size_t sizeof_gregset;

  /* Floating-point registers.  */
  struct regset *fpregset;
  size_t sizeof_fpregset;

  /* XSAVE extended state.  */
  struct regset *xstateregset;

  /* Register number for %st(0).  The register numbers for the other
     registers follow from this one.  Set this to -1 to indicate the
     absence of an FPU.  */
  int st0_regnum;

  /* Number of MMX registers.  */
  int num_mmx_regs;

  /* Register number for %mm0.  Set this to -1 to indicate the absence
     of MMX support.  */
  int mm0_regnum;

  /* Number of pseudo YMM registers.  */
  int num_ymm_regs;

  /* Register number for %ymm0.  Set this to -1 to indicate the absence
     of pseudo YMM register support.  */
  int ymm0_regnum;

  /* Number of AVX512 OpMask registers (K-registers)  */
  int num_k_regs;

  /* Register number for %k0.  Set this to -1 to indicate the absence
     of AVX512 OpMask register support.  */
  int k0_regnum;

  /* Number of pseudo ZMM registers ($zmm0-$zmm31).  */
  int num_zmm_regs;

  /* Register number for %zmm0.  Set this to -1 to indicate the absence
     of pseudo ZMM register support.  */
  int zmm0_regnum;

  /* Number of byte registers.  */
  int num_byte_regs;

  /* Register pseudo number for %al.  */
  int al_regnum;

  /* Number of pseudo word registers.  */
  int num_word_regs;

  /* Register number for %ax.  */
  int ax_regnum;

  /* Number of pseudo dword registers.  */
  int num_dword_regs;

  /* Register number for %eax.  Set this to -1 to indicate the absence
     of pseudo dword register support.  */
  int eax_regnum;

  /* Number of core registers.  */
  int num_core_regs;

  /* Number of SSE registers.  */
  int num_xmm_regs;

  /* Number of SSE registers added in AVX512.  */
  int num_xmm_avx512_regs;

  /* Register number of XMM16, the first XMM register added in AVX512.  */
  int xmm16_regnum;

  /* Number of YMM registers added in AVX512.  */
  int num_ymm_avx512_regs;

  /* Register number of YMM16, the first YMM register added in AVX512.  */
  int ymm16_regnum;

  /* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
     register), excluding the x87 bit, which are supported by this GDB.  */

  uint64_t xcr0;

  /* Offset of XCR0 in XSAVE extended state.  */
  int xsave_xcr0_offset;

  /* Register names.  */
  const char **register_names;

  /* Register number for %ymm0h.  Set this to -1 to indicate the absence
     of upper YMM register support.  */
  int ymm0h_regnum;

  /* Upper YMM register names.  Only used for tdesc_numbered_register.  */
  const char **ymmh_register_names;

  /* Register number for %ymm16h.  Set this to -1 to indicate the absence
  of support for YMM16-31.  */
  int ymm16h_regnum;

  /* YMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char **ymm16h_register_names;

  /* Register number for %bnd0r.  Set this to -1 to indicate the absence
     bound registers.  */
  int bnd0r_regnum;

  /* Register number for pseudo register %bnd0.  Set this to -1 to indicate the absence
     bound registers.  */
  int bnd0_regnum;

  /* Register number for %bndcfgu. Set this to -1 to indicate the absence
     bound control registers.  */
  int bndcfgu_regnum;

  /* MPX register names.  Only used for tdesc_numbered_register.  */
  const char **mpx_register_names;

  /* Register number for %zmm0h.  Set this to -1 to indicate the absence
     of ZMM_HI256 register support.  */
  int zmm0h_regnum;

  /* OpMask register names.  */
  const char **k_register_names;

  /* ZMM register names.  Only used for tdesc_numbered_register.  */
  const char **zmmh_register_names;

  /* XMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char **xmm_avx512_register_names;

  /* YMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char **ymm_avx512_register_names;

  /* Target description.  */
  const struct target_desc *tdesc;

  /* Register group function.  */
  const void *register_reggroup_p;

  /* Offset of saved PC in jmp_buf.  */
  int jb_pc_offset;

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Address range where sigtramp lives.  */
  CORE_ADDR sigtramp_start;
  CORE_ADDR sigtramp_end;

  /* Detect sigtramp.  */
  int (*sigtramp_p) (struct frame_info *);

  /* Get address of sigcontext for sigtramp.  */
  CORE_ADDR (*sigcontext_addr) (struct frame_info *);

  /* Offset of registers in `struct sigcontext'.  */
  int *sc_reg_offset;
  int sc_num_regs;

  /* Offset of saved PC and SP in `struct sigcontext'.  Usage of these
     is deprecated, please use `sc_reg_offset' instead.  */
  int sc_pc_offset;
  int sc_sp_offset;

  /* ISA-specific data types.  */
  struct type *i386_mmx_type;
  struct type *i386_ymm_type;
  struct type *i386_zmm_type;
  struct type *i387_ext_type;
  struct type *i386_bnd_type;

  /* Process record/replay target.  */
  /* The map for registers because the AMD64's registers order
     in GDB is not same as I386 instructions.  */
  const int *record_regmap;
  /* Parse intx80 args.  */
  int (*i386_intx80_record) (struct regcache *regcache);
  /* Parse sysenter args.  */
  int (*i386_sysenter_record) (struct regcache *regcache);
  /* Parse syscall args.  */
  int (*i386_syscall_record) (struct regcache *regcache);
};

/* Floating-point registers.  */

/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
   (at most) in the FPU, but are zero-extended to 32 bits in GDB's
   register cache.  */

/* Return non-zero if REGNUM matches the FP register and the FP
   register set is active.  */
extern int i386_fp_regnum_p (struct gdbarch *, int);
extern int i386_fpc_regnum_p (struct gdbarch *, int);

/* Register numbers of various important registers.  */

enum i386_regnum
{
  I386_EAX_REGNUM,		/* %eax */
  I386_ECX_REGNUM,		/* %ecx */
  I386_EDX_REGNUM,		/* %edx */
  I386_EBX_REGNUM,		/* %ebx */
  I386_ESP_REGNUM,		/* %esp */
  I386_EBP_REGNUM,		/* %ebp */
  I386_ESI_REGNUM,		/* %esi */
  I386_EDI_REGNUM,		/* %edi */
  I386_EIP_REGNUM,		/* %eip */
  I386_EFLAGS_REGNUM,		/* %eflags */
  I386_CS_REGNUM,		/* %cs */
  I386_SS_REGNUM,		/* %ss */
  I386_DS_REGNUM,		/* %ds */
  I386_ES_REGNUM,		/* %es */
  I386_FS_REGNUM,		/* %fs */
  I386_GS_REGNUM,		/* %gs */
  I386_ST0_REGNUM,		/* %st(0) */
  I386_MXCSR_REGNUM = 40,	/* %mxcsr */ 
  I386_YMM0H_REGNUM,		/* %ymm0h */
  I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7,
  I386_BND0R_REGNUM,
  I386_BND3R_REGNUM = I386_BND0R_REGNUM + 3,
  I386_BNDCFGU_REGNUM,
  I386_BNDSTATUS_REGNUM,
  I386_K0_REGNUM,		/* %k0 */
  I386_K7_REGNUM = I386_K0_REGNUM + 7,
  I386_ZMM0H_REGNUM,		/* %zmm0h */
  I386_ZMM7H_REGNUM = I386_ZMM0H_REGNUM + 7
};

/* Register numbers of RECORD_REGMAP.  */

enum record_i386_regnum
{
  X86_RECORD_REAX_REGNUM,
  X86_RECORD_RECX_REGNUM,
  X86_RECORD_REDX_REGNUM,
  X86_RECORD_REBX_REGNUM,
  X86_RECORD_RESP_REGNUM,
  X86_RECORD_REBP_REGNUM,
  X86_RECORD_RESI_REGNUM,
  X86_RECORD_REDI_REGNUM,
  X86_RECORD_R8_REGNUM,
  X86_RECORD_R9_REGNUM,
  X86_RECORD_R10_REGNUM,
  X86_RECORD_R11_REGNUM,
  X86_RECORD_R12_REGNUM,
  X86_RECORD_R13_REGNUM,
  X86_RECORD_R14_REGNUM,
  X86_RECORD_R15_REGNUM,
  X86_RECORD_REIP_REGNUM,
  X86_RECORD_EFLAGS_REGNUM,
  X86_RECORD_CS_REGNUM,
  X86_RECORD_SS_REGNUM,
  X86_RECORD_DS_REGNUM,
  X86_RECORD_ES_REGNUM,
  X86_RECORD_FS_REGNUM,
  X86_RECORD_GS_REGNUM,
};

#define I386_NUM_GREGS	16
#define I386_NUM_XREGS  9

#define I386_SSE_NUM_REGS	(I386_MXCSR_REGNUM + 1)
#define I386_AVX_NUM_REGS	(I386_YMM7H_REGNUM + 1)
#define I386_MPX_NUM_REGS	(I386_BNDSTATUS_REGNUM + 1)
#define I386_AVX512_NUM_REGS	(I386_ZMM7H_REGNUM + 1)

/* Size of the largest register.  */
#define I386_MAX_REGISTER_SIZE	64

/* Types for i386-specific registers.  */
extern struct type *i387_ext_type (struct gdbarch *gdbarch);

/* Checks of different pseudo-registers.  */
extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_avx512_regnum_p (struct gdbarch * gdbarch, int regnum);
extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_k_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum);

extern const char *i386_pseudo_register_name (struct gdbarch *gdbarch,
					      int regnum);
extern struct type *i386_pseudo_register_type (struct gdbarch *gdbarch,
					       int regnum);

extern void i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
						  struct regcache *regcache,
						  int regnum,
						  struct value *result);

extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
					struct regcache *regcache,
					int regnum, const gdb_byte *buf);

/* Segment selectors.  */
#define I386_SEL_RPL	0x0003  /* Requester's Privilege Level mask.  */
#define I386_SEL_UPL	0x0003	/* User Privilige Level.  */
#define I386_SEL_KPL	0x0000	/* Kernel Privilige Level.  */

/* The length of the longest i386 instruction (according to
   include/asm-i386/kprobes.h in Linux 2.6.  */
#define I386_MAX_INSN_LEN (16)

/* Functions exported from i386-tdep.c.  */
extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
					       CORE_ADDR pc, char *name);
extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
					  CORE_ADDR pc);

/* Return whether the THIS_FRAME corresponds to a sigtramp routine.  */
extern int i386_sigtramp_p (struct frame_info *this_frame);

/* Return non-zero if REGNUM is a member of the specified group.  */
extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
				     struct reggroup *group);

/* Supply register REGNUM from the general-purpose register set REGSET
   to register cache REGCACHE.  If REGNUM is -1, do this for all
   registers in REGSET.  */
extern void i386_supply_gregset (const struct regset *regset,
				 struct regcache *regcache, int regnum,
				 const void *gregs, size_t len);

/* Collect register REGNUM from the register cache REGCACHE and store
   it in the buffer specified by GREGS and LEN as described by the
   general-purpose register set REGSET.  If REGNUM is -1, do this for
   all registers in REGSET.  */
extern void i386_collect_gregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *gregs, size_t len);

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */
extern const struct regset *
  i386_regset_from_core_section (struct gdbarch *gdbarch,
				 const char *sect_name, size_t sect_size);


extern struct displaced_step_closure *i386_displaced_step_copy_insn
  (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
   struct regcache *regs);
extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
				       struct displaced_step_closure *closure,
				       CORE_ADDR from, CORE_ADDR to,
				       struct regcache *regs);

/* Initialize a basic ELF architecture variant.  */
extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);

/* Initialize a SVR4 architecture variant.  */
extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);

extern int i386_process_record (struct gdbarch *gdbarch,
                                struct regcache *regcache, CORE_ADDR addr);

\f

/* Functions and variables exported from i386bsd-tdep.c.  */

extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
extern CORE_ADDR i386fbsd_sigtramp_start_addr;
extern CORE_ADDR i386fbsd_sigtramp_end_addr;
extern CORE_ADDR i386obsd_sigtramp_start_addr;
extern CORE_ADDR i386obsd_sigtramp_end_addr;
extern int i386fbsd4_sc_reg_offset[];
extern int i386fbsd_sc_reg_offset[];
extern int i386nbsd_sc_reg_offset[];
extern int i386obsd_sc_reg_offset[];
extern int i386bsd_sc_reg_offset[];

/* SystemTap related functions.  */

extern int i386_stap_is_single_operand (struct gdbarch *gdbarch,
					const char *s);

extern int i386_stap_parse_special_token (struct gdbarch *gdbarch,
					  struct stap_parse_info *p);

#endif /* i386-tdep.h */
Commit	Line	Data
5716833c MK	1	/* Target-dependent code for the i386.
5716833c MK	2
ecd75fc8	3	Copyright (C) 2001-2014 Free Software Foundation, Inc.
9a82579f JS	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
9a82579f JS	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9a82579f JS	19
	20	#ifndef I386_TDEP_H
	21	#define I386_TDEP_H
	22
da3331ec	23	struct frame_info;
5716833c MK	24	struct gdbarch;
5716833c MK	25	struct reggroup;
c783cbd6	26	struct regset;
5439edaa	27	struct regcache;
da3331ec	28
96297dab MK	29	/* GDB's i386 target supports both the 32-bit Intel Architecture
	30	(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
	31	a similar register layout for both.
	32
	33	- General purpose registers
	34	- FPU data registers
	35	- FPU control registers
	36	- SSE data registers
	37	- SSE control register
	38
	39	The general purpose registers for the x86-64 architecture are quite
3e8c568d	40	different from IA-32. Therefore, gdbarch_fp0_regnum
96297dab MK	41	determines the register number at which the FPU data registers
	42	start. The number of FPU data and control registers is the same
	43	for both architectures. The number of SSE registers however,
	44	differs and is determined by the num_xmm_regs member of `struct
	45	gdbarch_tdep'. */
	46
8201327c	47	/* Convention for returning structures. */
3ce1502b	48
8201327c MK	49	enum struct_return
	50	{
	51	pcc_struct_return, /* Return "short" structures in memory. */
	52	reg_struct_return /* Return "short" structures in registers. */
3ce1502b MK	53	};
3ce1502b MK	54
96297dab MK	55	/* i386 architecture specific information. */
	56	struct gdbarch_tdep
	57	{
473f17b0 MK	58	/* General-purpose registers. */
	59	struct regset *gregset;
	60	int *gregset_reg_offset;
	61	int gregset_num_regs;
	62	size_t sizeof_gregset;
	63
	64	/* Floating-point registers. */
	65	struct regset *fpregset;
	66	size_t sizeof_fpregset;
	67
c131fcee L	68	/* XSAVE extended state. */
	69	struct regset *xstateregset;
	70
5716833c MK	71	/* Register number for %st(0). The register numbers for the other
	72	registers follow from this one. Set this to -1 to indicate the
	73	absence of an FPU. */
	74	int st0_regnum;
	75
1ba53b71 L	76	/* Number of MMX registers. */
	77	int num_mmx_regs;
	78
5716833c MK	79	/* Register number for %mm0. Set this to -1 to indicate the absence
	80	of MMX support. */
	81	int mm0_regnum;
	82
c131fcee L	83	/* Number of pseudo YMM registers. */
	84	int num_ymm_regs;
	85
	86	/* Register number for %ymm0. Set this to -1 to indicate the absence
	87	of pseudo YMM register support. */
	88	int ymm0_regnum;
	89
01f9f808 MS	90	/* Number of AVX512 OpMask registers (K-registers) */
	91	int num_k_regs;
	92
	93	/* Register number for %k0. Set this to -1 to indicate the absence
	94	of AVX512 OpMask register support. */
	95	int k0_regnum;
	96
	97	/* Number of pseudo ZMM registers ($zmm0-$zmm31). */
	98	int num_zmm_regs;
	99
	100	/* Register number for %zmm0. Set this to -1 to indicate the absence
	101	of pseudo ZMM register support. */
	102	int zmm0_regnum;
	103
1ba53b71 L	104	/* Number of byte registers. */
	105	int num_byte_regs;
	106
	107	/* Register pseudo number for %al. */
	108	int al_regnum;
	109
	110	/* Number of pseudo word registers. */
	111	int num_word_regs;
	112
	113	/* Register number for %ax. */
	114	int ax_regnum;
	115
	116	/* Number of pseudo dword registers. */
	117	int num_dword_regs;
	118
	119	/* Register number for %eax. Set this to -1 to indicate the absence
	120	of pseudo dword register support. */
	121	int eax_regnum;
	122
90884b2b L	123	/* Number of core registers. */
	124	int num_core_regs;
	125
96297dab MK	126	/* Number of SSE registers. */
96297dab MK	127	int num_xmm_regs;
8201327c	128
01f9f808 MS	129	/* Number of SSE registers added in AVX512. */
	130	int num_xmm_avx512_regs;
	131
	132	/* Register number of XMM16, the first XMM register added in AVX512. */
	133	int xmm16_regnum;
	134
	135	/* Number of YMM registers added in AVX512. */
	136	int num_ymm_avx512_regs;
	137
	138	/* Register number of YMM16, the first YMM register added in AVX512. */
	139	int ymm16_regnum;
	140
c131fcee	141	/* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
1777feb0 MS	142	register), excluding the x87 bit, which are supported by this GDB. */
1777feb0 MS	143
c131fcee L	144	uint64_t xcr0;
	145
	146	/* Offset of XCR0 in XSAVE extended state. */
	147	int xsave_xcr0_offset;
	148
90884b2b L	149	/* Register names. */
	150	const char **register_names;
	151
c131fcee L	152	/* Register number for %ymm0h. Set this to -1 to indicate the absence
	153	of upper YMM register support. */
	154	int ymm0h_regnum;
	155
	156	/* Upper YMM register names. Only used for tdesc_numbered_register. */
	157	const char **ymmh_register_names;
	158
01f9f808 MS	159	/* Register number for %ymm16h. Set this to -1 to indicate the absence
	160	of support for YMM16-31. */
	161	int ymm16h_regnum;
	162
	163	/* YMM16-31 register names. Only used for tdesc_numbered_register. */
	164	const char **ymm16h_register_names;
	165
1dbcd68c WT	166	/* Register number for %bnd0r. Set this to -1 to indicate the absence
	167	bound registers. */
	168	int bnd0r_regnum;
	169
	170	/* Register number for pseudo register %bnd0. Set this to -1 to indicate the absence
	171	bound registers. */
	172	int bnd0_regnum;
	173
	174	/* Register number for %bndcfgu. Set this to -1 to indicate the absence
	175	bound control registers. */
	176	int bndcfgu_regnum;
	177
	178	/* MPX register names. Only used for tdesc_numbered_register. */
	179	const char **mpx_register_names;
	180
01f9f808 MS	181	/* Register number for %zmm0h. Set this to -1 to indicate the absence
	182	of ZMM_HI256 register support. */
	183	int zmm0h_regnum;
	184
	185	/* OpMask register names. */
	186	const char **k_register_names;
	187
	188	/* ZMM register names. Only used for tdesc_numbered_register. */
	189	const char **zmmh_register_names;
	190
	191	/* XMM16-31 register names. Only used for tdesc_numbered_register. */
	192	const char **xmm_avx512_register_names;
	193
	194	/* YMM16-31 register names. Only used for tdesc_numbered_register. */
	195	const char **ymm_avx512_register_names;
	196
90884b2b L	197	/* Target description. */
	198	const struct target_desc *tdesc;
	199
	200	/* Register group function. */
	201	const void *register_reggroup_p;
	202
8201327c MK	203	/* Offset of saved PC in jmp_buf. */
	204	int jb_pc_offset;
	205
	206	/* Convention for returning structures. */
	207	enum struct_return struct_return;
	208
8201327c MK	209	/* Address range where sigtramp lives. */
	210	CORE_ADDR sigtramp_start;
	211	CORE_ADDR sigtramp_end;
	212
911bc6ee MK	213	/* Detect sigtramp. */
	214	int (sigtramp_p) (struct frame_info );
	215
21d0e8a4 MK	216	/* Get address of sigcontext for sigtramp. */
	217	CORE_ADDR (sigcontext_addr) (struct frame_info );
	218
a3386186 MK	219	/* Offset of registers in `struct sigcontext'. */
	220	int *sc_reg_offset;
	221	int sc_num_regs;
	222
	223	/* Offset of saved PC and SP in `struct sigcontext'. Usage of these
	224	is deprecated, please use `sc_reg_offset' instead. */
8201327c	225	int sc_pc_offset;
21d0e8a4	226	int sc_sp_offset;
794ac428 UW	227
	228	/* ISA-specific data types. */
	229	struct type *i386_mmx_type;
c131fcee	230	struct type *i386_ymm_type;
01f9f808	231	struct type *i386_zmm_type;
27067745	232	struct type *i387_ext_type;
1dbcd68c	233	struct type *i386_bnd_type;
7ad10968 HZ	234
7ad10968 HZ	235	/* Process record/replay target. */
cf648174 HZ	236	/* The map for registers because the AMD64's registers order
	237	in GDB is not same as I386 instructions. */
	238	const int *record_regmap;
7ad10968 HZ	239	/* Parse intx80 args. */
	240	int (i386_intx80_record) (struct regcache regcache);
	241	/* Parse sysenter args. */
	242	int (i386_sysenter_record) (struct regcache regcache);
cf648174 HZ	243	/* Parse syscall args. */
cf648174 HZ	244	int (i386_syscall_record) (struct regcache regcache);
96297dab MK	245	};
	246
	247	/* Floating-point registers. */
	248
96297dab MK	249	/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
	250	(at most) in the FPU, but are zero-extended to 32 bits in GDB's
	251	register cache. */
	252
23a34459 AC	253	/* Return non-zero if REGNUM matches the FP register and the FP
23a34459 AC	254	register set is active. */
20a6ec49 MD	255	extern int i386_fp_regnum_p (struct gdbarch *, int);
20a6ec49 MD	256	extern int i386_fpc_regnum_p (struct gdbarch *, int);
96297dab	257
a3386186 MK	258	/* Register numbers of various important registers. */
a3386186 MK	259
bcf48cc7 MK	260	enum i386_regnum
	261	{
	262	I386_EAX_REGNUM, /* %eax */
	263	I386_ECX_REGNUM, /* %ecx */
	264	I386_EDX_REGNUM, /* %edx */
	265	I386_EBX_REGNUM, /* %ebx */
	266	I386_ESP_REGNUM, /* %esp */
	267	I386_EBP_REGNUM, /* %ebp */
	268	I386_ESI_REGNUM, /* %esi */
	269	I386_EDI_REGNUM, /* %edi */
	270	I386_EIP_REGNUM, /* %eip */
	271	I386_EFLAGS_REGNUM, /* %eflags */
2666fb59 MK	272	I386_CS_REGNUM, /* %cs */
2666fb59 MK	273	I386_SS_REGNUM, /* %ss */
e9ff708b AC	274	I386_DS_REGNUM, /* %ds */
	275	I386_ES_REGNUM, /* %es */
	276	I386_FS_REGNUM, /* %fs */
	277	I386_GS_REGNUM, /* %gs */
90884b2b	278	I386_ST0_REGNUM, /* %st(0) */
c131fcee L	279	I386_MXCSR_REGNUM = 40, /* %mxcsr */
c131fcee L	280	I386_YMM0H_REGNUM, /* %ymm0h */
1dbcd68c WT	281	I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7,
	282	I386_BND0R_REGNUM,
	283	I386_BND3R_REGNUM = I386_BND0R_REGNUM + 3,
	284	I386_BNDCFGU_REGNUM,
01f9f808 MS	285	I386_BNDSTATUS_REGNUM,
	286	I386_K0_REGNUM, /* %k0 */
	287	I386_K7_REGNUM = I386_K0_REGNUM + 7,
	288	I386_ZMM0H_REGNUM, /* %zmm0h */
	289	I386_ZMM7H_REGNUM = I386_ZMM0H_REGNUM + 7
bcf48cc7	290	};
a3386186	291
cf648174 HZ	292	/* Register numbers of RECORD_REGMAP. */
	293
	294	enum record_i386_regnum
	295	{
	296	X86_RECORD_REAX_REGNUM,
	297	X86_RECORD_RECX_REGNUM,
	298	X86_RECORD_REDX_REGNUM,
	299	X86_RECORD_REBX_REGNUM,
	300	X86_RECORD_RESP_REGNUM,
	301	X86_RECORD_REBP_REGNUM,
	302	X86_RECORD_RESI_REGNUM,
	303	X86_RECORD_REDI_REGNUM,
	304	X86_RECORD_R8_REGNUM,
	305	X86_RECORD_R9_REGNUM,
	306	X86_RECORD_R10_REGNUM,
	307	X86_RECORD_R11_REGNUM,
	308	X86_RECORD_R12_REGNUM,
	309	X86_RECORD_R13_REGNUM,
	310	X86_RECORD_R14_REGNUM,
	311	X86_RECORD_R15_REGNUM,
	312	X86_RECORD_REIP_REGNUM,
	313	X86_RECORD_EFLAGS_REGNUM,
	314	X86_RECORD_CS_REGNUM,
	315	X86_RECORD_SS_REGNUM,
	316	X86_RECORD_DS_REGNUM,
	317	X86_RECORD_ES_REGNUM,
	318	X86_RECORD_FS_REGNUM,
	319	X86_RECORD_GS_REGNUM,
	320	};
	321
8201327c	322	#define I386_NUM_GREGS 16
8201327c MK	323	#define I386_NUM_XREGS 9
8201327c MK	324
90884b2b	325	#define I386_SSE_NUM_REGS (I386_MXCSR_REGNUM + 1)
c131fcee	326	#define I386_AVX_NUM_REGS (I386_YMM7H_REGNUM + 1)
1dbcd68c	327	#define I386_MPX_NUM_REGS (I386_BNDSTATUS_REGNUM + 1)
01f9f808	328	#define I386_AVX512_NUM_REGS (I386_ZMM7H_REGNUM + 1)
8201327c	329
00f8375e	330	/* Size of the largest register. */
01f9f808	331	#define I386_MAX_REGISTER_SIZE 64
00f8375e	332
5ae96ec1	333	/* Types for i386-specific registers. */
27067745	334	extern struct type i387_ext_type (struct gdbarch gdbarch);
794ac428	335
1ba53b71 L	336	/* Checks of different pseudo-registers. */
	337	extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
	338	extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
	339	extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
c131fcee	340	extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808	341	extern int i386_xmm_avx512_regnum_p (struct gdbarch * gdbarch, int regnum);
c131fcee	342	extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808	343	extern int i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum);
1dbcd68c	344	extern int i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808 MS	345	extern int i386_k_regnum_p (struct gdbarch *gdbarch, int regnum);
	346	extern int i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum);
	347	extern int i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum);
1ba53b71 L	348
	349	extern const char i386_pseudo_register_name (struct gdbarch gdbarch,
	350	int regnum);
fff4548b MK	351	extern struct type i386_pseudo_register_type (struct gdbarch gdbarch,
fff4548b MK	352	int regnum);
1ba53b71	353
3543a589 TT	354	extern void i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
	355	struct regcache *regcache,
	356	int regnum,
	357	struct value *result);
	358
1ba53b71 L	359	extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
	360	struct regcache *regcache,
	361	int regnum, const gdb_byte *buf);
	362
508fbfea MK	363	/* Segment selectors. */
508fbfea MK	364	#define I386_SEL_RPL 0x0003 /* Requester's Privilege Level mask. */
1777feb0 MS	365	#define I386_SEL_UPL 0x0003 /* User Privilige Level. */
1777feb0 MS	366	#define I386_SEL_KPL 0x0000 /* Kernel Privilige Level. */
508fbfea	367
237fc4c9 PA	368	/* The length of the longest i386 instruction (according to
	369	include/asm-i386/kprobes.h in Linux 2.6. */
	370	#define I386_MAX_INSN_LEN (16)
	371
1cce71eb	372	/* Functions exported from i386-tdep.c. */
e17a4113 UW	373	extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
e17a4113 UW	374	CORE_ADDR pc, char *name);
1777feb0 MS	375	extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
1777feb0 MS	376	CORE_ADDR pc);
1cce71eb	377
4bd207ef TG	378	/* Return whether the THIS_FRAME corresponds to a sigtramp routine. */
	379	extern int i386_sigtramp_p (struct frame_info *this_frame);
	380
38c968cf AC	381	/* Return non-zero if REGNUM is a member of the specified group. */
	382	extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
	383	struct reggroup *group);
	384
20187ed5 MK	385	/* Supply register REGNUM from the general-purpose register set REGSET
	386	to register cache REGCACHE. If REGNUM is -1, do this for all
	387	registers in REGSET. */
	388	extern void i386_supply_gregset (const struct regset *regset,
	389	struct regcache *regcache, int regnum,
	390	const void *gregs, size_t len);
3d171c85 MK	391
	392	/* Collect register REGNUM from the register cache REGCACHE and store
	393	it in the buffer specified by GREGS and LEN as described by the
	394	general-purpose register set REGSET. If REGNUM is -1, do this for
	395	all registers in REGSET. */
	396	extern void i386_collect_gregset (const struct regset *regset,
	397	const struct regcache *regcache,
	398	int regnum, void *gregs, size_t len);
20187ed5	399
8446b36a MK	400	/* Return the appropriate register set for the core section identified
	401	by SECT_NAME and SECT_SIZE. */
	402	extern const struct regset *
	403	i386_regset_from_core_section (struct gdbarch *gdbarch,
	404	const char *sect_name, size_t sect_size);
	405
237fc4c9	406
b55078be DE	407	extern struct displaced_step_closure *i386_displaced_step_copy_insn
	408	(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
	409	struct regcache *regs);
237fc4c9 PA	410	extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
	411	struct displaced_step_closure *closure,
	412	CORE_ADDR from, CORE_ADDR to,
	413	struct regcache *regs);
	414
8201327c MK	415	/* Initialize a basic ELF architecture variant. */
	416	extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);
	417
	418	/* Initialize a SVR4 architecture variant. */
	419	extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
a6b808b4 HZ	420
	421	extern int i386_process_record (struct gdbarch *gdbarch,
	422	struct regcache *regcache, CORE_ADDR addr);
55aa24fb	423
de0b6abb	424	\f
8201327c	425
de0b6abb	426	/* Functions and variables exported from i386bsd-tdep.c. */
8201327c	427
3cac699e	428	extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
5d93ae8c MK	429	extern CORE_ADDR i386fbsd_sigtramp_start_addr;
	430	extern CORE_ADDR i386fbsd_sigtramp_end_addr;
	431	extern CORE_ADDR i386obsd_sigtramp_start_addr;
	432	extern CORE_ADDR i386obsd_sigtramp_end_addr;
de0b6abb MK	433	extern int i386fbsd4_sc_reg_offset[];
	434	extern int i386fbsd_sc_reg_offset[];
	435	extern int i386nbsd_sc_reg_offset[];
	436	extern int i386obsd_sc_reg_offset[];
	437	extern int i386bsd_sc_reg_offset[];
3ce1502b	438
55aa24fb SDJ	439	/* SystemTap related functions. */
	440
	441	extern int i386_stap_is_single_operand (struct gdbarch *gdbarch,
	442	const char *s);
	443
	444	extern int i386_stap_parse_special_token (struct gdbarch *gdbarch,
	445	struct stap_parse_info *p);
	446
96297dab	447	#endif /* i386-tdep.h */