2012-03-05 Tristan Gingold <gingold@adacore.com>
[deliverable/binutils-gdb.git] / gdb / i387-tdep.c
CommitLineData
c906108c 1/* Intel 387 floating point stuff.
38edeab8 2
0b302171
JB
3 Copyright (C) 1988-1989, 1991-1994, 1998-2005, 2007-2012 Free
4 Software Foundation, Inc.
c906108c 5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
a9762ec7 10 the Free Software Foundation; either version 3 of the License, or
c5aa993b 11 (at your option) any later version.
c906108c 12
c5aa993b
JM
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b 18 You should have received a copy of the GNU General Public License
a9762ec7 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS
20
21#include "defs.h"
786a90bb
MK
22#include "doublest.h"
23#include "floatformat.h"
c906108c 24#include "frame.h"
786a90bb 25#include "gdbcore.h"
c906108c
SS
26#include "inferior.h"
27#include "language.h"
4e052eda 28#include "regcache.h"
786a90bb
MK
29#include "value.h"
30
d0df8472 31#include "gdb_assert.h"
309367d4 32#include "gdb_string.h"
c906108c 33
9a82579f 34#include "i386-tdep.h"
42c466d7 35#include "i387-tdep.h"
31aeac78 36#include "i386-xstate.h"
c906108c 37
de57eccd 38/* Print the floating point number specified by RAW. */
786a90bb 39
de57eccd 40static void
27067745
UW
41print_i387_value (struct gdbarch *gdbarch,
42 const gdb_byte *raw, struct ui_file *file)
de57eccd
JM
43{
44 DOUBLEST value;
4583280c
MK
45
46 /* Using extract_typed_floating here might affect the representation
47 of certain numbers such as NaNs, even if GDB is running natively.
48 This is fine since our caller already detects such special
49 numbers and we print the hexadecimal representation anyway. */
27067745 50 value = extract_typed_floating (raw, i387_ext_type (gdbarch));
de57eccd
JM
51
52 /* We try to print 19 digits. The last digit may or may not contain
53 garbage, but we'd better print one too many. We need enough room
54 to print the value, 1 position for the sign, 1 for the decimal
55 point, 19 for the digits and 6 for the exponent adds up to 27. */
56#ifdef PRINTF_HAS_LONG_DOUBLE
61113f8b 57 fprintf_filtered (file, " %-+27.19Lg", (long double) value);
de57eccd 58#else
61113f8b 59 fprintf_filtered (file, " %-+27.19g", (double) value);
de57eccd
JM
60#endif
61}
62
63/* Print the classification for the register contents RAW. */
786a90bb 64
de57eccd 65static void
27067745
UW
66print_i387_ext (struct gdbarch *gdbarch,
67 const gdb_byte *raw, struct ui_file *file)
de57eccd
JM
68{
69 int sign;
70 int integer;
71 unsigned int exponent;
72 unsigned long fraction[2];
73
74 sign = raw[9] & 0x80;
75 integer = raw[7] & 0x80;
76 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
77 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
78 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
79 | (raw[5] << 8) | raw[4]);
80
81 if (exponent == 0x7fff && integer)
82 {
83 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
84 /* Infinity. */
61113f8b 85 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
de57eccd
JM
86 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
87 /* Real Indefinite (QNaN). */
61113f8b 88 fputs_unfiltered (" Real Indefinite (QNaN)", file);
de57eccd
JM
89 else if (fraction[1] & 0x40000000)
90 /* QNaN. */
61113f8b 91 fputs_filtered (" QNaN", file);
de57eccd
JM
92 else
93 /* SNaN. */
61113f8b 94 fputs_filtered (" SNaN", file);
de57eccd
JM
95 }
96 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
97 /* Normal. */
27067745 98 print_i387_value (gdbarch, raw, file);
de57eccd
JM
99 else if (exponent == 0x0000)
100 {
101 /* Denormal or zero. */
27067745 102 print_i387_value (gdbarch, raw, file);
de57eccd
JM
103
104 if (integer)
105 /* Pseudo-denormal. */
61113f8b 106 fputs_filtered (" Pseudo-denormal", file);
de57eccd
JM
107 else if (fraction[0] || fraction[1])
108 /* Denormal. */
61113f8b 109 fputs_filtered (" Denormal", file);
de57eccd
JM
110 }
111 else
112 /* Unsupported. */
61113f8b 113 fputs_filtered (" Unsupported", file);
de57eccd
JM
114}
115
ad5f7d6e
PA
116/* Print the status word STATUS. If STATUS_P is false, then STATUS
117 was unavailable. */
786a90bb 118
de57eccd 119static void
ad5f7d6e
PA
120print_i387_status_word (int status_p,
121 unsigned int status, struct ui_file *file)
de57eccd 122{
ad5f7d6e
PA
123 fprintf_filtered (file, "Status Word: ");
124 if (!status_p)
125 {
126 fprintf_filtered (file, "%s\n", _("<unavailable>"));
127 return;
128 }
129
130 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
61113f8b
MK
131 fputs_filtered (" ", file);
132 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
133 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
134 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
135 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
136 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
137 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
138 fputs_filtered (" ", file);
139 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
140 fputs_filtered (" ", file);
141 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
142 fputs_filtered (" ", file);
143 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
144 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
145 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
146 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
147
148 fputs_filtered ("\n", file);
149
150 fprintf_filtered (file,
151 " TOP: %d\n", ((status >> 11) & 7));
de57eccd
JM
152}
153
ad5f7d6e
PA
154/* Print the control word CONTROL. If CONTROL_P is false, then
155 CONTROL was unavailable. */
786a90bb 156
de57eccd 157static void
ad5f7d6e
PA
158print_i387_control_word (int control_p,
159 unsigned int control, struct ui_file *file)
de57eccd 160{
ad5f7d6e
PA
161 fprintf_filtered (file, "Control Word: ");
162 if (!control_p)
163 {
164 fprintf_filtered (file, "%s\n", _("<unavailable>"));
165 return;
166 }
167
168 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
61113f8b
MK
169 fputs_filtered (" ", file);
170 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
171 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
172 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
173 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
174 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
175 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
de57eccd 176
61113f8b 177 fputs_filtered ("\n", file);
de57eccd 178
61113f8b 179 fputs_filtered (" PC: ", file);
de57eccd
JM
180 switch ((control >> 8) & 3)
181 {
182 case 0:
61113f8b 183 fputs_filtered ("Single Precision (24-bits)\n", file);
de57eccd
JM
184 break;
185 case 1:
61113f8b 186 fputs_filtered ("Reserved\n", file);
de57eccd
JM
187 break;
188 case 2:
61113f8b 189 fputs_filtered ("Double Precision (53-bits)\n", file);
de57eccd
JM
190 break;
191 case 3:
61113f8b 192 fputs_filtered ("Extended Precision (64-bits)\n", file);
de57eccd
JM
193 break;
194 }
195
61113f8b 196 fputs_filtered (" RC: ", file);
de57eccd
JM
197 switch ((control >> 10) & 3)
198 {
199 case 0:
61113f8b 200 fputs_filtered ("Round to nearest\n", file);
de57eccd
JM
201 break;
202 case 1:
61113f8b 203 fputs_filtered ("Round down\n", file);
de57eccd
JM
204 break;
205 case 2:
61113f8b 206 fputs_filtered ("Round up\n", file);
de57eccd
JM
207 break;
208 case 3:
61113f8b 209 fputs_filtered ("Round toward zero\n", file);
de57eccd
JM
210 break;
211 }
212}
213
9b949a49 214/* Print out the i387 floating point state. Note that we ignore FRAME
7d8d2918
MK
215 in the code below. That's OK since floating-point registers are
216 never saved on the stack. */
217
de57eccd 218void
61113f8b 219i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
8e186fd6 220 struct frame_info *frame, const char *args)
de57eccd 221{
5716833c 222 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
1d70089a 223 ULONGEST fctrl;
ad5f7d6e 224 int fctrl_p;
1d70089a 225 ULONGEST fstat;
ad5f7d6e 226 int fstat_p;
1d70089a 227 ULONGEST ftag;
ad5f7d6e 228 int ftag_p;
1d70089a 229 ULONGEST fiseg;
ad5f7d6e 230 int fiseg_p;
1d70089a 231 ULONGEST fioff;
ad5f7d6e 232 int fioff_p;
1d70089a 233 ULONGEST foseg;
ad5f7d6e 234 int foseg_p;
1d70089a 235 ULONGEST fooff;
ad5f7d6e 236 int fooff_p;
1d70089a 237 ULONGEST fop;
ad5f7d6e 238 int fop_p;
de57eccd 239 int fpreg;
ad5f7d6e 240 int fpreg_p;
de57eccd 241 int top;
ad5f7d6e 242 int top_p;
de57eccd 243
5716833c
MK
244 gdb_assert (gdbarch == get_frame_arch (frame));
245
ad5f7d6e
PA
246 fctrl_p = read_frame_register_unsigned (frame,
247 I387_FCTRL_REGNUM (tdep), &fctrl);
248 fstat_p = read_frame_register_unsigned (frame,
249 I387_FSTAT_REGNUM (tdep), &fstat);
250 ftag_p = read_frame_register_unsigned (frame,
251 I387_FTAG_REGNUM (tdep), &ftag);
252 fiseg_p = read_frame_register_unsigned (frame,
253 I387_FISEG_REGNUM (tdep), &fiseg);
254 fioff_p = read_frame_register_unsigned (frame,
255 I387_FIOFF_REGNUM (tdep), &fioff);
256 foseg_p = read_frame_register_unsigned (frame,
257 I387_FOSEG_REGNUM (tdep), &foseg);
258 fooff_p = read_frame_register_unsigned (frame,
259 I387_FOOFF_REGNUM (tdep), &fooff);
260 fop_p = read_frame_register_unsigned (frame,
261 I387_FOP_REGNUM (tdep), &fop);
262
263 if (fstat_p)
de57eccd 264 {
ad5f7d6e 265 top = ((fstat >> 11) & 7);
de57eccd 266
ad5f7d6e 267 for (fpreg = 7; fpreg >= 0; fpreg--)
de57eccd 268 {
ad5f7d6e
PA
269 struct value *regval;
270 int regnum;
271 int i;
272 int tag = -1;
273
274 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
275
276 if (ftag_p)
277 {
278 tag = (ftag >> (fpreg * 2)) & 3;
279
280 switch (tag)
281 {
282 case 0:
283 fputs_filtered ("Valid ", file);
284 break;
285 case 1:
286 fputs_filtered ("Zero ", file);
287 break;
288 case 2:
289 fputs_filtered ("Special ", file);
290 break;
291 case 3:
292 fputs_filtered ("Empty ", file);
293 break;
294 }
295 }
296 else
297 fputs_filtered ("Unknown ", file);
298
299 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
300 regval = get_frame_register_value (frame, regnum);
301
302 if (value_entirely_available (regval))
303 {
304 const char *raw = value_contents (regval);
305
306 fputs_filtered ("0x", file);
307 for (i = 9; i >= 0; i--)
308 fprintf_filtered (file, "%02x", raw[i]);
309
310 if (tag != -1 && tag != 3)
311 print_i387_ext (gdbarch, raw, file);
312 }
313 else
314 fprintf_filtered (file, "%s", _("<unavailable>"));
315
316 fputs_filtered ("\n", file);
de57eccd 317 }
de57eccd
JM
318 }
319
f16a25ae 320 fputs_filtered ("\n", file);
ad5f7d6e
PA
321 print_i387_status_word (fstat_p, fstat, file);
322 print_i387_control_word (fctrl_p, fctrl, file);
61113f8b 323 fprintf_filtered (file, "Tag Word: %s\n",
ad5f7d6e 324 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
61113f8b 325 fprintf_filtered (file, "Instruction Pointer: %s:",
ad5f7d6e
PA
326 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
327 fprintf_filtered (file, "%s\n",
328 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
61113f8b 329 fprintf_filtered (file, "Operand Pointer: %s:",
ad5f7d6e
PA
330 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
331 fprintf_filtered (file, "%s\n",
332 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
61113f8b 333 fprintf_filtered (file, "Opcode: %s\n",
ad5f7d6e
PA
334 fop_p
335 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
336 : _("<unavailable>"));
de57eccd 337}
d532c08f
MK
338\f
339
83acabca
DJ
340/* Return nonzero if a value of type TYPE stored in register REGNUM
341 needs any special handling. */
342
343int
1777feb0
MS
344i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
345 struct type *type)
83acabca 346{
20a6ec49 347 if (i386_fp_regnum_p (gdbarch, regnum))
83acabca
DJ
348 {
349 /* Floating point registers must be converted unless we are
350 accessing them in their hardware type. */
27067745 351 if (type == i387_ext_type (gdbarch))
83acabca
DJ
352 return 0;
353 else
354 return 1;
355 }
356
357 return 0;
358}
359
d532c08f
MK
360/* Read a value of type TYPE from register REGNUM in frame FRAME, and
361 return its contents in TO. */
362
8dccd430 363int
d532c08f 364i387_register_to_value (struct frame_info *frame, int regnum,
8dccd430
PA
365 struct type *type, gdb_byte *to,
366 int *optimizedp, int *unavailablep)
d532c08f 367{
27067745 368 struct gdbarch *gdbarch = get_frame_arch (frame);
b4ad899f 369 gdb_byte from[I386_MAX_REGISTER_SIZE];
d532c08f 370
27067745 371 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
d532c08f
MK
372
373 /* We only support floating-point values. */
374 if (TYPE_CODE (type) != TYPE_CODE_FLT)
375 {
8a3fe4f8
AC
376 warning (_("Cannot convert floating-point register value "
377 "to non-floating-point type."));
8dccd430
PA
378 *optimizedp = *unavailablep = 0;
379 return 0;
d532c08f
MK
380 }
381
83acabca 382 /* Convert to TYPE. */
8dccd430
PA
383 if (!get_frame_register_bytes (frame, regnum, 0, TYPE_LENGTH (type),
384 from, optimizedp, unavailablep))
385 return 0;
386
27067745 387 convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
8dccd430
PA
388 *optimizedp = *unavailablep = 0;
389 return 1;
d532c08f
MK
390}
391
392/* Write the contents FROM of a value of type TYPE into register
393 REGNUM in frame FRAME. */
394
395void
396i387_value_to_register (struct frame_info *frame, int regnum,
42835c2b 397 struct type *type, const gdb_byte *from)
d532c08f 398{
27067745 399 struct gdbarch *gdbarch = get_frame_arch (frame);
b4ad899f 400 gdb_byte to[I386_MAX_REGISTER_SIZE];
d532c08f 401
27067745 402 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
d532c08f
MK
403
404 /* We only support floating-point values. */
405 if (TYPE_CODE (type) != TYPE_CODE_FLT)
406 {
8a3fe4f8
AC
407 warning (_("Cannot convert non-floating-point type "
408 "to floating-point register value."));
d532c08f
MK
409 return;
410 }
411
83acabca 412 /* Convert from TYPE. */
27067745 413 convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
d532c08f
MK
414 put_frame_register (frame, regnum, to);
415}
416\f
e750d25e 417
786a90bb 418/* Handle FSAVE and FXSAVE formats. */
e750d25e
JT
419
420/* At fsave_offset[REGNUM] you'll find the offset to the location in
421 the data structure used by the "fsave" instruction where GDB
422 register REGNUM is stored. */
423
424static int fsave_offset[] =
425{
5716833c
MK
426 28 + 0 * 10, /* %st(0) ... */
427 28 + 1 * 10,
428 28 + 2 * 10,
429 28 + 3 * 10,
430 28 + 4 * 10,
431 28 + 5 * 10,
432 28 + 6 * 10,
433 28 + 7 * 10, /* ... %st(7). */
434 0, /* `fctrl' (16 bits). */
435 4, /* `fstat' (16 bits). */
436 8, /* `ftag' (16 bits). */
437 16, /* `fiseg' (16 bits). */
438 12, /* `fioff'. */
439 24, /* `foseg' (16 bits). */
440 20, /* `fooff'. */
441 18 /* `fop' (bottom 11 bits). */
e750d25e
JT
442};
443
20a6ec49
MD
444#define FSAVE_ADDR(tdep, fsave, regnum) \
445 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
e750d25e
JT
446\f
447
41d041d6
MK
448/* Fill register REGNUM in REGCACHE with the appropriate value from
449 *FSAVE. This function masks off any of the reserved bits in
450 *FSAVE. */
e750d25e
JT
451
452void
41d041d6 453i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
e750d25e 454{
e17a4113
UW
455 struct gdbarch *gdbarch = get_regcache_arch (regcache);
456 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
457 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
b4ad899f 458 const gdb_byte *regs = fsave;
e750d25e
JT
459 int i;
460
5716833c
MK
461 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
462
20a6ec49 463 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
ed504bdf
MK
464 if (regnum == -1 || regnum == i)
465 {
466 if (fsave == NULL)
467 {
5716833c
MK
468 regcache_raw_supply (regcache, i, NULL);
469 continue;
ed504bdf
MK
470 }
471
472 /* Most of the FPU control registers occupy only 16 bits in the
473 fsave area. Give those a special treatment. */
20a6ec49
MD
474 if (i >= I387_FCTRL_REGNUM (tdep)
475 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
ed504bdf 476 {
b4ad899f 477 gdb_byte val[4];
ed504bdf 478
20a6ec49 479 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
ed504bdf 480 val[2] = val[3] = 0;
20a6ec49 481 if (i == I387_FOP_REGNUM (tdep))
ed504bdf 482 val[1] &= ((1 << 3) - 1);
5716833c 483 regcache_raw_supply (regcache, i, val);
ed504bdf
MK
484 }
485 else
20a6ec49 486 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
ed504bdf 487 }
b87bc0d8
MK
488
489 /* Provide dummy values for the SSE registers. */
20a6ec49 490 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
b87bc0d8
MK
491 if (regnum == -1 || regnum == i)
492 regcache_raw_supply (regcache, i, NULL);
20a6ec49 493 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
b87bc0d8 494 {
b4ad899f 495 gdb_byte buf[4];
b87bc0d8 496
e17a4113 497 store_unsigned_integer (buf, 4, byte_order, 0x1f80);
20a6ec49 498 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
b87bc0d8 499 }
e750d25e
JT
500}
501
502/* Fill register REGNUM (if it is a floating-point register) in *FSAVE
63b6c53f
MK
503 with the value from REGCACHE. If REGNUM is -1, do this for all
504 registers. This function doesn't touch any of the reserved bits in
505 *FSAVE. */
e750d25e
JT
506
507void
63b6c53f 508i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
e750d25e 509{
e071d1f6 510 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
b4ad899f 511 gdb_byte *regs = fsave;
e750d25e
JT
512 int i;
513
5716833c
MK
514 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
515
20a6ec49 516 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
e750d25e
JT
517 if (regnum == -1 || regnum == i)
518 {
519 /* Most of the FPU control registers occupy only 16 bits in
520 the fsave area. Give those a special treatment. */
20a6ec49
MD
521 if (i >= I387_FCTRL_REGNUM (tdep)
522 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
e750d25e 523 {
b4ad899f 524 gdb_byte buf[4];
e750d25e 525
5716833c 526 regcache_raw_collect (regcache, i, buf);
e750d25e 527
20a6ec49 528 if (i == I387_FOP_REGNUM (tdep))
e750d25e
JT
529 {
530 /* The opcode occupies only 11 bits. Make sure we
531 don't touch the other bits. */
532 buf[1] &= ((1 << 3) - 1);
20a6ec49 533 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
e750d25e 534 }
20a6ec49 535 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
e750d25e
JT
536 }
537 else
20a6ec49 538 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
e750d25e
JT
539 }
540}
541\f
542
543/* At fxsave_offset[REGNUM] you'll find the offset to the location in
544 the data structure used by the "fxsave" instruction where GDB
545 register REGNUM is stored. */
546
547static int fxsave_offset[] =
548{
5716833c 549 32, /* %st(0) through ... */
e750d25e
JT
550 48,
551 64,
552 80,
553 96,
554 112,
555 128,
5716833c
MK
556 144, /* ... %st(7) (80 bits each). */
557 0, /* `fctrl' (16 bits). */
558 2, /* `fstat' (16 bits). */
559 4, /* `ftag' (16 bits). */
560 12, /* `fiseg' (16 bits). */
561 8, /* `fioff'. */
562 20, /* `foseg' (16 bits). */
563 16, /* `fooff'. */
564 6, /* `fop' (bottom 11 bits). */
565 160 + 0 * 16, /* %xmm0 through ... */
04c8243f
MK
566 160 + 1 * 16,
567 160 + 2 * 16,
568 160 + 3 * 16,
569 160 + 4 * 16,
570 160 + 5 * 16,
571 160 + 6 * 16,
572 160 + 7 * 16,
573 160 + 8 * 16,
574 160 + 9 * 16,
575 160 + 10 * 16,
576 160 + 11 * 16,
577 160 + 12 * 16,
578 160 + 13 * 16,
579 160 + 14 * 16,
5716833c 580 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
e750d25e
JT
581};
582
20a6ec49
MD
583#define FXSAVE_ADDR(tdep, fxsave, regnum) \
584 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
5716833c
MK
585
586/* We made an unfortunate choice in putting %mxcsr after the SSE
587 registers %xmm0-%xmm7 instead of before, since it makes supporting
588 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
589 don't include the offset for %mxcsr here above. */
590
591#define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
e750d25e 592
b4ad899f 593static int i387_tag (const gdb_byte *raw);
e750d25e
JT
594\f
595
41d041d6 596/* Fill register REGNUM in REGCACHE with the appropriate
ed504bdf
MK
597 floating-point or SSE register value from *FXSAVE. This function
598 masks off any of the reserved bits in *FXSAVE. */
e750d25e
JT
599
600void
41d041d6 601i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
e750d25e 602{
41d041d6 603 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
b4ad899f 604 const gdb_byte *regs = fxsave;
5716833c
MK
605 int i;
606
607 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
608 gdb_assert (tdep->num_xmm_regs > 0);
dff95cc7 609
20a6ec49 610 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
ed504bdf
MK
611 if (regnum == -1 || regnum == i)
612 {
5716833c 613 if (regs == NULL)
ed504bdf 614 {
5716833c 615 regcache_raw_supply (regcache, i, NULL);
ed504bdf
MK
616 continue;
617 }
932bb524 618
ed504bdf
MK
619 /* Most of the FPU control registers occupy only 16 bits in
620 the fxsave area. Give those a special treatment. */
20a6ec49
MD
621 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
622 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
ed504bdf 623 {
b4ad899f 624 gdb_byte val[4];
ed504bdf 625
20a6ec49 626 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
ed504bdf 627 val[2] = val[3] = 0;
20a6ec49 628 if (i == I387_FOP_REGNUM (tdep))
ed504bdf 629 val[1] &= ((1 << 3) - 1);
20a6ec49 630 else if (i== I387_FTAG_REGNUM (tdep))
ed504bdf
MK
631 {
632 /* The fxsave area contains a simplified version of
633 the tag word. We have to look at the actual 80-bit
634 FP data to recreate the traditional i387 tag word. */
635
636 unsigned long ftag = 0;
637 int fpreg;
638 int top;
639
20a6ec49
MD
640 top = ((FXSAVE_ADDR (tdep, regs,
641 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
5716833c 642 top &= 0x7;
ed504bdf
MK
643
644 for (fpreg = 7; fpreg >= 0; fpreg--)
645 {
646 int tag;
647
648 if (val[0] & (1 << fpreg))
649 {
6d5e094a
MS
650 int thisreg = (fpreg + 8 - top) % 8
651 + I387_ST0_REGNUM (tdep);
652 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
ed504bdf
MK
653 }
654 else
655 tag = 3; /* Empty */
656
657 ftag |= tag << (2 * fpreg);
658 }
659 val[0] = ftag & 0xff;
660 val[1] = (ftag >> 8) & 0xff;
661 }
5716833c 662 regcache_raw_supply (regcache, i, val);
ed504bdf
MK
663 }
664 else
20a6ec49 665 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
ed504bdf 666 }
5716833c 667
20a6ec49 668 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
5716833c
MK
669 {
670 if (regs == NULL)
20a6ec49 671 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
5716833c 672 else
20a6ec49 673 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
5716833c
MK
674 FXSAVE_MXCSR_ADDR (regs));
675 }
e750d25e
JT
676}
677
678/* Fill register REGNUM (if it is a floating-point or SSE register) in
80571bff
MK
679 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
680 all registers. This function doesn't touch any of the reserved
681 bits in *FXSAVE. */
e750d25e
JT
682
683void
80571bff 684i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
e750d25e 685{
e071d1f6 686 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
b4ad899f 687 gdb_byte *regs = fxsave;
5716833c
MK
688 int i;
689
690 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
691 gdb_assert (tdep->num_xmm_regs > 0);
dff95cc7 692
20a6ec49 693 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
e750d25e
JT
694 if (regnum == -1 || regnum == i)
695 {
696 /* Most of the FPU control registers occupy only 16 bits in
697 the fxsave area. Give those a special treatment. */
20a6ec49
MD
698 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
699 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
e750d25e 700 {
b4ad899f 701 gdb_byte buf[4];
e750d25e 702
5716833c 703 regcache_raw_collect (regcache, i, buf);
e750d25e 704
31aeac78
L
705 if (i == I387_FOP_REGNUM (tdep))
706 {
707 /* The opcode occupies only 11 bits. Make sure we
708 don't touch the other bits. */
709 buf[1] &= ((1 << 3) - 1);
710 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
711 }
712 else if (i == I387_FTAG_REGNUM (tdep))
713 {
714 /* Converting back is much easier. */
715
716 unsigned short ftag;
717 int fpreg;
718
719 ftag = (buf[1] << 8) | buf[0];
720 buf[0] = 0;
721 buf[1] = 0;
722
723 for (fpreg = 7; fpreg >= 0; fpreg--)
724 {
725 int tag = (ftag >> (fpreg * 2)) & 3;
726
727 if (tag != 3)
728 buf[0] |= (1 << fpreg);
729 }
730 }
731 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
732 }
733 else
734 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
735 }
736
737 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
738 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
739 FXSAVE_MXCSR_ADDR (regs));
740}
741
742/* `xstate_bv' is at byte offset 512. */
743#define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
744
745/* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
746 the upper 128bit of AVX register data structure used by the "xsave"
747 instruction where GDB register REGNUM is stored. */
748
749static int xsave_avxh_offset[] =
750{
751 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
752 576 + 1 * 16,
753 576 + 2 * 16,
754 576 + 3 * 16,
755 576 + 4 * 16,
756 576 + 5 * 16,
757 576 + 6 * 16,
758 576 + 7 * 16,
759 576 + 8 * 16,
760 576 + 9 * 16,
761 576 + 10 * 16,
762 576 + 11 * 16,
763 576 + 12 * 16,
764 576 + 13 * 16,
765 576 + 14 * 16,
766 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
767};
768
769#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
770 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
771
772/* Similar to i387_supply_fxsave, but use XSAVE extended state. */
773
774void
775i387_supply_xsave (struct regcache *regcache, int regnum,
776 const void *xsave)
777{
778 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
779 const gdb_byte *regs = xsave;
780 int i;
781 unsigned int clear_bv;
782 const gdb_byte *p;
783 enum
784 {
785 none = 0x0,
786 x87 = 0x1,
787 sse = 0x2,
788 avxh = 0x4,
789 all = x87 | sse | avxh
790 } regclass;
791
792 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
793 gdb_assert (tdep->num_xmm_regs > 0);
794
795 if (regnum == -1)
796 regclass = all;
797 else if (regnum >= I387_YMM0H_REGNUM (tdep)
798 && regnum < I387_YMMENDH_REGNUM (tdep))
799 regclass = avxh;
800 else if (regnum >= I387_XMM0_REGNUM(tdep)
801 && regnum < I387_MXCSR_REGNUM (tdep))
802 regclass = sse;
803 else if (regnum >= I387_ST0_REGNUM (tdep)
804 && regnum < I387_FCTRL_REGNUM (tdep))
805 regclass = x87;
806 else
807 regclass = none;
808
809 if (regs != NULL && regclass != none)
810 {
811 /* Get `xstat_bv'. */
812 const gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
813
814 /* The supported bits in `xstat_bv' are 1 byte. Clear part in
815 vector registers if its bit in xstat_bv is zero. */
816 clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
817 }
818 else
819 clear_bv = I386_XSTATE_AVX_MASK;
820
821 switch (regclass)
822 {
823 case none:
824 break;
825
826 case avxh:
827 if ((clear_bv & I386_XSTATE_AVX))
828 p = NULL;
829 else
830 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
831 regcache_raw_supply (regcache, regnum, p);
832 return;
833
834 case sse:
835 if ((clear_bv & I386_XSTATE_SSE))
836 p = NULL;
837 else
838 p = FXSAVE_ADDR (tdep, regs, regnum);
839 regcache_raw_supply (regcache, regnum, p);
840 return;
841
842 case x87:
843 if ((clear_bv & I386_XSTATE_X87))
844 p = NULL;
845 else
846 p = FXSAVE_ADDR (tdep, regs, regnum);
847 regcache_raw_supply (regcache, regnum, p);
848 return;
849
850 case all:
86d31898 851 /* Handle the upper YMM registers. */
31aeac78
L
852 if ((tdep->xcr0 & I386_XSTATE_AVX))
853 {
854 if ((clear_bv & I386_XSTATE_AVX))
855 p = NULL;
856 else
857 p = regs;
858
859 for (i = I387_YMM0H_REGNUM (tdep);
860 i < I387_YMMENDH_REGNUM (tdep); i++)
861 {
862 if (p != NULL)
863 p = XSAVE_AVXH_ADDR (tdep, regs, i);
864 regcache_raw_supply (regcache, i, p);
865 }
866 }
867
868 /* Handle the XMM registers. */
869 if ((tdep->xcr0 & I386_XSTATE_SSE))
870 {
871 if ((clear_bv & I386_XSTATE_SSE))
872 p = NULL;
873 else
874 p = regs;
875
876 for (i = I387_XMM0_REGNUM (tdep);
877 i < I387_MXCSR_REGNUM (tdep); i++)
878 {
879 if (p != NULL)
880 p = FXSAVE_ADDR (tdep, regs, i);
881 regcache_raw_supply (regcache, i, p);
882 }
883 }
884
885 /* Handle the x87 registers. */
886 if ((tdep->xcr0 & I386_XSTATE_X87))
887 {
888 if ((clear_bv & I386_XSTATE_X87))
889 p = NULL;
890 else
891 p = regs;
892
893 for (i = I387_ST0_REGNUM (tdep);
894 i < I387_FCTRL_REGNUM (tdep); i++)
895 {
896 if (p != NULL)
897 p = FXSAVE_ADDR (tdep, regs, i);
898 regcache_raw_supply (regcache, i, p);
899 }
900 }
901 break;
902 }
903
904 /* Only handle x87 control registers. */
905 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
906 if (regnum == -1 || regnum == i)
907 {
908 if (regs == NULL)
909 {
910 regcache_raw_supply (regcache, i, NULL);
911 continue;
912 }
913
914 /* Most of the FPU control registers occupy only 16 bits in
915 the xsave extended state. Give those a special treatment. */
916 if (i != I387_FIOFF_REGNUM (tdep)
917 && i != I387_FOOFF_REGNUM (tdep))
918 {
919 gdb_byte val[4];
920
921 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
922 val[2] = val[3] = 0;
923 if (i == I387_FOP_REGNUM (tdep))
924 val[1] &= ((1 << 3) - 1);
925 else if (i== I387_FTAG_REGNUM (tdep))
926 {
927 /* The fxsave area contains a simplified version of
928 the tag word. We have to look at the actual 80-bit
929 FP data to recreate the traditional i387 tag word. */
930
931 unsigned long ftag = 0;
932 int fpreg;
933 int top;
934
935 top = ((FXSAVE_ADDR (tdep, regs,
936 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
937 top &= 0x7;
938
939 for (fpreg = 7; fpreg >= 0; fpreg--)
940 {
941 int tag;
942
943 if (val[0] & (1 << fpreg))
944 {
e5b3d7d6 945 int thisreg = (fpreg + 8 - top) % 8
31aeac78 946 + I387_ST0_REGNUM (tdep);
e5b3d7d6 947 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
31aeac78
L
948 }
949 else
950 tag = 3; /* Empty */
951
952 ftag |= tag << (2 * fpreg);
953 }
954 val[0] = ftag & 0xff;
955 val[1] = (ftag >> 8) & 0xff;
956 }
957 regcache_raw_supply (regcache, i, val);
958 }
959 else
960 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
961 }
962
963 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
964 {
965 p = regs == NULL ? NULL : FXSAVE_MXCSR_ADDR (regs);
966 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), p);
967 }
968}
969
970/* Similar to i387_collect_fxsave, but use XSAVE extended state. */
971
972void
973i387_collect_xsave (const struct regcache *regcache, int regnum,
974 void *xsave, int gcore)
975{
976 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
977 gdb_byte *regs = xsave;
978 int i;
979 enum
980 {
981 none = 0x0,
982 check = 0x1,
983 x87 = 0x2 | check,
984 sse = 0x4 | check,
985 avxh = 0x8 | check,
986 all = x87 | sse | avxh
987 } regclass;
988
989 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
990 gdb_assert (tdep->num_xmm_regs > 0);
991
992 if (regnum == -1)
993 regclass = all;
994 else if (regnum >= I387_YMM0H_REGNUM (tdep)
995 && regnum < I387_YMMENDH_REGNUM (tdep))
996 regclass = avxh;
997 else if (regnum >= I387_XMM0_REGNUM(tdep)
998 && regnum < I387_MXCSR_REGNUM (tdep))
999 regclass = sse;
1000 else if (regnum >= I387_ST0_REGNUM (tdep)
1001 && regnum < I387_FCTRL_REGNUM (tdep))
1002 regclass = x87;
1003 else
1004 regclass = none;
1005
1006 if (gcore)
1007 {
1008 /* Clear XSAVE extended state. */
1009 memset (regs, 0, I386_XSTATE_SIZE (tdep->xcr0));
1010
1011 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1012 if (tdep->xsave_xcr0_offset != -1)
1013 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1014 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1015 }
1016
1017 if ((regclass & check))
1018 {
1019 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1020 gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
1021 unsigned int xstate_bv = 0;
1777feb0 1022 /* The supported bits in `xstat_bv' are 1 byte. */
31aeac78
L
1023 unsigned int clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
1024 gdb_byte *p;
1025
1026 /* Clear register set if its bit in xstat_bv is zero. */
1027 if (clear_bv)
1028 {
1029 if ((clear_bv & I386_XSTATE_AVX))
1030 for (i = I387_YMM0H_REGNUM (tdep);
1031 i < I387_YMMENDH_REGNUM (tdep); i++)
1032 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1033
1034 if ((clear_bv & I386_XSTATE_SSE))
1035 for (i = I387_XMM0_REGNUM (tdep);
1036 i < I387_MXCSR_REGNUM (tdep); i++)
1037 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1038
1039 if ((clear_bv & I386_XSTATE_X87))
1040 for (i = I387_ST0_REGNUM (tdep);
1041 i < I387_FCTRL_REGNUM (tdep); i++)
1042 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1043 }
1044
1045 if (regclass == all)
1046 {
1047 /* Check if any upper YMM registers are changed. */
1048 if ((tdep->xcr0 & I386_XSTATE_AVX))
1049 for (i = I387_YMM0H_REGNUM (tdep);
1050 i < I387_YMMENDH_REGNUM (tdep); i++)
1051 {
1052 regcache_raw_collect (regcache, i, raw);
1053 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1054 if (memcmp (raw, p, 16))
1055 {
1056 xstate_bv |= I386_XSTATE_AVX;
1057 memcpy (p, raw, 16);
1058 }
1059 }
1060
1061 /* Check if any SSE registers are changed. */
1062 if ((tdep->xcr0 & I386_XSTATE_SSE))
1063 for (i = I387_XMM0_REGNUM (tdep);
1064 i < I387_MXCSR_REGNUM (tdep); i++)
1065 {
1066 regcache_raw_collect (regcache, i, raw);
1067 p = FXSAVE_ADDR (tdep, regs, i);
1068 if (memcmp (raw, p, 16))
1069 {
1070 xstate_bv |= I386_XSTATE_SSE;
1071 memcpy (p, raw, 16);
1072 }
1073 }
1074
1075 /* Check if any X87 registers are changed. */
1076 if ((tdep->xcr0 & I386_XSTATE_X87))
1077 for (i = I387_ST0_REGNUM (tdep);
1078 i < I387_FCTRL_REGNUM (tdep); i++)
1079 {
1080 regcache_raw_collect (regcache, i, raw);
1081 p = FXSAVE_ADDR (tdep, regs, i);
1082 if (memcmp (raw, p, 10))
1083 {
1084 xstate_bv |= I386_XSTATE_X87;
1085 memcpy (p, raw, 10);
1086 }
1087 }
1088 }
1089 else
1090 {
1091 /* Check if REGNUM is changed. */
1092 regcache_raw_collect (regcache, regnum, raw);
1093
1094 switch (regclass)
1095 {
1096 default:
4e4d8374
L
1097 internal_error (__FILE__, __LINE__,
1098 _("invalid i387 regclass"));
31aeac78 1099
40936b0d
L
1100 case avxh:
1101 /* This is an upper YMM register. */
1102 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1103 if (memcmp (raw, p, 16))
31aeac78 1104 {
40936b0d
L
1105 xstate_bv |= I386_XSTATE_AVX;
1106 memcpy (p, raw, 16);
1107 }
1108 break;
31aeac78 1109
40936b0d
L
1110 case sse:
1111 /* This is an SSE register. */
1112 p = FXSAVE_ADDR (tdep, regs, regnum);
1113 if (memcmp (raw, p, 16))
1114 {
1115 xstate_bv |= I386_XSTATE_SSE;
1116 memcpy (p, raw, 16);
1117 }
1118 break;
31aeac78 1119
40936b0d
L
1120 case x87:
1121 /* This is an x87 register. */
1122 p = FXSAVE_ADDR (tdep, regs, regnum);
1123 if (memcmp (raw, p, 10))
1124 {
1125 xstate_bv |= I386_XSTATE_X87;
1126 memcpy (p, raw, 10);
31aeac78 1127 }
40936b0d 1128 break;
31aeac78 1129 }
40936b0d
L
1130 }
1131
1132 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1133 registers are changed. */
1134 if (xstate_bv)
1135 {
1136 /* The supported bits in `xstat_bv' are 1 byte. */
1137 *xstate_bv_p |= (gdb_byte) xstate_bv;
1138
1139 switch (regclass)
31aeac78 1140 {
40936b0d 1141 default:
4e4d8374
L
1142 internal_error (__FILE__, __LINE__,
1143 _("invalid i387 regclass"));
40936b0d
L
1144
1145 case all:
1146 break;
1147
1148 case x87:
1149 case sse:
1150 case avxh:
1151 /* Register REGNUM has been updated. Return. */
1152 return;
31aeac78 1153 }
40936b0d
L
1154 }
1155 else
1156 {
1157 /* Return if REGNUM isn't changed. */
1158 if (regclass != all)
1159 return;
1160 }
31aeac78
L
1161 }
1162
1163 /* Only handle x87 control registers. */
1164 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1165 if (regnum == -1 || regnum == i)
1166 {
1167 /* Most of the FPU control registers occupy only 16 bits in
1168 the xsave extended state. Give those a special treatment. */
1169 if (i != I387_FIOFF_REGNUM (tdep)
1170 && i != I387_FOOFF_REGNUM (tdep))
1171 {
1172 gdb_byte buf[4];
1173
1174 regcache_raw_collect (regcache, i, buf);
1175
20a6ec49 1176 if (i == I387_FOP_REGNUM (tdep))
e750d25e
JT
1177 {
1178 /* The opcode occupies only 11 bits. Make sure we
40936b0d 1179 don't touch the other bits. */
e750d25e 1180 buf[1] &= ((1 << 3) - 1);
20a6ec49 1181 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
e750d25e 1182 }
20a6ec49 1183 else if (i == I387_FTAG_REGNUM (tdep))
e750d25e
JT
1184 {
1185 /* Converting back is much easier. */
1186
1187 unsigned short ftag;
1188 int fpreg;
1189
1190 ftag = (buf[1] << 8) | buf[0];
1191 buf[0] = 0;
1192 buf[1] = 0;
1193
1194 for (fpreg = 7; fpreg >= 0; fpreg--)
1195 {
1196 int tag = (ftag >> (fpreg * 2)) & 3;
1197
1198 if (tag != 3)
1199 buf[0] |= (1 << fpreg);
1200 }
1201 }
20a6ec49 1202 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
e750d25e
JT
1203 }
1204 else
20a6ec49 1205 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
e750d25e 1206 }
5716833c 1207
20a6ec49
MD
1208 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1209 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
5716833c 1210 FXSAVE_MXCSR_ADDR (regs));
e750d25e
JT
1211}
1212
1213/* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1214 *RAW. */
1215
1216static int
b4ad899f 1217i387_tag (const gdb_byte *raw)
e750d25e
JT
1218{
1219 int integer;
1220 unsigned int exponent;
1221 unsigned long fraction[2];
1222
1223 integer = raw[7] & 0x80;
1224 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1225 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1226 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1227 | (raw[5] << 8) | raw[4]);
1228
1229 if (exponent == 0x7fff)
1230 {
1231 /* Special. */
1232 return (2);
1233 }
1234 else if (exponent == 0x0000)
1235 {
1236 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1237 {
1238 /* Zero. */
1239 return (1);
1240 }
1241 else
1242 {
1243 /* Special. */
1244 return (2);
1245 }
1246 }
1247 else
1248 {
1249 if (integer)
1250 {
1251 /* Valid. */
1252 return (0);
1253 }
1254 else
1255 {
1256 /* Special. */
1257 return (2);
1258 }
1259 }
1260}
efb1c01c
MK
1261
1262/* Prepare the FPU stack in REGCACHE for a function return. */
1263
1264void
1265i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1266{
1267 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1268 ULONGEST fstat;
1269
efb1c01c
MK
1270 /* Set the top of the floating-point register stack to 7. The
1271 actual value doesn't really matter, but 7 is what a normal
1272 function return would end up with if the program started out with
1273 a freshly initialized FPU. */
20a6ec49 1274 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
efb1c01c 1275 fstat |= (7 << 11);
20a6ec49 1276 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
efb1c01c
MK
1277
1278 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1279 floating-point register stack to 7, the appropriate value for the
1280 tag word is 0x3fff. */
20a6ec49 1281 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
efb1c01c 1282
efb1c01c 1283}
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