[deliverable/binutils-gdb.git] / gdb / ia64-linux-nat.c

/* Functions specific to running gdb native on IA-64 running Linux.
   Copyright 1999, 2000 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#include "defs.h"
#include "inferior.h"
#include "target.h"
#include "gdbcore.h"

#include <signal.h>
#include <sys/ptrace.h>
#include <sys/wait.h>
#ifdef HAVE_SYS_REG_H
#include <sys/reg.h>
#endif
#include <sys/user.h>

#include <asm/ptrace_offsets.h>
#include <sys/procfs.h>

/* These must match the order of the register names.

   Some sort of lookup table is needed because the offsets associated
   with the registers are all over the board.  */

static int u_offsets[] =
  {
    /* general registers */
    -1,		/* gr0 not available; i.e, it's always zero */
    PT_R1,
    PT_R2,
    PT_R3,
    PT_R4,
    PT_R5,
    PT_R6,
    PT_R7,
    PT_R8,
    PT_R9,
    PT_R10,
    PT_R11,
    PT_R12,
    PT_R13,
    PT_R14,
    PT_R15,
    PT_R16,
    PT_R17,
    PT_R18,
    PT_R19,
    PT_R20,
    PT_R21,
    PT_R22,
    PT_R23,
    PT_R24,
    PT_R25,
    PT_R26,
    PT_R27,
    PT_R28,
    PT_R29,
    PT_R30,
    PT_R31,
    /* gr32 through gr127 not directly available via the ptrace interface */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    /* Floating point registers */
    -1, -1,	/* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
    PT_F2,
    PT_F3,
    PT_F4,
    PT_F5,
    PT_F6,
    PT_F7,
    PT_F8,
    PT_F9,
    PT_F10,
    PT_F11,
    PT_F12,
    PT_F13,
    PT_F14,
    PT_F15,
    PT_F16,
    PT_F17,
    PT_F18,
    PT_F19,
    PT_F20,
    PT_F21,
    PT_F22,
    PT_F23,
    PT_F24,
    PT_F25,
    PT_F26,
    PT_F27,
    PT_F28,
    PT_F29,
    PT_F30,
    PT_F31,
    PT_F32,
    PT_F33,
    PT_F34,
    PT_F35,
    PT_F36,
    PT_F37,
    PT_F38,
    PT_F39,
    PT_F40,
    PT_F41,
    PT_F42,
    PT_F43,
    PT_F44,
    PT_F45,
    PT_F46,
    PT_F47,
    PT_F48,
    PT_F49,
    PT_F50,
    PT_F51,
    PT_F52,
    PT_F53,
    PT_F54,
    PT_F55,
    PT_F56,
    PT_F57,
    PT_F58,
    PT_F59,
    PT_F60,
    PT_F61,
    PT_F62,
    PT_F63,
    PT_F64,
    PT_F65,
    PT_F66,
    PT_F67,
    PT_F68,
    PT_F69,
    PT_F70,
    PT_F71,
    PT_F72,
    PT_F73,
    PT_F74,
    PT_F75,
    PT_F76,
    PT_F77,
    PT_F78,
    PT_F79,
    PT_F80,
    PT_F81,
    PT_F82,
    PT_F83,
    PT_F84,
    PT_F85,
    PT_F86,
    PT_F87,
    PT_F88,
    PT_F89,
    PT_F90,
    PT_F91,
    PT_F92,
    PT_F93,
    PT_F94,
    PT_F95,
    PT_F96,
    PT_F97,
    PT_F98,
    PT_F99,
    PT_F100,
    PT_F101,
    PT_F102,
    PT_F103,
    PT_F104,
    PT_F105,
    PT_F106,
    PT_F107,
    PT_F108,
    PT_F109,
    PT_F110,
    PT_F111,
    PT_F112,
    PT_F113,
    PT_F114,
    PT_F115,
    PT_F116,
    PT_F117,
    PT_F118,
    PT_F119,
    PT_F120,
    PT_F121,
    PT_F122,
    PT_F123,
    PT_F124,
    PT_F125,
    PT_F126,
    PT_F127,
    /* predicate registers - we don't fetch these individually */
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    /* branch registers */
    PT_B0,
    PT_B1,
    PT_B2,
    PT_B3,
    PT_B4,
    PT_B5,
    PT_B6,
    PT_B7,
    /* virtual frame pointer and virtual return address pointer */
    -1, -1,
    /* other registers */
    PT_PR,
    PT_CR_IIP,	/* ip */
    PT_CR_IPSR, /* psr */
    PT_CR_IFS,	/* cfm */
    /* kernel registers not visible via ptrace interface (?) */
    -1, -1, -1, -1, -1, -1, -1, -1,
    /* hole */
    -1, -1, -1, -1, -1, -1, -1, -1,
    PT_AR_RSC,
    PT_AR_BSP,
    PT_AR_BSPSTORE,
    PT_AR_RNAT,
    -1,
    -1,		/* Not available: FCR, IA32 floating control register */
    -1, -1,
    -1,		/* Not available: EFLAG */
    -1,		/* Not available: CSD */
    -1,		/* Not available: SSD */
    -1,		/* Not available: CFLG */
    -1,		/* Not available: FSR */
    -1,		/* Not available: FIR */
    -1,		/* Not available: FDR */
    -1,
    PT_AR_CCV,
    -1, -1, -1,
    PT_AR_UNAT,
    -1, -1, -1,
    PT_AR_FPSR,
    -1, -1, -1,
    -1,		/* Not available: ITC */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1,
    PT_AR_PFS,
    PT_AR_LC,
    -1,		/* Not available: EC, the Epilog Count register */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1,
    /* nat bits - not fetched directly; instead we obtain these bits from
       either rnat or unat or from memory. */
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
  };

CORE_ADDR
register_addr (regno, blockend)
     int regno;
     CORE_ADDR blockend;
{
  CORE_ADDR addr;

  if (regno < 0 || regno >= NUM_REGS)
    error ("Invalid register number %d.", regno);

  if (u_offsets[regno] == -1)
    addr = 0;
  else
    addr = (CORE_ADDR) u_offsets[regno];

  return addr;
}

int ia64_cannot_fetch_register (regno)
     int regno;
{
  return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
}

int ia64_cannot_store_register (regno)
     int regno;
{
  /* Rationale behind not permitting stores to bspstore...
  
     The IA-64 architecture provides bspstore and bsp which refer
     memory locations in the RSE's backing store.  bspstore is the
     next location which will be written when the RSE needs to write
     to memory.  bsp is the address at which r32 in the current frame
     would be found if it were written to the backing store.

     The IA-64 architecture provides read-only access to bsp and
     read/write access to bspstore (but only when the RSE is in
     the enforced lazy mode).  It should be noted that stores
     to bspstore also affect the value of bsp.  Changing bspstore
     does not affect the number of dirty entries between bspstore
     and bsp, so changing bspstore by N words will also cause bsp
     to be changed by (roughly) N as well.  (It could be N-1 or N+1
     depending upon where the NaT collection bits fall.)

     OTOH, the linux kernel provides read/write access to bsp (and
     currently read/write access to bspstore as well).  But it
     is definitely the case that if you change one, the other
     will change at the same time.  It is more useful to gdb to
     be able to change bsp.  So in order to prevent strange and
     undesirable things from happening when a dummy stack frame
     is popped (after calling an inferior function), we allow
     bspstore to be read, but not written.  (Note that popping
     a (generic) dummy stack frame causes all registers that
     were previously read from the inferior process to be written
     back.)  */

  return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
         || regno == IA64_BSPSTORE_REGNUM;
}

void
supply_gregset (gregsetp)
     gregset_t *gregsetp;
{
  int regi;
  greg_t *regp = (greg_t *) gregsetp;

  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
    {
      supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));
    }

  /* FIXME: NAT collection bits are at index 32; gotta deal with these
     somehow... */

  supply_register (IA64_PR_REGNUM, (char *) (regp + 33));

  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
    {
      supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
    }

  supply_register (IA64_IP_REGNUM, (char *) (regp + 42));
  supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));
  supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));
  supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));
  supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));
  supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));
  supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));
  supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));
  supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));
  supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));
  supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));
  supply_register (IA64_LC_REGNUM, (char *) (regp + 53));
  supply_register (IA64_EC_REGNUM, (char *) (regp + 54));
}

void
fill_gregset (gregsetp, regno)
     gregset_t *gregsetp;
     int regno;
{
  fprintf (stderr, "Warning: fill_gregset not implemented!\n");
  /* FIXME: Implement later */
}
Commit	Line	Data
64a5b29c KB	1	/* Functions specific to running gdb native on IA-64 running Linux.
64a5b29c KB	2	Copyright 1999, 2000 Free Software Foundation, Inc.
16461d7d KB	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330,
	19	Boston, MA 02111-1307, USA. */
	20
	21	#include "defs.h"
	22	#include "inferior.h"
	23	#include "target.h"
	24	#include "gdbcore.h"
	25
	26	#include <signal.h>
	27	#include <sys/ptrace.h>
	28	#include <sys/wait.h>
	29	#ifdef HAVE_SYS_REG_H
	30	#include <sys/reg.h>
	31	#endif
	32	#include <sys/user.h>
	33
	34	#include <asm/ptrace_offsets.h>
	35	#include <sys/procfs.h>
	36
	37	/* These must match the order of the register names.
	38
	39	Some sort of lookup table is needed because the offsets associated
	40	with the registers are all over the board. */
	41
	42	static int u_offsets[] =
	43	{
	44	/* general registers */
	45	-1, /* gr0 not available; i.e, it's always zero */
	46	PT_R1,
	47	PT_R2,
	48	PT_R3,
	49	PT_R4,
	50	PT_R5,
	51	PT_R6,
	52	PT_R7,
	53	PT_R8,
	54	PT_R9,
	55	PT_R10,
	56	PT_R11,
	57	PT_R12,
	58	PT_R13,
	59	PT_R14,
	60	PT_R15,
	61	PT_R16,
	62	PT_R17,
	63	PT_R18,
	64	PT_R19,
	65	PT_R20,
	66	PT_R21,
67	PT_R22,
68	PT_R23,
69	PT_R24,
70	PT_R25,
71	PT_R26,
72	PT_R27,
73	PT_R28,
74	PT_R29,
75	PT_R30,
76	PT_R31,
77	/* gr32 through gr127 not directly available via the ptrace interface */
78	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
79	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
80	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
81	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
82	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
83	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
84	/* Floating point registers */
85	-1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
86	PT_F2,
87	PT_F3,
88	PT_F4,
89	PT_F5,
90	PT_F6,
91	PT_F7,
92	PT_F8,
93	PT_F9,
94	PT_F10,
95	PT_F11,
96	PT_F12,
97	PT_F13,
98	PT_F14,
99	PT_F15,
100	PT_F16,
101	PT_F17,
102	PT_F18,
103	PT_F19,
104	PT_F20,
105	PT_F21,
106	PT_F22,
107	PT_F23,
108	PT_F24,
109	PT_F25,
110	PT_F26,
111	PT_F27,
112	PT_F28,
113	PT_F29,
114	PT_F30,
115	PT_F31,
116	PT_F32,
117	PT_F33,
118	PT_F34,
119	PT_F35,
120	PT_F36,
121	PT_F37,
122	PT_F38,
123	PT_F39,
124	PT_F40,
125	PT_F41,
126	PT_F42,
127	PT_F43,
128	PT_F44,
129	PT_F45,
130	PT_F46,
131	PT_F47,
132	PT_F48,
133	PT_F49,
134	PT_F50,
135	PT_F51,
136	PT_F52,
137	PT_F53,
138	PT_F54,
139	PT_F55,
140	PT_F56,
141	PT_F57,
142	PT_F58,
143	PT_F59,
144	PT_F60,
145	PT_F61,
146	PT_F62,
147	PT_F63,
148	PT_F64,
149	PT_F65,
150	PT_F66,
151	PT_F67,
152	PT_F68,
153	PT_F69,
154	PT_F70,
155	PT_F71,
156	PT_F72,
157	PT_F73,
158	PT_F74,
159	PT_F75,
160	PT_F76,
161	PT_F77,
162	PT_F78,
163	PT_F79,
164	PT_F80,
165	PT_F81,
166	PT_F82,
167	PT_F83,
168	PT_F84,
169	PT_F85,
170	PT_F86,
171	PT_F87,
172	PT_F88,
173	PT_F89,
174	PT_F90,
175	PT_F91,
176	PT_F92,
177	PT_F93,
178	PT_F94,
179	PT_F95,
180	PT_F96,
181	PT_F97,
182	PT_F98,
183	PT_F99,
184	PT_F100,
185	PT_F101,
186	PT_F102,
187	PT_F103,
188	PT_F104,
189	PT_F105,
190	PT_F106,
191	PT_F107,
192	PT_F108,
193	PT_F109,
194	PT_F110,
195	PT_F111,
196	PT_F112,
197	PT_F113,
198	PT_F114,
199	PT_F115,
200	PT_F116,
201	PT_F117,
202	PT_F118,
203	PT_F119,
204	PT_F120,
205	PT_F121,
206	PT_F122,
207	PT_F123,
208	PT_F124,
209	PT_F125,
210	PT_F126,
211	PT_F127,
212	/* predicate registers - we don't fetch these individually */
213	-1, -1, -1, -1, -1, -1, -1, -1,
214	-1, -1, -1, -1, -1, -1, -1, -1,
215	-1, -1, -1, -1, -1, -1, -1, -1,
216	-1, -1, -1, -1, -1, -1, -1, -1,
217	-1, -1, -1, -1, -1, -1, -1, -1,
218	-1, -1, -1, -1, -1, -1, -1, -1,
219	-1, -1, -1, -1, -1, -1, -1, -1,
220	-1, -1, -1, -1, -1, -1, -1, -1,
221	/* branch registers */
222	PT_B0,
223	PT_B1,
224	PT_B2,
225	PT_B3,
226	PT_B4,
227	PT_B5,
228	PT_B6,
229	PT_B7,
230	/* virtual frame pointer and virtual return address pointer */
231	-1, -1,
232	/* other registers */
233	PT_PR,
234	PT_CR_IIP, /* ip */
235	PT_CR_IPSR, /* psr */
236	PT_CR_IFS, /* cfm */
237	/* kernel registers not visible via ptrace interface (?) */
238	-1, -1, -1, -1, -1, -1, -1, -1,
239	/* hole */
240	-1, -1, -1, -1, -1, -1, -1, -1,
241	PT_AR_RSC,
242	PT_AR_BSP,
243	PT_AR_BSPSTORE,
244	PT_AR_RNAT,
245	-1,
246	-1, /* Not available: FCR, IA32 floating control register */
247	-1, -1,
248	-1, /* Not available: EFLAG */
249	-1, /* Not available: CSD */
250	-1, /* Not available: SSD */
251	-1, /* Not available: CFLG */
252	-1, /* Not available: FSR */
253	-1, /* Not available: FIR */
254	-1, /* Not available: FDR */
255	-1,
256	PT_AR_CCV,
257	-1, -1, -1,
258	PT_AR_UNAT,
259	-1, -1, -1,
260	PT_AR_FPSR,
261	-1, -1, -1,
262	-1, /* Not available: ITC */
263	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
264	-1, -1, -1, -1, -1, -1, -1, -1, -1,
265	PT_AR_PFS,
266	PT_AR_LC,
267	-1, /* Not available: EC, the Epilog Count register */
268	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
269	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
270	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
271	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
272	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
274	-1,
275	/* nat bits - not fetched directly; instead we obtain these bits from
276	either rnat or unat or from memory. */
277	-1, -1, -1, -1, -1, -1, -1, -1,
278	-1, -1, -1, -1, -1, -1, -1, -1,
279	-1, -1, -1, -1, -1, -1, -1, -1,
280	-1, -1, -1, -1, -1, -1, -1, -1,
281	-1, -1, -1, -1, -1, -1, -1, -1,
282	-1, -1, -1, -1, -1, -1, -1, -1,
283	-1, -1, -1, -1, -1, -1, -1, -1,
284	-1, -1, -1, -1, -1, -1, -1, -1,
285	-1, -1, -1, -1, -1, -1, -1, -1,
286	-1, -1, -1, -1, -1, -1, -1, -1,
287	-1, -1, -1, -1, -1, -1, -1, -1,
288	-1, -1, -1, -1, -1, -1, -1, -1,
289	-1, -1, -1, -1, -1, -1, -1, -1,
290	-1, -1, -1, -1, -1, -1, -1, -1,
291	-1, -1, -1, -1, -1, -1, -1, -1,
292	-1, -1, -1, -1, -1, -1, -1, -1,
293	};
294
295	CORE_ADDR
296	register_addr (regno, blockend)
297	int regno;
298	CORE_ADDR blockend;
299	{
300	CORE_ADDR addr;
301
302	if (regno < 0 \|\| regno >= NUM_REGS)
303	error ("Invalid register number %d.", regno);
304
305	if (u_offsets[regno] == -1)
306	addr = 0;
307	else
308	addr = (CORE_ADDR) u_offsets[regno];
309
310	return addr;
311	}
312
313	int ia64_cannot_fetch_register (regno)
314	int regno;
315	{
316	return regno < 0 \|\| regno >= NUM_REGS \|\| u_offsets[regno] == -1;
317	}
318
319	int ia64_cannot_store_register (regno)
320	int regno;
321	{
322	/* Rationale behind not permitting stores to bspstore...
323
324	The IA-64 architecture provides bspstore and bsp which refer
325	memory locations in the RSE's backing store. bspstore is the
326	next location which will be written when the RSE needs to write
327	to memory. bsp is the address at which r32 in the current frame
328	would be found if it were written to the backing store.
329
330	The IA-64 architecture provides read-only access to bsp and
331	read/write access to bspstore (but only when the RSE is in
332	the enforced lazy mode). It should be noted that stores
333	to bspstore also affect the value of bsp. Changing bspstore
334	does not affect the number of dirty entries between bspstore
335	and bsp, so changing bspstore by N words will also cause bsp
336	to be changed by (roughly) N as well. (It could be N-1 or N+1
337	depending upon where the NaT collection bits fall.)
338
339	OTOH, the linux kernel provides read/write access to bsp (and
340	currently read/write access to bspstore as well). But it
341	is definitely the case that if you change one, the other
342	will change at the same time. It is more useful to gdb to
343	be able to change bsp. So in order to prevent strange and
344	undesirable things from happening when a dummy stack frame
345	is popped (after calling an inferior function), we allow
346	bspstore to be read, but not written. (Note that popping
347	a (generic) dummy stack frame causes all registers that
348	were previously read from the inferior process to be written
349	back.) */
350
351	return regno < 0 \|\| regno >= NUM_REGS \|\| u_offsets[regno] == -1
352	\|\| regno == IA64_BSPSTORE_REGNUM;
353	}
354
355	void
356	supply_gregset (gregsetp)
357	gregset_t *gregsetp;
358	{
359	int regi;
360	greg_t regp = (greg_t ) gregsetp;
361
362	for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
363	{
364	supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));
365	}
366
367	/* FIXME: NAT collection bits are at index 32; gotta deal with these
368	somehow... */
369
370	supply_register (IA64_PR_REGNUM, (char *) (regp + 33));
371
372	for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
373	{
374	supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
375	}
376
377	supply_register (IA64_IP_REGNUM, (char *) (regp + 42));
378	supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));
379	supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));
380	supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));
381	supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));
382	supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));
383	supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));
384	supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));
385	supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));
386	supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));
387	supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));
388	supply_register (IA64_LC_REGNUM, (char *) (regp + 53));
389	supply_register (IA64_EC_REGNUM, (char *) (regp + 54));
390	}
391
392	void
393	fill_gregset (gregsetp, regno)
394	gregset_t *gregsetp;
395	int regno;
396	{
64a5b29c	397	fprintf (stderr, "Warning: fill_gregset not implemented!\n");
16461d7d KB	398	/* FIXME: Implement later */
16461d7d KB	399	}