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[deliverable/binutils-gdb.git] / gdb / ia64-linux-nat.c
CommitLineData
ca557f44
AC		 1/* Functions specific to running gdb native on IA-64 running
2 GNU/Linux.
3
6aba47ca 4 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
c5fa4245 5 Free Software Foundation, Inc.
16461d7d
KB		 6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
197e01b6
EZ		 21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
16461d7d
KB		 23
24#include "defs.h"
e162d11b 25#include "gdb_string.h"
16461d7d
KB		 26#include "inferior.h"
27#include "target.h"
28#include "gdbcore.h"
4e052eda 29#include "regcache.h"
949df321 30#include "ia64-tdep.h"
10d6c8cd 31#include "linux-nat.h"
16461d7d
KB		 32
33#include <signal.h>
34#include <sys/ptrace.h>
2555fe1a 35#include "gdb_wait.h"
16461d7d
KB		 36#ifdef HAVE_SYS_REG_H
37#include <sys/reg.h>
38#endif
287a334e 39#include <sys/syscall.h>
16461d7d
KB		 40#include <sys/user.h>
41
42#include <asm/ptrace_offsets.h>
43#include <sys/procfs.h>
44
c60c0f5f
MS		 45/* Prototypes for supply_gregset etc. */
46#include "gregset.h"
47
16461d7d
KB		 48/* These must match the order of the register names.
49
50 Some sort of lookup table is needed because the offsets associated
51 with the registers are all over the board. */
52
53static int u_offsets[] =
54 {
55 /* general registers */
56 -1, /* gr0 not available; i.e, it's always zero */
57 PT_R1,
58 PT_R2,
59 PT_R3,
60 PT_R4,
61 PT_R5,
62 PT_R6,
63 PT_R7,
64 PT_R8,
65 PT_R9,
66 PT_R10,
67 PT_R11,
68 PT_R12,
69 PT_R13,
70 PT_R14,
71 PT_R15,
72 PT_R16,
73 PT_R17,
74 PT_R18,
75 PT_R19,
76 PT_R20,
77 PT_R21,
78 PT_R22,
79 PT_R23,
80 PT_R24,
81 PT_R25,
82 PT_R26,
83 PT_R27,
84 PT_R28,
85 PT_R29,
86 PT_R30,
87 PT_R31,
88 /* gr32 through gr127 not directly available via the ptrace interface */
89 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
90 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
92 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
93 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
94 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
95 /* Floating point registers */
96 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
97 PT_F2,
98 PT_F3,
99 PT_F4,
100 PT_F5,
101 PT_F6,
102 PT_F7,
103 PT_F8,
104 PT_F9,
105 PT_F10,
106 PT_F11,
107 PT_F12,
108 PT_F13,
109 PT_F14,
110 PT_F15,
111 PT_F16,
112 PT_F17,
113 PT_F18,
114 PT_F19,
115 PT_F20,
116 PT_F21,
117 PT_F22,
118 PT_F23,
119 PT_F24,
120 PT_F25,
121 PT_F26,
122 PT_F27,
123 PT_F28,
124 PT_F29,
125 PT_F30,
126 PT_F31,
127 PT_F32,
128 PT_F33,
129 PT_F34,
130 PT_F35,
131 PT_F36,
132 PT_F37,
133 PT_F38,
134 PT_F39,
135 PT_F40,
136 PT_F41,
137 PT_F42,
138 PT_F43,
139 PT_F44,
140 PT_F45,
141 PT_F46,
142 PT_F47,
143 PT_F48,
144 PT_F49,
145 PT_F50,
146 PT_F51,
147 PT_F52,
148 PT_F53,
149 PT_F54,
150 PT_F55,
151 PT_F56,
152 PT_F57,
153 PT_F58,
154 PT_F59,
155 PT_F60,
156 PT_F61,
157 PT_F62,
158 PT_F63,
159 PT_F64,
160 PT_F65,
161 PT_F66,
162 PT_F67,
163 PT_F68,
164 PT_F69,
165 PT_F70,
166 PT_F71,
167 PT_F72,
168 PT_F73,
169 PT_F74,
170 PT_F75,
171 PT_F76,
172 PT_F77,
173 PT_F78,
174 PT_F79,
175 PT_F80,
176 PT_F81,
177 PT_F82,
178 PT_F83,
179 PT_F84,
180 PT_F85,
181 PT_F86,
182 PT_F87,
183 PT_F88,
184 PT_F89,
185 PT_F90,
186 PT_F91,
187 PT_F92,
188 PT_F93,
189 PT_F94,
190 PT_F95,
191 PT_F96,
192 PT_F97,
193 PT_F98,
194 PT_F99,
195 PT_F100,
196 PT_F101,
197 PT_F102,
198 PT_F103,
199 PT_F104,
200 PT_F105,
201 PT_F106,
202 PT_F107,
203 PT_F108,
204 PT_F109,
205 PT_F110,
206 PT_F111,
207 PT_F112,
208 PT_F113,
209 PT_F114,
210 PT_F115,
211 PT_F116,
212 PT_F117,
213 PT_F118,
214 PT_F119,
215 PT_F120,
216 PT_F121,
217 PT_F122,
218 PT_F123,
219 PT_F124,
220 PT_F125,
221 PT_F126,
222 PT_F127,
223 /* predicate registers - we don't fetch these individually */
224 -1, -1, -1, -1, -1, -1, -1, -1,
225 -1, -1, -1, -1, -1, -1, -1, -1,
226 -1, -1, -1, -1, -1, -1, -1, -1,
227 -1, -1, -1, -1, -1, -1, -1, -1,
228 -1, -1, -1, -1, -1, -1, -1, -1,
229 -1, -1, -1, -1, -1, -1, -1, -1,
230 -1, -1, -1, -1, -1, -1, -1, -1,
231 -1, -1, -1, -1, -1, -1, -1, -1,
232 /* branch registers */
233 PT_B0,
234 PT_B1,
235 PT_B2,
236 PT_B3,
237 PT_B4,
238 PT_B5,
239 PT_B6,
240 PT_B7,
241 /* virtual frame pointer and virtual return address pointer */
242 -1, -1,
243 /* other registers */
244 PT_PR,
245 PT_CR_IIP, /* ip */
246 PT_CR_IPSR, /* psr */
9ac12c35 247 PT_CFM, /* cfm */
16461d7d
KB		 248 /* kernel registers not visible via ptrace interface (?) */
249 -1, -1, -1, -1, -1, -1, -1, -1,
250 /* hole */
251 -1, -1, -1, -1, -1, -1, -1, -1,
252 PT_AR_RSC,
253 PT_AR_BSP,
254 PT_AR_BSPSTORE,
255 PT_AR_RNAT,
256 -1,
257 -1, /* Not available: FCR, IA32 floating control register */
258 -1, -1,
259 -1, /* Not available: EFLAG */
260 -1, /* Not available: CSD */
261 -1, /* Not available: SSD */
262 -1, /* Not available: CFLG */
263 -1, /* Not available: FSR */
264 -1, /* Not available: FIR */
265 -1, /* Not available: FDR */
266 -1,
267 PT_AR_CCV,
268 -1, -1, -1,
269 PT_AR_UNAT,
270 -1, -1, -1,
271 PT_AR_FPSR,
272 -1, -1, -1,
273 -1, /* Not available: ITC */
274 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
275 -1, -1, -1, -1, -1, -1, -1, -1, -1,
276 PT_AR_PFS,
277 PT_AR_LC,
278 -1, /* Not available: EC, the Epilog Count register */
279 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
283 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
284 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
285 -1,
286 /* nat bits - not fetched directly; instead we obtain these bits from
287 either rnat or unat or from memory. */
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
293 -1, -1, -1, -1, -1, -1, -1, -1,
294 -1, -1, -1, -1, -1, -1, -1, -1,
295 -1, -1, -1, -1, -1, -1, -1, -1,
296 -1, -1, -1, -1, -1, -1, -1, -1,
297 -1, -1, -1, -1, -1, -1, -1, -1,
298 -1, -1, -1, -1, -1, -1, -1, -1,
299 -1, -1, -1, -1, -1, -1, -1, -1,
300 -1, -1, -1, -1, -1, -1, -1, -1,
301 -1, -1, -1, -1, -1, -1, -1, -1,
302 -1, -1, -1, -1, -1, -1, -1, -1,
303 -1, -1, -1, -1, -1, -1, -1, -1,
304 };
305
74174d2e
UW		 306static CORE_ADDR
307ia64_register_addr (int regno)
16461d7d
KB		 308{
309 CORE_ADDR addr;
310
f57d151a 311 if (regno < 0 || regno >= gdbarch_num_regs (current_gdbarch))
8a3fe4f8 312 error (_("Invalid register number %d."), regno);
16461d7d
KB		 313
314 if (u_offsets[regno] == -1)
315 addr = 0;
316 else
317 addr = (CORE_ADDR) u_offsets[regno];
318
319 return addr;
320}
321
74174d2e
UW		 322static int
323ia64_cannot_fetch_register (int regno)
16461d7d 324{
f57d151a
UW		 325 return regno < 0
326 || regno >= gdbarch_num_regs (current_gdbarch)
327 || u_offsets[regno] == -1;
16461d7d
KB		 328}
329
74174d2e
UW		 330static int
331ia64_cannot_store_register (int regno)
16461d7d
KB		 332{
333 /* Rationale behind not permitting stores to bspstore...
334
335 The IA-64 architecture provides bspstore and bsp which refer
336 memory locations in the RSE's backing store. bspstore is the
337 next location which will be written when the RSE needs to write
338 to memory. bsp is the address at which r32 in the current frame
339 would be found if it were written to the backing store.
340
341 The IA-64 architecture provides read-only access to bsp and
342 read/write access to bspstore (but only when the RSE is in
343 the enforced lazy mode). It should be noted that stores
344 to bspstore also affect the value of bsp. Changing bspstore
345 does not affect the number of dirty entries between bspstore
346 and bsp, so changing bspstore by N words will also cause bsp
347 to be changed by (roughly) N as well. (It could be N-1 or N+1
348 depending upon where the NaT collection bits fall.)
349
92362027 350 OTOH, the Linux kernel provides read/write access to bsp (and
16461d7d
KB		 351 currently read/write access to bspstore as well). But it
352 is definitely the case that if you change one, the other
353 will change at the same time. It is more useful to gdb to
354 be able to change bsp. So in order to prevent strange and
355 undesirable things from happening when a dummy stack frame
356 is popped (after calling an inferior function), we allow
357 bspstore to be read, but not written. (Note that popping
358 a (generic) dummy stack frame causes all registers that
359 were previously read from the inferior process to be written
360 back.) */
361
f57d151a
UW		 362 return regno < 0
363 || regno >= gdbarch_num_regs (current_gdbarch)
364 || u_offsets[regno] == -1
16461d7d
KB		 365 || regno == IA64_BSPSTORE_REGNUM;
366}
367
368void
7f7fe91e 369supply_gregset (struct regcache *regcache, const gregset_t *gregsetp)
16461d7d
KB		 370{
371 int regi;
7f7fe91e 372 const greg_t *regp = (const greg_t *) gregsetp;
16461d7d
KB		 373
374 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
375 {
7f7fe91e 376 regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
16461d7d
KB		 377 }
378
379 /* FIXME: NAT collection bits are at index 32; gotta deal with these
380 somehow... */
381
7f7fe91e 382 regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
16461d7d
KB		 383
384 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
385 {
7f7fe91e
UW		 386 regcache_raw_supply (regcache, regi,
387 regp + 34 + (regi - IA64_BR0_REGNUM));
16461d7d
KB		 388 }
389
7f7fe91e
UW		 390 regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
391 regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
392 regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
393 regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
394 regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
395 regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
396 regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
397 regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
398 regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
399 regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
400 regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
401 regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
402 regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
16461d7d
KB		 403}
404
405void
7f7fe91e 406fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno)
16461d7d 407{
76d689a6
KB		 408 int regi;
409 greg_t *regp = (greg_t *) gregsetp;
410
411#define COPY_REG(_idx_,_regi_) \
412 if ((regno == -1) || regno == _regi_) \
7f7fe91e 413 regcache_raw_collect (regcache, _regi_, regp + _idx_)
76d689a6
KB		 414
415 for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
416 {
417 COPY_REG (regi - IA64_GR0_REGNUM, regi);
418 }
419
420 /* FIXME: NAT collection bits at index 32? */
421
422 COPY_REG (33, IA64_PR_REGNUM);
423
424 for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
425 {
426 COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
427 }
428
429 COPY_REG (42, IA64_IP_REGNUM);
430 COPY_REG (43, IA64_CFM_REGNUM);
431 COPY_REG (44, IA64_PSR_REGNUM);
432 COPY_REG (45, IA64_RSC_REGNUM);
433 COPY_REG (46, IA64_BSP_REGNUM);
434 COPY_REG (47, IA64_BSPSTORE_REGNUM);
435 COPY_REG (48, IA64_RNAT_REGNUM);
436 COPY_REG (49, IA64_CCV_REGNUM);
437 COPY_REG (50, IA64_UNAT_REGNUM);
438 COPY_REG (51, IA64_FPSR_REGNUM);
439 COPY_REG (52, IA64_PFS_REGNUM);
440 COPY_REG (53, IA64_LC_REGNUM);
441 COPY_REG (54, IA64_EC_REGNUM);
442}
443
444/* Given a pointer to a floating point register set in /proc format
445 (fpregset_t *), unpack the register contents and supply them as gdb's
446 idea of the current floating point register values. */
447
448void
7f7fe91e 449supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
76d689a6 450{
52f0bd74 451 int regi;
7f7fe91e 452 const char *from;
76d689a6
KB		 453
454 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
455 {
7f7fe91e
UW		 456 from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
457 regcache_raw_supply (regcache, regi, from);
76d689a6
KB		 458 }
459}
460
461/* Given a pointer to a floating point register set in /proc format
462 (fpregset_t *), update the register specified by REGNO from gdb's idea
463 of the current floating point register set. If REGNO is -1, update
464 them all. */
465
466void
7f7fe91e
UW		 467fill_fpregset (const struct regcache *regcache,
468 fpregset_t *fpregsetp, int regno)
76d689a6
KB		 469{
470 int regi;
76d689a6
KB		 471
472 for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
473 {
474 if ((regno == -1) || (regno == regi))
7f7fe91e 475 regcache_raw_collect (regcache, regi,
e0e25c6c 476 &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
76d689a6 477 }
16461d7d 478}
acf7b9e1
KB		 479
480#define IA64_PSR_DB (1UL << 24)
481#define IA64_PSR_DD (1UL << 39)
482
483static void
7b86a1b8 484enable_watchpoints_in_psr (struct regcache *regcache)
acf7b9e1 485{
7b86a1b8 486 ULONGEST psr;
acf7b9e1 487
7b86a1b8 488 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
acf7b9e1
KB		 489 if (!(psr & IA64_PSR_DB))
490 {
491 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
492 watchpoints and breakpoints. */
7b86a1b8 493 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
acf7b9e1
KB		 494 }
495}
496
497static long
39f77062 498fetch_debug_register (ptid_t ptid, int idx)
acf7b9e1
KB		 499{
500 long val;
501 int tid;
502
39f77062 503 tid = TIDGET (ptid);
acf7b9e1 504 if (tid == 0)
39f77062 505 tid = PIDGET (ptid);
acf7b9e1 506
c5fa4245 507 val = ptrace (PT_READ_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), 0);
acf7b9e1
KB		 508
509 return val;
510}
511
512static void
39f77062 513store_debug_register (ptid_t ptid, int idx, long val)
acf7b9e1
KB		 514{
515 int tid;
516
39f77062 517 tid = TIDGET (ptid);
acf7b9e1 518 if (tid == 0)
39f77062 519 tid = PIDGET (ptid);
acf7b9e1 520
c5fa4245 521 (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
acf7b9e1
KB		 522}
523
524static void
39f77062 525fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
acf7b9e1
KB		 526{
527 if (dbr_addr)
39f77062 528 *dbr_addr = fetch_debug_register (ptid, 2 * idx);
acf7b9e1 529 if (dbr_mask)
39f77062 530 *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
acf7b9e1
KB		 531}
532
533static void
39f77062 534store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
acf7b9e1
KB		 535{
536 if (dbr_addr)
39f77062 537 store_debug_register (ptid, 2 * idx, *dbr_addr);
acf7b9e1 538 if (dbr_mask)
39f77062 539 store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
acf7b9e1
KB		 540}
541
542static int
543is_power_of_2 (int val)
544{
545 int i, onecount;
546
547 onecount = 0;
548 for (i = 0; i < 8 * sizeof (val); i++)
549 if (val & (1 << i))
550 onecount++;
551
552 return onecount <= 1;
553}
554
74174d2e
UW		 555static int
556ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw)
acf7b9e1 557{
74174d2e 558 ptid_t ptid = inferior_ptid;
acf7b9e1
KB		 559 int idx;
560 long dbr_addr, dbr_mask;
561 int max_watchpoints = 4;
562
563 if (len <= 0 || !is_power_of_2 (len))
564 return -1;
565
566 for (idx = 0; idx < max_watchpoints; idx++)
567 {
39f77062 568 fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
acf7b9e1
KB		 569 if ((dbr_mask & (0x3UL << 62)) == 0)
570 {
571 /* Exit loop if both r and w bits clear */
572 break;
573 }
574 }
575
576 if (idx == max_watchpoints)
577 return -1;
578
579 dbr_addr = (long) addr;
580 dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
581 dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
582 switch (rw)
583 {
584 case hw_write:
585 dbr_mask |= (1L << 62); /* Set w bit */
586 break;
587 case hw_read:
588 dbr_mask |= (1L << 63); /* Set r bit */
589 break;
590 case hw_access:
591 dbr_mask |= (3L << 62); /* Set both r and w bits */
592 break;
593 default:
594 return -1;
595 }
596
39f77062 597 store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
7b86a1b8 598 enable_watchpoints_in_psr (current_regcache);
acf7b9e1
KB		 599
600 return 0;
601}
602
74174d2e
UW		 603static int
604ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type)
acf7b9e1 605{
74174d2e 606 ptid_t ptid = inferior_ptid;
acf7b9e1
KB		 607 int idx;
608 long dbr_addr, dbr_mask;
609 int max_watchpoints = 4;
610
611 if (len <= 0 || !is_power_of_2 (len))
612 return -1;
613
614 for (idx = 0; idx < max_watchpoints; idx++)
615 {
39f77062 616 fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
acf7b9e1
KB		 617 if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
618 {
619 dbr_addr = 0;
620 dbr_mask = 0;
39f77062 621 store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
acf7b9e1
KB		 622 return 0;
623 }
624 }
625 return -1;
626}
627
74174d2e
UW		 628static int
629ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
acf7b9e1
KB		 630{
631 CORE_ADDR psr;
632 int tid;
633 struct siginfo siginfo;
4aa7a7f5 634 ptid_t ptid = inferior_ptid;
7b86a1b8 635 struct regcache *regcache = current_regcache;
acf7b9e1 636
39f77062 637 tid = TIDGET(ptid);
acf7b9e1 638 if (tid == 0)
39f77062 639 tid = PIDGET (ptid);
acf7b9e1
KB		 640
641 errno = 0;
c5fa4245 642 ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo);
acf7b9e1 643
705b278b
JJ		 644 if (errno != 0 || siginfo.si_signo != SIGTRAP ||
645 (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
acf7b9e1
KB		 646 return 0;
647
7b86a1b8 648 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
acf7b9e1
KB		 649 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
650 for the next instruction */
7b86a1b8 651 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
acf7b9e1 652
4aa7a7f5
JJ		 653 *addr_p = (CORE_ADDR)siginfo.si_addr;
654 return 1;
655}
656
74174d2e 657static int
4aa7a7f5
JJ		 658ia64_linux_stopped_by_watchpoint (void)
659{
660 CORE_ADDR addr;
74174d2e
UW		 661 return ia64_linux_stopped_data_address (&current_target, &addr);
662}
663
664static int
665ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
666{
667 return 1;
668}
669
670
671/* Fetch register REGNUM from the inferior. */
672
673static void
56be3814 674ia64_linux_fetch_register (struct regcache *regcache, int regnum)
74174d2e
UW		 675{
676 CORE_ADDR addr;
677 size_t size;
678 PTRACE_TYPE_RET *buf;
679 int pid, i;
680
681 if (ia64_cannot_fetch_register (regnum))
682 {
56be3814 683 regcache_raw_supply (regcache, regnum, NULL);
74174d2e
UW		 684 return;
685 }
686
687 /* Cater for systems like GNU/Linux, that implement threads as
688 separate processes. */
689 pid = ptid_get_lwp (inferior_ptid);
690 if (pid == 0)
691 pid = ptid_get_pid (inferior_ptid);
692
693 /* This isn't really an address, but ptrace thinks of it as one. */
694 addr = ia64_register_addr (regnum);
695 size = register_size (current_gdbarch, regnum);
696
697 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
698 buf = alloca (size);
699
700 /* Read the register contents from the inferior a chunk at a time. */
701 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
702 {
703 errno = 0;
704 buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0);
705 if (errno != 0)
706 error (_("Couldn't read register %s (#%d): %s."),
c9f4d572
UW		 707 gdbarch_register_name (current_gdbarch, regnum),
708 regnum, safe_strerror (errno));
74174d2e
UW		 709
710 addr += sizeof (PTRACE_TYPE_RET);
711 }
56be3814 712 regcache_raw_supply (regcache, regnum, buf);
74174d2e
UW		 713}
714
715/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
716 for all registers. */
717
718static void
56be3814 719ia64_linux_fetch_registers (struct regcache *regcache, int regnum)
74174d2e
UW		 720{
721 if (regnum == -1)
f57d151a 722 for (regnum = 0; regnum < gdbarch_num_regs (current_gdbarch); regnum++)
56be3814 723 ia64_linux_fetch_register (regcache, regnum);
74174d2e 724 else
56be3814 725 ia64_linux_fetch_register (regcache, regnum);
74174d2e
UW		 726}
727
728/* Store register REGNUM into the inferior. */
729
730static void
56be3814 731ia64_linux_store_register (const struct regcache *regcache, int regnum)
74174d2e
UW		 732{
733 CORE_ADDR addr;
734 size_t size;
735 PTRACE_TYPE_RET *buf;
736 int pid, i;
737
738 if (ia64_cannot_store_register (regnum))
739 return;
740
741 /* Cater for systems like GNU/Linux, that implement threads as
742 separate processes. */
743 pid = ptid_get_lwp (inferior_ptid);
744 if (pid == 0)
745 pid = ptid_get_pid (inferior_ptid);
746
747 /* This isn't really an address, but ptrace thinks of it as one. */
748 addr = ia64_register_addr (regnum);
749 size = register_size (current_gdbarch, regnum);
750
751 gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
752 buf = alloca (size);
753
754 /* Write the register contents into the inferior a chunk at a time. */
56be3814 755 regcache_raw_collect (regcache, regnum, buf);
74174d2e
UW		 756 for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
757 {
758 errno = 0;
759 ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]);
760 if (errno != 0)
761 error (_("Couldn't write register %s (#%d): %s."),
c9f4d572
UW		 762 gdbarch_register_name (current_gdbarch, regnum),
763 regnum, safe_strerror (errno));
74174d2e
UW		 764
765 addr += sizeof (PTRACE_TYPE_RET);
766 }
acf7b9e1 767}
287a334e 768
74174d2e
UW		 769/* Store register REGNUM back into the inferior. If REGNUM is -1, do
770 this for all registers. */
771
772static void
56be3814 773ia64_linux_store_registers (struct regcache *regcache, int regnum)
74174d2e
UW		 774{
775 if (regnum == -1)
f57d151a 776 for (regnum = 0; regnum < gdbarch_num_regs (current_gdbarch); regnum++)
56be3814 777 ia64_linux_store_register (regcache, regnum);
74174d2e 778 else
56be3814 779 ia64_linux_store_register (regcache, regnum);
74174d2e
UW		 780}
781
782
10d6c8cd
DJ		 783static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
784 const char *, gdb_byte *, const gdb_byte *,
785 ULONGEST, LONGEST);
786
787static LONGEST
788ia64_linux_xfer_partial (struct target_ops *ops,
789 enum target_object object,
790 const char *annex,
791 gdb_byte *readbuf, const gdb_byte *writebuf,
792 ULONGEST offset, LONGEST len)
793{
794 if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
795 return syscall (__NR_getunwind, readbuf, len);
796
797 return super_xfer_partial (ops, object, annex, readbuf, writebuf,
798 offset, len);
799}
800
801void _initialize_ia64_linux_nat (void);
802
803void
804_initialize_ia64_linux_nat (void)
287a334e 805{
10d6c8cd
DJ		 806 struct target_ops *t = linux_target ();
807
808 /* Fill in the generic GNU/Linux methods. */
809 t = linux_target ();
810
74174d2e
UW		 811 /* Override the default fetch/store register routines. */
812 t->to_fetch_registers = ia64_linux_fetch_registers;
813 t->to_store_registers = ia64_linux_store_registers;
814
10d6c8cd
DJ		 815 /* Override the default to_xfer_partial. */
816 super_xfer_partial = t->to_xfer_partial;
817 t->to_xfer_partial = ia64_linux_xfer_partial;
818
74174d2e
UW		 819 /* Override watchpoint routines. */
820
821 /* The IA-64 architecture can step over a watch point (without triggering
822 it again) if the "dd" (data debug fault disable) bit in the processor
823 status word is set.
824
825 This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
826 code there has determined that a hardware watchpoint has indeed
827 been hit. The CPU will then be able to execute one instruction
828 without triggering a watchpoint. */
829
830 t->to_have_steppable_watchpoint = 1;
831 t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
832 t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
833 t->to_stopped_data_address = ia64_linux_stopped_data_address;
834 t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
835 t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
836
10d6c8cd 837 /* Register the target. */
f973ed9c 838 linux_nat_add_target (t);
287a334e 839}
GDB Binutils - Deliverables
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