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2005-02-10 Andrew Cagney <cagney@gnu.org>
[deliverable/binutils-gdb.git] / gdb / ia64-tdep.c
CommitLineData
16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
0fd88904 3 Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
9fc9f5e2 4 Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23#include "defs.h"
24#include "inferior.h"
16461d7d 25#include "gdbcore.h"
8064c6ae 26#include "arch-utils.h"
16461d7d 27#include "floatformat.h"
4e052eda 28#include "regcache.h"
004d836a
JJ		 29#include "reggroups.h"
30#include "frame.h"
31#include "frame-base.h"
32#include "frame-unwind.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
bd1ce8ba 35#include "gdb_assert.h"
16461d7d
KB		 36#include "objfiles.h"
37#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 38#include "elf-bfd.h"
a89aa300 39#include "dis-asm.h"
7d9b040b 40#include "infcall.h"
b33e8514 41#include "osabi.h"
9fc9f5e2 42#include "ia64-tdep.h"
16461d7d 43
968d1cb4 44#ifdef HAVE_LIBUNWIND_IA64_H
8973ff21 45#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
968d1cb4
JJ		 46#include "libunwind-frame.h"
47#include "libunwind-ia64.h"
48#endif
49
698cb3f0
KB		 50/* An enumeration of the different IA-64 instruction types. */
51
16461d7d
KB		 52typedef enum instruction_type
53{
54 A, /* Integer ALU ; I-unit or M-unit */
55 I, /* Non-ALU integer; I-unit */
56 M, /* Memory ; M-unit */
57 F, /* Floating-point ; F-unit */
58 B, /* Branch ; B-unit */
59 L, /* Extended (L+X) ; I-unit */
60 X, /* Extended (L+X) ; I-unit */
61 undefined /* undefined or reserved */
62} instruction_type;
63
64/* We represent IA-64 PC addresses as the value of the instruction
65 pointer or'd with some bit combination in the low nibble which
66 represents the slot number in the bundle addressed by the
67 instruction pointer. The problem is that the Linux kernel
68 multiplies its slot numbers (for exceptions) by one while the
69 disassembler multiplies its slot numbers by 6. In addition, I've
70 heard it said that the simulator uses 1 as the multiplier.
71
72 I've fixed the disassembler so that the bytes_per_line field will
73 be the slot multiplier. If bytes_per_line comes in as zero, it
74 is set to six (which is how it was set up initially). -- objdump
75 displays pretty disassembly dumps with this value. For our purposes,
76 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
77 never want to also display the raw bytes the way objdump does. */
78
79#define SLOT_MULTIPLIER 1
80
81/* Length in bytes of an instruction bundle */
82
83#define BUNDLE_LEN 16
84
16461d7d
KB		 85static gdbarch_init_ftype ia64_gdbarch_init;
86
87static gdbarch_register_name_ftype ia64_register_name;
004d836a 88static gdbarch_register_type_ftype ia64_register_type;
16461d7d 89static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 90static gdbarch_skip_prologue_ftype ia64_skip_prologue;
004d836a 91static gdbarch_extract_return_value_ftype ia64_extract_return_value;
64a5b29c 92static struct type *is_float_or_hfa_type (struct type *t);
b33e8514 93static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
16461d7d 94
004d836a
JJ		 95static struct type *builtin_type_ia64_ext;
96
97#define NUM_IA64_RAW_REGS 462
16461d7d 98
16461d7d
KB		 99static int sp_regnum = IA64_GR12_REGNUM;
100static int fp_regnum = IA64_VFP_REGNUM;
101static int lr_regnum = IA64_VRAP_REGNUM;
102
004d836a 103/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 104 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 105enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
106 V127_REGNUM = V32_REGNUM + 95,
107 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 108
109/* Array of register names; There should be ia64_num_regs strings in
110 the initializer. */
111
112static char *ia64_register_names[] =
113{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
114 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
115 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
116 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 117 "", "", "", "", "", "", "", "",
118 "", "", "", "", "", "", "", "",
119 "", "", "", "", "", "", "", "",
120 "", "", "", "", "", "", "", "",
121 "", "", "", "", "", "", "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
16461d7d
KB		 129
130 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
131 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
132 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
133 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
134 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
135 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
136 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
137 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
138 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
139 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
140 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
141 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
142 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
143 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
144 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
145 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
146
004d836a
JJ		 147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
16461d7d
KB		 155
156 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
157
158 "vfp", "vrap",
159
160 "pr", "ip", "psr", "cfm",
161
162 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
163 "", "", "", "", "", "", "", "",
164 "rsc", "bsp", "bspstore", "rnat",
165 "", "fcr", "", "",
166 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
167 "ccv", "", "", "", "unat", "", "", "",
168 "fpsr", "", "", "", "itc",
169 "", "", "", "", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "", "",
171 "pfs", "lc", "ec",
172 "", "", "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "", "", "",
174 "", "", "", "", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "", "", "",
178 "",
179 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
180 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
181 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
182 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
183 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
184 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
185 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
186 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
187 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
188 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
189 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
190 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
191 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
192 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
193 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
194 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 195
196 "bof",
197
198 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
199 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
200 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
201 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
202 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
203 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
204 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
205 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
206 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
207 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
208 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
209 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
210
211 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
212 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
213 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
214 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
215 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
216 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
217 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
218 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 219};
220
004d836a
JJ		 221struct ia64_frame_cache
222{
223 CORE_ADDR base; /* frame pointer base for frame */
224 CORE_ADDR pc; /* function start pc for frame */
225 CORE_ADDR saved_sp; /* stack pointer for frame */
226 CORE_ADDR bsp; /* points at r32 for the current frame */
227 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 228 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 229 int frameless;
230 int sof; /* Size of frame (decoded from cfm value) */
231 int sol; /* Size of locals (decoded from cfm value) */
232 int sor; /* Number of rotating registers. (decoded from cfm value) */
233 CORE_ADDR after_prologue;
234 /* Address of first instruction after the last
235 prologue instruction; Note that there may
236 be instructions from the function's body
237 intermingled with the prologue. */
238 int mem_stack_frame_size;
239 /* Size of the memory stack frame (may be zero),
240 or -1 if it has not been determined yet. */
241 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 242 for this frame. 0 if no register is being used
16461d7d 243 as the frame pointer. */
004d836a
JJ		 244
245 /* Saved registers. */
246 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
247
248};
244bc108 249
698cb3f0
KB		 250#define SIGCONTEXT_REGISTER_ADDRESS \
251 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
16461d7d 252
004d836a
JJ		 253int
254ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
255 struct reggroup *group)
16461d7d 256{
004d836a
JJ		 257 int vector_p;
258 int float_p;
259 int raw_p;
260 if (group == all_reggroup)
261 return 1;
262 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
263 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
264 raw_p = regnum < NUM_IA64_RAW_REGS;
265 if (group == float_reggroup)
266 return float_p;
267 if (group == vector_reggroup)
268 return vector_p;
269 if (group == general_reggroup)
270 return (!vector_p && !float_p);
271 if (group == save_reggroup || group == restore_reggroup)
272 return raw_p;
273 return 0;
16461d7d
KB		 274}
275
004d836a
JJ		 276static const char *
277ia64_register_name (int reg)
16461d7d 278{
004d836a 279 return ia64_register_names[reg];
16461d7d
KB		 280}
281
004d836a
JJ		 282struct type *
283ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 284{
004d836a
JJ		 285 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
286 return builtin_type_ia64_ext;
287 else
288 return builtin_type_long;
16461d7d
KB		 289}
290
a78f21af 291static int
004d836a 292ia64_dwarf_reg_to_regnum (int reg)
16461d7d 293{
004d836a
JJ		 294 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
295 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
296 return reg;
16461d7d
KB		 297}
298
4afcc598 299static int
7be0c536 300floatformat_valid (const struct floatformat *fmt, const char *from)
4afcc598
JJ		 301{
302 return 1;
303}
304
16461d7d
KB		 305const struct floatformat floatformat_ia64_ext =
306{
307 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4afcc598 308 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
16461d7d
KB		 309};
310
16461d7d
KB		 311
312/* Extract ``len'' bits from an instruction bundle starting at
313 bit ``from''. */
314
244bc108 315static long long
16461d7d
KB		 316extract_bit_field (char *bundle, int from, int len)
317{
318 long long result = 0LL;
319 int to = from + len;
320 int from_byte = from / 8;
321 int to_byte = to / 8;
322 unsigned char *b = (unsigned char *) bundle;
323 unsigned char c;
324 int lshift;
325 int i;
326
327 c = b[from_byte];
328 if (from_byte == to_byte)
329 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
330 result = c >> (from % 8);
331 lshift = 8 - (from % 8);
332
333 for (i = from_byte+1; i < to_byte; i++)
334 {
335 result |= ((long long) b[i]) << lshift;
336 lshift += 8;
337 }
338
339 if (from_byte < to_byte && (to % 8 != 0))
340 {
341 c = b[to_byte];
342 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
343 result |= ((long long) c) << lshift;
344 }
345
346 return result;
347}
348
349/* Replace the specified bits in an instruction bundle */
350
244bc108 351static void
16461d7d
KB		 352replace_bit_field (char *bundle, long long val, int from, int len)
353{
354 int to = from + len;
355 int from_byte = from / 8;
356 int to_byte = to / 8;
357 unsigned char *b = (unsigned char *) bundle;
358 unsigned char c;
359
360 if (from_byte == to_byte)
361 {
362 unsigned char left, right;
363 c = b[from_byte];
364 left = (c >> (to % 8)) << (to % 8);
365 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
366 c = (unsigned char) (val & 0xff);
367 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
368 c |= right | left;
369 b[from_byte] = c;
370 }
371 else
372 {
373 int i;
374 c = b[from_byte];
375 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
376 c = c | (val << (from % 8));
377 b[from_byte] = c;
378 val >>= 8 - from % 8;
379
380 for (i = from_byte+1; i < to_byte; i++)
381 {
382 c = val & 0xff;
383 val >>= 8;
384 b[i] = c;
385 }
386
387 if (to % 8 != 0)
388 {
389 unsigned char cv = (unsigned char) val;
390 c = b[to_byte];
391 c = c >> (to % 8) << (to % 8);
392 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
393 b[to_byte] = c;
394 }
395 }
396}
397
398/* Return the contents of slot N (for N = 0, 1, or 2) in
399 and instruction bundle */
400
244bc108 401static long long
2fc3ac7e 402slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 403{
404 return extract_bit_field (bundle, 5+41*slotnum, 41);
405}
406
407/* Store an instruction in an instruction bundle */
408
244bc108 409static void
2fc3ac7e 410replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 411{
412 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
413}
414
64a5b29c 415static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 416{
417 { M, I, I }, /* 00 */
418 { M, I, I }, /* 01 */
419 { M, I, I }, /* 02 */
420 { M, I, I }, /* 03 */
421 { M, L, X }, /* 04 */
422 { M, L, X }, /* 05 */
423 { undefined, undefined, undefined }, /* 06 */
424 { undefined, undefined, undefined }, /* 07 */
425 { M, M, I }, /* 08 */
426 { M, M, I }, /* 09 */
427 { M, M, I }, /* 0A */
428 { M, M, I }, /* 0B */
429 { M, F, I }, /* 0C */
430 { M, F, I }, /* 0D */
431 { M, M, F }, /* 0E */
432 { M, M, F }, /* 0F */
433 { M, I, B }, /* 10 */
434 { M, I, B }, /* 11 */
435 { M, B, B }, /* 12 */
436 { M, B, B }, /* 13 */
437 { undefined, undefined, undefined }, /* 14 */
438 { undefined, undefined, undefined }, /* 15 */
439 { B, B, B }, /* 16 */
440 { B, B, B }, /* 17 */
441 { M, M, B }, /* 18 */
442 { M, M, B }, /* 19 */
443 { undefined, undefined, undefined }, /* 1A */
444 { undefined, undefined, undefined }, /* 1B */
445 { M, F, B }, /* 1C */
446 { M, F, B }, /* 1D */
447 { undefined, undefined, undefined }, /* 1E */
448 { undefined, undefined, undefined }, /* 1F */
449};
450
451/* Fetch and (partially) decode an instruction at ADDR and return the
452 address of the next instruction to fetch. */
453
454static CORE_ADDR
455fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
456{
457 char bundle[BUNDLE_LEN];
458 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
459 long long template;
460 int val;
461
c26e1c2b
KB		 462 /* Warn about slot numbers greater than 2. We used to generate
463 an error here on the assumption that the user entered an invalid
464 address. But, sometimes GDB itself requests an invalid address.
465 This can (easily) happen when execution stops in a function for
466 which there are no symbols. The prologue scanner will attempt to
467 find the beginning of the function - if the nearest symbol
468 happens to not be aligned on a bundle boundary (16 bytes), the
469 resulting starting address will cause GDB to think that the slot
470 number is too large.
471
472 So we warn about it and set the slot number to zero. It is
473 not necessarily a fatal condition, particularly if debugging
474 at the assembly language level. */
16461d7d 475 if (slotnum > 2)
c26e1c2b 476 {
8a3fe4f8
AC		 477 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
478 "Using slot 0 instead"));
c26e1c2b
KB		 479 slotnum = 0;
480 }
16461d7d
KB		 481
482 addr &= ~0x0f;
483
484 val = target_read_memory (addr, bundle, BUNDLE_LEN);
485
486 if (val != 0)
487 return 0;
488
489 *instr = slotN_contents (bundle, slotnum);
490 template = extract_bit_field (bundle, 0, 5);
491 *it = template_encoding_table[(int)template][slotnum];
492
64a5b29c 493 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 494 addr += 16;
495 else
496 addr += (slotnum + 1) * SLOT_MULTIPLIER;
497
498 return addr;
499}
500
501/* There are 5 different break instructions (break.i, break.b,
502 break.m, break.f, and break.x), but they all have the same
503 encoding. (The five bit template in the low five bits of the
504 instruction bundle distinguishes one from another.)
505
506 The runtime architecture manual specifies that break instructions
507 used for debugging purposes must have the upper two bits of the 21
508 bit immediate set to a 0 and a 1 respectively. A breakpoint
509 instruction encodes the most significant bit of its 21 bit
510 immediate at bit 36 of the 41 bit instruction. The penultimate msb
511 is at bit 25 which leads to the pattern below.
512
513 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
514 it turns out that 0x80000 was used as the syscall break in the early
515 simulators. So I changed the pattern slightly to do "break.i 0x080001"
516 instead. But that didn't work either (I later found out that this
517 pattern was used by the simulator that I was using.) So I ended up
518 using the pattern seen below. */
519
520#if 0
aaab4dba 521#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 522#endif
aaab4dba 523#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 524
525static int
526ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache)
527{
528 char bundle[BUNDLE_LEN];
529 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
530 long long instr;
531 int val;
126fa72d 532 int template;
16461d7d
KB		 533
534 if (slotnum > 2)
8a3fe4f8 535 error (_("Can't insert breakpoint for slot numbers greater than 2."));
16461d7d
KB		 536
537 addr &= ~0x0f;
538
539 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 540
541 /* Check for L type instruction in 2nd slot, if present then
542 bump up the slot number to the 3rd slot */
543 template = extract_bit_field (bundle, 0, 5);
544 if (slotnum == 1 && template_encoding_table[template][1] == L)
545 {
546 slotnum = 2;
547 }
548
16461d7d
KB		 549 instr = slotN_contents (bundle, slotnum);
550 memcpy(contents_cache, &instr, sizeof(instr));
aaab4dba 551 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 552 if (val == 0)
553 target_write_memory (addr, bundle, BUNDLE_LEN);
554
555 return val;
556}
557
558static int
559ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache)
560{
561 char bundle[BUNDLE_LEN];
562 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
563 long long instr;
564 int val;
126fa72d 565 int template;
16461d7d
KB		 566
567 addr &= ~0x0f;
568
569 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 570
571 /* Check for L type instruction in 2nd slot, if present then
572 bump up the slot number to the 3rd slot */
573 template = extract_bit_field (bundle, 0, 5);
574 if (slotnum == 1 && template_encoding_table[template][1] == L)
575 {
576 slotnum = 2;
577 }
578
16461d7d
KB		 579 memcpy (&instr, contents_cache, sizeof instr);
580 replace_slotN_contents (bundle, instr, slotnum);
581 if (val == 0)
582 target_write_memory (addr, bundle, BUNDLE_LEN);
583
584 return val;
585}
586
587/* We don't really want to use this, but remote.c needs to call it in order
588 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 589const unsigned char *
fba45db2 590ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 591{
592 static unsigned char breakpoint[] =
593 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
594 *lenptr = sizeof (breakpoint);
595#if 0
596 *pcptr &= ~0x0f;
597#endif
598 return breakpoint;
599}
600
a78f21af 601static CORE_ADDR
39f77062 602ia64_read_pc (ptid_t ptid)
16461d7d 603{
39f77062
KB		 604 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
605 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
16461d7d
KB		 606 int slot_num = (psr_value >> 41) & 3;
607
608 return pc_value | (slot_num * SLOT_MULTIPLIER);
609}
610
54a5c8d8 611void
39f77062 612ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
16461d7d
KB		 613{
614 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
39f77062 615 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
16461d7d
KB		 616 psr_value &= ~(3LL << 41);
617 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
618
619 new_pc &= ~0xfLL;
620
39f77062
KB		 621 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
622 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
16461d7d
KB		 623}
624
625#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
626
627/* Returns the address of the slot that's NSLOTS slots away from
628 the address ADDR. NSLOTS may be positive or negative. */
629static CORE_ADDR
630rse_address_add(CORE_ADDR addr, int nslots)
631{
632 CORE_ADDR new_addr;
633 int mandatory_nat_slots = nslots / 63;
634 int direction = nslots < 0 ? -1 : 1;
635
636 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
637
638 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
639 new_addr += 8 * direction;
640
641 if (IS_NaT_COLLECTION_ADDR(new_addr))
642 new_addr += 8 * direction;
643
644 return new_addr;
645}
646
004d836a
JJ		 647static void
648ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
649 int regnum, void *buf)
16461d7d 650{
004d836a 651 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 652 {
004d836a
JJ		 653 ULONGEST bsp;
654 ULONGEST cfm;
655 CORE_ADDR reg;
656 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
657 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
658
659 /* The bsp points at the end of the register frame so we
660 subtract the size of frame from it to get start of register frame. */
661 bsp = rse_address_add (bsp, -(cfm & 0x7f));
662
663 if ((cfm & 0x7f) > regnum - V32_REGNUM)
664 {
665 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
666 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
aa2a9a3c 667 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
004d836a 668 }
244bc108 669 else
aa2a9a3c 670 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
004d836a
JJ		 671 }
672 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
673 {
674 ULONGEST unatN_val;
675 ULONGEST unat;
676 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
677 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
aa2a9a3c 678 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
004d836a
JJ		 679 }
680 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
681 {
682 ULONGEST natN_val = 0;
683 ULONGEST bsp;
684 ULONGEST cfm;
685 CORE_ADDR gr_addr = 0;
686 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
687 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
688
689 /* The bsp points at the end of the register frame so we
690 subtract the size of frame from it to get start of register frame. */
691 bsp = rse_address_add (bsp, -(cfm & 0x7f));
692
693 if ((cfm & 0x7f) > regnum - V32_REGNUM)
694 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
695
696 if (gr_addr != 0)
697 {
698 /* Compute address of nat collection bits. */
699 CORE_ADDR nat_addr = gr_addr | 0x1f8;
700 CORE_ADDR nat_collection;
701 int nat_bit;
702 /* If our nat collection address is bigger than bsp, we have to get
703 the nat collection from rnat. Otherwise, we fetch the nat
704 collection from the computed address. */
705 if (nat_addr >= bsp)
706 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
707 else
708 nat_collection = read_memory_integer (nat_addr, 8);
709 nat_bit = (gr_addr >> 3) & 0x3f;
710 natN_val = (nat_collection >> nat_bit) & 1;
711 }
712
aa2a9a3c 713 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
244bc108 714 }
004d836a
JJ		 715 else if (regnum == VBOF_REGNUM)
716 {
717 /* A virtual register frame start is provided for user convenience.
718 It can be calculated as the bsp - sof (sizeof frame). */
719 ULONGEST bsp, vbsp;
720 ULONGEST cfm;
721 CORE_ADDR reg;
722 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
723 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
724
725 /* The bsp points at the end of the register frame so we
726 subtract the size of frame from it to get beginning of frame. */
727 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
aa2a9a3c 728 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
004d836a
JJ		 729 }
730 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
731 {
732 ULONGEST pr;
733 ULONGEST cfm;
734 ULONGEST prN_val;
735 CORE_ADDR reg;
736 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
737 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
738
739 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
740 {
741 /* Fetch predicate register rename base from current frame
742 marker for this frame. */
743 int rrb_pr = (cfm >> 32) & 0x3f;
744
745 /* Adjust the register number to account for register rotation. */
746 regnum = VP16_REGNUM
747 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
748 }
749 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
aa2a9a3c 750 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
004d836a
JJ		 751 }
752 else
aa2a9a3c 753 memset (buf, 0, register_size (current_gdbarch, regnum));
16461d7d
KB		 754}
755
004d836a
JJ		 756static void
757ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
758 int regnum, const void *buf)
16461d7d 759{
004d836a 760 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 761 {
004d836a
JJ		 762 ULONGEST bsp;
763 ULONGEST cfm;
764 CORE_ADDR reg;
765 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
766 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
767
768 bsp = rse_address_add (bsp, -(cfm & 0x7f));
769
770 if ((cfm & 0x7f) > regnum - V32_REGNUM)
771 {
772 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
773 write_memory (reg_addr, (void *)buf, 8);
774 }
775 }
776 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
777 {
778 ULONGEST unatN_val, unat, unatN_mask;
779 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
aa2a9a3c 780 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 781 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
782 if (unatN_val == 0)
783 unat &= ~unatN_mask;
784 else if (unatN_val == 1)
785 unat |= unatN_mask;
786 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
787 }
788 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
789 {
790 ULONGEST natN_val;
791 ULONGEST bsp;
792 ULONGEST cfm;
793 CORE_ADDR gr_addr = 0;
794 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
795 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
796
797 /* The bsp points at the end of the register frame so we
798 subtract the size of frame from it to get start of register frame. */
799 bsp = rse_address_add (bsp, -(cfm & 0x7f));
800
801 if ((cfm & 0x7f) > regnum - V32_REGNUM)
802 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
803
aa2a9a3c 804 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 805
806 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
807 {
808 /* Compute address of nat collection bits. */
809 CORE_ADDR nat_addr = gr_addr | 0x1f8;
810 CORE_ADDR nat_collection;
811 int natN_bit = (gr_addr >> 3) & 0x3f;
812 ULONGEST natN_mask = (1LL << natN_bit);
813 /* If our nat collection address is bigger than bsp, we have to get
814 the nat collection from rnat. Otherwise, we fetch the nat
815 collection from the computed address. */
816 if (nat_addr >= bsp)
817 {
818 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
819 if (natN_val)
820 nat_collection |= natN_mask;
821 else
822 nat_collection &= ~natN_mask;
823 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
824 }
825 else
826 {
827 char nat_buf[8];
828 nat_collection = read_memory_integer (nat_addr, 8);
829 if (natN_val)
830 nat_collection |= natN_mask;
831 else
832 nat_collection &= ~natN_mask;
aa2a9a3c 833 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
004d836a
JJ		 834 write_memory (nat_addr, nat_buf, 8);
835 }
836 }
837 }
838 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
839 {
840 ULONGEST pr;
841 ULONGEST cfm;
842 ULONGEST prN_val;
843 ULONGEST prN_mask;
844
845 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
846 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
847
848 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
849 {
850 /* Fetch predicate register rename base from current frame
851 marker for this frame. */
852 int rrb_pr = (cfm >> 32) & 0x3f;
853
854 /* Adjust the register number to account for register rotation. */
855 regnum = VP16_REGNUM
856 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
857 }
aa2a9a3c 858 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 859 prN_mask = (1LL << (regnum - VP0_REGNUM));
860 if (prN_val == 0)
861 pr &= ~prN_mask;
862 else if (prN_val == 1)
863 pr |= prN_mask;
864 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 865 }
16461d7d
KB		 866}
867
004d836a
JJ		 868/* The ia64 needs to convert between various ieee floating-point formats
869 and the special ia64 floating point register format. */
870
871static int
872ia64_convert_register_p (int regno, struct type *type)
873{
874 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
875}
876
877static void
878ia64_register_to_value (struct frame_info *frame, int regnum,
879 struct type *valtype, void *out)
880{
881 char in[MAX_REGISTER_SIZE];
882 frame_register_read (frame, regnum, in);
883 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
884}
885
886static void
887ia64_value_to_register (struct frame_info *frame, int regnum,
888 struct type *valtype, const void *in)
889{
890 char out[MAX_REGISTER_SIZE];
891 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
892 put_frame_register (frame, regnum, out);
893}
894
895
58ab00f9
KB		 896/* Limit the number of skipped non-prologue instructions since examining
897 of the prologue is expensive. */
5ea2bd7f 898static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 899
900/* Given PC representing the starting address of a function, and
901 LIM_PC which is the (sloppy) limit to which to scan when looking
902 for a prologue, attempt to further refine this limit by using
903 the line data in the symbol table. If successful, a better guess
904 on where the prologue ends is returned, otherwise the previous
905 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
906 which will be set to indicate whether the returned limit may be
907 used with no further scanning in the event that the function is
908 frameless. */
909
634aa483
AC		 910/* FIXME: cagney/2004-02-14: This function and logic have largely been
911 superseded by skip_prologue_using_sal. */
912
58ab00f9
KB		 913static CORE_ADDR
914refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
915{
916 struct symtab_and_line prologue_sal;
917 CORE_ADDR start_pc = pc;
918
919 /* Start off not trusting the limit. */
920 *trust_limit = 0;
921
922 prologue_sal = find_pc_line (pc, 0);
923 if (prologue_sal.line != 0)
924 {
925 int i;
926 CORE_ADDR addr = prologue_sal.end;
927
928 /* Handle the case in which compiler's optimizer/scheduler
929 has moved instructions into the prologue. We scan ahead
930 in the function looking for address ranges whose corresponding
931 line number is less than or equal to the first one that we
932 found for the function. (It can be less than when the
933 scheduler puts a body instruction before the first prologue
934 instruction.) */
935 for (i = 2 * max_skip_non_prologue_insns;
936 i > 0 && (lim_pc == 0 || addr < lim_pc);
937 i--)
938 {
939 struct symtab_and_line sal;
940
941 sal = find_pc_line (addr, 0);
942 if (sal.line == 0)
943 break;
944 if (sal.line <= prologue_sal.line
945 && sal.symtab == prologue_sal.symtab)
946 {
947 prologue_sal = sal;
948 }
949 addr = sal.end;
950 }
951
952 if (lim_pc == 0 || prologue_sal.end < lim_pc)
953 {
954 lim_pc = prologue_sal.end;
955 if (start_pc == get_pc_function_start (lim_pc))
956 *trust_limit = 1;
957 }
958 }
959 return lim_pc;
960}
961
16461d7d
KB		 962#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
963 || (8 <= (_regnum_) && (_regnum_) <= 11) \
964 || (14 <= (_regnum_) && (_regnum_) <= 31))
965#define imm9(_instr_) \
966 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
967 | (((_instr_) & 0x00008000000LL) >> 20) \
968 | (((_instr_) & 0x00000001fc0LL) >> 6))
969
004d836a
JJ		 970/* Allocate and initialize a frame cache. */
971
972static struct ia64_frame_cache *
973ia64_alloc_frame_cache (void)
974{
975 struct ia64_frame_cache *cache;
976 int i;
977
978 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
979
980 /* Base address. */
981 cache->base = 0;
982 cache->pc = 0;
983 cache->cfm = 0;
4afcc598 984 cache->prev_cfm = 0;
004d836a
JJ		 985 cache->sof = 0;
986 cache->sol = 0;
987 cache->sor = 0;
988 cache->bsp = 0;
989 cache->fp_reg = 0;
990 cache->frameless = 1;
991
992 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
993 cache->saved_regs[i] = 0;
994
995 return cache;
996}
997
16461d7d 998static CORE_ADDR
004d836a 999examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1000{
1001 CORE_ADDR next_pc;
1002 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1003 instruction_type it;
1004 long long instr;
16461d7d
KB		 1005 int cfm_reg = 0;
1006 int ret_reg = 0;
1007 int fp_reg = 0;
1008 int unat_save_reg = 0;
1009 int pr_save_reg = 0;
1010 int mem_stack_frame_size = 0;
1011 int spill_reg = 0;
1012 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1013 char instores[8];
1014 char infpstores[8];
5ea2bd7f 1015 char reg_contents[256];
58ab00f9 1016 int trust_limit;
004d836a
JJ		 1017 int frameless = 1;
1018 int i;
1019 CORE_ADDR addr;
1020 char buf[8];
1021 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1022
1023 memset (instores, 0, sizeof instores);
1024 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1025 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1026
004d836a
JJ		 1027 if (cache->after_prologue != 0
1028 && cache->after_prologue <= lim_pc)
1029 return cache->after_prologue;
16461d7d 1030
58ab00f9 1031 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1032 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1033
1034 /* We want to check if we have a recognizable function start before we
1035 look ahead for a prologue. */
16461d7d
KB		 1036 if (pc < lim_pc && next_pc
1037 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1038 {
5ea2bd7f 1039 /* alloc - start of a regular function. */
16461d7d
KB		 1040 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1041 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1042 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1043 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1044
1045 /* Verify that the current cfm matches what we think is the
1046 function start. If we have somehow jumped within a function,
1047 we do not want to interpret the prologue and calculate the
1048 addresses of various registers such as the return address.
1049 We will instead treat the frame as frameless. */
1050 if (!next_frame ||
1051 (sof == (cache->cfm & 0x7f) &&
1052 sol == ((cache->cfm >> 7) & 0x7f)))
1053 frameless = 0;
1054
16461d7d
KB		 1055 cfm_reg = rN;
1056 last_prologue_pc = next_pc;
1057 pc = next_pc;
1058 }
1059 else
58ab00f9 1060 {
5ea2bd7f
JJ		 1061 /* Look for a leaf routine. */
1062 if (pc < lim_pc && next_pc
1063 && (it == I || it == M)
1064 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1065 {
1066 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1067 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1068 | ((instr & 0x001f8000000LL) >> 20)
1069 | ((instr & 0x000000fe000LL) >> 13));
1070 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1071 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1072 int qp = (int) (instr & 0x0000000003fLL);
1073 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1074 {
1075 /* mov r2, r12 - beginning of leaf routine */
1076 fp_reg = rN;
5ea2bd7f
JJ		 1077 last_prologue_pc = next_pc;
1078 }
1079 }
1080
1081 /* If we don't recognize a regular function or leaf routine, we are
1082 done. */
1083 if (!fp_reg)
1084 {
1085 pc = lim_pc;
1086 if (trust_limit)
1087 last_prologue_pc = lim_pc;
1088 }
58ab00f9 1089 }
16461d7d
KB		 1090
1091 /* Loop, looking for prologue instructions, keeping track of
1092 where preserved registers were spilled. */
1093 while (pc < lim_pc)
1094 {
1095 next_pc = fetch_instruction (pc, &it, &instr);
1096 if (next_pc == 0)
1097 break;
1098
594706e6 1099 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
0927a22b 1100 {
102d615a
JJ		 1101 /* Exit loop upon hitting a non-nop branch instruction. */
1102 if (trust_limit)
1103 lim_pc = pc;
1104 break;
1105 }
1106 else if (((instr & 0x3fLL) != 0LL) &&
1107 (frameless || ret_reg != 0))
1108 {
1109 /* Exit loop upon hitting a predicated instruction if
1110 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1111 if (trust_limit)
1112 lim_pc = pc;
0927a22b
KB		 1113 break;
1114 }
1115 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1116 {
1117 /* Move from BR */
1118 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1119 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1120 int qp = (int) (instr & 0x0000000003f);
1121
1122 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1123 {
1124 ret_reg = rN;
1125 last_prologue_pc = next_pc;
1126 }
1127 }
1128 else if ((it == I || it == M)
1129 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1130 {
1131 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1132 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1133 | ((instr & 0x001f8000000LL) >> 20)
1134 | ((instr & 0x000000fe000LL) >> 13));
1135 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1136 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1137 int qp = (int) (instr & 0x0000000003fLL);
1138
1139 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1140 {
1141 /* mov rN, r12 */
1142 fp_reg = rN;
1143 last_prologue_pc = next_pc;
1144 }
1145 else if (qp == 0 && rN == 12 && rM == 12)
1146 {
1147 /* adds r12, -mem_stack_frame_size, r12 */
1148 mem_stack_frame_size -= imm;
1149 last_prologue_pc = next_pc;
1150 }
1151 else if (qp == 0 && rN == 2
1152 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1153 {
004d836a
JJ		 1154 char buf[MAX_REGISTER_SIZE];
1155 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1156 /* adds r2, spilloffset, rFramePointer
1157 or
1158 adds r2, spilloffset, r12
1159
1160 Get ready for stf.spill or st8.spill instructions.
1161 The address to start spilling at is loaded into r2.
1162 FIXME: Why r2? That's what gcc currently uses; it
1163 could well be different for other compilers. */
1164
1165 /* Hmm... whether or not this will work will depend on
1166 where the pc is. If it's still early in the prologue
1167 this'll be wrong. FIXME */
004d836a
JJ		 1168 if (next_frame)
1169 {
1170 frame_unwind_register (next_frame, sp_regnum, buf);
1171 saved_sp = extract_unsigned_integer (buf, 8);
1172 }
1173 spill_addr = saved_sp
16461d7d
KB		 1174 + (rM == 12 ? 0 : mem_stack_frame_size)
1175 + imm;
1176 spill_reg = rN;
1177 last_prologue_pc = next_pc;
1178 }
5ea2bd7f
JJ		 1179 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1180 rN < 256 && imm == 0)
1181 {
1182 /* mov rN, rM where rM is an input register */
1183 reg_contents[rN] = rM;
1184 last_prologue_pc = next_pc;
1185 }
1186 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1187 rM == 2)
1188 {
1189 /* mov r12, r2 */
1190 last_prologue_pc = next_pc;
1191 break;
1192 }
16461d7d
KB		 1193 }
1194 else if (it == M
1195 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1196 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1197 {
1198 /* stf.spill [rN] = fM, imm9
1199 or
1200 stf.spill [rN] = fM */
1201
1202 int imm = imm9(instr);
1203 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1204 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1205 int qp = (int) (instr & 0x0000000003fLL);
1206 if (qp == 0 && rN == spill_reg && spill_addr != 0
1207 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1208 {
004d836a 1209 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d 1210
594706e6 1211 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
16461d7d
KB		 1212 spill_addr += imm;
1213 else
1214 spill_addr = 0; /* last one; must be done */
1215 last_prologue_pc = next_pc;
1216 }
1217 }
1218 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1219 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1220 {
1221 /* mov.m rN = arM
1222 or
1223 mov.i rN = arM */
1224
1225 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1226 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1227 int qp = (int) (instr & 0x0000000003fLL);
1228 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1229 {
1230 /* We have something like "mov.m r3 = ar.unat". Remember the
1231 r3 (or whatever) and watch for a store of this register... */
1232 unat_save_reg = rN;
1233 last_prologue_pc = next_pc;
1234 }
1235 }
1236 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1237 {
1238 /* mov rN = pr */
1239 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1240 int qp = (int) (instr & 0x0000000003fLL);
1241 if (qp == 0 && isScratch (rN))
1242 {
1243 pr_save_reg = rN;
1244 last_prologue_pc = next_pc;
1245 }
1246 }
1247 else if (it == M
1248 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1249 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1250 {
1251 /* st8 [rN] = rM
1252 or
1253 st8 [rN] = rM, imm9 */
1254 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1255 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1256 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1257 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1258 if (qp == 0 && rN == spill_reg && spill_addr != 0
1259 && (rM == unat_save_reg || rM == pr_save_reg))
1260 {
1261 /* We've found a spill of either the UNAT register or the PR
1262 register. (Well, not exactly; what we've actually found is
1263 a spill of the register that UNAT or PR was moved to).
1264 Record that fact and move on... */
1265 if (rM == unat_save_reg)
1266 {
1267 /* Track UNAT register */
004d836a 1268 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1269 unat_save_reg = 0;
1270 }
1271 else
1272 {
1273 /* Track PR register */
004d836a 1274 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1275 pr_save_reg = 0;
1276 }
1277 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1278 /* st8 [rN] = rM, imm9 */
1279 spill_addr += imm9(instr);
1280 else
1281 spill_addr = 0; /* must be done spilling */
1282 last_prologue_pc = next_pc;
1283 }
0927a22b
KB		 1284 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1285 {
1286 /* Allow up to one store of each input register. */
1287 instores[rM-32] = 1;
1288 last_prologue_pc = next_pc;
1289 }
5ea2bd7f
JJ		 1290 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1291 !instores[indirect-32])
1292 {
1293 /* Allow an indirect store of an input register. */
1294 instores[indirect-32] = 1;
1295 last_prologue_pc = next_pc;
1296 }
0927a22b
KB		 1297 }
1298 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1299 {
1300 /* One of
1301 st1 [rN] = rM
1302 st2 [rN] = rM
1303 st4 [rN] = rM
1304 st8 [rN] = rM
1305 Note that the st8 case is handled in the clause above.
1306
1307 Advance over stores of input registers. One store per input
1308 register is permitted. */
1309 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1310 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1311 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1312 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1313 {
1314 instores[rM-32] = 1;
1315 last_prologue_pc = next_pc;
1316 }
5ea2bd7f
JJ		 1317 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1318 !instores[indirect-32])
1319 {
1320 /* Allow an indirect store of an input register. */
1321 instores[indirect-32] = 1;
1322 last_prologue_pc = next_pc;
1323 }
0927a22b
KB		 1324 }
1325 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1326 {
1327 /* Either
1328 stfs [rN] = fM
1329 or
1330 stfd [rN] = fM
1331
1332 Advance over stores of floating point input registers. Again
1333 one store per register is permitted */
1334 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1335 int qp = (int) (instr & 0x0000000003fLL);
1336 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1337 {
1338 infpstores[fM-8] = 1;
1339 last_prologue_pc = next_pc;
1340 }
16461d7d
KB		 1341 }
1342 else if (it == M
1343 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1344 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1345 {
1346 /* st8.spill [rN] = rM
1347 or
1348 st8.spill [rN] = rM, imm9 */
1349 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1350 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1351 int qp = (int) (instr & 0x0000000003fLL);
1352 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1353 {
1354 /* We've found a spill of one of the preserved general purpose
1355 regs. Record the spill address and advance the spill
1356 register if appropriate. */
004d836a 1357 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1358 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1359 /* st8.spill [rN] = rM, imm9 */
1360 spill_addr += imm9(instr);
1361 else
1362 spill_addr = 0; /* Done spilling */
1363 last_prologue_pc = next_pc;
1364 }
1365 }
16461d7d
KB		 1366
1367 pc = next_pc;
1368 }
1369
004d836a
JJ		 1370 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1371 registers for the previous frame which will be needed later. */
16461d7d 1372
004d836a 1373 if (!frameless && next_frame)
da50a4b7 1374 {
004d836a
JJ		 1375 /* Extract the size of the rotating portion of the stack
1376 frame and the register rename base from the current
1377 frame marker. */
1378 cfm = cache->cfm;
1379 sor = cache->sor;
1380 sof = cache->sof;
1381 sol = cache->sol;
1382 rrb_gr = (cfm >> 18) & 0x7f;
1383
1384 /* Find the bof (beginning of frame). */
1385 bof = rse_address_add (cache->bsp, -sof);
1386
1387 for (i = 0, addr = bof;
1388 i < sof;
1389 i++, addr += 8)
1390 {
1391 if (IS_NaT_COLLECTION_ADDR (addr))
1392 {
1393 addr += 8;
1394 }
1395 if (i+32 == cfm_reg)
1396 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1397 if (i+32 == ret_reg)
1398 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1399 if (i+32 == fp_reg)
1400 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1401 }
16461d7d 1402
004d836a
JJ		 1403 /* For the previous argument registers we require the previous bof.
1404 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1405 cfm = 0;
004d836a
JJ		 1406 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1407 {
1408 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1409 }
1410 else if (cfm_reg != 0)
1411 {
1412 frame_unwind_register (next_frame, cfm_reg, buf);
1413 cfm = extract_unsigned_integer (buf, 8);
1414 }
1415 cache->prev_cfm = cfm;
1416
1417 if (cfm != 0)
1418 {
004d836a
JJ		 1419 sor = ((cfm >> 14) & 0xf) * 8;
1420 sof = (cfm & 0x7f);
1421 sol = (cfm >> 7) & 0x7f;
1422 rrb_gr = (cfm >> 18) & 0x7f;
1423
1424 /* The previous bof only requires subtraction of the sol (size of locals)
1425 due to the overlap between output and input of subsequent frames. */
1426 bof = rse_address_add (bof, -sol);
1427
1428 for (i = 0, addr = bof;
1429 i < sof;
1430 i++, addr += 8)
1431 {
1432 if (IS_NaT_COLLECTION_ADDR (addr))
1433 {
1434 addr += 8;
1435 }
1436 if (i < sor)
1437 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1438 = addr;
1439 else
1440 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1441 }
1442
1443 }
1444 }
1445
5ea2bd7f
JJ		 1446 /* Try and trust the lim_pc value whenever possible. */
1447 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1448 last_prologue_pc = lim_pc;
1449
1450 cache->frameless = frameless;
1451 cache->after_prologue = last_prologue_pc;
1452 cache->mem_stack_frame_size = mem_stack_frame_size;
1453 cache->fp_reg = fp_reg;
5ea2bd7f 1454
16461d7d
KB		 1455 return last_prologue_pc;
1456}
1457
1458CORE_ADDR
1459ia64_skip_prologue (CORE_ADDR pc)
1460{
004d836a
JJ		 1461 struct ia64_frame_cache cache;
1462 cache.base = 0;
1463 cache.after_prologue = 0;
1464 cache.cfm = 0;
1465 cache.bsp = 0;
1466
1467 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1468 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1469}
1470
004d836a
JJ		 1471
1472/* Normal frames. */
1473
1474static struct ia64_frame_cache *
1475ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1476{
004d836a
JJ		 1477 struct ia64_frame_cache *cache;
1478 char buf[8];
1479 CORE_ADDR cfm, sof, sol, bsp, psr;
1480 int i;
16461d7d 1481
004d836a
JJ		 1482 if (*this_cache)
1483 return *this_cache;
16461d7d 1484
004d836a
JJ		 1485 cache = ia64_alloc_frame_cache ();
1486 *this_cache = cache;
16461d7d 1487
004d836a
JJ		 1488 frame_unwind_register (next_frame, sp_regnum, buf);
1489 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1490
004d836a
JJ		 1491 /* We always want the bsp to point to the end of frame.
1492 This way, we can always get the beginning of frame (bof)
1493 by subtracting frame size. */
1494 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1495 cache->bsp = extract_unsigned_integer (buf, 8);
1496
1497 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1498 psr = extract_unsigned_integer (buf, 8);
1499
1500 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1501 cfm = extract_unsigned_integer (buf, 8);
1502
1503 cache->sof = (cfm & 0x7f);
1504 cache->sol = (cfm >> 7) & 0x7f;
1505 cache->sor = ((cfm >> 14) & 0xf) * 8;
1506
1507 cache->cfm = cfm;
1508
1509 cache->pc = frame_func_unwind (next_frame);
1510
1511 if (cache->pc != 0)
1512 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1513
1514 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1515
1516 return cache;
16461d7d
KB		 1517}
1518
a78f21af 1519static void
004d836a
JJ		 1520ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1521 struct frame_id *this_id)
16461d7d 1522{
004d836a
JJ		 1523 struct ia64_frame_cache *cache =
1524 ia64_frame_cache (next_frame, this_cache);
16461d7d 1525
004d836a
JJ		 1526 /* This marks the outermost frame. */
1527 if (cache->base == 0)
1528 return;
16461d7d 1529
4afcc598
JJ		 1530 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1531 if (gdbarch_debug >= 1)
1532 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1533 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1534 paddr_nz (this_id->code_addr),
1535 paddr_nz (this_id->stack_addr),
1536 paddr_nz (cache->bsp), next_frame);
004d836a 1537}
244bc108 1538
004d836a
JJ		 1539static void
1540ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1541 int regnum, int *optimizedp,
1542 enum lval_type *lvalp, CORE_ADDR *addrp,
1543 int *realnump, void *valuep)
1544{
1545 struct ia64_frame_cache *cache =
1546 ia64_frame_cache (next_frame, this_cache);
1547 char dummy_valp[MAX_REGISTER_SIZE];
1548 char buf[8];
1549
1550 gdb_assert (regnum >= 0);
244bc108 1551
004d836a 1552 if (!target_has_registers)
8a3fe4f8 1553 error (_("No registers."));
244bc108 1554
004d836a
JJ		 1555 *optimizedp = 0;
1556 *addrp = 0;
1557 *lvalp = not_lval;
1558 *realnump = -1;
244bc108 1559
004d836a
JJ		 1560 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1561 when valuep is not supplied. */
1562 if (!valuep)
1563 valuep = dummy_valp;
1564
aa2a9a3c 1565 memset (valuep, 0, register_size (current_gdbarch, regnum));
004d836a
JJ		 1566
1567 if (regnum == SP_REGNUM)
16461d7d
KB		 1568 {
1569 /* Handle SP values for all frames but the topmost. */
aa2a9a3c 1570 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a 1571 cache->base);
16461d7d
KB		 1572 }
1573 else if (regnum == IA64_BSP_REGNUM)
1574 {
004d836a
JJ		 1575 char cfm_valuep[MAX_REGISTER_SIZE];
1576 int cfm_optim;
1577 int cfm_realnum;
1578 enum lval_type cfm_lval;
1579 CORE_ADDR cfm_addr;
1580 CORE_ADDR bsp, prev_cfm, prev_bsp;
1581
1582 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1583 This corresponds to what the hardware bsp register will be if we pop the frame
1584 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1585 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1586 the start of the output registers. We can calculate the end of that frame by adding
1587 the size of output (sof (size of frame) - sol (size of locals)). */
1588 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1589 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1590 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1591
1592 bsp = rse_address_add (cache->bsp, -(cache->sof));
1593 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1594
aa2a9a3c 1595 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a
JJ		 1596 prev_bsp);
1597 }
1598 else if (regnum == IA64_CFM_REGNUM)
1599 {
4afcc598
JJ		 1600 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1601
1602 if (addr != 0)
004d836a 1603 {
4afcc598
JJ		 1604 *lvalp = lval_memory;
1605 *addrp = addr;
1606 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a 1607 }
4afcc598
JJ		 1608 else if (cache->prev_cfm)
1609 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1610 else if (cache->frameless)
004d836a 1611 {
4afcc598
JJ		 1612 CORE_ADDR cfm = 0;
1613 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1614 }
16461d7d
KB		 1615 }
1616 else if (regnum == IA64_VFP_REGNUM)
1617 {
1618 /* If the function in question uses an automatic register (r32-r127)
1619 for the frame pointer, it'll be found by ia64_find_saved_register()
1620 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1621 still provide a value since we know the size of the frame. */
1622 CORE_ADDR vfp = cache->base;
aa2a9a3c 1623 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1624 }
004d836a 1625 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1626 {
004d836a 1627 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1628 int pr_optim;
004d836a 1629 int pr_realnum;
16461d7d
KB		 1630 enum lval_type pr_lval;
1631 CORE_ADDR pr_addr;
004d836a
JJ		 1632 ULONGEST prN_val;
1633 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1634 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1635 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1636 {
1637 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1638 marker for this frame. */
1639 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1640
004d836a
JJ		 1641 /* Adjust the register number to account for register rotation. */
1642 regnum = VP16_REGNUM
1643 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1644 }
004d836a
JJ		 1645 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1646 regnum - VP0_REGNUM, 1);
aa2a9a3c 1647 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
16461d7d
KB		 1648 }
1649 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1650 {
004d836a 1651 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1652 int unat_optim;
004d836a 1653 int unat_realnum;
16461d7d
KB		 1654 enum lval_type unat_lval;
1655 CORE_ADDR unat_addr;
004d836a
JJ		 1656 ULONGEST unatN_val;
1657 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1658 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1659 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1660 regnum - IA64_NAT0_REGNUM, 1);
aa2a9a3c 1661 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
16461d7d 1662 unatN_val);
16461d7d
KB		 1663 }
1664 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1665 {
1666 int natval = 0;
1667 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1668 interested in. */
1669 CORE_ADDR gr_addr;
244bc108 1670
004d836a
JJ		 1671 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1672 + IA64_GR0_REGNUM];
1673 if (gr_addr != 0)
244bc108 1674 {
004d836a 1675 /* Compute address of nat collection bits. */
16461d7d 1676 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1677 CORE_ADDR bsp;
16461d7d
KB		 1678 CORE_ADDR nat_collection;
1679 int nat_bit;
1680 /* If our nat collection address is bigger than bsp, we have to get
1681 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1682 collection from the computed address. */
1683 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1684 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1685 if (nat_addr >= bsp)
004d836a
JJ		 1686 {
1687 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1688 nat_collection = extract_unsigned_integer (buf, 8);
1689 }
16461d7d
KB		 1690 else
1691 nat_collection = read_memory_integer (nat_addr, 8);
1692 nat_bit = (gr_addr >> 3) & 0x3f;
1693 natval = (nat_collection >> nat_bit) & 1;
1694 }
004d836a 1695
aa2a9a3c 1696 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
244bc108
KB		 1697 }
1698 else if (regnum == IA64_IP_REGNUM)
1699 {
004d836a 1700 CORE_ADDR pc = 0;
4afcc598 1701 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1702
4afcc598 1703 if (addr != 0)
004d836a 1704 {
4afcc598
JJ		 1705 *lvalp = lval_memory;
1706 *addrp = addr;
1707 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1708 pc = extract_unsigned_integer (buf, 8);
1709 }
4afcc598 1710 else if (cache->frameless)
004d836a 1711 {
4afcc598
JJ		 1712 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1713 pc = extract_unsigned_integer (buf, 8);
244bc108 1714 }
004d836a
JJ		 1715 pc &= ~0xf;
1716 store_unsigned_integer (valuep, 8, pc);
244bc108 1717 }
004d836a 1718 else if (regnum == IA64_PSR_REGNUM)
244bc108 1719 {
4afcc598
JJ		 1720 /* We don't know how to get the complete previous PSR, but we need it for
1721 the slot information when we unwind the pc (pc is formed of IP register
1722 plus slot information from PSR). To get the previous slot information,
1723 we mask it off the return address. */
004d836a
JJ		 1724 ULONGEST slot_num = 0;
1725 CORE_ADDR pc= 0;
1726 CORE_ADDR psr = 0;
4afcc598 1727 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1728
1729 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1730 psr = extract_unsigned_integer (buf, 8);
1731
4afcc598 1732 if (addr != 0)
244bc108 1733 {
4afcc598
JJ		 1734 *lvalp = lval_memory;
1735 *addrp = addr;
1736 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a 1737 pc = extract_unsigned_integer (buf, 8);
244bc108 1738 }
4afcc598 1739 else if (cache->frameless)
004d836a 1740 {
4afcc598
JJ		 1741 CORE_ADDR pc;
1742 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1743 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1744 }
1745 psr &= ~(3LL << 41);
1746 slot_num = pc & 0x3LL;
1747 psr |= (CORE_ADDR)slot_num << 41;
1748 store_unsigned_integer (valuep, 8, psr);
1749 }
4afcc598
JJ		 1750 else if (regnum == IA64_BR0_REGNUM)
1751 {
1752 CORE_ADDR br0 = 0;
1753 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1754 if (addr != 0)
1755 {
1756 *lvalp = lval_memory;
1757 *addrp = addr;
1758 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1759 br0 = extract_unsigned_integer (buf, 8);
1760 }
1761 store_unsigned_integer (valuep, 8, br0);
1762 }
004d836a
JJ		 1763 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1764 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1765 {
1766 CORE_ADDR addr = 0;
1767 if (regnum >= V32_REGNUM)
1768 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1769 addr = cache->saved_regs[regnum];
244bc108
KB		 1770 if (addr != 0)
1771 {
004d836a
JJ		 1772 *lvalp = lval_memory;
1773 *addrp = addr;
aa2a9a3c 1774 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1775 }
004d836a 1776 else if (cache->frameless)
244bc108 1777 {
004d836a
JJ		 1778 char r_valuep[MAX_REGISTER_SIZE];
1779 int r_optim;
1780 int r_realnum;
1781 enum lval_type r_lval;
1782 CORE_ADDR r_addr;
1783 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1784 CORE_ADDR addr = 0;
1785 if (regnum >= V32_REGNUM)
1786 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1787 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1788 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1789 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1790 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1791 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1792 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1793 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1794
1795 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1796 *lvalp = lval_memory;
1797 *addrp = addr;
aa2a9a3c 1798 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1799 }
16461d7d
KB		 1800 }
1801 else
1802 {
004d836a 1803 CORE_ADDR addr = 0;
3a854e23
KB		 1804 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1805 {
1806 /* Fetch floating point register rename base from current
004d836a
JJ		 1807 frame marker for this frame. */
1808 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1809
1810 /* Adjust the floating point register number to account for
004d836a 1811 register rotation. */
3a854e23
KB		 1812 regnum = IA64_FR32_REGNUM
1813 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1814 }
1815
004d836a
JJ		 1816 /* If we have stored a memory address, access the register. */
1817 addr = cache->saved_regs[regnum];
1818 if (addr != 0)
1819 {
1820 *lvalp = lval_memory;
1821 *addrp = addr;
aa2a9a3c 1822 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a
JJ		 1823 }
1824 /* Otherwise, punt and get the current value of the register. */
1825 else
1826 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1827 }
4afcc598
JJ		 1828
1829 if (gdbarch_debug >= 1)
1830 fprintf_unfiltered (gdb_stdlog,
78ced177 1831 "regular prev register <%d> <%s> is 0x%s\n", regnum,
4afcc598 1832 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 1833 ? ia64_register_names[regnum] : "r??"),
1834 paddr_nz (extract_unsigned_integer (valuep, 8)));
16461d7d 1835}
004d836a
JJ		 1836
1837static const struct frame_unwind ia64_frame_unwind =
1838{
1839 NORMAL_FRAME,
1840 &ia64_frame_this_id,
1841 &ia64_frame_prev_register
1842};
1843
1844static const struct frame_unwind *
1845ia64_frame_sniffer (struct frame_info *next_frame)
1846{
1847 return &ia64_frame_unwind;
1848}
1849
1850/* Signal trampolines. */
1851
1852static void
1853ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1854{
1855 if (SIGCONTEXT_REGISTER_ADDRESS)
1856 {
1857 int regno;
1858
1859 cache->saved_regs[IA64_VRAP_REGNUM] =
1860 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1861 cache->saved_regs[IA64_CFM_REGNUM] =
1862 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1863 cache->saved_regs[IA64_PSR_REGNUM] =
1864 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
004d836a 1865 cache->saved_regs[IA64_BSP_REGNUM] =
4afcc598 1866 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
004d836a
JJ		 1867 cache->saved_regs[IA64_RNAT_REGNUM] =
1868 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1869 cache->saved_regs[IA64_CCV_REGNUM] =
1870 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1871 cache->saved_regs[IA64_UNAT_REGNUM] =
1872 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1873 cache->saved_regs[IA64_FPSR_REGNUM] =
1874 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1875 cache->saved_regs[IA64_PFS_REGNUM] =
1876 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1877 cache->saved_regs[IA64_LC_REGNUM] =
1878 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1879 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598
JJ		 1880 cache->saved_regs[regno] =
1881 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
004d836a
JJ		 1882 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1883 cache->saved_regs[regno] =
1884 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
932644f0 1885 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a
JJ		 1886 cache->saved_regs[regno] =
1887 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1888 }
1889}
1890
1891static struct ia64_frame_cache *
1892ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1893{
1894 struct ia64_frame_cache *cache;
1895 CORE_ADDR addr;
1896 char buf[8];
1897 int i;
1898
1899 if (*this_cache)
1900 return *this_cache;
1901
1902 cache = ia64_alloc_frame_cache ();
1903
1904 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1905 /* Note that frame size is hard-coded below. We cannot calculate it
1906 via prologue examination. */
1907 cache->base = extract_unsigned_integer (buf, 8) + 16;
1908
1909 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1910 cache->bsp = extract_unsigned_integer (buf, 8);
1911
1912 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1913 cache->cfm = extract_unsigned_integer (buf, 8);
1914 cache->sof = cache->cfm & 0x7f;
004d836a
JJ		 1915
1916 ia64_sigtramp_frame_init_saved_regs (cache);
1917
1918 *this_cache = cache;
1919 return cache;
1920}
1921
1922static void
1923ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1924 void **this_cache, struct frame_id *this_id)
1925{
1926 struct ia64_frame_cache *cache =
1927 ia64_sigtramp_frame_cache (next_frame, this_cache);
1928
4afcc598
JJ		 1929 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1930 if (gdbarch_debug >= 1)
1931 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1932 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1933 paddr_nz (this_id->code_addr),
1934 paddr_nz (this_id->stack_addr),
1935 paddr_nz (cache->bsp), next_frame);
004d836a
JJ		 1936}
1937
1938static void
1939ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1940 void **this_cache,
1941 int regnum, int *optimizedp,
1942 enum lval_type *lvalp, CORE_ADDR *addrp,
1943 int *realnump, void *valuep)
1944{
4afcc598
JJ		 1945 char dummy_valp[MAX_REGISTER_SIZE];
1946 char buf[MAX_REGISTER_SIZE];
1947
1948 struct ia64_frame_cache *cache =
1949 ia64_sigtramp_frame_cache (next_frame, this_cache);
1950
1951 gdb_assert (regnum >= 0);
1952
1953 if (!target_has_registers)
8a3fe4f8 1954 error (_("No registers."));
4afcc598
JJ		 1955
1956 *optimizedp = 0;
1957 *addrp = 0;
1958 *lvalp = not_lval;
1959 *realnump = -1;
1960
1961 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1962 when valuep is not supplied. */
1963 if (!valuep)
1964 valuep = dummy_valp;
1965
1966 memset (valuep, 0, register_size (current_gdbarch, regnum));
1967
1968 if (regnum == IA64_IP_REGNUM)
1969 {
1970 CORE_ADDR pc = 0;
1971 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1972
1973 if (addr != 0)
1974 {
1975 *lvalp = lval_memory;
1976 *addrp = addr;
1977 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
1978 pc = extract_unsigned_integer (buf, 8);
1979 }
1980 pc &= ~0xf;
1981 store_unsigned_integer (valuep, 8, pc);
1982 }
1983 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1984 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1985 {
1986 CORE_ADDR addr = 0;
1987 if (regnum >= V32_REGNUM)
1988 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1989 addr = cache->saved_regs[regnum];
1990 if (addr != 0)
1991 {
1992 *lvalp = lval_memory;
1993 *addrp = addr;
1994 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
1995 }
1996 }
1997 else
1998 {
1999 /* All other registers not listed above. */
2000 CORE_ADDR addr = cache->saved_regs[regnum];
2001 if (addr != 0)
2002 {
2003 *lvalp = lval_memory;
2004 *addrp = addr;
2005 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2006 }
2007 }
004d836a 2008
4afcc598
JJ		 2009 if (gdbarch_debug >= 1)
2010 fprintf_unfiltered (gdb_stdlog,
78ced177 2011 "sigtramp prev register <%s> is 0x%s\n",
4afcc598 2012 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2013 ? ia64_register_names[regnum] : "r??"),
2014 paddr_nz (extract_unsigned_integer (valuep, 8)));
004d836a
JJ		 2015}
2016
2017static const struct frame_unwind ia64_sigtramp_frame_unwind =
2018{
2019 SIGTRAMP_FRAME,
2020 ia64_sigtramp_frame_this_id,
2021 ia64_sigtramp_frame_prev_register
2022};
2023
2024static const struct frame_unwind *
2025ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2026{
2027 char *name;
2028 CORE_ADDR pc = frame_pc_unwind (next_frame);
2029
2030 find_pc_partial_function (pc, &name, NULL, NULL);
0b281939 2031 if (legacy_pc_in_sigtramp (pc, name))
004d836a
JJ		 2032 return &ia64_sigtramp_frame_unwind;
2033
2034 return NULL;
2035}
2036\f
2037
2038static CORE_ADDR
2039ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2040{
2041 struct ia64_frame_cache *cache =
2042 ia64_frame_cache (next_frame, this_cache);
2043
2044 return cache->base;
2045}
2046
2047static const struct frame_base ia64_frame_base =
2048{
2049 &ia64_frame_unwind,
2050 ia64_frame_base_address,
2051 ia64_frame_base_address,
2052 ia64_frame_base_address
2053};
16461d7d 2054
968d1cb4
JJ		 2055#ifdef HAVE_LIBUNWIND_IA64_H
2056
2057struct ia64_unwind_table_entry
2058 {
2059 unw_word_t start_offset;
2060 unw_word_t end_offset;
2061 unw_word_t info_offset;
2062 };
2063
2064static __inline__ uint64_t
2065ia64_rse_slot_num (uint64_t addr)
2066{
2067 return (addr >> 3) & 0x3f;
2068}
2069
2070/* Skip over a designated number of registers in the backing
2071 store, remembering every 64th position is for NAT. */
2072static __inline__ uint64_t
2073ia64_rse_skip_regs (uint64_t addr, long num_regs)
2074{
2075 long delta = ia64_rse_slot_num(addr) + num_regs;
2076
2077 if (num_regs < 0)
2078 delta -= 0x3e;
2079 return addr + ((num_regs + delta/0x3f) << 3);
2080}
2081
2082/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2083 number to a libunwind register number. */
2084static int
2085ia64_gdb2uw_regnum (int regnum)
2086{
2087 if (regnum == sp_regnum)
2088 return UNW_IA64_SP;
2089 else if (regnum == IA64_BSP_REGNUM)
2090 return UNW_IA64_BSP;
2091 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2092 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2093 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2094 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2095 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2096 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2097 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2098 return -1;
2099 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2100 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2101 else if (regnum == IA64_PR_REGNUM)
2102 return UNW_IA64_PR;
2103 else if (regnum == IA64_IP_REGNUM)
2104 return UNW_REG_IP;
2105 else if (regnum == IA64_CFM_REGNUM)
2106 return UNW_IA64_CFM;
2107 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2108 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2109 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2110 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2111 else
2112 return -1;
2113}
2114
2115/* Gdb libunwind-frame callback function to convert from a libunwind register
2116 number to a ia64 gdb register number. */
2117static int
2118ia64_uw2gdb_regnum (int uw_regnum)
2119{
2120 if (uw_regnum == UNW_IA64_SP)
2121 return sp_regnum;
2122 else if (uw_regnum == UNW_IA64_BSP)
2123 return IA64_BSP_REGNUM;
2124 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2125 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2126 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2127 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2128 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2129 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2130 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2131 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2132 else if (uw_regnum == UNW_IA64_PR)
2133 return IA64_PR_REGNUM;
2134 else if (uw_regnum == UNW_REG_IP)
2135 return IA64_IP_REGNUM;
2136 else if (uw_regnum == UNW_IA64_CFM)
2137 return IA64_CFM_REGNUM;
2138 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2139 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2140 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2141 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2142 else
2143 return -1;
2144}
2145
2146/* Gdb libunwind-frame callback function to reveal if register is a float
2147 register or not. */
2148static int
2149ia64_is_fpreg (int uw_regnum)
2150{
2151 return unw_is_fpreg (uw_regnum);
2152}
2153
2154/* Libunwind callback accessor function for general registers. */
2155static int
2156ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2157 int write, void *arg)
2158{
2159 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2160 unw_word_t bsp, sof, sol, cfm, psr, ip;
2161 struct frame_info *next_frame = arg;
2162 long new_sof, old_sof;
2163 char buf[MAX_REGISTER_SIZE];
2164
2165 if (write)
2166 {
2167 if (regnum < 0)
2168 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2169 return 0;
2170
2171 switch (uw_regnum)
2172 {
2173 case UNW_REG_IP:
2174 ia64_write_pc (*val, inferior_ptid);
2175 break;
2176
2177 case UNW_IA64_AR_BSPSTORE:
2178 write_register (IA64_BSP_REGNUM, *val);
2179 break;
2180
2181 case UNW_IA64_AR_BSP:
2182 case UNW_IA64_BSP:
2183 /* Account for the fact that ptrace() expects bsp to point
2184 after the current register frame. */
2185 cfm = read_register (IA64_CFM_REGNUM);
2186 sof = (cfm & 0x7f);
2187 bsp = ia64_rse_skip_regs (*val, sof);
2188 write_register (IA64_BSP_REGNUM, bsp);
2189 break;
2190
2191 case UNW_IA64_CFM:
2192 /* If we change CFM, we need to adjust ptrace's notion of
2193 bsp accordingly, so that the real bsp remains
2194 unchanged. */
2195 bsp = read_register (IA64_BSP_REGNUM);
2196 cfm = read_register (IA64_CFM_REGNUM);
2197 old_sof = (cfm & 0x7f);
2198 new_sof = (*val & 0x7f);
2199 if (old_sof != new_sof)
2200 {
2201 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2202 write_register (IA64_BSP_REGNUM, bsp);
2203 }
2204 write_register (IA64_CFM_REGNUM, *val);
2205 break;
2206
2207 default:
2208 write_register (regnum, *val);
2209 break;
2210 }
2211 if (gdbarch_debug >= 1)
2212 fprintf_unfiltered (gdb_stdlog,
78ced177 2213 " access_reg: to cache: %4s=0x%s\n",
968d1cb4 2214 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2215 ? ia64_register_names[regnum] : "r??"),
2216 paddr_nz (*val));
968d1cb4
JJ		 2217 }
2218 else
2219 {
2220 switch (uw_regnum)
2221 {
2222 case UNW_REG_IP:
2223 /* Libunwind expects to see the pc value which means the slot number
2224 from the psr must be merged with the ip word address. */
2225 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2226 ip = extract_unsigned_integer (buf, 8);
2227 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2228 psr = extract_unsigned_integer (buf, 8);
2229 *val = ip | ((psr >> 41) & 0x3);
2230 break;
2231
2232 case UNW_IA64_AR_BSP:
2233 /* Libunwind expects to see the beginning of the current register
2234 frame so we must account for the fact that ptrace() will return a value
2235 for bsp that points *after* the current register frame. */
2236 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2237 bsp = extract_unsigned_integer (buf, 8);
2238 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2239 cfm = extract_unsigned_integer (buf, 8);
2240 sof = (cfm & 0x7f);
2241 *val = ia64_rse_skip_regs (bsp, -sof);
2242 break;
2243
2244 case UNW_IA64_AR_BSPSTORE:
2245 /* Libunwind wants bspstore to be after the current register frame.
2246 This is what ptrace() and gdb treats as the regular bsp value. */
2247 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2248 *val = extract_unsigned_integer (buf, 8);
2249 break;
2250
2251 default:
2252 /* For all other registers, just unwind the value directly. */
2253 frame_unwind_register (next_frame, regnum, buf);
2254 *val = extract_unsigned_integer (buf, 8);
2255 break;
2256 }
2257
2258 if (gdbarch_debug >= 1)
2259 fprintf_unfiltered (gdb_stdlog,
78ced177 2260 " access_reg: from cache: %4s=0x%s\n",
968d1cb4 2261 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2262 ? ia64_register_names[regnum] : "r??"),
2263 paddr_nz (*val));
968d1cb4
JJ		 2264 }
2265 return 0;
2266}
2267
2268/* Libunwind callback accessor function for floating-point registers. */
2269static int
2270ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2271 int write, void *arg)
2272{
2273 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2274
2275 if (write)
2276 regcache_cooked_write (current_regcache, regnum, (char *) val);
2277 else
2278 regcache_cooked_read (current_regcache, regnum, (char *) val);
2279 return 0;
2280}
2281
2282/* Libunwind callback accessor function for accessing memory. */
2283static int
2284ia64_access_mem (unw_addr_space_t as,
2285 unw_word_t addr, unw_word_t *val,
2286 int write, void *arg)
2287{
2288 /* XXX do we need to normalize byte-order here? */
2289 if (write)
2290 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2291 else
2292 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2293}
2294
2295/* Call low-level function to access the kernel unwind table. */
2296static int
2297getunwind_table (void *buf, size_t len)
2298{
2299 LONGEST x;
2300 x = target_read_partial (&current_target, TARGET_OBJECT_UNWIND_TABLE, NULL,
2301 buf, 0, len);
2302
2303 return (int)x;
2304}
2305
2306/* Get the kernel unwind table. */
2307static int
2308get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2309{
2310 size_t size;
2311 struct ia64_table_entry
2312 {
2313 uint64_t start_offset;
2314 uint64_t end_offset;
2315 uint64_t info_offset;
2316 };
2317 static struct ia64_table_entry *ktab = NULL, *etab;
2318
2319 if (!ktab)
2320 {
2321 size = getunwind_table (NULL, 0);
2322 if ((int)size < 0)
2323 return -UNW_ENOINFO;
2324 ktab = xmalloc (size);
2325 getunwind_table (ktab, size);
2326
2327 /* Determine length of kernel's unwind table and relocate
2328 it's entries. */
2329 for (etab = ktab; etab->start_offset; ++etab)
2330 etab->info_offset += (uint64_t) ktab;
2331 }
2332
2333 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2334 return -UNW_ENOINFO;
2335
2336 di->format = UNW_INFO_FORMAT_TABLE;
2337 di->gp = 0;
2338 di->start_ip = ktab[0].start_offset;
2339 di->end_ip = etab[-1].end_offset;
2340 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2341 di->u.ti.segbase = 0;
2342 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2343 di->u.ti.table_data = (unw_word_t *) ktab;
2344
2345 if (gdbarch_debug >= 1)
2346 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
78ced177
JJ		 2347 "segbase=0x%s, length=%s, gp=0x%s\n",
2348 (char *) di->u.ti.name_ptr,
2349 paddr_nz (di->u.ti.segbase),
2350 paddr_u (di->u.ti.table_len),
2351 paddr_nz (di->gp));
968d1cb4
JJ		 2352 return 0;
2353}
2354
2355/* Find the unwind table entry for a specified address. */
2356static int
2357ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2358 unw_dyn_info_t *dip, void **buf)
2359{
2360 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2361 Elf_Internal_Ehdr *ehdr;
2362 unw_word_t segbase = 0;
2363 CORE_ADDR load_base;
2364 bfd *bfd;
2365 int i;
2366
2367 bfd = objfile->obfd;
2368
2369 ehdr = elf_tdata (bfd)->elf_header;
2370 phdr = elf_tdata (bfd)->phdr;
2371
2372 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2373
2374 for (i = 0; i < ehdr->e_phnum; ++i)
2375 {
2376 switch (phdr[i].p_type)
2377 {
2378 case PT_LOAD:
2379 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2380 < phdr[i].p_memsz)
2381 p_text = phdr + i;
2382 break;
2383
2384 case PT_IA_64_UNWIND:
2385 p_unwind = phdr + i;
2386 break;
2387
2388 default:
2389 break;
2390 }
2391 }
2392
2393 if (!p_text || !p_unwind
2394 /* Verify that the segment that contains the IP also contains
2395 the static unwind table. If not, we are dealing with
2396 runtime-generated code, for which we have no info here. */
2397 || (p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2398 return -UNW_ENOINFO;
2399
2400 segbase = p_text->p_vaddr + load_base;
2401
2402 dip->start_ip = segbase;
2403 dip->end_ip = dip->start_ip + p_text->p_memsz;
b33e8514 2404 dip->gp = ia64_find_global_pointer (ip);
503ff15d
KB		 2405 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2406 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2407 dip->u.rti.segbase = segbase;
2408 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2409 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
968d1cb4
JJ		 2410
2411 return 0;
2412}
2413
2414/* Libunwind callback accessor function to acquire procedure unwind-info. */
2415static int
2416ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2417 int need_unwind_info, void *arg)
2418{
2419 struct obj_section *sec = find_pc_section (ip);
2420 unw_dyn_info_t di;
2421 int ret;
2422 void *buf = NULL;
2423
2424 if (!sec)
2425 {
2426 /* XXX This only works if the host and the target architecture are
2427 both ia64 and if the have (more or less) the same kernel
2428 version. */
2429 if (get_kernel_table (ip, &di) < 0)
2430 return -UNW_ENOINFO;
503ff15d
KB		 2431
2432 if (gdbarch_debug >= 1)
78ced177
JJ		 2433 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2434 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2435 "length=%s,data=0x%s)\n",
2436 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2437 paddr_nz (di.u.ti.segbase),
2438 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2439 paddr_nz (di.gp),
2440 paddr_u (di.u.ti.table_len),
2441 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
968d1cb4
JJ		 2442 }
2443 else
2444 {
2445 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2446 if (ret < 0)
2447 return ret;
968d1cb4 2448
503ff15d 2449 if (gdbarch_debug >= 1)
78ced177
JJ		 2450 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2451 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2452 "length=%s,data=0x%s)\n",
2453 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2454 paddr_nz (di.u.rti.segbase),
2455 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2456 paddr_nz (di.gp),
2457 paddr_u (di.u.rti.table_len),
2458 paddr_nz (di.u.rti.table_data));
503ff15d 2459 }
968d1cb4 2460
503ff15d
KB		 2461 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2462 arg);
968d1cb4
JJ		 2463
2464 /* We no longer need the dyn info storage so free it. */
2465 xfree (buf);
2466
2467 return ret;
2468}
2469
2470/* Libunwind callback accessor function for cleanup. */
2471static void
2472ia64_put_unwind_info (unw_addr_space_t as,
2473 unw_proc_info_t *pip, void *arg)
2474{
2475 /* Nothing required for now. */
2476}
2477
2478/* Libunwind callback accessor function to get head of the dynamic
2479 unwind-info registration list. */
2480static int
2481ia64_get_dyn_info_list (unw_addr_space_t as,
2482 unw_word_t *dilap, void *arg)
2483{
2484 struct obj_section *text_sec;
2485 struct objfile *objfile;
2486 unw_word_t ip, addr;
2487 unw_dyn_info_t di;
2488 int ret;
2489
2490 if (!libunwind_is_initialized ())
2491 return -UNW_ENOINFO;
2492
2493 for (objfile = object_files; objfile; objfile = objfile->next)
2494 {
2495 void *buf = NULL;
2496
2497 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2498 ip = text_sec->addr;
2499 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2500 if (ret >= 0)
2501 {
503ff15d 2502 addr = libunwind_find_dyn_list (as, &di, arg);
968d1cb4
JJ		 2503 /* We no longer need the dyn info storage so free it. */
2504 xfree (buf);
2505
2506 if (addr)
2507 {
2508 if (gdbarch_debug >= 1)
2509 fprintf_unfiltered (gdb_stdlog,
2510 "dynamic unwind table in objfile %s "
78ced177 2511 "at 0x%s (gp=0x%s)\n",
968d1cb4 2512 bfd_get_filename (objfile->obfd),
78ced177 2513 paddr_nz (addr), paddr_nz (di.gp));
968d1cb4
JJ		 2514 *dilap = addr;
2515 return 0;
2516 }
2517 }
2518 }
2519 return -UNW_ENOINFO;
2520}
2521
2522
2523/* Frame interface functions for libunwind. */
2524
2525static void
2526ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
2527 struct frame_id *this_id)
2528{
2529 char buf[8];
2530 CORE_ADDR bsp;
2531 struct frame_id id;
2532
2533 libunwind_frame_this_id (next_frame, this_cache, &id);
2534
2535 /* We must add the bsp as the special address for frame comparison purposes. */
2536 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2537 bsp = extract_unsigned_integer (buf, 8);
2538
2539 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2540
2541 if (gdbarch_debug >= 1)
2542 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 2543 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2544 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2545 paddr_nz (bsp), next_frame);
968d1cb4
JJ		 2546}
2547
2548static void
2549ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2550 void **this_cache,
2551 int regnum, int *optimizedp,
2552 enum lval_type *lvalp, CORE_ADDR *addrp,
2553 int *realnump, void *valuep)
2554{
2555 int reg = regnum;
2556
2557 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2558 reg = IA64_PR_REGNUM;
2559 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2560 reg = IA64_UNAT_REGNUM;
2561
2562 /* Let libunwind do most of the work. */
2563 libunwind_frame_prev_register (next_frame, this_cache, reg,
2564 optimizedp, lvalp, addrp, realnump, valuep);
2565
6672f2ae
AS		 2566 /* No more to do if the value is not supposed to be supplied. */
2567 if (!valuep)
2568 return;
2569
968d1cb4
JJ		 2570 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2571 {
2572 ULONGEST prN_val;
2573
2574 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2575 {
2576 int rrb_pr = 0;
2577 ULONGEST cfm;
2578 unsigned char buf[MAX_REGISTER_SIZE];
2579
2580 /* Fetch predicate register rename base from current frame
2581 marker for this frame. */
2582 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2583 cfm = extract_unsigned_integer (buf, 8);
2584 rrb_pr = (cfm >> 32) & 0x3f;
2585
2586 /* Adjust the register number to account for register rotation. */
2587 regnum = VP16_REGNUM
2588 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2589 }
2590 prN_val = extract_bit_field ((unsigned char *) valuep,
2591 regnum - VP0_REGNUM, 1);
2592 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2593 }
2594 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2595 {
2596 ULONGEST unatN_val;
2597
2598 unatN_val = extract_bit_field ((unsigned char *) valuep,
2599 regnum - IA64_NAT0_REGNUM, 1);
2600 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2601 unatN_val);
2602 }
2603 else if (regnum == IA64_BSP_REGNUM)
2604 {
2605 char cfm_valuep[MAX_REGISTER_SIZE];
2606 int cfm_optim;
2607 int cfm_realnum;
2608 enum lval_type cfm_lval;
2609 CORE_ADDR cfm_addr;
2610 CORE_ADDR bsp, prev_cfm, prev_bsp;
2611
2612 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2613 This corresponds to what the hardware bsp register will be if we pop the frame
2614 back which is why we might have been called. We know that libunwind will pass us back
2615 the beginning of the current frame so we should just add sof to it. */
2616 prev_bsp = extract_unsigned_integer (valuep, 8);
2617 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2618 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2619 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2620 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2621
2622 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2623 prev_bsp);
2624 }
2625
2626 if (gdbarch_debug >= 1)
2627 fprintf_unfiltered (gdb_stdlog,
78ced177 2628 "libunwind prev register <%s> is 0x%s\n",
968d1cb4 2629 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2630 ? ia64_register_names[regnum] : "r??"),
2631 paddr_nz (extract_unsigned_integer (valuep, 8)));
968d1cb4
JJ		 2632}
2633
2634static const struct frame_unwind ia64_libunwind_frame_unwind =
2635{
2636 NORMAL_FRAME,
2637 ia64_libunwind_frame_this_id,
2638 ia64_libunwind_frame_prev_register
2639};
2640
2641static const struct frame_unwind *
2642ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2643{
2644 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2645 return &ia64_libunwind_frame_unwind;
2646
2647 return NULL;
2648}
2649
2650/* Set of libunwind callback acccessor functions. */
2651static unw_accessors_t ia64_unw_accessors =
2652{
2653 ia64_find_proc_info_x,
2654 ia64_put_unwind_info,
2655 ia64_get_dyn_info_list,
2656 ia64_access_mem,
2657 ia64_access_reg,
2658 ia64_access_fpreg,
2659 /* resume */
2660 /* get_proc_name */
2661};
2662
2663/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2664static struct libunwind_descr ia64_libunwind_descr =
2665{
2666 ia64_gdb2uw_regnum,
2667 ia64_uw2gdb_regnum,
2668 ia64_is_fpreg,
2669 &ia64_unw_accessors,
2670};
2671
2672#endif /* HAVE_LIBUNWIND_IA64_H */
2673
74055713
AC		 2674/* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2675 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2676 is the type (which is known to be struct, union or array). */
16461d7d
KB		 2677int
2678ia64_use_struct_convention (int gcc_p, struct type *type)
2679{
64a5b29c
KB		 2680 struct type *float_elt_type;
2681
2682 /* HFAs are structures (or arrays) consisting entirely of floating
2683 point values of the same length. Up to 8 of these are returned
2684 in registers. Don't use the struct convention when this is the
004d836a 2685 case. */
64a5b29c
KB		 2686 float_elt_type = is_float_or_hfa_type (type);
2687 if (float_elt_type != NULL
2688 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2689 return 0;
2690
2691 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 2692 Don't use the struct convention for those either. */
16461d7d
KB		 2693 return TYPE_LENGTH (type) > 32;
2694}
2695
2696void
004d836a 2697ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf)
16461d7d 2698{
64a5b29c
KB		 2699 struct type *float_elt_type;
2700
2701 float_elt_type = is_float_or_hfa_type (type);
2702 if (float_elt_type != NULL)
2703 {
004d836a 2704 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 2705 int offset = 0;
2706 int regnum = IA64_FR8_REGNUM;
2707 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2708
2709 while (n-- > 0)
2710 {
004d836a
JJ		 2711 regcache_cooked_read (regcache, regnum, from);
2712 convert_typed_floating (from, builtin_type_ia64_ext,
2713 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 2714 offset += TYPE_LENGTH (float_elt_type);
2715 regnum++;
2716 }
2717 }
16461d7d 2718 else
004d836a
JJ		 2719 {
2720 ULONGEST val;
2721 int offset = 0;
2722 int regnum = IA64_GR8_REGNUM;
2723 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
2724 int n = TYPE_LENGTH (type) / reglen;
2725 int m = TYPE_LENGTH (type) % reglen;
16461d7d 2726
004d836a
JJ		 2727 while (n-- > 0)
2728 {
2729 ULONGEST val;
2730 regcache_cooked_read_unsigned (regcache, regnum, &val);
2731 memcpy ((char *)valbuf + offset, &val, reglen);
2732 offset += reglen;
2733 regnum++;
2734 }
16461d7d 2735
004d836a
JJ		 2736 if (m)
2737 {
2738 regcache_cooked_read_unsigned (regcache, regnum, &val);
2739 memcpy ((char *)valbuf + offset, &val, m);
2740 }
2741 }
16461d7d
KB		 2742}
2743
2744CORE_ADDR
004d836a 2745ia64_extract_struct_value_address (struct regcache *regcache)
16461d7d 2746{
8a3fe4f8 2747 error (_("ia64_extract_struct_value_address called and cannot get struct value address"));
004d836a 2748 return 0;
16461d7d
KB		 2749}
2750
16461d7d 2751
64a5b29c
KB		 2752static int
2753is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
2754{
2755 switch (TYPE_CODE (t))
2756 {
2757 case TYPE_CODE_FLT:
2758 if (*etp)
2759 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
2760 else
2761 {
2762 *etp = t;
2763 return 1;
2764 }
2765 break;
2766 case TYPE_CODE_ARRAY:
98f96ba1
KB		 2767 return
2768 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
2769 etp);
64a5b29c
KB		 2770 break;
2771 case TYPE_CODE_STRUCT:
2772 {
2773 int i;
2774
2775 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 2776 if (!is_float_or_hfa_type_recurse
2777 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 2778 return 0;
2779 return 1;
2780 }
2781 break;
2782 default:
2783 return 0;
2784 break;
2785 }
2786}
2787
2788/* Determine if the given type is one of the floating point types or
2789 and HFA (which is a struct, array, or combination thereof whose
004d836a 2790 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 2791
2792static struct type *
2793is_float_or_hfa_type (struct type *t)
2794{
2795 struct type *et = 0;
2796
2797 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
2798}
2799
2800
98f96ba1
KB		 2801/* Return 1 if the alignment of T is such that the next even slot
2802 should be used. Return 0, if the next available slot should
2803 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 2804 and Runtime manual). */
98f96ba1
KB		 2805
2806static int
2807slot_alignment_is_next_even (struct type *t)
2808{
2809 switch (TYPE_CODE (t))
2810 {
2811 case TYPE_CODE_INT:
2812 case TYPE_CODE_FLT:
2813 if (TYPE_LENGTH (t) > 8)
2814 return 1;
2815 else
2816 return 0;
2817 case TYPE_CODE_ARRAY:
2818 return
2819 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
2820 case TYPE_CODE_STRUCT:
2821 {
2822 int i;
2823
2824 for (i = 0; i < TYPE_NFIELDS (t); i++)
2825 if (slot_alignment_is_next_even
2826 (check_typedef (TYPE_FIELD_TYPE (t, i))))
2827 return 1;
2828 return 0;
2829 }
2830 default:
2831 return 0;
2832 }
2833}
2834
64a5b29c
KB		 2835/* Attempt to find (and return) the global pointer for the given
2836 function.
2837
2838 This is a rather nasty bit of code searchs for the .dynamic section
2839 in the objfile corresponding to the pc of the function we're trying
2840 to call. Once it finds the addresses at which the .dynamic section
2841 lives in the child process, it scans the Elf64_Dyn entries for a
2842 DT_PLTGOT tag. If it finds one of these, the corresponding
2843 d_un.d_ptr value is the global pointer. */
2844
2845static CORE_ADDR
b33e8514 2846ia64_find_global_pointer (CORE_ADDR faddr)
64a5b29c 2847{
76d689a6 2848 struct obj_section *faddr_sect;
64a5b29c 2849
76d689a6
KB		 2850 faddr_sect = find_pc_section (faddr);
2851 if (faddr_sect != NULL)
64a5b29c
KB		 2852 {
2853 struct obj_section *osect;
2854
76d689a6 2855 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 2856 {
2857 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
2858 break;
2859 }
2860
76d689a6 2861 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 2862 {
2863 CORE_ADDR addr;
2864
2865 addr = osect->addr;
2866 while (addr < osect->endaddr)
2867 {
2868 int status;
2869 LONGEST tag;
2870 char buf[8];
2871
2872 status = target_read_memory (addr, buf, sizeof (buf));
2873 if (status != 0)
2874 break;
2875 tag = extract_signed_integer (buf, sizeof (buf));
2876
2877 if (tag == DT_PLTGOT)
2878 {
2879 CORE_ADDR global_pointer;
2880
2881 status = target_read_memory (addr + 8, buf, sizeof (buf));
2882 if (status != 0)
2883 break;
7c0b4a20 2884 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 2885
2886 /* The payoff... */
2887 return global_pointer;
2888 }
2889
2890 if (tag == DT_NULL)
2891 break;
2892
2893 addr += 16;
2894 }
2895 }
2896 }
2897 return 0;
2898}
2899
2900/* Given a function's address, attempt to find (and return) the
2901 corresponding (canonical) function descriptor. Return 0 if
004d836a 2902 not found. */
64a5b29c
KB		 2903static CORE_ADDR
2904find_extant_func_descr (CORE_ADDR faddr)
2905{
76d689a6 2906 struct obj_section *faddr_sect;
64a5b29c 2907
004d836a 2908 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 2909 faddr_sect = find_pc_section (faddr);
2910 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 2911 return faddr;
2912
76d689a6 2913 if (faddr_sect != NULL)
64a5b29c 2914 {
76d689a6
KB		 2915 struct obj_section *osect;
2916 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 2917 {
2918 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
2919 break;
2920 }
2921
76d689a6 2922 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 2923 {
2924 CORE_ADDR addr;
2925
2926 addr = osect->addr;
2927 while (addr < osect->endaddr)
2928 {
2929 int status;
2930 LONGEST faddr2;
2931 char buf[8];
2932
2933 status = target_read_memory (addr, buf, sizeof (buf));
2934 if (status != 0)
2935 break;
2936 faddr2 = extract_signed_integer (buf, sizeof (buf));
2937
2938 if (faddr == faddr2)
2939 return addr;
2940
2941 addr += 16;
2942 }
2943 }
2944 }
2945 return 0;
2946}
2947
2948/* Attempt to find a function descriptor corresponding to the
2949 given address. If none is found, construct one on the
004d836a 2950 stack using the address at fdaptr. */
64a5b29c
KB		 2951
2952static CORE_ADDR
2953find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
2954{
2955 CORE_ADDR fdesc;
2956
2957 fdesc = find_extant_func_descr (faddr);
2958
2959 if (fdesc == 0)
2960 {
2961 CORE_ADDR global_pointer;
2962 char buf[16];
2963
2964 fdesc = *fdaptr;
2965 *fdaptr += 16;
2966
b33e8514 2967 global_pointer = ia64_find_global_pointer (faddr);
64a5b29c
KB		 2968
2969 if (global_pointer == 0)
2970 global_pointer = read_register (IA64_GR1_REGNUM);
2971
fbd9dcd3
AC		 2972 store_unsigned_integer (buf, 8, faddr);
2973 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 2974
2975 write_memory (fdesc, buf, 16);
2976 }
2977
2978 return fdesc;
2979}
16461d7d 2980
af8b88dd
JJ		 2981/* Use the following routine when printing out function pointers
2982 so the user can see the function address rather than just the
2983 function descriptor. */
2984static CORE_ADDR
e2d0e7eb
AC		 2985ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
2986 struct target_ops *targ)
af8b88dd
JJ		 2987{
2988 struct obj_section *s;
2989
2990 s = find_pc_section (addr);
2991
2992 /* check if ADDR points to a function descriptor. */
2993 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
2994 return read_memory_unsigned_integer (addr, 8);
2995
2996 return addr;
2997}
2998
a78f21af 2999static CORE_ADDR
004d836a
JJ		 3000ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3001{
3002 return sp & ~0xfLL;
3003}
3004
3005static CORE_ADDR
7d9b040b 3006ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
8dd5115e
AS		 3007 struct regcache *regcache, CORE_ADDR bp_addr,
3008 int nargs, struct value **args, CORE_ADDR sp,
3009 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 3010{
3011 int argno;
ea7c478f 3012 struct value *arg;
16461d7d
KB		 3013 struct type *type;
3014 int len, argoffset;
64a5b29c 3015 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 3016 int floatreg;
004d836a 3017 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
7d9b040b 3018 CORE_ADDR func_addr = find_function_addr (function, NULL);
16461d7d
KB		 3019
3020 nslots = 0;
64a5b29c 3021 nfuncargs = 0;
004d836a 3022 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 3023 for (argno = 0; argno < nargs; argno++)
3024 {
3025 arg = args[argno];
4991999e 3026 type = check_typedef (value_type (arg));
16461d7d
KB		 3027 len = TYPE_LENGTH (type);
3028
98f96ba1 3029 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 3030 nslots++;
3031
64a5b29c
KB		 3032 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3033 nfuncargs++;
3034
16461d7d
KB		 3035 nslots += (len + 7) / 8;
3036 }
3037
004d836a 3038 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 3039 rseslots = (nslots > 8) ? 8 : nslots;
3040 memslots = nslots - rseslots;
3041
004d836a
JJ		 3042 /* Allocate a new RSE frame. */
3043 cfm = read_register (IA64_CFM_REGNUM);
16461d7d 3044
004d836a 3045 bsp = read_register (IA64_BSP_REGNUM);
16461d7d 3046 new_bsp = rse_address_add (bsp, rseslots);
004d836a 3047 write_register (IA64_BSP_REGNUM, new_bsp);
16461d7d 3048
004d836a 3049 pfs = read_register (IA64_PFS_REGNUM);
16461d7d
KB		 3050 pfs &= 0xc000000000000000LL;
3051 pfs |= (cfm & 0xffffffffffffLL);
004d836a 3052 write_register (IA64_PFS_REGNUM, pfs);
16461d7d
KB		 3053
3054 cfm &= 0xc000000000000000LL;
3055 cfm |= rseslots;
004d836a 3056 write_register (IA64_CFM_REGNUM, cfm);
16461d7d 3057
64a5b29c
KB		 3058 /* We will attempt to find function descriptors in the .opd segment,
3059 but if we can't we'll construct them ourselves. That being the
004d836a 3060 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 3061 funcdescaddr = sp - nfuncargs * 16;
3062 funcdescaddr &= ~0xfLL;
3063
3064 /* Adjust the stack pointer to it's new value. The calling conventions
3065 require us to have 16 bytes of scratch, plus whatever space is
004d836a 3066 necessary for the memory slots and our function descriptors. */
64a5b29c 3067 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 3068 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 3069
64a5b29c
KB		 3070 /* Place the arguments where they belong. The arguments will be
3071 either placed in the RSE backing store or on the memory stack.
3072 In addition, floating point arguments or HFAs are placed in
004d836a 3073 floating point registers. */
16461d7d
KB		 3074 slotnum = 0;
3075 floatreg = IA64_FR8_REGNUM;
3076 for (argno = 0; argno < nargs; argno++)
3077 {
64a5b29c
KB		 3078 struct type *float_elt_type;
3079
16461d7d 3080 arg = args[argno];
4991999e 3081 type = check_typedef (value_type (arg));
16461d7d 3082 len = TYPE_LENGTH (type);
64a5b29c 3083
004d836a 3084 /* Special handling for function parameters. */
64a5b29c
KB		 3085 if (len == 8
3086 && TYPE_CODE (type) == TYPE_CODE_PTR
3087 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3088 {
3089 char val_buf[8];
3090
fbd9dcd3 3091 store_unsigned_integer (val_buf, 8,
0fd88904 3092 find_func_descr (extract_unsigned_integer (value_contents (arg), 8),
fbd9dcd3 3093 &funcdescaddr));
64a5b29c
KB		 3094 if (slotnum < rseslots)
3095 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3096 else
3097 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3098 slotnum++;
3099 continue;
3100 }
3101
004d836a 3102 /* Normal slots. */
98f96ba1
KB		 3103
3104 /* Skip odd slot if necessary... */
3105 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 3106 slotnum++;
98f96ba1 3107
16461d7d
KB		 3108 argoffset = 0;
3109 while (len > 0)
3110 {
3111 char val_buf[8];
3112
3113 memset (val_buf, 0, 8);
0fd88904 3114 memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
16461d7d
KB		 3115
3116 if (slotnum < rseslots)
3117 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3118 else
3119 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3120
3121 argoffset += 8;
3122 len -= 8;
3123 slotnum++;
3124 }
64a5b29c 3125
004d836a 3126 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 3127 float_elt_type = is_float_or_hfa_type (type);
3128 if (float_elt_type != NULL)
3129 {
3130 argoffset = 0;
3131 len = TYPE_LENGTH (type);
3132 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3133 {
004d836a 3134 char to[MAX_REGISTER_SIZE];
0fd88904 3135 convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
004d836a
JJ		 3136 to, builtin_type_ia64_ext);
3137 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 3138 floatreg++;
3139 argoffset += TYPE_LENGTH (float_elt_type);
3140 len -= TYPE_LENGTH (float_elt_type);
3141 }
16461d7d
KB		 3142 }
3143 }
3144
004d836a 3145 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 3146 if (struct_return)
3147 {
004d836a 3148 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 3149 }
3150
b33e8514 3151 global_pointer = ia64_find_global_pointer (func_addr);
8dd5115e 3152
004d836a
JJ		 3153 if (global_pointer != 0)
3154 write_register (IA64_GR1_REGNUM, global_pointer);
a59fe496 3155
004d836a 3156 write_register (IA64_BR0_REGNUM, bp_addr);
16461d7d 3157
004d836a 3158 write_register (sp_regnum, sp);
16461d7d
KB		 3159
3160 return sp;
3161}
3162
004d836a
JJ		 3163static struct frame_id
3164ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3165{
004d836a 3166 char buf[8];
4afcc598 3167 CORE_ADDR sp, bsp;
004d836a
JJ		 3168
3169 frame_unwind_register (next_frame, sp_regnum, buf);
3170 sp = extract_unsigned_integer (buf, 8);
3171
4afcc598
JJ		 3172 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3173 bsp = extract_unsigned_integer (buf, 8);
3174
3175 if (gdbarch_debug >= 1)
3176 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 3177 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3178 paddr_nz (frame_pc_unwind (next_frame)),
3179 paddr_nz (sp), paddr_nz (bsp));
4afcc598
JJ		 3180
3181 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 3182}
3183
004d836a
JJ		 3184static CORE_ADDR
3185ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3186{
004d836a
JJ		 3187 char buf[8];
3188 CORE_ADDR ip, psr, pc;
3189
3190 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3191 ip = extract_unsigned_integer (buf, 8);
3192 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3193 psr = extract_unsigned_integer (buf, 8);
3194
3195 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3196 return pc;
16461d7d
KB		 3197}
3198
3199static void
004d836a 3200ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf)
16461d7d 3201{
004d836a 3202 if (TYPE_CODE (type) == TYPE_CODE_FLT)
16461d7d 3203 {
004d836a
JJ		 3204 char to[MAX_REGISTER_SIZE];
3205 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3206 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3207 target_store_registers (IA64_FR8_REGNUM);
16461d7d
KB		 3208 }
3209 else
004d836a 3210 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
16461d7d
KB		 3211}
3212
3213static void
1750fa04
AC		 3214ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3215 struct regcache *regcache,
3216 CORE_ADDR memaddr, int nr_bytes,
16461d7d
KB		 3217 CORE_ADDR *targ_addr, int *targ_len)
3218{
3219 *targ_addr = memaddr;
3220 *targ_len = nr_bytes;
3221}
3222
6926787d
AS		 3223static int
3224ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3225{
3226 info->bytes_per_line = SLOT_MULTIPLIER;
3227 return print_insn_ia64 (memaddr, info);
3228}
3229
16461d7d
KB		 3230static struct gdbarch *
3231ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3232{
3233 struct gdbarch *gdbarch;
244bc108 3234 struct gdbarch_tdep *tdep;
244bc108 3235
85bf2b91
JJ		 3236 /* If there is already a candidate, use it. */
3237 arches = gdbarch_list_lookup_by_info (arches, &info);
3238 if (arches != NULL)
3239 return arches->gdbarch;
16461d7d 3240
244bc108
KB		 3241 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3242 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 3243
b33e8514 3244 tdep->sigcontext_register_address = 0;
698cb3f0 3245
004d836a
JJ		 3246 /* Define the ia64 floating-point format to gdb. */
3247 builtin_type_ia64_ext =
3248 init_type (TYPE_CODE_FLT, 128 / 8,
3249 0, "builtin_type_ia64_ext", NULL);
3250 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
3251
5439edaa
AC		 3252 /* According to the ia64 specs, instructions that store long double
3253 floats in memory use a long-double format different than that
3254 used in the floating registers. The memory format matches the
3255 x86 extended float format which is 80 bits. An OS may choose to
3256 use this format (e.g. GNU/Linux) or choose to use a different
3257 format for storing long doubles (e.g. HPUX). In the latter case,
3258 the setting of the format may be moved/overridden in an
3259 OS-specific tdep file. */
32edc941
JJ		 3260 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext);
3261
16461d7d
KB		 3262 set_gdbarch_short_bit (gdbarch, 16);
3263 set_gdbarch_int_bit (gdbarch, 32);
3264 set_gdbarch_long_bit (gdbarch, 64);
3265 set_gdbarch_long_long_bit (gdbarch, 64);
3266 set_gdbarch_float_bit (gdbarch, 32);
3267 set_gdbarch_double_bit (gdbarch, 64);
33c08150 3268 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 3269 set_gdbarch_ptr_bit (gdbarch, 64);
3270
004d836a
JJ		 3271 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3272 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 3273 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 3274 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 3275
3276 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a
JJ		 3277 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3278 gets a number of extra failures. */
b1e29e33 3279 set_gdbarch_deprecated_register_size (gdbarch, 8);
004d836a 3280 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 3281
004d836a
JJ		 3282 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3283 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3284 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3285 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3286 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3287 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3288 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 3289
004d836a 3290 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d 3291
b5622e8d 3292 set_gdbarch_deprecated_use_struct_convention (gdbarch, ia64_use_struct_convention);
004d836a 3293 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
16461d7d 3294
004d836a 3295 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
74055713 3296 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
16461d7d
KB		 3297
3298 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3299 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3300 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3301 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
b33e8514 3302 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
16461d7d
KB		 3303
3304 /* Settings for calling functions in the inferior. */
8dd5115e 3305 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 3306 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3307 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 3308
004d836a
JJ		 3309 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
3310 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
968d1cb4
JJ		 3311#ifdef HAVE_LIBUNWIND_IA64_H
3312 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3313 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
3314#endif
004d836a
JJ		 3315 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3316 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 3317
3318 /* Settings that should be unnecessary. */
3319 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3320
16461d7d
KB		 3321 set_gdbarch_remote_translate_xfer_address (
3322 gdbarch, ia64_remote_translate_xfer_address);
3323
6926787d 3324 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 3325 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 3326
b33e8514
AS		 3327 /* Hook in ABI-specific overrides, if they have been registered. */
3328 gdbarch_init_osabi (info, gdbarch);
3329
16461d7d
KB		 3330 return gdbarch;
3331}
3332
a78f21af
AC		 3333extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3334
16461d7d
KB		 3335void
3336_initialize_ia64_tdep (void)
3337{
b33e8514 3338 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
16461d7d 3339}
GDB Binutils - Deliverables
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