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c28c63d8 JB |
1 | /* Target-dependent code for Lattice Mico32 processor, for GDB. |
2 | Contributed by Jon Beniston <jon@beniston.com> | |
3 | ||
3666a048 | 4 | Copyright (C) 2009-2021 Free Software Foundation, Inc. |
c28c63d8 JB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | #include "frame.h" | |
23 | #include "frame-unwind.h" | |
24 | #include "frame-base.h" | |
25 | #include "inferior.h" | |
26 | #include "dis-asm.h" | |
27 | #include "symfile.h" | |
28 | #include "remote.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdb/sim-lm32.h" | |
c28c63d8 JB |
31 | #include "arch-utils.h" |
32 | #include "regcache.h" | |
33 | #include "trad-frame.h" | |
34 | #include "reggroups.h" | |
f16f7b7c | 35 | #include "opcodes/lm32-desc.h" |
325fac50 | 36 | #include <algorithm> |
c28c63d8 | 37 | |
c28c63d8 JB |
38 | /* Macros to extract fields from an instruction. */ |
39 | #define LM32_OPCODE(insn) ((insn >> 26) & 0x3f) | |
40 | #define LM32_REG0(insn) ((insn >> 21) & 0x1f) | |
41 | #define LM32_REG1(insn) ((insn >> 16) & 0x1f) | |
42 | #define LM32_REG2(insn) ((insn >> 11) & 0x1f) | |
43 | #define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16) | |
44 | ||
45 | struct gdbarch_tdep | |
46 | { | |
1777feb0 | 47 | /* gdbarch target dependent data here. Currently unused for LM32. */ |
c28c63d8 JB |
48 | }; |
49 | ||
50 | struct lm32_frame_cache | |
51 | { | |
52 | /* The frame's base. Used when constructing a frame ID. */ | |
53 | CORE_ADDR base; | |
54 | CORE_ADDR pc; | |
55 | /* Size of frame. */ | |
56 | int size; | |
57 | /* Table indicating the location of each and every register. */ | |
098caef4 | 58 | trad_frame_saved_reg *saved_regs; |
c28c63d8 JB |
59 | }; |
60 | ||
61 | /* Add the available register groups. */ | |
62 | ||
63 | static void | |
64 | lm32_add_reggroups (struct gdbarch *gdbarch) | |
65 | { | |
66 | reggroup_add (gdbarch, general_reggroup); | |
67 | reggroup_add (gdbarch, all_reggroup); | |
68 | reggroup_add (gdbarch, system_reggroup); | |
69 | } | |
70 | ||
71 | /* Return whether a given register is in a given group. */ | |
72 | ||
73 | static int | |
74 | lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
75 | struct reggroup *group) | |
76 | { | |
77 | if (group == general_reggroup) | |
78 | return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM)) | |
79 | || (regnum == SIM_LM32_PC_REGNUM); | |
80 | else if (group == system_reggroup) | |
aa370940 | 81 | return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM)) |
c28c63d8 JB |
82 | || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM)); |
83 | return default_register_reggroup_p (gdbarch, regnum, group); | |
84 | } | |
85 | ||
86 | /* Return a name that corresponds to the given register number. */ | |
87 | ||
88 | static const char * | |
89 | lm32_register_name (struct gdbarch *gdbarch, int reg_nr) | |
90 | { | |
a121b7c1 | 91 | static const char *register_names[] = { |
c28c63d8 JB |
92 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
93 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
94 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
95 | "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba", | |
96 | "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP" | |
97 | }; | |
98 | ||
99 | if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names))) | |
100 | return NULL; | |
101 | else | |
102 | return register_names[reg_nr]; | |
103 | } | |
104 | ||
105 | /* Return type of register. */ | |
106 | ||
107 | static struct type * | |
108 | lm32_register_type (struct gdbarch *gdbarch, int reg_nr) | |
109 | { | |
df4df182 | 110 | return builtin_type (gdbarch)->builtin_int32; |
c28c63d8 JB |
111 | } |
112 | ||
113 | /* Return non-zero if a register can't be written. */ | |
114 | ||
115 | static int | |
116 | lm32_cannot_store_register (struct gdbarch *gdbarch, int regno) | |
117 | { | |
118 | return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM); | |
119 | } | |
120 | ||
121 | /* Analyze a function's prologue. */ | |
122 | ||
123 | static CORE_ADDR | |
e17a4113 UW |
124 | lm32_analyze_prologue (struct gdbarch *gdbarch, |
125 | CORE_ADDR pc, CORE_ADDR limit, | |
c28c63d8 JB |
126 | struct lm32_frame_cache *info) |
127 | { | |
e17a4113 | 128 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c28c63d8 JB |
129 | unsigned long instruction; |
130 | ||
131 | /* Keep reading though instructions, until we come across an instruction | |
132 | that isn't likely to be part of the prologue. */ | |
133 | info->size = 0; | |
134 | for (; pc < limit; pc += 4) | |
135 | { | |
136 | ||
137 | /* Read an instruction. */ | |
e17a4113 | 138 | instruction = read_memory_integer (pc, 4, byte_order); |
c28c63d8 JB |
139 | |
140 | if ((LM32_OPCODE (instruction) == OP_SW) | |
141 | && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM)) | |
142 | { | |
1777feb0 | 143 | /* Any stack displaced store is likely part of the prologue. |
c28c63d8 JB |
144 | Record that the register is being saved, and the offset |
145 | into the stack. */ | |
098caef4 | 146 | info->saved_regs[LM32_REG1 (instruction)].set_addr (LM32_IMM16 (instruction)); |
c28c63d8 JB |
147 | } |
148 | else if ((LM32_OPCODE (instruction) == OP_ADDI) | |
149 | && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM)) | |
150 | { | |
1777feb0 | 151 | /* An add to the SP is likely to be part of the prologue. |
c28c63d8 JB |
152 | Adjust stack size by whatever the instruction adds to the sp. */ |
153 | info->size -= LM32_IMM16 (instruction); | |
154 | } | |
155 | else if ( /* add fp,fp,sp */ | |
156 | ((LM32_OPCODE (instruction) == OP_ADD) | |
157 | && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM) | |
158 | && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM) | |
159 | && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM)) | |
160 | /* mv fp,imm */ | |
161 | || ((LM32_OPCODE (instruction) == OP_ADDI) | |
162 | && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM) | |
163 | && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM))) | |
164 | { | |
165 | /* Likely to be in the prologue for functions that require | |
166 | a frame pointer. */ | |
167 | } | |
168 | else | |
169 | { | |
1777feb0 MS |
170 | /* Any other instruction is likely not to be part of the |
171 | prologue. */ | |
c28c63d8 JB |
172 | break; |
173 | } | |
174 | } | |
175 | ||
176 | return pc; | |
177 | } | |
178 | ||
179 | /* Return PC of first non prologue instruction, for the function at the | |
180 | specified address. */ | |
181 | ||
182 | static CORE_ADDR | |
183 | lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
184 | { | |
185 | CORE_ADDR func_addr, limit_pc; | |
c28c63d8 | 186 | struct lm32_frame_cache frame_info; |
098caef4 | 187 | trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS]; |
c28c63d8 JB |
188 | |
189 | /* See if we can determine the end of the prologue via the symbol table. | |
190 | If so, then return either PC, or the PC after the prologue, whichever | |
191 | is greater. */ | |
192 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
193 | { | |
d80b854b UW |
194 | CORE_ADDR post_prologue_pc |
195 | = skip_prologue_using_sal (gdbarch, func_addr); | |
c28c63d8 | 196 | if (post_prologue_pc != 0) |
325fac50 | 197 | return std::max (pc, post_prologue_pc); |
c28c63d8 JB |
198 | } |
199 | ||
200 | /* Can't determine prologue from the symbol table, need to examine | |
201 | instructions. */ | |
202 | ||
203 | /* Find an upper limit on the function prologue using the debug | |
204 | information. If the debug information could not be used to provide | |
205 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 206 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
c28c63d8 JB |
207 | if (limit_pc == 0) |
208 | limit_pc = pc + 100; /* Magic. */ | |
209 | ||
210 | frame_info.saved_regs = saved_regs; | |
e17a4113 | 211 | return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info); |
c28c63d8 JB |
212 | } |
213 | ||
214 | /* Create a breakpoint instruction. */ | |
04180708 | 215 | constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 }; |
c28c63d8 | 216 | |
04180708 | 217 | typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint; |
c28c63d8 | 218 | |
c28c63d8 JB |
219 | |
220 | /* Setup registers and stack for faking a call to a function in the | |
221 | inferior. */ | |
222 | ||
223 | static CORE_ADDR | |
224 | lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
225 | struct regcache *regcache, CORE_ADDR bp_addr, | |
226 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
227 | function_call_return_method return_method, |
228 | CORE_ADDR struct_addr) | |
c28c63d8 | 229 | { |
e17a4113 | 230 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c28c63d8 JB |
231 | int first_arg_reg = SIM_LM32_R1_REGNUM; |
232 | int num_arg_regs = 8; | |
233 | int i; | |
234 | ||
235 | /* Set the return address. */ | |
236 | regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr); | |
237 | ||
238 | /* If we're returning a large struct, a pointer to the address to | |
239 | store it at is passed as a first hidden parameter. */ | |
cf84fa6b | 240 | if (return_method == return_method_struct) |
c28c63d8 JB |
241 | { |
242 | regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr); | |
243 | first_arg_reg++; | |
244 | num_arg_regs--; | |
245 | sp -= 4; | |
246 | } | |
247 | ||
248 | /* Setup parameters. */ | |
249 | for (i = 0; i < nargs; i++) | |
250 | { | |
251 | struct value *arg = args[i]; | |
252 | struct type *arg_type = check_typedef (value_type (arg)); | |
253 | gdb_byte *contents; | |
c28c63d8 JB |
254 | ULONGEST val; |
255 | ||
256 | /* Promote small integer types to int. */ | |
78134374 | 257 | switch (arg_type->code ()) |
c28c63d8 JB |
258 | { |
259 | case TYPE_CODE_INT: | |
260 | case TYPE_CODE_BOOL: | |
261 | case TYPE_CODE_CHAR: | |
262 | case TYPE_CODE_RANGE: | |
263 | case TYPE_CODE_ENUM: | |
264 | if (TYPE_LENGTH (arg_type) < 4) | |
265 | { | |
df4df182 | 266 | arg_type = builtin_type (gdbarch)->builtin_int32; |
c28c63d8 JB |
267 | arg = value_cast (arg_type, arg); |
268 | } | |
269 | break; | |
270 | } | |
271 | ||
272 | /* FIXME: Handle structures. */ | |
273 | ||
274 | contents = (gdb_byte *) value_contents (arg); | |
744a8059 SP |
275 | val = extract_unsigned_integer (contents, TYPE_LENGTH (arg_type), |
276 | byte_order); | |
c28c63d8 JB |
277 | |
278 | /* First num_arg_regs parameters are passed by registers, | |
dda83cd7 | 279 | and the rest are passed on the stack. */ |
c28c63d8 JB |
280 | if (i < num_arg_regs) |
281 | regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val); | |
282 | else | |
283 | { | |
4666fec3 SM |
284 | write_memory_unsigned_integer (sp, TYPE_LENGTH (arg_type), byte_order, |
285 | val); | |
c28c63d8 JB |
286 | sp -= 4; |
287 | } | |
288 | } | |
289 | ||
290 | /* Update stack pointer. */ | |
291 | regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp); | |
292 | ||
293 | /* Return adjusted stack pointer. */ | |
294 | return sp; | |
295 | } | |
296 | ||
297 | /* Extract return value after calling a function in the inferior. */ | |
298 | ||
299 | static void | |
300 | lm32_extract_return_value (struct type *type, struct regcache *regcache, | |
301 | gdb_byte *valbuf) | |
302 | { | |
ac7936df | 303 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 304 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c28c63d8 JB |
305 | ULONGEST l; |
306 | CORE_ADDR return_buffer; | |
307 | ||
78134374 SM |
308 | if (type->code () != TYPE_CODE_STRUCT |
309 | && type->code () != TYPE_CODE_UNION | |
310 | && type->code () != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4) | |
c28c63d8 JB |
311 | { |
312 | /* Return value is returned in a single register. */ | |
313 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); | |
e17a4113 | 314 | store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l); |
c28c63d8 | 315 | } |
78134374 | 316 | else if ((type->code () == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8)) |
c28c63d8 JB |
317 | { |
318 | /* 64-bit values are returned in a register pair. */ | |
319 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); | |
320 | memcpy (valbuf, &l, 4); | |
321 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l); | |
322 | memcpy (valbuf + 4, &l, 4); | |
323 | } | |
324 | else | |
325 | { | |
1777feb0 | 326 | /* Aggregate types greater than a single register are returned |
dda83cd7 | 327 | in memory. FIXME: Unless they are only 2 regs?. */ |
c28c63d8 JB |
328 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); |
329 | return_buffer = l; | |
330 | read_memory (return_buffer, valbuf, TYPE_LENGTH (type)); | |
331 | } | |
332 | } | |
333 | ||
334 | /* Write into appropriate registers a function return value of type | |
335 | TYPE, given in virtual format. */ | |
336 | static void | |
337 | lm32_store_return_value (struct type *type, struct regcache *regcache, | |
338 | const gdb_byte *valbuf) | |
339 | { | |
ac7936df | 340 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 341 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c28c63d8 | 342 | ULONGEST val; |
bad43aa5 | 343 | int len = TYPE_LENGTH (type); |
c28c63d8 | 344 | |
bad43aa5 | 345 | if (len <= 4) |
c28c63d8 | 346 | { |
bad43aa5 | 347 | val = extract_unsigned_integer (valbuf, len, byte_order); |
c28c63d8 JB |
348 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val); |
349 | } | |
bad43aa5 | 350 | else if (len <= 8) |
c28c63d8 | 351 | { |
e17a4113 | 352 | val = extract_unsigned_integer (valbuf, 4, byte_order); |
c28c63d8 | 353 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val); |
bad43aa5 | 354 | val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order); |
c28c63d8 JB |
355 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val); |
356 | } | |
357 | else | |
358 | error (_("lm32_store_return_value: type length too large.")); | |
359 | } | |
360 | ||
361 | /* Determine whether a functions return value is in a register or memory. */ | |
362 | static enum return_value_convention | |
6a3a010b | 363 | lm32_return_value (struct gdbarch *gdbarch, struct value *function, |
c28c63d8 JB |
364 | struct type *valtype, struct regcache *regcache, |
365 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
366 | { | |
78134374 | 367 | enum type_code code = valtype->code (); |
c28c63d8 JB |
368 | |
369 | if (code == TYPE_CODE_STRUCT | |
370 | || code == TYPE_CODE_UNION | |
371 | || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8) | |
372 | return RETURN_VALUE_STRUCT_CONVENTION; | |
373 | ||
374 | if (readbuf) | |
375 | lm32_extract_return_value (valtype, regcache, readbuf); | |
376 | if (writebuf) | |
377 | lm32_store_return_value (valtype, regcache, writebuf); | |
378 | ||
379 | return RETURN_VALUE_REGISTER_CONVENTION; | |
380 | } | |
381 | ||
c28c63d8 JB |
382 | /* Put here the code to store, into fi->saved_regs, the addresses of |
383 | the saved registers of frame described by FRAME_INFO. This | |
384 | includes special registers such as pc and fp saved in special ways | |
385 | in the stack frame. sp is even more special: the address we return | |
386 | for it IS the sp for the next frame. */ | |
387 | ||
388 | static struct lm32_frame_cache * | |
389 | lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache) | |
390 | { | |
c28c63d8 JB |
391 | CORE_ADDR current_pc; |
392 | ULONGEST prev_sp; | |
393 | ULONGEST this_base; | |
394 | struct lm32_frame_cache *info; | |
c28c63d8 | 395 | int i; |
c28c63d8 JB |
396 | |
397 | if ((*this_prologue_cache)) | |
9a3c8263 | 398 | return (struct lm32_frame_cache *) (*this_prologue_cache); |
c28c63d8 JB |
399 | |
400 | info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache); | |
401 | (*this_prologue_cache) = info; | |
402 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
403 | ||
404 | info->pc = get_frame_func (this_frame); | |
405 | current_pc = get_frame_pc (this_frame); | |
e17a4113 UW |
406 | lm32_analyze_prologue (get_frame_arch (this_frame), |
407 | info->pc, current_pc, info); | |
c28c63d8 JB |
408 | |
409 | /* Compute the frame's base, and the previous frame's SP. */ | |
410 | this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM); | |
411 | prev_sp = this_base + info->size; | |
412 | info->base = this_base; | |
413 | ||
414 | /* Convert callee save offsets into addresses. */ | |
415 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) | |
416 | { | |
a9a87d35 | 417 | if (info->saved_regs[i].is_addr ()) |
098caef4 | 418 | info->saved_regs[i].set_addr (this_base + info->saved_regs[i].addr ()); |
c28c63d8 JB |
419 | } |
420 | ||
421 | /* The call instruction moves the caller's PC in the callee's RA register. | |
422 | Since this is an unwind, do the reverse. Copy the location of RA register | |
423 | into PC (the address / regnum) so that a request for PC will be | |
424 | converted into a request for the RA register. */ | |
425 | info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM]; | |
426 | ||
1777feb0 MS |
427 | /* The previous frame's SP needed to be computed. Save the computed |
428 | value. */ | |
a9a87d35 | 429 | info->saved_regs[SIM_LM32_SP_REGNUM].set_value (prev_sp); |
c28c63d8 JB |
430 | |
431 | return info; | |
432 | } | |
433 | ||
434 | static void | |
435 | lm32_frame_this_id (struct frame_info *this_frame, void **this_cache, | |
436 | struct frame_id *this_id) | |
437 | { | |
438 | struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache); | |
439 | ||
440 | /* This marks the outermost frame. */ | |
441 | if (cache->base == 0) | |
442 | return; | |
443 | ||
444 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
445 | } | |
446 | ||
447 | static struct value * | |
448 | lm32_frame_prev_register (struct frame_info *this_frame, | |
449 | void **this_prologue_cache, int regnum) | |
450 | { | |
451 | struct lm32_frame_cache *info; | |
452 | ||
453 | info = lm32_frame_cache (this_frame, this_prologue_cache); | |
454 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
455 | } | |
456 | ||
457 | static const struct frame_unwind lm32_frame_unwind = { | |
a154d838 | 458 | "lm32 prologue", |
c28c63d8 | 459 | NORMAL_FRAME, |
8fbca658 | 460 | default_frame_unwind_stop_reason, |
c28c63d8 JB |
461 | lm32_frame_this_id, |
462 | lm32_frame_prev_register, | |
463 | NULL, | |
464 | default_frame_sniffer | |
465 | }; | |
466 | ||
467 | static CORE_ADDR | |
468 | lm32_frame_base_address (struct frame_info *this_frame, void **this_cache) | |
469 | { | |
470 | struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache); | |
471 | ||
472 | return info->base; | |
473 | } | |
474 | ||
475 | static const struct frame_base lm32_frame_base = { | |
476 | &lm32_frame_unwind, | |
477 | lm32_frame_base_address, | |
478 | lm32_frame_base_address, | |
479 | lm32_frame_base_address | |
480 | }; | |
481 | ||
482 | static CORE_ADDR | |
483 | lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
484 | { | |
485 | /* Align to the size of an instruction (so that they can safely be | |
486 | pushed onto the stack. */ | |
487 | return sp & ~3; | |
488 | } | |
489 | ||
490 | static struct gdbarch * | |
491 | lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
492 | { | |
493 | struct gdbarch *gdbarch; | |
494 | struct gdbarch_tdep *tdep; | |
495 | ||
496 | /* If there is already a candidate, use it. */ | |
497 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
498 | if (arches != NULL) | |
499 | return arches->gdbarch; | |
500 | ||
501 | /* None found, create a new architecture from the information provided. */ | |
cdd238da | 502 | tdep = XCNEW (struct gdbarch_tdep); |
c28c63d8 JB |
503 | gdbarch = gdbarch_alloc (&info, tdep); |
504 | ||
505 | /* Type sizes. */ | |
506 | set_gdbarch_short_bit (gdbarch, 16); | |
507 | set_gdbarch_int_bit (gdbarch, 32); | |
508 | set_gdbarch_long_bit (gdbarch, 32); | |
509 | set_gdbarch_long_long_bit (gdbarch, 64); | |
510 | set_gdbarch_float_bit (gdbarch, 32); | |
511 | set_gdbarch_double_bit (gdbarch, 64); | |
512 | set_gdbarch_long_double_bit (gdbarch, 64); | |
513 | set_gdbarch_ptr_bit (gdbarch, 32); | |
514 | ||
515 | /* Register info. */ | |
516 | set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS); | |
517 | set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM); | |
518 | set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM); | |
519 | set_gdbarch_register_name (gdbarch, lm32_register_name); | |
520 | set_gdbarch_register_type (gdbarch, lm32_register_type); | |
521 | set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register); | |
522 | ||
523 | /* Frame info. */ | |
524 | set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue); | |
525 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
526 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
527 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
528 | ||
529 | /* Frame unwinding. */ | |
530 | set_gdbarch_frame_align (gdbarch, lm32_frame_align); | |
531 | frame_base_set_default (gdbarch, &lm32_frame_base); | |
c28c63d8 JB |
532 | frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind); |
533 | ||
534 | /* Breakpoints. */ | |
04180708 YQ |
535 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc); |
536 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind); | |
c28c63d8 JB |
537 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
538 | ||
539 | /* Calling functions in the inferior. */ | |
540 | set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call); | |
541 | set_gdbarch_return_value (gdbarch, lm32_return_value); | |
542 | ||
c28c63d8 JB |
543 | lm32_add_reggroups (gdbarch); |
544 | set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p); | |
545 | ||
546 | return gdbarch; | |
547 | } | |
548 | ||
6c265988 | 549 | void _initialize_lm32_tdep (); |
c28c63d8 | 550 | void |
6c265988 | 551 | _initialize_lm32_tdep () |
c28c63d8 JB |
552 | { |
553 | register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init); | |
554 | } |