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[deliverable/binutils-gdb.git] / gdb / mips-linux-tdep.c
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75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
0b302171 3 Copyright (C) 2001-2002, 2004-2012 Free Software Foundation, Inc.
2aa830e4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ		 19
20#include "defs.h"
21#include "gdbcore.h"
22#include "target.h"
23#include "solib-svr4.h"
19ed69dd 24#include "osabi.h"
96f026fc 25#include "mips-tdep.h"
19ed69dd 26#include "gdb_string.h"
96f026fc 27#include "gdb_assert.h"
6de918a6 28#include "frame.h"
2fdf551c 29#include "regcache.h"
5792a79b
DJ		 30#include "trad-frame.h"
31#include "tramp-frame.h"
e6bb342a 32#include "gdbtypes.h"
5ea03926 33#include "solib.h"
7d522c90
DJ		 34#include "solib-svr4.h"
35#include "solist.h"
982e9687 36#include "symtab.h"
822b6570 37#include "target-descriptions.h"
50e8a0d5 38#include "regset.h"
d37eb719 39#include "mips-linux-tdep.h"
db5f024e 40#include "glibc-tdep.h"
a5ee0f0c 41#include "linux-tdep.h"
385203ed 42#include "xml-syscall.h"
232b8704 43#include "gdb_signals.h"
2aa830e4 44
7d522c90
DJ		 45static struct target_so_ops mips_svr4_so_ops;
46
2aa830e4 47/* Figure out where the longjmp will land.
295093a4
MS		 48 We expect the first arg to be a pointer to the jmp_buf structure
49 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
50 at. The pc is copied into PC. This routine returns 1 on
51 success. */
2aa830e4 52
19ed69dd
KB		 53#define MIPS_LINUX_JB_ELEMENT_SIZE 4
54#define MIPS_LINUX_JB_PC 0
55
56static int
60ade65d 57mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2aa830e4
DJ		 58{
59 CORE_ADDR jb_addr;
2eb4d78b 60 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 61 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2eb4d78b 62 char buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
2aa830e4 63
60ade65d 64 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
2aa830e4 65
bf072999 66 if (target_read_memory (jb_addr
819844ad 67 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
2eb4d78b 68 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
2aa830e4
DJ		 69 return 0;
70
819844ad 71 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 72 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
73 byte_order);
2aa830e4
DJ		 74
75 return 1;
76}
77
4246e332 78/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 79 for regcache_raw_supply(). This is needed when mips_isa_regsize()
80 is 8. */
96f026fc
KB		 81
82static void
28f5035f 83supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
96f026fc 84{
e17a4113
UW		 85 struct gdbarch *gdbarch = get_regcache_arch (regcache);
86 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d37eb719 87 gdb_byte buf[MAX_REGISTER_SIZE];
e17a4113
UW		 88 store_signed_integer (buf, register_size (gdbarch, regnum), byte_order,
89 extract_signed_integer (addr, 4, byte_order));
28f5035f 90 regcache_raw_supply (regcache, regnum, buf);
96f026fc
KB		 91}
92
2aa830e4
DJ		 93/* Unpack an elf_gregset_t into GDB's register cache. */
94
d37eb719 95void
28f5035f
UW		 96mips_supply_gregset (struct regcache *regcache,
97 const mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 98{
99 int regi;
28f5035f 100 const mips_elf_greg_t *regp = *gregsetp;
d9d9c31f 101 char zerobuf[MAX_REGISTER_SIZE];
2eb4d78b 102 struct gdbarch *gdbarch = get_regcache_arch (regcache);
bf072999 103
d9d9c31f 104 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4 105
822b6570 106 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++)
28f5035f 107 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
2aa830e4 108
2eb4d78b 109 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 110 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0);
111
2eb4d78b
UW		 112 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO);
113 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI);
56cea623 114
2eb4d78b 115 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 116 regp + EF_CP0_EPC);
2eb4d78b 117 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 118 regp + EF_CP0_BADVADDR);
119 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
2eb4d78b 120 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 121 regp + EF_CP0_CAUSE);
2aa830e4 122
1faeff08 123 /* Fill the inaccessible zero register with zero. */
822b6570 124 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
2aa830e4
DJ		 125}
126
50e8a0d5
HZ		 127static void
128mips_supply_gregset_wrapper (const struct regset *regset,
129 struct regcache *regcache,
130 int regnum, const void *gregs, size_t len)
131{
132 gdb_assert (len == sizeof (mips_elf_gregset_t));
133
134 mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs);
135}
136
2aa830e4
DJ		 137/* Pack our registers (or one register) into an elf_gregset_t. */
138
d37eb719 139void
28f5035f
UW		 140mips_fill_gregset (const struct regcache *regcache,
141 mips_elf_gregset_t *gregsetp, int regno)
2aa830e4 142{
2eb4d78b 143 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2aa830e4 144 int regaddr, regi;
d37eb719 145 mips_elf_greg_t *regp = *gregsetp;
96f026fc 146 void *dst;
2aa830e4
DJ		 147
148 if (regno == -1)
149 {
d37eb719 150 memset (regp, 0, sizeof (mips_elf_gregset_t));
822b6570 151 for (regi = 1; regi < 32; regi++)
28f5035f 152 mips_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 153 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
154 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
155 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
156 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
28f5035f 157 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 158 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 159 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
2aa830e4
DJ		 160 return;
161 }
162
822b6570 163 if (regno > 0 && regno < 32)
2aa830e4 164 {
2aa830e4 165 dst = regp + regno + EF_REG0;
28f5035f 166 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 167 return;
168 }
169
2eb4d78b
UW		 170 if (regno == mips_regnum (gdbarch)->lo)
171 regaddr = EF_LO;
172 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 173 regaddr = EF_HI;
2eb4d78b 174 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 175 regaddr = EF_CP0_EPC;
2eb4d78b 176 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 177 regaddr = EF_CP0_BADVADDR;
24e05951 178 else if (regno == MIPS_PS_REGNUM)
56cea623 179 regaddr = EF_CP0_STATUS;
2eb4d78b 180 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 181 regaddr = EF_CP0_CAUSE;
2eb4d78b 182 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 183 && regno == MIPS_RESTART_REGNUM)
184 regaddr = EF_REG0;
56cea623
AC		 185 else
186 regaddr = -1;
2aa830e4
DJ		 187
188 if (regaddr != -1)
189 {
2aa830e4 190 dst = regp + regaddr;
28f5035f 191 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 192 }
193}
194
50e8a0d5
HZ		 195static void
196mips_fill_gregset_wrapper (const struct regset *regset,
197 const struct regcache *regcache,
198 int regnum, void *gregs, size_t len)
199{
200 gdb_assert (len == sizeof (mips_elf_gregset_t));
201
202 mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum);
203}
204
2aa830e4
DJ		 205/* Likewise, unpack an elf_fpregset_t. */
206
d37eb719 207void
28f5035f
UW		 208mips_supply_fpregset (struct regcache *regcache,
209 const mips_elf_fpregset_t *fpregsetp)
2aa830e4 210{
2eb4d78b 211 struct gdbarch *gdbarch = get_regcache_arch (regcache);
52f0bd74 212 int regi;
d9d9c31f 213 char zerobuf[MAX_REGISTER_SIZE];
bf072999 214
d9d9c31f 215 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 216
217 for (regi = 0; regi < 32; regi++)
3e8c568d 218 regcache_raw_supply (regcache,
2eb4d78b 219 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 220 *fpregsetp + regi);
2aa830e4 221
28f5035f 222 regcache_raw_supply (regcache,
2eb4d78b 223 mips_regnum (gdbarch)->fp_control_status,
28f5035f 224 *fpregsetp + 32);
2aa830e4 225
295093a4 226 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
28f5035f 227 regcache_raw_supply (regcache,
2eb4d78b 228 mips_regnum (gdbarch)->fp_implementation_revision,
23a6d369 229 zerobuf);
2aa830e4
DJ		 230}
231
50e8a0d5
HZ		 232static void
233mips_supply_fpregset_wrapper (const struct regset *regset,
234 struct regcache *regcache,
235 int regnum, const void *gregs, size_t len)
236{
237 gdb_assert (len == sizeof (mips_elf_fpregset_t));
238
239 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs);
240}
241
2aa830e4
DJ		 242/* Likewise, pack one or all floating point registers into an
243 elf_fpregset_t. */
244
d37eb719 245void
28f5035f
UW		 246mips_fill_fpregset (const struct regcache *regcache,
247 mips_elf_fpregset_t *fpregsetp, int regno)
2aa830e4 248{
2eb4d78b 249 struct gdbarch *gdbarch = get_regcache_arch (regcache);
22e048c9 250 char *to;
2aa830e4 251
2eb4d78b
UW		 252 if ((regno >= gdbarch_fp0_regnum (gdbarch))
253 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
2aa830e4 254 {
2eb4d78b 255 to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch));
28f5035f 256 regcache_raw_collect (regcache, regno, to);
2aa830e4 257 }
2eb4d78b 258 else if (regno == mips_regnum (gdbarch)->fp_control_status)
2aa830e4 259 {
2aa830e4 260 to = (char *) (*fpregsetp + 32);
28f5035f 261 regcache_raw_collect (regcache, regno, to);
2aa830e4
DJ		 262 }
263 else if (regno == -1)
264 {
265 int regi;
266
267 for (regi = 0; regi < 32; regi++)
3e8c568d 268 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 269 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 270 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 271 mips_regnum (gdbarch)->fp_control_status);
2aa830e4
DJ		 272 }
273}
274
50e8a0d5
HZ		 275static void
276mips_fill_fpregset_wrapper (const struct regset *regset,
277 const struct regcache *regcache,
278 int regnum, void *gregs, size_t len)
279{
280 gdb_assert (len == sizeof (mips_elf_fpregset_t));
281
282 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum);
283}
284
96f026fc
KB		 285/* Support for 64-bit ABIs. */
286
96f026fc 287/* Figure out where the longjmp will land.
295093a4
MS		 288 We expect the first arg to be a pointer to the jmp_buf structure
289 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
290 at. The pc is copied into PC. This routine returns 1 on
291 success. */
96f026fc
KB		 292
293/* Details about jmp_buf. */
294
295#define MIPS64_LINUX_JB_PC 0
296
297static int
60ade65d 298mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
96f026fc
KB		 299{
300 CORE_ADDR jb_addr;
2eb4d78b 301 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 302 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2eb4d78b
UW		 303 void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
304 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8;
96f026fc 305
60ade65d 306 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
96f026fc
KB		 307
308 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
819844ad 309 buf,
2eb4d78b 310 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
96f026fc
KB		 311 return 0;
312
819844ad 313 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 314 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
315 byte_order);
96f026fc
KB		 316
317 return 1;
318}
319
d37eb719
DJ		 320/* Register set support functions. These operate on standard 64-bit
321 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
322 target will still use the 64-bit format for PTRACE_GETREGS. */
323
324/* Supply a 64-bit register. */
96f026fc 325
63807e1d 326static void
28f5035f
UW		 327supply_64bit_reg (struct regcache *regcache, int regnum,
328 const gdb_byte *buf)
d37eb719 329{
2eb4d78b
UW		 330 struct gdbarch *gdbarch = get_regcache_arch (regcache);
331 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
332 && register_size (gdbarch, regnum) == 4)
28f5035f 333 regcache_raw_supply (regcache, regnum, buf + 4);
d37eb719 334 else
28f5035f 335 regcache_raw_supply (regcache, regnum, buf);
d37eb719
DJ		 336}
337
338/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
339
340void
28f5035f
UW		 341mips64_supply_gregset (struct regcache *regcache,
342 const mips64_elf_gregset_t *gregsetp)
96f026fc
KB		 343{
344 int regi;
28f5035f 345 const mips64_elf_greg_t *regp = *gregsetp;
d37eb719 346 gdb_byte zerobuf[MAX_REGISTER_SIZE];
2eb4d78b 347 struct gdbarch *gdbarch = get_regcache_arch (regcache);
96f026fc 348
d9d9c31f 349 memset (zerobuf, 0, MAX_REGISTER_SIZE);
96f026fc 350
822b6570 351 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++)
28f5035f
UW		 352 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
353 (const gdb_byte *)(regp + regi));
354
2eb4d78b 355 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 356 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM,
357 (const gdb_byte *)(regp + MIPS64_EF_REG0));
358
2eb4d78b 359 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo,
28f5035f 360 (const gdb_byte *) (regp + MIPS64_EF_LO));
2eb4d78b 361 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi,
28f5035f
UW		 362 (const gdb_byte *) (regp + MIPS64_EF_HI));
363
2eb4d78b 364 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 365 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
2eb4d78b 366 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 367 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
368 supply_64bit_reg (regcache, MIPS_PS_REGNUM,
369 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
2eb4d78b 370 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 371 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc 372
1faeff08 373 /* Fill the inaccessible zero register with zero. */
822b6570 374 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
96f026fc
KB		 375}
376
50e8a0d5
HZ		 377static void
378mips64_supply_gregset_wrapper (const struct regset *regset,
379 struct regcache *regcache,
380 int regnum, const void *gregs, size_t len)
381{
382 gdb_assert (len == sizeof (mips64_elf_gregset_t));
383
384 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs);
385}
386
d37eb719 387/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 388
d37eb719 389void
28f5035f
UW		 390mips64_fill_gregset (const struct regcache *regcache,
391 mips64_elf_gregset_t *gregsetp, int regno)
96f026fc 392{
2eb4d78b 393 struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 394 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
96f026fc
KB		 395 int regaddr, regi;
396 mips64_elf_greg_t *regp = *gregsetp;
2ba93934 397 void *dst;
96f026fc
KB		 398
399 if (regno == -1)
400 {
401 memset (regp, 0, sizeof (mips64_elf_gregset_t));
822b6570 402 for (regi = 1; regi < 32; regi++)
28f5035f 403 mips64_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 404 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
405 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
406 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
025bb325
MS		 407 mips64_fill_gregset (regcache, gregsetp,
408 mips_regnum (gdbarch)->badvaddr);
28f5035f 409 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 410 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 411 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
96f026fc
KB		 412 return;
413 }
414
822b6570 415 if (regno > 0 && regno < 32)
d37eb719 416 regaddr = regno + MIPS64_EF_REG0;
2eb4d78b 417 else if (regno == mips_regnum (gdbarch)->lo)
56cea623 418 regaddr = MIPS64_EF_LO;
2eb4d78b 419 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 420 regaddr = MIPS64_EF_HI;
2eb4d78b 421 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 422 regaddr = MIPS64_EF_CP0_EPC;
2eb4d78b 423 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 424 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 425 else if (regno == MIPS_PS_REGNUM)
56cea623 426 regaddr = MIPS64_EF_CP0_STATUS;
2eb4d78b 427 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 428 regaddr = MIPS64_EF_CP0_CAUSE;
2eb4d78b 429 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 430 && regno == MIPS_RESTART_REGNUM)
431 regaddr = MIPS64_EF_REG0;
56cea623
AC		 432 else
433 regaddr = -1;
96f026fc
KB		 434
435 if (regaddr != -1)
436 {
d37eb719
DJ		 437 gdb_byte buf[MAX_REGISTER_SIZE];
438 LONGEST val;
439
28f5035f 440 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 441 val = extract_signed_integer (buf, register_size (gdbarch, regno),
442 byte_order);
96f026fc 443 dst = regp + regaddr;
e17a4113 444 store_signed_integer (dst, 8, byte_order, val);
96f026fc
KB		 445 }
446}
447
50e8a0d5
HZ		 448static void
449mips64_fill_gregset_wrapper (const struct regset *regset,
450 const struct regcache *regcache,
451 int regnum, void *gregs, size_t len)
452{
453 gdb_assert (len == sizeof (mips64_elf_gregset_t));
454
455 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum);
456}
457
96f026fc
KB		 458/* Likewise, unpack an elf_fpregset_t. */
459
d37eb719 460void
28f5035f
UW		 461mips64_supply_fpregset (struct regcache *regcache,
462 const mips64_elf_fpregset_t *fpregsetp)
96f026fc 463{
2eb4d78b 464 struct gdbarch *gdbarch = get_regcache_arch (regcache);
52f0bd74 465 int regi;
96f026fc 466
d37eb719
DJ		 467 /* See mips_linux_o32_sigframe_init for a description of the
468 peculiar FP register layout. */
2eb4d78b 469 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4)
d37eb719
DJ		 470 for (regi = 0; regi < 32; regi++)
471 {
28f5035f 472 const gdb_byte *reg_ptr = (const gdb_byte *)(*fpregsetp + (regi & ~1));
2eb4d78b 473 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 474 reg_ptr += 4;
3e8c568d 475 regcache_raw_supply (regcache,
2eb4d78b 476 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 477 reg_ptr);
d37eb719
DJ		 478 }
479 else
480 for (regi = 0; regi < 32; regi++)
3e8c568d 481 regcache_raw_supply (regcache,
2eb4d78b 482 gdbarch_fp0_regnum (gdbarch) + regi,
28f5035f 483 (const char *)(*fpregsetp + regi));
d37eb719 484
2eb4d78b 485 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status,
28f5035f 486 (const gdb_byte *)(*fpregsetp + 32));
d37eb719
DJ		 487
488 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
489 include it - but the result of PTRACE_GETFPREGS does. The best we
490 can do is to assume that its value is present. */
28f5035f 491 supply_32bit_reg (regcache,
2eb4d78b 492 mips_regnum (gdbarch)->fp_implementation_revision,
28f5035f 493 (const gdb_byte *)(*fpregsetp + 32) + 4);
96f026fc
KB		 494}
495
50e8a0d5
HZ		 496static void
497mips64_supply_fpregset_wrapper (const struct regset *regset,
498 struct regcache *regcache,
499 int regnum, const void *gregs, size_t len)
500{
501 gdb_assert (len == sizeof (mips64_elf_fpregset_t));
502
503 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs);
504}
505
96f026fc
KB		 506/* Likewise, pack one or all floating point registers into an
507 elf_fpregset_t. */
508
d37eb719 509void
28f5035f
UW		 510mips64_fill_fpregset (const struct regcache *regcache,
511 mips64_elf_fpregset_t *fpregsetp, int regno)
96f026fc 512{
2eb4d78b 513 struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 514 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d37eb719 515 gdb_byte *to;
96f026fc 516
2eb4d78b
UW		 517 if ((regno >= gdbarch_fp0_regnum (gdbarch))
518 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
96f026fc 519 {
d37eb719
DJ		 520 /* See mips_linux_o32_sigframe_init for a description of the
521 peculiar FP register layout. */
2eb4d78b 522 if (register_size (gdbarch, regno) == 4)
d37eb719 523 {
2eb4d78b 524 int regi = regno - gdbarch_fp0_regnum (gdbarch);
d37eb719
DJ		 525
526 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 527 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 528 to += 4;
28f5035f 529 regcache_raw_collect (regcache, regno, to);
d37eb719
DJ		 530 }
531 else
532 {
025bb325
MS		 533 to = (gdb_byte *) (*fpregsetp + regno
534 - gdbarch_fp0_regnum (gdbarch));
28f5035f 535 regcache_raw_collect (regcache, regno, to);
d37eb719 536 }
96f026fc 537 }
2eb4d78b 538 else if (regno == mips_regnum (gdbarch)->fp_control_status)
96f026fc 539 {
d37eb719
DJ		 540 gdb_byte buf[MAX_REGISTER_SIZE];
541 LONGEST val;
542
28f5035f 543 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 544 val = extract_signed_integer (buf, register_size (gdbarch, regno),
545 byte_order);
d37eb719 546 to = (gdb_byte *) (*fpregsetp + 32);
e17a4113 547 store_signed_integer (to, 4, byte_order, val);
d37eb719 548 }
2eb4d78b 549 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ		 550 {
551 gdb_byte buf[MAX_REGISTER_SIZE];
552 LONGEST val;
553
28f5035f 554 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 555 val = extract_signed_integer (buf, register_size (gdbarch, regno),
556 byte_order);
d37eb719 557 to = (gdb_byte *) (*fpregsetp + 32) + 4;
e17a4113 558 store_signed_integer (to, 4, byte_order, val);
96f026fc
KB		 559 }
560 else if (regno == -1)
561 {
562 int regi;
563
564 for (regi = 0; regi < 32; regi++)
3e8c568d 565 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 566 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 567 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 568 mips_regnum (gdbarch)->fp_control_status);
28f5035f 569 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b
UW		 570 (mips_regnum (gdbarch)
571 ->fp_implementation_revision));
96f026fc
KB		 572 }
573}
574
50e8a0d5
HZ		 575static void
576mips64_fill_fpregset_wrapper (const struct regset *regset,
577 const struct regcache *regcache,
578 int regnum, void *gregs, size_t len)
579{
580 gdb_assert (len == sizeof (mips64_elf_fpregset_t));
96f026fc 581
50e8a0d5
HZ		 582 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum);
583}
2aa830e4 584
693be288 585static const struct regset *
50e8a0d5
HZ		 586mips_linux_regset_from_core_section (struct gdbarch *gdbarch,
587 const char *sect_name, size_t sect_size)
2aa830e4 588{
50e8a0d5 589 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
d37eb719
DJ		 590 mips_elf_gregset_t gregset;
591 mips_elf_fpregset_t fpregset;
96f026fc
KB		 592 mips64_elf_gregset_t gregset64;
593 mips64_elf_fpregset_t fpregset64;
2aa830e4 594
50e8a0d5 595 if (strcmp (sect_name, ".reg") == 0)
2aa830e4 596 {
50e8a0d5 597 if (sect_size == sizeof (gregset))
2aa830e4 598 {
50e8a0d5
HZ		 599 if (tdep->gregset == NULL)
600 tdep->gregset = regset_alloc (gdbarch,
601 mips_supply_gregset_wrapper,
602 mips_fill_gregset_wrapper);
603 return tdep->gregset;
96f026fc 604 }
50e8a0d5 605 else if (sect_size == sizeof (gregset64))
96f026fc 606 {
50e8a0d5
HZ		 607 if (tdep->gregset64 == NULL)
608 tdep->gregset64 = regset_alloc (gdbarch,
609 mips64_supply_gregset_wrapper,
610 mips64_fill_gregset_wrapper);
611 return tdep->gregset64;
2aa830e4
DJ		 612 }
613 else
614 {
8a3fe4f8 615 warning (_("wrong size gregset struct in core file"));
2aa830e4
DJ		 616 }
617 }
50e8a0d5 618 else if (strcmp (sect_name, ".reg2") == 0)
2aa830e4 619 {
50e8a0d5 620 if (sect_size == sizeof (fpregset))
2aa830e4 621 {
50e8a0d5
HZ		 622 if (tdep->fpregset == NULL)
623 tdep->fpregset = regset_alloc (gdbarch,
624 mips_supply_fpregset_wrapper,
625 mips_fill_fpregset_wrapper);
626 return tdep->fpregset;
96f026fc 627 }
50e8a0d5 628 else if (sect_size == sizeof (fpregset64))
96f026fc 629 {
50e8a0d5
HZ		 630 if (tdep->fpregset64 == NULL)
631 tdep->fpregset64 = regset_alloc (gdbarch,
632 mips64_supply_fpregset_wrapper,
633 mips64_fill_fpregset_wrapper);
634 return tdep->fpregset64;
2aa830e4
DJ		 635 }
636 else
637 {
8a3fe4f8 638 warning (_("wrong size fpregset struct in core file"));
2aa830e4
DJ		 639 }
640 }
2aa830e4 641
50e8a0d5
HZ		 642 return NULL;
643}
2aa830e4 644
4eb0ad19
DJ		 645static const struct target_desc *
646mips_linux_core_read_description (struct gdbarch *gdbarch,
647 struct target_ops *target,
648 bfd *abfd)
649{
650 asection *section = bfd_get_section_by_name (abfd, ".reg");
651 if (! section)
652 return NULL;
653
654 switch (bfd_section_size (abfd, section))
655 {
656 case sizeof (mips_elf_gregset_t):
657 return mips_tdesc_gp32;
658
659 case sizeof (mips64_elf_gregset_t):
660 return mips_tdesc_gp64;
661
662 default:
663 return NULL;
664 }
665}
666
96f026fc 667
295093a4
MS		 668/* Check the code at PC for a dynamic linker lazy resolution stub.
669 Because they aren't in the .plt section, we pattern-match on the
670 code generated by GNU ld. They look like this:
6de918a6
DJ		 671
672 lw t9,0x8010(gp)
673 addu t7,ra
674 jalr t9,ra
675 addiu t8,zero,INDEX
676
295093a4
MS		 677 (with the appropriate doubleword instructions for N64). Also
678 return the dynamic symbol index used in the last instruction. */
6de918a6
DJ		 679
680static int
681mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
682{
683 unsigned char buf[28], *p;
684 ULONGEST insn, insn1;
1cf3db46 685 int n64 = (mips_abi (target_gdbarch) == MIPS_ABI_N64);
e17a4113 686 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch);
6de918a6
DJ		 687
688 read_memory (pc - 12, buf, 28);
689
690 if (n64)
691 {
692 /* ld t9,0x8010(gp) */
693 insn1 = 0xdf998010;
694 }
695 else
696 {
697 /* lw t9,0x8010(gp) */
698 insn1 = 0x8f998010;
699 }
700
701 p = buf + 12;
702 while (p >= buf)
703 {
e17a4113 704 insn = extract_unsigned_integer (p, 4, byte_order);
6de918a6
DJ		 705 if (insn == insn1)
706 break;
707 p -= 4;
708 }
709 if (p < buf)
710 return 0;
711
e17a4113 712 insn = extract_unsigned_integer (p + 4, 4, byte_order);
6de918a6
DJ		 713 if (n64)
714 {
715 /* daddu t7,ra */
716 if (insn != 0x03e0782d)
717 return 0;
718 }
719 else
720 {
721 /* addu t7,ra */
722 if (insn != 0x03e07821)
723 return 0;
724 }
295093a4 725
e17a4113 726 insn = extract_unsigned_integer (p + 8, 4, byte_order);
6de918a6
DJ		 727 /* jalr t9,ra */
728 if (insn != 0x0320f809)
729 return 0;
730
e17a4113 731 insn = extract_unsigned_integer (p + 12, 4, byte_order);
6de918a6
DJ		 732 if (n64)
733 {
734 /* daddiu t8,zero,0 */
735 if ((insn & 0xffff0000) != 0x64180000)
736 return 0;
737 }
738 else
739 {
740 /* addiu t8,zero,0 */
741 if ((insn & 0xffff0000) != 0x24180000)
742 return 0;
743 }
744
745 return (insn & 0xffff);
746}
747
295093a4 748/* Return non-zero iff PC belongs to the dynamic linker resolution
db5f024e 749 code, a PLT entry, or a lazy binding stub. */
6de918a6 750
7d522c90 751static int
6de918a6
DJ		 752mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
753{
295093a4 754 /* Check whether PC is in the dynamic linker. This also checks
db5f024e 755 whether it is in the .plt section, used by non-PIC executables. */
7d522c90 756 if (svr4_in_dynsym_resolve_code (pc))
6de918a6
DJ		 757 return 1;
758
295093a4
MS		 759 /* Pattern match for the stub. It would be nice if there were a
760 more efficient way to avoid this check. */
6de918a6
DJ		 761 if (mips_linux_in_dynsym_stub (pc, NULL))
762 return 1;
763
764 return 0;
765}
766
767/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
768 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
769 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba 770 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
db5f024e
DJ		 771 "__dl_runtime_resolve" directly. An unresolved lazy binding
772 stub will point to _dl_runtime_resolve, which will first call
c4c5b7ba
AC		 773 __dl_runtime_resolve, and then pass control to the resolved
774 function. */
6de918a6
DJ		 775
776static CORE_ADDR
777mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
778{
779 struct minimal_symbol *resolver;
780
781 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
782
783 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
c7ce8faa 784 return frame_unwind_caller_pc (get_current_frame ());
6de918a6 785
db5f024e 786 return glibc_skip_solib_resolver (gdbarch, pc);
295093a4 787}
6de918a6 788
5792a79b
DJ		 789/* Signal trampoline support. There are four supported layouts for a
790 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
791 n64 rt_sigframe. We handle them all independently; not the most
792 efficient way, but simplest. First, declare all the unwinders. */
793
794static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 795 struct frame_info *this_frame,
5792a79b
DJ		 796 struct trad_frame_cache *this_cache,
797 CORE_ADDR func);
798
799static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 800 struct frame_info *this_frame,
5792a79b
DJ		 801 struct trad_frame_cache *this_cache,
802 CORE_ADDR func);
803
804#define MIPS_NR_LINUX 4000
805#define MIPS_NR_N64_LINUX 5000
806#define MIPS_NR_N32_LINUX 6000
807
808#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
809#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
810#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
811#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
812
813#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
814#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
815#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
816#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
817#define MIPS_INST_SYSCALL 0x0000000c
818
2cd8546d
AC		 819static const struct tramp_frame mips_linux_o32_sigframe = {
820 SIGTRAMP_FRAME,
5792a79b 821 4,
2cd8546d
AC		 822 {
823 { MIPS_INST_LI_V0_SIGRETURN, -1 },
824 { MIPS_INST_SYSCALL, -1 },
825 { TRAMP_SENTINEL_INSN, -1 }
826 },
5792a79b
DJ		 827 mips_linux_o32_sigframe_init
828};
829
2cd8546d
AC		 830static const struct tramp_frame mips_linux_o32_rt_sigframe = {
831 SIGTRAMP_FRAME,
5792a79b 832 4,
2cd8546d
AC		 833 {
834 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
835 { MIPS_INST_SYSCALL, -1 },
836 { TRAMP_SENTINEL_INSN, -1 } },
5792a79b
DJ		 837 mips_linux_o32_sigframe_init
838};
839
2cd8546d
AC		 840static const struct tramp_frame mips_linux_n32_rt_sigframe = {
841 SIGTRAMP_FRAME,
5792a79b 842 4,
2cd8546d
AC		 843 {
844 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
845 { MIPS_INST_SYSCALL, -1 },
846 { TRAMP_SENTINEL_INSN, -1 }
847 },
5792a79b
DJ		 848 mips_linux_n32n64_sigframe_init
849};
850
2cd8546d
AC		 851static const struct tramp_frame mips_linux_n64_rt_sigframe = {
852 SIGTRAMP_FRAME,
5792a79b 853 4,
fcbd8a5c
TS		 854 {
855 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
856 { MIPS_INST_SYSCALL, -1 },
857 { TRAMP_SENTINEL_INSN, -1 }
858 },
5792a79b
DJ		 859 mips_linux_n32n64_sigframe_init
860};
861
862/* *INDENT-OFF* */
863/* The unwinder for o32 signal frames. The legacy structures look
864 like this:
865
866 struct sigframe {
867 u32 sf_ass[4]; [argument save space for o32]
eb195664 868 u32 sf_code[2]; [signal trampoline or fill]
5792a79b
DJ		 869 struct sigcontext sf_sc;
870 sigset_t sf_mask;
871 };
872
d0e64392
MR		 873 Pre-2.6.12 sigcontext:
874
5792a79b
DJ		 875 struct sigcontext {
876 unsigned int sc_regmask; [Unused]
877 unsigned int sc_status;
878 unsigned long long sc_pc;
879 unsigned long long sc_regs[32];
880 unsigned long long sc_fpregs[32];
881 unsigned int sc_ownedfp;
882 unsigned int sc_fpc_csr;
883 unsigned int sc_fpc_eir; [Unused]
884 unsigned int sc_used_math;
885 unsigned int sc_ssflags; [Unused]
886 [Alignment hole of four bytes]
887 unsigned long long sc_mdhi;
888 unsigned long long sc_mdlo;
889
890 unsigned int sc_cause; [Unused]
891 unsigned int sc_badvaddr; [Unused]
892
893 unsigned long sc_sigset[4]; [kernel's sigset_t]
894 };
895
d0e64392
MR		 896 Post-2.6.12 sigcontext (SmartMIPS/DSP support added):
897
898 struct sigcontext {
899 unsigned int sc_regmask; [Unused]
900 unsigned int sc_status; [Unused]
901 unsigned long long sc_pc;
902 unsigned long long sc_regs[32];
903 unsigned long long sc_fpregs[32];
904 unsigned int sc_acx;
905 unsigned int sc_fpc_csr;
906 unsigned int sc_fpc_eir; [Unused]
907 unsigned int sc_used_math;
908 unsigned int sc_dsp;
909 [Alignment hole of four bytes]
910 unsigned long long sc_mdhi;
911 unsigned long long sc_mdlo;
912 unsigned long sc_hi1;
913 unsigned long sc_lo1;
914 unsigned long sc_hi2;
915 unsigned long sc_lo2;
916 unsigned long sc_hi3;
917 unsigned long sc_lo3;
918 };
919
5792a79b
DJ		 920 The RT signal frames look like this:
921
922 struct rt_sigframe {
923 u32 rs_ass[4]; [argument save space for o32]
eb195664 924 u32 rs_code[2] [signal trampoline or fill]
5792a79b
DJ		 925 struct siginfo rs_info;
926 struct ucontext rs_uc;
927 };
928
929 struct ucontext {
930 unsigned long uc_flags;
931 struct ucontext *uc_link;
932 stack_t uc_stack;
933 [Alignment hole of four bytes]
934 struct sigcontext uc_mcontext;
935 sigset_t uc_sigmask;
936 }; */
937/* *INDENT-ON* */
938
5792a79b
DJ		 939#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
940
941#define RTSIGFRAME_SIGINFO_SIZE 128
942#define STACK_T_SIZE (3 * 4)
943#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
944#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
945 + RTSIGFRAME_SIGINFO_SIZE \
946 + UCONTEXT_SIGCONTEXT_OFFSET)
947
948#define SIGCONTEXT_PC (1 * 8)
949#define SIGCONTEXT_REGS (2 * 8)
950#define SIGCONTEXT_FPREGS (34 * 8)
951#define SIGCONTEXT_FPCSR (66 * 8 + 4)
d0e64392 952#define SIGCONTEXT_DSPCTL (68 * 8 + 0)
5792a79b
DJ		 953#define SIGCONTEXT_HI (69 * 8)
954#define SIGCONTEXT_LO (70 * 8)
955#define SIGCONTEXT_CAUSE (71 * 8 + 0)
956#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
d0e64392
MR		 957#define SIGCONTEXT_HI1 (71 * 8 + 0)
958#define SIGCONTEXT_LO1 (71 * 8 + 4)
959#define SIGCONTEXT_HI2 (72 * 8 + 0)
960#define SIGCONTEXT_LO2 (72 * 8 + 4)
961#define SIGCONTEXT_HI3 (73 * 8 + 0)
962#define SIGCONTEXT_LO3 (73 * 8 + 4)
5792a79b
DJ		 963
964#define SIGCONTEXT_REG_SIZE 8
965
966static void
967mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 968 struct frame_info *this_frame,
5792a79b
DJ		 969 struct trad_frame_cache *this_cache,
970 CORE_ADDR func)
971{
b8a22b94 972 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 973 int ireg;
eb195664
DD		 974 CORE_ADDR frame_sp = get_frame_sp (this_frame);
975 CORE_ADDR sigcontext_base;
2eb4d78b 976 const struct mips_regnum *regs = mips_regnum (gdbarch);
37c4d197 977 CORE_ADDR regs_base;
5792a79b
DJ		 978
979 if (self == &mips_linux_o32_sigframe)
eb195664 980 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 981 else
eb195664 982 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 983
984 /* I'm not proud of this hack. Eventually we will have the
985 infrastructure to indicate the size of saved registers on a
986 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 987 bytes but we only want four. Use regs_base to access any
988 64-bit fields. */
2eb4d78b 989 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
37c4d197
DJ		 990 regs_base = sigcontext_base + 4;
991 else
992 regs_base = sigcontext_base;
5792a79b 993
2eb4d78b 994 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 995 trad_frame_set_reg_addr (this_cache,
996 (MIPS_RESTART_REGNUM
2eb4d78b 997 + gdbarch_num_regs (gdbarch)),
822b6570 998 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 999
1000 for (ireg = 1; ireg < 32; ireg++)
295093a4 1001 trad_frame_set_reg_addr (this_cache,
f57d151a 1002 ireg + MIPS_ZERO_REGNUM
2eb4d78b 1003 + gdbarch_num_regs (gdbarch),
37c4d197 1004 regs_base + SIGCONTEXT_REGS
5792a79b
DJ		 1005 + ireg * SIGCONTEXT_REG_SIZE);
1006
37c4d197
DJ		 1007 /* The way that floating point registers are saved, unfortunately,
1008 depends on the architecture the kernel is built for. For the r3000 and
1009 tx39, four bytes of each register are at the beginning of each of the
1010 32 eight byte slots. For everything else, the registers are saved
1011 using double precision; only the even-numbered slots are initialized,
1012 and the high bits are the odd-numbered register. Assume the latter
1013 layout, since we can't tell, and it's much more common. Which bits are
1014 the "high" bits depends on endianness. */
5792a79b 1015 for (ireg = 0; ireg < 32; ireg++)
2eb4d78b 1016 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
f57d151a
UW		 1017 trad_frame_set_reg_addr (this_cache,
1018 ireg + regs->fp0 +
2eb4d78b 1019 gdbarch_num_regs (gdbarch),
37c4d197
DJ		 1020 sigcontext_base + SIGCONTEXT_FPREGS + 4
1021 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
1022 else
f57d151a
UW		 1023 trad_frame_set_reg_addr (this_cache,
1024 ireg + regs->fp0
2eb4d78b 1025 + gdbarch_num_regs (gdbarch),
37c4d197
DJ		 1026 sigcontext_base + SIGCONTEXT_FPREGS
1027 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
5792a79b 1028
f57d151a 1029 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1030 regs->pc + gdbarch_num_regs (gdbarch),
37c4d197 1031 regs_base + SIGCONTEXT_PC);
5792a79b 1032
295093a4 1033 trad_frame_set_reg_addr (this_cache,
f57d151a 1034 regs->fp_control_status
2eb4d78b 1035 + gdbarch_num_regs (gdbarch),
5792a79b 1036 sigcontext_base + SIGCONTEXT_FPCSR);
d0e64392
MR		 1037
1038 if (regs->dspctl != -1)
1039 trad_frame_set_reg_addr (this_cache,
1040 regs->dspctl + gdbarch_num_regs (gdbarch),
1041 sigcontext_base + SIGCONTEXT_DSPCTL);
1042
f57d151a 1043 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1044 regs->hi + gdbarch_num_regs (gdbarch),
37c4d197 1045 regs_base + SIGCONTEXT_HI);
f57d151a 1046 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1047 regs->lo + gdbarch_num_regs (gdbarch),
37c4d197 1048 regs_base + SIGCONTEXT_LO);
d0e64392
MR		 1049
1050 if (regs->dspacc != -1)
1051 {
1052 trad_frame_set_reg_addr (this_cache,
1053 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1054 sigcontext_base + SIGCONTEXT_HI1);
1055 trad_frame_set_reg_addr (this_cache,
1056 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1057 sigcontext_base + SIGCONTEXT_LO1);
1058 trad_frame_set_reg_addr (this_cache,
1059 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1060 sigcontext_base + SIGCONTEXT_HI2);
1061 trad_frame_set_reg_addr (this_cache,
1062 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1063 sigcontext_base + SIGCONTEXT_LO2);
1064 trad_frame_set_reg_addr (this_cache,
1065 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1066 sigcontext_base + SIGCONTEXT_HI3);
1067 trad_frame_set_reg_addr (this_cache,
1068 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1069 sigcontext_base + SIGCONTEXT_LO3);
1070 }
1071 else
1072 {
1073 trad_frame_set_reg_addr (this_cache,
1074 regs->cause + gdbarch_num_regs (gdbarch),
1075 sigcontext_base + SIGCONTEXT_CAUSE);
1076 trad_frame_set_reg_addr (this_cache,
1077 regs->badvaddr + gdbarch_num_regs (gdbarch),
1078 sigcontext_base + SIGCONTEXT_BADVADDR);
1079 }
5792a79b
DJ		 1080
1081 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1082 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1083}
1084
1085/* *INDENT-OFF* */
1086/* For N32/N64 things look different. There is no non-rt signal frame.
1087
1088 struct rt_sigframe_n32 {
1089 u32 rs_ass[4]; [ argument save space for o32 ]
eb195664 1090 u32 rs_code[2]; [ signal trampoline or fill ]
5792a79b
DJ		 1091 struct siginfo rs_info;
1092 struct ucontextn32 rs_uc;
1093 };
1094
1095 struct ucontextn32 {
1096 u32 uc_flags;
1097 s32 uc_link;
1098 stack32_t uc_stack;
1099 struct sigcontext uc_mcontext;
1100 sigset_t uc_sigmask; [ mask last for extensibility ]
1101 };
295093a4 1102
e741f4d4 1103 struct rt_sigframe {
5792a79b
DJ		 1104 u32 rs_ass[4]; [ argument save space for o32 ]
1105 u32 rs_code[2]; [ signal trampoline ]
1106 struct siginfo rs_info;
1107 struct ucontext rs_uc;
1108 };
1109
1110 struct ucontext {
1111 unsigned long uc_flags;
1112 struct ucontext *uc_link;
1113 stack_t uc_stack;
1114 struct sigcontext uc_mcontext;
1115 sigset_t uc_sigmask; [ mask last for extensibility ]
1116 };
1117
1118 And the sigcontext is different (this is for both n32 and n64):
1119
1120 struct sigcontext {
1121 unsigned long long sc_regs[32];
1122 unsigned long long sc_fpregs[32];
1123 unsigned long long sc_mdhi;
e741f4d4
DJ		 1124 unsigned long long sc_hi1;
1125 unsigned long long sc_hi2;
1126 unsigned long long sc_hi3;
5792a79b 1127 unsigned long long sc_mdlo;
e741f4d4
DJ		 1128 unsigned long long sc_lo1;
1129 unsigned long long sc_lo2;
1130 unsigned long long sc_lo3;
5792a79b 1131 unsigned long long sc_pc;
5792a79b 1132 unsigned int sc_fpc_csr;
5792a79b 1133 unsigned int sc_used_math;
e741f4d4
DJ		 1134 unsigned int sc_dsp;
1135 unsigned int sc_reserved;
1136 };
1137
1138 That is the post-2.6.12 definition of the 64-bit sigcontext; before
1139 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
1140 included too. */
5792a79b
DJ		 1141/* *INDENT-ON* */
1142
1143#define N32_STACK_T_SIZE STACK_T_SIZE
1144#define N64_STACK_T_SIZE (2 * 8 + 4)
1145#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1146#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1147#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1148 + RTSIGFRAME_SIGINFO_SIZE \
1149 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1150#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1151 + RTSIGFRAME_SIGINFO_SIZE \
1152 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1153
1154#define N64_SIGCONTEXT_REGS (0 * 8)
1155#define N64_SIGCONTEXT_FPREGS (32 * 8)
1156#define N64_SIGCONTEXT_HI (64 * 8)
d0e64392
MR		 1157#define N64_SIGCONTEXT_HI1 (65 * 8)
1158#define N64_SIGCONTEXT_HI2 (66 * 8)
1159#define N64_SIGCONTEXT_HI3 (67 * 8)
e741f4d4 1160#define N64_SIGCONTEXT_LO (68 * 8)
d0e64392
MR		 1161#define N64_SIGCONTEXT_LO1 (69 * 8)
1162#define N64_SIGCONTEXT_LO2 (70 * 8)
1163#define N64_SIGCONTEXT_LO3 (71 * 8)
e741f4d4 1164#define N64_SIGCONTEXT_PC (72 * 8)
d0e64392
MR		 1165#define N64_SIGCONTEXT_FPCSR (73 * 8 + 0)
1166#define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0)
5792a79b
DJ		 1167
1168#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1169
5792a79b
DJ		 1170static void
1171mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 1172 struct frame_info *this_frame,
5792a79b
DJ		 1173 struct trad_frame_cache *this_cache,
1174 CORE_ADDR func)
1175{
b8a22b94 1176 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1177 int ireg;
eb195664
DD		 1178 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1179 CORE_ADDR sigcontext_base;
2eb4d78b 1180 const struct mips_regnum *regs = mips_regnum (gdbarch);
5792a79b
DJ		 1181
1182 if (self == &mips_linux_n32_rt_sigframe)
eb195664 1183 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1184 else
eb195664 1185 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1186
2eb4d78b 1187 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1188 trad_frame_set_reg_addr (this_cache,
1189 (MIPS_RESTART_REGNUM
2eb4d78b 1190 + gdbarch_num_regs (gdbarch)),
822b6570 1191 sigcontext_base + N64_SIGCONTEXT_REGS);
5792a79b
DJ		 1192
1193 for (ireg = 1; ireg < 32; ireg++)
295093a4 1194 trad_frame_set_reg_addr (this_cache,
f57d151a 1195 ireg + MIPS_ZERO_REGNUM
2eb4d78b 1196 + gdbarch_num_regs (gdbarch),
5792a79b
DJ		 1197 sigcontext_base + N64_SIGCONTEXT_REGS
1198 + ireg * N64_SIGCONTEXT_REG_SIZE);
1199
1200 for (ireg = 0; ireg < 32; ireg++)
f57d151a
UW		 1201 trad_frame_set_reg_addr (this_cache,
1202 ireg + regs->fp0
2eb4d78b 1203 + gdbarch_num_regs (gdbarch),
5792a79b
DJ		 1204 sigcontext_base + N64_SIGCONTEXT_FPREGS
1205 + ireg * N64_SIGCONTEXT_REG_SIZE);
1206
f57d151a 1207 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1208 regs->pc + gdbarch_num_regs (gdbarch),
5792a79b
DJ		 1209 sigcontext_base + N64_SIGCONTEXT_PC);
1210
295093a4 1211 trad_frame_set_reg_addr (this_cache,
f57d151a 1212 regs->fp_control_status
2eb4d78b 1213 + gdbarch_num_regs (gdbarch),
5792a79b 1214 sigcontext_base + N64_SIGCONTEXT_FPCSR);
d0e64392 1215
f57d151a 1216 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1217 regs->hi + gdbarch_num_regs (gdbarch),
5792a79b 1218 sigcontext_base + N64_SIGCONTEXT_HI);
f57d151a 1219 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1220 regs->lo + gdbarch_num_regs (gdbarch),
5792a79b 1221 sigcontext_base + N64_SIGCONTEXT_LO);
5792a79b 1222
d0e64392
MR		 1223 if (regs->dspacc != -1)
1224 {
1225 trad_frame_set_reg_addr (this_cache,
1226 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1227 sigcontext_base + N64_SIGCONTEXT_HI1);
1228 trad_frame_set_reg_addr (this_cache,
1229 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1230 sigcontext_base + N64_SIGCONTEXT_LO1);
1231 trad_frame_set_reg_addr (this_cache,
1232 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1233 sigcontext_base + N64_SIGCONTEXT_HI2);
1234 trad_frame_set_reg_addr (this_cache,
1235 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1236 sigcontext_base + N64_SIGCONTEXT_LO2);
1237 trad_frame_set_reg_addr (this_cache,
1238 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1239 sigcontext_base + N64_SIGCONTEXT_HI3);
1240 trad_frame_set_reg_addr (this_cache,
1241 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1242 sigcontext_base + N64_SIGCONTEXT_LO3);
1243 }
1244 if (regs->dspctl != -1)
1245 trad_frame_set_reg_addr (this_cache,
1246 regs->dspctl + gdbarch_num_regs (gdbarch),
1247 sigcontext_base + N64_SIGCONTEXT_DSPCTL);
1248
5792a79b 1249 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1250 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1251}
1252
5a439849
MR		 1253/* Implement the "write_pc" gdbarch method. */
1254
822b6570 1255static void
61a1198a 1256mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
822b6570 1257{
2eb4d78b 1258 struct gdbarch *gdbarch = get_regcache_arch (regcache);
5a439849
MR		 1259
1260 mips_write_pc (regcache, pc);
822b6570
DJ		 1261
1262 /* Clear the syscall restart flag. */
2eb4d78b 1263 if (mips_linux_restart_reg_p (gdbarch))
61a1198a 1264 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
822b6570
DJ		 1265}
1266
1267/* Return 1 if MIPS_RESTART_REGNUM is usable. */
1268
1269int
1270mips_linux_restart_reg_p (struct gdbarch *gdbarch)
1271{
1272 /* If we do not have a target description with registers, then
1273 MIPS_RESTART_REGNUM will not be included in the register set. */
1274 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
1275 return 0;
1276
1277 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
1278 either be GPR-sized or missing. */
1279 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
1280}
9f62d0e2 1281
e38d4e1a
DJ		 1282/* When FRAME is at a syscall instruction, return the PC of the next
1283 instruction to be executed. */
1284
63807e1d 1285static CORE_ADDR
e38d4e1a
DJ		 1286mips_linux_syscall_next_pc (struct frame_info *frame)
1287{
1288 CORE_ADDR pc = get_frame_pc (frame);
1289 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
1290
1291 /* If we are about to make a sigreturn syscall, use the unwinder to
1292 decode the signal frame. */
1293 if (v0 == MIPS_NR_sigreturn
1294 || v0 == MIPS_NR_rt_sigreturn
1295 || v0 == MIPS_NR_N64_rt_sigreturn
1296 || v0 == MIPS_NR_N32_rt_sigreturn)
c7ce8faa 1297 return frame_unwind_caller_pc (get_current_frame ());
e38d4e1a
DJ		 1298
1299 return pc + 4;
1300}
1301
385203ed
DD		 1302/* Return the current system call's number present in the
1303 v0 register. When the function fails, it returns -1. */
1304
1305static LONGEST
1306mips_linux_get_syscall_number (struct gdbarch *gdbarch,
1307 ptid_t ptid)
1308{
1309 struct regcache *regcache = get_thread_regcache (ptid);
1310 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1311 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1312 int regsize = register_size (gdbarch, MIPS_V0_REGNUM);
1313 /* The content of a register */
1314 gdb_byte buf[8];
1315 /* The result */
1316 LONGEST ret;
1317
1318 /* Make sure we're in a known ABI */
1319 gdb_assert (tdep->mips_abi == MIPS_ABI_O32
1320 || tdep->mips_abi == MIPS_ABI_N32
1321 || tdep->mips_abi == MIPS_ABI_N64);
1322
1323 gdb_assert (regsize <= sizeof (buf));
1324
1325 /* Getting the system call number from the register.
1326 syscall number is in v0 or $2. */
1327 regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf);
1328
1329 ret = extract_signed_integer (buf, regsize, byte_order);
1330
1331 return ret;
1332}
1333
232b8704
ME		 1334/* Translate signals based on MIPS signal values.
1335 Adapted from gdb/common/signals.c. */
1336
1337static enum gdb_signal
1338mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signo)
1339{
1340 switch (signo)
1341 {
1342 case 0:
1343 return GDB_SIGNAL_0;
1344 case MIPS_SIGHUP:
1345 return GDB_SIGNAL_HUP;
1346 case MIPS_SIGINT:
1347 return GDB_SIGNAL_INT;
1348 case MIPS_SIGQUIT:
1349 return GDB_SIGNAL_QUIT;
1350 case MIPS_SIGILL:
1351 return GDB_SIGNAL_ILL;
1352 case MIPS_SIGTRAP:
1353 return GDB_SIGNAL_TRAP;
1354 case MIPS_SIGABRT:
1355 return GDB_SIGNAL_ABRT;
1356 case MIPS_SIGEMT:
1357 return GDB_SIGNAL_EMT;
1358 case MIPS_SIGFPE:
1359 return GDB_SIGNAL_FPE;
1360 case MIPS_SIGKILL:
1361 return GDB_SIGNAL_KILL;
1362 case MIPS_SIGBUS:
1363 return GDB_SIGNAL_BUS;
1364 case MIPS_SIGSEGV:
1365 return GDB_SIGNAL_SEGV;
1366 case MIPS_SIGSYS:
1367 return GDB_SIGNAL_SYS;
1368 case MIPS_SIGPIPE:
1369 return GDB_SIGNAL_PIPE;
1370 case MIPS_SIGALRM:
1371 return GDB_SIGNAL_ALRM;
1372 case MIPS_SIGTERM:
1373 return GDB_SIGNAL_TERM;
1374 case MIPS_SIGUSR1:
1375 return GDB_SIGNAL_USR1;
1376 case MIPS_SIGUSR2:
1377 return GDB_SIGNAL_USR2;
1378 case MIPS_SIGCHLD:
1379 return GDB_SIGNAL_CHLD;
1380 case MIPS_SIGPWR:
1381 return GDB_SIGNAL_PWR;
1382 case MIPS_SIGWINCH:
1383 return GDB_SIGNAL_WINCH;
1384 case MIPS_SIGURG:
1385 return GDB_SIGNAL_URG;
1386 case MIPS_SIGPOLL:
1387 return GDB_SIGNAL_POLL;
1388 case MIPS_SIGSTOP:
1389 return GDB_SIGNAL_STOP;
1390 case MIPS_SIGTSTP:
1391 return GDB_SIGNAL_TSTP;
1392 case MIPS_SIGCONT:
1393 return GDB_SIGNAL_CONT;
1394 case MIPS_SIGTTIN:
1395 return GDB_SIGNAL_TTIN;
1396 case MIPS_SIGTTOU:
1397 return GDB_SIGNAL_TTOU;
1398 case MIPS_SIGVTALRM:
1399 return GDB_SIGNAL_VTALRM;
1400 case MIPS_SIGPROF:
1401 return GDB_SIGNAL_PROF;
1402 case MIPS_SIGXCPU:
1403 return GDB_SIGNAL_XCPU;
1404 case MIPS_SIGXFSZ:
1405 return GDB_SIGNAL_XFSZ;
1406 }
1407
1408 if (signo >= MIPS_SIGRTMIN && signo <= MIPS_SIGRTMAX)
1409 {
1410 /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of
1411 the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */
1412 signo -= MIPS_SIGRTMIN;
1413 if (signo == 0)
1414 return GDB_SIGNAL_REALTIME_32;
1415 else if (signo < 32)
1416 return ((enum gdb_signal) (signo - 1 + (int) GDB_SIGNAL_REALTIME_33));
1417 else
1418 return ((enum gdb_signal) (signo - 32 + (int) GDB_SIGNAL_REALTIME_64));
1419 }
1420
1421 return GDB_SIGNAL_UNKNOWN;
1422}
1423
5792a79b
DJ		 1424/* Initialize one of the GNU/Linux OS ABIs. */
1425
19ed69dd 1426static void
295093a4
MS		 1427mips_linux_init_abi (struct gdbarch_info info,
1428 struct gdbarch *gdbarch)
19ed69dd 1429{
96f026fc
KB		 1430 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1431 enum mips_abi abi = mips_abi (gdbarch);
822b6570 1432 struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info;
96f026fc 1433
a5ee0f0c
PA		 1434 linux_init_abi (info, gdbarch);
1435
385203ed
DD		 1436 /* Get the syscall number from the arch's register. */
1437 set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number);
1438
96f026fc
KB		 1439 switch (abi)
1440 {
1441 case MIPS_ABI_O32:
1442 set_gdbarch_get_longjmp_target (gdbarch,
1443 mips_linux_get_longjmp_target);
1444 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1445 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
fb2be677
AC		 1446 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1447 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
385203ed 1448 set_xml_syscall_file_name ("syscalls/mips-o32-linux.xml");
96f026fc
KB		 1449 break;
1450 case MIPS_ABI_N32:
1451 set_gdbarch_get_longjmp_target (gdbarch,
1452 mips_linux_get_longjmp_target);
1453 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1454 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
d05f6826
DJ		 1455 set_gdbarch_long_double_bit (gdbarch, 128);
1456 /* These floatformats should probably be renamed. MIPS uses
1457 the same 128-bit IEEE floating point format that IA-64 uses,
1458 except that the quiet/signalling NaN bit is reversed (GDB
1459 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1460 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
fb2be677 1461 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
385203ed 1462 set_xml_syscall_file_name ("syscalls/mips-n32-linux.xml");
96f026fc
KB		 1463 break;
1464 case MIPS_ABI_N64:
1465 set_gdbarch_get_longjmp_target (gdbarch,
1466 mips64_linux_get_longjmp_target);
1467 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1468 (gdbarch, svr4_lp64_fetch_link_map_offsets);
d05f6826
DJ		 1469 set_gdbarch_long_double_bit (gdbarch, 128);
1470 /* These floatformats should probably be renamed. MIPS uses
1471 the same 128-bit IEEE floating point format that IA-64 uses,
1472 except that the quiet/signalling NaN bit is reversed (GDB
1473 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1474 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
fb2be677 1475 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
385203ed 1476 set_xml_syscall_file_name ("syscalls/mips-n64-linux.xml");
96f026fc
KB		 1477 break;
1478 default:
96f026fc
KB		 1479 break;
1480 }
6de918a6
DJ		 1481
1482 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1483
0d0266c6 1484 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1485
1486 /* Enable TLS support. */
1487 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1488 svr4_fetch_objfile_link_map);
7d522c90
DJ		 1489
1490 /* Initialize this lazily, to avoid an initialization order
1491 dependency on solib-svr4.c's _initialize routine. */
1492 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
1493 {
1494 mips_svr4_so_ops = svr4_so_ops;
1495 mips_svr4_so_ops.in_dynsym_resolve_code
1496 = mips_linux_in_dynsym_resolve_code;
1497 }
1498 set_solib_ops (gdbarch, &mips_svr4_so_ops);
822b6570
DJ		 1499
1500 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
1501
4eb0ad19
DJ		 1502 set_gdbarch_core_read_description (gdbarch,
1503 mips_linux_core_read_description);
1504
50e8a0d5
HZ		 1505 set_gdbarch_regset_from_core_section (gdbarch,
1506 mips_linux_regset_from_core_section);
1507
232b8704
ME		 1508 set_gdbarch_gdb_signal_from_target (gdbarch,
1509 mips_gdb_signal_from_target);
1510
e38d4e1a
DJ		 1511 tdep->syscall_next_pc = mips_linux_syscall_next_pc;
1512
822b6570
DJ		 1513 if (tdesc_data)
1514 {
1515 const struct tdesc_feature *feature;
1516
1517 /* If we have target-described registers, then we can safely
1518 reserve a number for MIPS_RESTART_REGNUM (whether it is
1519 described or not). */
1520 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
1521 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
cf233303 1522 set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
822b6570
DJ		 1523
1524 /* If it's present, then assign it to the reserved number. */
1525 feature = tdesc_find_feature (info.target_desc,
1526 "org.gnu.gdb.mips.linux");
1527 if (feature != NULL)
1528 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
1529 "restart");
1530 }
19ed69dd
KB		 1531}
1532
63807e1d
PA		 1533/* Provide a prototype to silence -Wmissing-prototypes. */
1534extern initialize_file_ftype _initialize_mips_linux_tdep;
1535
2aa830e4 1536void
d1bacddc 1537_initialize_mips_linux_tdep (void)
2aa830e4 1538{
96f026fc
KB		 1539 const struct bfd_arch_info *arch_info;
1540
96f026fc
KB		 1541 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1542 arch_info != NULL;
1543 arch_info = arch_info->next)
1544 {
295093a4
MS		 1545 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1546 GDB_OSABI_LINUX,
96f026fc
KB		 1547 mips_linux_init_abi);
1548 }
2aa830e4 1549}
GDB Binutils - Deliverables
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