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Remove regcache_raw_write
[deliverable/binutils-gdb.git] / gdb / mips-linux-tdep.c
CommitLineData
75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
e2882c85 3 Copyright (C) 2001-2018 Free Software Foundation, Inc.
2aa830e4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ		 19
20#include "defs.h"
21#include "gdbcore.h"
22#include "target.h"
23#include "solib-svr4.h"
19ed69dd 24#include "osabi.h"
96f026fc 25#include "mips-tdep.h"
6de918a6 26#include "frame.h"
2fdf551c 27#include "regcache.h"
5792a79b
DJ		 28#include "trad-frame.h"
29#include "tramp-frame.h"
e6bb342a 30#include "gdbtypes.h"
3e5d3a5a 31#include "objfiles.h"
5ea03926 32#include "solib.h"
7d522c90 33#include "solist.h"
982e9687 34#include "symtab.h"
822b6570 35#include "target-descriptions.h"
50e8a0d5 36#include "regset.h"
d37eb719 37#include "mips-linux-tdep.h"
db5f024e 38#include "glibc-tdep.h"
a5ee0f0c 39#include "linux-tdep.h"
385203ed 40#include "xml-syscall.h"
232b8704 41#include "gdb_signals.h"
2aa830e4 42
032bb6ea
YQ		 43#include "features/mips-linux.c"
44#include "features/mips-dsp-linux.c"
45#include "features/mips64-linux.c"
46#include "features/mips64-dsp-linux.c"
47
7d522c90
DJ		 48static struct target_so_ops mips_svr4_so_ops;
49
eb14d406
SDJ		 50/* This enum represents the signals' numbers on the MIPS
51 architecture. It just contains the signal definitions which are
52 different from the generic implementation.
53
54 It is derived from the file <arch/mips/include/uapi/asm/signal.h>,
55 from the Linux kernel tree. */
56
57enum
58 {
59 MIPS_LINUX_SIGEMT = 7,
60 MIPS_LINUX_SIGBUS = 10,
61 MIPS_LINUX_SIGSYS = 12,
62 MIPS_LINUX_SIGUSR1 = 16,
63 MIPS_LINUX_SIGUSR2 = 17,
64 MIPS_LINUX_SIGCHLD = 18,
65 MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD,
66 MIPS_LINUX_SIGPWR = 19,
67 MIPS_LINUX_SIGWINCH = 20,
68 MIPS_LINUX_SIGURG = 21,
69 MIPS_LINUX_SIGIO = 22,
70 MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO,
71 MIPS_LINUX_SIGSTOP = 23,
72 MIPS_LINUX_SIGTSTP = 24,
73 MIPS_LINUX_SIGCONT = 25,
74 MIPS_LINUX_SIGTTIN = 26,
75 MIPS_LINUX_SIGTTOU = 27,
76 MIPS_LINUX_SIGVTALRM = 28,
77 MIPS_LINUX_SIGPROF = 29,
78 MIPS_LINUX_SIGXCPU = 30,
79 MIPS_LINUX_SIGXFSZ = 31,
80
81 MIPS_LINUX_SIGRTMIN = 32,
82 MIPS_LINUX_SIGRT64 = 64,
83 MIPS_LINUX_SIGRTMAX = 127,
84 };
85
2aa830e4 86/* Figure out where the longjmp will land.
295093a4
MS		 87 We expect the first arg to be a pointer to the jmp_buf structure
88 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
89 at. The pc is copied into PC. This routine returns 1 on
90 success. */
2aa830e4 91
19ed69dd
KB		 92#define MIPS_LINUX_JB_ELEMENT_SIZE 4
93#define MIPS_LINUX_JB_PC 0
94
95static int
60ade65d 96mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2aa830e4
DJ		 97{
98 CORE_ADDR jb_addr;
2eb4d78b 99 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 100 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e362b510 101 gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
2aa830e4 102
60ade65d 103 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
2aa830e4 104
7d266584
MR		 105 if (target_read_memory ((jb_addr
106 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE),
2eb4d78b 107 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
2aa830e4
DJ		 108 return 0;
109
819844ad 110 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 111 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
112 byte_order);
2aa830e4
DJ		 113
114 return 1;
115}
116
4246e332 117/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 118 for regcache_raw_supply(). This is needed when mips_isa_regsize()
119 is 8. */
96f026fc
KB		 120
121static void
28f5035f 122supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
96f026fc 123{
b057297a 124 regcache->raw_supply_integer (regnum, (const gdb_byte *) addr, 4, true);
96f026fc
KB		 125}
126
2aa830e4
DJ		 127/* Unpack an elf_gregset_t into GDB's register cache. */
128
d37eb719 129void
28f5035f
UW		 130mips_supply_gregset (struct regcache *regcache,
131 const mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 132{
133 int regi;
28f5035f 134 const mips_elf_greg_t *regp = *gregsetp;
ac7936df 135 struct gdbarch *gdbarch = regcache->arch ();
bf072999 136
822b6570 137 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++)
28f5035f 138 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
2aa830e4 139
2eb4d78b 140 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 141 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0);
142
2eb4d78b
UW		 143 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO);
144 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI);
56cea623 145
2eb4d78b 146 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 147 regp + EF_CP0_EPC);
2eb4d78b 148 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 149 regp + EF_CP0_BADVADDR);
150 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
2eb4d78b 151 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 152 regp + EF_CP0_CAUSE);
2aa830e4 153
1faeff08 154 /* Fill the inaccessible zero register with zero. */
27bfc1d1 155 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
2aa830e4
DJ		 156}
157
50e8a0d5
HZ		 158static void
159mips_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 160 struct regcache *regcache,
161 int regnum, const void *gregs, size_t len)
50e8a0d5 162{
1528345d 163 gdb_assert (len >= sizeof (mips_elf_gregset_t));
50e8a0d5
HZ		 164
165 mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs);
166}
167
2aa830e4
DJ		 168/* Pack our registers (or one register) into an elf_gregset_t. */
169
d37eb719 170void
28f5035f
UW		 171mips_fill_gregset (const struct regcache *regcache,
172 mips_elf_gregset_t *gregsetp, int regno)
2aa830e4 173{
ac7936df 174 struct gdbarch *gdbarch = regcache->arch ();
2aa830e4 175 int regaddr, regi;
d37eb719 176 mips_elf_greg_t *regp = *gregsetp;
96f026fc 177 void *dst;
2aa830e4
DJ		 178
179 if (regno == -1)
180 {
d37eb719 181 memset (regp, 0, sizeof (mips_elf_gregset_t));
822b6570 182 for (regi = 1; regi < 32; regi++)
28f5035f 183 mips_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 184 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
185 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
186 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
187 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
28f5035f 188 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 189 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 190 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
2aa830e4
DJ		 191 return;
192 }
193
822b6570 194 if (regno > 0 && regno < 32)
2aa830e4 195 {
2aa830e4 196 dst = regp + regno + EF_REG0;
28f5035f 197 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 198 return;
199 }
200
2eb4d78b
UW		 201 if (regno == mips_regnum (gdbarch)->lo)
202 regaddr = EF_LO;
203 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 204 regaddr = EF_HI;
2eb4d78b 205 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 206 regaddr = EF_CP0_EPC;
2eb4d78b 207 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 208 regaddr = EF_CP0_BADVADDR;
24e05951 209 else if (regno == MIPS_PS_REGNUM)
56cea623 210 regaddr = EF_CP0_STATUS;
2eb4d78b 211 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 212 regaddr = EF_CP0_CAUSE;
2eb4d78b 213 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 214 && regno == MIPS_RESTART_REGNUM)
215 regaddr = EF_REG0;
56cea623
AC		 216 else
217 regaddr = -1;
2aa830e4
DJ		 218
219 if (regaddr != -1)
220 {
2aa830e4 221 dst = regp + regaddr;
28f5035f 222 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 223 }
224}
225
50e8a0d5
HZ		 226static void
227mips_fill_gregset_wrapper (const struct regset *regset,
228 const struct regcache *regcache,
229 int regnum, void *gregs, size_t len)
230{
1528345d 231 gdb_assert (len >= sizeof (mips_elf_gregset_t));
50e8a0d5
HZ		 232
233 mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum);
234}
235
96f026fc
KB		 236/* Support for 64-bit ABIs. */
237
96f026fc 238/* Figure out where the longjmp will land.
295093a4
MS		 239 We expect the first arg to be a pointer to the jmp_buf structure
240 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
241 at. The pc is copied into PC. This routine returns 1 on
242 success. */
96f026fc
KB		 243
244/* Details about jmp_buf. */
245
246#define MIPS64_LINUX_JB_PC 0
247
248static int
60ade65d 249mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
96f026fc
KB		 250{
251 CORE_ADDR jb_addr;
2eb4d78b 252 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 253 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
709476c3
SM		 254 gdb_byte *buf
255 = (gdb_byte *) alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
2eb4d78b 256 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8;
96f026fc 257
60ade65d 258 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
96f026fc
KB		 259
260 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
819844ad 261 buf,
2eb4d78b 262 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
96f026fc
KB		 263 return 0;
264
819844ad 265 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 266 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
267 byte_order);
96f026fc
KB		 268
269 return 1;
270}
271
d37eb719
DJ		 272/* Register set support functions. These operate on standard 64-bit
273 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
274 target will still use the 64-bit format for PTRACE_GETREGS. */
275
276/* Supply a 64-bit register. */
96f026fc 277
63807e1d 278static void
28f5035f
UW		 279supply_64bit_reg (struct regcache *regcache, int regnum,
280 const gdb_byte *buf)
d37eb719 281{
ac7936df 282 struct gdbarch *gdbarch = regcache->arch ();
2eb4d78b
UW		 283 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
284 && register_size (gdbarch, regnum) == 4)
28f5035f 285 regcache_raw_supply (regcache, regnum, buf + 4);
d37eb719 286 else
28f5035f 287 regcache_raw_supply (regcache, regnum, buf);
d37eb719
DJ		 288}
289
290/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
291
292void
28f5035f
UW		 293mips64_supply_gregset (struct regcache *regcache,
294 const mips64_elf_gregset_t *gregsetp)
96f026fc
KB		 295{
296 int regi;
28f5035f 297 const mips64_elf_greg_t *regp = *gregsetp;
ac7936df 298 struct gdbarch *gdbarch = regcache->arch ();
96f026fc 299
822b6570 300 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++)
28f5035f 301 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
7d266584 302 (const gdb_byte *) (regp + regi));
28f5035f 303
2eb4d78b 304 if (mips_linux_restart_reg_p (gdbarch))
822b6570 305 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM,
7d266584 306 (const gdb_byte *) (regp + MIPS64_EF_REG0));
822b6570 307
2eb4d78b 308 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo,
28f5035f 309 (const gdb_byte *) (regp + MIPS64_EF_LO));
2eb4d78b 310 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi,
28f5035f
UW		 311 (const gdb_byte *) (regp + MIPS64_EF_HI));
312
2eb4d78b 313 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 314 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
2eb4d78b 315 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 316 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
317 supply_64bit_reg (regcache, MIPS_PS_REGNUM,
318 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
2eb4d78b 319 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 320 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc 321
1faeff08 322 /* Fill the inaccessible zero register with zero. */
27bfc1d1 323 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
96f026fc
KB		 324}
325
50e8a0d5
HZ		 326static void
327mips64_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 328 struct regcache *regcache,
329 int regnum, const void *gregs, size_t len)
50e8a0d5 330{
1528345d 331 gdb_assert (len >= sizeof (mips64_elf_gregset_t));
50e8a0d5
HZ		 332
333 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs);
334}
335
d37eb719 336/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 337
d37eb719 338void
28f5035f
UW		 339mips64_fill_gregset (const struct regcache *regcache,
340 mips64_elf_gregset_t *gregsetp, int regno)
96f026fc 341{
ac7936df 342 struct gdbarch *gdbarch = regcache->arch ();
96f026fc
KB		 343 int regaddr, regi;
344 mips64_elf_greg_t *regp = *gregsetp;
2ba93934 345 void *dst;
96f026fc
KB		 346
347 if (regno == -1)
348 {
349 memset (regp, 0, sizeof (mips64_elf_gregset_t));
822b6570 350 for (regi = 1; regi < 32; regi++)
7d266584 351 mips64_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 352 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
353 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
354 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
025bb325
MS		 355 mips64_fill_gregset (regcache, gregsetp,
356 mips_regnum (gdbarch)->badvaddr);
28f5035f 357 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 358 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 359 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
96f026fc
KB		 360 return;
361 }
362
822b6570 363 if (regno > 0 && regno < 32)
d37eb719 364 regaddr = regno + MIPS64_EF_REG0;
2eb4d78b 365 else if (regno == mips_regnum (gdbarch)->lo)
56cea623 366 regaddr = MIPS64_EF_LO;
2eb4d78b 367 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 368 regaddr = MIPS64_EF_HI;
2eb4d78b 369 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 370 regaddr = MIPS64_EF_CP0_EPC;
2eb4d78b 371 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 372 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 373 else if (regno == MIPS_PS_REGNUM)
56cea623 374 regaddr = MIPS64_EF_CP0_STATUS;
2eb4d78b 375 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 376 regaddr = MIPS64_EF_CP0_CAUSE;
2eb4d78b 377 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 378 && regno == MIPS_RESTART_REGNUM)
379 regaddr = MIPS64_EF_REG0;
56cea623
AC		 380 else
381 regaddr = -1;
96f026fc
KB		 382
383 if (regaddr != -1)
384 {
385 dst = regp + regaddr;
b057297a 386 regcache->raw_collect_integer (regno, (gdb_byte *) dst, 8, true);
96f026fc
KB		 387 }
388}
389
50e8a0d5
HZ		 390static void
391mips64_fill_gregset_wrapper (const struct regset *regset,
392 const struct regcache *regcache,
393 int regnum, void *gregs, size_t len)
394{
1528345d 395 gdb_assert (len >= sizeof (mips64_elf_gregset_t));
50e8a0d5
HZ		 396
397 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum);
398}
399
d8dab6c3
MR		 400/* Likewise, unpack an elf_fpregset_t. Linux only uses even-numbered
401 FPR slots in the Status.FR=0 mode, storing even-odd FPR pairs as the
402 SDC1 instruction would. When run on MIPS I architecture processors
403 all FPR slots used to be used, unusually, holding the respective FPRs
404 in the first 4 bytes, but that was corrected for consistency, with
405 `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator
406 changes."), the fix corrected with LMO commit 849fa7a50dff ("R3k FPU
407 ptrace() handling fixes."), and then broken and fixed over and over
408 again, until last time fixed with commit 80cbfad79096 ("MIPS: Correct
409 MIPS I FP context layout"). */
96f026fc 410
d37eb719 411void
28f5035f
UW		 412mips64_supply_fpregset (struct regcache *regcache,
413 const mips64_elf_fpregset_t *fpregsetp)
96f026fc 414{
ac7936df 415 struct gdbarch *gdbarch = regcache->arch ();
52f0bd74 416 int regi;
96f026fc 417
2eb4d78b 418 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4)
d37eb719
DJ		 419 for (regi = 0; regi < 32; regi++)
420 {
7d266584
MR		 421 const gdb_byte *reg_ptr
422 = (const gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 423 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 424 reg_ptr += 4;
3e8c568d 425 regcache_raw_supply (regcache,
2eb4d78b 426 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 427 reg_ptr);
d37eb719
DJ		 428 }
429 else
430 for (regi = 0; regi < 32; regi++)
3e8c568d 431 regcache_raw_supply (regcache,
2eb4d78b 432 gdbarch_fp0_regnum (gdbarch) + regi,
7d266584 433 (const char *) (*fpregsetp + regi));
d37eb719 434
2eb4d78b 435 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status,
7d266584 436 (const gdb_byte *) (*fpregsetp + 32));
d37eb719
DJ		 437
438 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
439 include it - but the result of PTRACE_GETFPREGS does. The best we
440 can do is to assume that its value is present. */
28f5035f 441 supply_32bit_reg (regcache,
2eb4d78b 442 mips_regnum (gdbarch)->fp_implementation_revision,
7d266584 443 (const gdb_byte *) (*fpregsetp + 32) + 4);
96f026fc
KB		 444}
445
50e8a0d5
HZ		 446static void
447mips64_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 448 struct regcache *regcache,
449 int regnum, const void *gregs, size_t len)
50e8a0d5 450{
1528345d 451 gdb_assert (len >= sizeof (mips64_elf_fpregset_t));
50e8a0d5
HZ		 452
453 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs);
454}
455
96f026fc 456/* Likewise, pack one or all floating point registers into an
d8dab6c3
MR		 457 elf_fpregset_t. See `mips_supply_fpregset' for an explanation
458 of the layout. */
96f026fc 459
d37eb719 460void
28f5035f
UW		 461mips64_fill_fpregset (const struct regcache *regcache,
462 mips64_elf_fpregset_t *fpregsetp, int regno)
96f026fc 463{
ac7936df 464 struct gdbarch *gdbarch = regcache->arch ();
d37eb719 465 gdb_byte *to;
96f026fc 466
2eb4d78b
UW		 467 if ((regno >= gdbarch_fp0_regnum (gdbarch))
468 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
96f026fc 469 {
2eb4d78b 470 if (register_size (gdbarch, regno) == 4)
d37eb719 471 {
2eb4d78b 472 int regi = regno - gdbarch_fp0_regnum (gdbarch);
d37eb719
DJ		 473
474 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 475 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 476 to += 4;
28f5035f 477 regcache_raw_collect (regcache, regno, to);
d37eb719
DJ		 478 }
479 else
480 {
025bb325
MS		 481 to = (gdb_byte *) (*fpregsetp + regno
482 - gdbarch_fp0_regnum (gdbarch));
28f5035f 483 regcache_raw_collect (regcache, regno, to);
d37eb719 484 }
96f026fc 485 }
2eb4d78b 486 else if (regno == mips_regnum (gdbarch)->fp_control_status)
96f026fc 487 {
d37eb719 488 to = (gdb_byte *) (*fpregsetp + 32);
b057297a 489 regcache->raw_collect_integer (regno, to, 4, true);
d37eb719 490 }
2eb4d78b 491 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719 492 {
d37eb719 493 to = (gdb_byte *) (*fpregsetp + 32) + 4;
b057297a 494 regcache->raw_collect_integer (regno, to, 4, true);
96f026fc
KB		 495 }
496 else if (regno == -1)
497 {
498 int regi;
499
500 for (regi = 0; regi < 32; regi++)
3e8c568d 501 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 502 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 503 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 504 mips_regnum (gdbarch)->fp_control_status);
28f5035f 505 mips64_fill_fpregset (regcache, fpregsetp,
7d266584 506 mips_regnum (gdbarch)->fp_implementation_revision);
96f026fc
KB		 507 }
508}
509
50e8a0d5
HZ		 510static void
511mips64_fill_fpregset_wrapper (const struct regset *regset,
512 const struct regcache *regcache,
513 int regnum, void *gregs, size_t len)
514{
1528345d 515 gdb_assert (len >= sizeof (mips64_elf_fpregset_t));
96f026fc 516
50e8a0d5
HZ		 517 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum);
518}
2aa830e4 519
b7195f27
AA		 520static const struct regset mips_linux_gregset =
521 {
522 NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper
523 };
524
525static const struct regset mips64_linux_gregset =
526 {
527 NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper
528 };
529
b7195f27
AA		 530static const struct regset mips64_linux_fpregset =
531 {
532 NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper
533 };
534
d4036235
AA		 535static void
536mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
537 iterate_over_regset_sections_cb *cb,
538 void *cb_data,
539 const struct regcache *regcache)
2aa830e4 540{
d4036235 541 if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4)
2aa830e4 542 {
d4036235
AA		 543 cb (".reg", sizeof (mips_elf_gregset_t), &mips_linux_gregset,
544 NULL, cb_data);
d8dab6c3 545 cb (".reg2", sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset,
d4036235 546 NULL, cb_data);
2aa830e4 547 }
d4036235 548 else
2aa830e4 549 {
d4036235
AA		 550 cb (".reg", sizeof (mips64_elf_gregset_t), &mips64_linux_gregset,
551 NULL, cb_data);
552 cb (".reg2", sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset,
553 NULL, cb_data);
2aa830e4 554 }
50e8a0d5 555}
2aa830e4 556
4eb0ad19
DJ		 557static const struct target_desc *
558mips_linux_core_read_description (struct gdbarch *gdbarch,
559 struct target_ops *target,
560 bfd *abfd)
561{
562 asection *section = bfd_get_section_by_name (abfd, ".reg");
563 if (! section)
564 return NULL;
565
566 switch (bfd_section_size (abfd, section))
567 {
568 case sizeof (mips_elf_gregset_t):
569 return mips_tdesc_gp32;
570
571 case sizeof (mips64_elf_gregset_t):
572 return mips_tdesc_gp64;
573
574 default:
575 return NULL;
576 }
577}
578
96f026fc 579
295093a4 580/* Check the code at PC for a dynamic linker lazy resolution stub.
3e5d3a5a
MR		 581 GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs"
582 section uniformly since version 2.15. If the pc is in that section,
583 then we are in such a stub. Before that ".stub" was used in 32-bit
584 ELF binaries, however we do not bother checking for that since we
585 have never had and that case should be extremely rare these days.
586 Instead we pattern-match on the code generated by GNU ld. They look
587 like this:
6de918a6
DJ		 588
589 lw t9,0x8010(gp)
590 addu t7,ra
591 jalr t9,ra
592 addiu t8,zero,INDEX
593
3e5d3a5a
MR		 594 (with the appropriate doubleword instructions for N64). As any lazy
595 resolution stubs in microMIPS binaries will always be in a
596 ".MIPS.stubs" section we only ever verify standard MIPS patterns. */
6de918a6
DJ		 597
598static int
3e5d3a5a 599mips_linux_in_dynsym_stub (CORE_ADDR pc)
6de918a6 600{
e362b510 601 gdb_byte buf[28], *p;
6de918a6 602 ULONGEST insn, insn1;
f5656ead
TT		 603 int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64);
604 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
6de918a6 605
3e5d3a5a
MR		 606 if (in_mips_stubs_section (pc))
607 return 1;
608
6de918a6
DJ		 609 read_memory (pc - 12, buf, 28);
610
611 if (n64)
612 {
613 /* ld t9,0x8010(gp) */
614 insn1 = 0xdf998010;
615 }
616 else
617 {
618 /* lw t9,0x8010(gp) */
619 insn1 = 0x8f998010;
620 }
621
622 p = buf + 12;
623 while (p >= buf)
624 {
e17a4113 625 insn = extract_unsigned_integer (p, 4, byte_order);
6de918a6
DJ		 626 if (insn == insn1)
627 break;
628 p -= 4;
629 }
630 if (p < buf)
631 return 0;
632
e17a4113 633 insn = extract_unsigned_integer (p + 4, 4, byte_order);
6de918a6
DJ		 634 if (n64)
635 {
93084fcd
SD		 636 /* 'daddu t7,ra' or 'or t7, ra, zero'*/
637 if (insn != 0x03e0782d || insn != 0x03e07825)
6de918a6 638 return 0;
93084fcd 639
6de918a6
DJ		 640 }
641 else
642 {
93084fcd
SD		 643 /* 'addu t7,ra' or 'or t7, ra, zero'*/
644 if (insn != 0x03e07821 || insn != 0x03e07825)
6de918a6 645 return 0;
93084fcd 646
6de918a6 647 }
295093a4 648
e17a4113 649 insn = extract_unsigned_integer (p + 8, 4, byte_order);
6de918a6
DJ		 650 /* jalr t9,ra */
651 if (insn != 0x0320f809)
652 return 0;
653
e17a4113 654 insn = extract_unsigned_integer (p + 12, 4, byte_order);
6de918a6
DJ		 655 if (n64)
656 {
657 /* daddiu t8,zero,0 */
658 if ((insn & 0xffff0000) != 0x64180000)
659 return 0;
660 }
661 else
662 {
663 /* addiu t8,zero,0 */
664 if ((insn & 0xffff0000) != 0x24180000)
665 return 0;
666 }
667
3e5d3a5a 668 return 1;
6de918a6
DJ		 669}
670
295093a4 671/* Return non-zero iff PC belongs to the dynamic linker resolution
db5f024e 672 code, a PLT entry, or a lazy binding stub. */
6de918a6 673
7d522c90 674static int
6de918a6
DJ		 675mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
676{
295093a4 677 /* Check whether PC is in the dynamic linker. This also checks
db5f024e 678 whether it is in the .plt section, used by non-PIC executables. */
7d522c90 679 if (svr4_in_dynsym_resolve_code (pc))
6de918a6
DJ		 680 return 1;
681
3e5d3a5a
MR		 682 /* Likewise for the stubs. They live in the .MIPS.stubs section these
683 days, so we check if the PC is within, than fall back to a pattern
684 match. */
685 if (mips_linux_in_dynsym_stub (pc))
6de918a6
DJ		 686 return 1;
687
688 return 0;
689}
690
691/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
692 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
693 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba 694 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
db5f024e
DJ		 695 "__dl_runtime_resolve" directly. An unresolved lazy binding
696 stub will point to _dl_runtime_resolve, which will first call
c4c5b7ba
AC		 697 __dl_runtime_resolve, and then pass control to the resolved
698 function. */
6de918a6
DJ		 699
700static CORE_ADDR
701mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
702{
3b7344d5 703 struct bound_minimal_symbol resolver;
6de918a6
DJ		 704
705 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
706
77e371c0 707 if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc)
c7ce8faa 708 return frame_unwind_caller_pc (get_current_frame ());
6de918a6 709
db5f024e 710 return glibc_skip_solib_resolver (gdbarch, pc);
295093a4 711}
6de918a6 712
5792a79b
DJ		 713/* Signal trampoline support. There are four supported layouts for a
714 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
715 n64 rt_sigframe. We handle them all independently; not the most
716 efficient way, but simplest. First, declare all the unwinders. */
717
718static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 719 struct frame_info *this_frame,
5792a79b
DJ		 720 struct trad_frame_cache *this_cache,
721 CORE_ADDR func);
722
723static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 724 struct frame_info *this_frame,
5792a79b
DJ		 725 struct trad_frame_cache *this_cache,
726 CORE_ADDR func);
727
858339f2
MR		 728static int mips_linux_sigframe_validate (const struct tramp_frame *self,
729 struct frame_info *this_frame,
730 CORE_ADDR *pc);
731
732static int micromips_linux_sigframe_validate (const struct tramp_frame *self,
733 struct frame_info *this_frame,
734 CORE_ADDR *pc);
735
5792a79b
DJ		 736#define MIPS_NR_LINUX 4000
737#define MIPS_NR_N64_LINUX 5000
738#define MIPS_NR_N32_LINUX 6000
739
740#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
741#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
742#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
743#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
744
745#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
746#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
747#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
748#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
749#define MIPS_INST_SYSCALL 0x0000000c
750
858339f2
MR		 751#define MICROMIPS_INST_LI_V0 0x3040
752#define MICROMIPS_INST_POOL32A 0x0000
753#define MICROMIPS_INST_SYSCALL 0x8b7c
754
2cd8546d
AC		 755static const struct tramp_frame mips_linux_o32_sigframe = {
756 SIGTRAMP_FRAME,
5792a79b 757 4,
2cd8546d
AC		 758 {
759 { MIPS_INST_LI_V0_SIGRETURN, -1 },
760 { MIPS_INST_SYSCALL, -1 },
761 { TRAMP_SENTINEL_INSN, -1 }
762 },
858339f2
MR		 763 mips_linux_o32_sigframe_init,
764 mips_linux_sigframe_validate
5792a79b
DJ		 765};
766
2cd8546d
AC		 767static const struct tramp_frame mips_linux_o32_rt_sigframe = {
768 SIGTRAMP_FRAME,
5792a79b 769 4,
2cd8546d
AC		 770 {
771 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
772 { MIPS_INST_SYSCALL, -1 },
773 { TRAMP_SENTINEL_INSN, -1 } },
858339f2
MR		 774 mips_linux_o32_sigframe_init,
775 mips_linux_sigframe_validate
5792a79b
DJ		 776};
777
2cd8546d
AC		 778static const struct tramp_frame mips_linux_n32_rt_sigframe = {
779 SIGTRAMP_FRAME,
5792a79b 780 4,
2cd8546d
AC		 781 {
782 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
783 { MIPS_INST_SYSCALL, -1 },
784 { TRAMP_SENTINEL_INSN, -1 }
785 },
858339f2
MR		 786 mips_linux_n32n64_sigframe_init,
787 mips_linux_sigframe_validate
5792a79b
DJ		 788};
789
2cd8546d
AC		 790static const struct tramp_frame mips_linux_n64_rt_sigframe = {
791 SIGTRAMP_FRAME,
5792a79b 792 4,
fcbd8a5c
TS		 793 {
794 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
795 { MIPS_INST_SYSCALL, -1 },
796 { TRAMP_SENTINEL_INSN, -1 }
797 },
858339f2
MR		 798 mips_linux_n32n64_sigframe_init,
799 mips_linux_sigframe_validate
800};
801
802static const struct tramp_frame micromips_linux_o32_sigframe = {
803 SIGTRAMP_FRAME,
804 2,
805 {
806 { MICROMIPS_INST_LI_V0, -1 },
807 { MIPS_NR_sigreturn, -1 },
808 { MICROMIPS_INST_POOL32A, -1 },
809 { MICROMIPS_INST_SYSCALL, -1 },
810 { TRAMP_SENTINEL_INSN, -1 }
811 },
812 mips_linux_o32_sigframe_init,
813 micromips_linux_sigframe_validate
814};
815
816static const struct tramp_frame micromips_linux_o32_rt_sigframe = {
817 SIGTRAMP_FRAME,
818 2,
819 {
820 { MICROMIPS_INST_LI_V0, -1 },
821 { MIPS_NR_rt_sigreturn, -1 },
822 { MICROMIPS_INST_POOL32A, -1 },
823 { MICROMIPS_INST_SYSCALL, -1 },
824 { TRAMP_SENTINEL_INSN, -1 }
825 },
826 mips_linux_o32_sigframe_init,
827 micromips_linux_sigframe_validate
828};
829
830static const struct tramp_frame micromips_linux_n32_rt_sigframe = {
831 SIGTRAMP_FRAME,
832 2,
833 {
834 { MICROMIPS_INST_LI_V0, -1 },
835 { MIPS_NR_N32_rt_sigreturn, -1 },
836 { MICROMIPS_INST_POOL32A, -1 },
837 { MICROMIPS_INST_SYSCALL, -1 },
838 { TRAMP_SENTINEL_INSN, -1 }
839 },
840 mips_linux_n32n64_sigframe_init,
841 micromips_linux_sigframe_validate
842};
843
844static const struct tramp_frame micromips_linux_n64_rt_sigframe = {
845 SIGTRAMP_FRAME,
846 2,
847 {
848 { MICROMIPS_INST_LI_V0, -1 },
849 { MIPS_NR_N64_rt_sigreturn, -1 },
850 { MICROMIPS_INST_POOL32A, -1 },
851 { MICROMIPS_INST_SYSCALL, -1 },
852 { TRAMP_SENTINEL_INSN, -1 }
853 },
854 mips_linux_n32n64_sigframe_init,
855 micromips_linux_sigframe_validate
5792a79b
DJ		 856};
857
858/* *INDENT-OFF* */
859/* The unwinder for o32 signal frames. The legacy structures look
860 like this:
861
862 struct sigframe {
863 u32 sf_ass[4]; [argument save space for o32]
eb195664 864 u32 sf_code[2]; [signal trampoline or fill]
5792a79b
DJ		 865 struct sigcontext sf_sc;
866 sigset_t sf_mask;
867 };
868
d0e64392
MR		 869 Pre-2.6.12 sigcontext:
870
5792a79b
DJ		 871 struct sigcontext {
872 unsigned int sc_regmask; [Unused]
873 unsigned int sc_status;
874 unsigned long long sc_pc;
875 unsigned long long sc_regs[32];
876 unsigned long long sc_fpregs[32];
877 unsigned int sc_ownedfp;
878 unsigned int sc_fpc_csr;
879 unsigned int sc_fpc_eir; [Unused]
880 unsigned int sc_used_math;
881 unsigned int sc_ssflags; [Unused]
882 [Alignment hole of four bytes]
883 unsigned long long sc_mdhi;
884 unsigned long long sc_mdlo;
885
886 unsigned int sc_cause; [Unused]
887 unsigned int sc_badvaddr; [Unused]
888
889 unsigned long sc_sigset[4]; [kernel's sigset_t]
890 };
891
d0e64392
MR		 892 Post-2.6.12 sigcontext (SmartMIPS/DSP support added):
893
894 struct sigcontext {
895 unsigned int sc_regmask; [Unused]
896 unsigned int sc_status; [Unused]
897 unsigned long long sc_pc;
898 unsigned long long sc_regs[32];
899 unsigned long long sc_fpregs[32];
900 unsigned int sc_acx;
901 unsigned int sc_fpc_csr;
902 unsigned int sc_fpc_eir; [Unused]
903 unsigned int sc_used_math;
904 unsigned int sc_dsp;
905 [Alignment hole of four bytes]
906 unsigned long long sc_mdhi;
907 unsigned long long sc_mdlo;
908 unsigned long sc_hi1;
909 unsigned long sc_lo1;
910 unsigned long sc_hi2;
911 unsigned long sc_lo2;
912 unsigned long sc_hi3;
913 unsigned long sc_lo3;
914 };
915
5792a79b
DJ		 916 The RT signal frames look like this:
917
918 struct rt_sigframe {
919 u32 rs_ass[4]; [argument save space for o32]
eb195664 920 u32 rs_code[2] [signal trampoline or fill]
5792a79b
DJ		 921 struct siginfo rs_info;
922 struct ucontext rs_uc;
923 };
924
925 struct ucontext {
926 unsigned long uc_flags;
927 struct ucontext *uc_link;
928 stack_t uc_stack;
929 [Alignment hole of four bytes]
930 struct sigcontext uc_mcontext;
931 sigset_t uc_sigmask;
932 }; */
933/* *INDENT-ON* */
934
5792a79b
DJ		 935#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
936
937#define RTSIGFRAME_SIGINFO_SIZE 128
938#define STACK_T_SIZE (3 * 4)
939#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
940#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
941 + RTSIGFRAME_SIGINFO_SIZE \
942 + UCONTEXT_SIGCONTEXT_OFFSET)
943
944#define SIGCONTEXT_PC (1 * 8)
945#define SIGCONTEXT_REGS (2 * 8)
946#define SIGCONTEXT_FPREGS (34 * 8)
947#define SIGCONTEXT_FPCSR (66 * 8 + 4)
d0e64392 948#define SIGCONTEXT_DSPCTL (68 * 8 + 0)
5792a79b
DJ		 949#define SIGCONTEXT_HI (69 * 8)
950#define SIGCONTEXT_LO (70 * 8)
951#define SIGCONTEXT_CAUSE (71 * 8 + 0)
952#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
d0e64392
MR		 953#define SIGCONTEXT_HI1 (71 * 8 + 0)
954#define SIGCONTEXT_LO1 (71 * 8 + 4)
955#define SIGCONTEXT_HI2 (72 * 8 + 0)
956#define SIGCONTEXT_LO2 (72 * 8 + 4)
957#define SIGCONTEXT_HI3 (73 * 8 + 0)
958#define SIGCONTEXT_LO3 (73 * 8 + 4)
5792a79b
DJ		 959
960#define SIGCONTEXT_REG_SIZE 8
961
962static void
963mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 964 struct frame_info *this_frame,
5792a79b
DJ		 965 struct trad_frame_cache *this_cache,
966 CORE_ADDR func)
967{
b8a22b94 968 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 969 int ireg;
eb195664
DD		 970 CORE_ADDR frame_sp = get_frame_sp (this_frame);
971 CORE_ADDR sigcontext_base;
2eb4d78b 972 const struct mips_regnum *regs = mips_regnum (gdbarch);
37c4d197 973 CORE_ADDR regs_base;
5792a79b 974
858339f2
MR		 975 if (self == &mips_linux_o32_sigframe
976 || self == &micromips_linux_o32_sigframe)
eb195664 977 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 978 else
eb195664 979 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 980
981 /* I'm not proud of this hack. Eventually we will have the
982 infrastructure to indicate the size of saved registers on a
983 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 984 bytes but we only want four. Use regs_base to access any
985 64-bit fields. */
2eb4d78b 986 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
37c4d197
DJ		 987 regs_base = sigcontext_base + 4;
988 else
989 regs_base = sigcontext_base;
5792a79b 990
2eb4d78b 991 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 992 trad_frame_set_reg_addr (this_cache,
993 (MIPS_RESTART_REGNUM
2eb4d78b 994 + gdbarch_num_regs (gdbarch)),
822b6570 995 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 996
997 for (ireg = 1; ireg < 32; ireg++)
295093a4 998 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 999 (ireg + MIPS_ZERO_REGNUM
1000 + gdbarch_num_regs (gdbarch)),
1001 (regs_base + SIGCONTEXT_REGS
1002 + ireg * SIGCONTEXT_REG_SIZE));
5792a79b
DJ		 1003
1004 for (ireg = 0; ireg < 32; ireg++)
2eb4d78b 1005 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
f57d151a 1006 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1007 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1008 (sigcontext_base + SIGCONTEXT_FPREGS + 4
1009 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
37c4d197 1010 else
f57d151a 1011 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1012 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1013 (sigcontext_base + SIGCONTEXT_FPREGS
1014 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
5792a79b 1015
f57d151a 1016 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1017 regs->pc + gdbarch_num_regs (gdbarch),
37c4d197 1018 regs_base + SIGCONTEXT_PC);
5792a79b 1019
295093a4 1020 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1021 (regs->fp_control_status
1022 + gdbarch_num_regs (gdbarch)),
5792a79b 1023 sigcontext_base + SIGCONTEXT_FPCSR);
d0e64392
MR		 1024
1025 if (regs->dspctl != -1)
1026 trad_frame_set_reg_addr (this_cache,
1027 regs->dspctl + gdbarch_num_regs (gdbarch),
1028 sigcontext_base + SIGCONTEXT_DSPCTL);
1029
f57d151a 1030 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1031 regs->hi + gdbarch_num_regs (gdbarch),
37c4d197 1032 regs_base + SIGCONTEXT_HI);
f57d151a 1033 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1034 regs->lo + gdbarch_num_regs (gdbarch),
37c4d197 1035 regs_base + SIGCONTEXT_LO);
d0e64392
MR		 1036
1037 if (regs->dspacc != -1)
1038 {
1039 trad_frame_set_reg_addr (this_cache,
1040 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1041 sigcontext_base + SIGCONTEXT_HI1);
1042 trad_frame_set_reg_addr (this_cache,
1043 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1044 sigcontext_base + SIGCONTEXT_LO1);
1045 trad_frame_set_reg_addr (this_cache,
1046 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1047 sigcontext_base + SIGCONTEXT_HI2);
1048 trad_frame_set_reg_addr (this_cache,
1049 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1050 sigcontext_base + SIGCONTEXT_LO2);
1051 trad_frame_set_reg_addr (this_cache,
1052 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1053 sigcontext_base + SIGCONTEXT_HI3);
1054 trad_frame_set_reg_addr (this_cache,
1055 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1056 sigcontext_base + SIGCONTEXT_LO3);
1057 }
1058 else
1059 {
1060 trad_frame_set_reg_addr (this_cache,
1061 regs->cause + gdbarch_num_regs (gdbarch),
1062 sigcontext_base + SIGCONTEXT_CAUSE);
1063 trad_frame_set_reg_addr (this_cache,
1064 regs->badvaddr + gdbarch_num_regs (gdbarch),
1065 sigcontext_base + SIGCONTEXT_BADVADDR);
1066 }
5792a79b
DJ		 1067
1068 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1069 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1070}
1071
1072/* *INDENT-OFF* */
1073/* For N32/N64 things look different. There is no non-rt signal frame.
1074
1075 struct rt_sigframe_n32 {
1076 u32 rs_ass[4]; [ argument save space for o32 ]
eb195664 1077 u32 rs_code[2]; [ signal trampoline or fill ]
5792a79b
DJ		 1078 struct siginfo rs_info;
1079 struct ucontextn32 rs_uc;
1080 };
1081
1082 struct ucontextn32 {
1083 u32 uc_flags;
1084 s32 uc_link;
1085 stack32_t uc_stack;
1086 struct sigcontext uc_mcontext;
1087 sigset_t uc_sigmask; [ mask last for extensibility ]
1088 };
295093a4 1089
e741f4d4 1090 struct rt_sigframe {
5792a79b
DJ		 1091 u32 rs_ass[4]; [ argument save space for o32 ]
1092 u32 rs_code[2]; [ signal trampoline ]
1093 struct siginfo rs_info;
1094 struct ucontext rs_uc;
1095 };
1096
1097 struct ucontext {
1098 unsigned long uc_flags;
1099 struct ucontext *uc_link;
1100 stack_t uc_stack;
1101 struct sigcontext uc_mcontext;
1102 sigset_t uc_sigmask; [ mask last for extensibility ]
1103 };
1104
1105 And the sigcontext is different (this is for both n32 and n64):
1106
1107 struct sigcontext {
1108 unsigned long long sc_regs[32];
1109 unsigned long long sc_fpregs[32];
1110 unsigned long long sc_mdhi;
e741f4d4
DJ		 1111 unsigned long long sc_hi1;
1112 unsigned long long sc_hi2;
1113 unsigned long long sc_hi3;
5792a79b 1114 unsigned long long sc_mdlo;
e741f4d4
DJ		 1115 unsigned long long sc_lo1;
1116 unsigned long long sc_lo2;
1117 unsigned long long sc_lo3;
5792a79b 1118 unsigned long long sc_pc;
5792a79b 1119 unsigned int sc_fpc_csr;
5792a79b 1120 unsigned int sc_used_math;
e741f4d4
DJ		 1121 unsigned int sc_dsp;
1122 unsigned int sc_reserved;
1123 };
1124
1125 That is the post-2.6.12 definition of the 64-bit sigcontext; before
1126 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
1127 included too. */
5792a79b
DJ		 1128/* *INDENT-ON* */
1129
1130#define N32_STACK_T_SIZE STACK_T_SIZE
1131#define N64_STACK_T_SIZE (2 * 8 + 4)
1132#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1133#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1134#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1135 + RTSIGFRAME_SIGINFO_SIZE \
1136 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1137#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1138 + RTSIGFRAME_SIGINFO_SIZE \
1139 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1140
1141#define N64_SIGCONTEXT_REGS (0 * 8)
1142#define N64_SIGCONTEXT_FPREGS (32 * 8)
1143#define N64_SIGCONTEXT_HI (64 * 8)
d0e64392
MR		 1144#define N64_SIGCONTEXT_HI1 (65 * 8)
1145#define N64_SIGCONTEXT_HI2 (66 * 8)
1146#define N64_SIGCONTEXT_HI3 (67 * 8)
e741f4d4 1147#define N64_SIGCONTEXT_LO (68 * 8)
d0e64392
MR		 1148#define N64_SIGCONTEXT_LO1 (69 * 8)
1149#define N64_SIGCONTEXT_LO2 (70 * 8)
1150#define N64_SIGCONTEXT_LO3 (71 * 8)
e741f4d4 1151#define N64_SIGCONTEXT_PC (72 * 8)
d0e64392
MR		 1152#define N64_SIGCONTEXT_FPCSR (73 * 8 + 0)
1153#define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0)
5792a79b
DJ		 1154
1155#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1156
5792a79b
DJ		 1157static void
1158mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 1159 struct frame_info *this_frame,
5792a79b
DJ		 1160 struct trad_frame_cache *this_cache,
1161 CORE_ADDR func)
1162{
b8a22b94 1163 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1164 int ireg;
eb195664
DD		 1165 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1166 CORE_ADDR sigcontext_base;
2eb4d78b 1167 const struct mips_regnum *regs = mips_regnum (gdbarch);
5792a79b 1168
858339f2
MR		 1169 if (self == &mips_linux_n32_rt_sigframe
1170 || self == &micromips_linux_n32_rt_sigframe)
eb195664 1171 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1172 else
eb195664 1173 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1174
2eb4d78b 1175 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1176 trad_frame_set_reg_addr (this_cache,
1177 (MIPS_RESTART_REGNUM
2eb4d78b 1178 + gdbarch_num_regs (gdbarch)),
822b6570 1179 sigcontext_base + N64_SIGCONTEXT_REGS);
5792a79b
DJ		 1180
1181 for (ireg = 1; ireg < 32; ireg++)
295093a4 1182 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1183 (ireg + MIPS_ZERO_REGNUM
1184 + gdbarch_num_regs (gdbarch)),
1185 (sigcontext_base + N64_SIGCONTEXT_REGS
1186 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b
DJ		 1187
1188 for (ireg = 0; ireg < 32; ireg++)
f57d151a 1189 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1190 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1191 (sigcontext_base + N64_SIGCONTEXT_FPREGS
1192 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b 1193
f57d151a 1194 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1195 regs->pc + gdbarch_num_regs (gdbarch),
5792a79b
DJ		 1196 sigcontext_base + N64_SIGCONTEXT_PC);
1197
295093a4 1198 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1199 (regs->fp_control_status
1200 + gdbarch_num_regs (gdbarch)),
5792a79b 1201 sigcontext_base + N64_SIGCONTEXT_FPCSR);
d0e64392 1202
f57d151a 1203 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1204 regs->hi + gdbarch_num_regs (gdbarch),
5792a79b 1205 sigcontext_base + N64_SIGCONTEXT_HI);
f57d151a 1206 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1207 regs->lo + gdbarch_num_regs (gdbarch),
5792a79b 1208 sigcontext_base + N64_SIGCONTEXT_LO);
5792a79b 1209
d0e64392
MR		 1210 if (regs->dspacc != -1)
1211 {
1212 trad_frame_set_reg_addr (this_cache,
1213 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1214 sigcontext_base + N64_SIGCONTEXT_HI1);
1215 trad_frame_set_reg_addr (this_cache,
1216 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1217 sigcontext_base + N64_SIGCONTEXT_LO1);
1218 trad_frame_set_reg_addr (this_cache,
1219 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1220 sigcontext_base + N64_SIGCONTEXT_HI2);
1221 trad_frame_set_reg_addr (this_cache,
1222 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1223 sigcontext_base + N64_SIGCONTEXT_LO2);
1224 trad_frame_set_reg_addr (this_cache,
1225 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1226 sigcontext_base + N64_SIGCONTEXT_HI3);
1227 trad_frame_set_reg_addr (this_cache,
1228 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1229 sigcontext_base + N64_SIGCONTEXT_LO3);
1230 }
1231 if (regs->dspctl != -1)
1232 trad_frame_set_reg_addr (this_cache,
1233 regs->dspctl + gdbarch_num_regs (gdbarch),
1234 sigcontext_base + N64_SIGCONTEXT_DSPCTL);
1235
5792a79b 1236 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1237 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1238}
1239
858339f2
MR		 1240/* Implement struct tramp_frame's "validate" method for standard MIPS code. */
1241
1242static int
1243mips_linux_sigframe_validate (const struct tramp_frame *self,
1244 struct frame_info *this_frame,
1245 CORE_ADDR *pc)
1246{
1247 return mips_pc_is_mips (*pc);
1248}
1249
1250/* Implement struct tramp_frame's "validate" method for microMIPS code. */
1251
1252static int
1253micromips_linux_sigframe_validate (const struct tramp_frame *self,
1254 struct frame_info *this_frame,
1255 CORE_ADDR *pc)
1256{
3e29f34a
MR		 1257 if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc))
1258 {
1259 *pc = mips_unmake_compact_addr (*pc);
1260 return 1;
1261 }
1262 else
1263 return 0;
858339f2
MR		 1264}
1265
5a439849
MR		 1266/* Implement the "write_pc" gdbarch method. */
1267
822b6570 1268static void
61a1198a 1269mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
822b6570 1270{
ac7936df 1271 struct gdbarch *gdbarch = regcache->arch ();
5a439849
MR		 1272
1273 mips_write_pc (regcache, pc);
822b6570
DJ		 1274
1275 /* Clear the syscall restart flag. */
2eb4d78b 1276 if (mips_linux_restart_reg_p (gdbarch))
61a1198a 1277 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
822b6570
DJ		 1278}
1279
1280/* Return 1 if MIPS_RESTART_REGNUM is usable. */
1281
1282int
1283mips_linux_restart_reg_p (struct gdbarch *gdbarch)
1284{
1285 /* If we do not have a target description with registers, then
1286 MIPS_RESTART_REGNUM will not be included in the register set. */
1287 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
1288 return 0;
1289
1290 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
1291 either be GPR-sized or missing. */
1292 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
1293}
9f62d0e2 1294
e38d4e1a
DJ		 1295/* When FRAME is at a syscall instruction, return the PC of the next
1296 instruction to be executed. */
1297
63807e1d 1298static CORE_ADDR
e38d4e1a
DJ		 1299mips_linux_syscall_next_pc (struct frame_info *frame)
1300{
1301 CORE_ADDR pc = get_frame_pc (frame);
1302 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
1303
1304 /* If we are about to make a sigreturn syscall, use the unwinder to
1305 decode the signal frame. */
1306 if (v0 == MIPS_NR_sigreturn
1307 || v0 == MIPS_NR_rt_sigreturn
1308 || v0 == MIPS_NR_N64_rt_sigreturn
1309 || v0 == MIPS_NR_N32_rt_sigreturn)
c7ce8faa 1310 return frame_unwind_caller_pc (get_current_frame ());
e38d4e1a
DJ		 1311
1312 return pc + 4;
1313}
1314
385203ed
DD		 1315/* Return the current system call's number present in the
1316 v0 register. When the function fails, it returns -1. */
1317
1318static LONGEST
1319mips_linux_get_syscall_number (struct gdbarch *gdbarch,
1320 ptid_t ptid)
1321{
1322 struct regcache *regcache = get_thread_regcache (ptid);
1323 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1324 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1325 int regsize = register_size (gdbarch, MIPS_V0_REGNUM);
1326 /* The content of a register */
1327 gdb_byte buf[8];
1328 /* The result */
1329 LONGEST ret;
1330
1331 /* Make sure we're in a known ABI */
1332 gdb_assert (tdep->mips_abi == MIPS_ABI_O32
1333 || tdep->mips_abi == MIPS_ABI_N32
1334 || tdep->mips_abi == MIPS_ABI_N64);
1335
1336 gdb_assert (regsize <= sizeof (buf));
1337
1338 /* Getting the system call number from the register.
1339 syscall number is in v0 or $2. */
1340 regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf);
1341
1342 ret = extract_signed_integer (buf, regsize, byte_order);
1343
1344 return ret;
1345}
1346
eb14d406
SDJ		 1347/* Implementation of `gdbarch_gdb_signal_to_target', as defined in
1348 gdbarch.h. */
1349
1350static int
1351mips_gdb_signal_to_target (struct gdbarch *gdbarch,
1352 enum gdb_signal signal)
1353{
1354 switch (signal)
1355 {
1356 case GDB_SIGNAL_EMT:
1357 return MIPS_LINUX_SIGEMT;
1358
1359 case GDB_SIGNAL_BUS:
1360 return MIPS_LINUX_SIGBUS;
1361
1362 case GDB_SIGNAL_SYS:
1363 return MIPS_LINUX_SIGSYS;
1364
1365 case GDB_SIGNAL_USR1:
1366 return MIPS_LINUX_SIGUSR1;
1367
1368 case GDB_SIGNAL_USR2:
1369 return MIPS_LINUX_SIGUSR2;
1370
1371 case GDB_SIGNAL_CHLD:
1372 return MIPS_LINUX_SIGCHLD;
1373
1374 case GDB_SIGNAL_PWR:
1375 return MIPS_LINUX_SIGPWR;
1376
1377 case GDB_SIGNAL_WINCH:
1378 return MIPS_LINUX_SIGWINCH;
1379
1380 case GDB_SIGNAL_URG:
1381 return MIPS_LINUX_SIGURG;
1382
1383 case GDB_SIGNAL_IO:
1384 return MIPS_LINUX_SIGIO;
1385
1386 case GDB_SIGNAL_POLL:
1387 return MIPS_LINUX_SIGPOLL;
1388
1389 case GDB_SIGNAL_STOP:
1390 return MIPS_LINUX_SIGSTOP;
1391
1392 case GDB_SIGNAL_TSTP:
1393 return MIPS_LINUX_SIGTSTP;
1394
1395 case GDB_SIGNAL_CONT:
1396 return MIPS_LINUX_SIGCONT;
1397
1398 case GDB_SIGNAL_TTIN:
1399 return MIPS_LINUX_SIGTTIN;
1400
1401 case GDB_SIGNAL_TTOU:
1402 return MIPS_LINUX_SIGTTOU;
1403
1404 case GDB_SIGNAL_VTALRM:
1405 return MIPS_LINUX_SIGVTALRM;
1406
1407 case GDB_SIGNAL_PROF:
1408 return MIPS_LINUX_SIGPROF;
1409
1410 case GDB_SIGNAL_XCPU:
1411 return MIPS_LINUX_SIGXCPU;
1412
1413 case GDB_SIGNAL_XFSZ:
1414 return MIPS_LINUX_SIGXFSZ;
1415
1416 /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>,
1417 therefore we have to handle it here. */
1418 case GDB_SIGNAL_REALTIME_32:
1419 return MIPS_LINUX_SIGRTMIN;
1420 }
1421
1422 if (signal >= GDB_SIGNAL_REALTIME_33
1423 && signal <= GDB_SIGNAL_REALTIME_63)
1424 {
1425 int offset = signal - GDB_SIGNAL_REALTIME_33;
1426
1427 return MIPS_LINUX_SIGRTMIN + 1 + offset;
1428 }
1429 else if (signal >= GDB_SIGNAL_REALTIME_64
1430 && signal <= GDB_SIGNAL_REALTIME_127)
1431 {
1432 int offset = signal - GDB_SIGNAL_REALTIME_64;
1433
1434 return MIPS_LINUX_SIGRT64 + offset;
1435 }
1436
1437 return linux_gdb_signal_to_target (gdbarch, signal);
1438}
1439
7d266584 1440/* Translate signals based on MIPS signal values.
232b8704
ME		 1441 Adapted from gdb/common/signals.c. */
1442
1443static enum gdb_signal
eb14d406 1444mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal)
232b8704 1445{
eb14d406 1446 switch (signal)
232b8704 1447 {
eb14d406 1448 case MIPS_LINUX_SIGEMT:
232b8704 1449 return GDB_SIGNAL_EMT;
eb14d406
SDJ		 1450
1451 case MIPS_LINUX_SIGBUS:
232b8704 1452 return GDB_SIGNAL_BUS;
eb14d406
SDJ		 1453
1454 case MIPS_LINUX_SIGSYS:
232b8704 1455 return GDB_SIGNAL_SYS;
eb14d406
SDJ		 1456
1457 case MIPS_LINUX_SIGUSR1:
232b8704 1458 return GDB_SIGNAL_USR1;
eb14d406
SDJ		 1459
1460 case MIPS_LINUX_SIGUSR2:
232b8704 1461 return GDB_SIGNAL_USR2;
eb14d406
SDJ		 1462
1463 case MIPS_LINUX_SIGCHLD:
232b8704 1464 return GDB_SIGNAL_CHLD;
eb14d406
SDJ		 1465
1466 case MIPS_LINUX_SIGPWR:
232b8704 1467 return GDB_SIGNAL_PWR;
eb14d406
SDJ		 1468
1469 case MIPS_LINUX_SIGWINCH:
232b8704 1470 return GDB_SIGNAL_WINCH;
eb14d406
SDJ		 1471
1472 case MIPS_LINUX_SIGURG:
232b8704 1473 return GDB_SIGNAL_URG;
eb14d406
SDJ		 1474
1475 /* No way to differentiate between SIGIO and SIGPOLL.
1476 Therefore, we just handle the first one. */
1477 case MIPS_LINUX_SIGIO:
1478 return GDB_SIGNAL_IO;
1479
1480 case MIPS_LINUX_SIGSTOP:
232b8704 1481 return GDB_SIGNAL_STOP;
eb14d406
SDJ		 1482
1483 case MIPS_LINUX_SIGTSTP:
232b8704 1484 return GDB_SIGNAL_TSTP;
eb14d406
SDJ		 1485
1486 case MIPS_LINUX_SIGCONT:
232b8704 1487 return GDB_SIGNAL_CONT;
eb14d406
SDJ		 1488
1489 case MIPS_LINUX_SIGTTIN:
232b8704 1490 return GDB_SIGNAL_TTIN;
eb14d406
SDJ		 1491
1492 case MIPS_LINUX_SIGTTOU:
232b8704 1493 return GDB_SIGNAL_TTOU;
eb14d406
SDJ		 1494
1495 case MIPS_LINUX_SIGVTALRM:
232b8704 1496 return GDB_SIGNAL_VTALRM;
eb14d406
SDJ		 1497
1498 case MIPS_LINUX_SIGPROF:
232b8704 1499 return GDB_SIGNAL_PROF;
eb14d406
SDJ		 1500
1501 case MIPS_LINUX_SIGXCPU:
232b8704 1502 return GDB_SIGNAL_XCPU;
eb14d406
SDJ		 1503
1504 case MIPS_LINUX_SIGXFSZ:
232b8704 1505 return GDB_SIGNAL_XFSZ;
eb14d406 1506 }
232b8704 1507
eb14d406 1508 if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX)
232b8704
ME		 1509 {
1510 /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of
1511 the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */
eb14d406
SDJ		 1512 int offset = signal - MIPS_LINUX_SIGRTMIN;
1513
1514 if (offset == 0)
232b8704 1515 return GDB_SIGNAL_REALTIME_32;
eb14d406
SDJ		 1516 else if (offset < 32)
1517 return (enum gdb_signal) (offset - 1
1518 + (int) GDB_SIGNAL_REALTIME_33);
232b8704 1519 else
eb14d406
SDJ		 1520 return (enum gdb_signal) (offset - 32
1521 + (int) GDB_SIGNAL_REALTIME_64);
232b8704
ME		 1522 }
1523
eb14d406 1524 return linux_gdb_signal_from_target (gdbarch, signal);
232b8704
ME		 1525}
1526
5792a79b
DJ		 1527/* Initialize one of the GNU/Linux OS ABIs. */
1528
19ed69dd 1529static void
295093a4
MS		 1530mips_linux_init_abi (struct gdbarch_info info,
1531 struct gdbarch *gdbarch)
19ed69dd 1532{
96f026fc
KB		 1533 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1534 enum mips_abi abi = mips_abi (gdbarch);
0dba2a6c 1535 struct tdesc_arch_data *tdesc_data = info.tdesc_data;
96f026fc 1536
a5ee0f0c
PA		 1537 linux_init_abi (info, gdbarch);
1538
385203ed
DD		 1539 /* Get the syscall number from the arch's register. */
1540 set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number);
1541
96f026fc
KB		 1542 switch (abi)
1543 {
1544 case MIPS_ABI_O32:
1545 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1546 mips_linux_get_longjmp_target);
96f026fc 1547 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1548 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
858339f2
MR		 1549 tramp_frame_prepend_unwinder (gdbarch, &micromips_linux_o32_sigframe);
1550 tramp_frame_prepend_unwinder (gdbarch,
1551 &micromips_linux_o32_rt_sigframe);
fb2be677
AC		 1552 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1553 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
458c8db8 1554 set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml");
96f026fc
KB		 1555 break;
1556 case MIPS_ABI_N32:
1557 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1558 mips_linux_get_longjmp_target);
96f026fc 1559 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1560 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
d05f6826
DJ		 1561 set_gdbarch_long_double_bit (gdbarch, 128);
1562 /* These floatformats should probably be renamed. MIPS uses
1563 the same 128-bit IEEE floating point format that IA-64 uses,
1564 except that the quiet/signalling NaN bit is reversed (GDB
1565 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1566 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
858339f2
MR		 1567 tramp_frame_prepend_unwinder (gdbarch,
1568 &micromips_linux_n32_rt_sigframe);
fb2be677 1569 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
458c8db8 1570 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml");
96f026fc
KB		 1571 break;
1572 case MIPS_ABI_N64:
1573 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1574 mips64_linux_get_longjmp_target);
96f026fc 1575 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1576 (gdbarch, svr4_lp64_fetch_link_map_offsets);
d05f6826
DJ		 1577 set_gdbarch_long_double_bit (gdbarch, 128);
1578 /* These floatformats should probably be renamed. MIPS uses
1579 the same 128-bit IEEE floating point format that IA-64 uses,
1580 except that the quiet/signalling NaN bit is reversed (GDB
1581 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1582 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
858339f2
MR		 1583 tramp_frame_prepend_unwinder (gdbarch,
1584 &micromips_linux_n64_rt_sigframe);
fb2be677 1585 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
458c8db8 1586 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml");
96f026fc
KB		 1587 break;
1588 default:
96f026fc
KB		 1589 break;
1590 }
6de918a6
DJ		 1591
1592 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1593
0d0266c6 1594 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1595
1596 /* Enable TLS support. */
1597 set_gdbarch_fetch_tls_load_module_address (gdbarch,
7d266584 1598 svr4_fetch_objfile_link_map);
7d522c90
DJ		 1599
1600 /* Initialize this lazily, to avoid an initialization order
1601 dependency on solib-svr4.c's _initialize routine. */
1602 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
1603 {
1604 mips_svr4_so_ops = svr4_so_ops;
1605 mips_svr4_so_ops.in_dynsym_resolve_code
1606 = mips_linux_in_dynsym_resolve_code;
1607 }
1608 set_solib_ops (gdbarch, &mips_svr4_so_ops);
822b6570
DJ		 1609
1610 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
1611
4eb0ad19
DJ		 1612 set_gdbarch_core_read_description (gdbarch,
1613 mips_linux_core_read_description);
1614
d4036235
AA		 1615 set_gdbarch_iterate_over_regset_sections
1616 (gdbarch, mips_linux_iterate_over_regset_sections);
50e8a0d5 1617
232b8704
ME		 1618 set_gdbarch_gdb_signal_from_target (gdbarch,
1619 mips_gdb_signal_from_target);
1620
eb14d406
SDJ		 1621 set_gdbarch_gdb_signal_to_target (gdbarch,
1622 mips_gdb_signal_to_target);
1623
e38d4e1a
DJ		 1624 tdep->syscall_next_pc = mips_linux_syscall_next_pc;
1625
822b6570
DJ		 1626 if (tdesc_data)
1627 {
1628 const struct tdesc_feature *feature;
1629
1630 /* If we have target-described registers, then we can safely
1631 reserve a number for MIPS_RESTART_REGNUM (whether it is
1632 described or not). */
1633 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
1634 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
cf233303 1635 set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
822b6570
DJ		 1636
1637 /* If it's present, then assign it to the reserved number. */
1638 feature = tdesc_find_feature (info.target_desc,
1639 "org.gnu.gdb.mips.linux");
1640 if (feature != NULL)
1641 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
1642 "restart");
1643 }
19ed69dd
KB		 1644}
1645
2aa830e4 1646void
d1bacddc 1647_initialize_mips_linux_tdep (void)
2aa830e4 1648{
96f026fc
KB		 1649 const struct bfd_arch_info *arch_info;
1650
96f026fc
KB		 1651 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1652 arch_info != NULL;
1653 arch_info = arch_info->next)
1654 {
295093a4
MS		 1655 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1656 GDB_OSABI_LINUX,
96f026fc
KB		 1657 mips_linux_init_abi);
1658 }
032bb6ea
YQ		 1659
1660 /* Initialize the standard target descriptions. */
1661 initialize_tdesc_mips_linux ();
1662 initialize_tdesc_mips_dsp_linux ();
1663 initialize_tdesc_mips64_linux ();
1664 initialize_tdesc_mips64_dsp_linux ();
2aa830e4 1665}
GDB Binutils - Deliverables
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