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Remove unnecessary XMALLOC definitions.
[deliverable/binutils-gdb.git] / gdb / mips-linux-tdep.c
CommitLineData
75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
28e7fd62 3 Copyright (C) 2001-2013 Free Software Foundation, Inc.
2aa830e4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ		 19
20#include "defs.h"
21#include "gdbcore.h"
22#include "target.h"
23#include "solib-svr4.h"
19ed69dd 24#include "osabi.h"
96f026fc 25#include "mips-tdep.h"
19ed69dd 26#include "gdb_string.h"
96f026fc 27#include "gdb_assert.h"
6de918a6 28#include "frame.h"
2fdf551c 29#include "regcache.h"
5792a79b
DJ		 30#include "trad-frame.h"
31#include "tramp-frame.h"
e6bb342a 32#include "gdbtypes.h"
3e5d3a5a 33#include "objfiles.h"
5ea03926 34#include "solib.h"
7d522c90
DJ		 35#include "solib-svr4.h"
36#include "solist.h"
982e9687 37#include "symtab.h"
822b6570 38#include "target-descriptions.h"
50e8a0d5 39#include "regset.h"
d37eb719 40#include "mips-linux-tdep.h"
db5f024e 41#include "glibc-tdep.h"
a5ee0f0c 42#include "linux-tdep.h"
385203ed 43#include "xml-syscall.h"
232b8704 44#include "gdb_signals.h"
2aa830e4 45
7d522c90
DJ		 46static struct target_so_ops mips_svr4_so_ops;
47
2aa830e4 48/* Figure out where the longjmp will land.
295093a4
MS		 49 We expect the first arg to be a pointer to the jmp_buf structure
50 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
51 at. The pc is copied into PC. This routine returns 1 on
52 success. */
2aa830e4 53
19ed69dd
KB		 54#define MIPS_LINUX_JB_ELEMENT_SIZE 4
55#define MIPS_LINUX_JB_PC 0
56
57static int
60ade65d 58mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2aa830e4
DJ		 59{
60 CORE_ADDR jb_addr;
2eb4d78b 61 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 62 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e362b510 63 gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
2aa830e4 64
60ade65d 65 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
2aa830e4 66
7d266584
MR		 67 if (target_read_memory ((jb_addr
68 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE),
2eb4d78b 69 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
2aa830e4
DJ		 70 return 0;
71
819844ad 72 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 73 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
74 byte_order);
2aa830e4
DJ		 75
76 return 1;
77}
78
4246e332 79/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 80 for regcache_raw_supply(). This is needed when mips_isa_regsize()
81 is 8. */
96f026fc
KB		 82
83static void
28f5035f 84supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
96f026fc 85{
e17a4113
UW		 86 struct gdbarch *gdbarch = get_regcache_arch (regcache);
87 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d37eb719 88 gdb_byte buf[MAX_REGISTER_SIZE];
e17a4113 89 store_signed_integer (buf, register_size (gdbarch, regnum), byte_order,
7d266584 90 extract_signed_integer (addr, 4, byte_order));
28f5035f 91 regcache_raw_supply (regcache, regnum, buf);
96f026fc
KB		 92}
93
2aa830e4
DJ		 94/* Unpack an elf_gregset_t into GDB's register cache. */
95
d37eb719 96void
28f5035f
UW		 97mips_supply_gregset (struct regcache *regcache,
98 const mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 99{
100 int regi;
28f5035f 101 const mips_elf_greg_t *regp = *gregsetp;
d9d9c31f 102 char zerobuf[MAX_REGISTER_SIZE];
2eb4d78b 103 struct gdbarch *gdbarch = get_regcache_arch (regcache);
bf072999 104
d9d9c31f 105 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4 106
822b6570 107 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++)
28f5035f 108 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
2aa830e4 109
2eb4d78b 110 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 111 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0);
112
2eb4d78b
UW		 113 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO);
114 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI);
56cea623 115
2eb4d78b 116 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 117 regp + EF_CP0_EPC);
2eb4d78b 118 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 119 regp + EF_CP0_BADVADDR);
120 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
2eb4d78b 121 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 122 regp + EF_CP0_CAUSE);
2aa830e4 123
1faeff08 124 /* Fill the inaccessible zero register with zero. */
822b6570 125 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
2aa830e4
DJ		 126}
127
50e8a0d5
HZ		 128static void
129mips_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 130 struct regcache *regcache,
131 int regnum, const void *gregs, size_t len)
50e8a0d5
HZ		 132{
133 gdb_assert (len == sizeof (mips_elf_gregset_t));
134
135 mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs);
136}
137
2aa830e4
DJ		 138/* Pack our registers (or one register) into an elf_gregset_t. */
139
d37eb719 140void
28f5035f
UW		 141mips_fill_gregset (const struct regcache *regcache,
142 mips_elf_gregset_t *gregsetp, int regno)
2aa830e4 143{
2eb4d78b 144 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2aa830e4 145 int regaddr, regi;
d37eb719 146 mips_elf_greg_t *regp = *gregsetp;
96f026fc 147 void *dst;
2aa830e4
DJ		 148
149 if (regno == -1)
150 {
d37eb719 151 memset (regp, 0, sizeof (mips_elf_gregset_t));
822b6570 152 for (regi = 1; regi < 32; regi++)
28f5035f 153 mips_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 154 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
155 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
156 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
157 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
28f5035f 158 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 159 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 160 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
2aa830e4
DJ		 161 return;
162 }
163
822b6570 164 if (regno > 0 && regno < 32)
2aa830e4 165 {
2aa830e4 166 dst = regp + regno + EF_REG0;
28f5035f 167 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 168 return;
169 }
170
2eb4d78b
UW		 171 if (regno == mips_regnum (gdbarch)->lo)
172 regaddr = EF_LO;
173 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 174 regaddr = EF_HI;
2eb4d78b 175 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 176 regaddr = EF_CP0_EPC;
2eb4d78b 177 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 178 regaddr = EF_CP0_BADVADDR;
24e05951 179 else if (regno == MIPS_PS_REGNUM)
56cea623 180 regaddr = EF_CP0_STATUS;
2eb4d78b 181 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 182 regaddr = EF_CP0_CAUSE;
2eb4d78b 183 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 184 && regno == MIPS_RESTART_REGNUM)
185 regaddr = EF_REG0;
56cea623
AC		 186 else
187 regaddr = -1;
2aa830e4
DJ		 188
189 if (regaddr != -1)
190 {
2aa830e4 191 dst = regp + regaddr;
28f5035f 192 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 193 }
194}
195
50e8a0d5
HZ		 196static void
197mips_fill_gregset_wrapper (const struct regset *regset,
198 const struct regcache *regcache,
199 int regnum, void *gregs, size_t len)
200{
201 gdb_assert (len == sizeof (mips_elf_gregset_t));
202
203 mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum);
204}
205
2aa830e4
DJ		 206/* Likewise, unpack an elf_fpregset_t. */
207
d37eb719 208void
28f5035f
UW		 209mips_supply_fpregset (struct regcache *regcache,
210 const mips_elf_fpregset_t *fpregsetp)
2aa830e4 211{
2eb4d78b 212 struct gdbarch *gdbarch = get_regcache_arch (regcache);
52f0bd74 213 int regi;
d9d9c31f 214 char zerobuf[MAX_REGISTER_SIZE];
bf072999 215
d9d9c31f 216 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 217
218 for (regi = 0; regi < 32; regi++)
3e8c568d 219 regcache_raw_supply (regcache,
2eb4d78b 220 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 221 *fpregsetp + regi);
2aa830e4 222
28f5035f 223 regcache_raw_supply (regcache,
2eb4d78b 224 mips_regnum (gdbarch)->fp_control_status,
28f5035f 225 *fpregsetp + 32);
2aa830e4 226
295093a4 227 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
28f5035f 228 regcache_raw_supply (regcache,
2eb4d78b 229 mips_regnum (gdbarch)->fp_implementation_revision,
23a6d369 230 zerobuf);
2aa830e4
DJ		 231}
232
50e8a0d5
HZ		 233static void
234mips_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 235 struct regcache *regcache,
236 int regnum, const void *gregs, size_t len)
50e8a0d5
HZ		 237{
238 gdb_assert (len == sizeof (mips_elf_fpregset_t));
239
240 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs);
241}
242
2aa830e4
DJ		 243/* Likewise, pack one or all floating point registers into an
244 elf_fpregset_t. */
245
d37eb719 246void
28f5035f
UW		 247mips_fill_fpregset (const struct regcache *regcache,
248 mips_elf_fpregset_t *fpregsetp, int regno)
2aa830e4 249{
2eb4d78b 250 struct gdbarch *gdbarch = get_regcache_arch (regcache);
22e048c9 251 char *to;
2aa830e4 252
2eb4d78b
UW		 253 if ((regno >= gdbarch_fp0_regnum (gdbarch))
254 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
2aa830e4 255 {
2eb4d78b 256 to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch));
28f5035f 257 regcache_raw_collect (regcache, regno, to);
2aa830e4 258 }
2eb4d78b 259 else if (regno == mips_regnum (gdbarch)->fp_control_status)
2aa830e4 260 {
2aa830e4 261 to = (char *) (*fpregsetp + 32);
28f5035f 262 regcache_raw_collect (regcache, regno, to);
2aa830e4
DJ		 263 }
264 else if (regno == -1)
265 {
266 int regi;
267
268 for (regi = 0; regi < 32; regi++)
3e8c568d 269 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 270 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 271 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 272 mips_regnum (gdbarch)->fp_control_status);
2aa830e4
DJ		 273 }
274}
275
50e8a0d5
HZ		 276static void
277mips_fill_fpregset_wrapper (const struct regset *regset,
278 const struct regcache *regcache,
279 int regnum, void *gregs, size_t len)
280{
281 gdb_assert (len == sizeof (mips_elf_fpregset_t));
282
283 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum);
284}
285
96f026fc
KB		 286/* Support for 64-bit ABIs. */
287
96f026fc 288/* Figure out where the longjmp will land.
295093a4
MS		 289 We expect the first arg to be a pointer to the jmp_buf structure
290 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
291 at. The pc is copied into PC. This routine returns 1 on
292 success. */
96f026fc
KB		 293
294/* Details about jmp_buf. */
295
296#define MIPS64_LINUX_JB_PC 0
297
298static int
60ade65d 299mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
96f026fc
KB		 300{
301 CORE_ADDR jb_addr;
2eb4d78b 302 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 303 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2eb4d78b
UW		 304 void *buf = alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
305 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8;
96f026fc 306
60ade65d 307 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
96f026fc
KB		 308
309 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
819844ad 310 buf,
2eb4d78b 311 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
96f026fc
KB		 312 return 0;
313
819844ad 314 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 315 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
316 byte_order);
96f026fc
KB		 317
318 return 1;
319}
320
d37eb719
DJ		 321/* Register set support functions. These operate on standard 64-bit
322 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
323 target will still use the 64-bit format for PTRACE_GETREGS. */
324
325/* Supply a 64-bit register. */
96f026fc 326
63807e1d 327static void
28f5035f
UW		 328supply_64bit_reg (struct regcache *regcache, int regnum,
329 const gdb_byte *buf)
d37eb719 330{
2eb4d78b
UW		 331 struct gdbarch *gdbarch = get_regcache_arch (regcache);
332 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
333 && register_size (gdbarch, regnum) == 4)
28f5035f 334 regcache_raw_supply (regcache, regnum, buf + 4);
d37eb719 335 else
28f5035f 336 regcache_raw_supply (regcache, regnum, buf);
d37eb719
DJ		 337}
338
339/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
340
341void
28f5035f
UW		 342mips64_supply_gregset (struct regcache *regcache,
343 const mips64_elf_gregset_t *gregsetp)
96f026fc
KB		 344{
345 int regi;
28f5035f 346 const mips64_elf_greg_t *regp = *gregsetp;
d37eb719 347 gdb_byte zerobuf[MAX_REGISTER_SIZE];
2eb4d78b 348 struct gdbarch *gdbarch = get_regcache_arch (regcache);
96f026fc 349
d9d9c31f 350 memset (zerobuf, 0, MAX_REGISTER_SIZE);
96f026fc 351
822b6570 352 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++)
28f5035f 353 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
7d266584 354 (const gdb_byte *) (regp + regi));
28f5035f 355
2eb4d78b 356 if (mips_linux_restart_reg_p (gdbarch))
822b6570 357 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM,
7d266584 358 (const gdb_byte *) (regp + MIPS64_EF_REG0));
822b6570 359
2eb4d78b 360 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo,
28f5035f 361 (const gdb_byte *) (regp + MIPS64_EF_LO));
2eb4d78b 362 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi,
28f5035f
UW		 363 (const gdb_byte *) (regp + MIPS64_EF_HI));
364
2eb4d78b 365 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 366 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
2eb4d78b 367 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 368 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
369 supply_64bit_reg (regcache, MIPS_PS_REGNUM,
370 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
2eb4d78b 371 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 372 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc 373
1faeff08 374 /* Fill the inaccessible zero register with zero. */
822b6570 375 regcache_raw_supply (regcache, MIPS_ZERO_REGNUM, zerobuf);
96f026fc
KB		 376}
377
50e8a0d5
HZ		 378static void
379mips64_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 380 struct regcache *regcache,
381 int regnum, const void *gregs, size_t len)
50e8a0d5
HZ		 382{
383 gdb_assert (len == sizeof (mips64_elf_gregset_t));
384
385 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs);
386}
387
d37eb719 388/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 389
d37eb719 390void
28f5035f
UW		 391mips64_fill_gregset (const struct regcache *regcache,
392 mips64_elf_gregset_t *gregsetp, int regno)
96f026fc 393{
2eb4d78b 394 struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 395 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
96f026fc
KB		 396 int regaddr, regi;
397 mips64_elf_greg_t *regp = *gregsetp;
2ba93934 398 void *dst;
96f026fc
KB		 399
400 if (regno == -1)
401 {
402 memset (regp, 0, sizeof (mips64_elf_gregset_t));
822b6570 403 for (regi = 1; regi < 32; regi++)
7d266584 404 mips64_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 405 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
406 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
407 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
025bb325
MS		 408 mips64_fill_gregset (regcache, gregsetp,
409 mips_regnum (gdbarch)->badvaddr);
28f5035f 410 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 411 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 412 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
96f026fc
KB		 413 return;
414 }
415
822b6570 416 if (regno > 0 && regno < 32)
d37eb719 417 regaddr = regno + MIPS64_EF_REG0;
2eb4d78b 418 else if (regno == mips_regnum (gdbarch)->lo)
56cea623 419 regaddr = MIPS64_EF_LO;
2eb4d78b 420 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 421 regaddr = MIPS64_EF_HI;
2eb4d78b 422 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 423 regaddr = MIPS64_EF_CP0_EPC;
2eb4d78b 424 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 425 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 426 else if (regno == MIPS_PS_REGNUM)
56cea623 427 regaddr = MIPS64_EF_CP0_STATUS;
2eb4d78b 428 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 429 regaddr = MIPS64_EF_CP0_CAUSE;
2eb4d78b 430 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 431 && regno == MIPS_RESTART_REGNUM)
432 regaddr = MIPS64_EF_REG0;
56cea623
AC		 433 else
434 regaddr = -1;
96f026fc
KB		 435
436 if (regaddr != -1)
437 {
d37eb719
DJ		 438 gdb_byte buf[MAX_REGISTER_SIZE];
439 LONGEST val;
440
28f5035f 441 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 442 val = extract_signed_integer (buf, register_size (gdbarch, regno),
443 byte_order);
96f026fc 444 dst = regp + regaddr;
e17a4113 445 store_signed_integer (dst, 8, byte_order, val);
96f026fc
KB		 446 }
447}
448
50e8a0d5
HZ		 449static void
450mips64_fill_gregset_wrapper (const struct regset *regset,
451 const struct regcache *regcache,
452 int regnum, void *gregs, size_t len)
453{
454 gdb_assert (len == sizeof (mips64_elf_gregset_t));
455
456 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum);
457}
458
96f026fc
KB		 459/* Likewise, unpack an elf_fpregset_t. */
460
d37eb719 461void
28f5035f
UW		 462mips64_supply_fpregset (struct regcache *regcache,
463 const mips64_elf_fpregset_t *fpregsetp)
96f026fc 464{
2eb4d78b 465 struct gdbarch *gdbarch = get_regcache_arch (regcache);
52f0bd74 466 int regi;
96f026fc 467
d37eb719
DJ		 468 /* See mips_linux_o32_sigframe_init for a description of the
469 peculiar FP register layout. */
2eb4d78b 470 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4)
d37eb719
DJ		 471 for (regi = 0; regi < 32; regi++)
472 {
7d266584
MR		 473 const gdb_byte *reg_ptr
474 = (const gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 475 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 476 reg_ptr += 4;
3e8c568d 477 regcache_raw_supply (regcache,
2eb4d78b 478 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 479 reg_ptr);
d37eb719
DJ		 480 }
481 else
482 for (regi = 0; regi < 32; regi++)
3e8c568d 483 regcache_raw_supply (regcache,
2eb4d78b 484 gdbarch_fp0_regnum (gdbarch) + regi,
7d266584 485 (const char *) (*fpregsetp + regi));
d37eb719 486
2eb4d78b 487 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status,
7d266584 488 (const gdb_byte *) (*fpregsetp + 32));
d37eb719
DJ		 489
490 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
491 include it - but the result of PTRACE_GETFPREGS does. The best we
492 can do is to assume that its value is present. */
28f5035f 493 supply_32bit_reg (regcache,
2eb4d78b 494 mips_regnum (gdbarch)->fp_implementation_revision,
7d266584 495 (const gdb_byte *) (*fpregsetp + 32) + 4);
96f026fc
KB		 496}
497
50e8a0d5
HZ		 498static void
499mips64_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 500 struct regcache *regcache,
501 int regnum, const void *gregs, size_t len)
50e8a0d5
HZ		 502{
503 gdb_assert (len == sizeof (mips64_elf_fpregset_t));
504
505 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs);
506}
507
96f026fc
KB		 508/* Likewise, pack one or all floating point registers into an
509 elf_fpregset_t. */
510
d37eb719 511void
28f5035f
UW		 512mips64_fill_fpregset (const struct regcache *regcache,
513 mips64_elf_fpregset_t *fpregsetp, int regno)
96f026fc 514{
2eb4d78b 515 struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 516 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d37eb719 517 gdb_byte *to;
96f026fc 518
2eb4d78b
UW		 519 if ((regno >= gdbarch_fp0_regnum (gdbarch))
520 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
96f026fc 521 {
d37eb719
DJ		 522 /* See mips_linux_o32_sigframe_init for a description of the
523 peculiar FP register layout. */
2eb4d78b 524 if (register_size (gdbarch, regno) == 4)
d37eb719 525 {
2eb4d78b 526 int regi = regno - gdbarch_fp0_regnum (gdbarch);
d37eb719
DJ		 527
528 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 529 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 530 to += 4;
28f5035f 531 regcache_raw_collect (regcache, regno, to);
d37eb719
DJ		 532 }
533 else
534 {
025bb325
MS		 535 to = (gdb_byte *) (*fpregsetp + regno
536 - gdbarch_fp0_regnum (gdbarch));
28f5035f 537 regcache_raw_collect (regcache, regno, to);
d37eb719 538 }
96f026fc 539 }
2eb4d78b 540 else if (regno == mips_regnum (gdbarch)->fp_control_status)
96f026fc 541 {
d37eb719
DJ		 542 gdb_byte buf[MAX_REGISTER_SIZE];
543 LONGEST val;
544
28f5035f 545 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 546 val = extract_signed_integer (buf, register_size (gdbarch, regno),
547 byte_order);
d37eb719 548 to = (gdb_byte *) (*fpregsetp + 32);
e17a4113 549 store_signed_integer (to, 4, byte_order, val);
d37eb719 550 }
2eb4d78b 551 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ		 552 {
553 gdb_byte buf[MAX_REGISTER_SIZE];
554 LONGEST val;
555
28f5035f 556 regcache_raw_collect (regcache, regno, buf);
e17a4113
UW		 557 val = extract_signed_integer (buf, register_size (gdbarch, regno),
558 byte_order);
d37eb719 559 to = (gdb_byte *) (*fpregsetp + 32) + 4;
e17a4113 560 store_signed_integer (to, 4, byte_order, val);
96f026fc
KB		 561 }
562 else if (regno == -1)
563 {
564 int regi;
565
566 for (regi = 0; regi < 32; regi++)
3e8c568d 567 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 568 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 569 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 570 mips_regnum (gdbarch)->fp_control_status);
28f5035f 571 mips64_fill_fpregset (regcache, fpregsetp,
7d266584 572 mips_regnum (gdbarch)->fp_implementation_revision);
96f026fc
KB		 573 }
574}
575
50e8a0d5
HZ		 576static void
577mips64_fill_fpregset_wrapper (const struct regset *regset,
578 const struct regcache *regcache,
579 int regnum, void *gregs, size_t len)
580{
581 gdb_assert (len == sizeof (mips64_elf_fpregset_t));
96f026fc 582
50e8a0d5
HZ		 583 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum);
584}
2aa830e4 585
693be288 586static const struct regset *
50e8a0d5 587mips_linux_regset_from_core_section (struct gdbarch *gdbarch,
7d266584 588 const char *sect_name, size_t sect_size)
2aa830e4 589{
50e8a0d5 590 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
d37eb719
DJ		 591 mips_elf_gregset_t gregset;
592 mips_elf_fpregset_t fpregset;
96f026fc
KB		 593 mips64_elf_gregset_t gregset64;
594 mips64_elf_fpregset_t fpregset64;
2aa830e4 595
50e8a0d5 596 if (strcmp (sect_name, ".reg") == 0)
2aa830e4 597 {
50e8a0d5 598 if (sect_size == sizeof (gregset))
2aa830e4 599 {
50e8a0d5
HZ		 600 if (tdep->gregset == NULL)
601 tdep->gregset = regset_alloc (gdbarch,
7d266584
MR		 602 mips_supply_gregset_wrapper,
603 mips_fill_gregset_wrapper);
50e8a0d5 604 return tdep->gregset;
96f026fc 605 }
50e8a0d5 606 else if (sect_size == sizeof (gregset64))
96f026fc 607 {
50e8a0d5
HZ		 608 if (tdep->gregset64 == NULL)
609 tdep->gregset64 = regset_alloc (gdbarch,
7d266584
MR		 610 mips64_supply_gregset_wrapper,
611 mips64_fill_gregset_wrapper);
50e8a0d5 612 return tdep->gregset64;
2aa830e4
DJ		 613 }
614 else
615 {
8a3fe4f8 616 warning (_("wrong size gregset struct in core file"));
2aa830e4
DJ		 617 }
618 }
50e8a0d5 619 else if (strcmp (sect_name, ".reg2") == 0)
2aa830e4 620 {
50e8a0d5 621 if (sect_size == sizeof (fpregset))
2aa830e4 622 {
50e8a0d5
HZ		 623 if (tdep->fpregset == NULL)
624 tdep->fpregset = regset_alloc (gdbarch,
7d266584
MR		 625 mips_supply_fpregset_wrapper,
626 mips_fill_fpregset_wrapper);
50e8a0d5 627 return tdep->fpregset;
96f026fc 628 }
50e8a0d5 629 else if (sect_size == sizeof (fpregset64))
96f026fc 630 {
50e8a0d5
HZ		 631 if (tdep->fpregset64 == NULL)
632 tdep->fpregset64 = regset_alloc (gdbarch,
7d266584
MR		 633 mips64_supply_fpregset_wrapper,
634 mips64_fill_fpregset_wrapper);
50e8a0d5 635 return tdep->fpregset64;
2aa830e4
DJ		 636 }
637 else
638 {
8a3fe4f8 639 warning (_("wrong size fpregset struct in core file"));
2aa830e4
DJ		 640 }
641 }
2aa830e4 642
50e8a0d5
HZ		 643 return NULL;
644}
2aa830e4 645
4eb0ad19
DJ		 646static const struct target_desc *
647mips_linux_core_read_description (struct gdbarch *gdbarch,
648 struct target_ops *target,
649 bfd *abfd)
650{
651 asection *section = bfd_get_section_by_name (abfd, ".reg");
652 if (! section)
653 return NULL;
654
655 switch (bfd_section_size (abfd, section))
656 {
657 case sizeof (mips_elf_gregset_t):
658 return mips_tdesc_gp32;
659
660 case sizeof (mips64_elf_gregset_t):
661 return mips_tdesc_gp64;
662
663 default:
664 return NULL;
665 }
666}
667
96f026fc 668
295093a4 669/* Check the code at PC for a dynamic linker lazy resolution stub.
3e5d3a5a
MR		 670 GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs"
671 section uniformly since version 2.15. If the pc is in that section,
672 then we are in such a stub. Before that ".stub" was used in 32-bit
673 ELF binaries, however we do not bother checking for that since we
674 have never had and that case should be extremely rare these days.
675 Instead we pattern-match on the code generated by GNU ld. They look
676 like this:
6de918a6
DJ		 677
678 lw t9,0x8010(gp)
679 addu t7,ra
680 jalr t9,ra
681 addiu t8,zero,INDEX
682
3e5d3a5a
MR		 683 (with the appropriate doubleword instructions for N64). As any lazy
684 resolution stubs in microMIPS binaries will always be in a
685 ".MIPS.stubs" section we only ever verify standard MIPS patterns. */
6de918a6
DJ		 686
687static int
3e5d3a5a 688mips_linux_in_dynsym_stub (CORE_ADDR pc)
6de918a6 689{
e362b510 690 gdb_byte buf[28], *p;
6de918a6 691 ULONGEST insn, insn1;
f5656ead
TT		 692 int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64);
693 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
6de918a6 694
3e5d3a5a
MR		 695 if (in_mips_stubs_section (pc))
696 return 1;
697
6de918a6
DJ		 698 read_memory (pc - 12, buf, 28);
699
700 if (n64)
701 {
702 /* ld t9,0x8010(gp) */
703 insn1 = 0xdf998010;
704 }
705 else
706 {
707 /* lw t9,0x8010(gp) */
708 insn1 = 0x8f998010;
709 }
710
711 p = buf + 12;
712 while (p >= buf)
713 {
e17a4113 714 insn = extract_unsigned_integer (p, 4, byte_order);
6de918a6
DJ		 715 if (insn == insn1)
716 break;
717 p -= 4;
718 }
719 if (p < buf)
720 return 0;
721
e17a4113 722 insn = extract_unsigned_integer (p + 4, 4, byte_order);
6de918a6
DJ		 723 if (n64)
724 {
725 /* daddu t7,ra */
726 if (insn != 0x03e0782d)
727 return 0;
728 }
729 else
730 {
731 /* addu t7,ra */
732 if (insn != 0x03e07821)
733 return 0;
734 }
295093a4 735
e17a4113 736 insn = extract_unsigned_integer (p + 8, 4, byte_order);
6de918a6
DJ		 737 /* jalr t9,ra */
738 if (insn != 0x0320f809)
739 return 0;
740
e17a4113 741 insn = extract_unsigned_integer (p + 12, 4, byte_order);
6de918a6
DJ		 742 if (n64)
743 {
744 /* daddiu t8,zero,0 */
745 if ((insn & 0xffff0000) != 0x64180000)
746 return 0;
747 }
748 else
749 {
750 /* addiu t8,zero,0 */
751 if ((insn & 0xffff0000) != 0x24180000)
752 return 0;
753 }
754
3e5d3a5a 755 return 1;
6de918a6
DJ		 756}
757
295093a4 758/* Return non-zero iff PC belongs to the dynamic linker resolution
db5f024e 759 code, a PLT entry, or a lazy binding stub. */
6de918a6 760
7d522c90 761static int
6de918a6
DJ		 762mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
763{
295093a4 764 /* Check whether PC is in the dynamic linker. This also checks
db5f024e 765 whether it is in the .plt section, used by non-PIC executables. */
7d522c90 766 if (svr4_in_dynsym_resolve_code (pc))
6de918a6
DJ		 767 return 1;
768
3e5d3a5a
MR		 769 /* Likewise for the stubs. They live in the .MIPS.stubs section these
770 days, so we check if the PC is within, than fall back to a pattern
771 match. */
772 if (mips_linux_in_dynsym_stub (pc))
6de918a6
DJ		 773 return 1;
774
775 return 0;
776}
777
778/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
779 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
780 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba 781 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
db5f024e
DJ		 782 "__dl_runtime_resolve" directly. An unresolved lazy binding
783 stub will point to _dl_runtime_resolve, which will first call
c4c5b7ba
AC		 784 __dl_runtime_resolve, and then pass control to the resolved
785 function. */
6de918a6
DJ		 786
787static CORE_ADDR
788mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
789{
790 struct minimal_symbol *resolver;
791
792 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
793
794 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
c7ce8faa 795 return frame_unwind_caller_pc (get_current_frame ());
6de918a6 796
db5f024e 797 return glibc_skip_solib_resolver (gdbarch, pc);
295093a4 798}
6de918a6 799
5792a79b
DJ		 800/* Signal trampoline support. There are four supported layouts for a
801 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
802 n64 rt_sigframe. We handle them all independently; not the most
803 efficient way, but simplest. First, declare all the unwinders. */
804
805static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 806 struct frame_info *this_frame,
5792a79b
DJ		 807 struct trad_frame_cache *this_cache,
808 CORE_ADDR func);
809
810static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 811 struct frame_info *this_frame,
5792a79b
DJ		 812 struct trad_frame_cache *this_cache,
813 CORE_ADDR func);
814
815#define MIPS_NR_LINUX 4000
816#define MIPS_NR_N64_LINUX 5000
817#define MIPS_NR_N32_LINUX 6000
818
819#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
820#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
821#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
822#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
823
824#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
825#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
826#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
827#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
828#define MIPS_INST_SYSCALL 0x0000000c
829
2cd8546d
AC		 830static const struct tramp_frame mips_linux_o32_sigframe = {
831 SIGTRAMP_FRAME,
5792a79b 832 4,
2cd8546d
AC		 833 {
834 { MIPS_INST_LI_V0_SIGRETURN, -1 },
835 { MIPS_INST_SYSCALL, -1 },
836 { TRAMP_SENTINEL_INSN, -1 }
837 },
5792a79b
DJ		 838 mips_linux_o32_sigframe_init
839};
840
2cd8546d
AC		 841static const struct tramp_frame mips_linux_o32_rt_sigframe = {
842 SIGTRAMP_FRAME,
5792a79b 843 4,
2cd8546d
AC		 844 {
845 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
846 { MIPS_INST_SYSCALL, -1 },
847 { TRAMP_SENTINEL_INSN, -1 } },
5792a79b
DJ		 848 mips_linux_o32_sigframe_init
849};
850
2cd8546d
AC		 851static const struct tramp_frame mips_linux_n32_rt_sigframe = {
852 SIGTRAMP_FRAME,
5792a79b 853 4,
2cd8546d
AC		 854 {
855 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
856 { MIPS_INST_SYSCALL, -1 },
857 { TRAMP_SENTINEL_INSN, -1 }
858 },
5792a79b
DJ		 859 mips_linux_n32n64_sigframe_init
860};
861
2cd8546d
AC		 862static const struct tramp_frame mips_linux_n64_rt_sigframe = {
863 SIGTRAMP_FRAME,
5792a79b 864 4,
fcbd8a5c
TS		 865 {
866 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
867 { MIPS_INST_SYSCALL, -1 },
868 { TRAMP_SENTINEL_INSN, -1 }
869 },
5792a79b
DJ		 870 mips_linux_n32n64_sigframe_init
871};
872
873/* *INDENT-OFF* */
874/* The unwinder for o32 signal frames. The legacy structures look
875 like this:
876
877 struct sigframe {
878 u32 sf_ass[4]; [argument save space for o32]
eb195664 879 u32 sf_code[2]; [signal trampoline or fill]
5792a79b
DJ		 880 struct sigcontext sf_sc;
881 sigset_t sf_mask;
882 };
883
d0e64392
MR		 884 Pre-2.6.12 sigcontext:
885
5792a79b
DJ		 886 struct sigcontext {
887 unsigned int sc_regmask; [Unused]
888 unsigned int sc_status;
889 unsigned long long sc_pc;
890 unsigned long long sc_regs[32];
891 unsigned long long sc_fpregs[32];
892 unsigned int sc_ownedfp;
893 unsigned int sc_fpc_csr;
894 unsigned int sc_fpc_eir; [Unused]
895 unsigned int sc_used_math;
896 unsigned int sc_ssflags; [Unused]
897 [Alignment hole of four bytes]
898 unsigned long long sc_mdhi;
899 unsigned long long sc_mdlo;
900
901 unsigned int sc_cause; [Unused]
902 unsigned int sc_badvaddr; [Unused]
903
904 unsigned long sc_sigset[4]; [kernel's sigset_t]
905 };
906
d0e64392
MR		 907 Post-2.6.12 sigcontext (SmartMIPS/DSP support added):
908
909 struct sigcontext {
910 unsigned int sc_regmask; [Unused]
911 unsigned int sc_status; [Unused]
912 unsigned long long sc_pc;
913 unsigned long long sc_regs[32];
914 unsigned long long sc_fpregs[32];
915 unsigned int sc_acx;
916 unsigned int sc_fpc_csr;
917 unsigned int sc_fpc_eir; [Unused]
918 unsigned int sc_used_math;
919 unsigned int sc_dsp;
920 [Alignment hole of four bytes]
921 unsigned long long sc_mdhi;
922 unsigned long long sc_mdlo;
923 unsigned long sc_hi1;
924 unsigned long sc_lo1;
925 unsigned long sc_hi2;
926 unsigned long sc_lo2;
927 unsigned long sc_hi3;
928 unsigned long sc_lo3;
929 };
930
5792a79b
DJ		 931 The RT signal frames look like this:
932
933 struct rt_sigframe {
934 u32 rs_ass[4]; [argument save space for o32]
eb195664 935 u32 rs_code[2] [signal trampoline or fill]
5792a79b
DJ		 936 struct siginfo rs_info;
937 struct ucontext rs_uc;
938 };
939
940 struct ucontext {
941 unsigned long uc_flags;
942 struct ucontext *uc_link;
943 stack_t uc_stack;
944 [Alignment hole of four bytes]
945 struct sigcontext uc_mcontext;
946 sigset_t uc_sigmask;
947 }; */
948/* *INDENT-ON* */
949
5792a79b
DJ		 950#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
951
952#define RTSIGFRAME_SIGINFO_SIZE 128
953#define STACK_T_SIZE (3 * 4)
954#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
955#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
956 + RTSIGFRAME_SIGINFO_SIZE \
957 + UCONTEXT_SIGCONTEXT_OFFSET)
958
959#define SIGCONTEXT_PC (1 * 8)
960#define SIGCONTEXT_REGS (2 * 8)
961#define SIGCONTEXT_FPREGS (34 * 8)
962#define SIGCONTEXT_FPCSR (66 * 8 + 4)
d0e64392 963#define SIGCONTEXT_DSPCTL (68 * 8 + 0)
5792a79b
DJ		 964#define SIGCONTEXT_HI (69 * 8)
965#define SIGCONTEXT_LO (70 * 8)
966#define SIGCONTEXT_CAUSE (71 * 8 + 0)
967#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
d0e64392
MR		 968#define SIGCONTEXT_HI1 (71 * 8 + 0)
969#define SIGCONTEXT_LO1 (71 * 8 + 4)
970#define SIGCONTEXT_HI2 (72 * 8 + 0)
971#define SIGCONTEXT_LO2 (72 * 8 + 4)
972#define SIGCONTEXT_HI3 (73 * 8 + 0)
973#define SIGCONTEXT_LO3 (73 * 8 + 4)
5792a79b
DJ		 974
975#define SIGCONTEXT_REG_SIZE 8
976
977static void
978mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 979 struct frame_info *this_frame,
5792a79b
DJ		 980 struct trad_frame_cache *this_cache,
981 CORE_ADDR func)
982{
b8a22b94 983 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 984 int ireg;
eb195664
DD		 985 CORE_ADDR frame_sp = get_frame_sp (this_frame);
986 CORE_ADDR sigcontext_base;
2eb4d78b 987 const struct mips_regnum *regs = mips_regnum (gdbarch);
37c4d197 988 CORE_ADDR regs_base;
5792a79b
DJ		 989
990 if (self == &mips_linux_o32_sigframe)
eb195664 991 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 992 else
eb195664 993 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 994
995 /* I'm not proud of this hack. Eventually we will have the
996 infrastructure to indicate the size of saved registers on a
997 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 998 bytes but we only want four. Use regs_base to access any
999 64-bit fields. */
2eb4d78b 1000 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
37c4d197
DJ		 1001 regs_base = sigcontext_base + 4;
1002 else
1003 regs_base = sigcontext_base;
5792a79b 1004
2eb4d78b 1005 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1006 trad_frame_set_reg_addr (this_cache,
1007 (MIPS_RESTART_REGNUM
2eb4d78b 1008 + gdbarch_num_regs (gdbarch)),
822b6570 1009 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 1010
1011 for (ireg = 1; ireg < 32; ireg++)
295093a4 1012 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1013 (ireg + MIPS_ZERO_REGNUM
1014 + gdbarch_num_regs (gdbarch)),
1015 (regs_base + SIGCONTEXT_REGS
1016 + ireg * SIGCONTEXT_REG_SIZE));
5792a79b 1017
37c4d197
DJ		 1018 /* The way that floating point registers are saved, unfortunately,
1019 depends on the architecture the kernel is built for. For the r3000 and
1020 tx39, four bytes of each register are at the beginning of each of the
1021 32 eight byte slots. For everything else, the registers are saved
1022 using double precision; only the even-numbered slots are initialized,
1023 and the high bits are the odd-numbered register. Assume the latter
1024 layout, since we can't tell, and it's much more common. Which bits are
1025 the "high" bits depends on endianness. */
5792a79b 1026 for (ireg = 0; ireg < 32; ireg++)
2eb4d78b 1027 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
f57d151a 1028 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1029 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1030 (sigcontext_base + SIGCONTEXT_FPREGS + 4
1031 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
37c4d197 1032 else
f57d151a 1033 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1034 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1035 (sigcontext_base + SIGCONTEXT_FPREGS
1036 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
5792a79b 1037
f57d151a 1038 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1039 regs->pc + gdbarch_num_regs (gdbarch),
37c4d197 1040 regs_base + SIGCONTEXT_PC);
5792a79b 1041
295093a4 1042 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1043 (regs->fp_control_status
1044 + gdbarch_num_regs (gdbarch)),
5792a79b 1045 sigcontext_base + SIGCONTEXT_FPCSR);
d0e64392
MR		 1046
1047 if (regs->dspctl != -1)
1048 trad_frame_set_reg_addr (this_cache,
1049 regs->dspctl + gdbarch_num_regs (gdbarch),
1050 sigcontext_base + SIGCONTEXT_DSPCTL);
1051
f57d151a 1052 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1053 regs->hi + gdbarch_num_regs (gdbarch),
37c4d197 1054 regs_base + SIGCONTEXT_HI);
f57d151a 1055 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1056 regs->lo + gdbarch_num_regs (gdbarch),
37c4d197 1057 regs_base + SIGCONTEXT_LO);
d0e64392
MR		 1058
1059 if (regs->dspacc != -1)
1060 {
1061 trad_frame_set_reg_addr (this_cache,
1062 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1063 sigcontext_base + SIGCONTEXT_HI1);
1064 trad_frame_set_reg_addr (this_cache,
1065 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1066 sigcontext_base + SIGCONTEXT_LO1);
1067 trad_frame_set_reg_addr (this_cache,
1068 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1069 sigcontext_base + SIGCONTEXT_HI2);
1070 trad_frame_set_reg_addr (this_cache,
1071 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1072 sigcontext_base + SIGCONTEXT_LO2);
1073 trad_frame_set_reg_addr (this_cache,
1074 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1075 sigcontext_base + SIGCONTEXT_HI3);
1076 trad_frame_set_reg_addr (this_cache,
1077 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1078 sigcontext_base + SIGCONTEXT_LO3);
1079 }
1080 else
1081 {
1082 trad_frame_set_reg_addr (this_cache,
1083 regs->cause + gdbarch_num_regs (gdbarch),
1084 sigcontext_base + SIGCONTEXT_CAUSE);
1085 trad_frame_set_reg_addr (this_cache,
1086 regs->badvaddr + gdbarch_num_regs (gdbarch),
1087 sigcontext_base + SIGCONTEXT_BADVADDR);
1088 }
5792a79b
DJ		 1089
1090 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1091 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1092}
1093
1094/* *INDENT-OFF* */
1095/* For N32/N64 things look different. There is no non-rt signal frame.
1096
1097 struct rt_sigframe_n32 {
1098 u32 rs_ass[4]; [ argument save space for o32 ]
eb195664 1099 u32 rs_code[2]; [ signal trampoline or fill ]
5792a79b
DJ		 1100 struct siginfo rs_info;
1101 struct ucontextn32 rs_uc;
1102 };
1103
1104 struct ucontextn32 {
1105 u32 uc_flags;
1106 s32 uc_link;
1107 stack32_t uc_stack;
1108 struct sigcontext uc_mcontext;
1109 sigset_t uc_sigmask; [ mask last for extensibility ]
1110 };
295093a4 1111
e741f4d4 1112 struct rt_sigframe {
5792a79b
DJ		 1113 u32 rs_ass[4]; [ argument save space for o32 ]
1114 u32 rs_code[2]; [ signal trampoline ]
1115 struct siginfo rs_info;
1116 struct ucontext rs_uc;
1117 };
1118
1119 struct ucontext {
1120 unsigned long uc_flags;
1121 struct ucontext *uc_link;
1122 stack_t uc_stack;
1123 struct sigcontext uc_mcontext;
1124 sigset_t uc_sigmask; [ mask last for extensibility ]
1125 };
1126
1127 And the sigcontext is different (this is for both n32 and n64):
1128
1129 struct sigcontext {
1130 unsigned long long sc_regs[32];
1131 unsigned long long sc_fpregs[32];
1132 unsigned long long sc_mdhi;
e741f4d4
DJ		 1133 unsigned long long sc_hi1;
1134 unsigned long long sc_hi2;
1135 unsigned long long sc_hi3;
5792a79b 1136 unsigned long long sc_mdlo;
e741f4d4
DJ		 1137 unsigned long long sc_lo1;
1138 unsigned long long sc_lo2;
1139 unsigned long long sc_lo3;
5792a79b 1140 unsigned long long sc_pc;
5792a79b 1141 unsigned int sc_fpc_csr;
5792a79b 1142 unsigned int sc_used_math;
e741f4d4
DJ		 1143 unsigned int sc_dsp;
1144 unsigned int sc_reserved;
1145 };
1146
1147 That is the post-2.6.12 definition of the 64-bit sigcontext; before
1148 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
1149 included too. */
5792a79b
DJ		 1150/* *INDENT-ON* */
1151
1152#define N32_STACK_T_SIZE STACK_T_SIZE
1153#define N64_STACK_T_SIZE (2 * 8 + 4)
1154#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1155#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1156#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1157 + RTSIGFRAME_SIGINFO_SIZE \
1158 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1159#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1160 + RTSIGFRAME_SIGINFO_SIZE \
1161 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1162
1163#define N64_SIGCONTEXT_REGS (0 * 8)
1164#define N64_SIGCONTEXT_FPREGS (32 * 8)
1165#define N64_SIGCONTEXT_HI (64 * 8)
d0e64392
MR		 1166#define N64_SIGCONTEXT_HI1 (65 * 8)
1167#define N64_SIGCONTEXT_HI2 (66 * 8)
1168#define N64_SIGCONTEXT_HI3 (67 * 8)
e741f4d4 1169#define N64_SIGCONTEXT_LO (68 * 8)
d0e64392
MR		 1170#define N64_SIGCONTEXT_LO1 (69 * 8)
1171#define N64_SIGCONTEXT_LO2 (70 * 8)
1172#define N64_SIGCONTEXT_LO3 (71 * 8)
e741f4d4 1173#define N64_SIGCONTEXT_PC (72 * 8)
d0e64392
MR		 1174#define N64_SIGCONTEXT_FPCSR (73 * 8 + 0)
1175#define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0)
5792a79b
DJ		 1176
1177#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1178
5792a79b
DJ		 1179static void
1180mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 1181 struct frame_info *this_frame,
5792a79b
DJ		 1182 struct trad_frame_cache *this_cache,
1183 CORE_ADDR func)
1184{
b8a22b94 1185 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1186 int ireg;
eb195664
DD		 1187 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1188 CORE_ADDR sigcontext_base;
2eb4d78b 1189 const struct mips_regnum *regs = mips_regnum (gdbarch);
5792a79b
DJ		 1190
1191 if (self == &mips_linux_n32_rt_sigframe)
eb195664 1192 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1193 else
eb195664 1194 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1195
2eb4d78b 1196 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1197 trad_frame_set_reg_addr (this_cache,
1198 (MIPS_RESTART_REGNUM
2eb4d78b 1199 + gdbarch_num_regs (gdbarch)),
822b6570 1200 sigcontext_base + N64_SIGCONTEXT_REGS);
5792a79b
DJ		 1201
1202 for (ireg = 1; ireg < 32; ireg++)
295093a4 1203 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1204 (ireg + MIPS_ZERO_REGNUM
1205 + gdbarch_num_regs (gdbarch)),
1206 (sigcontext_base + N64_SIGCONTEXT_REGS
1207 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b
DJ		 1208
1209 for (ireg = 0; ireg < 32; ireg++)
f57d151a 1210 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1211 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1212 (sigcontext_base + N64_SIGCONTEXT_FPREGS
1213 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b 1214
f57d151a 1215 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1216 regs->pc + gdbarch_num_regs (gdbarch),
5792a79b
DJ		 1217 sigcontext_base + N64_SIGCONTEXT_PC);
1218
295093a4 1219 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1220 (regs->fp_control_status
1221 + gdbarch_num_regs (gdbarch)),
5792a79b 1222 sigcontext_base + N64_SIGCONTEXT_FPCSR);
d0e64392 1223
f57d151a 1224 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1225 regs->hi + gdbarch_num_regs (gdbarch),
5792a79b 1226 sigcontext_base + N64_SIGCONTEXT_HI);
f57d151a 1227 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1228 regs->lo + gdbarch_num_regs (gdbarch),
5792a79b 1229 sigcontext_base + N64_SIGCONTEXT_LO);
5792a79b 1230
d0e64392
MR		 1231 if (regs->dspacc != -1)
1232 {
1233 trad_frame_set_reg_addr (this_cache,
1234 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1235 sigcontext_base + N64_SIGCONTEXT_HI1);
1236 trad_frame_set_reg_addr (this_cache,
1237 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1238 sigcontext_base + N64_SIGCONTEXT_LO1);
1239 trad_frame_set_reg_addr (this_cache,
1240 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1241 sigcontext_base + N64_SIGCONTEXT_HI2);
1242 trad_frame_set_reg_addr (this_cache,
1243 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1244 sigcontext_base + N64_SIGCONTEXT_LO2);
1245 trad_frame_set_reg_addr (this_cache,
1246 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1247 sigcontext_base + N64_SIGCONTEXT_HI3);
1248 trad_frame_set_reg_addr (this_cache,
1249 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1250 sigcontext_base + N64_SIGCONTEXT_LO3);
1251 }
1252 if (regs->dspctl != -1)
1253 trad_frame_set_reg_addr (this_cache,
1254 regs->dspctl + gdbarch_num_regs (gdbarch),
1255 sigcontext_base + N64_SIGCONTEXT_DSPCTL);
1256
5792a79b 1257 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1258 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1259}
1260
5a439849
MR		 1261/* Implement the "write_pc" gdbarch method. */
1262
822b6570 1263static void
61a1198a 1264mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
822b6570 1265{
2eb4d78b 1266 struct gdbarch *gdbarch = get_regcache_arch (regcache);
5a439849
MR		 1267
1268 mips_write_pc (regcache, pc);
822b6570
DJ		 1269
1270 /* Clear the syscall restart flag. */
2eb4d78b 1271 if (mips_linux_restart_reg_p (gdbarch))
61a1198a 1272 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
822b6570
DJ		 1273}
1274
1275/* Return 1 if MIPS_RESTART_REGNUM is usable. */
1276
1277int
1278mips_linux_restart_reg_p (struct gdbarch *gdbarch)
1279{
1280 /* If we do not have a target description with registers, then
1281 MIPS_RESTART_REGNUM will not be included in the register set. */
1282 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
1283 return 0;
1284
1285 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
1286 either be GPR-sized or missing. */
1287 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
1288}
9f62d0e2 1289
e38d4e1a
DJ		 1290/* When FRAME is at a syscall instruction, return the PC of the next
1291 instruction to be executed. */
1292
63807e1d 1293static CORE_ADDR
e38d4e1a
DJ		 1294mips_linux_syscall_next_pc (struct frame_info *frame)
1295{
1296 CORE_ADDR pc = get_frame_pc (frame);
1297 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
1298
1299 /* If we are about to make a sigreturn syscall, use the unwinder to
1300 decode the signal frame. */
1301 if (v0 == MIPS_NR_sigreturn
1302 || v0 == MIPS_NR_rt_sigreturn
1303 || v0 == MIPS_NR_N64_rt_sigreturn
1304 || v0 == MIPS_NR_N32_rt_sigreturn)
c7ce8faa 1305 return frame_unwind_caller_pc (get_current_frame ());
e38d4e1a
DJ		 1306
1307 return pc + 4;
1308}
1309
385203ed
DD		 1310/* Return the current system call's number present in the
1311 v0 register. When the function fails, it returns -1. */
1312
1313static LONGEST
1314mips_linux_get_syscall_number (struct gdbarch *gdbarch,
1315 ptid_t ptid)
1316{
1317 struct regcache *regcache = get_thread_regcache (ptid);
1318 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1319 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1320 int regsize = register_size (gdbarch, MIPS_V0_REGNUM);
1321 /* The content of a register */
1322 gdb_byte buf[8];
1323 /* The result */
1324 LONGEST ret;
1325
1326 /* Make sure we're in a known ABI */
1327 gdb_assert (tdep->mips_abi == MIPS_ABI_O32
1328 || tdep->mips_abi == MIPS_ABI_N32
1329 || tdep->mips_abi == MIPS_ABI_N64);
1330
1331 gdb_assert (regsize <= sizeof (buf));
1332
1333 /* Getting the system call number from the register.
1334 syscall number is in v0 or $2. */
1335 regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf);
1336
1337 ret = extract_signed_integer (buf, regsize, byte_order);
1338
1339 return ret;
1340}
1341
7d266584 1342/* Translate signals based on MIPS signal values.
232b8704
ME		 1343 Adapted from gdb/common/signals.c. */
1344
1345static enum gdb_signal
1346mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signo)
1347{
7d266584 1348 switch (signo)
232b8704
ME		 1349 {
1350 case 0:
1351 return GDB_SIGNAL_0;
1352 case MIPS_SIGHUP:
1353 return GDB_SIGNAL_HUP;
1354 case MIPS_SIGINT:
1355 return GDB_SIGNAL_INT;
1356 case MIPS_SIGQUIT:
1357 return GDB_SIGNAL_QUIT;
1358 case MIPS_SIGILL:
1359 return GDB_SIGNAL_ILL;
1360 case MIPS_SIGTRAP:
1361 return GDB_SIGNAL_TRAP;
1362 case MIPS_SIGABRT:
1363 return GDB_SIGNAL_ABRT;
1364 case MIPS_SIGEMT:
1365 return GDB_SIGNAL_EMT;
1366 case MIPS_SIGFPE:
1367 return GDB_SIGNAL_FPE;
1368 case MIPS_SIGKILL:
1369 return GDB_SIGNAL_KILL;
1370 case MIPS_SIGBUS:
1371 return GDB_SIGNAL_BUS;
1372 case MIPS_SIGSEGV:
1373 return GDB_SIGNAL_SEGV;
1374 case MIPS_SIGSYS:
1375 return GDB_SIGNAL_SYS;
1376 case MIPS_SIGPIPE:
1377 return GDB_SIGNAL_PIPE;
1378 case MIPS_SIGALRM:
1379 return GDB_SIGNAL_ALRM;
1380 case MIPS_SIGTERM:
1381 return GDB_SIGNAL_TERM;
1382 case MIPS_SIGUSR1:
1383 return GDB_SIGNAL_USR1;
1384 case MIPS_SIGUSR2:
1385 return GDB_SIGNAL_USR2;
1386 case MIPS_SIGCHLD:
1387 return GDB_SIGNAL_CHLD;
1388 case MIPS_SIGPWR:
1389 return GDB_SIGNAL_PWR;
1390 case MIPS_SIGWINCH:
1391 return GDB_SIGNAL_WINCH;
1392 case MIPS_SIGURG:
1393 return GDB_SIGNAL_URG;
1394 case MIPS_SIGPOLL:
1395 return GDB_SIGNAL_POLL;
1396 case MIPS_SIGSTOP:
1397 return GDB_SIGNAL_STOP;
1398 case MIPS_SIGTSTP:
1399 return GDB_SIGNAL_TSTP;
1400 case MIPS_SIGCONT:
1401 return GDB_SIGNAL_CONT;
1402 case MIPS_SIGTTIN:
1403 return GDB_SIGNAL_TTIN;
1404 case MIPS_SIGTTOU:
1405 return GDB_SIGNAL_TTOU;
1406 case MIPS_SIGVTALRM:
1407 return GDB_SIGNAL_VTALRM;
1408 case MIPS_SIGPROF:
1409 return GDB_SIGNAL_PROF;
1410 case MIPS_SIGXCPU:
1411 return GDB_SIGNAL_XCPU;
1412 case MIPS_SIGXFSZ:
1413 return GDB_SIGNAL_XFSZ;
1414 }
1415
1416 if (signo >= MIPS_SIGRTMIN && signo <= MIPS_SIGRTMAX)
1417 {
1418 /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of
1419 the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */
1420 signo -= MIPS_SIGRTMIN;
1421 if (signo == 0)
1422 return GDB_SIGNAL_REALTIME_32;
1423 else if (signo < 32)
1424 return ((enum gdb_signal) (signo - 1 + (int) GDB_SIGNAL_REALTIME_33));
1425 else
1426 return ((enum gdb_signal) (signo - 32 + (int) GDB_SIGNAL_REALTIME_64));
1427 }
1428
1429 return GDB_SIGNAL_UNKNOWN;
1430}
1431
5792a79b
DJ		 1432/* Initialize one of the GNU/Linux OS ABIs. */
1433
19ed69dd 1434static void
295093a4
MS		 1435mips_linux_init_abi (struct gdbarch_info info,
1436 struct gdbarch *gdbarch)
19ed69dd 1437{
96f026fc
KB		 1438 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1439 enum mips_abi abi = mips_abi (gdbarch);
822b6570 1440 struct tdesc_arch_data *tdesc_data = (void *) info.tdep_info;
96f026fc 1441
a5ee0f0c
PA		 1442 linux_init_abi (info, gdbarch);
1443
385203ed
DD		 1444 /* Get the syscall number from the arch's register. */
1445 set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number);
1446
96f026fc
KB		 1447 switch (abi)
1448 {
1449 case MIPS_ABI_O32:
1450 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1451 mips_linux_get_longjmp_target);
96f026fc 1452 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1453 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
fb2be677
AC		 1454 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1455 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
385203ed 1456 set_xml_syscall_file_name ("syscalls/mips-o32-linux.xml");
96f026fc
KB		 1457 break;
1458 case MIPS_ABI_N32:
1459 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1460 mips_linux_get_longjmp_target);
96f026fc 1461 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1462 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
d05f6826
DJ		 1463 set_gdbarch_long_double_bit (gdbarch, 128);
1464 /* These floatformats should probably be renamed. MIPS uses
1465 the same 128-bit IEEE floating point format that IA-64 uses,
1466 except that the quiet/signalling NaN bit is reversed (GDB
1467 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1468 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
fb2be677 1469 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
385203ed 1470 set_xml_syscall_file_name ("syscalls/mips-n32-linux.xml");
96f026fc
KB		 1471 break;
1472 case MIPS_ABI_N64:
1473 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1474 mips64_linux_get_longjmp_target);
96f026fc 1475 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1476 (gdbarch, svr4_lp64_fetch_link_map_offsets);
d05f6826
DJ		 1477 set_gdbarch_long_double_bit (gdbarch, 128);
1478 /* These floatformats should probably be renamed. MIPS uses
1479 the same 128-bit IEEE floating point format that IA-64 uses,
1480 except that the quiet/signalling NaN bit is reversed (GDB
1481 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1482 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
fb2be677 1483 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
385203ed 1484 set_xml_syscall_file_name ("syscalls/mips-n64-linux.xml");
96f026fc
KB		 1485 break;
1486 default:
96f026fc
KB		 1487 break;
1488 }
6de918a6
DJ		 1489
1490 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1491
0d0266c6 1492 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1493
1494 /* Enable TLS support. */
1495 set_gdbarch_fetch_tls_load_module_address (gdbarch,
7d266584 1496 svr4_fetch_objfile_link_map);
7d522c90
DJ		 1497
1498 /* Initialize this lazily, to avoid an initialization order
1499 dependency on solib-svr4.c's _initialize routine. */
1500 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
1501 {
1502 mips_svr4_so_ops = svr4_so_ops;
1503 mips_svr4_so_ops.in_dynsym_resolve_code
1504 = mips_linux_in_dynsym_resolve_code;
1505 }
1506 set_solib_ops (gdbarch, &mips_svr4_so_ops);
822b6570
DJ		 1507
1508 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
1509
4eb0ad19
DJ		 1510 set_gdbarch_core_read_description (gdbarch,
1511 mips_linux_core_read_description);
1512
50e8a0d5
HZ		 1513 set_gdbarch_regset_from_core_section (gdbarch,
1514 mips_linux_regset_from_core_section);
1515
232b8704
ME		 1516 set_gdbarch_gdb_signal_from_target (gdbarch,
1517 mips_gdb_signal_from_target);
1518
e38d4e1a
DJ		 1519 tdep->syscall_next_pc = mips_linux_syscall_next_pc;
1520
822b6570
DJ		 1521 if (tdesc_data)
1522 {
1523 const struct tdesc_feature *feature;
1524
1525 /* If we have target-described registers, then we can safely
1526 reserve a number for MIPS_RESTART_REGNUM (whether it is
1527 described or not). */
1528 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
1529 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
cf233303 1530 set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
822b6570
DJ		 1531
1532 /* If it's present, then assign it to the reserved number. */
1533 feature = tdesc_find_feature (info.target_desc,
1534 "org.gnu.gdb.mips.linux");
1535 if (feature != NULL)
1536 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
1537 "restart");
1538 }
19ed69dd
KB		 1539}
1540
63807e1d
PA		 1541/* Provide a prototype to silence -Wmissing-prototypes. */
1542extern initialize_file_ftype _initialize_mips_linux_tdep;
1543
2aa830e4 1544void
d1bacddc 1545_initialize_mips_linux_tdep (void)
2aa830e4 1546{
96f026fc
KB		 1547 const struct bfd_arch_info *arch_info;
1548
96f026fc
KB		 1549 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1550 arch_info != NULL;
1551 arch_info = arch_info->next)
1552 {
295093a4
MS		 1553 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1554 GDB_OSABI_LINUX,
96f026fc
KB		 1555 mips_linux_init_abi);
1556 }
2aa830e4 1557}
GDB Binutils - Deliverables
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