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* mips-tdep.c (mips_gdbarch_init): Default 64-bit ELF files to N64.
[deliverable/binutils-gdb.git] / gdb / mips-linux-tdep.c
CommitLineData
75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
76a9d10f
MK		 3 Copyright (C) 2001, 2002, 2004, 2005, 2006
4 Free Software Foundation, Inc.
2aa830e4
DJ		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
2aa830e4
DJ		 22
23#include "defs.h"
24#include "gdbcore.h"
25#include "target.h"
26#include "solib-svr4.h"
19ed69dd 27#include "osabi.h"
96f026fc 28#include "mips-tdep.h"
19ed69dd 29#include "gdb_string.h"
96f026fc 30#include "gdb_assert.h"
6de918a6 31#include "frame.h"
2fdf551c 32#include "regcache.h"
5792a79b
DJ		 33#include "trad-frame.h"
34#include "tramp-frame.h"
d05f6826 35#include "floatformat.h"
2aa830e4
DJ		 36
37/* Copied from <asm/elf.h>. */
38#define ELF_NGREG 45
39#define ELF_NFPREG 33
40
41typedef unsigned char elf_greg_t[4];
42typedef elf_greg_t elf_gregset_t[ELF_NGREG];
43
44typedef unsigned char elf_fpreg_t[8];
45typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
46
47/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
48#define FPR_BASE 32
49#define PC 64
50#define CAUSE 65
51#define BADVADDR 66
52#define MMHI 67
53#define MMLO 68
54#define FPC_CSR 69
55#define FPC_EIR 70
56
57#define EF_REG0 6
58#define EF_REG31 37
59#define EF_LO 38
60#define EF_HI 39
61#define EF_CP0_EPC 40
62#define EF_CP0_BADVADDR 41
63#define EF_CP0_STATUS 42
64#define EF_CP0_CAUSE 43
65
66#define EF_SIZE 180
67
68/* Figure out where the longjmp will land.
295093a4
MS		 69 We expect the first arg to be a pointer to the jmp_buf structure
70 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
71 at. The pc is copied into PC. This routine returns 1 on
72 success. */
2aa830e4 73
19ed69dd
KB		 74#define MIPS_LINUX_JB_ELEMENT_SIZE 4
75#define MIPS_LINUX_JB_PC 0
76
77static int
2aa830e4
DJ		 78mips_linux_get_longjmp_target (CORE_ADDR *pc)
79{
80 CORE_ADDR jb_addr;
81 char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
82
613e114f 83 jb_addr = read_register (MIPS_A0_REGNUM);
2aa830e4 84
bf072999
DJ		 85 if (target_read_memory (jb_addr
86 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
87 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
2aa830e4
DJ		 88 return 0;
89
7c0b4a20 90 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
2aa830e4
DJ		 91
92 return 1;
93}
94
4246e332 95/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 96 for regcache_raw_supply(). This is needed when mips_isa_regsize()
97 is 8. */
96f026fc
KB		 98
99static void
100supply_32bit_reg (int regnum, const void *addr)
101{
d9d9c31f 102 char buf[MAX_REGISTER_SIZE];
3acba339 103 store_signed_integer (buf, register_size (current_gdbarch, regnum),
96f026fc 104 extract_signed_integer (addr, 4));
23a6d369 105 regcache_raw_supply (current_regcache, regnum, buf);
96f026fc
KB		 106}
107
2aa830e4
DJ		 108/* Unpack an elf_gregset_t into GDB's register cache. */
109
110void
111supply_gregset (elf_gregset_t *gregsetp)
112{
113 int regi;
114 elf_greg_t *regp = *gregsetp;
d9d9c31f 115 char zerobuf[MAX_REGISTER_SIZE];
bf072999 116
d9d9c31f 117 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 118
119 for (regi = EF_REG0; regi <= EF_REG31; regi++)
96f026fc 120 supply_32bit_reg ((regi - EF_REG0), (char *)(regp + regi));
2aa830e4 121
56cea623
AC		 122 supply_32bit_reg (mips_regnum (current_gdbarch)->lo,
123 (char *)(regp + EF_LO));
124 supply_32bit_reg (mips_regnum (current_gdbarch)->hi,
125 (char *)(regp + EF_HI));
126
127 supply_32bit_reg (mips_regnum (current_gdbarch)->pc,
128 (char *)(regp + EF_CP0_EPC));
129 supply_32bit_reg (mips_regnum (current_gdbarch)->badvaddr,
130 (char *)(regp + EF_CP0_BADVADDR));
24e05951 131 supply_32bit_reg (MIPS_PS_REGNUM, (char *)(regp + EF_CP0_STATUS));
56cea623
AC		 132 supply_32bit_reg (mips_regnum (current_gdbarch)->cause,
133 (char *)(regp + EF_CP0_CAUSE));
2aa830e4
DJ		 134
135 /* Fill inaccessible registers with zero. */
613e114f 136 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
295093a4
MS		 137 for (regi = MIPS_FIRST_EMBED_REGNUM;
138 regi < MIPS_LAST_EMBED_REGNUM;
139 regi++)
23a6d369 140 regcache_raw_supply (current_regcache, regi, zerobuf);
2aa830e4
DJ		 141}
142
143/* Pack our registers (or one register) into an elf_gregset_t. */
144
145void
146fill_gregset (elf_gregset_t *gregsetp, int regno)
147{
148 int regaddr, regi;
149 elf_greg_t *regp = *gregsetp;
96f026fc 150 void *dst;
2aa830e4
DJ		 151
152 if (regno == -1)
153 {
154 memset (regp, 0, sizeof (elf_gregset_t));
155 for (regi = 0; regi < 32; regi++)
156 fill_gregset (gregsetp, regi);
56cea623
AC		 157 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
158 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
159 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
160 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->badvaddr);
24e05951 161 fill_gregset (gregsetp, MIPS_PS_REGNUM);
56cea623 162 fill_gregset (gregsetp, mips_regnum (current_gdbarch)->cause);
2aa830e4
DJ		 163
164 return;
165 }
166
167 if (regno < 32)
168 {
2aa830e4 169 dst = regp + regno + EF_REG0;
822c9732 170 regcache_raw_collect (current_regcache, regno, dst);
2aa830e4
DJ		 171 return;
172 }
173
56cea623
AC		 174 if (regno == mips_regnum (current_gdbarch)->lo)
175 regaddr = EF_LO;
176 else if (regno == mips_regnum (current_gdbarch)->hi)
177 regaddr = EF_HI;
178 else if (regno == mips_regnum (current_gdbarch)->pc)
179 regaddr = EF_CP0_EPC;
180 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
181 regaddr = EF_CP0_BADVADDR;
24e05951 182 else if (regno == MIPS_PS_REGNUM)
56cea623
AC		 183 regaddr = EF_CP0_STATUS;
184 else if (regno == mips_regnum (current_gdbarch)->cause)
185 regaddr = EF_CP0_CAUSE;
186 else
187 regaddr = -1;
2aa830e4
DJ		 188
189 if (regaddr != -1)
190 {
2aa830e4 191 dst = regp + regaddr;
822c9732 192 regcache_raw_collect (current_regcache, regno, dst);
2aa830e4
DJ		 193 }
194}
195
196/* Likewise, unpack an elf_fpregset_t. */
197
198void
199supply_fpregset (elf_fpregset_t *fpregsetp)
200{
52f0bd74 201 int regi;
d9d9c31f 202 char zerobuf[MAX_REGISTER_SIZE];
bf072999 203
d9d9c31f 204 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 205
206 for (regi = 0; regi < 32; regi++)
23a6d369
AC		 207 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
208 (char *)(*fpregsetp + regi));
2aa830e4 209
23a6d369
AC		 210 regcache_raw_supply (current_regcache,
211 mips_regnum (current_gdbarch)->fp_control_status,
212 (char *)(*fpregsetp + 32));
2aa830e4 213
295093a4 214 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
23a6d369
AC		 215 regcache_raw_supply (current_regcache,
216 mips_regnum (current_gdbarch)->fp_implementation_revision,
217 zerobuf);
2aa830e4
DJ		 218}
219
220/* Likewise, pack one or all floating point registers into an
221 elf_fpregset_t. */
222
223void
224fill_fpregset (elf_fpregset_t *fpregsetp, int regno)
225{
226 char *from, *to;
227
228 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
229 {
2aa830e4 230 to = (char *) (*fpregsetp + regno - FP0_REGNUM);
2fdf551c 231 regcache_raw_collect (current_regcache, regno, to);
2aa830e4 232 }
56cea623 233 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
2aa830e4 234 {
2aa830e4 235 to = (char *) (*fpregsetp + 32);
2fdf551c 236 regcache_raw_collect (current_regcache, regno, to);
2aa830e4
DJ		 237 }
238 else if (regno == -1)
239 {
240 int regi;
241
242 for (regi = 0; regi < 32; regi++)
243 fill_fpregset (fpregsetp, FP0_REGNUM + regi);
295093a4
MS		 244 fill_fpregset (fpregsetp,
245 mips_regnum (current_gdbarch)->fp_control_status);
2aa830e4
DJ		 246 }
247}
248
249/* Map gdb internal register number to ptrace ``address''.
250 These ``addresses'' are normally defined in <asm/ptrace.h>. */
251
96f026fc
KB		 252static CORE_ADDR
253mips_linux_register_addr (int regno, CORE_ADDR blockend)
2aa830e4
DJ		 254{
255 int regaddr;
256
257 if (regno < 0 || regno >= NUM_REGS)
8a3fe4f8 258 error (_("Bogon register number %d."), regno);
2aa830e4
DJ		 259
260 if (regno < 32)
261 regaddr = regno;
56cea623
AC		 262 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
263 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
264 regaddr = FPR_BASE + (regno - mips_regnum (current_gdbarch)->fp0);
265 else if (regno == mips_regnum (current_gdbarch)->pc)
2aa830e4 266 regaddr = PC;
56cea623 267 else if (regno == mips_regnum (current_gdbarch)->cause)
2aa830e4 268 regaddr = CAUSE;
56cea623 269 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
2aa830e4 270 regaddr = BADVADDR;
56cea623 271 else if (regno == mips_regnum (current_gdbarch)->lo)
2aa830e4 272 regaddr = MMLO;
56cea623 273 else if (regno == mips_regnum (current_gdbarch)->hi)
2aa830e4 274 regaddr = MMHI;
56cea623 275 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
2aa830e4 276 regaddr = FPC_CSR;
56cea623 277 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
2aa830e4
DJ		 278 regaddr = FPC_EIR;
279 else
8a3fe4f8 280 error (_("Unknowable register number %d."), regno);
2aa830e4
DJ		 281
282 return regaddr;
283}
284
96f026fc
KB		 285/* Support for 64-bit ABIs. */
286
287/* Copied from <asm/elf.h>. */
288#define MIPS64_ELF_NGREG 45
289#define MIPS64_ELF_NFPREG 33
290
291typedef unsigned char mips64_elf_greg_t[8];
292typedef mips64_elf_greg_t mips64_elf_gregset_t[MIPS64_ELF_NGREG];
293
294typedef unsigned char mips64_elf_fpreg_t[8];
295typedef mips64_elf_fpreg_t mips64_elf_fpregset_t[MIPS64_ELF_NFPREG];
296
297/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
298#define MIPS64_FPR_BASE 32
299#define MIPS64_PC 64
300#define MIPS64_CAUSE 65
301#define MIPS64_BADVADDR 66
302#define MIPS64_MMHI 67
303#define MIPS64_MMLO 68
304#define MIPS64_FPC_CSR 69
305#define MIPS64_FPC_EIR 70
306
307#define MIPS64_EF_REG0 0
308#define MIPS64_EF_REG31 31
309#define MIPS64_EF_LO 32
310#define MIPS64_EF_HI 33
311#define MIPS64_EF_CP0_EPC 34
312#define MIPS64_EF_CP0_BADVADDR 35
313#define MIPS64_EF_CP0_STATUS 36
314#define MIPS64_EF_CP0_CAUSE 37
315
316#define MIPS64_EF_SIZE 304
317
318/* Figure out where the longjmp will land.
295093a4
MS		 319 We expect the first arg to be a pointer to the jmp_buf structure
320 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
321 at. The pc is copied into PC. This routine returns 1 on
322 success. */
96f026fc
KB		 323
324/* Details about jmp_buf. */
325
326#define MIPS64_LINUX_JB_PC 0
327
328static int
329mips64_linux_get_longjmp_target (CORE_ADDR *pc)
330{
331 CORE_ADDR jb_addr;
332 void *buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT);
333 int element_size = TARGET_PTR_BIT == 32 ? 4 : 8;
334
613e114f 335 jb_addr = read_register (MIPS_A0_REGNUM);
96f026fc
KB		 336
337 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
338 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
339 return 0;
340
7c0b4a20 341 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
96f026fc
KB		 342
343 return 1;
344}
345
346/* Unpack an elf_gregset_t into GDB's register cache. */
347
348static void
349mips64_supply_gregset (mips64_elf_gregset_t *gregsetp)
350{
351 int regi;
352 mips64_elf_greg_t *regp = *gregsetp;
d9d9c31f 353 char zerobuf[MAX_REGISTER_SIZE];
96f026fc 354
d9d9c31f 355 memset (zerobuf, 0, MAX_REGISTER_SIZE);
96f026fc
KB		 356
357 for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++)
23a6d369
AC		 358 regcache_raw_supply (current_regcache, (regi - MIPS64_EF_REG0),
359 (char *)(regp + regi));
360
295093a4
MS		 361 regcache_raw_supply (current_regcache,
362 mips_regnum (current_gdbarch)->lo,
363 (char *) (regp + MIPS64_EF_LO));
364 regcache_raw_supply (current_regcache,
365 mips_regnum (current_gdbarch)->hi,
366 (char *) (regp + MIPS64_EF_HI));
23a6d369 367
295093a4
MS		 368 regcache_raw_supply (current_regcache,
369 mips_regnum (current_gdbarch)->pc,
370 (char *) (regp + MIPS64_EF_CP0_EPC));
371 regcache_raw_supply (current_regcache,
372 mips_regnum (current_gdbarch)->badvaddr,
373 (char *) (regp + MIPS64_EF_CP0_BADVADDR));
24e05951 374 regcache_raw_supply (current_regcache, MIPS_PS_REGNUM,
295093a4
MS		 375 (char *) (regp + MIPS64_EF_CP0_STATUS));
376 regcache_raw_supply (current_regcache,
377 mips_regnum (current_gdbarch)->cause,
378 (char *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc
KB		 379
380 /* Fill inaccessible registers with zero. */
613e114f 381 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
295093a4
MS		 382 for (regi = MIPS_FIRST_EMBED_REGNUM;
383 regi < MIPS_LAST_EMBED_REGNUM;
384 regi++)
23a6d369 385 regcache_raw_supply (current_regcache, regi, zerobuf);
96f026fc
KB		 386}
387
388/* Pack our registers (or one register) into an elf_gregset_t. */
389
390static void
391mips64_fill_gregset (mips64_elf_gregset_t *gregsetp, int regno)
392{
393 int regaddr, regi;
394 mips64_elf_greg_t *regp = *gregsetp;
395 void *src, *dst;
396
397 if (regno == -1)
398 {
399 memset (regp, 0, sizeof (mips64_elf_gregset_t));
400 for (regi = 0; regi < 32; regi++)
401 mips64_fill_gregset (gregsetp, regi);
56cea623
AC		 402 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
403 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
404 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
295093a4
MS		 405 mips64_fill_gregset (gregsetp,
406 mips_regnum (current_gdbarch)->badvaddr);
24e05951 407 mips64_fill_gregset (gregsetp, MIPS_PS_REGNUM);
295093a4
MS		 408 mips64_fill_gregset (gregsetp,
409 mips_regnum (current_gdbarch)->cause);
96f026fc
KB		 410
411 return;
412 }
413
414 if (regno < 32)
415 {
416 dst = regp + regno + MIPS64_EF_REG0;
822c9732 417 regcache_raw_collect (current_regcache, regno, dst);
96f026fc
KB		 418 return;
419 }
420
56cea623
AC		 421 if (regno == mips_regnum (current_gdbarch)->lo)
422 regaddr = MIPS64_EF_LO;
423 else if (regno == mips_regnum (current_gdbarch)->hi)
424 regaddr = MIPS64_EF_HI;
425 else if (regno == mips_regnum (current_gdbarch)->pc)
426 regaddr = MIPS64_EF_CP0_EPC;
427 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
428 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 429 else if (regno == MIPS_PS_REGNUM)
56cea623
AC		 430 regaddr = MIPS64_EF_CP0_STATUS;
431 else if (regno == mips_regnum (current_gdbarch)->cause)
432 regaddr = MIPS64_EF_CP0_CAUSE;
433 else
434 regaddr = -1;
96f026fc
KB		 435
436 if (regaddr != -1)
437 {
438 dst = regp + regaddr;
822c9732 439 regcache_raw_collect (current_regcache, regno, dst);
96f026fc
KB		 440 }
441}
442
443/* Likewise, unpack an elf_fpregset_t. */
444
445static void
446mips64_supply_fpregset (mips64_elf_fpregset_t *fpregsetp)
447{
52f0bd74 448 int regi;
d9d9c31f 449 char zerobuf[MAX_REGISTER_SIZE];
96f026fc 450
d9d9c31f 451 memset (zerobuf, 0, MAX_REGISTER_SIZE);
96f026fc
KB		 452
453 for (regi = 0; regi < 32; regi++)
23a6d369
AC		 454 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
455 (char *)(*fpregsetp + regi));
96f026fc 456
23a6d369
AC		 457 regcache_raw_supply (current_regcache,
458 mips_regnum (current_gdbarch)->fp_control_status,
459 (char *)(*fpregsetp + 32));
96f026fc 460
295093a4 461 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
23a6d369
AC		 462 regcache_raw_supply (current_regcache,
463 mips_regnum (current_gdbarch)->fp_implementation_revision,
464 zerobuf);
96f026fc
KB		 465}
466
467/* Likewise, pack one or all floating point registers into an
468 elf_fpregset_t. */
469
470static void
471mips64_fill_fpregset (mips64_elf_fpregset_t *fpregsetp, int regno)
472{
473 char *from, *to;
474
475 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
476 {
96f026fc 477 to = (char *) (*fpregsetp + regno - FP0_REGNUM);
2fdf551c 478 regcache_raw_collect (current_regcache, regno, to);
96f026fc 479 }
56cea623 480 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
96f026fc 481 {
96f026fc 482 to = (char *) (*fpregsetp + 32);
2fdf551c 483 regcache_raw_collect (current_regcache, regno, to);
96f026fc
KB		 484 }
485 else if (regno == -1)
486 {
487 int regi;
488
489 for (regi = 0; regi < 32; regi++)
490 mips64_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
56cea623
AC		 491 mips64_fill_fpregset(fpregsetp,
492 mips_regnum (current_gdbarch)->fp_control_status);
96f026fc
KB		 493 }
494}
495
496
497/* Map gdb internal register number to ptrace ``address''.
498 These ``addresses'' are normally defined in <asm/ptrace.h>. */
499
500static CORE_ADDR
501mips64_linux_register_addr (int regno, CORE_ADDR blockend)
502{
503 int regaddr;
504
505 if (regno < 0 || regno >= NUM_REGS)
8a3fe4f8 506 error (_("Bogon register number %d."), regno);
96f026fc
KB		 507
508 if (regno < 32)
509 regaddr = regno;
56cea623
AC		 510 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
511 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
96f026fc 512 regaddr = MIPS64_FPR_BASE + (regno - FP0_REGNUM);
56cea623 513 else if (regno == mips_regnum (current_gdbarch)->pc)
96f026fc 514 regaddr = MIPS64_PC;
56cea623 515 else if (regno == mips_regnum (current_gdbarch)->cause)
96f026fc 516 regaddr = MIPS64_CAUSE;
56cea623 517 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
96f026fc 518 regaddr = MIPS64_BADVADDR;
56cea623 519 else if (regno == mips_regnum (current_gdbarch)->lo)
96f026fc 520 regaddr = MIPS64_MMLO;
56cea623 521 else if (regno == mips_regnum (current_gdbarch)->hi)
96f026fc 522 regaddr = MIPS64_MMHI;
56cea623 523 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
96f026fc 524 regaddr = MIPS64_FPC_CSR;
56cea623 525 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
96f026fc
KB		 526 regaddr = MIPS64_FPC_EIR;
527 else
8a3fe4f8 528 error (_("Unknowable register number %d."), regno);
96f026fc
KB		 529
530 return regaddr;
531}
532
2aa830e4
DJ		 533/* Use a local version of this function to get the correct types for
534 regsets, until multi-arch core support is ready. */
535
536static void
537fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
538 int which, CORE_ADDR reg_addr)
539{
540 elf_gregset_t gregset;
541 elf_fpregset_t fpregset;
96f026fc
KB		 542 mips64_elf_gregset_t gregset64;
543 mips64_elf_fpregset_t fpregset64;
2aa830e4
DJ		 544
545 if (which == 0)
546 {
96f026fc 547 if (core_reg_size == sizeof (gregset))
2aa830e4 548 {
96f026fc
KB		 549 memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
550 supply_gregset (&gregset);
551 }
552 else if (core_reg_size == sizeof (gregset64))
553 {
554 memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64));
555 mips64_supply_gregset (&gregset64);
2aa830e4
DJ		 556 }
557 else
558 {
8a3fe4f8 559 warning (_("wrong size gregset struct in core file"));
2aa830e4
DJ		 560 }
561 }
562 else if (which == 2)
563 {
96f026fc 564 if (core_reg_size == sizeof (fpregset))
2aa830e4 565 {
96f026fc
KB		 566 memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
567 supply_fpregset (&fpregset);
568 }
569 else if (core_reg_size == sizeof (fpregset64))
570 {
295093a4
MS		 571 memcpy ((char *) &fpregset64, core_reg_sect,
572 sizeof (fpregset64));
96f026fc 573 mips64_supply_fpregset (&fpregset64);
2aa830e4
DJ		 574 }
575 else
576 {
8a3fe4f8 577 warning (_("wrong size fpregset struct in core file"));
2aa830e4
DJ		 578 }
579 }
580}
581
582/* Register that we are able to handle ELF file formats using standard
583 procfs "regset" structures. */
584
585static struct core_fns regset_core_fns =
586{
587 bfd_target_elf_flavour, /* core_flavour */
588 default_check_format, /* check_format */
589 default_core_sniffer, /* core_sniffer */
590 fetch_core_registers, /* core_read_registers */
591 NULL /* next */
592};
593
295093a4
MS		 594/* Handle for obtaining pointer to the current register_addr()
595 function for a given architecture. */
96f026fc
KB		 596static struct gdbarch_data *register_addr_data;
597
598CORE_ADDR
599register_addr (int regno, CORE_ADDR blockend)
600{
601 CORE_ADDR (*register_addr_ptr) (int, CORE_ADDR) =
602 gdbarch_data (current_gdbarch, register_addr_data);
603
604 gdb_assert (register_addr_ptr != 0);
605
606 return register_addr_ptr (regno, blockend);
607}
608
609static void
610set_mips_linux_register_addr (struct gdbarch *gdbarch,
295093a4
MS		 611 CORE_ADDR (*register_addr_ptr) (int,
612 CORE_ADDR))
96f026fc 613{
295093a4
MS		 614 deprecated_set_gdbarch_data (gdbarch, register_addr_data,
615 register_addr_ptr);
96f026fc
KB		 616}
617
618static void *
619init_register_addr_data (struct gdbarch *gdbarch)
620{
621 return 0;
622}
623
295093a4
MS		 624/* Check the code at PC for a dynamic linker lazy resolution stub.
625 Because they aren't in the .plt section, we pattern-match on the
626 code generated by GNU ld. They look like this:
6de918a6
DJ		 627
628 lw t9,0x8010(gp)
629 addu t7,ra
630 jalr t9,ra
631 addiu t8,zero,INDEX
632
295093a4
MS		 633 (with the appropriate doubleword instructions for N64). Also
634 return the dynamic symbol index used in the last instruction. */
6de918a6
DJ		 635
636static int
637mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
638{
639 unsigned char buf[28], *p;
640 ULONGEST insn, insn1;
641 int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64);
642
643 read_memory (pc - 12, buf, 28);
644
645 if (n64)
646 {
647 /* ld t9,0x8010(gp) */
648 insn1 = 0xdf998010;
649 }
650 else
651 {
652 /* lw t9,0x8010(gp) */
653 insn1 = 0x8f998010;
654 }
655
656 p = buf + 12;
657 while (p >= buf)
658 {
659 insn = extract_unsigned_integer (p, 4);
660 if (insn == insn1)
661 break;
662 p -= 4;
663 }
664 if (p < buf)
665 return 0;
666
667 insn = extract_unsigned_integer (p + 4, 4);
668 if (n64)
669 {
670 /* daddu t7,ra */
671 if (insn != 0x03e0782d)
672 return 0;
673 }
674 else
675 {
676 /* addu t7,ra */
677 if (insn != 0x03e07821)
678 return 0;
679 }
295093a4 680
6de918a6
DJ		 681 insn = extract_unsigned_integer (p + 8, 4);
682 /* jalr t9,ra */
683 if (insn != 0x0320f809)
684 return 0;
685
686 insn = extract_unsigned_integer (p + 12, 4);
687 if (n64)
688 {
689 /* daddiu t8,zero,0 */
690 if ((insn & 0xffff0000) != 0x64180000)
691 return 0;
692 }
693 else
694 {
695 /* addiu t8,zero,0 */
696 if ((insn & 0xffff0000) != 0x24180000)
697 return 0;
698 }
699
700 return (insn & 0xffff);
701}
702
295093a4
MS		 703/* Return non-zero iff PC belongs to the dynamic linker resolution
704 code or to a stub. */
6de918a6
DJ		 705
706int
707mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
708{
295093a4
MS		 709 /* Check whether PC is in the dynamic linker. This also checks
710 whether it is in the .plt section, which MIPS does not use. */
6de918a6
DJ		 711 if (in_solib_dynsym_resolve_code (pc))
712 return 1;
713
295093a4
MS		 714 /* Pattern match for the stub. It would be nice if there were a
715 more efficient way to avoid this check. */
6de918a6
DJ		 716 if (mips_linux_in_dynsym_stub (pc, NULL))
717 return 1;
718
719 return 0;
720}
721
722/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
723 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
724 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba
AC		 725 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
726 "__dl_runtime_resolve" directly. An unresolved PLT entry will
727 point to _dl_runtime_resolve, which will first call
728 __dl_runtime_resolve, and then pass control to the resolved
729 function. */
6de918a6
DJ		 730
731static CORE_ADDR
732mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
733{
734 struct minimal_symbol *resolver;
735
736 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
737
738 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
295093a4 739 return frame_pc_unwind (get_current_frame ());
6de918a6
DJ		 740
741 return 0;
295093a4 742}
6de918a6 743
5792a79b
DJ		 744/* Signal trampoline support. There are four supported layouts for a
745 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
746 n64 rt_sigframe. We handle them all independently; not the most
747 efficient way, but simplest. First, declare all the unwinders. */
748
749static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
750 struct frame_info *next_frame,
751 struct trad_frame_cache *this_cache,
752 CORE_ADDR func);
753
754static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
755 struct frame_info *next_frame,
756 struct trad_frame_cache *this_cache,
757 CORE_ADDR func);
758
759#define MIPS_NR_LINUX 4000
760#define MIPS_NR_N64_LINUX 5000
761#define MIPS_NR_N32_LINUX 6000
762
763#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
764#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
765#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
766#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
767
768#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
769#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
770#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
771#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
772#define MIPS_INST_SYSCALL 0x0000000c
773
2cd8546d
AC		 774static const struct tramp_frame mips_linux_o32_sigframe = {
775 SIGTRAMP_FRAME,
5792a79b 776 4,
2cd8546d
AC		 777 {
778 { MIPS_INST_LI_V0_SIGRETURN, -1 },
779 { MIPS_INST_SYSCALL, -1 },
780 { TRAMP_SENTINEL_INSN, -1 }
781 },
5792a79b
DJ		 782 mips_linux_o32_sigframe_init
783};
784
2cd8546d
AC		 785static const struct tramp_frame mips_linux_o32_rt_sigframe = {
786 SIGTRAMP_FRAME,
5792a79b 787 4,
2cd8546d
AC		 788 {
789 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
790 { MIPS_INST_SYSCALL, -1 },
791 { TRAMP_SENTINEL_INSN, -1 } },
5792a79b
DJ		 792 mips_linux_o32_sigframe_init
793};
794
2cd8546d
AC		 795static const struct tramp_frame mips_linux_n32_rt_sigframe = {
796 SIGTRAMP_FRAME,
5792a79b 797 4,
2cd8546d
AC		 798 {
799 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
800 { MIPS_INST_SYSCALL, -1 },
801 { TRAMP_SENTINEL_INSN, -1 }
802 },
5792a79b
DJ		 803 mips_linux_n32n64_sigframe_init
804};
805
2cd8546d
AC		 806static const struct tramp_frame mips_linux_n64_rt_sigframe = {
807 SIGTRAMP_FRAME,
5792a79b 808 4,
295093a4
MS		 809 { MIPS_INST_LI_V0_N64_RT_SIGRETURN,
810 MIPS_INST_SYSCALL,
811 TRAMP_SENTINEL_INSN },
5792a79b
DJ		 812 mips_linux_n32n64_sigframe_init
813};
814
815/* *INDENT-OFF* */
816/* The unwinder for o32 signal frames. The legacy structures look
817 like this:
818
819 struct sigframe {
820 u32 sf_ass[4]; [argument save space for o32]
821 u32 sf_code[2]; [signal trampoline]
822 struct sigcontext sf_sc;
823 sigset_t sf_mask;
824 };
825
826 struct sigcontext {
827 unsigned int sc_regmask; [Unused]
828 unsigned int sc_status;
829 unsigned long long sc_pc;
830 unsigned long long sc_regs[32];
831 unsigned long long sc_fpregs[32];
832 unsigned int sc_ownedfp;
833 unsigned int sc_fpc_csr;
834 unsigned int sc_fpc_eir; [Unused]
835 unsigned int sc_used_math;
836 unsigned int sc_ssflags; [Unused]
837 [Alignment hole of four bytes]
838 unsigned long long sc_mdhi;
839 unsigned long long sc_mdlo;
840
841 unsigned int sc_cause; [Unused]
842 unsigned int sc_badvaddr; [Unused]
843
844 unsigned long sc_sigset[4]; [kernel's sigset_t]
845 };
846
847 The RT signal frames look like this:
848
849 struct rt_sigframe {
850 u32 rs_ass[4]; [argument save space for o32]
851 u32 rs_code[2] [signal trampoline]
852 struct siginfo rs_info;
853 struct ucontext rs_uc;
854 };
855
856 struct ucontext {
857 unsigned long uc_flags;
858 struct ucontext *uc_link;
859 stack_t uc_stack;
860 [Alignment hole of four bytes]
861 struct sigcontext uc_mcontext;
862 sigset_t uc_sigmask;
863 }; */
864/* *INDENT-ON* */
865
866#define SIGFRAME_CODE_OFFSET (4 * 4)
867#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
868
869#define RTSIGFRAME_SIGINFO_SIZE 128
870#define STACK_T_SIZE (3 * 4)
871#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
872#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
873 + RTSIGFRAME_SIGINFO_SIZE \
874 + UCONTEXT_SIGCONTEXT_OFFSET)
875
876#define SIGCONTEXT_PC (1 * 8)
877#define SIGCONTEXT_REGS (2 * 8)
878#define SIGCONTEXT_FPREGS (34 * 8)
879#define SIGCONTEXT_FPCSR (66 * 8 + 4)
880#define SIGCONTEXT_HI (69 * 8)
881#define SIGCONTEXT_LO (70 * 8)
882#define SIGCONTEXT_CAUSE (71 * 8 + 0)
883#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
884
885#define SIGCONTEXT_REG_SIZE 8
886
887static void
888mips_linux_o32_sigframe_init (const struct tramp_frame *self,
889 struct frame_info *next_frame,
890 struct trad_frame_cache *this_cache,
891 CORE_ADDR func)
892{
893 int ireg, reg_position;
894 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
895 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
37c4d197 896 CORE_ADDR regs_base;
5792a79b
DJ		 897
898 if (self == &mips_linux_o32_sigframe)
899 sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET;
900 else
901 sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 902
903 /* I'm not proud of this hack. Eventually we will have the
904 infrastructure to indicate the size of saved registers on a
905 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 906 bytes but we only want four. Use regs_base to access any
907 64-bit fields. */
5792a79b 908 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
37c4d197
DJ		 909 regs_base = sigcontext_base + 4;
910 else
911 regs_base = sigcontext_base;
5792a79b
DJ		 912
913#if 0
914 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
37c4d197 915 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 916#endif
917
918 for (ireg = 1; ireg < 32; ireg++)
295093a4
MS		 919 trad_frame_set_reg_addr (this_cache,
920 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
37c4d197 921 regs_base + SIGCONTEXT_REGS
5792a79b
DJ		 922 + ireg * SIGCONTEXT_REG_SIZE);
923
37c4d197
DJ		 924 /* The way that floating point registers are saved, unfortunately,
925 depends on the architecture the kernel is built for. For the r3000 and
926 tx39, four bytes of each register are at the beginning of each of the
927 32 eight byte slots. For everything else, the registers are saved
928 using double precision; only the even-numbered slots are initialized,
929 and the high bits are the odd-numbered register. Assume the latter
930 layout, since we can't tell, and it's much more common. Which bits are
931 the "high" bits depends on endianness. */
5792a79b 932 for (ireg = 0; ireg < 32; ireg++)
37c4d197
DJ		 933 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (ireg & 1))
934 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
935 sigcontext_base + SIGCONTEXT_FPREGS + 4
936 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
937 else
938 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
939 sigcontext_base + SIGCONTEXT_FPREGS
940 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
5792a79b
DJ		 941
942 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
37c4d197 943 regs_base + SIGCONTEXT_PC);
5792a79b 944
295093a4
MS		 945 trad_frame_set_reg_addr (this_cache,
946 regs->fp_control_status + NUM_REGS,
5792a79b
DJ		 947 sigcontext_base + SIGCONTEXT_FPCSR);
948 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
37c4d197 949 regs_base + SIGCONTEXT_HI);
5792a79b 950 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
37c4d197 951 regs_base + SIGCONTEXT_LO);
5792a79b
DJ		 952 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
953 sigcontext_base + SIGCONTEXT_CAUSE);
954 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
955 sigcontext_base + SIGCONTEXT_BADVADDR);
956
957 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
958 trad_frame_set_id (this_cache,
295093a4
MS		 959 frame_id_build (func - SIGFRAME_CODE_OFFSET,
960 func));
5792a79b
DJ		 961}
962
963/* *INDENT-OFF* */
964/* For N32/N64 things look different. There is no non-rt signal frame.
965
966 struct rt_sigframe_n32 {
967 u32 rs_ass[4]; [ argument save space for o32 ]
968 u32 rs_code[2]; [ signal trampoline ]
969 struct siginfo rs_info;
970 struct ucontextn32 rs_uc;
971 };
972
973 struct ucontextn32 {
974 u32 uc_flags;
975 s32 uc_link;
976 stack32_t uc_stack;
977 struct sigcontext uc_mcontext;
978 sigset_t uc_sigmask; [ mask last for extensibility ]
979 };
295093a4 980
5792a79b
DJ		 981 struct rt_sigframe_n32 {
982 u32 rs_ass[4]; [ argument save space for o32 ]
983 u32 rs_code[2]; [ signal trampoline ]
984 struct siginfo rs_info;
985 struct ucontext rs_uc;
986 };
987
988 struct ucontext {
989 unsigned long uc_flags;
990 struct ucontext *uc_link;
991 stack_t uc_stack;
992 struct sigcontext uc_mcontext;
993 sigset_t uc_sigmask; [ mask last for extensibility ]
994 };
995
996 And the sigcontext is different (this is for both n32 and n64):
997
998 struct sigcontext {
999 unsigned long long sc_regs[32];
1000 unsigned long long sc_fpregs[32];
1001 unsigned long long sc_mdhi;
1002 unsigned long long sc_mdlo;
1003 unsigned long long sc_pc;
1004 unsigned int sc_status;
1005 unsigned int sc_fpc_csr;
1006 unsigned int sc_fpc_eir;
1007 unsigned int sc_used_math;
1008 unsigned int sc_cause;
1009 unsigned int sc_badvaddr;
1010 }; */
1011/* *INDENT-ON* */
1012
1013#define N32_STACK_T_SIZE STACK_T_SIZE
1014#define N64_STACK_T_SIZE (2 * 8 + 4)
1015#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1016#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1017#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1018 + RTSIGFRAME_SIGINFO_SIZE \
1019 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1020#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1021 + RTSIGFRAME_SIGINFO_SIZE \
1022 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1023
1024#define N64_SIGCONTEXT_REGS (0 * 8)
1025#define N64_SIGCONTEXT_FPREGS (32 * 8)
1026#define N64_SIGCONTEXT_HI (64 * 8)
1027#define N64_SIGCONTEXT_LO (65 * 8)
1028#define N64_SIGCONTEXT_PC (66 * 8)
1029#define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
1030#define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
1031#define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
1032#define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1033
1034#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1035
5792a79b
DJ		 1036static void
1037mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
1038 struct frame_info *next_frame,
1039 struct trad_frame_cache *this_cache,
1040 CORE_ADDR func)
1041{
1042 int ireg, reg_position;
1043 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
1044 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
1045
1046 if (self == &mips_linux_n32_rt_sigframe)
1047 sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET;
1048 else
1049 sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1050
5792a79b
DJ		 1051#if 0
1052 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
1053 sigcontext_base + N64_SIGCONTEXT_REGS);
1054#endif
1055
1056 for (ireg = 1; ireg < 32; ireg++)
295093a4
MS		 1057 trad_frame_set_reg_addr (this_cache,
1058 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
5792a79b
DJ		 1059 sigcontext_base + N64_SIGCONTEXT_REGS
1060 + ireg * N64_SIGCONTEXT_REG_SIZE);
1061
1062 for (ireg = 0; ireg < 32; ireg++)
1063 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
1064 sigcontext_base + N64_SIGCONTEXT_FPREGS
1065 + ireg * N64_SIGCONTEXT_REG_SIZE);
1066
1067 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
1068 sigcontext_base + N64_SIGCONTEXT_PC);
1069
295093a4
MS		 1070 trad_frame_set_reg_addr (this_cache,
1071 regs->fp_control_status + NUM_REGS,
5792a79b
DJ		 1072 sigcontext_base + N64_SIGCONTEXT_FPCSR);
1073 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
1074 sigcontext_base + N64_SIGCONTEXT_HI);
1075 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
1076 sigcontext_base + N64_SIGCONTEXT_LO);
1077 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
1078 sigcontext_base + N64_SIGCONTEXT_CAUSE);
1079 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
1080 sigcontext_base + N64_SIGCONTEXT_BADVADDR);
1081
1082 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1083 trad_frame_set_id (this_cache,
295093a4
MS		 1084 frame_id_build (func - SIGFRAME_CODE_OFFSET,
1085 func));
5792a79b
DJ		 1086}
1087
1088/* Initialize one of the GNU/Linux OS ABIs. */
1089
19ed69dd 1090static void
295093a4
MS		 1091mips_linux_init_abi (struct gdbarch_info info,
1092 struct gdbarch *gdbarch)
19ed69dd 1093{
96f026fc
KB		 1094 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1095 enum mips_abi abi = mips_abi (gdbarch);
1096
1097 switch (abi)
1098 {
1099 case MIPS_ABI_O32:
1100 set_gdbarch_get_longjmp_target (gdbarch,
1101 mips_linux_get_longjmp_target);
1102 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1103 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
96f026fc 1104 set_mips_linux_register_addr (gdbarch, mips_linux_register_addr);
fb2be677
AC		 1105 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1106 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
96f026fc
KB		 1107 break;
1108 case MIPS_ABI_N32:
1109 set_gdbarch_get_longjmp_target (gdbarch,
1110 mips_linux_get_longjmp_target);
1111 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1112 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
96f026fc 1113 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
d05f6826
DJ		 1114 set_gdbarch_long_double_bit (gdbarch, 128);
1115 /* These floatformats should probably be renamed. MIPS uses
1116 the same 128-bit IEEE floating point format that IA-64 uses,
1117 except that the quiet/signalling NaN bit is reversed (GDB
1118 does not distinguish between quiet and signalling NaNs). */
1119 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1120 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_big);
1121 else
1122 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_little);
fb2be677 1123 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
96f026fc
KB		 1124 break;
1125 case MIPS_ABI_N64:
1126 set_gdbarch_get_longjmp_target (gdbarch,
1127 mips64_linux_get_longjmp_target);
1128 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1129 (gdbarch, svr4_lp64_fetch_link_map_offsets);
96f026fc 1130 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
d05f6826
DJ		 1131 set_gdbarch_long_double_bit (gdbarch, 128);
1132 /* These floatformats should probably be renamed. MIPS uses
1133 the same 128-bit IEEE floating point format that IA-64 uses,
1134 except that the quiet/signalling NaN bit is reversed (GDB
1135 does not distinguish between quiet and signalling NaNs). */
1136 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1137 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_big);
1138 else
1139 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_little);
fb2be677 1140 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
96f026fc
KB		 1141 break;
1142 default:
e2e0b3e5 1143 internal_error (__FILE__, __LINE__, _("can't handle ABI"));
96f026fc
KB		 1144 break;
1145 }
6de918a6
DJ		 1146
1147 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1148
0d0266c6 1149 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1150
1151 /* Enable TLS support. */
1152 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1153 svr4_fetch_objfile_link_map);
19ed69dd
KB		 1154}
1155
2aa830e4 1156void
d1bacddc 1157_initialize_mips_linux_tdep (void)
2aa830e4 1158{
96f026fc
KB		 1159 const struct bfd_arch_info *arch_info;
1160
1161 register_addr_data =
030f20e1 1162 gdbarch_data_register_post_init (init_register_addr_data);
96f026fc
KB		 1163
1164 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1165 arch_info != NULL;
1166 arch_info = arch_info->next)
1167 {
295093a4
MS		 1168 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1169 GDB_OSABI_LINUX,
96f026fc
KB		 1170 mips_linux_init_abi);
1171 }
1172
00e32a35 1173 deprecated_add_core_fns (&regset_core_fns);
2aa830e4 1174}
GDB Binutils - Deliverables
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