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[deliverable/binutils-gdb.git] / gdb / mips-linux-tdep.c
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75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
61baf725 3 Copyright (C) 2001-2017 Free Software Foundation, Inc.
2aa830e4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ		 19
20#include "defs.h"
21#include "gdbcore.h"
22#include "target.h"
23#include "solib-svr4.h"
19ed69dd 24#include "osabi.h"
96f026fc 25#include "mips-tdep.h"
6de918a6 26#include "frame.h"
2fdf551c 27#include "regcache.h"
5792a79b
DJ		 28#include "trad-frame.h"
29#include "tramp-frame.h"
e6bb342a 30#include "gdbtypes.h"
3e5d3a5a 31#include "objfiles.h"
5ea03926 32#include "solib.h"
7d522c90 33#include "solist.h"
982e9687 34#include "symtab.h"
822b6570 35#include "target-descriptions.h"
50e8a0d5 36#include "regset.h"
d37eb719 37#include "mips-linux-tdep.h"
db5f024e 38#include "glibc-tdep.h"
a5ee0f0c 39#include "linux-tdep.h"
385203ed 40#include "xml-syscall.h"
232b8704 41#include "gdb_signals.h"
2aa830e4 42
7d522c90
DJ		 43static struct target_so_ops mips_svr4_so_ops;
44
eb14d406
SDJ		 45/* This enum represents the signals' numbers on the MIPS
46 architecture. It just contains the signal definitions which are
47 different from the generic implementation.
48
49 It is derived from the file <arch/mips/include/uapi/asm/signal.h>,
50 from the Linux kernel tree. */
51
52enum
53 {
54 MIPS_LINUX_SIGEMT = 7,
55 MIPS_LINUX_SIGBUS = 10,
56 MIPS_LINUX_SIGSYS = 12,
57 MIPS_LINUX_SIGUSR1 = 16,
58 MIPS_LINUX_SIGUSR2 = 17,
59 MIPS_LINUX_SIGCHLD = 18,
60 MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD,
61 MIPS_LINUX_SIGPWR = 19,
62 MIPS_LINUX_SIGWINCH = 20,
63 MIPS_LINUX_SIGURG = 21,
64 MIPS_LINUX_SIGIO = 22,
65 MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO,
66 MIPS_LINUX_SIGSTOP = 23,
67 MIPS_LINUX_SIGTSTP = 24,
68 MIPS_LINUX_SIGCONT = 25,
69 MIPS_LINUX_SIGTTIN = 26,
70 MIPS_LINUX_SIGTTOU = 27,
71 MIPS_LINUX_SIGVTALRM = 28,
72 MIPS_LINUX_SIGPROF = 29,
73 MIPS_LINUX_SIGXCPU = 30,
74 MIPS_LINUX_SIGXFSZ = 31,
75
76 MIPS_LINUX_SIGRTMIN = 32,
77 MIPS_LINUX_SIGRT64 = 64,
78 MIPS_LINUX_SIGRTMAX = 127,
79 };
80
2aa830e4 81/* Figure out where the longjmp will land.
295093a4
MS		 82 We expect the first arg to be a pointer to the jmp_buf structure
83 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
84 at. The pc is copied into PC. This routine returns 1 on
85 success. */
2aa830e4 86
19ed69dd
KB		 87#define MIPS_LINUX_JB_ELEMENT_SIZE 4
88#define MIPS_LINUX_JB_PC 0
89
90static int
60ade65d 91mips_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2aa830e4
DJ		 92{
93 CORE_ADDR jb_addr;
2eb4d78b 94 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 95 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e362b510 96 gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT];
2aa830e4 97
60ade65d 98 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
2aa830e4 99
7d266584
MR		 100 if (target_read_memory ((jb_addr
101 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE),
2eb4d78b 102 buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
2aa830e4
DJ		 103 return 0;
104
819844ad 105 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 106 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
107 byte_order);
2aa830e4
DJ		 108
109 return 1;
110}
111
4246e332 112/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 113 for regcache_raw_supply(). This is needed when mips_isa_regsize()
114 is 8. */
96f026fc
KB		 115
116static void
28f5035f 117supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr)
96f026fc 118{
b057297a 119 regcache->raw_supply_integer (regnum, (const gdb_byte *) addr, 4, true);
96f026fc
KB		 120}
121
2aa830e4
DJ		 122/* Unpack an elf_gregset_t into GDB's register cache. */
123
d37eb719 124void
28f5035f
UW		 125mips_supply_gregset (struct regcache *regcache,
126 const mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 127{
128 int regi;
28f5035f 129 const mips_elf_greg_t *regp = *gregsetp;
2eb4d78b 130 struct gdbarch *gdbarch = get_regcache_arch (regcache);
bf072999 131
822b6570 132 for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++)
28f5035f 133 supply_32bit_reg (regcache, regi - EF_REG0, regp + regi);
2aa830e4 134
2eb4d78b 135 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 136 supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0);
137
2eb4d78b
UW		 138 supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO);
139 supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI);
56cea623 140
2eb4d78b 141 supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 142 regp + EF_CP0_EPC);
2eb4d78b 143 supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 144 regp + EF_CP0_BADVADDR);
145 supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS);
2eb4d78b 146 supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 147 regp + EF_CP0_CAUSE);
2aa830e4 148
1faeff08 149 /* Fill the inaccessible zero register with zero. */
27bfc1d1 150 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
2aa830e4
DJ		 151}
152
50e8a0d5
HZ		 153static void
154mips_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 155 struct regcache *regcache,
156 int regnum, const void *gregs, size_t len)
50e8a0d5 157{
1528345d 158 gdb_assert (len >= sizeof (mips_elf_gregset_t));
50e8a0d5
HZ		 159
160 mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs);
161}
162
2aa830e4
DJ		 163/* Pack our registers (or one register) into an elf_gregset_t. */
164
d37eb719 165void
28f5035f
UW		 166mips_fill_gregset (const struct regcache *regcache,
167 mips_elf_gregset_t *gregsetp, int regno)
2aa830e4 168{
2eb4d78b 169 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2aa830e4 170 int regaddr, regi;
d37eb719 171 mips_elf_greg_t *regp = *gregsetp;
96f026fc 172 void *dst;
2aa830e4
DJ		 173
174 if (regno == -1)
175 {
d37eb719 176 memset (regp, 0, sizeof (mips_elf_gregset_t));
822b6570 177 for (regi = 1; regi < 32; regi++)
28f5035f 178 mips_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 179 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
180 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
181 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
182 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr);
28f5035f 183 mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 184 mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 185 mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
2aa830e4
DJ		 186 return;
187 }
188
822b6570 189 if (regno > 0 && regno < 32)
2aa830e4 190 {
2aa830e4 191 dst = regp + regno + EF_REG0;
28f5035f 192 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 193 return;
194 }
195
2eb4d78b
UW		 196 if (regno == mips_regnum (gdbarch)->lo)
197 regaddr = EF_LO;
198 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 199 regaddr = EF_HI;
2eb4d78b 200 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 201 regaddr = EF_CP0_EPC;
2eb4d78b 202 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 203 regaddr = EF_CP0_BADVADDR;
24e05951 204 else if (regno == MIPS_PS_REGNUM)
56cea623 205 regaddr = EF_CP0_STATUS;
2eb4d78b 206 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 207 regaddr = EF_CP0_CAUSE;
2eb4d78b 208 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 209 && regno == MIPS_RESTART_REGNUM)
210 regaddr = EF_REG0;
56cea623
AC		 211 else
212 regaddr = -1;
2aa830e4
DJ		 213
214 if (regaddr != -1)
215 {
2aa830e4 216 dst = regp + regaddr;
28f5035f 217 regcache_raw_collect (regcache, regno, dst);
2aa830e4
DJ		 218 }
219}
220
50e8a0d5
HZ		 221static void
222mips_fill_gregset_wrapper (const struct regset *regset,
223 const struct regcache *regcache,
224 int regnum, void *gregs, size_t len)
225{
1528345d 226 gdb_assert (len >= sizeof (mips_elf_gregset_t));
50e8a0d5
HZ		 227
228 mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum);
229}
230
2aa830e4
DJ		 231/* Likewise, unpack an elf_fpregset_t. */
232
d37eb719 233void
28f5035f
UW		 234mips_supply_fpregset (struct regcache *regcache,
235 const mips_elf_fpregset_t *fpregsetp)
2aa830e4 236{
2eb4d78b 237 struct gdbarch *gdbarch = get_regcache_arch (regcache);
52f0bd74 238 int regi;
2aa830e4
DJ		 239
240 for (regi = 0; regi < 32; regi++)
3e8c568d 241 regcache_raw_supply (regcache,
2eb4d78b 242 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 243 *fpregsetp + regi);
2aa830e4 244
28f5035f 245 regcache_raw_supply (regcache,
2eb4d78b 246 mips_regnum (gdbarch)->fp_control_status,
28f5035f 247 *fpregsetp + 32);
2aa830e4 248
295093a4 249 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
27bfc1d1
AH		 250 regcache->raw_supply_zeroed
251 (mips_regnum (gdbarch)->fp_implementation_revision);
2aa830e4
DJ		 252}
253
50e8a0d5
HZ		 254static void
255mips_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 256 struct regcache *regcache,
257 int regnum, const void *gregs, size_t len)
50e8a0d5 258{
1528345d 259 gdb_assert (len >= sizeof (mips_elf_fpregset_t));
50e8a0d5
HZ		 260
261 mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *)gregs);
262}
263
2aa830e4
DJ		 264/* Likewise, pack one or all floating point registers into an
265 elf_fpregset_t. */
266
d37eb719 267void
28f5035f
UW		 268mips_fill_fpregset (const struct regcache *regcache,
269 mips_elf_fpregset_t *fpregsetp, int regno)
2aa830e4 270{
2eb4d78b 271 struct gdbarch *gdbarch = get_regcache_arch (regcache);
22e048c9 272 char *to;
2aa830e4 273
2eb4d78b
UW		 274 if ((regno >= gdbarch_fp0_regnum (gdbarch))
275 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
2aa830e4 276 {
2eb4d78b 277 to = (char *) (*fpregsetp + regno - gdbarch_fp0_regnum (gdbarch));
28f5035f 278 regcache_raw_collect (regcache, regno, to);
2aa830e4 279 }
2eb4d78b 280 else if (regno == mips_regnum (gdbarch)->fp_control_status)
2aa830e4 281 {
2aa830e4 282 to = (char *) (*fpregsetp + 32);
28f5035f 283 regcache_raw_collect (regcache, regno, to);
2aa830e4
DJ		 284 }
285 else if (regno == -1)
286 {
287 int regi;
288
289 for (regi = 0; regi < 32; regi++)
3e8c568d 290 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 291 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 292 mips_fill_fpregset (regcache, fpregsetp,
2eb4d78b 293 mips_regnum (gdbarch)->fp_control_status);
2aa830e4
DJ		 294 }
295}
296
50e8a0d5
HZ		 297static void
298mips_fill_fpregset_wrapper (const struct regset *regset,
299 const struct regcache *regcache,
300 int regnum, void *gregs, size_t len)
301{
1528345d 302 gdb_assert (len >= sizeof (mips_elf_fpregset_t));
50e8a0d5
HZ		 303
304 mips_fill_fpregset (regcache, (mips_elf_fpregset_t *)gregs, regnum);
305}
306
96f026fc
KB		 307/* Support for 64-bit ABIs. */
308
96f026fc 309/* Figure out where the longjmp will land.
295093a4
MS		 310 We expect the first arg to be a pointer to the jmp_buf structure
311 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
312 at. The pc is copied into PC. This routine returns 1 on
313 success. */
96f026fc
KB		 314
315/* Details about jmp_buf. */
316
317#define MIPS64_LINUX_JB_PC 0
318
319static int
60ade65d 320mips64_linux_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
96f026fc
KB		 321{
322 CORE_ADDR jb_addr;
2eb4d78b 323 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 324 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
709476c3
SM		 325 gdb_byte *buf
326 = (gdb_byte *) alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT);
2eb4d78b 327 int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8;
96f026fc 328
60ade65d 329 jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM);
96f026fc
KB		 330
331 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
819844ad 332 buf,
2eb4d78b 333 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT))
96f026fc
KB		 334 return 0;
335
819844ad 336 *pc = extract_unsigned_integer (buf,
e17a4113
UW		 337 gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT,
338 byte_order);
96f026fc
KB		 339
340 return 1;
341}
342
d37eb719
DJ		 343/* Register set support functions. These operate on standard 64-bit
344 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
345 target will still use the 64-bit format for PTRACE_GETREGS. */
346
347/* Supply a 64-bit register. */
96f026fc 348
63807e1d 349static void
28f5035f
UW		 350supply_64bit_reg (struct regcache *regcache, int regnum,
351 const gdb_byte *buf)
d37eb719 352{
2eb4d78b
UW		 353 struct gdbarch *gdbarch = get_regcache_arch (regcache);
354 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
355 && register_size (gdbarch, regnum) == 4)
28f5035f 356 regcache_raw_supply (regcache, regnum, buf + 4);
d37eb719 357 else
28f5035f 358 regcache_raw_supply (regcache, regnum, buf);
d37eb719
DJ		 359}
360
361/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
362
363void
28f5035f
UW		 364mips64_supply_gregset (struct regcache *regcache,
365 const mips64_elf_gregset_t *gregsetp)
96f026fc
KB		 366{
367 int regi;
28f5035f 368 const mips64_elf_greg_t *regp = *gregsetp;
2eb4d78b 369 struct gdbarch *gdbarch = get_regcache_arch (regcache);
96f026fc 370
822b6570 371 for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++)
28f5035f 372 supply_64bit_reg (regcache, regi - MIPS64_EF_REG0,
7d266584 373 (const gdb_byte *) (regp + regi));
28f5035f 374
2eb4d78b 375 if (mips_linux_restart_reg_p (gdbarch))
822b6570 376 supply_64bit_reg (regcache, MIPS_RESTART_REGNUM,
7d266584 377 (const gdb_byte *) (regp + MIPS64_EF_REG0));
822b6570 378
2eb4d78b 379 supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo,
28f5035f 380 (const gdb_byte *) (regp + MIPS64_EF_LO));
2eb4d78b 381 supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi,
28f5035f
UW		 382 (const gdb_byte *) (regp + MIPS64_EF_HI));
383
2eb4d78b 384 supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc,
28f5035f 385 (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
2eb4d78b 386 supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr,
28f5035f
UW		 387 (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
388 supply_64bit_reg (regcache, MIPS_PS_REGNUM,
389 (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
2eb4d78b 390 supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause,
28f5035f 391 (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc 392
1faeff08 393 /* Fill the inaccessible zero register with zero. */
27bfc1d1 394 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
96f026fc
KB		 395}
396
50e8a0d5
HZ		 397static void
398mips64_supply_gregset_wrapper (const struct regset *regset,
7d266584
MR		 399 struct regcache *regcache,
400 int regnum, const void *gregs, size_t len)
50e8a0d5 401{
1528345d 402 gdb_assert (len >= sizeof (mips64_elf_gregset_t));
50e8a0d5
HZ		 403
404 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs);
405}
406
d37eb719 407/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 408
d37eb719 409void
28f5035f
UW		 410mips64_fill_gregset (const struct regcache *regcache,
411 mips64_elf_gregset_t *gregsetp, int regno)
96f026fc 412{
2eb4d78b 413 struct gdbarch *gdbarch = get_regcache_arch (regcache);
96f026fc
KB		 414 int regaddr, regi;
415 mips64_elf_greg_t *regp = *gregsetp;
2ba93934 416 void *dst;
96f026fc
KB		 417
418 if (regno == -1)
419 {
420 memset (regp, 0, sizeof (mips64_elf_gregset_t));
822b6570 421 for (regi = 1; regi < 32; regi++)
7d266584 422 mips64_fill_gregset (regcache, gregsetp, regi);
2eb4d78b
UW		 423 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo);
424 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi);
425 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc);
025bb325
MS		 426 mips64_fill_gregset (regcache, gregsetp,
427 mips_regnum (gdbarch)->badvaddr);
28f5035f 428 mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM);
2eb4d78b 429 mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause);
822b6570 430 mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM);
96f026fc
KB		 431 return;
432 }
433
822b6570 434 if (regno > 0 && regno < 32)
d37eb719 435 regaddr = regno + MIPS64_EF_REG0;
2eb4d78b 436 else if (regno == mips_regnum (gdbarch)->lo)
56cea623 437 regaddr = MIPS64_EF_LO;
2eb4d78b 438 else if (regno == mips_regnum (gdbarch)->hi)
56cea623 439 regaddr = MIPS64_EF_HI;
2eb4d78b 440 else if (regno == mips_regnum (gdbarch)->pc)
56cea623 441 regaddr = MIPS64_EF_CP0_EPC;
2eb4d78b 442 else if (regno == mips_regnum (gdbarch)->badvaddr)
56cea623 443 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 444 else if (regno == MIPS_PS_REGNUM)
56cea623 445 regaddr = MIPS64_EF_CP0_STATUS;
2eb4d78b 446 else if (regno == mips_regnum (gdbarch)->cause)
56cea623 447 regaddr = MIPS64_EF_CP0_CAUSE;
2eb4d78b 448 else if (mips_linux_restart_reg_p (gdbarch)
822b6570
DJ		 449 && regno == MIPS_RESTART_REGNUM)
450 regaddr = MIPS64_EF_REG0;
56cea623
AC		 451 else
452 regaddr = -1;
96f026fc
KB		 453
454 if (regaddr != -1)
455 {
456 dst = regp + regaddr;
b057297a 457 regcache->raw_collect_integer (regno, (gdb_byte *) dst, 8, true);
96f026fc
KB		 458 }
459}
460
50e8a0d5
HZ		 461static void
462mips64_fill_gregset_wrapper (const struct regset *regset,
463 const struct regcache *regcache,
464 int regnum, void *gregs, size_t len)
465{
1528345d 466 gdb_assert (len >= sizeof (mips64_elf_gregset_t));
50e8a0d5
HZ		 467
468 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum);
469}
470
96f026fc
KB		 471/* Likewise, unpack an elf_fpregset_t. */
472
d37eb719 473void
28f5035f
UW		 474mips64_supply_fpregset (struct regcache *regcache,
475 const mips64_elf_fpregset_t *fpregsetp)
96f026fc 476{
2eb4d78b 477 struct gdbarch *gdbarch = get_regcache_arch (regcache);
52f0bd74 478 int regi;
96f026fc 479
d37eb719
DJ		 480 /* See mips_linux_o32_sigframe_init for a description of the
481 peculiar FP register layout. */
2eb4d78b 482 if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4)
d37eb719
DJ		 483 for (regi = 0; regi < 32; regi++)
484 {
7d266584
MR		 485 const gdb_byte *reg_ptr
486 = (const gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 487 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 488 reg_ptr += 4;
3e8c568d 489 regcache_raw_supply (regcache,
2eb4d78b 490 gdbarch_fp0_regnum (gdbarch) + regi,
3e8c568d 491 reg_ptr);
d37eb719
DJ		 492 }
493 else
494 for (regi = 0; regi < 32; regi++)
3e8c568d 495 regcache_raw_supply (regcache,
2eb4d78b 496 gdbarch_fp0_regnum (gdbarch) + regi,
7d266584 497 (const char *) (*fpregsetp + regi));
d37eb719 498
2eb4d78b 499 supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status,
7d266584 500 (const gdb_byte *) (*fpregsetp + 32));
d37eb719
DJ		 501
502 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
503 include it - but the result of PTRACE_GETFPREGS does. The best we
504 can do is to assume that its value is present. */
28f5035f 505 supply_32bit_reg (regcache,
2eb4d78b 506 mips_regnum (gdbarch)->fp_implementation_revision,
7d266584 507 (const gdb_byte *) (*fpregsetp + 32) + 4);
96f026fc
KB		 508}
509
50e8a0d5
HZ		 510static void
511mips64_supply_fpregset_wrapper (const struct regset *regset,
7d266584
MR		 512 struct regcache *regcache,
513 int regnum, const void *gregs, size_t len)
50e8a0d5 514{
1528345d 515 gdb_assert (len >= sizeof (mips64_elf_fpregset_t));
50e8a0d5
HZ		 516
517 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs);
518}
519
96f026fc
KB		 520/* Likewise, pack one or all floating point registers into an
521 elf_fpregset_t. */
522
d37eb719 523void
28f5035f
UW		 524mips64_fill_fpregset (const struct regcache *regcache,
525 mips64_elf_fpregset_t *fpregsetp, int regno)
96f026fc 526{
2eb4d78b 527 struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 528 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d37eb719 529 gdb_byte *to;
96f026fc 530
2eb4d78b
UW		 531 if ((regno >= gdbarch_fp0_regnum (gdbarch))
532 && (regno < gdbarch_fp0_regnum (gdbarch) + 32))
96f026fc 533 {
d37eb719
DJ		 534 /* See mips_linux_o32_sigframe_init for a description of the
535 peculiar FP register layout. */
2eb4d78b 536 if (register_size (gdbarch, regno) == 4)
d37eb719 537 {
2eb4d78b 538 int regi = regno - gdbarch_fp0_regnum (gdbarch);
d37eb719
DJ		 539
540 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
2eb4d78b 541 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1))
d37eb719 542 to += 4;
28f5035f 543 regcache_raw_collect (regcache, regno, to);
d37eb719
DJ		 544 }
545 else
546 {
025bb325
MS		 547 to = (gdb_byte *) (*fpregsetp + regno
548 - gdbarch_fp0_regnum (gdbarch));
28f5035f 549 regcache_raw_collect (regcache, regno, to);
d37eb719 550 }
96f026fc 551 }
2eb4d78b 552 else if (regno == mips_regnum (gdbarch)->fp_control_status)
96f026fc 553 {
d37eb719 554 to = (gdb_byte *) (*fpregsetp + 32);
b057297a 555 regcache->raw_collect_integer (regno, to, 4, true);
d37eb719 556 }
2eb4d78b 557 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719 558 {
d37eb719 559 to = (gdb_byte *) (*fpregsetp + 32) + 4;
b057297a 560 regcache->raw_collect_integer (regno, to, 4, true);
96f026fc
KB		 561 }
562 else if (regno == -1)
563 {
564 int regi;
565
566 for (regi = 0; regi < 32; regi++)
3e8c568d 567 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 568 gdbarch_fp0_regnum (gdbarch) + regi);
28f5035f 569 mips64_fill_fpregset (regcache, fpregsetp,
2eb4d78b 570 mips_regnum (gdbarch)->fp_control_status);
28f5035f 571 mips64_fill_fpregset (regcache, fpregsetp,
7d266584 572 mips_regnum (gdbarch)->fp_implementation_revision);
96f026fc
KB		 573 }
574}
575
50e8a0d5
HZ		 576static void
577mips64_fill_fpregset_wrapper (const struct regset *regset,
578 const struct regcache *regcache,
579 int regnum, void *gregs, size_t len)
580{
1528345d 581 gdb_assert (len >= sizeof (mips64_elf_fpregset_t));
96f026fc 582
50e8a0d5
HZ		 583 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum);
584}
2aa830e4 585
b7195f27
AA		 586static const struct regset mips_linux_gregset =
587 {
588 NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper
589 };
590
591static const struct regset mips64_linux_gregset =
592 {
593 NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper
594 };
595
596static const struct regset mips_linux_fpregset =
597 {
598 NULL, mips_supply_fpregset_wrapper, mips_fill_fpregset_wrapper
599 };
600
601static const struct regset mips64_linux_fpregset =
602 {
603 NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper
604 };
605
d4036235
AA		 606static void
607mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
608 iterate_over_regset_sections_cb *cb,
609 void *cb_data,
610 const struct regcache *regcache)
2aa830e4 611{
d4036235 612 if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4)
2aa830e4 613 {
d4036235
AA		 614 cb (".reg", sizeof (mips_elf_gregset_t), &mips_linux_gregset,
615 NULL, cb_data);
616 cb (".reg2", sizeof (mips_elf_fpregset_t), &mips_linux_fpregset,
617 NULL, cb_data);
2aa830e4 618 }
d4036235 619 else
2aa830e4 620 {
d4036235
AA		 621 cb (".reg", sizeof (mips64_elf_gregset_t), &mips64_linux_gregset,
622 NULL, cb_data);
623 cb (".reg2", sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset,
624 NULL, cb_data);
2aa830e4 625 }
50e8a0d5 626}
2aa830e4 627
4eb0ad19
DJ		 628static const struct target_desc *
629mips_linux_core_read_description (struct gdbarch *gdbarch,
630 struct target_ops *target,
631 bfd *abfd)
632{
633 asection *section = bfd_get_section_by_name (abfd, ".reg");
634 if (! section)
635 return NULL;
636
637 switch (bfd_section_size (abfd, section))
638 {
639 case sizeof (mips_elf_gregset_t):
640 return mips_tdesc_gp32;
641
642 case sizeof (mips64_elf_gregset_t):
643 return mips_tdesc_gp64;
644
645 default:
646 return NULL;
647 }
648}
649
96f026fc 650
295093a4 651/* Check the code at PC for a dynamic linker lazy resolution stub.
3e5d3a5a
MR		 652 GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs"
653 section uniformly since version 2.15. If the pc is in that section,
654 then we are in such a stub. Before that ".stub" was used in 32-bit
655 ELF binaries, however we do not bother checking for that since we
656 have never had and that case should be extremely rare these days.
657 Instead we pattern-match on the code generated by GNU ld. They look
658 like this:
6de918a6
DJ		 659
660 lw t9,0x8010(gp)
661 addu t7,ra
662 jalr t9,ra
663 addiu t8,zero,INDEX
664
3e5d3a5a
MR		 665 (with the appropriate doubleword instructions for N64). As any lazy
666 resolution stubs in microMIPS binaries will always be in a
667 ".MIPS.stubs" section we only ever verify standard MIPS patterns. */
6de918a6
DJ		 668
669static int
3e5d3a5a 670mips_linux_in_dynsym_stub (CORE_ADDR pc)
6de918a6 671{
e362b510 672 gdb_byte buf[28], *p;
6de918a6 673 ULONGEST insn, insn1;
f5656ead
TT		 674 int n64 = (mips_abi (target_gdbarch ()) == MIPS_ABI_N64);
675 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
6de918a6 676
3e5d3a5a
MR		 677 if (in_mips_stubs_section (pc))
678 return 1;
679
6de918a6
DJ		 680 read_memory (pc - 12, buf, 28);
681
682 if (n64)
683 {
684 /* ld t9,0x8010(gp) */
685 insn1 = 0xdf998010;
686 }
687 else
688 {
689 /* lw t9,0x8010(gp) */
690 insn1 = 0x8f998010;
691 }
692
693 p = buf + 12;
694 while (p >= buf)
695 {
e17a4113 696 insn = extract_unsigned_integer (p, 4, byte_order);
6de918a6
DJ		 697 if (insn == insn1)
698 break;
699 p -= 4;
700 }
701 if (p < buf)
702 return 0;
703
e17a4113 704 insn = extract_unsigned_integer (p + 4, 4, byte_order);
6de918a6
DJ		 705 if (n64)
706 {
93084fcd
SD		 707 /* 'daddu t7,ra' or 'or t7, ra, zero'*/
708 if (insn != 0x03e0782d || insn != 0x03e07825)
6de918a6 709 return 0;
93084fcd 710
6de918a6
DJ		 711 }
712 else
713 {
93084fcd
SD		 714 /* 'addu t7,ra' or 'or t7, ra, zero'*/
715 if (insn != 0x03e07821 || insn != 0x03e07825)
6de918a6 716 return 0;
93084fcd 717
6de918a6 718 }
295093a4 719
e17a4113 720 insn = extract_unsigned_integer (p + 8, 4, byte_order);
6de918a6
DJ		 721 /* jalr t9,ra */
722 if (insn != 0x0320f809)
723 return 0;
724
e17a4113 725 insn = extract_unsigned_integer (p + 12, 4, byte_order);
6de918a6
DJ		 726 if (n64)
727 {
728 /* daddiu t8,zero,0 */
729 if ((insn & 0xffff0000) != 0x64180000)
730 return 0;
731 }
732 else
733 {
734 /* addiu t8,zero,0 */
735 if ((insn & 0xffff0000) != 0x24180000)
736 return 0;
737 }
738
3e5d3a5a 739 return 1;
6de918a6
DJ		 740}
741
295093a4 742/* Return non-zero iff PC belongs to the dynamic linker resolution
db5f024e 743 code, a PLT entry, or a lazy binding stub. */
6de918a6 744
7d522c90 745static int
6de918a6
DJ		 746mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
747{
295093a4 748 /* Check whether PC is in the dynamic linker. This also checks
db5f024e 749 whether it is in the .plt section, used by non-PIC executables. */
7d522c90 750 if (svr4_in_dynsym_resolve_code (pc))
6de918a6
DJ		 751 return 1;
752
3e5d3a5a
MR		 753 /* Likewise for the stubs. They live in the .MIPS.stubs section these
754 days, so we check if the PC is within, than fall back to a pattern
755 match. */
756 if (mips_linux_in_dynsym_stub (pc))
6de918a6
DJ		 757 return 1;
758
759 return 0;
760}
761
762/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
763 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
764 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba 765 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
db5f024e
DJ		 766 "__dl_runtime_resolve" directly. An unresolved lazy binding
767 stub will point to _dl_runtime_resolve, which will first call
c4c5b7ba
AC		 768 __dl_runtime_resolve, and then pass control to the resolved
769 function. */
6de918a6
DJ		 770
771static CORE_ADDR
772mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
773{
3b7344d5 774 struct bound_minimal_symbol resolver;
6de918a6
DJ		 775
776 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
777
77e371c0 778 if (resolver.minsym && BMSYMBOL_VALUE_ADDRESS (resolver) == pc)
c7ce8faa 779 return frame_unwind_caller_pc (get_current_frame ());
6de918a6 780
db5f024e 781 return glibc_skip_solib_resolver (gdbarch, pc);
295093a4 782}
6de918a6 783
5792a79b
DJ		 784/* Signal trampoline support. There are four supported layouts for a
785 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
786 n64 rt_sigframe. We handle them all independently; not the most
787 efficient way, but simplest. First, declare all the unwinders. */
788
789static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 790 struct frame_info *this_frame,
5792a79b
DJ		 791 struct trad_frame_cache *this_cache,
792 CORE_ADDR func);
793
794static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 795 struct frame_info *this_frame,
5792a79b
DJ		 796 struct trad_frame_cache *this_cache,
797 CORE_ADDR func);
798
858339f2
MR		 799static int mips_linux_sigframe_validate (const struct tramp_frame *self,
800 struct frame_info *this_frame,
801 CORE_ADDR *pc);
802
803static int micromips_linux_sigframe_validate (const struct tramp_frame *self,
804 struct frame_info *this_frame,
805 CORE_ADDR *pc);
806
5792a79b
DJ		 807#define MIPS_NR_LINUX 4000
808#define MIPS_NR_N64_LINUX 5000
809#define MIPS_NR_N32_LINUX 6000
810
811#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
812#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
813#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
814#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
815
816#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
817#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
818#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
819#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
820#define MIPS_INST_SYSCALL 0x0000000c
821
858339f2
MR		 822#define MICROMIPS_INST_LI_V0 0x3040
823#define MICROMIPS_INST_POOL32A 0x0000
824#define MICROMIPS_INST_SYSCALL 0x8b7c
825
2cd8546d
AC		 826static const struct tramp_frame mips_linux_o32_sigframe = {
827 SIGTRAMP_FRAME,
5792a79b 828 4,
2cd8546d
AC		 829 {
830 { MIPS_INST_LI_V0_SIGRETURN, -1 },
831 { MIPS_INST_SYSCALL, -1 },
832 { TRAMP_SENTINEL_INSN, -1 }
833 },
858339f2
MR		 834 mips_linux_o32_sigframe_init,
835 mips_linux_sigframe_validate
5792a79b
DJ		 836};
837
2cd8546d
AC		 838static const struct tramp_frame mips_linux_o32_rt_sigframe = {
839 SIGTRAMP_FRAME,
5792a79b 840 4,
2cd8546d
AC		 841 {
842 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
843 { MIPS_INST_SYSCALL, -1 },
844 { TRAMP_SENTINEL_INSN, -1 } },
858339f2
MR		 845 mips_linux_o32_sigframe_init,
846 mips_linux_sigframe_validate
5792a79b
DJ		 847};
848
2cd8546d
AC		 849static const struct tramp_frame mips_linux_n32_rt_sigframe = {
850 SIGTRAMP_FRAME,
5792a79b 851 4,
2cd8546d
AC		 852 {
853 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
854 { MIPS_INST_SYSCALL, -1 },
855 { TRAMP_SENTINEL_INSN, -1 }
856 },
858339f2
MR		 857 mips_linux_n32n64_sigframe_init,
858 mips_linux_sigframe_validate
5792a79b
DJ		 859};
860
2cd8546d
AC		 861static const struct tramp_frame mips_linux_n64_rt_sigframe = {
862 SIGTRAMP_FRAME,
5792a79b 863 4,
fcbd8a5c
TS		 864 {
865 { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 },
866 { MIPS_INST_SYSCALL, -1 },
867 { TRAMP_SENTINEL_INSN, -1 }
868 },
858339f2
MR		 869 mips_linux_n32n64_sigframe_init,
870 mips_linux_sigframe_validate
871};
872
873static const struct tramp_frame micromips_linux_o32_sigframe = {
874 SIGTRAMP_FRAME,
875 2,
876 {
877 { MICROMIPS_INST_LI_V0, -1 },
878 { MIPS_NR_sigreturn, -1 },
879 { MICROMIPS_INST_POOL32A, -1 },
880 { MICROMIPS_INST_SYSCALL, -1 },
881 { TRAMP_SENTINEL_INSN, -1 }
882 },
883 mips_linux_o32_sigframe_init,
884 micromips_linux_sigframe_validate
885};
886
887static const struct tramp_frame micromips_linux_o32_rt_sigframe = {
888 SIGTRAMP_FRAME,
889 2,
890 {
891 { MICROMIPS_INST_LI_V0, -1 },
892 { MIPS_NR_rt_sigreturn, -1 },
893 { MICROMIPS_INST_POOL32A, -1 },
894 { MICROMIPS_INST_SYSCALL, -1 },
895 { TRAMP_SENTINEL_INSN, -1 }
896 },
897 mips_linux_o32_sigframe_init,
898 micromips_linux_sigframe_validate
899};
900
901static const struct tramp_frame micromips_linux_n32_rt_sigframe = {
902 SIGTRAMP_FRAME,
903 2,
904 {
905 { MICROMIPS_INST_LI_V0, -1 },
906 { MIPS_NR_N32_rt_sigreturn, -1 },
907 { MICROMIPS_INST_POOL32A, -1 },
908 { MICROMIPS_INST_SYSCALL, -1 },
909 { TRAMP_SENTINEL_INSN, -1 }
910 },
911 mips_linux_n32n64_sigframe_init,
912 micromips_linux_sigframe_validate
913};
914
915static const struct tramp_frame micromips_linux_n64_rt_sigframe = {
916 SIGTRAMP_FRAME,
917 2,
918 {
919 { MICROMIPS_INST_LI_V0, -1 },
920 { MIPS_NR_N64_rt_sigreturn, -1 },
921 { MICROMIPS_INST_POOL32A, -1 },
922 { MICROMIPS_INST_SYSCALL, -1 },
923 { TRAMP_SENTINEL_INSN, -1 }
924 },
925 mips_linux_n32n64_sigframe_init,
926 micromips_linux_sigframe_validate
5792a79b
DJ		 927};
928
929/* *INDENT-OFF* */
930/* The unwinder for o32 signal frames. The legacy structures look
931 like this:
932
933 struct sigframe {
934 u32 sf_ass[4]; [argument save space for o32]
eb195664 935 u32 sf_code[2]; [signal trampoline or fill]
5792a79b
DJ		 936 struct sigcontext sf_sc;
937 sigset_t sf_mask;
938 };
939
d0e64392
MR		 940 Pre-2.6.12 sigcontext:
941
5792a79b
DJ		 942 struct sigcontext {
943 unsigned int sc_regmask; [Unused]
944 unsigned int sc_status;
945 unsigned long long sc_pc;
946 unsigned long long sc_regs[32];
947 unsigned long long sc_fpregs[32];
948 unsigned int sc_ownedfp;
949 unsigned int sc_fpc_csr;
950 unsigned int sc_fpc_eir; [Unused]
951 unsigned int sc_used_math;
952 unsigned int sc_ssflags; [Unused]
953 [Alignment hole of four bytes]
954 unsigned long long sc_mdhi;
955 unsigned long long sc_mdlo;
956
957 unsigned int sc_cause; [Unused]
958 unsigned int sc_badvaddr; [Unused]
959
960 unsigned long sc_sigset[4]; [kernel's sigset_t]
961 };
962
d0e64392
MR		 963 Post-2.6.12 sigcontext (SmartMIPS/DSP support added):
964
965 struct sigcontext {
966 unsigned int sc_regmask; [Unused]
967 unsigned int sc_status; [Unused]
968 unsigned long long sc_pc;
969 unsigned long long sc_regs[32];
970 unsigned long long sc_fpregs[32];
971 unsigned int sc_acx;
972 unsigned int sc_fpc_csr;
973 unsigned int sc_fpc_eir; [Unused]
974 unsigned int sc_used_math;
975 unsigned int sc_dsp;
976 [Alignment hole of four bytes]
977 unsigned long long sc_mdhi;
978 unsigned long long sc_mdlo;
979 unsigned long sc_hi1;
980 unsigned long sc_lo1;
981 unsigned long sc_hi2;
982 unsigned long sc_lo2;
983 unsigned long sc_hi3;
984 unsigned long sc_lo3;
985 };
986
5792a79b
DJ		 987 The RT signal frames look like this:
988
989 struct rt_sigframe {
990 u32 rs_ass[4]; [argument save space for o32]
eb195664 991 u32 rs_code[2] [signal trampoline or fill]
5792a79b
DJ		 992 struct siginfo rs_info;
993 struct ucontext rs_uc;
994 };
995
996 struct ucontext {
997 unsigned long uc_flags;
998 struct ucontext *uc_link;
999 stack_t uc_stack;
1000 [Alignment hole of four bytes]
1001 struct sigcontext uc_mcontext;
1002 sigset_t uc_sigmask;
1003 }; */
1004/* *INDENT-ON* */
1005
5792a79b
DJ		 1006#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
1007
1008#define RTSIGFRAME_SIGINFO_SIZE 128
1009#define STACK_T_SIZE (3 * 4)
1010#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
1011#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1012 + RTSIGFRAME_SIGINFO_SIZE \
1013 + UCONTEXT_SIGCONTEXT_OFFSET)
1014
1015#define SIGCONTEXT_PC (1 * 8)
1016#define SIGCONTEXT_REGS (2 * 8)
1017#define SIGCONTEXT_FPREGS (34 * 8)
1018#define SIGCONTEXT_FPCSR (66 * 8 + 4)
d0e64392 1019#define SIGCONTEXT_DSPCTL (68 * 8 + 0)
5792a79b
DJ		 1020#define SIGCONTEXT_HI (69 * 8)
1021#define SIGCONTEXT_LO (70 * 8)
1022#define SIGCONTEXT_CAUSE (71 * 8 + 0)
1023#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
d0e64392
MR		 1024#define SIGCONTEXT_HI1 (71 * 8 + 0)
1025#define SIGCONTEXT_LO1 (71 * 8 + 4)
1026#define SIGCONTEXT_HI2 (72 * 8 + 0)
1027#define SIGCONTEXT_LO2 (72 * 8 + 4)
1028#define SIGCONTEXT_HI3 (73 * 8 + 0)
1029#define SIGCONTEXT_LO3 (73 * 8 + 4)
5792a79b
DJ		 1030
1031#define SIGCONTEXT_REG_SIZE 8
1032
1033static void
1034mips_linux_o32_sigframe_init (const struct tramp_frame *self,
b8a22b94 1035 struct frame_info *this_frame,
5792a79b
DJ		 1036 struct trad_frame_cache *this_cache,
1037 CORE_ADDR func)
1038{
b8a22b94 1039 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1040 int ireg;
eb195664
DD		 1041 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1042 CORE_ADDR sigcontext_base;
2eb4d78b 1043 const struct mips_regnum *regs = mips_regnum (gdbarch);
37c4d197 1044 CORE_ADDR regs_base;
5792a79b 1045
858339f2
MR		 1046 if (self == &mips_linux_o32_sigframe
1047 || self == &micromips_linux_o32_sigframe)
eb195664 1048 sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1049 else
eb195664 1050 sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 1051
1052 /* I'm not proud of this hack. Eventually we will have the
1053 infrastructure to indicate the size of saved registers on a
1054 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 1055 bytes but we only want four. Use regs_base to access any
1056 64-bit fields. */
2eb4d78b 1057 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
37c4d197
DJ		 1058 regs_base = sigcontext_base + 4;
1059 else
1060 regs_base = sigcontext_base;
5792a79b 1061
2eb4d78b 1062 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1063 trad_frame_set_reg_addr (this_cache,
1064 (MIPS_RESTART_REGNUM
2eb4d78b 1065 + gdbarch_num_regs (gdbarch)),
822b6570 1066 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 1067
1068 for (ireg = 1; ireg < 32; ireg++)
295093a4 1069 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1070 (ireg + MIPS_ZERO_REGNUM
1071 + gdbarch_num_regs (gdbarch)),
1072 (regs_base + SIGCONTEXT_REGS
1073 + ireg * SIGCONTEXT_REG_SIZE));
5792a79b 1074
37c4d197
DJ		 1075 /* The way that floating point registers are saved, unfortunately,
1076 depends on the architecture the kernel is built for. For the r3000 and
1077 tx39, four bytes of each register are at the beginning of each of the
1078 32 eight byte slots. For everything else, the registers are saved
1079 using double precision; only the even-numbered slots are initialized,
1080 and the high bits are the odd-numbered register. Assume the latter
1081 layout, since we can't tell, and it's much more common. Which bits are
1082 the "high" bits depends on endianness. */
5792a79b 1083 for (ireg = 0; ireg < 32; ireg++)
2eb4d78b 1084 if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1))
f57d151a 1085 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1086 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1087 (sigcontext_base + SIGCONTEXT_FPREGS + 4
1088 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
37c4d197 1089 else
f57d151a 1090 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1091 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1092 (sigcontext_base + SIGCONTEXT_FPREGS
1093 + (ireg & ~1) * SIGCONTEXT_REG_SIZE));
5792a79b 1094
f57d151a 1095 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1096 regs->pc + gdbarch_num_regs (gdbarch),
37c4d197 1097 regs_base + SIGCONTEXT_PC);
5792a79b 1098
295093a4 1099 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1100 (regs->fp_control_status
1101 + gdbarch_num_regs (gdbarch)),
5792a79b 1102 sigcontext_base + SIGCONTEXT_FPCSR);
d0e64392
MR		 1103
1104 if (regs->dspctl != -1)
1105 trad_frame_set_reg_addr (this_cache,
1106 regs->dspctl + gdbarch_num_regs (gdbarch),
1107 sigcontext_base + SIGCONTEXT_DSPCTL);
1108
f57d151a 1109 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1110 regs->hi + gdbarch_num_regs (gdbarch),
37c4d197 1111 regs_base + SIGCONTEXT_HI);
f57d151a 1112 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1113 regs->lo + gdbarch_num_regs (gdbarch),
37c4d197 1114 regs_base + SIGCONTEXT_LO);
d0e64392
MR		 1115
1116 if (regs->dspacc != -1)
1117 {
1118 trad_frame_set_reg_addr (this_cache,
1119 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1120 sigcontext_base + SIGCONTEXT_HI1);
1121 trad_frame_set_reg_addr (this_cache,
1122 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1123 sigcontext_base + SIGCONTEXT_LO1);
1124 trad_frame_set_reg_addr (this_cache,
1125 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1126 sigcontext_base + SIGCONTEXT_HI2);
1127 trad_frame_set_reg_addr (this_cache,
1128 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1129 sigcontext_base + SIGCONTEXT_LO2);
1130 trad_frame_set_reg_addr (this_cache,
1131 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1132 sigcontext_base + SIGCONTEXT_HI3);
1133 trad_frame_set_reg_addr (this_cache,
1134 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1135 sigcontext_base + SIGCONTEXT_LO3);
1136 }
1137 else
1138 {
1139 trad_frame_set_reg_addr (this_cache,
1140 regs->cause + gdbarch_num_regs (gdbarch),
1141 sigcontext_base + SIGCONTEXT_CAUSE);
1142 trad_frame_set_reg_addr (this_cache,
1143 regs->badvaddr + gdbarch_num_regs (gdbarch),
1144 sigcontext_base + SIGCONTEXT_BADVADDR);
1145 }
5792a79b
DJ		 1146
1147 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1148 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1149}
1150
1151/* *INDENT-OFF* */
1152/* For N32/N64 things look different. There is no non-rt signal frame.
1153
1154 struct rt_sigframe_n32 {
1155 u32 rs_ass[4]; [ argument save space for o32 ]
eb195664 1156 u32 rs_code[2]; [ signal trampoline or fill ]
5792a79b
DJ		 1157 struct siginfo rs_info;
1158 struct ucontextn32 rs_uc;
1159 };
1160
1161 struct ucontextn32 {
1162 u32 uc_flags;
1163 s32 uc_link;
1164 stack32_t uc_stack;
1165 struct sigcontext uc_mcontext;
1166 sigset_t uc_sigmask; [ mask last for extensibility ]
1167 };
295093a4 1168
e741f4d4 1169 struct rt_sigframe {
5792a79b
DJ		 1170 u32 rs_ass[4]; [ argument save space for o32 ]
1171 u32 rs_code[2]; [ signal trampoline ]
1172 struct siginfo rs_info;
1173 struct ucontext rs_uc;
1174 };
1175
1176 struct ucontext {
1177 unsigned long uc_flags;
1178 struct ucontext *uc_link;
1179 stack_t uc_stack;
1180 struct sigcontext uc_mcontext;
1181 sigset_t uc_sigmask; [ mask last for extensibility ]
1182 };
1183
1184 And the sigcontext is different (this is for both n32 and n64):
1185
1186 struct sigcontext {
1187 unsigned long long sc_regs[32];
1188 unsigned long long sc_fpregs[32];
1189 unsigned long long sc_mdhi;
e741f4d4
DJ		 1190 unsigned long long sc_hi1;
1191 unsigned long long sc_hi2;
1192 unsigned long long sc_hi3;
5792a79b 1193 unsigned long long sc_mdlo;
e741f4d4
DJ		 1194 unsigned long long sc_lo1;
1195 unsigned long long sc_lo2;
1196 unsigned long long sc_lo3;
5792a79b 1197 unsigned long long sc_pc;
5792a79b 1198 unsigned int sc_fpc_csr;
5792a79b 1199 unsigned int sc_used_math;
e741f4d4
DJ		 1200 unsigned int sc_dsp;
1201 unsigned int sc_reserved;
1202 };
1203
1204 That is the post-2.6.12 definition of the 64-bit sigcontext; before
1205 then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were
1206 included too. */
5792a79b
DJ		 1207/* *INDENT-ON* */
1208
1209#define N32_STACK_T_SIZE STACK_T_SIZE
1210#define N64_STACK_T_SIZE (2 * 8 + 4)
1211#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1212#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1213#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1214 + RTSIGFRAME_SIGINFO_SIZE \
1215 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1216#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1217 + RTSIGFRAME_SIGINFO_SIZE \
1218 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1219
1220#define N64_SIGCONTEXT_REGS (0 * 8)
1221#define N64_SIGCONTEXT_FPREGS (32 * 8)
1222#define N64_SIGCONTEXT_HI (64 * 8)
d0e64392
MR		 1223#define N64_SIGCONTEXT_HI1 (65 * 8)
1224#define N64_SIGCONTEXT_HI2 (66 * 8)
1225#define N64_SIGCONTEXT_HI3 (67 * 8)
e741f4d4 1226#define N64_SIGCONTEXT_LO (68 * 8)
d0e64392
MR		 1227#define N64_SIGCONTEXT_LO1 (69 * 8)
1228#define N64_SIGCONTEXT_LO2 (70 * 8)
1229#define N64_SIGCONTEXT_LO3 (71 * 8)
e741f4d4 1230#define N64_SIGCONTEXT_PC (72 * 8)
d0e64392
MR		 1231#define N64_SIGCONTEXT_FPCSR (73 * 8 + 0)
1232#define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0)
5792a79b
DJ		 1233
1234#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1235
5792a79b
DJ		 1236static void
1237mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
b8a22b94 1238 struct frame_info *this_frame,
5792a79b
DJ		 1239 struct trad_frame_cache *this_cache,
1240 CORE_ADDR func)
1241{
b8a22b94 1242 struct gdbarch *gdbarch = get_frame_arch (this_frame);
22e048c9 1243 int ireg;
eb195664
DD		 1244 CORE_ADDR frame_sp = get_frame_sp (this_frame);
1245 CORE_ADDR sigcontext_base;
2eb4d78b 1246 const struct mips_regnum *regs = mips_regnum (gdbarch);
5792a79b 1247
858339f2
MR		 1248 if (self == &mips_linux_n32_rt_sigframe
1249 || self == &micromips_linux_n32_rt_sigframe)
eb195664 1250 sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET;
5792a79b 1251 else
eb195664 1252 sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1253
2eb4d78b 1254 if (mips_linux_restart_reg_p (gdbarch))
822b6570
DJ		 1255 trad_frame_set_reg_addr (this_cache,
1256 (MIPS_RESTART_REGNUM
2eb4d78b 1257 + gdbarch_num_regs (gdbarch)),
822b6570 1258 sigcontext_base + N64_SIGCONTEXT_REGS);
5792a79b
DJ		 1259
1260 for (ireg = 1; ireg < 32; ireg++)
295093a4 1261 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1262 (ireg + MIPS_ZERO_REGNUM
1263 + gdbarch_num_regs (gdbarch)),
1264 (sigcontext_base + N64_SIGCONTEXT_REGS
1265 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b
DJ		 1266
1267 for (ireg = 0; ireg < 32; ireg++)
f57d151a 1268 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1269 ireg + regs->fp0 + gdbarch_num_regs (gdbarch),
1270 (sigcontext_base + N64_SIGCONTEXT_FPREGS
1271 + ireg * N64_SIGCONTEXT_REG_SIZE));
5792a79b 1272
f57d151a 1273 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1274 regs->pc + gdbarch_num_regs (gdbarch),
5792a79b
DJ		 1275 sigcontext_base + N64_SIGCONTEXT_PC);
1276
295093a4 1277 trad_frame_set_reg_addr (this_cache,
7d266584
MR		 1278 (regs->fp_control_status
1279 + gdbarch_num_regs (gdbarch)),
5792a79b 1280 sigcontext_base + N64_SIGCONTEXT_FPCSR);
d0e64392 1281
f57d151a 1282 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1283 regs->hi + gdbarch_num_regs (gdbarch),
5792a79b 1284 sigcontext_base + N64_SIGCONTEXT_HI);
f57d151a 1285 trad_frame_set_reg_addr (this_cache,
2eb4d78b 1286 regs->lo + gdbarch_num_regs (gdbarch),
5792a79b 1287 sigcontext_base + N64_SIGCONTEXT_LO);
5792a79b 1288
d0e64392
MR		 1289 if (regs->dspacc != -1)
1290 {
1291 trad_frame_set_reg_addr (this_cache,
1292 regs->dspacc + 0 + gdbarch_num_regs (gdbarch),
1293 sigcontext_base + N64_SIGCONTEXT_HI1);
1294 trad_frame_set_reg_addr (this_cache,
1295 regs->dspacc + 1 + gdbarch_num_regs (gdbarch),
1296 sigcontext_base + N64_SIGCONTEXT_LO1);
1297 trad_frame_set_reg_addr (this_cache,
1298 regs->dspacc + 2 + gdbarch_num_regs (gdbarch),
1299 sigcontext_base + N64_SIGCONTEXT_HI2);
1300 trad_frame_set_reg_addr (this_cache,
1301 regs->dspacc + 3 + gdbarch_num_regs (gdbarch),
1302 sigcontext_base + N64_SIGCONTEXT_LO2);
1303 trad_frame_set_reg_addr (this_cache,
1304 regs->dspacc + 4 + gdbarch_num_regs (gdbarch),
1305 sigcontext_base + N64_SIGCONTEXT_HI3);
1306 trad_frame_set_reg_addr (this_cache,
1307 regs->dspacc + 5 + gdbarch_num_regs (gdbarch),
1308 sigcontext_base + N64_SIGCONTEXT_LO3);
1309 }
1310 if (regs->dspctl != -1)
1311 trad_frame_set_reg_addr (this_cache,
1312 regs->dspctl + gdbarch_num_regs (gdbarch),
1313 sigcontext_base + N64_SIGCONTEXT_DSPCTL);
1314
5792a79b 1315 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
eb195664 1316 trad_frame_set_id (this_cache, frame_id_build (frame_sp, func));
5792a79b
DJ		 1317}
1318
858339f2
MR		 1319/* Implement struct tramp_frame's "validate" method for standard MIPS code. */
1320
1321static int
1322mips_linux_sigframe_validate (const struct tramp_frame *self,
1323 struct frame_info *this_frame,
1324 CORE_ADDR *pc)
1325{
1326 return mips_pc_is_mips (*pc);
1327}
1328
1329/* Implement struct tramp_frame's "validate" method for microMIPS code. */
1330
1331static int
1332micromips_linux_sigframe_validate (const struct tramp_frame *self,
1333 struct frame_info *this_frame,
1334 CORE_ADDR *pc)
1335{
3e29f34a
MR		 1336 if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc))
1337 {
1338 *pc = mips_unmake_compact_addr (*pc);
1339 return 1;
1340 }
1341 else
1342 return 0;
858339f2
MR		 1343}
1344
5a439849
MR		 1345/* Implement the "write_pc" gdbarch method. */
1346
822b6570 1347static void
61a1198a 1348mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc)
822b6570 1349{
2eb4d78b 1350 struct gdbarch *gdbarch = get_regcache_arch (regcache);
5a439849
MR		 1351
1352 mips_write_pc (regcache, pc);
822b6570
DJ		 1353
1354 /* Clear the syscall restart flag. */
2eb4d78b 1355 if (mips_linux_restart_reg_p (gdbarch))
61a1198a 1356 regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0);
822b6570
DJ		 1357}
1358
1359/* Return 1 if MIPS_RESTART_REGNUM is usable. */
1360
1361int
1362mips_linux_restart_reg_p (struct gdbarch *gdbarch)
1363{
1364 /* If we do not have a target description with registers, then
1365 MIPS_RESTART_REGNUM will not be included in the register set. */
1366 if (!tdesc_has_registers (gdbarch_target_desc (gdbarch)))
1367 return 0;
1368
1369 /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will
1370 either be GPR-sized or missing. */
1371 return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0;
1372}
9f62d0e2 1373
e38d4e1a
DJ		 1374/* When FRAME is at a syscall instruction, return the PC of the next
1375 instruction to be executed. */
1376
63807e1d 1377static CORE_ADDR
e38d4e1a
DJ		 1378mips_linux_syscall_next_pc (struct frame_info *frame)
1379{
1380 CORE_ADDR pc = get_frame_pc (frame);
1381 ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM);
1382
1383 /* If we are about to make a sigreturn syscall, use the unwinder to
1384 decode the signal frame. */
1385 if (v0 == MIPS_NR_sigreturn
1386 || v0 == MIPS_NR_rt_sigreturn
1387 || v0 == MIPS_NR_N64_rt_sigreturn
1388 || v0 == MIPS_NR_N32_rt_sigreturn)
c7ce8faa 1389 return frame_unwind_caller_pc (get_current_frame ());
e38d4e1a
DJ		 1390
1391 return pc + 4;
1392}
1393
385203ed
DD		 1394/* Return the current system call's number present in the
1395 v0 register. When the function fails, it returns -1. */
1396
1397static LONGEST
1398mips_linux_get_syscall_number (struct gdbarch *gdbarch,
1399 ptid_t ptid)
1400{
1401 struct regcache *regcache = get_thread_regcache (ptid);
1402 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1403 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1404 int regsize = register_size (gdbarch, MIPS_V0_REGNUM);
1405 /* The content of a register */
1406 gdb_byte buf[8];
1407 /* The result */
1408 LONGEST ret;
1409
1410 /* Make sure we're in a known ABI */
1411 gdb_assert (tdep->mips_abi == MIPS_ABI_O32
1412 || tdep->mips_abi == MIPS_ABI_N32
1413 || tdep->mips_abi == MIPS_ABI_N64);
1414
1415 gdb_assert (regsize <= sizeof (buf));
1416
1417 /* Getting the system call number from the register.
1418 syscall number is in v0 or $2. */
1419 regcache_cooked_read (regcache, MIPS_V0_REGNUM, buf);
1420
1421 ret = extract_signed_integer (buf, regsize, byte_order);
1422
1423 return ret;
1424}
1425
eb14d406
SDJ		 1426/* Implementation of `gdbarch_gdb_signal_to_target', as defined in
1427 gdbarch.h. */
1428
1429static int
1430mips_gdb_signal_to_target (struct gdbarch *gdbarch,
1431 enum gdb_signal signal)
1432{
1433 switch (signal)
1434 {
1435 case GDB_SIGNAL_EMT:
1436 return MIPS_LINUX_SIGEMT;
1437
1438 case GDB_SIGNAL_BUS:
1439 return MIPS_LINUX_SIGBUS;
1440
1441 case GDB_SIGNAL_SYS:
1442 return MIPS_LINUX_SIGSYS;
1443
1444 case GDB_SIGNAL_USR1:
1445 return MIPS_LINUX_SIGUSR1;
1446
1447 case GDB_SIGNAL_USR2:
1448 return MIPS_LINUX_SIGUSR2;
1449
1450 case GDB_SIGNAL_CHLD:
1451 return MIPS_LINUX_SIGCHLD;
1452
1453 case GDB_SIGNAL_PWR:
1454 return MIPS_LINUX_SIGPWR;
1455
1456 case GDB_SIGNAL_WINCH:
1457 return MIPS_LINUX_SIGWINCH;
1458
1459 case GDB_SIGNAL_URG:
1460 return MIPS_LINUX_SIGURG;
1461
1462 case GDB_SIGNAL_IO:
1463 return MIPS_LINUX_SIGIO;
1464
1465 case GDB_SIGNAL_POLL:
1466 return MIPS_LINUX_SIGPOLL;
1467
1468 case GDB_SIGNAL_STOP:
1469 return MIPS_LINUX_SIGSTOP;
1470
1471 case GDB_SIGNAL_TSTP:
1472 return MIPS_LINUX_SIGTSTP;
1473
1474 case GDB_SIGNAL_CONT:
1475 return MIPS_LINUX_SIGCONT;
1476
1477 case GDB_SIGNAL_TTIN:
1478 return MIPS_LINUX_SIGTTIN;
1479
1480 case GDB_SIGNAL_TTOU:
1481 return MIPS_LINUX_SIGTTOU;
1482
1483 case GDB_SIGNAL_VTALRM:
1484 return MIPS_LINUX_SIGVTALRM;
1485
1486 case GDB_SIGNAL_PROF:
1487 return MIPS_LINUX_SIGPROF;
1488
1489 case GDB_SIGNAL_XCPU:
1490 return MIPS_LINUX_SIGXCPU;
1491
1492 case GDB_SIGNAL_XFSZ:
1493 return MIPS_LINUX_SIGXFSZ;
1494
1495 /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>,
1496 therefore we have to handle it here. */
1497 case GDB_SIGNAL_REALTIME_32:
1498 return MIPS_LINUX_SIGRTMIN;
1499 }
1500
1501 if (signal >= GDB_SIGNAL_REALTIME_33
1502 && signal <= GDB_SIGNAL_REALTIME_63)
1503 {
1504 int offset = signal - GDB_SIGNAL_REALTIME_33;
1505
1506 return MIPS_LINUX_SIGRTMIN + 1 + offset;
1507 }
1508 else if (signal >= GDB_SIGNAL_REALTIME_64
1509 && signal <= GDB_SIGNAL_REALTIME_127)
1510 {
1511 int offset = signal - GDB_SIGNAL_REALTIME_64;
1512
1513 return MIPS_LINUX_SIGRT64 + offset;
1514 }
1515
1516 return linux_gdb_signal_to_target (gdbarch, signal);
1517}
1518
7d266584 1519/* Translate signals based on MIPS signal values.
232b8704
ME		 1520 Adapted from gdb/common/signals.c. */
1521
1522static enum gdb_signal
eb14d406 1523mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal)
232b8704 1524{
eb14d406 1525 switch (signal)
232b8704 1526 {
eb14d406 1527 case MIPS_LINUX_SIGEMT:
232b8704 1528 return GDB_SIGNAL_EMT;
eb14d406
SDJ		 1529
1530 case MIPS_LINUX_SIGBUS:
232b8704 1531 return GDB_SIGNAL_BUS;
eb14d406
SDJ		 1532
1533 case MIPS_LINUX_SIGSYS:
232b8704 1534 return GDB_SIGNAL_SYS;
eb14d406
SDJ		 1535
1536 case MIPS_LINUX_SIGUSR1:
232b8704 1537 return GDB_SIGNAL_USR1;
eb14d406
SDJ		 1538
1539 case MIPS_LINUX_SIGUSR2:
232b8704 1540 return GDB_SIGNAL_USR2;
eb14d406
SDJ		 1541
1542 case MIPS_LINUX_SIGCHLD:
232b8704 1543 return GDB_SIGNAL_CHLD;
eb14d406
SDJ		 1544
1545 case MIPS_LINUX_SIGPWR:
232b8704 1546 return GDB_SIGNAL_PWR;
eb14d406
SDJ		 1547
1548 case MIPS_LINUX_SIGWINCH:
232b8704 1549 return GDB_SIGNAL_WINCH;
eb14d406
SDJ		 1550
1551 case MIPS_LINUX_SIGURG:
232b8704 1552 return GDB_SIGNAL_URG;
eb14d406
SDJ		 1553
1554 /* No way to differentiate between SIGIO and SIGPOLL.
1555 Therefore, we just handle the first one. */
1556 case MIPS_LINUX_SIGIO:
1557 return GDB_SIGNAL_IO;
1558
1559 case MIPS_LINUX_SIGSTOP:
232b8704 1560 return GDB_SIGNAL_STOP;
eb14d406
SDJ		 1561
1562 case MIPS_LINUX_SIGTSTP:
232b8704 1563 return GDB_SIGNAL_TSTP;
eb14d406
SDJ		 1564
1565 case MIPS_LINUX_SIGCONT:
232b8704 1566 return GDB_SIGNAL_CONT;
eb14d406
SDJ		 1567
1568 case MIPS_LINUX_SIGTTIN:
232b8704 1569 return GDB_SIGNAL_TTIN;
eb14d406
SDJ		 1570
1571 case MIPS_LINUX_SIGTTOU:
232b8704 1572 return GDB_SIGNAL_TTOU;
eb14d406
SDJ		 1573
1574 case MIPS_LINUX_SIGVTALRM:
232b8704 1575 return GDB_SIGNAL_VTALRM;
eb14d406
SDJ		 1576
1577 case MIPS_LINUX_SIGPROF:
232b8704 1578 return GDB_SIGNAL_PROF;
eb14d406
SDJ		 1579
1580 case MIPS_LINUX_SIGXCPU:
232b8704 1581 return GDB_SIGNAL_XCPU;
eb14d406
SDJ		 1582
1583 case MIPS_LINUX_SIGXFSZ:
232b8704 1584 return GDB_SIGNAL_XFSZ;
eb14d406 1585 }
232b8704 1586
eb14d406 1587 if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX)
232b8704
ME		 1588 {
1589 /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of
1590 the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */
eb14d406
SDJ		 1591 int offset = signal - MIPS_LINUX_SIGRTMIN;
1592
1593 if (offset == 0)
232b8704 1594 return GDB_SIGNAL_REALTIME_32;
eb14d406
SDJ		 1595 else if (offset < 32)
1596 return (enum gdb_signal) (offset - 1
1597 + (int) GDB_SIGNAL_REALTIME_33);
232b8704 1598 else
eb14d406
SDJ		 1599 return (enum gdb_signal) (offset - 32
1600 + (int) GDB_SIGNAL_REALTIME_64);
232b8704
ME		 1601 }
1602
eb14d406 1603 return linux_gdb_signal_from_target (gdbarch, signal);
232b8704
ME		 1604}
1605
5792a79b
DJ		 1606/* Initialize one of the GNU/Linux OS ABIs. */
1607
19ed69dd 1608static void
295093a4
MS		 1609mips_linux_init_abi (struct gdbarch_info info,
1610 struct gdbarch *gdbarch)
19ed69dd 1611{
96f026fc
KB		 1612 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1613 enum mips_abi abi = mips_abi (gdbarch);
19ba03f4
SM		 1614 struct tdesc_arch_data *tdesc_data
1615 = (struct tdesc_arch_data *) info.tdep_info;
96f026fc 1616
a5ee0f0c
PA		 1617 linux_init_abi (info, gdbarch);
1618
385203ed
DD		 1619 /* Get the syscall number from the arch's register. */
1620 set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number);
1621
96f026fc
KB		 1622 switch (abi)
1623 {
1624 case MIPS_ABI_O32:
1625 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1626 mips_linux_get_longjmp_target);
96f026fc 1627 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1628 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
858339f2
MR		 1629 tramp_frame_prepend_unwinder (gdbarch, &micromips_linux_o32_sigframe);
1630 tramp_frame_prepend_unwinder (gdbarch,
1631 &micromips_linux_o32_rt_sigframe);
fb2be677
AC		 1632 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1633 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
458c8db8 1634 set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml");
96f026fc
KB		 1635 break;
1636 case MIPS_ABI_N32:
1637 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1638 mips_linux_get_longjmp_target);
96f026fc 1639 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1640 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
d05f6826
DJ		 1641 set_gdbarch_long_double_bit (gdbarch, 128);
1642 /* These floatformats should probably be renamed. MIPS uses
1643 the same 128-bit IEEE floating point format that IA-64 uses,
1644 except that the quiet/signalling NaN bit is reversed (GDB
1645 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1646 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
858339f2
MR		 1647 tramp_frame_prepend_unwinder (gdbarch,
1648 &micromips_linux_n32_rt_sigframe);
fb2be677 1649 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
458c8db8 1650 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml");
96f026fc
KB		 1651 break;
1652 case MIPS_ABI_N64:
1653 set_gdbarch_get_longjmp_target (gdbarch,
7d266584 1654 mips64_linux_get_longjmp_target);
96f026fc 1655 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1656 (gdbarch, svr4_lp64_fetch_link_map_offsets);
d05f6826
DJ		 1657 set_gdbarch_long_double_bit (gdbarch, 128);
1658 /* These floatformats should probably be renamed. MIPS uses
1659 the same 128-bit IEEE floating point format that IA-64 uses,
1660 except that the quiet/signalling NaN bit is reversed (GDB
1661 does not distinguish between quiet and signalling NaNs). */
8da61cc4 1662 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
858339f2
MR		 1663 tramp_frame_prepend_unwinder (gdbarch,
1664 &micromips_linux_n64_rt_sigframe);
fb2be677 1665 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
458c8db8 1666 set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml");
96f026fc
KB		 1667 break;
1668 default:
96f026fc
KB		 1669 break;
1670 }
6de918a6
DJ		 1671
1672 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1673
0d0266c6 1674 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1675
1676 /* Enable TLS support. */
1677 set_gdbarch_fetch_tls_load_module_address (gdbarch,
7d266584 1678 svr4_fetch_objfile_link_map);
7d522c90
DJ		 1679
1680 /* Initialize this lazily, to avoid an initialization order
1681 dependency on solib-svr4.c's _initialize routine. */
1682 if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL)
1683 {
1684 mips_svr4_so_ops = svr4_so_ops;
1685 mips_svr4_so_ops.in_dynsym_resolve_code
1686 = mips_linux_in_dynsym_resolve_code;
1687 }
1688 set_solib_ops (gdbarch, &mips_svr4_so_ops);
822b6570
DJ		 1689
1690 set_gdbarch_write_pc (gdbarch, mips_linux_write_pc);
1691
4eb0ad19
DJ		 1692 set_gdbarch_core_read_description (gdbarch,
1693 mips_linux_core_read_description);
1694
d4036235
AA		 1695 set_gdbarch_iterate_over_regset_sections
1696 (gdbarch, mips_linux_iterate_over_regset_sections);
50e8a0d5 1697
232b8704
ME		 1698 set_gdbarch_gdb_signal_from_target (gdbarch,
1699 mips_gdb_signal_from_target);
1700
eb14d406
SDJ		 1701 set_gdbarch_gdb_signal_to_target (gdbarch,
1702 mips_gdb_signal_to_target);
1703
e38d4e1a
DJ		 1704 tdep->syscall_next_pc = mips_linux_syscall_next_pc;
1705
822b6570
DJ		 1706 if (tdesc_data)
1707 {
1708 const struct tdesc_feature *feature;
1709
1710 /* If we have target-described registers, then we can safely
1711 reserve a number for MIPS_RESTART_REGNUM (whether it is
1712 described or not). */
1713 gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM);
1714 set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
cf233303 1715 set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1);
822b6570
DJ		 1716
1717 /* If it's present, then assign it to the reserved number. */
1718 feature = tdesc_find_feature (info.target_desc,
1719 "org.gnu.gdb.mips.linux");
1720 if (feature != NULL)
1721 tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM,
1722 "restart");
1723 }
19ed69dd
KB		 1724}
1725
63807e1d
PA		 1726/* Provide a prototype to silence -Wmissing-prototypes. */
1727extern initialize_file_ftype _initialize_mips_linux_tdep;
1728
2aa830e4 1729void
d1bacddc 1730_initialize_mips_linux_tdep (void)
2aa830e4 1731{
96f026fc
KB		 1732 const struct bfd_arch_info *arch_info;
1733
96f026fc
KB		 1734 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1735 arch_info != NULL;
1736 arch_info = arch_info->next)
1737 {
295093a4
MS		 1738 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1739 GDB_OSABI_LINUX,
96f026fc
KB		 1740 mips_linux_init_abi);
1741 }
2aa830e4 1742}
GDB Binutils - Deliverables
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