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import gdb-1999-10-04 snapshot
[deliverable/binutils-gdb.git] / gdb / mips-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
53a5351d 2 Copyright 1988-1999, Free Software Foundation, Inc.
c906108c
SS		 3 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
4 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
c906108c 12
c5aa993b
JM		 13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b
JM		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
c906108c
SS		 22
23#include "defs.h"
24#include "gdb_string.h"
25#include "frame.h"
26#include "inferior.h"
27#include "symtab.h"
28#include "value.h"
29#include "gdbcmd.h"
30#include "language.h"
31#include "gdbcore.h"
32#include "symfile.h"
33#include "objfiles.h"
34#include "gdbtypes.h"
35#include "target.h"
36
37#include "opcode/mips.h"
38
cce74817 39struct frame_extra_info
c5aa993b
JM		 40 {
41 mips_extra_func_info_t proc_desc;
42 int num_args;
43 };
cce74817 44
7a292a7a
SS		 45/* Some MIPS boards don't support floating point while others only
46 support single-precision floating-point operations. See also
47 FP_REGISTER_DOUBLE. */
c906108c
SS		 48
49enum mips_fpu_type
c5aa993b
JM		 50 {
51 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
52 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
53 MIPS_FPU_NONE /* No floating point. */
54 };
c906108c
SS		 55
56#ifndef MIPS_DEFAULT_FPU_TYPE
57#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
58#endif
59static int mips_fpu_type_auto = 1;
60static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
61#define MIPS_FPU_TYPE mips_fpu_type
62
7a292a7a
SS		 63#ifndef MIPS_SAVED_REGSIZE
64#define MIPS_SAVED_REGSIZE MIPS_REGSIZE
65#endif
c906108c
SS		 66
67/* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
7a292a7a 68#ifndef FP_REGISTER_DOUBLE
c906108c 69#define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
7a292a7a
SS		 70#endif
71
72
73#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
c906108c
SS		 74
75#if 0
76static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR));
77#endif
78
79int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *));
80
81static void mips_print_register PARAMS ((int, int));
82
83static mips_extra_func_info_t
c5aa993b 84 heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *));
c906108c
SS		 85
86static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR));
87
88static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int));
89
c906108c
SS		 90int mips_set_processor_type PARAMS ((char *));
91
92static void mips_show_processor_type_command PARAMS ((char *, int));
93
94static void reinit_frame_cache_sfunc PARAMS ((char *, int,
95 struct cmd_list_element *));
96
97static mips_extra_func_info_t
c5aa993b 98 find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info * next_frame));
c906108c
SS		 99
100static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc,
101 mips_extra_func_info_t proc_desc));
102
103/* This value is the model of MIPS in use. It is derived from the value
104 of the PrID register. */
105
106char *mips_processor_type;
107
108char *tmp_mips_processor_type;
109
110/* A set of original names, to be used when restoring back to generic
111 registers from a specific set. */
112
cce74817
JM		 113char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES;
114char **mips_processor_reg_names = mips_generic_reg_names;
115
116char *
117mips_register_name (i)
118 int i;
119{
120 return mips_processor_reg_names[i];
121}
9846de1b 122/* *INDENT-OFF* */
c906108c
SS		 123/* Names of IDT R3041 registers. */
124
125char *mips_r3041_reg_names[] = {
126 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
127 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
128 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
129 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
130 "sr", "lo", "hi", "bad", "cause","pc",
131 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
132 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
133 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
134 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
135 "fsr", "fir", "fp", "",
136 "", "", "bus", "ccfg", "", "", "", "",
137 "", "", "port", "cmp", "", "", "epc", "prid",
138};
139
140/* Names of IDT R3051 registers. */
141
142char *mips_r3051_reg_names[] = {
143 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
144 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
145 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
146 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
147 "sr", "lo", "hi", "bad", "cause","pc",
148 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
149 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
150 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
151 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
152 "fsr", "fir", "fp", "",
153 "inx", "rand", "elo", "", "ctxt", "", "", "",
154 "", "", "ehi", "", "", "", "epc", "prid",
155};
156
157/* Names of IDT R3081 registers. */
158
159char *mips_r3081_reg_names[] = {
160 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
161 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
162 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
163 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
164 "sr", "lo", "hi", "bad", "cause","pc",
165 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
166 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
167 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
168 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
169 "fsr", "fir", "fp", "",
170 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
171 "", "", "ehi", "", "", "", "epc", "prid",
172};
173
174/* Names of LSI 33k registers. */
175
176char *mips_lsi33k_reg_names[] = {
177 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
178 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
179 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
180 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
181 "epc", "hi", "lo", "sr", "cause","badvaddr",
182 "dcic", "bpc", "bda", "", "", "", "", "",
183 "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "",
185 "", "", "", "", "", "", "", "",
186 "", "", "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
189};
190
191struct {
192 char *name;
193 char **regnames;
194} mips_processor_type_table[] = {
195 { "generic", mips_generic_reg_names },
196 { "r3041", mips_r3041_reg_names },
197 { "r3051", mips_r3051_reg_names },
198 { "r3071", mips_r3081_reg_names },
199 { "r3081", mips_r3081_reg_names },
200 { "lsi33k", mips_lsi33k_reg_names },
201 { NULL, NULL }
202};
9846de1b 203/* *INDENT-ON* */
c906108c 204
c5aa993b
JM		 205
206
207
c906108c 208/* Table to translate MIPS16 register field to actual register number. */
c5aa993b
JM		 209static int mips16_to_32_reg[8] =
210{16, 17, 2, 3, 4, 5, 6, 7};
c906108c
SS		 211
212/* Heuristic_proc_start may hunt through the text section for a long
213 time across a 2400 baud serial line. Allows the user to limit this
214 search. */
215
216static unsigned int heuristic_fence_post = 0;
217
c5aa993b
JM		 218#define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
219#define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
c906108c
SS		 220#define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
221#define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
222#define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
223#define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
224#define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
225#define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
226#define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
227#define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
228#define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
229#define _PROC_MAGIC_ 0x0F0F0F0F
230#define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
231#define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
232
233struct linked_proc_info
c5aa993b
JM		 234 {
235 struct mips_extra_func_info info;
236 struct linked_proc_info *next;
237 }
238 *linked_proc_desc_table = NULL;
c906108c 239
cce74817
JM		 240void
241mips_print_extra_frame_info (fi)
242 struct frame_info *fi;
243{
244 if (fi
245 && fi->extra_info
246 && fi->extra_info->proc_desc
247 && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS)
d4f3574e 248 printf_filtered (" frame pointer is at %s+%s\n",
cce74817 249 REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg),
d4f3574e 250 paddr_d (fi->extra_info->proc_desc->pdr.frameoffset));
cce74817 251}
c906108c 252
43e526b9
JM		 253/* Convert between RAW and VIRTUAL registers. The RAW register size
254 defines the remote-gdb packet. */
255
256static int mips64_transfers_32bit_regs_p = 0;
257
258int
259mips_register_raw_size (reg_nr)
260 int reg_nr;
261{
262 if (mips64_transfers_32bit_regs_p)
263 return REGISTER_VIRTUAL_SIZE (reg_nr);
264 else
265 return MIPS_REGSIZE;
266}
267
268int
269mips_register_convertible (reg_nr)
270 int reg_nr;
271{
272 if (mips64_transfers_32bit_regs_p)
273 return 0;
274 else
275 return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr));
276}
277
278void
279mips_register_convert_to_virtual (n, virtual_type, raw_buf, virt_buf)
280 int n;
281 struct type *virtual_type;
282 char *raw_buf;
283 char *virt_buf;
284{
285 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
286 memcpy (virt_buf,
287 raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
288 TYPE_LENGTH (virtual_type));
289 else
290 memcpy (virt_buf,
291 raw_buf,
292 TYPE_LENGTH (virtual_type));
293}
294
295void
296mips_register_convert_to_raw (virtual_type, n, virt_buf, raw_buf)
297 struct type *virtual_type;
298 int n;
299 char *virt_buf;
300 char *raw_buf;
301{
302 memset (raw_buf, 0, REGISTER_RAW_SIZE (n));
303 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
304 memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)),
305 virt_buf,
306 TYPE_LENGTH (virtual_type));
307 else
308 memcpy (raw_buf,
309 virt_buf,
310 TYPE_LENGTH (virtual_type));
311}
312
c906108c
SS		 313/* Should the upper word of 64-bit addresses be zeroed? */
314static int mask_address_p = 1;
315
316/* Should call_function allocate stack space for a struct return? */
317int
318mips_use_struct_convention (gcc_p, type)
319 int gcc_p;
320 struct type *type;
321{
322 if (MIPS_EABI)
7a292a7a 323 return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE);
c906108c 324 else
c5aa993b 325 return 1; /* Structures are returned by ref in extra arg0 */
c906108c
SS		 326}
327
328/* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
329
330static int
331pc_is_mips16 (bfd_vma memaddr)
332{
333 struct minimal_symbol *sym;
334
335 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
336 if (IS_MIPS16_ADDR (memaddr))
337 return 1;
338
339 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
340 the high bit of the info field. Use this to decide if the function is
341 MIPS16 or normal MIPS. */
342 sym = lookup_minimal_symbol_by_pc (memaddr);
343 if (sym)
344 return MSYMBOL_IS_SPECIAL (sym);
345 else
346 return 0;
347}
348
349
350/* This returns the PC of the first inst after the prologue. If we can't
351 find the prologue, then return 0. */
352
353static CORE_ADDR
354after_prologue (pc, proc_desc)
355 CORE_ADDR pc;
356 mips_extra_func_info_t proc_desc;
357{
358 struct symtab_and_line sal;
359 CORE_ADDR func_addr, func_end;
360
361 if (!proc_desc)
362 proc_desc = find_proc_desc (pc, NULL);
363
364 if (proc_desc)
365 {
366 /* If function is frameless, then we need to do it the hard way. I
c5aa993b 367 strongly suspect that frameless always means prologueless... */
c906108c
SS		 368 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
369 && PROC_FRAME_OFFSET (proc_desc) == 0)
370 return 0;
371 }
372
373 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
374 return 0; /* Unknown */
375
376 sal = find_pc_line (func_addr, 0);
377
378 if (sal.end < func_end)
379 return sal.end;
380
381 /* The line after the prologue is after the end of the function. In this
382 case, tell the caller to find the prologue the hard way. */
383
384 return 0;
385}
386
387/* Decode a MIPS32 instruction that saves a register in the stack, and
388 set the appropriate bit in the general register mask or float register mask
389 to indicate which register is saved. This is a helper function
390 for mips_find_saved_regs. */
391
392static void
393mips32_decode_reg_save (inst, gen_mask, float_mask)
394 t_inst inst;
395 unsigned long *gen_mask;
396 unsigned long *float_mask;
397{
398 int reg;
399
400 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
401 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
402 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
403 {
404 /* It might be possible to use the instruction to
c5aa993b
JM		 405 find the offset, rather than the code below which
406 is based on things being in a certain order in the
407 frame, but figuring out what the instruction's offset
408 is relative to might be a little tricky. */
c906108c
SS		 409 reg = (inst & 0x001f0000) >> 16;
410 *gen_mask |= (1 << reg);
411 }
412 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
c5aa993b
JM		 413 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
414 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
c906108c
SS		 415
416 {
417 reg = ((inst & 0x001f0000) >> 16);
418 *float_mask |= (1 << reg);
419 }
420}
421
422/* Decode a MIPS16 instruction that saves a register in the stack, and
423 set the appropriate bit in the general register or float register mask
424 to indicate which register is saved. This is a helper function
425 for mips_find_saved_regs. */
426
427static void
428mips16_decode_reg_save (inst, gen_mask)
429 t_inst inst;
430 unsigned long *gen_mask;
431{
c5aa993b 432 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
c906108c
SS		 433 {
434 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
435 *gen_mask |= (1 << reg);
436 }
c5aa993b 437 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
c906108c
SS		 438 {
439 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
440 *gen_mask |= (1 << reg);
441 }
c5aa993b 442 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
c906108c
SS		 443 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
444 *gen_mask |= (1 << RA_REGNUM);
445}
446
447
448/* Fetch and return instruction from the specified location. If the PC
449 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
450
451static t_inst
452mips_fetch_instruction (addr)
c5aa993b 453 CORE_ADDR addr;
c906108c
SS		 454{
455 char buf[MIPS_INSTLEN];
456 int instlen;
457 int status;
458
459 if (pc_is_mips16 (addr))
460 {
461 instlen = MIPS16_INSTLEN;
462 addr = UNMAKE_MIPS16_ADDR (addr);
463 }
464 else
c5aa993b 465 instlen = MIPS_INSTLEN;
c906108c
SS		 466 status = read_memory_nobpt (addr, buf, instlen);
467 if (status)
468 memory_error (status, addr);
469 return extract_unsigned_integer (buf, instlen);
470}
471
472
473/* These the fields of 32 bit mips instructions */
474#define mips32_op(x) (x >> 25)
475#define itype_op(x) (x >> 25)
476#define itype_rs(x) ((x >> 21)& 0x1f)
477#define itype_rt(x) ((x >> 16) & 0x1f)
478#define itype_immediate(x) ( x & 0xffff)
479
480#define jtype_op(x) (x >> 25)
481#define jtype_target(x) ( x & 0x03fffff)
482
483#define rtype_op(x) (x >>25)
484#define rtype_rs(x) ((x>>21) & 0x1f)
485#define rtype_rt(x) ((x>>16) & 0x1f)
c5aa993b 486#define rtype_rd(x) ((x>>11) & 0x1f)
c906108c
SS		 487#define rtype_shamt(x) ((x>>6) & 0x1f)
488#define rtype_funct(x) (x & 0x3f )
489
490static CORE_ADDR
c5aa993b
JM		 491mips32_relative_offset (unsigned long inst)
492{
493 long x;
494 x = itype_immediate (inst);
495 if (x & 0x8000) /* sign bit set */
c906108c 496 {
c5aa993b 497 x |= 0xffff0000; /* sign extension */
c906108c 498 }
c5aa993b
JM		 499 x = x << 2;
500 return x;
c906108c
SS		 501}
502
503/* Determine whate to set a single step breakpoint while considering
504 branch prediction */
505CORE_ADDR
c5aa993b
JM		 506mips32_next_pc (CORE_ADDR pc)
507{
508 unsigned long inst;
509 int op;
510 inst = mips_fetch_instruction (pc);
511 if ((inst & 0xe0000000) != 0) /* Not a special, junp or branch instruction */
512 {
513 if ((inst >> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
514 {
515 op = ((inst >> 25) & 0x03);
c906108c
SS		 516 switch (op)
517 {
c5aa993b
JM		 518 case 0:
519 goto equal_branch; /* BEQL */
520 case 1:
521 goto neq_branch; /* BNEZ */
522 case 2:
523 goto less_branch; /* BLEZ */
524 case 3:
525 goto greater_branch; /* BGTZ */
526 default:
527 pc += 4;
c906108c
SS		 528 }
529 }
c5aa993b
JM		 530 else
531 pc += 4; /* Not a branch, next instruction is easy */
c906108c
SS		 532 }
533 else
c5aa993b
JM		 534 { /* This gets way messy */
535
c906108c 536 /* Further subdivide into SPECIAL, REGIMM and other */
c5aa993b 537 switch (op = ((inst >> 26) & 0x07)) /* extract bits 28,27,26 */
c906108c 538 {
c5aa993b
JM		 539 case 0: /* SPECIAL */
540 op = rtype_funct (inst);
541 switch (op)
542 {
543 case 8: /* JR */
544 case 9: /* JALR */
545 pc = read_register (rtype_rs (inst)); /* Set PC to that address */
546 break;
547 default:
548 pc += 4;
549 }
550
551 break; /* end special */
552 case 1: /* REGIMM */
c906108c 553 {
c5aa993b
JM		 554 op = jtype_op (inst); /* branch condition */
555 switch (jtype_op (inst))
c906108c 556 {
c5aa993b
JM		 557 case 0: /* BLTZ */
558 case 2: /* BLTXL */
559 case 16: /* BLTZALL */
560 case 18: /* BLTZALL */
c906108c 561 less_branch:
c5aa993b
JM		 562 if (read_register (itype_rs (inst)) < 0)
563 pc += mips32_relative_offset (inst) + 4;
564 else
565 pc += 8; /* after the delay slot */
566 break;
567 case 1: /* GEZ */
568 case 3: /* BGEZL */
569 case 17: /* BGEZAL */
570 case 19: /* BGEZALL */
c906108c 571 greater_equal_branch:
c5aa993b
JM		 572 if (read_register (itype_rs (inst)) >= 0)
573 pc += mips32_relative_offset (inst) + 4;
574 else
575 pc += 8; /* after the delay slot */
576 break;
577 /* All of the other intructions in the REGIMM catagory */
578 default:
579 pc += 4;
c906108c
SS		 580 }
581 }
c5aa993b
JM		 582 break; /* end REGIMM */
583 case 2: /* J */
584 case 3: /* JAL */
585 {
586 unsigned long reg;
587 reg = jtype_target (inst) << 2;
588 pc = reg + ((pc + 4) & 0xf0000000);
c906108c
SS		 589 /* Whats this mysterious 0xf000000 adjustment ??? */
590 }
c5aa993b
JM		 591 break;
592 /* FIXME case JALX : */
593 {
594 unsigned long reg;
595 reg = jtype_target (inst) << 2;
596 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
c906108c
SS		 597 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
598 }
c5aa993b
JM		 599 break; /* The new PC will be alternate mode */
600 case 4: /* BEQ , BEQL */
601 equal_branch:
602 if (read_register (itype_rs (inst)) ==
603 read_register (itype_rt (inst)))
604 pc += mips32_relative_offset (inst) + 4;
605 else
606 pc += 8;
607 break;
608 case 5: /* BNE , BNEL */
609 neq_branch:
610 if (read_register (itype_rs (inst)) !=
611 read_register (itype_rs (inst)))
612 pc += mips32_relative_offset (inst) + 4;
613 else
614 pc += 8;
615 break;
616 case 6: /* BLEZ , BLEZL */
c906108c 617 less_zero_branch:
c5aa993b
JM		 618 if (read_register (itype_rs (inst) <= 0))
619 pc += mips32_relative_offset (inst) + 4;
620 else
621 pc += 8;
622 break;
623 case 7:
624 greater_branch: /* BGTZ BGTZL */
625 if (read_register (itype_rs (inst) > 0))
626 pc += mips32_relative_offset (inst) + 4;
627 else
628 pc += 8;
629 break;
630 default:
631 pc += 8;
632 } /* switch */
633 } /* else */
634 return pc;
635} /* mips32_next_pc */
c906108c
SS		 636
637/* Decoding the next place to set a breakpoint is irregular for the
638 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
639 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
640 We dont want to set a single step instruction on the extend instruction
641 either.
c5aa993b 642 */
c906108c
SS		 643
644/* Lots of mips16 instruction formats */
645/* Predicting jumps requires itype,ritype,i8type
646 and their extensions extItype,extritype,extI8type
c5aa993b 647 */
c906108c
SS		 648enum mips16_inst_fmts
649{
c5aa993b
JM		 650 itype, /* 0 immediate 5,10 */
651 ritype, /* 1 5,3,8 */
652 rrtype, /* 2 5,3,3,5 */
653 rritype, /* 3 5,3,3,5 */
654 rrrtype, /* 4 5,3,3,3,2 */
655 rriatype, /* 5 5,3,3,1,4 */
656 shifttype, /* 6 5,3,3,3,2 */
657 i8type, /* 7 5,3,8 */
658 i8movtype, /* 8 5,3,3,5 */
659 i8mov32rtype, /* 9 5,3,5,3 */
660 i64type, /* 10 5,3,8 */
661 ri64type, /* 11 5,3,3,5 */
662 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
663 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
664 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
665 extRRItype, /* 15 5,5,5,5,3,3,5 */
666 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
667 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
668 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
669 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
670 extRi64type, /* 20 5,6,5,5,3,3,5 */
671 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
672};
c906108c
SS		 673/* I am heaping all the fields of the formats into one structure and then,
674 only the fields which are involved in instruction extension */
675struct upk_mips16
c5aa993b
JM		 676 {
677 unsigned short inst;
678 enum mips16_inst_fmts fmt;
679 unsigned long offset;
680 unsigned int regx; /* Function in i8 type */
681 unsigned int regy;
682 };
c906108c
SS		 683
684
685
c5aa993b
JM		 686static void
687print_unpack (char *comment,
688 struct upk_mips16 *u)
c906108c 689{
d4f3574e
SS		 690 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
691 comment, u->inst, u->fmt, paddr (u->offset), u->regx, u->regy);
c906108c
SS		 692}
693
694/* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
695 format for the bits which make up the immediatate extension.
c5aa993b 696 */
c906108c 697static unsigned long
c5aa993b 698extended_offset (unsigned long extension)
c906108c 699{
c5aa993b
JM		 700 unsigned long value;
701 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
702 value = value << 6;
703 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
704 value = value << 5;
705 value |= extension & 0x01f; /* extract 4:0 */
706 return value;
c906108c
SS		 707}
708
709/* Only call this function if you know that this is an extendable
710 instruction, It wont malfunction, but why make excess remote memory references?
711 If the immediate operands get sign extended or somthing, do it after
712 the extension is performed.
c5aa993b 713 */
c906108c
SS		 714/* FIXME: Every one of these cases needs to worry about sign extension
715 when the offset is to be used in relative addressing */
716
717
c5aa993b
JM		 718static unsigned short
719fetch_mips_16 (CORE_ADDR pc)
c906108c 720{
c5aa993b
JM		 721 char buf[8];
722 pc &= 0xfffffffe; /* clear the low order bit */
723 target_read_memory (pc, buf, 2);
724 return extract_unsigned_integer (buf, 2);
c906108c
SS		 725}
726
727static void
c5aa993b
JM		 728unpack_mips16 (CORE_ADDR pc,
729 struct upk_mips16 *upk)
c906108c 730{
c5aa993b
JM		 731 CORE_ADDR extpc;
732 unsigned long extension;
733 int extended;
734 extpc = (pc - 4) & ~0x01; /* Extensions are 32 bit instructions */
c906108c
SS		 735 /* Decrement to previous address and loose the 16bit mode flag */
736 /* return if the instruction was extendable, but not actually extended */
c5aa993b
JM		 737 extended = ((mips32_op (extension) == 30) ? 1 : 0);
738 if (extended)
739 {
740 extension = mips_fetch_instruction (extpc);
741 }
c906108c
SS		 742 switch (upk->fmt)
743 {
c5aa993b 744 case itype:
c906108c 745 {
c5aa993b 746 unsigned long value;
c906108c 747 if (extended)
c5aa993b
JM		 748 {
749 value = extended_offset (extension);
750 value = value << 11; /* rom for the original value */
751 value |= upk->inst & 0x7ff; /* eleven bits from instruction */
c906108c
SS		 752 }
753 else
c5aa993b
JM		 754 {
755 value = upk->inst & 0x7ff;
756 /* FIXME : Consider sign extension */
c906108c 757 }
c5aa993b 758 upk->offset = value;
c906108c 759 }
c5aa993b
JM		 760 break;
761 case ritype:
762 case i8type:
763 { /* A register identifier and an offset */
c906108c
SS		 764 /* Most of the fields are the same as I type but the
765 immediate value is of a different length */
c5aa993b 766 unsigned long value;
c906108c
SS		 767 if (extended)
768 {
c5aa993b
JM		 769 value = extended_offset (extension);
770 value = value << 8; /* from the original instruction */
771 value |= upk->inst & 0xff; /* eleven bits from instruction */
772 upk->regx = (extension >> 8) & 0x07; /* or i8 funct */
773 if (value & 0x4000) /* test the sign bit , bit 26 */
774 {
775 value &= ~0x3fff; /* remove the sign bit */
776 value = -value;
c906108c
SS		 777 }
778 }
c5aa993b
JM		 779 else
780 {
781 value = upk->inst & 0xff; /* 8 bits */
782 upk->regx = (upk->inst >> 8) & 0x07; /* or i8 funct */
783 /* FIXME: Do sign extension , this format needs it */
784 if (value & 0x80) /* THIS CONFUSES ME */
785 {
786 value &= 0xef; /* remove the sign bit */
787 value = -value;
788 }
789
790 }
791 upk->offset = value;
792 break;
c906108c 793 }
c5aa993b 794 case jalxtype:
c906108c 795 {
c5aa993b
JM		 796 unsigned long value;
797 unsigned short nexthalf;
798 value = ((upk->inst & 0x1f) << 5) | ((upk->inst >> 5) & 0x1f);
799 value = value << 16;
800 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
801 value |= nexthalf;
802 upk->offset = value;
803 break;
c906108c
SS		 804 }
805 default:
c5aa993b
JM		 806 printf_filtered ("Decoding unimplemented instruction format type\n");
807 break;
c906108c
SS		 808 }
809 /* print_unpack("UPK",upk) ; */
810}
811
812
813#define mips16_op(x) (x >> 11)
814
815/* This is a map of the opcodes which ae known to perform branches */
816static unsigned char map16[32] =
c5aa993b
JM		 817{0, 0, 1, 1, 1, 1, 0, 0,
818 0, 0, 0, 0, 1, 0, 0, 0,
819 0, 0, 0, 0, 0, 0, 0, 0,
820 0, 0, 0, 0, 0, 1, 1, 0
821};
c906108c 822
c5aa993b
JM		 823static CORE_ADDR
824add_offset_16 (CORE_ADDR pc, int offset)
c906108c 825{
c5aa993b
JM		 826 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
827
c906108c
SS		 828}
829
830
831
c5aa993b 832static struct upk_mips16 upk;
c906108c 833
c5aa993b
JM		 834CORE_ADDR
835mips16_next_pc (CORE_ADDR pc)
c906108c 836{
c5aa993b
JM		 837 int op;
838 t_inst inst;
c906108c 839 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
c5aa993b
JM		 840 inst = fetch_mips_16 (pc);
841 upk.inst = inst;
842 op = mips16_op (upk.inst);
c906108c
SS		 843 if (map16[op])
844 {
c5aa993b 845 int reg;
c906108c
SS		 846 switch (op)
847 {
c5aa993b
JM		 848 case 2: /* Branch */
849 upk.fmt = itype;
850 unpack_mips16 (pc, &upk);
851 {
852 long offset;
853 offset = upk.offset;
c906108c 854 if (offset & 0x800)
c5aa993b
JM		 855 {
856 offset &= 0xeff;
857 offset = -offset;
c906108c 858 }
c5aa993b 859 pc += (offset << 1) + 2;
c906108c 860 }
c5aa993b
JM		 861 break;
862 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
863 upk.fmt = jalxtype;
864 unpack_mips16 (pc, &upk);
865 pc = add_offset_16 (pc, upk.offset);
866 if ((upk.inst >> 10) & 0x01) /* Exchange mode */
867 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
868 else
869 pc |= 0x01;
870 break;
871 case 4: /* beqz */
872 upk.fmt = ritype;
873 unpack_mips16 (pc, &upk);
874 reg = read_register (upk.regx);
875 if (reg == 0)
876 pc += (upk.offset << 1) + 2;
877 else
878 pc += 2;
879 break;
880 case 5: /* bnez */
881 upk.fmt = ritype;
882 unpack_mips16 (pc, &upk);
883 reg = read_register (upk.regx);
884 if (reg != 0)
885 pc += (upk.offset << 1) + 2;
886 else
887 pc += 2;
888 break;
889 case 12: /* I8 Formats btez btnez */
890 upk.fmt = i8type;
891 unpack_mips16 (pc, &upk);
892 /* upk.regx contains the opcode */
893 reg = read_register (24); /* Test register is 24 */
894 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
895 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
896 /* pc = add_offset_16(pc,upk.offset) ; */
897 pc += (upk.offset << 1) + 2;
898 else
899 pc += 2;
900 break;
901 case 29: /* RR Formats JR, JALR, JALR-RA */
902 upk.fmt = rrtype;
903 op = upk.inst & 0x1f;
c906108c 904 if (op == 0)
c5aa993b
JM		 905 {
906 upk.regx = (upk.inst >> 8) & 0x07;
907 upk.regy = (upk.inst >> 5) & 0x07;
c906108c
SS		 908 switch (upk.regy)
909 {
c5aa993b
JM		 910 case 0:
911 reg = upk.regx;
912 break;
913 case 1:
914 reg = 31;
915 break; /* Function return instruction */
916 case 2:
917 reg = upk.regx;
918 break;
919 default:
920 reg = 31;
921 break; /* BOGUS Guess */
c906108c 922 }
c5aa993b 923 pc = read_register (reg);
c906108c 924 }
c5aa993b
JM		 925 else
926 pc += 2;
927 break;
928 case 30: /* This is an extend instruction */
929 pc += 4; /* Dont be setting breakpints on the second half */
930 break;
931 default:
932 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
933 pc += 2;
934 break;
c906108c
SS		 935 }
936 }
c5aa993b
JM		 937 else
938 pc += 2; /* just a good old instruction */
c906108c
SS		 939 /* See if we CAN actually break on the next instruction */
940 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
c5aa993b
JM		 941 return pc;
942} /* mips16_next_pc */
c906108c
SS		 943
944/* The mips_next_pc function supports single_tep when the remote target monitor or
945 stub is not developed enough to so a single_step.
946 It works by decoding the current instruction and predicting where a branch
947 will go. This isnt hard because all the data is available.
948 The MIPS32 and MIPS16 variants are quite different
c5aa993b
JM		 949 */
950CORE_ADDR
951mips_next_pc (CORE_ADDR pc)
c906108c 952{
c5aa993b 953 t_inst inst;
c906108c
SS		 954 /* inst = mips_fetch_instruction(pc) ; */
955 /* if (pc_is_mips16) <----- This is failing */
c5aa993b
JM		 956 if (pc & 0x01)
957 return mips16_next_pc (pc);
958 else
959 return mips32_next_pc (pc);
960} /* mips_next_pc */
c906108c
SS		 961
962/* Guaranteed to set fci->saved_regs to some values (it never leaves it
963 NULL). */
964
965void
966mips_find_saved_regs (fci)
967 struct frame_info *fci;
968{
969 int ireg;
970 CORE_ADDR reg_position;
971 /* r0 bit means kernel trap */
972 int kernel_trap;
973 /* What registers have been saved? Bitmasks. */
974 unsigned long gen_mask, float_mask;
975 mips_extra_func_info_t proc_desc;
976 t_inst inst;
977
978 frame_saved_regs_zalloc (fci);
979
980 /* If it is the frame for sigtramp, the saved registers are located
981 in a sigcontext structure somewhere on the stack.
982 If the stack layout for sigtramp changes we might have to change these
983 constants and the companion fixup_sigtramp in mdebugread.c */
984#ifndef SIGFRAME_BASE
985/* To satisfy alignment restrictions, sigcontext is located 4 bytes
986 above the sigtramp frame. */
987#define SIGFRAME_BASE MIPS_REGSIZE
988/* FIXME! Are these correct?? */
989#define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
990#define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
991#define SIGFRAME_FPREGSAVE_OFF \
992 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
993#endif
994#ifndef SIGFRAME_REG_SIZE
995/* FIXME! Is this correct?? */
996#define SIGFRAME_REG_SIZE MIPS_REGSIZE
997#endif
998 if (fci->signal_handler_caller)
999 {
1000 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1001 {
c5aa993b
JM		 1002 reg_position = fci->frame + SIGFRAME_REGSAVE_OFF
1003 + ireg * SIGFRAME_REG_SIZE;
1004 fci->saved_regs[ireg] = reg_position;
c906108c
SS		 1005 }
1006 for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
1007 {
c5aa993b
JM		 1008 reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF
1009 + ireg * SIGFRAME_REG_SIZE;
1010 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
c906108c
SS		 1011 }
1012 fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF;
1013 return;
1014 }
1015
cce74817 1016 proc_desc = fci->extra_info->proc_desc;
c906108c
SS		 1017 if (proc_desc == NULL)
1018 /* I'm not sure how/whether this can happen. Normally when we can't
1019 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1020 and set the saved_regs right away. */
1021 return;
1022
c5aa993b
JM		 1023 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1024 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1025 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
c906108c 1026
c5aa993b
JM		 1027 if ( /* In any frame other than the innermost or a frame interrupted by
1028 a signal, we assume that all registers have been saved.
1029 This assumes that all register saves in a function happen before
1030 the first function call. */
1031 (fci->next == NULL || fci->next->signal_handler_caller)
c906108c 1032
c5aa993b
JM		 1033 /* In a dummy frame we know exactly where things are saved. */
1034 && !PROC_DESC_IS_DUMMY (proc_desc)
c906108c 1035
c5aa993b
JM		 1036 /* Don't bother unless we are inside a function prologue. Outside the
1037 prologue, we know where everything is. */
c906108c 1038
c5aa993b 1039 && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc))
c906108c 1040
c5aa993b
JM		 1041 /* Not sure exactly what kernel_trap means, but if it means
1042 the kernel saves the registers without a prologue doing it,
1043 we better not examine the prologue to see whether registers
1044 have been saved yet. */
1045 && !kernel_trap)
c906108c
SS		 1046 {
1047 /* We need to figure out whether the registers that the proc_desc
c5aa993b 1048 claims are saved have been saved yet. */
c906108c
SS		 1049
1050 CORE_ADDR addr;
1051
1052 /* Bitmasks; set if we have found a save for the register. */
1053 unsigned long gen_save_found = 0;
1054 unsigned long float_save_found = 0;
1055 int instlen;
1056
1057 /* If the address is odd, assume this is MIPS16 code. */
1058 addr = PROC_LOW_ADDR (proc_desc);
1059 instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1060
1061 /* Scan through this function's instructions preceding the current
1062 PC, and look for those that save registers. */
1063 while (addr < fci->pc)
1064 {
1065 inst = mips_fetch_instruction (addr);
1066 if (pc_is_mips16 (addr))
1067 mips16_decode_reg_save (inst, &gen_save_found);
1068 else
1069 mips32_decode_reg_save (inst, &gen_save_found, &float_save_found);
1070 addr += instlen;
1071 }
1072 gen_mask = gen_save_found;
1073 float_mask = float_save_found;
1074 }
1075
1076 /* Fill in the offsets for the registers which gen_mask says
1077 were saved. */
1078 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
c5aa993b 1079 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
c906108c
SS		 1080 if (gen_mask & 0x80000000)
1081 {
1082 fci->saved_regs[ireg] = reg_position;
7a292a7a 1083 reg_position -= MIPS_SAVED_REGSIZE;
c906108c
SS		 1084 }
1085
1086 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1087 of that normally used by gcc. Therefore, we have to fetch the first
1088 instruction of the function, and if it's an entry instruction that
1089 saves $s0 or $s1, correct their saved addresses. */
1090 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1091 {
1092 inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc));
c5aa993b 1093 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
c906108c
SS		 1094 {
1095 int reg;
1096 int sreg_count = (inst >> 6) & 3;
c5aa993b 1097
c906108c
SS		 1098 /* Check if the ra register was pushed on the stack. */
1099 reg_position = fci->frame + PROC_REG_OFFSET (proc_desc);
1100 if (inst & 0x20)
7a292a7a 1101 reg_position -= MIPS_SAVED_REGSIZE;
c906108c
SS		 1102
1103 /* Check if the s0 and s1 registers were pushed on the stack. */
c5aa993b 1104 for (reg = 16; reg < sreg_count + 16; reg++)
c906108c
SS		 1105 {
1106 fci->saved_regs[reg] = reg_position;
7a292a7a 1107 reg_position -= MIPS_SAVED_REGSIZE;
c906108c
SS		 1108 }
1109 }
1110 }
1111
1112 /* Fill in the offsets for the registers which float_mask says
1113 were saved. */
1114 reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc);
1115
1116 /* The freg_offset points to where the first *double* register
1117 is saved. So skip to the high-order word. */
c5aa993b 1118 if (!GDB_TARGET_IS_MIPS64)
7a292a7a 1119 reg_position += MIPS_SAVED_REGSIZE;
c906108c
SS		 1120
1121 /* Fill in the offsets for the float registers which float_mask says
1122 were saved. */
c5aa993b 1123 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
c906108c
SS		 1124 if (float_mask & 0x80000000)
1125 {
c5aa993b 1126 fci->saved_regs[FP0_REGNUM + ireg] = reg_position;
7a292a7a 1127 reg_position -= MIPS_SAVED_REGSIZE;
c906108c
SS		 1128 }
1129
1130 fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM];
1131}
1132
1133static CORE_ADDR
c5aa993b 1134read_next_frame_reg (fi, regno)
c906108c
SS		 1135 struct frame_info *fi;
1136 int regno;
1137{
1138 for (; fi; fi = fi->next)
1139 {
1140 /* We have to get the saved sp from the sigcontext
c5aa993b 1141 if it is a signal handler frame. */
c906108c
SS		 1142 if (regno == SP_REGNUM && !fi->signal_handler_caller)
1143 return fi->frame;
1144 else
1145 {
1146 if (fi->saved_regs == NULL)
1147 mips_find_saved_regs (fi);
1148 if (fi->saved_regs[regno])
2acceee2 1149 return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE);
c906108c
SS		 1150 }
1151 }
1152 return read_register (regno);
1153}
1154
1155/* mips_addr_bits_remove - remove useless address bits */
1156
1157CORE_ADDR
1158mips_addr_bits_remove (addr)
c5aa993b 1159 CORE_ADDR addr;
c906108c
SS		 1160{
1161#if GDB_TARGET_IS_MIPS64
c5aa993b 1162 if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
c906108c
SS		 1163 {
1164 /* This hack is a work-around for existing boards using PMON,
c5aa993b
JM		 1165 the simulator, and any other 64-bit targets that doesn't have
1166 true 64-bit addressing. On these targets, the upper 32 bits
1167 of addresses are ignored by the hardware. Thus, the PC or SP
1168 are likely to have been sign extended to all 1s by instruction
1169 sequences that load 32-bit addresses. For example, a typical
1170 piece of code that loads an address is this:
1171 lui $r2, <upper 16 bits>
1172 ori $r2, <lower 16 bits>
1173 But the lui sign-extends the value such that the upper 32 bits
1174 may be all 1s. The workaround is simply to mask off these bits.
1175 In the future, gcc may be changed to support true 64-bit
1176 addressing, and this masking will have to be disabled. */
1177 addr &= (CORE_ADDR) 0xffffffff;
c906108c
SS		 1178 }
1179#else
1180 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1181 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1182 So we still have to mask off useless bits from addresses. */
c5aa993b 1183 addr &= (CORE_ADDR) 0xffffffff;
c906108c
SS		 1184#endif
1185
1186 return addr;
1187}
1188
1189void
1190mips_init_frame_pc_first (fromleaf, prev)
1191 int fromleaf;
1192 struct frame_info *prev;
1193{
1194 CORE_ADDR pc, tmp;
1195
1196 pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) :
c5aa993b 1197 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
c906108c 1198 tmp = mips_skip_stub (pc);
c5aa993b 1199 prev->pc = tmp ? tmp : pc;
c906108c
SS		 1200}
1201
1202
1203CORE_ADDR
c5aa993b 1204mips_frame_saved_pc (frame)
c906108c
SS		 1205 struct frame_info *frame;
1206{
1207 CORE_ADDR saved_pc;
cce74817 1208 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
c906108c
SS		 1209 /* We have to get the saved pc from the sigcontext
1210 if it is a signal handler frame. */
1211 int pcreg = frame->signal_handler_caller ? PC_REGNUM
c5aa993b 1212 : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM);
c906108c 1213
c5aa993b 1214 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
7a292a7a 1215 saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE);
c906108c 1216 else
7a292a7a 1217 saved_pc = read_next_frame_reg (frame, pcreg);
c906108c
SS		 1218
1219 return ADDR_BITS_REMOVE (saved_pc);
1220}
1221
1222static struct mips_extra_func_info temp_proc_desc;
cce74817 1223static CORE_ADDR temp_saved_regs[NUM_REGS];
c906108c
SS		 1224
1225/* Set a register's saved stack address in temp_saved_regs. If an address
1226 has already been set for this register, do nothing; this way we will
1227 only recognize the first save of a given register in a function prologue.
1228 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1229
1230static void
1231set_reg_offset (regno, offset)
1232 int regno;
1233 CORE_ADDR offset;
1234{
cce74817
JM		 1235 if (temp_saved_regs[regno] == 0)
1236 temp_saved_regs[regno] = offset;
c906108c
SS		 1237}
1238
1239
1240/* Test whether the PC points to the return instruction at the
1241 end of a function. */
1242
c5aa993b 1243static int
c906108c
SS		 1244mips_about_to_return (pc)
1245 CORE_ADDR pc;
1246{
1247 if (pc_is_mips16 (pc))
1248 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1249 generates a "jr $ra"; other times it generates code to load
1250 the return address from the stack to an accessible register (such
1251 as $a3), then a "jr" using that register. This second case
1252 is almost impossible to distinguish from an indirect jump
1253 used for switch statements, so we don't even try. */
1254 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1255 else
1256 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1257}
1258
1259
1260/* This fencepost looks highly suspicious to me. Removing it also
1261 seems suspicious as it could affect remote debugging across serial
1262 lines. */
1263
1264static CORE_ADDR
1265heuristic_proc_start (pc)
c5aa993b 1266 CORE_ADDR pc;
c906108c 1267{
c5aa993b
JM		 1268 CORE_ADDR start_pc;
1269 CORE_ADDR fence;
1270 int instlen;
1271 int seen_adjsp = 0;
c906108c 1272
c5aa993b
JM		 1273 pc = ADDR_BITS_REMOVE (pc);
1274 start_pc = pc;
1275 fence = start_pc - heuristic_fence_post;
1276 if (start_pc == 0)
1277 return 0;
c906108c 1278
c5aa993b
JM		 1279 if (heuristic_fence_post == UINT_MAX
1280 || fence < VM_MIN_ADDRESS)
1281 fence = VM_MIN_ADDRESS;
c906108c 1282
c5aa993b 1283 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
c906108c 1284
c5aa993b
JM		 1285 /* search back for previous return */
1286 for (start_pc -= instlen;; start_pc -= instlen)
1287 if (start_pc < fence)
1288 {
1289 /* It's not clear to me why we reach this point when
1290 stop_soon_quietly, but with this test, at least we
1291 don't print out warnings for every child forked (eg, on
1292 decstation). 22apr93 rich@cygnus.com. */
1293 if (!stop_soon_quietly)
c906108c 1294 {
c5aa993b
JM		 1295 static int blurb_printed = 0;
1296
1297 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1298 paddr_nz (pc));
1299
1300 if (!blurb_printed)
c906108c 1301 {
c5aa993b
JM		 1302 /* This actually happens frequently in embedded
1303 development, when you first connect to a board
1304 and your stack pointer and pc are nowhere in
1305 particular. This message needs to give people
1306 in that situation enough information to
1307 determine that it's no big deal. */
1308 printf_filtered ("\n\
cd0fc7c3
SS		 1309 GDB is unable to find the start of the function at 0x%s\n\
1310and thus can't determine the size of that function's stack frame.\n\
1311This means that GDB may be unable to access that stack frame, or\n\
1312the frames below it.\n\
1313 This problem is most likely caused by an invalid program counter or\n\
1314stack pointer.\n\
1315 However, if you think GDB should simply search farther back\n\
1316from 0x%s for code which looks like the beginning of a\n\
1317function, you can increase the range of the search using the `set\n\
1318heuristic-fence-post' command.\n",
c5aa993b
JM		 1319 paddr_nz (pc), paddr_nz (pc));
1320 blurb_printed = 1;
c906108c 1321 }
c906108c
SS		 1322 }
1323
c5aa993b
JM		 1324 return 0;
1325 }
1326 else if (pc_is_mips16 (start_pc))
1327 {
1328 unsigned short inst;
1329
1330 /* On MIPS16, any one of the following is likely to be the
1331 start of a function:
1332 entry
1333 addiu sp,-n
1334 daddiu sp,-n
1335 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1336 inst = mips_fetch_instruction (start_pc);
1337 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1338 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1339 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1340 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1341 break;
1342 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1343 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1344 seen_adjsp = 1;
1345 else
1346 seen_adjsp = 0;
1347 }
1348 else if (mips_about_to_return (start_pc))
1349 {
1350 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1351 break;
1352 }
1353
c906108c 1354#if 0
c5aa993b
JM		 1355 /* skip nops (usually 1) 0 - is this */
1356 while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0)
1357 start_pc += MIPS_INSTLEN;
c906108c 1358#endif
c5aa993b 1359 return start_pc;
c906108c
SS		 1360}
1361
1362/* Fetch the immediate value from a MIPS16 instruction.
1363 If the previous instruction was an EXTEND, use it to extend
1364 the upper bits of the immediate value. This is a helper function
1365 for mips16_heuristic_proc_desc. */
1366
1367static int
1368mips16_get_imm (prev_inst, inst, nbits, scale, is_signed)
c5aa993b
JM		 1369 unsigned short prev_inst; /* previous instruction */
1370 unsigned short inst; /* current instruction */
1371 int nbits; /* number of bits in imm field */
1372 int scale; /* scale factor to be applied to imm */
1373 int is_signed; /* is the imm field signed? */
c906108c
SS		 1374{
1375 int offset;
1376
1377 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1378 {
1379 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
c5aa993b 1380 if (offset & 0x8000) /* check for negative extend */
c906108c
SS		 1381 offset = 0 - (0x10000 - (offset & 0xffff));
1382 return offset | (inst & 0x1f);
1383 }
1384 else
1385 {
1386 int max_imm = 1 << nbits;
1387 int mask = max_imm - 1;
1388 int sign_bit = max_imm >> 1;
1389
1390 offset = inst & mask;
1391 if (is_signed && (offset & sign_bit))
1392 offset = 0 - (max_imm - offset);
1393 return offset * scale;
1394 }
1395}
1396
1397
1398/* Fill in values in temp_proc_desc based on the MIPS16 instruction
1399 stream from start_pc to limit_pc. */
1400
1401static void
c5aa993b
JM		 1402mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp)
1403 CORE_ADDR start_pc, limit_pc;
1404 struct frame_info *next_frame;
1405 CORE_ADDR sp;
c906108c
SS		 1406{
1407 CORE_ADDR cur_pc;
1408 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1409 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1410 unsigned inst = 0; /* current instruction */
1411 unsigned entry_inst = 0; /* the entry instruction */
1412 int reg, offset;
1413
c5aa993b
JM		 1414 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
1415 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
c906108c
SS		 1416
1417 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
1418 {
1419 /* Save the previous instruction. If it's an EXTEND, we'll extract
1420 the immediate offset extension from it in mips16_get_imm. */
1421 prev_inst = inst;
1422
1423 /* Fetch and decode the instruction. */
1424 inst = (unsigned short) mips_fetch_instruction (cur_pc);
c5aa993b 1425 if ((inst & 0xff00) == 0x6300 /* addiu sp */
c906108c
SS		 1426 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1427 {
1428 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
c5aa993b
JM		 1429 if (offset < 0) /* negative stack adjustment? */
1430 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
c906108c
SS		 1431 else
1432 /* Exit loop if a positive stack adjustment is found, which
1433 usually means that the stack cleanup code in the function
1434 epilogue is reached. */
1435 break;
1436 }
1437 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
1438 {
1439 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1440 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
c5aa993b 1441 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
c906108c
SS		 1442 set_reg_offset (reg, sp + offset);
1443 }
1444 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
1445 {
1446 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1447 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
c5aa993b 1448 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
c906108c
SS		 1449 set_reg_offset (reg, sp + offset);
1450 }
1451 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
1452 {
1453 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
c5aa993b 1454 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
c906108c
SS		 1455 set_reg_offset (RA_REGNUM, sp + offset);
1456 }
1457 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1458 {
1459 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
c5aa993b 1460 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
c906108c
SS		 1461 set_reg_offset (RA_REGNUM, sp + offset);
1462 }
c5aa993b 1463 else if (inst == 0x673d) /* move $s1, $sp */
c906108c
SS		 1464 {
1465 frame_addr = sp;
1466 PROC_FRAME_REG (&temp_proc_desc) = 17;
1467 }
1468 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
1469 {
1470 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
1471 frame_addr = sp + offset;
1472 PROC_FRAME_REG (&temp_proc_desc) = 17;
1473 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
1474 }
1475 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1476 {
1477 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
1478 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
c5aa993b 1479 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
c906108c
SS		 1480 set_reg_offset (reg, frame_addr + offset);
1481 }
1482 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1483 {
1484 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
1485 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
c5aa993b 1486 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
c906108c
SS		 1487 set_reg_offset (reg, frame_addr + offset);
1488 }
c5aa993b
JM		 1489 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1490 entry_inst = inst; /* save for later processing */
c906108c 1491 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
c5aa993b 1492 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
c906108c
SS		 1493 }
1494
c5aa993b
JM		 1495 /* The entry instruction is typically the first instruction in a function,
1496 and it stores registers at offsets relative to the value of the old SP
1497 (before the prologue). But the value of the sp parameter to this
1498 function is the new SP (after the prologue has been executed). So we
1499 can't calculate those offsets until we've seen the entire prologue,
1500 and can calculate what the old SP must have been. */
1501 if (entry_inst != 0)
1502 {
1503 int areg_count = (entry_inst >> 8) & 7;
1504 int sreg_count = (entry_inst >> 6) & 3;
c906108c 1505
c5aa993b
JM		 1506 /* The entry instruction always subtracts 32 from the SP. */
1507 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
c906108c 1508
c5aa993b
JM		 1509 /* Now we can calculate what the SP must have been at the
1510 start of the function prologue. */
1511 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
c906108c 1512
c5aa993b
JM		 1513 /* Check if a0-a3 were saved in the caller's argument save area. */
1514 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
1515 {
1516 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1517 set_reg_offset (reg, sp + offset);
1518 offset += MIPS_SAVED_REGSIZE;
1519 }
c906108c 1520
c5aa993b
JM		 1521 /* Check if the ra register was pushed on the stack. */
1522 offset = -4;
1523 if (entry_inst & 0x20)
1524 {
1525 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
1526 set_reg_offset (RA_REGNUM, sp + offset);
1527 offset -= MIPS_SAVED_REGSIZE;
1528 }
c906108c 1529
c5aa993b
JM		 1530 /* Check if the s0 and s1 registers were pushed on the stack. */
1531 for (reg = 16; reg < sreg_count + 16; reg++)
1532 {
1533 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
1534 set_reg_offset (reg, sp + offset);
1535 offset -= MIPS_SAVED_REGSIZE;
1536 }
1537 }
c906108c
SS		 1538}
1539
1540static void
c5aa993b
JM		 1541mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp)
1542 CORE_ADDR start_pc, limit_pc;
1543 struct frame_info *next_frame;
1544 CORE_ADDR sp;
c906108c
SS		 1545{
1546 CORE_ADDR cur_pc;
c5aa993b 1547 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
c906108c 1548restart:
cce74817 1549 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
c5aa993b 1550 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
c906108c
SS		 1551 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
1552 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
1553 {
1554 unsigned long inst, high_word, low_word;
1555 int reg;
1556
1557 /* Fetch the instruction. */
1558 inst = (unsigned long) mips_fetch_instruction (cur_pc);
1559
1560 /* Save some code by pre-extracting some useful fields. */
1561 high_word = (inst >> 16) & 0xffff;
1562 low_word = inst & 0xffff;
1563 reg = high_word & 0x1f;
1564
c5aa993b 1565 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
c906108c
SS		 1566 || high_word == 0x23bd /* addi $sp,$sp,-i */
1567 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
1568 {
1569 if (low_word & 0x8000) /* negative stack adjustment? */
c5aa993b 1570 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
c906108c
SS		 1571 else
1572 /* Exit loop if a positive stack adjustment is found, which
1573 usually means that the stack cleanup code in the function
1574 epilogue is reached. */
1575 break;
1576 }
1577 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1578 {
c5aa993b 1579 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
c906108c
SS		 1580 set_reg_offset (reg, sp + low_word);
1581 }
1582 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1583 {
1584 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1585 but the register size used is only 32 bits. Make the address
1586 for the saved register point to the lower 32 bits. */
c5aa993b 1587 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
c906108c
SS		 1588 set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
1589 }
c5aa993b 1590 else if (high_word == 0x27be) /* addiu $30,$sp,size */
c906108c
SS		 1591 {
1592 /* Old gcc frame, r30 is virtual frame pointer. */
c5aa993b
JM		 1593 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
1594 frame_addr = sp + low_word;
c906108c
SS		 1595 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1596 {
1597 unsigned alloca_adjust;
1598 PROC_FRAME_REG (&temp_proc_desc) = 30;
c5aa993b
JM		 1599 frame_addr = read_next_frame_reg (next_frame, 30);
1600 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
c906108c
SS		 1601 if (alloca_adjust > 0)
1602 {
1603 /* FP > SP + frame_size. This may be because
1604 * of an alloca or somethings similar.
1605 * Fix sp to "pre-alloca" value, and try again.
1606 */
1607 sp += alloca_adjust;
1608 goto restart;
1609 }
1610 }
1611 }
c5aa993b
JM		 1612 /* move $30,$sp. With different versions of gas this will be either
1613 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1614 Accept any one of these. */
c906108c
SS		 1615 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
1616 {
1617 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1618 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
1619 {
1620 unsigned alloca_adjust;
1621 PROC_FRAME_REG (&temp_proc_desc) = 30;
c5aa993b
JM		 1622 frame_addr = read_next_frame_reg (next_frame, 30);
1623 alloca_adjust = (unsigned) (frame_addr - sp);
c906108c
SS		 1624 if (alloca_adjust > 0)
1625 {
1626 /* FP > SP + frame_size. This may be because
1627 * of an alloca or somethings similar.
1628 * Fix sp to "pre-alloca" value, and try again.
1629 */
1630 sp += alloca_adjust;
1631 goto restart;
1632 }
1633 }
1634 }
c5aa993b 1635 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
c906108c 1636 {
c5aa993b 1637 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
c906108c
SS		 1638 set_reg_offset (reg, frame_addr + low_word);
1639 }
1640 }
1641}
1642
1643static mips_extra_func_info_t
c5aa993b
JM		 1644heuristic_proc_desc (start_pc, limit_pc, next_frame)
1645 CORE_ADDR start_pc, limit_pc;
1646 struct frame_info *next_frame;
c906108c
SS		 1647{
1648 CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM);
1649
c5aa993b
JM		 1650 if (start_pc == 0)
1651 return NULL;
1652 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
cce74817 1653 memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
c906108c
SS		 1654 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
1655 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
1656 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
1657
1658 if (start_pc + 200 < limit_pc)
1659 limit_pc = start_pc + 200;
1660 if (pc_is_mips16 (start_pc))
1661 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
1662 else
1663 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
1664 return &temp_proc_desc;
1665}
1666
1667static mips_extra_func_info_t
1668non_heuristic_proc_desc (pc, addrptr)
1669 CORE_ADDR pc;
1670 CORE_ADDR *addrptr;
1671{
1672 CORE_ADDR startaddr;
1673 mips_extra_func_info_t proc_desc;
c5aa993b 1674 struct block *b = block_for_pc (pc);
c906108c
SS		 1675 struct symbol *sym;
1676
1677 find_pc_partial_function (pc, NULL, &startaddr, NULL);
1678 if (addrptr)
1679 *addrptr = startaddr;
1680 if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0))
1681 sym = NULL;
1682 else
1683 {
1684 if (startaddr > BLOCK_START (b))
1685 /* This is the "pathological" case referred to in a comment in
1686 print_frame_info. It might be better to move this check into
1687 symbol reading. */
1688 sym = NULL;
1689 else
1690 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL);
1691 }
1692
1693 /* If we never found a PDR for this function in symbol reading, then
1694 examine prologues to find the information. */
1695 if (sym)
1696 {
1697 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
1698 if (PROC_FRAME_REG (proc_desc) == -1)
1699 return NULL;
1700 else
1701 return proc_desc;
1702 }
1703 else
1704 return NULL;
1705}
1706
1707
1708static mips_extra_func_info_t
1709find_proc_desc (pc, next_frame)
1710 CORE_ADDR pc;
1711 struct frame_info *next_frame;
1712{
1713 mips_extra_func_info_t proc_desc;
1714 CORE_ADDR startaddr;
1715
1716 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
1717
1718 if (proc_desc)
1719 {
1720 /* IF this is the topmost frame AND
1721 * (this proc does not have debugging information OR
1722 * the PC is in the procedure prologue)
1723 * THEN create a "heuristic" proc_desc (by analyzing
1724 * the actual code) to replace the "official" proc_desc.
1725 */
1726 if (next_frame == NULL)
1727 {
1728 struct symtab_and_line val;
1729 struct symbol *proc_symbol =
c5aa993b 1730 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
c906108c
SS		 1731
1732 if (proc_symbol)
1733 {
1734 val = find_pc_line (BLOCK_START
c5aa993b 1735 (SYMBOL_BLOCK_VALUE (proc_symbol)),
c906108c
SS		 1736 0);
1737 val.pc = val.end ? val.end : pc;
1738 }
1739 if (!proc_symbol || pc < val.pc)
1740 {
1741 mips_extra_func_info_t found_heuristic =
c5aa993b
JM		 1742 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
1743 pc, next_frame);
c906108c
SS		 1744 if (found_heuristic)
1745 proc_desc = found_heuristic;
1746 }
1747 }
1748 }
1749 else
1750 {
1751 /* Is linked_proc_desc_table really necessary? It only seems to be used
c5aa993b
JM		 1752 by procedure call dummys. However, the procedures being called ought
1753 to have their own proc_descs, and even if they don't,
1754 heuristic_proc_desc knows how to create them! */
c906108c
SS		 1755
1756 register struct linked_proc_info *link;
1757
1758 for (link = linked_proc_desc_table; link; link = link->next)
c5aa993b
JM		 1759 if (PROC_LOW_ADDR (&link->info) <= pc
1760 && PROC_HIGH_ADDR (&link->info) > pc)
c906108c
SS		 1761 return &link->info;
1762
1763 if (startaddr == 0)
1764 startaddr = heuristic_proc_start (pc);
1765
1766 proc_desc =
1767 heuristic_proc_desc (startaddr, pc, next_frame);
1768 }
1769 return proc_desc;
1770}
1771
1772static CORE_ADDR
c5aa993b
JM		 1773get_frame_pointer (frame, proc_desc)
1774 struct frame_info *frame;
1775 mips_extra_func_info_t proc_desc;
c906108c
SS		 1776{
1777 return ADDR_BITS_REMOVE (
c5aa993b
JM		 1778 read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) +
1779 PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
c906108c
SS		 1780}
1781
1782mips_extra_func_info_t cached_proc_desc;
1783
1784CORE_ADDR
c5aa993b
JM		 1785mips_frame_chain (frame)
1786 struct frame_info *frame;
c906108c
SS		 1787{
1788 mips_extra_func_info_t proc_desc;
1789 CORE_ADDR tmp;
c5aa993b 1790 CORE_ADDR saved_pc = FRAME_SAVED_PC (frame);
c906108c
SS		 1791
1792 if (saved_pc == 0 || inside_entry_file (saved_pc))
1793 return 0;
1794
1795 /* Check if the PC is inside a call stub. If it is, fetch the
1796 PC of the caller of that stub. */
1797 if ((tmp = mips_skip_stub (saved_pc)) != 0)
1798 saved_pc = tmp;
1799
1800 /* Look up the procedure descriptor for this PC. */
c5aa993b 1801 proc_desc = find_proc_desc (saved_pc, frame);
c906108c
SS		 1802 if (!proc_desc)
1803 return 0;
1804
1805 cached_proc_desc = proc_desc;
1806
1807 /* If no frame pointer and frame size is zero, we must be at end
1808 of stack (or otherwise hosed). If we don't check frame size,
1809 we loop forever if we see a zero size frame. */
1810 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
1811 && PROC_FRAME_OFFSET (proc_desc) == 0
c5aa993b
JM		 1812 /* The previous frame from a sigtramp frame might be frameless
1813 and have frame size zero. */
c906108c
SS		 1814 && !frame->signal_handler_caller)
1815 return 0;
1816 else
1817 return get_frame_pointer (frame, proc_desc);
1818}
1819
1820void
c5aa993b 1821mips_init_extra_frame_info (fromleaf, fci)
cce74817 1822 int fromleaf;
c906108c
SS		 1823 struct frame_info *fci;
1824{
1825 int regnum;
1826
1827 /* Use proc_desc calculated in frame_chain */
1828 mips_extra_func_info_t proc_desc =
c5aa993b 1829 fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next);
c906108c 1830
cce74817
JM		 1831 fci->extra_info = (struct frame_extra_info *)
1832 frame_obstack_alloc (sizeof (struct frame_extra_info));
1833
c906108c 1834 fci->saved_regs = NULL;
cce74817 1835 fci->extra_info->proc_desc =
c906108c
SS		 1836 proc_desc == &temp_proc_desc ? 0 : proc_desc;
1837 if (proc_desc)
1838 {
1839 /* Fixup frame-pointer - only needed for top frame */
1840 /* This may not be quite right, if proc has a real frame register.
c5aa993b
JM		 1841 Get the value of the frame relative sp, procedure might have been
1842 interrupted by a signal at it's very start. */
c906108c
SS		 1843 if (fci->pc == PROC_LOW_ADDR (proc_desc)
1844 && !PROC_DESC_IS_DUMMY (proc_desc))
1845 fci->frame = read_next_frame_reg (fci->next, SP_REGNUM);
1846 else
1847 fci->frame = get_frame_pointer (fci->next, proc_desc);
1848
1849 if (proc_desc == &temp_proc_desc)
1850 {
1851 char *name;
1852
1853 /* Do not set the saved registers for a sigtramp frame,
1854 mips_find_saved_registers will do that for us.
1855 We can't use fci->signal_handler_caller, it is not yet set. */
1856 find_pc_partial_function (fci->pc, &name,
c5aa993b 1857 (CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
c906108c
SS		 1858 if (!IN_SIGTRAMP (fci->pc, name))
1859 {
c5aa993b 1860 frame_saved_regs_zalloc (fci);
cce74817 1861 memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
c906108c
SS		 1862 fci->saved_regs[PC_REGNUM]
1863 = fci->saved_regs[RA_REGNUM];
1864 }
1865 }
1866
1867 /* hack: if argument regs are saved, guess these contain args */
cce74817
JM		 1868 /* assume we can't tell how many args for now */
1869 fci->extra_info->num_args = -1;
c906108c
SS		 1870 for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--)
1871 {
c5aa993b 1872 if (PROC_REG_MASK (proc_desc) & (1 << regnum))
c906108c 1873 {
cce74817 1874 fci->extra_info->num_args = regnum - A0_REGNUM + 1;
c906108c
SS		 1875 break;
1876 }
c5aa993b 1877 }
c906108c
SS		 1878 }
1879}
1880
1881/* MIPS stack frames are almost impenetrable. When execution stops,
1882 we basically have to look at symbol information for the function
1883 that we stopped in, which tells us *which* register (if any) is
1884 the base of the frame pointer, and what offset from that register
1885 the frame itself is at.
1886
1887 This presents a problem when trying to examine a stack in memory
1888 (that isn't executing at the moment), using the "frame" command. We
1889 don't have a PC, nor do we have any registers except SP.
1890
1891 This routine takes two arguments, SP and PC, and tries to make the
1892 cached frames look as if these two arguments defined a frame on the
1893 cache. This allows the rest of info frame to extract the important
1894 arguments without difficulty. */
1895
1896struct frame_info *
1897setup_arbitrary_frame (argc, argv)
1898 int argc;
1899 CORE_ADDR *argv;
1900{
1901 if (argc != 2)
1902 error ("MIPS frame specifications require two arguments: sp and pc");
1903
1904 return create_new_frame (argv[0], argv[1]);
1905}
1906
1907/*
1908 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1909 *
1910 * For n32 ABI, eight.
1911 * For all others, he same as the size of a general register.
1912 */
1913#if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1914#define MIPS_NABI32 1
1915#define STACK_ARGSIZE 8
1916#else
1917#define MIPS_NABI32 0
7a292a7a 1918#define STACK_ARGSIZE MIPS_SAVED_REGSIZE
c906108c
SS		 1919#endif
1920
1921CORE_ADDR
c5aa993b 1922mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
c906108c
SS		 1923 int nargs;
1924 value_ptr *args;
1925 CORE_ADDR sp;
1926 int struct_return;
1927 CORE_ADDR struct_addr;
1928{
1929 int argreg;
1930 int float_argreg;
1931 int argnum;
1932 int len = 0;
1933 int stack_offset = 0;
1934
1935 /* Macros to round N up or down to the next A boundary; A must be
1936 a power of two. */
1937#define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1938#define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
c5aa993b 1939
c906108c
SS		 1940 /* First ensure that the stack and structure return address (if any)
1941 are properly aligned. The stack has to be at least 64-bit aligned
1942 even on 32-bit machines, because doubles must be 64-bit aligned.
1943 On at least one MIPS variant, stack frames need to be 128-bit
1944 aligned, so we round to this widest known alignment. */
1945 sp = ROUND_DOWN (sp, 16);
7a292a7a 1946 struct_addr = ROUND_DOWN (struct_addr, MIPS_SAVED_REGSIZE);
c5aa993b 1947
c906108c
SS		 1948 /* Now make space on the stack for the args. We allocate more
1949 than necessary for EABI, because the first few arguments are
1950 passed in registers, but that's OK. */
1951 for (argnum = 0; argnum < nargs; argnum++)
c5aa993b 1952 len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_SAVED_REGSIZE);
c906108c
SS		 1953 sp -= ROUND_UP (len, 16);
1954
1955 /* Initialize the integer and float register pointers. */
1956 argreg = A0_REGNUM;
1957 float_argreg = FPA0_REGNUM;
1958
1959 /* the struct_return pointer occupies the first parameter-passing reg */
1960 if (struct_return)
c5aa993b 1961 write_register (argreg++, struct_addr);
c906108c
SS		 1962
1963 /* Now load as many as possible of the first arguments into
1964 registers, and push the rest onto the stack. Loop thru args
1965 from first to last. */
1966 for (argnum = 0; argnum < nargs; argnum++)
1967 {
1968 char *val;
1969 char valbuf[MAX_REGISTER_RAW_SIZE];
1970 value_ptr arg = args[argnum];
1971 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
1972 int len = TYPE_LENGTH (arg_type);
1973 enum type_code typecode = TYPE_CODE (arg_type);
1974
1975 /* The EABI passes structures that do not fit in a register by
c5aa993b 1976 reference. In all other cases, pass the structure by value. */
7a292a7a 1977 if (MIPS_EABI && len > MIPS_SAVED_REGSIZE &&
c906108c
SS		 1978 (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1979 {
7a292a7a 1980 store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
c906108c 1981 typecode = TYPE_CODE_PTR;
7a292a7a 1982 len = MIPS_SAVED_REGSIZE;
c906108c
SS		 1983 val = valbuf;
1984 }
1985 else
c5aa993b 1986 val = (char *) VALUE_CONTENTS (arg);
c906108c
SS		 1987
1988 /* 32-bit ABIs always start floating point arguments in an
1989 even-numbered floating point register. */
1990 if (!FP_REGISTER_DOUBLE && typecode == TYPE_CODE_FLT
c5aa993b 1991 && (float_argreg & 1))
c906108c
SS		 1992 float_argreg++;
1993
1994 /* Floating point arguments passed in registers have to be
1995 treated specially. On 32-bit architectures, doubles
c5aa993b
JM		 1996 are passed in register pairs; the even register gets
1997 the low word, and the odd register gets the high word.
1998 On non-EABI processors, the first two floating point arguments are
1999 also copied to general registers, because MIPS16 functions
2000 don't use float registers for arguments. This duplication of
2001 arguments in general registers can't hurt non-MIPS16 functions
2002 because those registers are normally skipped. */
c906108c
SS		 2003 if (typecode == TYPE_CODE_FLT
2004 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM
2005 && MIPS_FPU_TYPE != MIPS_FPU_NONE)
2006 {
2007 if (!FP_REGISTER_DOUBLE && len == 8)
2008 {
2009 int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0;
2010 unsigned long regval;
2011
2012 /* Write the low word of the double to the even register(s). */
c5aa993b 2013 regval = extract_unsigned_integer (val + low_offset, 4);
c906108c
SS		 2014 write_register (float_argreg++, regval);
2015 if (!MIPS_EABI)
c5aa993b 2016 write_register (argreg + 1, regval);
c906108c
SS		 2017
2018 /* Write the high word of the double to the odd register(s). */
c5aa993b 2019 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
c906108c
SS		 2020 write_register (float_argreg++, regval);
2021 if (!MIPS_EABI)
c5aa993b 2022 {
c906108c
SS		 2023 write_register (argreg, regval);
2024 argreg += 2;
2025 }
2026
2027 }
2028 else
2029 {
2030 /* This is a floating point value that fits entirely
2031 in a single register. */
53a5351d
JM		 2032 /* On 32 bit ABI's the float_argreg is further adjusted
2033 above to ensure that it is even register aligned. */
c906108c
SS		 2034 CORE_ADDR regval = extract_address (val, len);
2035 write_register (float_argreg++, regval);
2036 if (!MIPS_EABI)
c5aa993b 2037 {
53a5351d
JM		 2038 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2039 registers for each argument. The below is (my
2040 guess) to ensure that the corresponding integer
2041 register has reserved the same space. */
c906108c
SS		 2042 write_register (argreg, regval);
2043 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
2044 }
2045 }
2046 }
2047 else
2048 {
2049 /* Copy the argument to general registers or the stack in
2050 register-sized pieces. Large arguments are split between
2051 registers and stack. */
2052 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2053 are treated specially: Irix cc passes them in registers
2054 where gcc sometimes puts them on the stack. For maximum
2055 compatibility, we will put them in both places. */
2056
c5aa993b 2057 int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) &&
7a292a7a 2058 (len % MIPS_SAVED_REGSIZE != 0));
c906108c
SS		 2059 while (len > 0)
2060 {
7a292a7a 2061 int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE;
c906108c
SS		 2062
2063 if (argreg > MIPS_LAST_ARG_REGNUM || odd_sized_struct)
2064 {
2065 /* Write this portion of the argument to the stack. */
2066 /* Should shorter than int integer values be
2067 promoted to int before being stored? */
2068
2069 int longword_offset = 0;
2070 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
7a292a7a
SS		 2071 {
2072 if (STACK_ARGSIZE == 8 &&
2073 (typecode == TYPE_CODE_INT ||
2074 typecode == TYPE_CODE_PTR ||
2075 typecode == TYPE_CODE_FLT) && len <= 4)
2076 longword_offset = STACK_ARGSIZE - len;
2077 else if ((typecode == TYPE_CODE_STRUCT ||
2078 typecode == TYPE_CODE_UNION) &&
2079 TYPE_LENGTH (arg_type) < STACK_ARGSIZE)
2080 longword_offset = STACK_ARGSIZE - len;
2081 }
c5aa993b
JM		 2082
2083 write_memory (sp + stack_offset + longword_offset,
c906108c
SS		 2084 val, partial_len);
2085 }
2086
2087 /* Note!!! This is NOT an else clause.
c5aa993b 2088 Odd sized structs may go thru BOTH paths. */
c906108c
SS		 2089 if (argreg <= MIPS_LAST_ARG_REGNUM)
2090 {
2091 CORE_ADDR regval = extract_address (val, partial_len);
2092
2093 /* A non-floating-point argument being passed in a
2094 general register. If a struct or union, and if
2095 the remaining length is smaller than the register
2096 size, we have to adjust the register value on
2097 big endian targets.
2098
2099 It does not seem to be necessary to do the
2100 same for integral types.
2101
2102 Also don't do this adjustment on EABI and O64
2103 binaries. */
2104
2105 if (!MIPS_EABI
7a292a7a 2106 && MIPS_SAVED_REGSIZE < 8
c906108c 2107 && TARGET_BYTE_ORDER == BIG_ENDIAN
7a292a7a 2108 && partial_len < MIPS_SAVED_REGSIZE
c906108c
SS		 2109 && (typecode == TYPE_CODE_STRUCT ||
2110 typecode == TYPE_CODE_UNION))
c5aa993b 2111 regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
c906108c
SS		 2112 TARGET_CHAR_BIT);
2113
2114 write_register (argreg, regval);
2115 argreg++;
c5aa993b 2116
c906108c
SS		 2117 /* If this is the old ABI, prevent subsequent floating
2118 point arguments from being passed in floating point
2119 registers. */
2120 if (!MIPS_EABI)
2121 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
2122 }
c5aa993b 2123
c906108c
SS		 2124 len -= partial_len;
2125 val += partial_len;
2126
2127 /* The offset onto the stack at which we will start
c5aa993b
JM		 2128 copying parameters (after the registers are used up)
2129 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2130 leaves room for the "home" area for register parameters.
c906108c 2131
c5aa993b
JM		 2132 In the new EABI (and the NABI32), the 8 register parameters
2133 do not have "home" stack space reserved for them, so the
2134 stack offset does not get incremented until after
2135 we have used up the 8 parameter registers. */
c906108c
SS		 2136
2137 if (!(MIPS_EABI || MIPS_NABI32) ||
2138 argnum >= 8)
2139 stack_offset += ROUND_UP (partial_len, STACK_ARGSIZE);
2140 }
2141 }
2142 }
2143
0f71a2f6
JM		 2144 /* Return adjusted stack pointer. */
2145 return sp;
2146}
2147
2148CORE_ADDR
2149mips_push_return_address (pc, sp)
2150 CORE_ADDR pc;
2151 CORE_ADDR sp;
2152{
c906108c
SS		 2153 /* Set the return address register to point to the entry
2154 point of the program, where a breakpoint lies in wait. */
c5aa993b 2155 write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ());
c906108c
SS		 2156 return sp;
2157}
2158
2159static void
c5aa993b 2160mips_push_register (CORE_ADDR * sp, int regno)
c906108c
SS		 2161{
2162 char buffer[MAX_REGISTER_RAW_SIZE];
7a292a7a
SS		 2163 int regsize;
2164 int offset;
2165 if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno))
2166 {
2167 regsize = MIPS_SAVED_REGSIZE;
2168 offset = (TARGET_BYTE_ORDER == BIG_ENDIAN
2169 ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE
2170 : 0);
2171 }
2172 else
2173 {
2174 regsize = REGISTER_RAW_SIZE (regno);
2175 offset = 0;
2176 }
c906108c
SS		 2177 *sp -= regsize;
2178 read_register_gen (regno, buffer);
7a292a7a 2179 write_memory (*sp, buffer + offset, regsize);
c906108c
SS		 2180}
2181
2182/* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2183#define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2184
2185void
7a292a7a 2186mips_push_dummy_frame ()
c906108c
SS		 2187{
2188 int ireg;
c5aa993b
JM		 2189 struct linked_proc_info *link = (struct linked_proc_info *)
2190 xmalloc (sizeof (struct linked_proc_info));
c906108c
SS		 2191 mips_extra_func_info_t proc_desc = &link->info;
2192 CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM));
2193 CORE_ADDR old_sp = sp;
2194 link->next = linked_proc_desc_table;
2195 linked_proc_desc_table = link;
2196
2197/* FIXME! are these correct ? */
c5aa993b 2198#define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
c906108c
SS		 2199#define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2200#define FLOAT_REG_SAVE_MASK MASK(0,19)
2201#define FLOAT_SINGLE_REG_SAVE_MASK \
2202 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2203 /*
2204 * The registers we must save are all those not preserved across
2205 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2206 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2207 * and FP Control/Status registers.
2208 *
2209 *
2210 * Dummy frame layout:
2211 * (high memory)
c5aa993b
JM		 2212 * Saved PC
2213 * Saved MMHI, MMLO, FPC_CSR
2214 * Saved R31
2215 * Saved R28
2216 * ...
2217 * Saved R1
c906108c
SS		 2218 * Saved D18 (i.e. F19, F18)
2219 * ...
2220 * Saved D0 (i.e. F1, F0)
c5aa993b 2221 * Argument build area and stack arguments written via mips_push_arguments
c906108c
SS		 2222 * (low memory)
2223 */
2224
2225 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
c5aa993b
JM		 2226 PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM;
2227 PROC_FRAME_OFFSET (proc_desc) = 0;
2228 PROC_FRAME_ADJUST (proc_desc) = 0;
c906108c
SS		 2229 mips_push_register (&sp, PC_REGNUM);
2230 mips_push_register (&sp, HI_REGNUM);
2231 mips_push_register (&sp, LO_REGNUM);
2232 mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM);
2233
2234 /* Save general CPU registers */
c5aa993b 2235 PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK;
c906108c 2236 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
c5aa993b
JM		 2237 PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE;
2238 for (ireg = 32; --ireg >= 0;)
2239 if (PROC_REG_MASK (proc_desc) & (1 << ireg))
c906108c
SS		 2240 mips_push_register (&sp, ireg);
2241
2242 /* Save floating point registers starting with high order word */
c5aa993b 2243 PROC_FREG_MASK (proc_desc) =
c906108c
SS		 2244 MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
2245 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
2246 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2247 from FP. */
c5aa993b
JM		 2248 PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8;
2249 for (ireg = 32; --ireg >= 0;)
2250 if (PROC_FREG_MASK (proc_desc) & (1 << ireg))
c906108c
SS		 2251 mips_push_register (&sp, ireg + FP0_REGNUM);
2252
2253 /* Update the frame pointer for the call dummy and the stack pointer.
2254 Set the procedure's starting and ending addresses to point to the
2255 call dummy address at the entry point. */
2256 write_register (PUSH_FP_REGNUM, old_sp);
2257 write_register (SP_REGNUM, sp);
c5aa993b
JM		 2258 PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS ();
2259 PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4;
2260 SET_PROC_DESC_IS_DUMMY (proc_desc);
2261 PROC_PC_REG (proc_desc) = RA_REGNUM;
c906108c
SS		 2262}
2263
2264void
c5aa993b 2265mips_pop_frame ()
c906108c
SS		 2266{
2267 register int regnum;
2268 struct frame_info *frame = get_current_frame ();
2269 CORE_ADDR new_sp = FRAME_FP (frame);
2270
cce74817 2271 mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc;
c906108c 2272
c5aa993b 2273 write_register (PC_REGNUM, FRAME_SAVED_PC (frame));
c906108c
SS		 2274 if (frame->saved_regs == NULL)
2275 mips_find_saved_regs (frame);
2276 for (regnum = 0; regnum < NUM_REGS; regnum++)
2277 {
2278 if (regnum != SP_REGNUM && regnum != PC_REGNUM
2279 && frame->saved_regs[regnum])
2280 write_register (regnum,
2281 read_memory_integer (frame->saved_regs[regnum],
c5aa993b 2282 MIPS_SAVED_REGSIZE));
c906108c
SS		 2283 }
2284 write_register (SP_REGNUM, new_sp);
2285 flush_cached_frames ();
2286
c5aa993b 2287 if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
c906108c
SS		 2288 {
2289 struct linked_proc_info *pi_ptr, *prev_ptr;
2290
2291 for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
2292 pi_ptr != NULL;
2293 prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
2294 {
2295 if (&pi_ptr->info == proc_desc)
2296 break;
2297 }
2298
2299 if (pi_ptr == NULL)
2300 error ("Can't locate dummy extra frame info\n");
2301
2302 if (prev_ptr != NULL)
2303 prev_ptr->next = pi_ptr->next;
2304 else
2305 linked_proc_desc_table = pi_ptr->next;
2306
2307 free (pi_ptr);
2308
2309 write_register (HI_REGNUM,
c5aa993b 2310 read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE,
7a292a7a 2311 MIPS_SAVED_REGSIZE));
c906108c 2312 write_register (LO_REGNUM,
c5aa993b 2313 read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE,
7a292a7a 2314 MIPS_SAVED_REGSIZE));
c906108c
SS		 2315 if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
2316 write_register (FCRCS_REGNUM,
c5aa993b 2317 read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE,
7a292a7a 2318 MIPS_SAVED_REGSIZE));
c906108c
SS		 2319 }
2320}
2321
2322static void
2323mips_print_register (regnum, all)
2324 int regnum, all;
2325{
2326 char raw_buffer[MAX_REGISTER_RAW_SIZE];
2327
2328 /* Get the data in raw format. */
2329 if (read_relative_register_raw_bytes (regnum, raw_buffer))
2330 {
2331 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum));
2332 return;
2333 }
2334
2335 /* If an even floating point register, also print as double. */
2336 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
c5aa993b
JM		 2337 && !((regnum - FP0_REGNUM) & 1))
2338 if (REGISTER_RAW_SIZE (regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
c906108c 2339 {
c5aa993b 2340 char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
c906108c
SS		 2341
2342 read_relative_register_raw_bytes (regnum, dbuffer);
c5aa993b 2343 read_relative_register_raw_bytes (regnum + 1, dbuffer + MIPS_REGSIZE);
c906108c
SS		 2344 REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer);
2345
c5aa993b 2346 printf_filtered ("(d%d: ", regnum - FP0_REGNUM);
c906108c
SS		 2347 val_print (builtin_type_double, dbuffer, 0, 0,
2348 gdb_stdout, 0, 1, 0, Val_pretty_default);
2349 printf_filtered ("); ");
2350 }
2351 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
2352
2353 /* The problem with printing numeric register names (r26, etc.) is that
2354 the user can't use them on input. Probably the best solution is to
2355 fix it so that either the numeric or the funky (a2, etc.) names
2356 are accepted on input. */
2357 if (regnum < MIPS_NUMREGS)
2358 printf_filtered ("(r%d): ", regnum);
2359 else
2360 printf_filtered (": ");
2361
2362 /* If virtual format is floating, print it that way. */
2363 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2364 if (FP_REGISTER_DOUBLE)
c5aa993b 2365 { /* show 8-byte floats as float AND double: */
c906108c
SS		 2366 int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN);
2367
2368 printf_filtered (" (float) ");
2369 val_print (builtin_type_float, raw_buffer + offset, 0, 0,
2370 gdb_stdout, 0, 1, 0, Val_pretty_default);
2371 printf_filtered (", (double) ");
2372 val_print (builtin_type_double, raw_buffer, 0, 0,
2373 gdb_stdout, 0, 1, 0, Val_pretty_default);
2374 }
2375 else
2376 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
2377 gdb_stdout, 0, 1, 0, Val_pretty_default);
2378 /* Else print as integer in hex. */
2379 else
2380 print_scalar_formatted (raw_buffer, REGISTER_VIRTUAL_TYPE (regnum),
2381 'x', 0, gdb_stdout);
2382}
2383
2384/* Replacement for generic do_registers_info.
2385 Print regs in pretty columns. */
2386
2387static int
2388do_fp_register_row (regnum)
2389 int regnum;
c5aa993b 2390{ /* do values for FP (float) regs */
c906108c
SS		 2391 char *raw_buffer[2];
2392 char *dbl_buffer;
2393 /* use HI and LO to control the order of combining two flt regs */
2394 int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN);
2395 int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN);
2396 double doub, flt1, flt2; /* doubles extracted from raw hex data */
2397 int inv1, inv2, inv3;
c5aa993b 2398
c906108c
SS		 2399 raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
2400 raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
2401 dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM));
2402
2403 /* Get the data in raw format. */
2404 if (read_relative_register_raw_bytes (regnum, raw_buffer[HI]))
2405 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
c5aa993b 2406 if (REGISTER_RAW_SIZE (regnum) == 4)
c906108c
SS		 2407 {
2408 /* 4-byte registers: we can fit two registers per row. */
2409 /* Also print every pair of 4-byte regs as an 8-byte double. */
2410 if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO]))
c5aa993b 2411 error ("can't read register %d (%s)",
c906108c
SS		 2412 regnum + 1, REGISTER_NAME (regnum + 1));
2413
2414 /* copy the two floats into one double, and unpack both */
c5aa993b
JM		 2415 memcpy (dbl_buffer, raw_buffer, sizeof (dbl_buffer));
2416 flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1);
2417 flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2);
2418 doub = unpack_double (builtin_type_double, dbl_buffer, &inv3);
2419
2420 printf_filtered (inv1 ? " %-5s: <invalid float>" :
2421 " %-5s%-17.9g", REGISTER_NAME (regnum), flt1);
2422 printf_filtered (inv2 ? " %-5s: <invalid float>" :
c906108c 2423 " %-5s%-17.9g", REGISTER_NAME (regnum + 1), flt2);
c5aa993b 2424 printf_filtered (inv3 ? " dbl: <invalid double>\n" :
c906108c
SS		 2425 " dbl: %-24.17g\n", doub);
2426 /* may want to do hex display here (future enhancement) */
c5aa993b 2427 regnum += 2;
c906108c
SS		 2428 }
2429 else
c5aa993b 2430 { /* eight byte registers: print each one as float AND as double. */
c906108c
SS		 2431 int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN);
2432
c5aa993b
JM		 2433 memcpy (dbl_buffer, raw_buffer[HI], sizeof (dbl_buffer));
2434 flt1 = unpack_double (builtin_type_float,
c906108c 2435 &raw_buffer[HI][offset], &inv1);
c5aa993b 2436 doub = unpack_double (builtin_type_double, dbl_buffer, &inv3);
c906108c 2437
c5aa993b 2438 printf_filtered (inv1 ? " %-5s: <invalid float>" :
c906108c 2439 " %-5s flt: %-17.9g", REGISTER_NAME (regnum), flt1);
c5aa993b 2440 printf_filtered (inv3 ? " dbl: <invalid double>\n" :
c906108c
SS		 2441 " dbl: %-24.17g\n", doub);
2442 /* may want to do hex display here (future enhancement) */
2443 regnum++;
2444 }
2445 return regnum;
2446}
2447
2448/* Print a row's worth of GP (int) registers, with name labels above */
2449
2450static int
2451do_gp_register_row (regnum)
2452 int regnum;
2453{
2454 /* do values for GP (int) regs */
2455 char raw_buffer[MAX_REGISTER_RAW_SIZE];
2456 int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */
2457 int col, byte;
2458 int start_regnum = regnum;
2459 int numregs = NUM_REGS;
2460
2461
2462 /* For GP registers, we print a separate row of names above the vals */
2463 printf_filtered (" ");
2464 for (col = 0; col < ncols && regnum < numregs; regnum++)
2465 {
2466 if (*REGISTER_NAME (regnum) == '\0')
c5aa993b 2467 continue; /* unused register */
c906108c 2468 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
c5aa993b
JM		 2469 break; /* end the row: reached FP register */
2470 printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s",
c906108c
SS		 2471 REGISTER_NAME (regnum));
2472 col++;
2473 }
c5aa993b 2474 printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ",
c906108c
SS		 2475 start_regnum); /* print the R0 to R31 names */
2476
2477 regnum = start_regnum; /* go back to start of row */
2478 /* now print the values in hex, 4 or 8 to the row */
2479 for (col = 0; col < ncols && regnum < numregs; regnum++)
2480 {
2481 if (*REGISTER_NAME (regnum) == '\0')
c5aa993b 2482 continue; /* unused register */
c906108c 2483 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
c5aa993b 2484 break; /* end row: reached FP register */
c906108c
SS		 2485 /* OK: get the data in raw format. */
2486 if (read_relative_register_raw_bytes (regnum, raw_buffer))
2487 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2488 /* pad small registers */
43e526b9 2489 for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++)
c906108c
SS		 2490 printf_filtered (" ");
2491 /* Now print the register value in hex, endian order. */
2492 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
43e526b9
JM		 2493 for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum);
2494 byte < REGISTER_RAW_SIZE (regnum);
2495 byte++)
c906108c
SS		 2496 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
2497 else
43e526b9
JM		 2498 for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1;
2499 byte >= 0;
2500 byte--)
c906108c
SS		 2501 printf_filtered ("%02x", (unsigned char) raw_buffer[byte]);
2502 printf_filtered (" ");
2503 col++;
2504 }
c5aa993b 2505 if (col > 0) /* ie. if we actually printed anything... */
c906108c
SS		 2506 printf_filtered ("\n");
2507
2508 return regnum;
2509}
2510
2511/* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2512
2513void
2514mips_do_registers_info (regnum, fpregs)
2515 int regnum;
2516 int fpregs;
2517{
c5aa993b 2518 if (regnum != -1) /* do one specified register */
c906108c
SS		 2519 {
2520 if (*(REGISTER_NAME (regnum)) == '\0')
2521 error ("Not a valid register for the current processor type");
2522
2523 mips_print_register (regnum, 0);
2524 printf_filtered ("\n");
2525 }
c5aa993b
JM		 2526 else
2527 /* do all (or most) registers */
c906108c
SS		 2528 {
2529 regnum = 0;
2530 while (regnum < NUM_REGS)
2531 {
c5aa993b
JM		 2532 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
2533 if (fpregs) /* true for "INFO ALL-REGISTERS" command */
c906108c
SS		 2534 regnum = do_fp_register_row (regnum); /* FP regs */
2535 else
2536 regnum += MIPS_NUMREGS; /* skip floating point regs */
2537 else
2538 regnum = do_gp_register_row (regnum); /* GP (int) regs */
2539 }
2540 }
2541}
2542
2543/* Return number of args passed to a frame. described by FIP.
2544 Can return -1, meaning no way to tell. */
2545
2546int
2547mips_frame_num_args (frame)
c5aa993b 2548 struct frame_info *frame;
c906108c 2549{
c5aa993b 2550#if 0 /* FIXME Use or lose this! */
c906108c
SS		 2551 struct chain_info_t *p;
2552
2553 p = mips_find_cached_frame (FRAME_FP (frame));
2554 if (p->valid)
2555 return p->the_info.numargs;
2556#endif
2557 return -1;
2558}
2559
2560/* Is this a branch with a delay slot? */
2561
2562static int is_delayed PARAMS ((unsigned long));
2563
2564static int
2565is_delayed (insn)
2566 unsigned long insn;
2567{
2568 int i;
2569 for (i = 0; i < NUMOPCODES; ++i)
2570 if (mips_opcodes[i].pinfo != INSN_MACRO
2571 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
2572 break;
2573 return (i < NUMOPCODES
2574 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
2575 | INSN_COND_BRANCH_DELAY
2576 | INSN_COND_BRANCH_LIKELY)));
2577}
2578
2579int
2580mips_step_skips_delay (pc)
2581 CORE_ADDR pc;
2582{
2583 char buf[MIPS_INSTLEN];
2584
2585 /* There is no branch delay slot on MIPS16. */
2586 if (pc_is_mips16 (pc))
2587 return 0;
2588
2589 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
2590 /* If error reading memory, guess that it is not a delayed branch. */
2591 return 0;
c5aa993b 2592 return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
c906108c
SS		 2593}
2594
2595
2596/* Skip the PC past function prologue instructions (32-bit version).
2597 This is a helper function for mips_skip_prologue. */
2598
2599static CORE_ADDR
2600mips32_skip_prologue (pc, lenient)
c5aa993b 2601 CORE_ADDR pc; /* starting PC to search from */
c906108c
SS		 2602 int lenient;
2603{
c5aa993b
JM		 2604 t_inst inst;
2605 CORE_ADDR end_pc;
2606 int seen_sp_adjust = 0;
2607 int load_immediate_bytes = 0;
2608
2609 /* Skip the typical prologue instructions. These are the stack adjustment
2610 instruction and the instructions that save registers on the stack
2611 or in the gcc frame. */
2612 for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN)
2613 {
2614 unsigned long high_word;
c906108c 2615
c5aa993b
JM		 2616 inst = mips_fetch_instruction (pc);
2617 high_word = (inst >> 16) & 0xffff;
c906108c
SS		 2618
2619#if 0
c5aa993b
JM		 2620 if (lenient && is_delayed (inst))
2621 continue;
c906108c
SS		 2622#endif
2623
c5aa993b
JM		 2624 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
2625 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
2626 seen_sp_adjust = 1;
2627 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
2628 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
2629 seen_sp_adjust = 1;
2630 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2631 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2632 && (inst & 0x001F0000)) /* reg != $zero */
2633 continue;
2634
2635 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2636 continue;
2637 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
2638 /* sx reg,n($s8) */
2639 continue; /* reg != $zero */
2640
2641 /* move $s8,$sp. With different versions of gas this will be either
2642 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2643 Accept any one of these. */
2644 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2645 continue;
2646
2647 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2648 continue;
2649 else if (high_word == 0x3c1c) /* lui $gp,n */
2650 continue;
2651 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
2652 continue;
2653 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
2654 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
2655 continue;
2656 /* The following instructions load $at or $t0 with an immediate
2657 value in preparation for a stack adjustment via
2658 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2659 a local variable, so we accept them only before a stack adjustment
2660 instruction was seen. */
2661 else if (!seen_sp_adjust)
2662 {
2663 if (high_word == 0x3c01 || /* lui $at,n */
2664 high_word == 0x3c08) /* lui $t0,n */
2665 {
2666 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
2667 continue;
2668 }
2669 else if (high_word == 0x3421 || /* ori $at,$at,n */
2670 high_word == 0x3508 || /* ori $t0,$t0,n */
2671 high_word == 0x3401 || /* ori $at,$zero,n */
2672 high_word == 0x3408) /* ori $t0,$zero,n */
2673 {
2674 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
2675 continue;
2676 }
2677 else
2678 break;
2679 }
2680 else
2681 break;
c906108c
SS		 2682 }
2683
c5aa993b
JM		 2684 /* In a frameless function, we might have incorrectly
2685 skipped some load immediate instructions. Undo the skipping
2686 if the load immediate was not followed by a stack adjustment. */
2687 if (load_immediate_bytes && !seen_sp_adjust)
2688 pc -= load_immediate_bytes;
2689 return pc;
c906108c
SS		 2690}
2691
2692/* Skip the PC past function prologue instructions (16-bit version).
2693 This is a helper function for mips_skip_prologue. */
2694
2695static CORE_ADDR
2696mips16_skip_prologue (pc, lenient)
c5aa993b 2697 CORE_ADDR pc; /* starting PC to search from */
c906108c
SS		 2698 int lenient;
2699{
c5aa993b
JM		 2700 CORE_ADDR end_pc;
2701 int extend_bytes = 0;
2702 int prev_extend_bytes;
c906108c 2703
c5aa993b
JM		 2704 /* Table of instructions likely to be found in a function prologue. */
2705 static struct
c906108c
SS		 2706 {
2707 unsigned short inst;
2708 unsigned short mask;
c5aa993b
JM		 2709 }
2710 table[] =
2711 {
c906108c 2712 {
c5aa993b
JM		 2713 0x6300, 0xff00
2714 }
2715 , /* addiu $sp,offset */
2716 {
2717 0xfb00, 0xff00
2718 }
2719 , /* daddiu $sp,offset */
2720 {
2721 0xd000, 0xf800
2722 }
2723 , /* sw reg,n($sp) */
2724 {
2725 0xf900, 0xff00
2726 }
2727 , /* sd reg,n($sp) */
2728 {
2729 0x6200, 0xff00
2730 }
2731 , /* sw $ra,n($sp) */
2732 {
2733 0xfa00, 0xff00
2734 }
2735 , /* sd $ra,n($sp) */
2736 {
2737 0x673d, 0xffff
2738 }
2739 , /* move $s1,sp */
2740 {
2741 0xd980, 0xff80
2742 }
2743 , /* sw $a0-$a3,n($s1) */
2744 {
2745 0x6704, 0xff1c
2746 }
2747 , /* move reg,$a0-$a3 */
2748 {
2749 0xe809, 0xf81f
2750 }
2751 , /* entry pseudo-op */
2752 {
2753 0x0100, 0xff00
2754 }
2755 , /* addiu $s1,$sp,n */
2756 {
2757 0, 0
2758 } /* end of table marker */
2759 };
2760
2761 /* Skip the typical prologue instructions. These are the stack adjustment
2762 instruction and the instructions that save registers on the stack
2763 or in the gcc frame. */
2764 for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN)
2765 {
2766 unsigned short inst;
2767 int i;
c906108c 2768
c5aa993b 2769 inst = mips_fetch_instruction (pc);
c906108c 2770
c5aa993b
JM		 2771 /* Normally we ignore an extend instruction. However, if it is
2772 not followed by a valid prologue instruction, we must adjust
2773 the pc back over the extend so that it won't be considered
2774 part of the prologue. */
2775 if ((inst & 0xf800) == 0xf000) /* extend */
2776 {
2777 extend_bytes = MIPS16_INSTLEN;
2778 continue;
2779 }
2780 prev_extend_bytes = extend_bytes;
2781 extend_bytes = 0;
c906108c 2782
c5aa993b
JM		 2783 /* Check for other valid prologue instructions besides extend. */
2784 for (i = 0; table[i].mask != 0; i++)
2785 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
2786 break;
2787 if (table[i].mask != 0) /* it was in table? */
2788 continue; /* ignore it */
2789 else
2790 /* non-prologue */
2791 {
2792 /* Return the current pc, adjusted backwards by 2 if
2793 the previous instruction was an extend. */
2794 return pc - prev_extend_bytes;
2795 }
c906108c
SS		 2796 }
2797 return pc;
2798}
2799
2800/* To skip prologues, I use this predicate. Returns either PC itself
2801 if the code at PC does not look like a function prologue; otherwise
2802 returns an address that (if we're lucky) follows the prologue. If
2803 LENIENT, then we must skip everything which is involved in setting
2804 up the frame (it's OK to skip more, just so long as we don't skip
2805 anything which might clobber the registers which are being saved.
2806 We must skip more in the case where part of the prologue is in the
2807 delay slot of a non-prologue instruction). */
2808
2809CORE_ADDR
2810mips_skip_prologue (pc, lenient)
2811 CORE_ADDR pc;
2812 int lenient;
2813{
2814 /* See if we can determine the end of the prologue via the symbol table.
2815 If so, then return either PC, or the PC after the prologue, whichever
2816 is greater. */
2817
2818 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
2819
2820 if (post_prologue_pc != 0)
2821 return max (pc, post_prologue_pc);
2822
2823 /* Can't determine prologue from the symbol table, need to examine
2824 instructions. */
2825
2826 if (pc_is_mips16 (pc))
2827 return mips16_skip_prologue (pc, lenient);
2828 else
2829 return mips32_skip_prologue (pc, lenient);
2830}
2831
2832#if 0
2833/* The lenient prologue stuff should be superseded by the code in
2834 init_extra_frame_info which looks to see whether the stores mentioned
2835 in the proc_desc have actually taken place. */
2836
2837/* Is address PC in the prologue (loosely defined) for function at
2838 STARTADDR? */
2839
2840static int
2841mips_in_lenient_prologue (startaddr, pc)
2842 CORE_ADDR startaddr;
2843 CORE_ADDR pc;
2844{
2845 CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1);
2846 return pc >= startaddr && pc < end_prologue;
2847}
2848#endif
2849
7a292a7a
SS		 2850/* Determine how a return value is stored within the MIPS register
2851 file, given the return type `valtype'. */
2852
2853struct return_value_word
2854{
2855 int len;
2856 int reg;
2857 int reg_offset;
2858 int buf_offset;
2859};
2860
2861static void return_value_location PARAMS ((struct type *, struct return_value_word *, struct return_value_word *));
2862
2863static void
2864return_value_location (valtype, hi, lo)
2865 struct type *valtype;
2866 struct return_value_word *hi;
2867 struct return_value_word *lo;
2868{
2869 int len = TYPE_LENGTH (valtype);
c5aa993b 2870
7a292a7a
SS		 2871 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
2872 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
2873 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
2874 {
2875 if (!FP_REGISTER_DOUBLE && len == 8)
2876 {
2877 /* We need to break a 64bit float in two 32 bit halves and
c5aa993b 2878 spread them across a floating-point register pair. */
7a292a7a
SS		 2879 lo->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0;
2880 hi->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 0 : 4;
2881 lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN
2882 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8)
2883 ? 4 : 0);
2884 hi->reg_offset = lo->reg_offset;
2885 lo->reg = FP0_REGNUM + 0;
2886 hi->reg = FP0_REGNUM + 1;
2887 lo->len = 4;
2888 hi->len = 4;
2889 }
2890 else
2891 {
2892 /* The floating point value fits in a single floating-point
c5aa993b 2893 register. */
7a292a7a
SS		 2894 lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN
2895 && REGISTER_RAW_SIZE (FP0_REGNUM) == 8
2896 && len == 4)
2897 ? 4 : 0);
2898 lo->reg = FP0_REGNUM;
2899 lo->len = len;
2900 lo->buf_offset = 0;
2901 hi->len = 0;
2902 hi->reg_offset = 0;
2903 hi->buf_offset = 0;
2904 hi->reg = 0;
2905 }
2906 }
2907 else
2908 {
2909 /* Locate a result possibly spread across two registers. */
2910 int regnum = 2;
2911 lo->reg = regnum + 0;
2912 hi->reg = regnum + 1;
2913 if (TARGET_BYTE_ORDER == BIG_ENDIAN
2914 && len < MIPS_SAVED_REGSIZE)
2915 {
2916 /* "un-left-justify" the value in the low register */
2917 lo->reg_offset = MIPS_SAVED_REGSIZE - len;
2918 lo->len = len;
2919 hi->reg_offset = 0;
2920 hi->len = 0;
2921 }
2922 else if (TARGET_BYTE_ORDER == BIG_ENDIAN
2923 && len > MIPS_SAVED_REGSIZE /* odd-size structs */
2924 && len < MIPS_SAVED_REGSIZE * 2
2925 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
2926 TYPE_CODE (valtype) == TYPE_CODE_UNION))
2927 {
2928 /* "un-left-justify" the value spread across two registers. */
2929 lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len;
2930 lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset;
2931 hi->reg_offset = 0;
2932 hi->len = len - lo->len;
2933 }
2934 else
2935 {
2936 /* Only perform a partial copy of the second register. */
2937 lo->reg_offset = 0;
2938 hi->reg_offset = 0;
2939 if (len > MIPS_SAVED_REGSIZE)
2940 {
2941 lo->len = MIPS_SAVED_REGSIZE;
2942 hi->len = len - MIPS_SAVED_REGSIZE;
2943 }
2944 else
2945 {
2946 lo->len = len;
2947 hi->len = 0;
2948 }
2949 }
2950 if (TARGET_BYTE_ORDER == BIG_ENDIAN
2951 && REGISTER_RAW_SIZE (regnum) == 8
2952 && MIPS_SAVED_REGSIZE == 4)
2953 {
2954 /* Account for the fact that only the least-signficant part
c5aa993b 2955 of the register is being used */
7a292a7a
SS		 2956 lo->reg_offset += 4;
2957 hi->reg_offset += 4;
2958 }
2959 lo->buf_offset = 0;
2960 hi->buf_offset = lo->len;
2961 }
2962}
2963
2964/* Given a return value in `regbuf' with a type `valtype', extract and
2965 copy its value into `valbuf'. */
2966
c906108c
SS		 2967void
2968mips_extract_return_value (valtype, regbuf, valbuf)
c5aa993b
JM		 2969 struct type *valtype;
2970 char regbuf[REGISTER_BYTES];
2971 char *valbuf;
c906108c 2972{
7a292a7a
SS		 2973 struct return_value_word lo;
2974 struct return_value_word hi;
2975 return_value_location (valtype, &lo, &hi);
2976
2977 memcpy (valbuf + lo.buf_offset,
2978 regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset,
2979 lo.len);
2980
2981 if (hi.len > 0)
2982 memcpy (valbuf + hi.buf_offset,
2983 regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset,
2984 hi.len);
2985
2986#if 0
c906108c
SS		 2987 int regnum;
2988 int offset = 0;
2989 int len = TYPE_LENGTH (valtype);
c5aa993b 2990
c906108c
SS		 2991 regnum = 2;
2992 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
2993 && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE
2994 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE
2995 && len <= MIPS_FPU_SINGLE_REGSIZE)))
2996 regnum = FP0_REGNUM;
2997
2998 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
c5aa993b 2999 { /* "un-left-justify" the value from the register */
c906108c
SS		 3000 if (len < REGISTER_RAW_SIZE (regnum))
3001 offset = REGISTER_RAW_SIZE (regnum) - len;
c5aa993b 3002 if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */
c906108c
SS		 3003 len < REGISTER_RAW_SIZE (regnum) * 2 &&
3004 (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
3005 TYPE_CODE (valtype) == TYPE_CODE_UNION))
3006 offset = 2 * REGISTER_RAW_SIZE (regnum) - len;
3007 }
3008 memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len);
3009 REGISTER_CONVERT_TO_TYPE (regnum, valtype, valbuf);
7a292a7a 3010#endif
c906108c
SS		 3011}
3012
7a292a7a
SS		 3013/* Given a return value in `valbuf' with a type `valtype', write it's
3014 value into the appropriate register. */
3015
c906108c
SS		 3016void
3017mips_store_return_value (valtype, valbuf)
c5aa993b
JM		 3018 struct type *valtype;
3019 char *valbuf;
c906108c 3020{
7a292a7a
SS		 3021 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3022 struct return_value_word lo;
3023 struct return_value_word hi;
3024 return_value_location (valtype, &lo, &hi);
3025
3026 memset (raw_buffer, 0, sizeof (raw_buffer));
3027 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
3028 write_register_bytes (REGISTER_BYTE (lo.reg),
3029 raw_buffer,
3030 REGISTER_RAW_SIZE (lo.reg));
c5aa993b 3031
7a292a7a
SS		 3032 if (hi.len > 0)
3033 {
3034 memset (raw_buffer, 0, sizeof (raw_buffer));
3035 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
3036 write_register_bytes (REGISTER_BYTE (hi.reg),
3037 raw_buffer,
3038 REGISTER_RAW_SIZE (hi.reg));
3039 }
3040
3041#if 0
c906108c
SS		 3042 int regnum;
3043 int offset = 0;
3044 int len = TYPE_LENGTH (valtype);
3045 char raw_buffer[MAX_REGISTER_RAW_SIZE];
c5aa993b 3046
c906108c
SS		 3047 regnum = 2;
3048 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
3049 && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE
3050 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE
3051 && len <= MIPS_REGSIZE)))
3052 regnum = FP0_REGNUM;
3053
3054 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
c5aa993b 3055 { /* "left-justify" the value in the register */
c906108c
SS		 3056 if (len < REGISTER_RAW_SIZE (regnum))
3057 offset = REGISTER_RAW_SIZE (regnum) - len;
c5aa993b 3058 if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */
c906108c
SS		 3059 len < REGISTER_RAW_SIZE (regnum) * 2 &&
3060 (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
3061 TYPE_CODE (valtype) == TYPE_CODE_UNION))
3062 offset = 2 * REGISTER_RAW_SIZE (regnum) - len;
3063 }
c5aa993b
JM		 3064 memcpy (raw_buffer + offset, valbuf, len);
3065 REGISTER_CONVERT_FROM_TYPE (regnum, valtype, raw_buffer);
3066 write_register_bytes (REGISTER_BYTE (regnum), raw_buffer,
3067 len > REGISTER_RAW_SIZE (regnum) ?
3068 len : REGISTER_RAW_SIZE (regnum));
7a292a7a 3069#endif
c906108c
SS		 3070}
3071
3072/* Exported procedure: Is PC in the signal trampoline code */
3073
3074int
3075in_sigtramp (pc, ignore)
3076 CORE_ADDR pc;
3077 char *ignore; /* function name */
3078{
3079 if (sigtramp_address == 0)
3080 fixup_sigtramp ();
3081 return (pc >= sigtramp_address && pc < sigtramp_end);
3082}
3083
3084/* Commands to show/set the MIPS FPU type. */
3085
3086static void show_mipsfpu_command PARAMS ((char *, int));
3087static void
3088show_mipsfpu_command (args, from_tty)
3089 char *args;
3090 int from_tty;
3091{
3092 char *msg;
3093 char *fpu;
3094 switch (MIPS_FPU_TYPE)
3095 {
3096 case MIPS_FPU_SINGLE:
3097 fpu = "single-precision";
3098 break;
3099 case MIPS_FPU_DOUBLE:
3100 fpu = "double-precision";
3101 break;
3102 case MIPS_FPU_NONE:
3103 fpu = "absent (none)";
3104 break;
3105 }
3106 if (mips_fpu_type_auto)
3107 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3108 fpu);
3109 else
3110 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3111 fpu);
3112}
3113
3114
3115static void set_mipsfpu_command PARAMS ((char *, int));
3116static void
3117set_mipsfpu_command (args, from_tty)
3118 char *args;
3119 int from_tty;
3120{
3121 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3122 show_mipsfpu_command (args, from_tty);
3123}
3124
3125static void set_mipsfpu_single_command PARAMS ((char *, int));
3126static void
3127set_mipsfpu_single_command (args, from_tty)
3128 char *args;
3129 int from_tty;
3130{
3131 mips_fpu_type = MIPS_FPU_SINGLE;
3132 mips_fpu_type_auto = 0;
3133}
3134
3135static void set_mipsfpu_double_command PARAMS ((char *, int));
3136static void
3137set_mipsfpu_double_command (args, from_tty)
3138 char *args;
3139 int from_tty;
3140{
3141 mips_fpu_type = MIPS_FPU_DOUBLE;
3142 mips_fpu_type_auto = 0;
3143}
3144
3145static void set_mipsfpu_none_command PARAMS ((char *, int));
3146static void
3147set_mipsfpu_none_command (args, from_tty)
3148 char *args;
3149 int from_tty;
3150{
3151 mips_fpu_type = MIPS_FPU_NONE;
3152 mips_fpu_type_auto = 0;
3153}
3154
3155static void set_mipsfpu_auto_command PARAMS ((char *, int));
3156static void
3157set_mipsfpu_auto_command (args, from_tty)
3158 char *args;
3159 int from_tty;
3160{
3161 mips_fpu_type_auto = 1;
3162}
3163
3164/* Command to set the processor type. */
3165
3166void
3167mips_set_processor_type_command (args, from_tty)
3168 char *args;
3169 int from_tty;
3170{
3171 int i;
3172
3173 if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0')
3174 {
3175 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3176 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3177 printf_unfiltered ("%s\n", mips_processor_type_table[i].name);
3178
3179 /* Restore the value. */
3180 tmp_mips_processor_type = strsave (mips_processor_type);
3181
3182 return;
3183 }
c5aa993b 3184
c906108c
SS		 3185 if (!mips_set_processor_type (tmp_mips_processor_type))
3186 {
3187 error ("Unknown processor type `%s'.", tmp_mips_processor_type);
3188 /* Restore its value. */
3189 tmp_mips_processor_type = strsave (mips_processor_type);
3190 }
3191}
3192
3193static void
3194mips_show_processor_type_command (args, from_tty)
3195 char *args;
3196 int from_tty;
3197{
3198}
3199
3200/* Modify the actual processor type. */
3201
3202int
3203mips_set_processor_type (str)
3204 char *str;
3205{
3206 int i, j;
3207
3208 if (str == NULL)
3209 return 0;
3210
3211 for (i = 0; mips_processor_type_table[i].name != NULL; ++i)
3212 {
3213 if (strcasecmp (str, mips_processor_type_table[i].name) == 0)
3214 {
3215 mips_processor_type = str;
cce74817 3216 mips_processor_reg_names = mips_processor_type_table[i].regnames;
c906108c 3217 return 1;
c906108c
SS		 3218 /* FIXME tweak fpu flag too */
3219 }
3220 }
3221
3222 return 0;
3223}
3224
3225/* Attempt to identify the particular processor model by reading the
3226 processor id. */
3227
3228char *
3229mips_read_processor_type ()
3230{
3231 CORE_ADDR prid;
3232
3233 prid = read_register (PRID_REGNUM);
3234
3235 if ((prid & ~0xf) == 0x700)
c5aa993b 3236 return savestring ("r3041", strlen ("r3041"));
c906108c
SS		 3237
3238 return NULL;
3239}
3240
3241/* Just like reinit_frame_cache, but with the right arguments to be
3242 callable as an sfunc. */
3243
3244static void
3245reinit_frame_cache_sfunc (args, from_tty, c)
3246 char *args;
3247 int from_tty;
3248 struct cmd_list_element *c;
3249{
3250 reinit_frame_cache ();
3251}
3252
3253int
3254gdb_print_insn_mips (memaddr, info)
3255 bfd_vma memaddr;
3256 disassemble_info *info;
3257{
3258 mips_extra_func_info_t proc_desc;
3259
3260 /* Search for the function containing this address. Set the low bit
3261 of the address when searching, in case we were given an even address
3262 that is the start of a 16-bit function. If we didn't do this,
3263 the search would fail because the symbol table says the function
3264 starts at an odd address, i.e. 1 byte past the given address. */
3265 memaddr = ADDR_BITS_REMOVE (memaddr);
3266 proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL);
3267
3268 /* Make an attempt to determine if this is a 16-bit function. If
3269 the procedure descriptor exists and the address therein is odd,
3270 it's definitely a 16-bit function. Otherwise, we have to just
3271 guess that if the address passed in is odd, it's 16-bits. */
3272 if (proc_desc)
3273 info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : TM_PRINT_INSN_MACH;
3274 else
3275 info->mach = pc_is_mips16 (memaddr) ? 16 : TM_PRINT_INSN_MACH;
3276
3277 /* Round down the instruction address to the appropriate boundary. */
3278 memaddr &= (info->mach == 16 ? ~1 : ~3);
c5aa993b 3279
c906108c
SS		 3280 /* Call the appropriate disassembler based on the target endian-ness. */
3281 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
3282 return print_insn_big_mips (memaddr, info);
3283 else
3284 return print_insn_little_mips (memaddr, info);
3285}
3286
3287/* Old-style breakpoint macros.
3288 The IDT board uses an unusual breakpoint value, and sometimes gets
3289 confused when it sees the usual MIPS breakpoint instruction. */
3290
3291#define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3292#define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3293#define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3294#define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3295#define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3296#define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3297#define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3298#define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3299
3300/* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3301 counter value to determine whether a 16- or 32-bit breakpoint should be
3302 used. It returns a pointer to a string of bytes that encode a breakpoint
3303 instruction, stores the length of the string to *lenptr, and adjusts pc
3304 (if necessary) to point to the actual memory location where the
3305 breakpoint should be inserted. */
3306
c5aa993b
JM		 3307unsigned char *
3308mips_breakpoint_from_pc (pcptr, lenptr)
c906108c
SS		 3309 CORE_ADDR *pcptr;
3310 int *lenptr;
3311{
3312 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
3313 {
3314 if (pc_is_mips16 (*pcptr))
3315 {
3316 static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT;
3317 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
c5aa993b 3318 *lenptr = sizeof (mips16_big_breakpoint);
c906108c
SS		 3319 return mips16_big_breakpoint;
3320 }
3321 else
3322 {
3323 static char big_breakpoint[] = BIG_BREAKPOINT;
3324 static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT;
3325 static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT;
3326
c5aa993b 3327 *lenptr = sizeof (big_breakpoint);
c906108c
SS		 3328
3329 if (strcmp (target_shortname, "mips") == 0)
3330 return idt_big_breakpoint;
3331 else if (strcmp (target_shortname, "ddb") == 0
3332 || strcmp (target_shortname, "pmon") == 0
3333 || strcmp (target_shortname, "lsi") == 0)
3334 return pmon_big_breakpoint;
3335 else
3336 return big_breakpoint;
3337 }
3338 }
3339 else
3340 {
3341 if (pc_is_mips16 (*pcptr))
3342 {
3343 static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT;
3344 *pcptr = UNMAKE_MIPS16_ADDR (*pcptr);
c5aa993b 3345 *lenptr = sizeof (mips16_little_breakpoint);
c906108c
SS		 3346 return mips16_little_breakpoint;
3347 }
3348 else
3349 {
3350 static char little_breakpoint[] = LITTLE_BREAKPOINT;
3351 static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT;
3352 static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT;
3353
c5aa993b 3354 *lenptr = sizeof (little_breakpoint);
c906108c
SS		 3355
3356 if (strcmp (target_shortname, "mips") == 0)
3357 return idt_little_breakpoint;
3358 else if (strcmp (target_shortname, "ddb") == 0
3359 || strcmp (target_shortname, "pmon") == 0
3360 || strcmp (target_shortname, "lsi") == 0)
3361 return pmon_little_breakpoint;
3362 else
3363 return little_breakpoint;
3364 }
3365 }
3366}
3367
3368/* If PC is in a mips16 call or return stub, return the address of the target
3369 PC, which is either the callee or the caller. There are several
3370 cases which must be handled:
3371
3372 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
c5aa993b 3373 target PC is in $31 ($ra).
c906108c 3374 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
c5aa993b 3375 and the target PC is in $2.
c906108c 3376 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
c5aa993b
JM		 3377 before the jal instruction, this is effectively a call stub
3378 and the the target PC is in $2. Otherwise this is effectively
3379 a return stub and the target PC is in $18.
c906108c
SS		 3380
3381 See the source code for the stubs in gcc/config/mips/mips16.S for
3382 gory details.
3383
3384 This function implements the SKIP_TRAMPOLINE_CODE macro.
c5aa993b 3385 */
c906108c
SS		 3386
3387CORE_ADDR
3388mips_skip_stub (pc)
3389 CORE_ADDR pc;
3390{
3391 char *name;
3392 CORE_ADDR start_addr;
3393
3394 /* Find the starting address and name of the function containing the PC. */
3395 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
3396 return 0;
3397
3398 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3399 target PC is in $31 ($ra). */
3400 if (strcmp (name, "__mips16_ret_sf") == 0
3401 || strcmp (name, "__mips16_ret_df") == 0)
3402 return read_register (RA_REGNUM);
3403
3404 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
3405 {
3406 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3407 and the target PC is in $2. */
3408 if (name[19] >= '0' && name[19] <= '9')
3409 return read_register (2);
3410
3411 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
c5aa993b
JM		 3412 before the jal instruction, this is effectively a call stub
3413 and the the target PC is in $2. Otherwise this is effectively
3414 a return stub and the target PC is in $18. */
c906108c
SS		 3415 else if (name[19] == 's' || name[19] == 'd')
3416 {
3417 if (pc == start_addr)
3418 {
3419 /* Check if the target of the stub is a compiler-generated
c5aa993b
JM		 3420 stub. Such a stub for a function bar might have a name
3421 like __fn_stub_bar, and might look like this:
3422 mfc1 $4,$f13
3423 mfc1 $5,$f12
3424 mfc1 $6,$f15
3425 mfc1 $7,$f14
3426 la $1,bar (becomes a lui/addiu pair)
3427 jr $1
3428 So scan down to the lui/addi and extract the target
3429 address from those two instructions. */
c906108c
SS		 3430
3431 CORE_ADDR target_pc = read_register (2);
3432 t_inst inst;
3433 int i;
3434
3435 /* See if the name of the target function is __fn_stub_*. */
3436 if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
3437 return target_pc;
3438 if (strncmp (name, "__fn_stub_", 10) != 0
3439 && strcmp (name, "etext") != 0
3440 && strcmp (name, "_etext") != 0)
3441 return target_pc;
3442
3443 /* Scan through this _fn_stub_ code for the lui/addiu pair.
c5aa993b
JM		 3444 The limit on the search is arbitrarily set to 20
3445 instructions. FIXME. */
c906108c
SS		 3446 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
3447 {
c5aa993b
JM		 3448 inst = mips_fetch_instruction (target_pc);
3449 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
3450 pc = (inst << 16) & 0xffff0000; /* high word */
3451 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
3452 return pc | (inst & 0xffff); /* low word */
c906108c
SS		 3453 }
3454
3455 /* Couldn't find the lui/addui pair, so return stub address. */
3456 return target_pc;
3457 }
3458 else
3459 /* This is the 'return' part of a call stub. The return
3460 address is in $r18. */
3461 return read_register (18);
3462 }
3463 }
c5aa993b 3464 return 0; /* not a stub */
c906108c
SS		 3465}
3466
3467
3468/* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3469 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3470
3471int
3472mips_in_call_stub (pc, name)
3473 CORE_ADDR pc;
3474 char *name;
3475{
3476 CORE_ADDR start_addr;
3477
3478 /* Find the starting address of the function containing the PC. If the
3479 caller didn't give us a name, look it up at the same time. */
3480 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
3481 return 0;
3482
3483 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
3484 {
3485 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3486 if (name[19] >= '0' && name[19] <= '9')
3487 return 1;
3488 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
c5aa993b 3489 before the jal instruction, this is effectively a call stub. */
c906108c
SS		 3490 else if (name[19] == 's' || name[19] == 'd')
3491 return pc == start_addr;
3492 }
3493
c5aa993b 3494 return 0; /* not a stub */
c906108c
SS		 3495}
3496
3497
3498/* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3499 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3500
3501int
3502mips_in_return_stub (pc, name)
3503 CORE_ADDR pc;
3504 char *name;
3505{
3506 CORE_ADDR start_addr;
3507
3508 /* Find the starting address of the function containing the PC. */
3509 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
3510 return 0;
3511
3512 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3513 if (strcmp (name, "__mips16_ret_sf") == 0
3514 || strcmp (name, "__mips16_ret_df") == 0)
3515 return 1;
3516
3517 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
c5aa993b 3518 i.e. after the jal instruction, this is effectively a return stub. */
c906108c
SS		 3519 if (strncmp (name, "__mips16_call_stub_", 19) == 0
3520 && (name[19] == 's' || name[19] == 'd')
3521 && pc != start_addr)
3522 return 1;
3523
c5aa993b 3524 return 0; /* not a stub */
c906108c
SS		 3525}
3526
3527
3528/* Return non-zero if the PC is in a library helper function that should
3529 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3530
3531int
3532mips_ignore_helper (pc)
3533 CORE_ADDR pc;
3534{
3535 char *name;
3536
3537 /* Find the starting address and name of the function containing the PC. */
3538 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
3539 return 0;
3540
3541 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3542 that we want to ignore. */
3543 return (strcmp (name, "__mips16_ret_sf") == 0
3544 || strcmp (name, "__mips16_ret_df") == 0);
3545}
3546
3547
3548/* Return a location where we can set a breakpoint that will be hit
3549 when an inferior function call returns. This is normally the
3550 program's entry point. Executables that don't have an entry
3551 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3552 whose address is the location where the breakpoint should be placed. */
3553
3554CORE_ADDR
3555mips_call_dummy_address ()
3556{
3557 struct minimal_symbol *sym;
3558
3559 sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL);
3560 if (sym)
3561 return SYMBOL_VALUE_ADDRESS (sym);
3562 else
3563 return entry_point_address ();
3564}
3565
3566
2acceee2 3567
c906108c
SS		 3568void
3569_initialize_mips_tdep ()
3570{
3571 static struct cmd_list_element *mipsfpulist = NULL;
3572 struct cmd_list_element *c;
3573
c5aa993b 3574 if (!tm_print_insn) /* Someone may have already set it */
c906108c
SS		 3575 tm_print_insn = gdb_print_insn_mips;
3576
3577 /* Let the user turn off floating point and set the fence post for
3578 heuristic_proc_start. */
3579
3580 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
3581 "Set use of MIPS floating-point coprocessor.",
3582 &mipsfpulist, "set mipsfpu ", 0, &setlist);
3583 add_cmd ("single", class_support, set_mipsfpu_single_command,
3584 "Select single-precision MIPS floating-point coprocessor.",
3585 &mipsfpulist);
3586 add_cmd ("double", class_support, set_mipsfpu_double_command,
3587 "Select double-precision MIPS floating-point coprocessor .",
3588 &mipsfpulist);
3589 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
3590 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
3591 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
3592 add_cmd ("none", class_support, set_mipsfpu_none_command,
3593 "Select no MIPS floating-point coprocessor.",
3594 &mipsfpulist);
3595 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
3596 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
3597 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
3598 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
3599 "Select MIPS floating-point coprocessor automatically.",
3600 &mipsfpulist);
3601 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
3602 "Show current use of MIPS floating-point coprocessor target.",
3603 &showlist);
3604
3605 c = add_set_cmd ("processor", class_support, var_string_noescape,
3606 (char *) &tmp_mips_processor_type,
3607 "Set the type of MIPS processor in use.\n\
3608Set this to be able to access processor-type-specific registers.\n\
3609",
3610 &setlist);
3611 c->function.cfunc = mips_set_processor_type_command;
3612 c = add_show_from_set (c, &showlist);
3613 c->function.cfunc = mips_show_processor_type_command;
3614
3615 tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE);
3616 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0);
3617
3618 /* We really would like to have both "0" and "unlimited" work, but
3619 command.c doesn't deal with that. So make it a var_zinteger
3620 because the user can always use "999999" or some such for unlimited. */
3621 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
3622 (char *) &heuristic_fence_post,
3623 "\
3624Set the distance searched for the start of a function.\n\
3625If you are debugging a stripped executable, GDB needs to search through the\n\
3626program for the start of a function. This command sets the distance of the\n\
3627search. The only need to set it is when debugging a stripped executable.",
3628 &setlist);
3629 /* We need to throw away the frame cache when we set this, since it
3630 might change our ability to get backtraces. */
3631 c->function.sfunc = reinit_frame_cache_sfunc;
3632 add_show_from_set (c, &showlist);
3633
3634 /* Allow the user to control whether the upper bits of 64-bit
3635 addresses should be zeroed. */
3636 add_show_from_set
c5aa993b
JM		 3637 (add_set_cmd ("mask-address", no_class, var_boolean, (char *) &mask_address_p,
3638 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
c906108c
SS		 3639Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3640Without an argument, zeroing of upper address bits is enabled.", &setlist),
3641 &showlist);
43e526b9
JM		 3642
3643 /* Allow the user to control the size of 32 bit registers within the
3644 raw remote packet. */
3645 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
3646 class_obscure,
3647 var_boolean,
3648 (char *)&mips64_transfers_32bit_regs_p, "\
3649Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
3650Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
3651that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
365264 bits for others. Use \"off\" to disable compatibility mode",
3653 &setlist),
3654 &showlist);
c906108c 3655}
GDB Binutils - Deliverables
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