Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
dd824b04 DJ |
63 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
64 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
65 | #define ST0_FR (1 << 26) | |
66 | ||
b0069a17 AC |
67 | /* The sizes of floating point registers. */ |
68 | ||
69 | enum | |
70 | { | |
71 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
72 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
73 | }; | |
74 | ||
0dadbba0 | 75 | |
2e4ebe70 DJ |
76 | static const char *mips_abi_string; |
77 | ||
78 | static const char *mips_abi_strings[] = { | |
79 | "auto", | |
80 | "n32", | |
81 | "o32", | |
28d169de | 82 | "n64", |
2e4ebe70 DJ |
83 | "o64", |
84 | "eabi32", | |
85 | "eabi64", | |
86 | NULL | |
87 | }; | |
88 | ||
cce74817 | 89 | struct frame_extra_info |
6d82d43b AC |
90 | { |
91 | mips_extra_func_info_t proc_desc; | |
92 | int num_args; | |
93 | }; | |
cce74817 | 94 | |
d929b26f AC |
95 | /* Various MIPS ISA options (related to stack analysis) can be |
96 | overridden dynamically. Establish an enum/array for managing | |
97 | them. */ | |
98 | ||
53904c9e AC |
99 | static const char size_auto[] = "auto"; |
100 | static const char size_32[] = "32"; | |
101 | static const char size_64[] = "64"; | |
d929b26f | 102 | |
53904c9e | 103 | static const char *size_enums[] = { |
d929b26f AC |
104 | size_auto, |
105 | size_32, | |
106 | size_64, | |
a5ea2558 AC |
107 | 0 |
108 | }; | |
109 | ||
7a292a7a | 110 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 111 | support single-precision floating-point operations. */ |
c906108c SS |
112 | |
113 | enum mips_fpu_type | |
6d82d43b AC |
114 | { |
115 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
116 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
117 | MIPS_FPU_NONE /* No floating point. */ | |
118 | }; | |
c906108c SS |
119 | |
120 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
121 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
122 | #endif | |
123 | static int mips_fpu_type_auto = 1; | |
124 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 125 | |
9ace0497 | 126 | static int mips_debug = 0; |
7a292a7a | 127 | |
c2d11a7d JM |
128 | /* MIPS specific per-architecture information */ |
129 | struct gdbarch_tdep | |
6d82d43b AC |
130 | { |
131 | /* from the elf header */ | |
132 | int elf_flags; | |
133 | ||
134 | /* mips options */ | |
135 | enum mips_abi mips_abi; | |
136 | enum mips_abi found_abi; | |
137 | enum mips_fpu_type mips_fpu_type; | |
138 | int mips_last_arg_regnum; | |
139 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
140 | int default_mask_address_p; |
141 | /* Is the target using 64-bit raw integer registers but only | |
142 | storing a left-aligned 32-bit value in each? */ | |
143 | int mips64_transfers_32bit_regs_p; | |
144 | /* Indexes for various registers. IRIX and embedded have | |
145 | different values. This contains the "public" fields. Don't | |
146 | add any that do not need to be public. */ | |
147 | const struct mips_regnum *regnum; | |
148 | /* Register names table for the current register set. */ | |
149 | const char **mips_processor_reg_names; | |
150 | }; | |
c2d11a7d | 151 | |
fed7ba43 JB |
152 | static int |
153 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
154 | const char *from) | |
155 | { | |
156 | return 1; | |
157 | } | |
158 | ||
159 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
160 | They are implemented as a pair of 64bit doubles where the high | |
161 | part holds the result of the operation rounded to double, and | |
162 | the low double holds the difference between the exact result and | |
163 | the rounded result. So "high" + "low" contains the result with | |
164 | added precision. Unfortunately, the floatformat structure used | |
165 | by GDB is not powerful enough to describe this format. As a temporary | |
166 | measure, we define a 128bit floatformat that only uses the high part. | |
167 | We lose a bit of precision but that's probably the best we can do | |
168 | for now with the current infrastructure. */ | |
169 | ||
170 | static const struct floatformat floatformat_n32n64_long_double_big = | |
171 | { | |
172 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
173 | floatformat_intbit_no, | |
174 | "floatformat_ieee_double_big", | |
175 | n32n64_floatformat_always_valid | |
176 | }; | |
177 | ||
56cea623 AC |
178 | const struct mips_regnum * |
179 | mips_regnum (struct gdbarch *gdbarch) | |
180 | { | |
181 | return gdbarch_tdep (gdbarch)->regnum; | |
182 | } | |
183 | ||
184 | static int | |
185 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
186 | { | |
187 | return mips_regnum (gdbarch)->fp0 + 12; | |
188 | } | |
189 | ||
0dadbba0 | 190 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 191 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 192 | |
c2d11a7d | 193 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 194 | |
c2d11a7d | 195 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 196 | |
c2d11a7d | 197 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 198 | |
95404a3e AC |
199 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
200 | functions to test, set, or clear bit 0 of addresses. */ | |
201 | ||
202 | static CORE_ADDR | |
203 | is_mips16_addr (CORE_ADDR addr) | |
204 | { | |
205 | return ((addr) & 1); | |
206 | } | |
207 | ||
208 | static CORE_ADDR | |
209 | make_mips16_addr (CORE_ADDR addr) | |
210 | { | |
211 | return ((addr) | 1); | |
212 | } | |
213 | ||
214 | static CORE_ADDR | |
215 | unmake_mips16_addr (CORE_ADDR addr) | |
216 | { | |
217 | return ((addr) & ~1); | |
218 | } | |
219 | ||
22540ece AC |
220 | /* Return the contents of register REGNUM as a signed integer. */ |
221 | ||
222 | static LONGEST | |
223 | read_signed_register (int regnum) | |
224 | { | |
1d93fe1a AC |
225 | LONGEST val; |
226 | regcache_cooked_read_signed (current_regcache, regnum, &val); | |
227 | return val; | |
22540ece AC |
228 | } |
229 | ||
230 | static LONGEST | |
231 | read_signed_register_pid (int regnum, ptid_t ptid) | |
232 | { | |
233 | ptid_t save_ptid; | |
234 | LONGEST retval; | |
235 | ||
236 | if (ptid_equal (ptid, inferior_ptid)) | |
237 | return read_signed_register (regnum); | |
238 | ||
239 | save_ptid = inferior_ptid; | |
240 | ||
241 | inferior_ptid = ptid; | |
242 | ||
243 | retval = read_signed_register (regnum); | |
244 | ||
245 | inferior_ptid = save_ptid; | |
246 | ||
247 | return retval; | |
248 | } | |
249 | ||
d1973055 KB |
250 | /* Return the MIPS ABI associated with GDBARCH. */ |
251 | enum mips_abi | |
252 | mips_abi (struct gdbarch *gdbarch) | |
253 | { | |
254 | return gdbarch_tdep (gdbarch)->mips_abi; | |
255 | } | |
256 | ||
4246e332 | 257 | int |
1b13c4f6 | 258 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
259 | { |
260 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
261 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
262 | } | |
263 | ||
480d3dd2 AC |
264 | /* Return the currently configured (or set) saved register size. */ |
265 | ||
1b13c4f6 | 266 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 267 | |
d929b26f | 268 | static unsigned int |
13326b4e | 269 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 270 | { |
1b13c4f6 | 271 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
272 | switch (mips_abi (gdbarch)) |
273 | { | |
274 | case MIPS_ABI_EABI32: | |
275 | case MIPS_ABI_O32: | |
276 | return 4; | |
277 | case MIPS_ABI_N32: | |
278 | case MIPS_ABI_N64: | |
279 | case MIPS_ABI_O64: | |
280 | case MIPS_ABI_EABI64: | |
281 | return 8; | |
282 | case MIPS_ABI_UNKNOWN: | |
283 | case MIPS_ABI_LAST: | |
284 | default: | |
285 | internal_error (__FILE__, __LINE__, "bad switch"); | |
286 | } | |
1b13c4f6 | 287 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 288 | return 8; |
1b13c4f6 | 289 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
290 | return 4; |
291 | } | |
292 | ||
71b8ef93 | 293 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 294 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 295 | "info" field is used for this purpose. |
5a89d8aa MS |
296 | |
297 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
298 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
299 | minimal symbol to mark it as a 16-bit function | |
300 | ||
f594e5e9 | 301 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 302 | |
5a89d8aa | 303 | static void |
6d82d43b AC |
304 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
305 | { | |
306 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
307 | { | |
308 | MSYMBOL_INFO (msym) = (char *) | |
309 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
310 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
311 | } | |
5a89d8aa MS |
312 | } |
313 | ||
71b8ef93 MS |
314 | static int |
315 | msymbol_is_special (struct minimal_symbol *msym) | |
316 | { | |
317 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
318 | } | |
319 | ||
88658117 AC |
320 | /* XFER a value from the big/little/left end of the register. |
321 | Depending on the size of the value it might occupy the entire | |
322 | register or just part of it. Make an allowance for this, aligning | |
323 | things accordingly. */ | |
324 | ||
325 | static void | |
326 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
327 | enum bfd_endian endian, bfd_byte * in, |
328 | const bfd_byte * out, int buf_offset) | |
88658117 | 329 | { |
88658117 | 330 | int reg_offset = 0; |
a4b8ebc8 | 331 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
332 | /* Need to transfer the left or right part of the register, based on |
333 | the targets byte order. */ | |
88658117 AC |
334 | switch (endian) |
335 | { | |
336 | case BFD_ENDIAN_BIG: | |
719ec221 | 337 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
338 | break; |
339 | case BFD_ENDIAN_LITTLE: | |
340 | reg_offset = 0; | |
341 | break; | |
6d82d43b | 342 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
343 | reg_offset = 0; |
344 | break; | |
345 | default: | |
346 | internal_error (__FILE__, __LINE__, "bad switch"); | |
347 | } | |
348 | if (mips_debug) | |
cb1d2653 AC |
349 | fprintf_unfiltered (gdb_stderr, |
350 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
351 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
352 | if (mips_debug && out != NULL) |
353 | { | |
354 | int i; | |
cb1d2653 | 355 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 356 | for (i = 0; i < length; i++) |
cb1d2653 | 357 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
358 | } |
359 | if (in != NULL) | |
6d82d43b AC |
360 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
361 | in + buf_offset); | |
88658117 | 362 | if (out != NULL) |
6d82d43b AC |
363 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
364 | out + buf_offset); | |
88658117 AC |
365 | if (mips_debug && in != NULL) |
366 | { | |
367 | int i; | |
cb1d2653 | 368 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 369 | for (i = 0; i < length; i++) |
cb1d2653 | 370 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
371 | } |
372 | if (mips_debug) | |
373 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
374 | } | |
375 | ||
dd824b04 DJ |
376 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
377 | compatiblity mode. A return value of 1 means that we have | |
378 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
379 | ||
380 | static int | |
381 | mips2_fp_compat (void) | |
382 | { | |
383 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
384 | meaningful. */ | |
6d82d43b AC |
385 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
386 | 4) | |
dd824b04 DJ |
387 | return 0; |
388 | ||
389 | #if 0 | |
390 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
391 | in all the places we deal with FP registers. PR gdb/413. */ | |
392 | /* Otherwise check the FR bit in the status register - it controls | |
393 | the FP compatiblity mode. If it is clear we are in compatibility | |
394 | mode. */ | |
395 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
396 | return 1; | |
397 | #endif | |
361d1df0 | 398 | |
dd824b04 DJ |
399 | return 0; |
400 | } | |
401 | ||
d929b26f | 402 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 403 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
404 | data allocated after the registers have run out. */ |
405 | ||
53904c9e | 406 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
407 | |
408 | static unsigned int | |
13326b4e | 409 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
410 | { |
411 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 412 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
413 | else if (mips_stack_argsize_string == size_64) |
414 | return 8; | |
6d82d43b | 415 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
416 | return 4; |
417 | } | |
418 | ||
7a292a7a | 419 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 420 | |
c9343fd1 | 421 | struct mips_frame_cache; |
570b8f7c | 422 | static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR, |
c9343fd1 AC |
423 | struct frame_info *, |
424 | struct mips_frame_cache *); | |
eec63939 AC |
425 | static mips_extra_func_info_t non_heuristic_proc_desc (CORE_ADDR pc, |
426 | CORE_ADDR *addrptr); | |
c906108c | 427 | |
a14ed312 | 428 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 429 | |
a14ed312 | 430 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 431 | |
a14ed312 | 432 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 433 | |
177f84a3 | 434 | static CORE_ADDR after_prologue (CORE_ADDR pc); |
c906108c | 435 | |
67b2c998 DJ |
436 | static struct type *mips_float_register_type (void); |
437 | static struct type *mips_double_register_type (void); | |
438 | ||
acdb74a0 AC |
439 | /* The list of available "set mips " and "show mips " commands */ |
440 | ||
441 | static struct cmd_list_element *setmipscmdlist = NULL; | |
442 | static struct cmd_list_element *showmipscmdlist = NULL; | |
443 | ||
5e2e9765 KB |
444 | /* Integer registers 0 thru 31 are handled explicitly by |
445 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
446 | are listed in the followign tables. */ |
447 | ||
6d82d43b AC |
448 | enum |
449 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
450 | |
451 | /* Generic MIPS. */ | |
452 | ||
453 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
454 | "sr", "lo", "hi", "bad", "cause", "pc", |
455 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
456 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
457 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
458 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
459 | "fsr", "fir", "" /*"fp" */ , "", | |
460 | "", "", "", "", "", "", "", "", | |
461 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
462 | }; |
463 | ||
464 | /* Names of IDT R3041 registers. */ | |
465 | ||
466 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
467 | "sr", "lo", "hi", "bad", "cause", "pc", |
468 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
469 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
470 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
471 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
472 | "fsr", "fir", "", /*"fp" */ "", | |
473 | "", "", "bus", "ccfg", "", "", "", "", | |
474 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
475 | }; |
476 | ||
477 | /* Names of tx39 registers. */ | |
478 | ||
479 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
480 | "sr", "lo", "hi", "bad", "cause", "pc", |
481 | "", "", "", "", "", "", "", "", | |
482 | "", "", "", "", "", "", "", "", | |
483 | "", "", "", "", "", "", "", "", | |
484 | "", "", "", "", "", "", "", "", | |
485 | "", "", "", "", | |
486 | "", "", "", "", "", "", "", "", | |
487 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
488 | }; |
489 | ||
490 | /* Names of IRIX registers. */ | |
491 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
492 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
493 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
494 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
495 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
496 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
497 | }; |
498 | ||
cce74817 | 499 | |
5e2e9765 | 500 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 501 | static const char * |
5e2e9765 | 502 | mips_register_name (int regno) |
cce74817 | 503 | { |
691c0433 | 504 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
505 | /* GPR names for all ABIs other than n32/n64. */ |
506 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
507 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
508 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
509 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
510 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
511 | }; |
512 | ||
513 | /* GPR names for n32 and n64 ABIs. */ | |
514 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
515 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
516 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
517 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
518 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
519 | }; |
520 | ||
521 | enum mips_abi abi = mips_abi (current_gdbarch); | |
522 | ||
a4b8ebc8 AC |
523 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
524 | don't make the raw register names visible. */ | |
525 | int rawnum = regno % NUM_REGS; | |
526 | if (regno < NUM_REGS) | |
527 | return ""; | |
528 | ||
5e2e9765 KB |
529 | /* The MIPS integer registers are always mapped from 0 to 31. The |
530 | names of the registers (which reflects the conventions regarding | |
531 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 532 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
533 | { |
534 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 535 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 536 | else |
a4b8ebc8 | 537 | return mips_gpr_names[rawnum]; |
5e2e9765 | 538 | } |
a4b8ebc8 | 539 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
540 | { |
541 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
542 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
543 | } | |
5e2e9765 KB |
544 | else |
545 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 546 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 547 | } |
5e2e9765 | 548 | |
a4b8ebc8 | 549 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 550 | |
a4b8ebc8 AC |
551 | static int |
552 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
553 | struct reggroup *reggroup) | |
554 | { | |
555 | int vector_p; | |
556 | int float_p; | |
557 | int raw_p; | |
558 | int rawnum = regnum % NUM_REGS; | |
559 | int pseudo = regnum / NUM_REGS; | |
560 | if (reggroup == all_reggroup) | |
561 | return pseudo; | |
562 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
563 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
564 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
565 | (gdbarch), as not all architectures are multi-arch. */ | |
566 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 567 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
568 | return 0; |
569 | if (reggroup == float_reggroup) | |
570 | return float_p && pseudo; | |
571 | if (reggroup == vector_reggroup) | |
572 | return vector_p && pseudo; | |
573 | if (reggroup == general_reggroup) | |
574 | return (!vector_p && !float_p) && pseudo; | |
575 | /* Save the pseudo registers. Need to make certain that any code | |
576 | extracting register values from a saved register cache also uses | |
577 | pseudo registers. */ | |
578 | if (reggroup == save_reggroup) | |
579 | return raw_p && pseudo; | |
580 | /* Restore the same pseudo register. */ | |
581 | if (reggroup == restore_reggroup) | |
582 | return raw_p && pseudo; | |
6d82d43b | 583 | return 0; |
a4b8ebc8 AC |
584 | } |
585 | ||
586 | /* Map the symbol table registers which live in the range [1 * | |
587 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 588 | registers. Take care of alignment and size problems. */ |
c5aa993b | 589 | |
a4b8ebc8 AC |
590 | static void |
591 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
592 | int cookednum, void *buf) | |
593 | { | |
47ebcfbe | 594 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 595 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 596 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 597 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
598 | else if (register_size (gdbarch, rawnum) > |
599 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
600 | { |
601 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
602 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
603 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
604 | else | |
605 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
606 | } | |
607 | else | |
608 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
609 | } |
610 | ||
611 | static void | |
6d82d43b AC |
612 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
613 | struct regcache *regcache, int cookednum, | |
614 | const void *buf) | |
a4b8ebc8 | 615 | { |
47ebcfbe | 616 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 617 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 618 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 619 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
620 | else if (register_size (gdbarch, rawnum) > |
621 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
622 | { |
623 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
624 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
625 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
626 | else | |
627 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
628 | } | |
629 | else | |
630 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 631 | } |
c5aa993b | 632 | |
c906108c | 633 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 634 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
635 | |
636 | /* Heuristic_proc_start may hunt through the text section for a long | |
637 | time across a 2400 baud serial line. Allows the user to limit this | |
638 | search. */ | |
639 | ||
640 | static unsigned int heuristic_fence_post = 0; | |
641 | ||
c5aa993b JM |
642 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
643 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ | |
c906108c SS |
644 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
645 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) | |
646 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) | |
647 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) | |
648 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) | |
649 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) | |
650 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) | |
651 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) | |
6c0d6680 DJ |
652 | /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long, |
653 | this will corrupt pdr.iline. Fortunately we don't use it. */ | |
c906108c SS |
654 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
655 | #define _PROC_MAGIC_ 0x0F0F0F0F | |
c906108c | 656 | |
46cd78fb | 657 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
658 | register N. NOTE: This defines the pseudo register type so need to |
659 | rebuild the architecture vector. */ | |
43e526b9 JM |
660 | |
661 | static int mips64_transfers_32bit_regs_p = 0; | |
662 | ||
719ec221 AC |
663 | static void |
664 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
665 | struct cmd_list_element *c) | |
43e526b9 | 666 | { |
719ec221 AC |
667 | struct gdbarch_info info; |
668 | gdbarch_info_init (&info); | |
669 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
670 | instead of relying on globals. Doing that would let generic code | |
671 | handle the search for this specific architecture. */ | |
672 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 673 | { |
719ec221 AC |
674 | mips64_transfers_32bit_regs_p = 0; |
675 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 676 | } |
a4b8ebc8 AC |
677 | } |
678 | ||
47ebcfbe | 679 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 680 | |
ff2e87ac AC |
681 | static int |
682 | mips_convert_register_p (int regnum, struct type *type) | |
683 | { | |
684 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 685 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
686 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
687 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 688 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
689 | } |
690 | ||
42c466d7 | 691 | static void |
ff2e87ac AC |
692 | mips_register_to_value (struct frame_info *frame, int regnum, |
693 | struct type *type, void *to) | |
102182a9 | 694 | { |
7f5f525d AC |
695 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
696 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
697 | } |
698 | ||
42c466d7 | 699 | static void |
ff2e87ac AC |
700 | mips_value_to_register (struct frame_info *frame, int regnum, |
701 | struct type *type, const void *from) | |
102182a9 | 702 | { |
ff2e87ac AC |
703 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
704 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
705 | } |
706 | ||
a4b8ebc8 AC |
707 | /* Return the GDB type object for the "standard" data type of data in |
708 | register REG. */ | |
78fde5f8 KB |
709 | |
710 | static struct type * | |
a4b8ebc8 AC |
711 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
712 | { | |
5ef80fb0 | 713 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
714 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
715 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 716 | { |
5ef80fb0 | 717 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 718 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
719 | switch (gdbarch_byte_order (gdbarch)) |
720 | { | |
721 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 722 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
723 | return builtin_type_ieee_single_big; |
724 | else | |
725 | return builtin_type_ieee_double_big; | |
726 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 727 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
728 | return builtin_type_ieee_single_little; |
729 | else | |
730 | return builtin_type_ieee_double_little; | |
731 | case BFD_ENDIAN_UNKNOWN: | |
732 | default: | |
733 | internal_error (__FILE__, __LINE__, "bad switch"); | |
734 | } | |
a6425924 | 735 | } |
d5ac5a39 AC |
736 | else if (regnum < NUM_REGS) |
737 | { | |
738 | /* The raw or ISA registers. These are all sized according to | |
739 | the ISA regsize. */ | |
740 | if (mips_isa_regsize (gdbarch) == 4) | |
741 | return builtin_type_int32; | |
742 | else | |
743 | return builtin_type_int64; | |
744 | } | |
78fde5f8 | 745 | else |
d5ac5a39 AC |
746 | { |
747 | /* The cooked or ABI registers. These are sized according to | |
748 | the ABI (with a few complications). */ | |
749 | if (regnum >= (NUM_REGS | |
750 | + mips_regnum (current_gdbarch)->fp_control_status) | |
751 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) | |
752 | /* The pseudo/cooked view of the embedded registers is always | |
753 | 32-bit. The raw view is handled below. */ | |
754 | return builtin_type_int32; | |
755 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
756 | /* The target, while possibly using a 64-bit register buffer, | |
757 | is only transfering 32-bits of each integer register. | |
758 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
759 | return builtin_type_int32; | |
760 | else if (mips_abi_regsize (gdbarch) == 4) | |
761 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
762 | 32- or 64-bit). */ | |
763 | return builtin_type_int32; | |
764 | else | |
765 | /* 64-bit ABI. */ | |
766 | return builtin_type_int64; | |
767 | } | |
78fde5f8 KB |
768 | } |
769 | ||
bcb0cc15 MS |
770 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
771 | ||
772 | static CORE_ADDR | |
773 | mips_read_sp (void) | |
774 | { | |
f10683bb | 775 | return read_signed_register (MIPS_SP_REGNUM); |
bcb0cc15 MS |
776 | } |
777 | ||
c906108c | 778 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 779 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
780 | |
781 | static int | |
480d3dd2 | 782 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
783 | { |
784 | switch (mask_address_var) | |
785 | { | |
7f19b9a2 | 786 | case AUTO_BOOLEAN_TRUE: |
4014092b | 787 | return 1; |
7f19b9a2 | 788 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
789 | return 0; |
790 | break; | |
7f19b9a2 | 791 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 792 | return tdep->default_mask_address_p; |
4014092b | 793 | default: |
6d82d43b | 794 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 795 | return -1; |
361d1df0 | 796 | } |
4014092b AC |
797 | } |
798 | ||
799 | static void | |
e9e68a56 | 800 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 801 | { |
480d3dd2 | 802 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
803 | switch (mask_address_var) |
804 | { | |
7f19b9a2 | 805 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
806 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
807 | break; | |
7f19b9a2 | 808 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
809 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
810 | break; | |
7f19b9a2 | 811 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
812 | printf_filtered |
813 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
814 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
815 | break; |
816 | default: | |
6d82d43b | 817 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 818 | break; |
361d1df0 | 819 | } |
4014092b | 820 | } |
c906108c | 821 | |
c906108c SS |
822 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
823 | ||
0fe7e7c8 AC |
824 | int |
825 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
826 | { |
827 | struct minimal_symbol *sym; | |
828 | ||
829 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 830 | if (is_mips16_addr (memaddr)) |
c906108c SS |
831 | return 1; |
832 | ||
833 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
834 | the high bit of the info field. Use this to decide if the function is | |
835 | MIPS16 or normal MIPS. */ | |
836 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
837 | if (sym) | |
71b8ef93 | 838 | return msymbol_is_special (sym); |
c906108c SS |
839 | else |
840 | return 0; | |
841 | } | |
842 | ||
b2fa5097 | 843 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
844 | all registers should be sign extended for simplicity? */ |
845 | ||
846 | static CORE_ADDR | |
39f77062 | 847 | mips_read_pc (ptid_t ptid) |
6c997a34 | 848 | { |
b6cb9035 AC |
849 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
850 | } | |
851 | ||
58dfe9ff AC |
852 | static CORE_ADDR |
853 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
854 | { | |
edfae063 AC |
855 | return frame_unwind_register_signed (next_frame, |
856 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
857 | } | |
858 | ||
859 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
860 | dummy frame. The frame ID's base needs to match the TOS value | |
861 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
862 | breakpoint. */ | |
863 | ||
864 | static struct frame_id | |
865 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
866 | { | |
f10683bb | 867 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 868 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
869 | } |
870 | ||
b6cb9035 AC |
871 | static void |
872 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
873 | { | |
874 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 875 | } |
c906108c SS |
876 | |
877 | /* This returns the PC of the first inst after the prologue. If we can't | |
878 | find the prologue, then return 0. */ | |
879 | ||
880 | static CORE_ADDR | |
177f84a3 | 881 | after_prologue (CORE_ADDR pc) |
c906108c | 882 | { |
177f84a3 | 883 | mips_extra_func_info_t proc_desc; |
c906108c SS |
884 | struct symtab_and_line sal; |
885 | CORE_ADDR func_addr, func_end; | |
283be873 AC |
886 | CORE_ADDR startaddr = 0; |
887 | ||
888 | /* Pass a NULL next_frame to heuristic_proc_desc. We should not | |
889 | attempt to read the stack pointer from the current machine state, | |
890 | because the current machine state has nothing to do with the | |
891 | information we need from the proc_desc; and the process may or | |
892 | may not exist right now. */ | |
893 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
894 | if (proc_desc) | |
895 | { | |
896 | /* IF this is the topmost frame AND (this proc does not have | |
897 | debugging information OR the PC is in the procedure prologue) | |
898 | THEN create a "heuristic" proc_desc (by analyzing the actual | |
899 | code) to replace the "official" proc_desc. */ | |
900 | struct symtab_and_line val; | |
fb603883 | 901 | if (PROC_SYMBOL (proc_desc)) |
283be873 AC |
902 | { |
903 | val = find_pc_line (BLOCK_START | |
fb603883 AC |
904 | (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc))), |
905 | 0); | |
283be873 AC |
906 | val.pc = val.end ? val.end : pc; |
907 | } | |
fb603883 | 908 | if (!PROC_SYMBOL (proc_desc) || pc < val.pc) |
283be873 AC |
909 | { |
910 | mips_extra_func_info_t found_heuristic = | |
c9343fd1 | 911 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), pc, NULL, NULL); |
283be873 AC |
912 | if (found_heuristic) |
913 | proc_desc = found_heuristic; | |
914 | } | |
915 | } | |
916 | else | |
917 | { | |
918 | if (startaddr == 0) | |
919 | startaddr = heuristic_proc_start (pc); | |
c906108c | 920 | |
c9343fd1 | 921 | proc_desc = heuristic_proc_desc (startaddr, pc, NULL, NULL); |
283be873 | 922 | } |
c906108c SS |
923 | |
924 | if (proc_desc) | |
925 | { | |
926 | /* If function is frameless, then we need to do it the hard way. I | |
c5aa993b | 927 | strongly suspect that frameless always means prologueless... */ |
f10683bb | 928 | if (PROC_FRAME_REG (proc_desc) == MIPS_SP_REGNUM |
c906108c SS |
929 | && PROC_FRAME_OFFSET (proc_desc) == 0) |
930 | return 0; | |
931 | } | |
932 | ||
933 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
934 | return 0; /* Unknown */ | |
935 | ||
936 | sal = find_pc_line (func_addr, 0); | |
937 | ||
938 | if (sal.end < func_end) | |
939 | return sal.end; | |
940 | ||
941 | /* The line after the prologue is after the end of the function. In this | |
942 | case, tell the caller to find the prologue the hard way. */ | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
c906108c SS |
947 | /* Fetch and return instruction from the specified location. If the PC |
948 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
949 | ||
950 | static t_inst | |
acdb74a0 | 951 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 952 | { |
4c7d22cb | 953 | char buf[MIPS32_INSN_SIZE]; |
c906108c SS |
954 | int instlen; |
955 | int status; | |
956 | ||
0fe7e7c8 | 957 | if (mips_pc_is_mips16 (addr)) |
c906108c | 958 | { |
4c7d22cb | 959 | instlen = MIPS16_INSN_SIZE; |
95404a3e | 960 | addr = unmake_mips16_addr (addr); |
c906108c SS |
961 | } |
962 | else | |
4c7d22cb | 963 | instlen = MIPS32_INSN_SIZE; |
1f602b35 | 964 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
965 | if (status) |
966 | memory_error (status, addr); | |
967 | return extract_unsigned_integer (buf, instlen); | |
968 | } | |
969 | ||
edfae063 AC |
970 | static ULONGEST |
971 | mips16_fetch_instruction (CORE_ADDR addr) | |
972 | { | |
4c7d22cb | 973 | char buf[MIPS16_INSN_SIZE]; |
edfae063 AC |
974 | int status; |
975 | ||
edfae063 | 976 | addr = unmake_mips16_addr (addr); |
4c7d22cb | 977 | status = deprecated_read_memory_nobpt (addr, buf, sizeof (buf)); |
edfae063 AC |
978 | if (status) |
979 | memory_error (status, addr); | |
4c7d22cb | 980 | return extract_unsigned_integer (buf, sizeof (buf)); |
edfae063 AC |
981 | } |
982 | ||
c906108c | 983 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
984 | #define mips32_op(x) (x >> 26) |
985 | #define itype_op(x) (x >> 26) | |
986 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 987 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 988 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 989 | |
e135b889 DJ |
990 | #define jtype_op(x) (x >> 26) |
991 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 992 | |
e135b889 DJ |
993 | #define rtype_op(x) (x >> 26) |
994 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
995 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
996 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
997 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
998 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
999 | |
1000 | static CORE_ADDR | |
c5aa993b JM |
1001 | mips32_relative_offset (unsigned long inst) |
1002 | { | |
1003 | long x; | |
1004 | x = itype_immediate (inst); | |
1005 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 1006 | { |
c5aa993b | 1007 | x |= 0xffff0000; /* sign extension */ |
c906108c | 1008 | } |
c5aa993b JM |
1009 | x = x << 2; |
1010 | return x; | |
c906108c SS |
1011 | } |
1012 | ||
1013 | /* Determine whate to set a single step breakpoint while considering | |
1014 | branch prediction */ | |
5a89d8aa | 1015 | static CORE_ADDR |
c5aa993b JM |
1016 | mips32_next_pc (CORE_ADDR pc) |
1017 | { | |
1018 | unsigned long inst; | |
1019 | int op; | |
1020 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1021 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1022 | { |
e135b889 | 1023 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1024 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1025 | { |
e135b889 | 1026 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1027 | switch (op) |
1028 | { | |
e135b889 DJ |
1029 | case 0: /* BEQL */ |
1030 | goto equal_branch; | |
1031 | case 1: /* BNEL */ | |
1032 | goto neq_branch; | |
1033 | case 2: /* BLEZL */ | |
1034 | goto less_branch; | |
1035 | case 3: /* BGTZ */ | |
1036 | goto greater_branch; | |
c5aa993b JM |
1037 | default: |
1038 | pc += 4; | |
c906108c SS |
1039 | } |
1040 | } | |
e135b889 | 1041 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1042 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1043 | { |
1044 | int tf = itype_rt (inst) & 0x01; | |
1045 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
1046 | int fcrcs = |
1047 | read_signed_register (mips_regnum (current_gdbarch)-> | |
1048 | fp_control_status); | |
e135b889 DJ |
1049 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1050 | ||
1051 | if (((cond >> cnum) & 0x01) == tf) | |
1052 | pc += mips32_relative_offset (inst) + 4; | |
1053 | else | |
1054 | pc += 8; | |
1055 | } | |
c5aa993b JM |
1056 | else |
1057 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1058 | } |
1059 | else | |
c5aa993b JM |
1060 | { /* This gets way messy */ |
1061 | ||
c906108c | 1062 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1063 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1064 | { |
c5aa993b JM |
1065 | case 0: /* SPECIAL */ |
1066 | op = rtype_funct (inst); | |
1067 | switch (op) | |
1068 | { | |
1069 | case 8: /* JR */ | |
1070 | case 9: /* JALR */ | |
6c997a34 AC |
1071 | /* Set PC to that address */ |
1072 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
1073 | break; |
1074 | default: | |
1075 | pc += 4; | |
1076 | } | |
1077 | ||
6d82d43b | 1078 | break; /* end SPECIAL */ |
c5aa993b | 1079 | case 1: /* REGIMM */ |
c906108c | 1080 | { |
e135b889 DJ |
1081 | op = itype_rt (inst); /* branch condition */ |
1082 | switch (op) | |
c906108c | 1083 | { |
c5aa993b | 1084 | case 0: /* BLTZ */ |
e135b889 DJ |
1085 | case 2: /* BLTZL */ |
1086 | case 16: /* BLTZAL */ | |
c5aa993b | 1087 | case 18: /* BLTZALL */ |
c906108c | 1088 | less_branch: |
6c997a34 | 1089 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
1090 | pc += mips32_relative_offset (inst) + 4; |
1091 | else | |
1092 | pc += 8; /* after the delay slot */ | |
1093 | break; | |
e135b889 | 1094 | case 1: /* BGEZ */ |
c5aa993b JM |
1095 | case 3: /* BGEZL */ |
1096 | case 17: /* BGEZAL */ | |
1097 | case 19: /* BGEZALL */ | |
6c997a34 | 1098 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
1099 | pc += mips32_relative_offset (inst) + 4; |
1100 | else | |
1101 | pc += 8; /* after the delay slot */ | |
1102 | break; | |
e135b889 | 1103 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1104 | default: |
1105 | pc += 4; | |
c906108c SS |
1106 | } |
1107 | } | |
6d82d43b | 1108 | break; /* end REGIMM */ |
c5aa993b JM |
1109 | case 2: /* J */ |
1110 | case 3: /* JAL */ | |
1111 | { | |
1112 | unsigned long reg; | |
1113 | reg = jtype_target (inst) << 2; | |
e135b889 | 1114 | /* Upper four bits get never changed... */ |
c5aa993b | 1115 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1116 | } |
c5aa993b JM |
1117 | break; |
1118 | /* FIXME case JALX : */ | |
1119 | { | |
1120 | unsigned long reg; | |
1121 | reg = jtype_target (inst) << 2; | |
1122 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1123 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1124 | } | |
c5aa993b | 1125 | break; /* The new PC will be alternate mode */ |
e135b889 | 1126 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1127 | equal_branch: |
6c997a34 AC |
1128 | if (read_signed_register (itype_rs (inst)) == |
1129 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1130 | pc += mips32_relative_offset (inst) + 4; |
1131 | else | |
1132 | pc += 8; | |
1133 | break; | |
e135b889 | 1134 | case 5: /* BNE, BNEL */ |
c5aa993b | 1135 | neq_branch: |
6c997a34 | 1136 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1137 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1138 | pc += mips32_relative_offset (inst) + 4; |
1139 | else | |
1140 | pc += 8; | |
1141 | break; | |
e135b889 | 1142 | case 6: /* BLEZ, BLEZL */ |
1fd8cd20 | 1143 | if (read_signed_register (itype_rs (inst)) <= 0) |
c5aa993b JM |
1144 | pc += mips32_relative_offset (inst) + 4; |
1145 | else | |
1146 | pc += 8; | |
1147 | break; | |
1148 | case 7: | |
e135b889 DJ |
1149 | default: |
1150 | greater_branch: /* BGTZ, BGTZL */ | |
1fd8cd20 | 1151 | if (read_signed_register (itype_rs (inst)) > 0) |
c5aa993b JM |
1152 | pc += mips32_relative_offset (inst) + 4; |
1153 | else | |
1154 | pc += 8; | |
1155 | break; | |
c5aa993b JM |
1156 | } /* switch */ |
1157 | } /* else */ | |
1158 | return pc; | |
1159 | } /* mips32_next_pc */ | |
c906108c SS |
1160 | |
1161 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1162 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1163 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1164 | We dont want to set a single step instruction on the extend instruction | |
1165 | either. | |
c5aa993b | 1166 | */ |
c906108c SS |
1167 | |
1168 | /* Lots of mips16 instruction formats */ | |
1169 | /* Predicting jumps requires itype,ritype,i8type | |
1170 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1171 | */ |
c906108c SS |
1172 | enum mips16_inst_fmts |
1173 | { | |
c5aa993b JM |
1174 | itype, /* 0 immediate 5,10 */ |
1175 | ritype, /* 1 5,3,8 */ | |
1176 | rrtype, /* 2 5,3,3,5 */ | |
1177 | rritype, /* 3 5,3,3,5 */ | |
1178 | rrrtype, /* 4 5,3,3,3,2 */ | |
1179 | rriatype, /* 5 5,3,3,1,4 */ | |
1180 | shifttype, /* 6 5,3,3,3,2 */ | |
1181 | i8type, /* 7 5,3,8 */ | |
1182 | i8movtype, /* 8 5,3,3,5 */ | |
1183 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1184 | i64type, /* 10 5,3,8 */ | |
1185 | ri64type, /* 11 5,3,3,5 */ | |
1186 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1187 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1188 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1189 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1190 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1191 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1192 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1193 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1194 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1195 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1196 | }; | |
12f02c2a AC |
1197 | /* I am heaping all the fields of the formats into one structure and |
1198 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1199 | struct upk_mips16 |
6d82d43b AC |
1200 | { |
1201 | CORE_ADDR offset; | |
1202 | unsigned int regx; /* Function in i8 type */ | |
1203 | unsigned int regy; | |
1204 | }; | |
c906108c SS |
1205 | |
1206 | ||
12f02c2a AC |
1207 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1208 | for the bits which make up the immediatate extension. */ | |
c906108c | 1209 | |
12f02c2a AC |
1210 | static CORE_ADDR |
1211 | extended_offset (unsigned int extension) | |
c906108c | 1212 | { |
12f02c2a | 1213 | CORE_ADDR value; |
c5aa993b JM |
1214 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1215 | value = value << 6; | |
1216 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1217 | value = value << 5; | |
1218 | value |= extension & 0x01f; /* extract 4:0 */ | |
1219 | return value; | |
c906108c SS |
1220 | } |
1221 | ||
1222 | /* Only call this function if you know that this is an extendable | |
1223 | instruction, It wont malfunction, but why make excess remote memory references? | |
1224 | If the immediate operands get sign extended or somthing, do it after | |
1225 | the extension is performed. | |
c5aa993b | 1226 | */ |
c906108c SS |
1227 | /* FIXME: Every one of these cases needs to worry about sign extension |
1228 | when the offset is to be used in relative addressing */ | |
1229 | ||
1230 | ||
12f02c2a | 1231 | static unsigned int |
c5aa993b | 1232 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1233 | { |
c5aa993b JM |
1234 | char buf[8]; |
1235 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1236 | target_read_memory (pc, buf, 2); | |
1237 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1238 | } |
1239 | ||
1240 | static void | |
c5aa993b | 1241 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1242 | unsigned int extension, |
1243 | unsigned int inst, | |
6d82d43b | 1244 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1245 | { |
12f02c2a AC |
1246 | CORE_ADDR offset; |
1247 | int regx; | |
1248 | int regy; | |
1249 | switch (insn_format) | |
c906108c | 1250 | { |
c5aa993b | 1251 | case itype: |
c906108c | 1252 | { |
12f02c2a AC |
1253 | CORE_ADDR value; |
1254 | if (extension) | |
c5aa993b JM |
1255 | { |
1256 | value = extended_offset (extension); | |
1257 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1258 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1259 | } |
1260 | else | |
c5aa993b | 1261 | { |
12f02c2a | 1262 | value = inst & 0x7ff; |
c5aa993b | 1263 | /* FIXME : Consider sign extension */ |
c906108c | 1264 | } |
12f02c2a AC |
1265 | offset = value; |
1266 | regx = -1; | |
1267 | regy = -1; | |
c906108c | 1268 | } |
c5aa993b JM |
1269 | break; |
1270 | case ritype: | |
1271 | case i8type: | |
1272 | { /* A register identifier and an offset */ | |
c906108c SS |
1273 | /* Most of the fields are the same as I type but the |
1274 | immediate value is of a different length */ | |
12f02c2a AC |
1275 | CORE_ADDR value; |
1276 | if (extension) | |
c906108c | 1277 | { |
c5aa993b JM |
1278 | value = extended_offset (extension); |
1279 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1280 | value |= inst & 0xff; /* eleven bits from instruction */ |
1281 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1282 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1283 | { | |
1284 | value &= ~0x3fff; /* remove the sign bit */ | |
1285 | value = -value; | |
c906108c SS |
1286 | } |
1287 | } | |
c5aa993b JM |
1288 | else |
1289 | { | |
12f02c2a AC |
1290 | value = inst & 0xff; /* 8 bits */ |
1291 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1292 | /* FIXME: Do sign extension , this format needs it */ |
1293 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1294 | { | |
1295 | value &= 0xef; /* remove the sign bit */ | |
1296 | value = -value; | |
1297 | } | |
c5aa993b | 1298 | } |
12f02c2a AC |
1299 | offset = value; |
1300 | regy = -1; | |
c5aa993b | 1301 | break; |
c906108c | 1302 | } |
c5aa993b | 1303 | case jalxtype: |
c906108c | 1304 | { |
c5aa993b | 1305 | unsigned long value; |
12f02c2a AC |
1306 | unsigned int nexthalf; |
1307 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1308 | value = value << 16; |
1309 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1310 | value |= nexthalf; | |
12f02c2a AC |
1311 | offset = value; |
1312 | regx = -1; | |
1313 | regy = -1; | |
c5aa993b | 1314 | break; |
c906108c SS |
1315 | } |
1316 | default: | |
6d82d43b | 1317 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1318 | } |
12f02c2a AC |
1319 | upk->offset = offset; |
1320 | upk->regx = regx; | |
1321 | upk->regy = regy; | |
c906108c SS |
1322 | } |
1323 | ||
1324 | ||
c5aa993b JM |
1325 | static CORE_ADDR |
1326 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1327 | { |
c5aa993b | 1328 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1329 | } |
1330 | ||
12f02c2a AC |
1331 | static CORE_ADDR |
1332 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1333 | unsigned int extension, unsigned int insn) |
c906108c | 1334 | { |
12f02c2a AC |
1335 | int op = (insn >> 11); |
1336 | switch (op) | |
c906108c | 1337 | { |
6d82d43b | 1338 | case 2: /* Branch */ |
12f02c2a AC |
1339 | { |
1340 | CORE_ADDR offset; | |
1341 | struct upk_mips16 upk; | |
1342 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1343 | offset = upk.offset; | |
1344 | if (offset & 0x800) | |
1345 | { | |
1346 | offset &= 0xeff; | |
1347 | offset = -offset; | |
1348 | } | |
1349 | pc += (offset << 1) + 2; | |
1350 | break; | |
1351 | } | |
6d82d43b | 1352 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1353 | { |
1354 | struct upk_mips16 upk; | |
1355 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1356 | pc = add_offset_16 (pc, upk.offset); | |
1357 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1358 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1359 | else | |
1360 | pc |= 0x01; | |
1361 | break; | |
1362 | } | |
6d82d43b | 1363 | case 4: /* beqz */ |
12f02c2a AC |
1364 | { |
1365 | struct upk_mips16 upk; | |
1366 | int reg; | |
1367 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1368 | reg = read_signed_register (upk.regx); | |
1369 | if (reg == 0) | |
1370 | pc += (upk.offset << 1) + 2; | |
1371 | else | |
1372 | pc += 2; | |
1373 | break; | |
1374 | } | |
6d82d43b | 1375 | case 5: /* bnez */ |
12f02c2a AC |
1376 | { |
1377 | struct upk_mips16 upk; | |
1378 | int reg; | |
1379 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1380 | reg = read_signed_register (upk.regx); | |
1381 | if (reg != 0) | |
1382 | pc += (upk.offset << 1) + 2; | |
1383 | else | |
1384 | pc += 2; | |
1385 | break; | |
1386 | } | |
6d82d43b | 1387 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1388 | { |
1389 | struct upk_mips16 upk; | |
1390 | int reg; | |
1391 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1392 | /* upk.regx contains the opcode */ | |
1393 | reg = read_signed_register (24); /* Test register is 24 */ | |
1394 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1395 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1396 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1397 | pc += (upk.offset << 1) + 2; | |
1398 | else | |
1399 | pc += 2; | |
1400 | break; | |
1401 | } | |
6d82d43b | 1402 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1403 | { |
1404 | struct upk_mips16 upk; | |
1405 | /* upk.fmt = rrtype; */ | |
1406 | op = insn & 0x1f; | |
1407 | if (op == 0) | |
c5aa993b | 1408 | { |
12f02c2a AC |
1409 | int reg; |
1410 | upk.regx = (insn >> 8) & 0x07; | |
1411 | upk.regy = (insn >> 5) & 0x07; | |
1412 | switch (upk.regy) | |
c5aa993b | 1413 | { |
12f02c2a AC |
1414 | case 0: |
1415 | reg = upk.regx; | |
1416 | break; | |
1417 | case 1: | |
1418 | reg = 31; | |
6d82d43b | 1419 | break; /* Function return instruction */ |
12f02c2a AC |
1420 | case 2: |
1421 | reg = upk.regx; | |
1422 | break; | |
1423 | default: | |
1424 | reg = 31; | |
6d82d43b | 1425 | break; /* BOGUS Guess */ |
c906108c | 1426 | } |
12f02c2a | 1427 | pc = read_signed_register (reg); |
c906108c | 1428 | } |
12f02c2a | 1429 | else |
c5aa993b | 1430 | pc += 2; |
12f02c2a AC |
1431 | break; |
1432 | } | |
1433 | case 30: | |
1434 | /* This is an instruction extension. Fetch the real instruction | |
1435 | (which follows the extension) and decode things based on | |
1436 | that. */ | |
1437 | { | |
1438 | pc += 2; | |
1439 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1440 | break; | |
1441 | } | |
1442 | default: | |
1443 | { | |
1444 | pc += 2; | |
1445 | break; | |
1446 | } | |
c906108c | 1447 | } |
c5aa993b | 1448 | return pc; |
12f02c2a | 1449 | } |
c906108c | 1450 | |
5a89d8aa | 1451 | static CORE_ADDR |
12f02c2a AC |
1452 | mips16_next_pc (CORE_ADDR pc) |
1453 | { | |
1454 | unsigned int insn = fetch_mips_16 (pc); | |
1455 | return extended_mips16_next_pc (pc, 0, insn); | |
1456 | } | |
1457 | ||
1458 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1459 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1460 | It works by decoding the current instruction and predicting where a |
1461 | branch will go. This isnt hard because all the data is available. | |
1462 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1463 | CORE_ADDR |
1464 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1465 | { |
c5aa993b JM |
1466 | if (pc & 0x01) |
1467 | return mips16_next_pc (pc); | |
1468 | else | |
1469 | return mips32_next_pc (pc); | |
12f02c2a | 1470 | } |
c906108c | 1471 | |
edfae063 AC |
1472 | struct mips_frame_cache |
1473 | { | |
1474 | CORE_ADDR base; | |
1475 | struct trad_frame_saved_reg *saved_regs; | |
1476 | }; | |
1477 | ||
1478 | ||
1479 | static struct mips_frame_cache * | |
1480 | mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1481 | { | |
0d5febcc | 1482 | CORE_ADDR startaddr = 0; |
edfae063 AC |
1483 | mips_extra_func_info_t proc_desc; |
1484 | struct mips_frame_cache *cache; | |
1485 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
1486 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1487 | /* r0 bit means kernel trap */ | |
1488 | int kernel_trap; | |
1489 | /* What registers have been saved? Bitmasks. */ | |
1490 | unsigned long gen_mask, float_mask; | |
1491 | ||
1492 | if ((*this_cache) != NULL) | |
1493 | return (*this_cache); | |
1494 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); | |
1495 | (*this_cache) = cache; | |
1496 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1497 | ||
1498 | /* Get the mdebug proc descriptor. */ | |
0d5febcc AC |
1499 | proc_desc = non_heuristic_proc_desc (frame_pc_unwind (next_frame), |
1500 | &startaddr); | |
1501 | /* Must be true. This is only called when the sniffer detected a | |
1502 | proc descriptor. */ | |
1503 | gdb_assert (proc_desc != NULL); | |
edfae063 AC |
1504 | |
1505 | /* Extract the frame's base. */ | |
1506 | cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc)) | |
1507 | + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); | |
1508 | ||
1509 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1510 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); | |
1511 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); | |
1512 | ||
9733cfe1 AC |
1513 | /* Must be true. The in_prologue case is left for the heuristic |
1514 | unwinder. This is always used on kernel traps. */ | |
1515 | gdb_assert (!in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc)) | |
1516 | || kernel_trap); | |
edfae063 AC |
1517 | |
1518 | /* Fill in the offsets for the registers which gen_mask says were | |
1519 | saved. */ | |
1520 | { | |
4fbbbd07 | 1521 | CORE_ADDR reg_position = (cache->base + PROC_REG_OFFSET (proc_desc)); |
edfae063 | 1522 | int ireg; |
4fbbbd07 | 1523 | |
edfae063 AC |
1524 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
1525 | if (gen_mask & 0x80000000) | |
1526 | { | |
1527 | cache->saved_regs[NUM_REGS + ireg].addr = reg_position; | |
13326b4e | 1528 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1529 | } |
1530 | } | |
1531 | ||
1532 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse | |
1533 | order of that normally used by gcc. Therefore, we have to fetch | |
1534 | the first instruction of the function, and if it's an entry | |
1535 | instruction that saves $s0 or $s1, correct their saved addresses. */ | |
0fe7e7c8 | 1536 | if (mips_pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
edfae063 AC |
1537 | { |
1538 | ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc)); | |
1539 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) | |
1540 | /* entry */ | |
1541 | { | |
1542 | int reg; | |
1543 | int sreg_count = (inst >> 6) & 3; | |
1544 | ||
1545 | /* Check if the ra register was pushed on the stack. */ | |
1546 | CORE_ADDR reg_position = (cache->base | |
1547 | + PROC_REG_OFFSET (proc_desc)); | |
1548 | if (inst & 0x20) | |
13326b4e | 1549 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1550 | |
1551 | /* Check if the s0 and s1 registers were pushed on the | |
1552 | stack. */ | |
1553 | /* NOTE: cagney/2004-02-08: Huh? This is doing no such | |
1554 | check. */ | |
1555 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1556 | { | |
1557 | cache->saved_regs[NUM_REGS + reg].addr = reg_position; | |
13326b4e | 1558 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1559 | } |
1560 | } | |
1561 | } | |
1562 | ||
1563 | /* Fill in the offsets for the registers which float_mask says were | |
1564 | saved. */ | |
1565 | { | |
1566 | CORE_ADDR reg_position = (cache->base | |
1567 | + PROC_FREG_OFFSET (proc_desc)); | |
1568 | int ireg; | |
1569 | /* Fill in the offsets for the float registers which float_mask | |
1570 | says were saved. */ | |
1571 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) | |
1572 | if (float_mask & 0x80000000) | |
1573 | { | |
13326b4e | 1574 | if (mips_abi_regsize (gdbarch) == 4 |
edfae063 AC |
1575 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1576 | { | |
1577 | /* On a big endian 32 bit ABI, floating point registers | |
1578 | are paired to form doubles such that the most | |
1579 | significant part is in $f[N+1] and the least | |
1580 | significant in $f[N] vis: $f[N+1] ||| $f[N]. The | |
1581 | registers are also spilled as a pair and stored as a | |
1582 | double. | |
1583 | ||
1584 | When little-endian the least significant part is | |
1585 | stored first leading to the memory order $f[N] and | |
1586 | then $f[N+1]. | |
1587 | ||
1588 | Unfortunately, when big-endian the most significant | |
1589 | part of the double is stored first, and the least | |
1590 | significant is stored second. This leads to the | |
1591 | registers being ordered in memory as firt $f[N+1] and | |
1592 | then $f[N]. | |
1593 | ||
1594 | For the big-endian case make certain that the | |
1595 | addresses point at the correct (swapped) locations | |
1596 | $f[N] and $f[N+1] pair (keep in mind that | |
1597 | reg_position is decremented each time through the | |
1598 | loop). */ | |
1599 | if ((ireg & 1)) | |
1600 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1601 | .addr = reg_position - mips_abi_regsize (gdbarch); |
edfae063 AC |
1602 | else |
1603 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
13326b4e | 1604 | .addr = reg_position + mips_abi_regsize (gdbarch); |
edfae063 AC |
1605 | } |
1606 | else | |
1607 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg] | |
1608 | .addr = reg_position; | |
13326b4e | 1609 | reg_position -= mips_abi_regsize (gdbarch); |
edfae063 AC |
1610 | } |
1611 | ||
1612 | cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1613 | = cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
edfae063 AC |
1614 | } |
1615 | ||
1616 | /* SP_REGNUM, contains the value and not the address. */ | |
f10683bb | 1617 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); |
edfae063 AC |
1618 | |
1619 | return (*this_cache); | |
1620 | } | |
1621 | ||
1622 | static void | |
1623 | mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1624 | struct frame_id *this_id) | |
1625 | { | |
1626 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1627 | this_cache); | |
1628 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1629 | } | |
1630 | ||
1631 | static void | |
1632 | mips_mdebug_frame_prev_register (struct frame_info *next_frame, | |
1633 | void **this_cache, | |
1634 | int regnum, int *optimizedp, | |
1635 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1636 | int *realnump, void *valuep) | |
1637 | { | |
1638 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1639 | this_cache); | |
1f67027d AC |
1640 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
1641 | optimizedp, lvalp, addrp, realnump, valuep); | |
edfae063 AC |
1642 | } |
1643 | ||
1644 | static const struct frame_unwind mips_mdebug_frame_unwind = | |
1645 | { | |
1646 | NORMAL_FRAME, | |
1647 | mips_mdebug_frame_this_id, | |
1648 | mips_mdebug_frame_prev_register | |
1649 | }; | |
1650 | ||
1651 | static const struct frame_unwind * | |
1652 | mips_mdebug_frame_sniffer (struct frame_info *next_frame) | |
1653 | { | |
eec63939 AC |
1654 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1655 | CORE_ADDR startaddr = 0; | |
1656 | mips_extra_func_info_t proc_desc; | |
1657 | int kernel_trap; | |
1658 | ||
1659 | /* Only use the mdebug frame unwinder on mdebug frames where all the | |
1660 | registers have been saved. Leave hard cases such as no mdebug or | |
1661 | in prologue for the heuristic unwinders. */ | |
1662 | ||
1663 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); | |
1664 | if (proc_desc == NULL) | |
1665 | return NULL; | |
1666 | ||
1667 | /* Not sure exactly what kernel_trap means, but if it means the | |
1668 | kernel saves the registers without a prologue doing it, we better | |
1669 | not examine the prologue to see whether registers have been saved | |
1670 | yet. */ | |
1671 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; | |
1672 | if (kernel_trap) | |
1673 | return &mips_mdebug_frame_unwind; | |
1674 | ||
1675 | /* In any frame other than the innermost or a frame interrupted by a | |
1676 | signal, we assume that all registers have been saved. This | |
1677 | assumes that all register saves in a function happen before the | |
1678 | first function call. */ | |
1679 | if (!in_prologue (pc, PROC_LOW_ADDR (proc_desc))) | |
1680 | return &mips_mdebug_frame_unwind; | |
1681 | ||
1682 | return NULL; | |
edfae063 AC |
1683 | } |
1684 | ||
1685 | static CORE_ADDR | |
1686 | mips_mdebug_frame_base_address (struct frame_info *next_frame, | |
1687 | void **this_cache) | |
1688 | { | |
1689 | struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame, | |
1690 | this_cache); | |
1691 | return info->base; | |
1692 | } | |
1693 | ||
1694 | static const struct frame_base mips_mdebug_frame_base = { | |
1695 | &mips_mdebug_frame_unwind, | |
1696 | mips_mdebug_frame_base_address, | |
1697 | mips_mdebug_frame_base_address, | |
1698 | mips_mdebug_frame_base_address | |
1699 | }; | |
1700 | ||
1701 | static const struct frame_base * | |
1702 | mips_mdebug_frame_base_sniffer (struct frame_info *next_frame) | |
1703 | { | |
eec63939 AC |
1704 | if (mips_mdebug_frame_sniffer (next_frame) != NULL) |
1705 | return &mips_mdebug_frame_base; | |
1706 | else | |
1707 | return NULL; | |
1708 | } | |
1709 | ||
29639122 JB |
1710 | /* Set a register's saved stack address in temp_saved_regs. If an |
1711 | address has already been set for this register, do nothing; this | |
1712 | way we will only recognize the first save of a given register in a | |
1713 | function prologue. | |
eec63939 | 1714 | |
29639122 JB |
1715 | For simplicity, save the address in both [0 .. NUM_REGS) and |
1716 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1717 | is used as it is only second range (the ABI instead of ISA | |
1718 | registers) that comes into play when finding saved registers in a | |
1719 | frame. */ | |
eec63939 AC |
1720 | |
1721 | static void | |
29639122 JB |
1722 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1723 | CORE_ADDR offset) | |
eec63939 | 1724 | { |
29639122 JB |
1725 | if (this_cache != NULL |
1726 | && this_cache->saved_regs[regnum].addr == -1) | |
1727 | { | |
1728 | this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset; | |
1729 | this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset; | |
1730 | } | |
eec63939 AC |
1731 | } |
1732 | ||
eec63939 | 1733 | |
29639122 JB |
1734 | /* Fetch the immediate value from a MIPS16 instruction. |
1735 | If the previous instruction was an EXTEND, use it to extend | |
1736 | the upper bits of the immediate value. This is a helper function | |
1737 | for mips16_scan_prologue. */ | |
eec63939 | 1738 | |
29639122 JB |
1739 | static int |
1740 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1741 | unsigned short inst, /* current instruction */ | |
1742 | int nbits, /* number of bits in imm field */ | |
1743 | int scale, /* scale factor to be applied to imm */ | |
1744 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1745 | { |
29639122 | 1746 | int offset; |
eec63939 | 1747 | |
29639122 JB |
1748 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1749 | { | |
1750 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1751 | if (offset & 0x8000) /* check for negative extend */ | |
1752 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1753 | return offset | (inst & 0x1f); | |
1754 | } | |
eec63939 | 1755 | else |
29639122 JB |
1756 | { |
1757 | int max_imm = 1 << nbits; | |
1758 | int mask = max_imm - 1; | |
1759 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1760 | |
29639122 JB |
1761 | offset = inst & mask; |
1762 | if (is_signed && (offset & sign_bit)) | |
1763 | offset = 0 - (max_imm - offset); | |
1764 | return offset * scale; | |
1765 | } | |
1766 | } | |
eec63939 | 1767 | |
65596487 | 1768 | |
29639122 JB |
1769 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1770 | the associated FRAME_CACHE if not null. | |
1771 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1772 | |
29639122 JB |
1773 | static CORE_ADDR |
1774 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1775 | struct frame_info *next_frame, | |
1776 | struct mips_frame_cache *this_cache) | |
1777 | { | |
1778 | CORE_ADDR cur_pc; | |
1779 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1780 | CORE_ADDR sp; | |
1781 | long frame_offset = 0; /* Size of stack frame. */ | |
1782 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1783 | int frame_reg = MIPS_SP_REGNUM; | |
1784 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1785 | unsigned inst = 0; /* current instruction */ | |
1786 | unsigned entry_inst = 0; /* the entry instruction */ | |
1787 | int reg, offset; | |
a343eb3c | 1788 | |
29639122 JB |
1789 | int extend_bytes = 0; |
1790 | int prev_extend_bytes; | |
1791 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1792 | |
29639122 JB |
1793 | /* Can be called when there's no process, and hence when there's no |
1794 | NEXT_FRAME. */ | |
1795 | if (next_frame != NULL) | |
1796 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
1797 | else | |
1798 | sp = 0; | |
eec63939 | 1799 | |
29639122 JB |
1800 | if (limit_pc > start_pc + 200) |
1801 | limit_pc = start_pc + 200; | |
eec63939 | 1802 | |
4c7d22cb | 1803 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSN_SIZE) |
29639122 JB |
1804 | { |
1805 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1806 | the immediate offset extension from it in mips16_get_imm. */ | |
1807 | prev_inst = inst; | |
eec63939 | 1808 | |
29639122 JB |
1809 | /* Fetch and decode the instruction. */ |
1810 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1811 | |
29639122 JB |
1812 | /* Normally we ignore extend instructions. However, if it is |
1813 | not followed by a valid prologue instruction, then this | |
1814 | instruction is not part of the prologue either. We must | |
1815 | remember in this case to adjust the end_prologue_addr back | |
1816 | over the extend. */ | |
1817 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1818 | { | |
4c7d22cb | 1819 | extend_bytes = MIPS16_INSN_SIZE; |
29639122 JB |
1820 | continue; |
1821 | } | |
eec63939 | 1822 | |
29639122 JB |
1823 | prev_extend_bytes = extend_bytes; |
1824 | extend_bytes = 0; | |
eec63939 | 1825 | |
29639122 JB |
1826 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1827 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1828 | { | |
1829 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1830 | if (offset < 0) /* negative stack adjustment? */ | |
1831 | frame_offset -= offset; | |
1832 | else | |
1833 | /* Exit loop if a positive stack adjustment is found, which | |
1834 | usually means that the stack cleanup code in the function | |
1835 | epilogue is reached. */ | |
1836 | break; | |
1837 | } | |
1838 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1839 | { | |
1840 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1841 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1842 | set_reg_offset (this_cache, reg, sp + offset); | |
1843 | } | |
1844 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1845 | { | |
1846 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1847 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1848 | set_reg_offset (this_cache, reg, sp + offset); | |
1849 | } | |
1850 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1851 | { | |
1852 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1853 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1854 | } |
1855 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1856 | { | |
1857 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1858 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1859 | } |
1860 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1861 | { | |
1862 | frame_addr = sp; | |
1863 | frame_reg = 17; | |
1864 | } | |
1865 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1866 | { | |
1867 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1868 | frame_addr = sp + offset; | |
1869 | frame_reg = 17; | |
1870 | frame_adjust = offset; | |
1871 | } | |
1872 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1873 | { | |
1874 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1875 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1876 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1877 | } | |
1878 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1879 | { | |
1880 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1881 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1882 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1883 | } | |
1884 | else if ((inst & 0xf81f) == 0xe809 | |
1885 | && (inst & 0x700) != 0x700) /* entry */ | |
1886 | entry_inst = inst; /* save for later processing */ | |
1887 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
4c7d22cb | 1888 | cur_pc += MIPS16_INSN_SIZE; /* 32-bit instruction */ |
29639122 JB |
1889 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1890 | { | |
1891 | /* This instruction is part of the prologue, but we don't | |
1892 | need to do anything special to handle it. */ | |
1893 | } | |
1894 | else | |
1895 | { | |
1896 | /* This instruction is not an instruction typically found | |
1897 | in a prologue, so we must have reached the end of the | |
1898 | prologue. */ | |
1899 | if (end_prologue_addr == 0) | |
1900 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1901 | } | |
1902 | } | |
eec63939 | 1903 | |
29639122 JB |
1904 | /* The entry instruction is typically the first instruction in a function, |
1905 | and it stores registers at offsets relative to the value of the old SP | |
1906 | (before the prologue). But the value of the sp parameter to this | |
1907 | function is the new SP (after the prologue has been executed). So we | |
1908 | can't calculate those offsets until we've seen the entire prologue, | |
1909 | and can calculate what the old SP must have been. */ | |
1910 | if (entry_inst != 0) | |
1911 | { | |
1912 | int areg_count = (entry_inst >> 8) & 7; | |
1913 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1914 | |
29639122 JB |
1915 | /* The entry instruction always subtracts 32 from the SP. */ |
1916 | frame_offset += 32; | |
1917 | ||
1918 | /* Now we can calculate what the SP must have been at the | |
1919 | start of the function prologue. */ | |
1920 | sp += frame_offset; | |
1921 | ||
1922 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1923 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1924 | { | |
1925 | set_reg_offset (this_cache, reg, sp + offset); | |
1926 | offset += mips_abi_regsize (current_gdbarch); | |
1927 | } | |
1928 | ||
1929 | /* Check if the ra register was pushed on the stack. */ | |
1930 | offset = -4; | |
1931 | if (entry_inst & 0x20) | |
1932 | { | |
4c7d22cb | 1933 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1934 | offset -= mips_abi_regsize (current_gdbarch); |
1935 | } | |
1936 | ||
1937 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1938 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1939 | { | |
1940 | set_reg_offset (this_cache, reg, sp + offset); | |
1941 | offset -= mips_abi_regsize (current_gdbarch); | |
1942 | } | |
1943 | } | |
1944 | ||
1945 | if (this_cache != NULL) | |
1946 | { | |
1947 | this_cache->base = | |
1948 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
1949 | + frame_offset - frame_adjust); | |
1950 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1951 | be able to get rid of the assignment below, evetually. But it's | |
1952 | still needed for now. */ | |
1953 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1954 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 JB |
1955 | } |
1956 | ||
1957 | /* If we didn't reach the end of the prologue when scanning the function | |
1958 | instructions, then set end_prologue_addr to the address of the | |
1959 | instruction immediately after the last one we scanned. */ | |
1960 | if (end_prologue_addr == 0) | |
1961 | end_prologue_addr = cur_pc; | |
1962 | ||
1963 | return end_prologue_addr; | |
eec63939 AC |
1964 | } |
1965 | ||
29639122 JB |
1966 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1967 | Procedures that use the 32-bit instruction set are handled by the | |
1968 | mips_insn32 unwinder. */ | |
1969 | ||
1970 | static struct mips_frame_cache * | |
1971 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1972 | { |
29639122 | 1973 | struct mips_frame_cache *cache; |
eec63939 AC |
1974 | |
1975 | if ((*this_cache) != NULL) | |
1976 | return (*this_cache); | |
29639122 JB |
1977 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1978 | (*this_cache) = cache; | |
1979 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1980 | |
29639122 JB |
1981 | /* Analyze the function prologue. */ |
1982 | { | |
1983 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1984 | CORE_ADDR start_addr; | |
eec63939 | 1985 | |
29639122 JB |
1986 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1987 | if (start_addr == 0) | |
1988 | start_addr = heuristic_proc_start (pc); | |
1989 | /* We can't analyze the prologue if we couldn't find the begining | |
1990 | of the function. */ | |
1991 | if (start_addr == 0) | |
1992 | return cache; | |
eec63939 | 1993 | |
29639122 JB |
1994 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1995 | } | |
1996 | ||
1997 | /* SP_REGNUM, contains the value and not the address. */ | |
1998 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1999 | |
29639122 | 2000 | return (*this_cache); |
eec63939 AC |
2001 | } |
2002 | ||
2003 | static void | |
29639122 JB |
2004 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
2005 | struct frame_id *this_id) | |
eec63939 | 2006 | { |
29639122 JB |
2007 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
2008 | this_cache); | |
2009 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
eec63939 AC |
2010 | } |
2011 | ||
2012 | static void | |
29639122 | 2013 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
2014 | void **this_cache, |
2015 | int regnum, int *optimizedp, | |
2016 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2017 | int *realnump, void *valuep) | |
2018 | { | |
29639122 JB |
2019 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
2020 | this_cache); | |
2021 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2022 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
2023 | } |
2024 | ||
29639122 | 2025 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2026 | { |
2027 | NORMAL_FRAME, | |
29639122 JB |
2028 | mips_insn16_frame_this_id, |
2029 | mips_insn16_frame_prev_register | |
eec63939 AC |
2030 | }; |
2031 | ||
2032 | static const struct frame_unwind * | |
29639122 | 2033 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
2034 | { |
2035 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
0fe7e7c8 | 2036 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2037 | return &mips_insn16_frame_unwind; |
2038 | return NULL; | |
eec63939 AC |
2039 | } |
2040 | ||
2041 | static CORE_ADDR | |
29639122 JB |
2042 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
2043 | void **this_cache) | |
eec63939 | 2044 | { |
29639122 JB |
2045 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
2046 | this_cache); | |
2047 | return info->base; | |
eec63939 AC |
2048 | } |
2049 | ||
29639122 | 2050 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2051 | { |
29639122 JB |
2052 | &mips_insn16_frame_unwind, |
2053 | mips_insn16_frame_base_address, | |
2054 | mips_insn16_frame_base_address, | |
2055 | mips_insn16_frame_base_address | |
eec63939 AC |
2056 | }; |
2057 | ||
2058 | static const struct frame_base * | |
29639122 | 2059 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 2060 | { |
29639122 JB |
2061 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
2062 | return &mips_insn16_frame_base; | |
eec63939 AC |
2063 | else |
2064 | return NULL; | |
edfae063 AC |
2065 | } |
2066 | ||
29639122 JB |
2067 | /* Mark all the registers as unset in the saved_regs array |
2068 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
2069 | ||
2070 | void | |
2071 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 2072 | { |
29639122 JB |
2073 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
2074 | return; | |
2075 | ||
2076 | { | |
2077 | const int num_regs = NUM_REGS; | |
2078 | int i; | |
64159455 | 2079 | |
29639122 JB |
2080 | for (i = 0; i < num_regs; i++) |
2081 | { | |
2082 | this_cache->saved_regs[i].addr = -1; | |
2083 | } | |
2084 | } | |
c906108c SS |
2085 | } |
2086 | ||
29639122 JB |
2087 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2088 | the associated FRAME_CACHE if not null. | |
2089 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2090 | |
875e1767 | 2091 | static CORE_ADDR |
29639122 JB |
2092 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
2093 | struct frame_info *next_frame, | |
2094 | struct mips_frame_cache *this_cache) | |
c906108c | 2095 | { |
29639122 JB |
2096 | CORE_ADDR cur_pc; |
2097 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
2098 | CORE_ADDR sp; | |
2099 | long frame_offset; | |
2100 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2101 | |
29639122 JB |
2102 | CORE_ADDR end_prologue_addr = 0; |
2103 | int seen_sp_adjust = 0; | |
2104 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 2105 | |
29639122 JB |
2106 | /* Can be called when there's no process, and hence when there's no |
2107 | NEXT_FRAME. */ | |
2108 | if (next_frame != NULL) | |
2109 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2110 | else |
29639122 | 2111 | sp = 0; |
9022177c | 2112 | |
29639122 JB |
2113 | if (limit_pc > start_pc + 200) |
2114 | limit_pc = start_pc + 200; | |
9022177c | 2115 | |
29639122 | 2116 | restart: |
9022177c | 2117 | |
29639122 | 2118 | frame_offset = 0; |
4c7d22cb | 2119 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS32_INSN_SIZE) |
9022177c | 2120 | { |
29639122 JB |
2121 | unsigned long inst, high_word, low_word; |
2122 | int reg; | |
9022177c | 2123 | |
29639122 JB |
2124 | /* Fetch the instruction. */ |
2125 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 2126 | |
29639122 JB |
2127 | /* Save some code by pre-extracting some useful fields. */ |
2128 | high_word = (inst >> 16) & 0xffff; | |
2129 | low_word = inst & 0xffff; | |
2130 | reg = high_word & 0x1f; | |
fe29b929 | 2131 | |
29639122 JB |
2132 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
2133 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
2134 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2135 | { | |
2136 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
2137 | frame_offset += 0x10000 - low_word; | |
2138 | else | |
2139 | /* Exit loop if a positive stack adjustment is found, which | |
2140 | usually means that the stack cleanup code in the function | |
2141 | epilogue is reached. */ | |
2142 | break; | |
2143 | seen_sp_adjust = 1; | |
2144 | } | |
2145 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
2146 | { | |
2147 | set_reg_offset (this_cache, reg, sp + low_word); | |
2148 | } | |
2149 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
2150 | { | |
2151 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
2152 | set_reg_offset (this_cache, reg, sp + low_word); | |
2153 | } | |
2154 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2155 | { | |
2156 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2157 | if ((long) low_word != frame_offset) | |
2158 | frame_addr = sp + low_word; | |
2159 | else if (frame_reg == MIPS_SP_REGNUM) | |
2160 | { | |
2161 | unsigned alloca_adjust; | |
a4b8ebc8 | 2162 | |
29639122 JB |
2163 | frame_reg = 30; |
2164 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
2165 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
2166 | if (alloca_adjust > 0) | |
2167 | { | |
2168 | /* FP > SP + frame_size. This may be because of | |
2169 | an alloca or somethings similar. Fix sp to | |
2170 | "pre-alloca" value, and try again. */ | |
2171 | sp += alloca_adjust; | |
2172 | /* Need to reset the status of all registers. Otherwise, | |
2173 | we will hit a guard that prevents the new address | |
2174 | for each register to be recomputed during the second | |
2175 | pass. */ | |
2176 | reset_saved_regs (this_cache); | |
2177 | goto restart; | |
2178 | } | |
2179 | } | |
2180 | } | |
2181 | /* move $30,$sp. With different versions of gas this will be either | |
2182 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2183 | Accept any one of these. */ | |
2184 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2185 | { | |
2186 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
2187 | if (frame_reg == MIPS_SP_REGNUM) | |
2188 | { | |
2189 | unsigned alloca_adjust; | |
c906108c | 2190 | |
29639122 JB |
2191 | frame_reg = 30; |
2192 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
2193 | alloca_adjust = (unsigned) (frame_addr - sp); | |
2194 | if (alloca_adjust > 0) | |
2195 | { | |
2196 | /* FP > SP + frame_size. This may be because of | |
2197 | an alloca or somethings similar. Fix sp to | |
2198 | "pre-alloca" value, and try again. */ | |
2199 | sp = frame_addr; | |
2200 | /* Need to reset the status of all registers. Otherwise, | |
2201 | we will hit a guard that prevents the new address | |
2202 | for each register to be recomputed during the second | |
2203 | pass. */ | |
2204 | reset_saved_regs (this_cache); | |
2205 | goto restart; | |
2206 | } | |
2207 | } | |
2208 | } | |
2209 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
2210 | { | |
2211 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
2212 | } | |
2213 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2214 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2215 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2216 | || high_word == 0x3c1c /* lui $gp,n */ | |
2217 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2218 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2219 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2220 | ) | |
2221 | { | |
2222 | /* These instructions are part of the prologue, but we don't | |
2223 | need to do anything special to handle them. */ | |
2224 | } | |
2225 | /* The instructions below load $at or $t0 with an immediate | |
2226 | value in preparation for a stack adjustment via | |
2227 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
2228 | initialize a local variable, so we accept them only before | |
2229 | a stack adjustment instruction was seen. */ | |
2230 | else if (!seen_sp_adjust | |
2231 | && (high_word == 0x3c01 /* lui $at,n */ | |
2232 | || high_word == 0x3c08 /* lui $t0,n */ | |
2233 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2234 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2235 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2236 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2237 | )) | |
2238 | { | |
4c7d22cb | 2239 | load_immediate_bytes += MIPS32_INSN_SIZE; /* FIXME! */ |
29639122 JB |
2240 | } |
2241 | else | |
2242 | { | |
2243 | /* This instruction is not an instruction typically found | |
2244 | in a prologue, so we must have reached the end of the | |
2245 | prologue. */ | |
2246 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2247 | loop now? Why would we need to continue scanning the function | |
2248 | instructions? */ | |
2249 | if (end_prologue_addr == 0) | |
2250 | end_prologue_addr = cur_pc; | |
2251 | } | |
a4b8ebc8 | 2252 | } |
c906108c | 2253 | |
29639122 JB |
2254 | if (this_cache != NULL) |
2255 | { | |
2256 | this_cache->base = | |
2257 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
2258 | + frame_offset); | |
2259 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2260 | this assignment below, eventually. But it's still needed | |
2261 | for now. */ | |
2262 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 2263 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 | 2264 | } |
c906108c | 2265 | |
29639122 JB |
2266 | /* If we didn't reach the end of the prologue when scanning the function |
2267 | instructions, then set end_prologue_addr to the address of the | |
2268 | instruction immediately after the last one we scanned. */ | |
2269 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2270 | we may as well be careful and do our best if we have a null | |
2271 | end_prologue_addr. */ | |
2272 | if (end_prologue_addr == 0) | |
2273 | end_prologue_addr = cur_pc; | |
2274 | ||
2275 | /* In a frameless function, we might have incorrectly | |
2276 | skipped some load immediate instructions. Undo the skipping | |
2277 | if the load immediate was not followed by a stack adjustment. */ | |
2278 | if (load_immediate_bytes && !seen_sp_adjust) | |
2279 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2280 | |
29639122 | 2281 | return end_prologue_addr; |
c906108c SS |
2282 | } |
2283 | ||
29639122 JB |
2284 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2285 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2286 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2287 | unwinder. */ | |
c906108c | 2288 | |
29639122 JB |
2289 | static struct mips_frame_cache * |
2290 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2291 | { |
29639122 | 2292 | struct mips_frame_cache *cache; |
c906108c | 2293 | |
29639122 JB |
2294 | if ((*this_cache) != NULL) |
2295 | return (*this_cache); | |
c5aa993b | 2296 | |
29639122 JB |
2297 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2298 | (*this_cache) = cache; | |
2299 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2300 | |
29639122 JB |
2301 | /* Analyze the function prologue. */ |
2302 | { | |
2303 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2304 | CORE_ADDR start_addr; | |
c906108c | 2305 | |
29639122 JB |
2306 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2307 | if (start_addr == 0) | |
2308 | start_addr = heuristic_proc_start (pc); | |
2309 | /* We can't analyze the prologue if we couldn't find the begining | |
2310 | of the function. */ | |
2311 | if (start_addr == 0) | |
2312 | return cache; | |
c5aa993b | 2313 | |
29639122 JB |
2314 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2315 | } | |
2316 | ||
2317 | /* SP_REGNUM, contains the value and not the address. */ | |
2318 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
c5aa993b | 2319 | |
29639122 | 2320 | return (*this_cache); |
c906108c SS |
2321 | } |
2322 | ||
29639122 JB |
2323 | static void |
2324 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2325 | struct frame_id *this_id) | |
c906108c | 2326 | { |
29639122 JB |
2327 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2328 | this_cache); | |
2329 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2330 | } | |
c906108c | 2331 | |
29639122 JB |
2332 | static void |
2333 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2334 | void **this_cache, | |
2335 | int regnum, int *optimizedp, | |
2336 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2337 | int *realnump, void *valuep) | |
2338 | { | |
2339 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2340 | this_cache); | |
2341 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2342 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2343 | } |
2344 | ||
29639122 JB |
2345 | static const struct frame_unwind mips_insn32_frame_unwind = |
2346 | { | |
2347 | NORMAL_FRAME, | |
2348 | mips_insn32_frame_this_id, | |
2349 | mips_insn32_frame_prev_register | |
2350 | }; | |
c906108c | 2351 | |
29639122 JB |
2352 | static const struct frame_unwind * |
2353 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2354 | { | |
2355 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
0fe7e7c8 | 2356 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2357 | return &mips_insn32_frame_unwind; |
2358 | return NULL; | |
2359 | } | |
c906108c | 2360 | |
1c645fec | 2361 | static CORE_ADDR |
29639122 JB |
2362 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2363 | void **this_cache) | |
c906108c | 2364 | { |
29639122 JB |
2365 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2366 | this_cache); | |
2367 | return info->base; | |
2368 | } | |
c906108c | 2369 | |
29639122 JB |
2370 | static const struct frame_base mips_insn32_frame_base = |
2371 | { | |
2372 | &mips_insn32_frame_unwind, | |
2373 | mips_insn32_frame_base_address, | |
2374 | mips_insn32_frame_base_address, | |
2375 | mips_insn32_frame_base_address | |
2376 | }; | |
1c645fec | 2377 | |
29639122 JB |
2378 | static const struct frame_base * |
2379 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2380 | { | |
2381 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2382 | return &mips_insn32_frame_base; | |
a65bbe44 | 2383 | else |
29639122 JB |
2384 | return NULL; |
2385 | } | |
a65bbe44 | 2386 | |
29639122 JB |
2387 | static struct trad_frame_cache * |
2388 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2389 | { | |
2390 | CORE_ADDR pc; | |
2391 | CORE_ADDR start_addr; | |
2392 | CORE_ADDR stack_addr; | |
2393 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2394 | |
29639122 JB |
2395 | if ((*this_cache) != NULL) |
2396 | return (*this_cache); | |
2397 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2398 | (*this_cache) = this_trad_cache; | |
1c645fec | 2399 | |
29639122 | 2400 | /* The return address is in the link register. */ |
4c7d22cb | 2401 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM); |
1c645fec | 2402 | |
29639122 JB |
2403 | /* Frame ID, since it's a frameless / stackless function, no stack |
2404 | space is allocated and SP on entry is the current SP. */ | |
2405 | pc = frame_pc_unwind (next_frame); | |
2406 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2407 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2408 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2409 | |
29639122 JB |
2410 | /* Assume that the frame's base is the same as the |
2411 | stack-pointer. */ | |
2412 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2413 | |
29639122 JB |
2414 | return this_trad_cache; |
2415 | } | |
c906108c | 2416 | |
29639122 JB |
2417 | static void |
2418 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2419 | struct frame_id *this_id) | |
2420 | { | |
2421 | struct trad_frame_cache *this_trad_cache | |
2422 | = mips_stub_frame_cache (next_frame, this_cache); | |
2423 | trad_frame_get_id (this_trad_cache, this_id); | |
2424 | } | |
c906108c | 2425 | |
29639122 JB |
2426 | static void |
2427 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2428 | void **this_cache, | |
2429 | int regnum, int *optimizedp, | |
2430 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2431 | int *realnump, void *valuep) | |
2432 | { | |
2433 | struct trad_frame_cache *this_trad_cache | |
2434 | = mips_stub_frame_cache (next_frame, this_cache); | |
2435 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2436 | lvalp, addrp, realnump, valuep); | |
2437 | } | |
c906108c | 2438 | |
29639122 JB |
2439 | static const struct frame_unwind mips_stub_frame_unwind = |
2440 | { | |
2441 | NORMAL_FRAME, | |
2442 | mips_stub_frame_this_id, | |
2443 | mips_stub_frame_prev_register | |
2444 | }; | |
c906108c | 2445 | |
29639122 JB |
2446 | static const struct frame_unwind * |
2447 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2448 | { | |
2449 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2450 | if (in_plt_section (pc, NULL)) | |
2451 | return &mips_stub_frame_unwind; | |
2452 | else | |
2453 | return NULL; | |
2454 | } | |
c906108c | 2455 | |
29639122 JB |
2456 | static CORE_ADDR |
2457 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2458 | void **this_cache) | |
2459 | { | |
2460 | struct trad_frame_cache *this_trad_cache | |
2461 | = mips_stub_frame_cache (next_frame, this_cache); | |
2462 | return trad_frame_get_this_base (this_trad_cache); | |
2463 | } | |
0fce0821 | 2464 | |
29639122 JB |
2465 | static const struct frame_base mips_stub_frame_base = |
2466 | { | |
2467 | &mips_stub_frame_unwind, | |
2468 | mips_stub_frame_base_address, | |
2469 | mips_stub_frame_base_address, | |
2470 | mips_stub_frame_base_address | |
2471 | }; | |
2472 | ||
2473 | static const struct frame_base * | |
2474 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2475 | { | |
2476 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2477 | return &mips_stub_frame_base; | |
2478 | else | |
2479 | return NULL; | |
2480 | } | |
2481 | ||
2482 | static CORE_ADDR | |
2483 | read_next_frame_reg (struct frame_info *fi, int regno) | |
2484 | { | |
2485 | /* Always a pseudo. */ | |
2486 | gdb_assert (regno >= NUM_REGS); | |
2487 | if (fi == NULL) | |
0fce0821 | 2488 | { |
29639122 JB |
2489 | LONGEST val; |
2490 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2491 | return val; | |
0fce0821 | 2492 | } |
29639122 JB |
2493 | else |
2494 | return frame_unwind_register_signed (fi, regno); | |
1c645fec | 2495 | |
c906108c SS |
2496 | } |
2497 | ||
29639122 | 2498 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2499 | |
29639122 JB |
2500 | static CORE_ADDR |
2501 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2502 | { |
29639122 JB |
2503 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2504 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2505 | /* This hack is a work-around for existing boards using PMON, the | |
2506 | simulator, and any other 64-bit targets that doesn't have true | |
2507 | 64-bit addressing. On these targets, the upper 32 bits of | |
2508 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2509 | likely to have been sign extended to all 1s by instruction | |
2510 | sequences that load 32-bit addresses. For example, a typical | |
2511 | piece of code that loads an address is this: | |
65596487 | 2512 | |
29639122 JB |
2513 | lui $r2, <upper 16 bits> |
2514 | ori $r2, <lower 16 bits> | |
65596487 | 2515 | |
29639122 JB |
2516 | But the lui sign-extends the value such that the upper 32 bits |
2517 | may be all 1s. The workaround is simply to mask off these | |
2518 | bits. In the future, gcc may be changed to support true 64-bit | |
2519 | addressing, and this masking will have to be disabled. */ | |
2520 | return addr &= 0xffffffffUL; | |
2521 | else | |
2522 | return addr; | |
65596487 JB |
2523 | } |
2524 | ||
29639122 JB |
2525 | /* mips_software_single_step() is called just before we want to resume |
2526 | the inferior, if we want to single-step it but there is no hardware | |
2527 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
2528 | the target of the coming instruction and breakpoint it. | |
1e05a7bf | 2529 | |
29639122 JB |
2530 | single_step is also called just after the inferior stops. If we had |
2531 | set up a simulated single-step, we undo our damage. */ | |
2532 | ||
2533 | void | |
2534 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
c906108c | 2535 | { |
29639122 JB |
2536 | static CORE_ADDR next_pc; |
2537 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
2538 | static binsn_quantum break_mem; | |
2539 | CORE_ADDR pc; | |
65596487 | 2540 | |
29639122 JB |
2541 | if (insert_breakpoints_p) |
2542 | { | |
2543 | pc = read_register (mips_regnum (current_gdbarch)->pc); | |
2544 | next_pc = mips_next_pc (pc); | |
98b4dd94 | 2545 | |
29639122 JB |
2546 | target_insert_breakpoint (next_pc, break_mem); |
2547 | } | |
a65bbe44 | 2548 | else |
29639122 JB |
2549 | target_remove_breakpoint (next_pc, break_mem); |
2550 | } | |
a65bbe44 | 2551 | |
29639122 | 2552 | static struct mips_extra_func_info temp_proc_desc; |
a65bbe44 | 2553 | |
29639122 JB |
2554 | /* Test whether the PC points to the return instruction at the |
2555 | end of a function. */ | |
65596487 | 2556 | |
29639122 JB |
2557 | static int |
2558 | mips_about_to_return (CORE_ADDR pc) | |
2559 | { | |
0fe7e7c8 | 2560 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2561 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2562 | generates a "jr $ra"; other times it generates code to load | |
2563 | the return address from the stack to an accessible register (such | |
2564 | as $a3), then a "jr" using that register. This second case | |
2565 | is almost impossible to distinguish from an indirect jump | |
2566 | used for switch statements, so we don't even try. */ | |
2567 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2568 | else | |
2569 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2570 | } | |
c906108c | 2571 | |
c906108c | 2572 | |
29639122 JB |
2573 | /* This fencepost looks highly suspicious to me. Removing it also |
2574 | seems suspicious as it could affect remote debugging across serial | |
2575 | lines. */ | |
c906108c | 2576 | |
29639122 JB |
2577 | static CORE_ADDR |
2578 | heuristic_proc_start (CORE_ADDR pc) | |
2579 | { | |
2580 | CORE_ADDR start_pc; | |
2581 | CORE_ADDR fence; | |
2582 | int instlen; | |
2583 | int seen_adjsp = 0; | |
65596487 | 2584 | |
29639122 JB |
2585 | pc = ADDR_BITS_REMOVE (pc); |
2586 | start_pc = pc; | |
2587 | fence = start_pc - heuristic_fence_post; | |
2588 | if (start_pc == 0) | |
2589 | return 0; | |
65596487 | 2590 | |
29639122 JB |
2591 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2592 | fence = VM_MIN_ADDRESS; | |
65596487 | 2593 | |
0fe7e7c8 | 2594 | instlen = mips_pc_is_mips16 (pc) ? MIPS16_INSN_SIZE : MIPS32_INSN_SIZE; |
98b4dd94 | 2595 | |
29639122 JB |
2596 | /* search back for previous return */ |
2597 | for (start_pc -= instlen;; start_pc -= instlen) | |
2598 | if (start_pc < fence) | |
2599 | { | |
2600 | /* It's not clear to me why we reach this point when | |
2601 | stop_soon, but with this test, at least we | |
2602 | don't print out warnings for every child forked (eg, on | |
2603 | decstation). 22apr93 rich@cygnus.com. */ | |
2604 | if (stop_soon == NO_STOP_QUIETLY) | |
2605 | { | |
2606 | static int blurb_printed = 0; | |
98b4dd94 | 2607 | |
29639122 JB |
2608 | warning ("GDB can't find the start of the function at 0x%s.", |
2609 | paddr_nz (pc)); | |
2610 | ||
2611 | if (!blurb_printed) | |
2612 | { | |
2613 | /* This actually happens frequently in embedded | |
2614 | development, when you first connect to a board | |
2615 | and your stack pointer and pc are nowhere in | |
2616 | particular. This message needs to give people | |
2617 | in that situation enough information to | |
2618 | determine that it's no big deal. */ | |
2619 | printf_filtered ("\n\ | |
2620 | GDB is unable to find the start of the function at 0x%s\n\ | |
2621 | and thus can't determine the size of that function's stack frame.\n\ | |
2622 | This means that GDB may be unable to access that stack frame, or\n\ | |
2623 | the frames below it.\n\ | |
2624 | This problem is most likely caused by an invalid program counter or\n\ | |
2625 | stack pointer.\n\ | |
2626 | However, if you think GDB should simply search farther back\n\ | |
2627 | from 0x%s for code which looks like the beginning of a\n\ | |
2628 | function, you can increase the range of the search using the `set\n\ | |
2629 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2630 | blurb_printed = 1; | |
2631 | } | |
2632 | } | |
2633 | ||
2634 | return 0; | |
2635 | } | |
0fe7e7c8 | 2636 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2637 | { |
2638 | unsigned short inst; | |
2639 | ||
2640 | /* On MIPS16, any one of the following is likely to be the | |
2641 | start of a function: | |
2642 | entry | |
2643 | addiu sp,-n | |
2644 | daddiu sp,-n | |
2645 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2646 | inst = mips_fetch_instruction (start_pc); | |
2647 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2648 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2649 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2650 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2651 | break; | |
2652 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2653 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2654 | seen_adjsp = 1; | |
2655 | else | |
2656 | seen_adjsp = 0; | |
2657 | } | |
2658 | else if (mips_about_to_return (start_pc)) | |
2659 | { | |
4c7d22cb MK |
2660 | /* Skip return and its delay slot. */ |
2661 | start_pc += 2 * MIPS32_INSN_SIZE; | |
29639122 JB |
2662 | break; |
2663 | } | |
2664 | ||
2665 | return start_pc; | |
c906108c SS |
2666 | } |
2667 | ||
2668 | static mips_extra_func_info_t | |
acdb74a0 | 2669 | heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
c9343fd1 AC |
2670 | struct frame_info *next_frame, |
2671 | struct mips_frame_cache *this_cache) | |
c906108c | 2672 | { |
c5aa993b JM |
2673 | if (start_pc == 0) |
2674 | return NULL; | |
a65bbe44 | 2675 | |
c5aa993b | 2676 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); |
c906108c | 2677 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
f10683bb | 2678 | PROC_FRAME_REG (&temp_proc_desc) = MIPS_SP_REGNUM; |
4c7d22cb | 2679 | PROC_PC_REG (&temp_proc_desc) = MIPS_RA_REGNUM; |
c906108c | 2680 | |
0fe7e7c8 | 2681 | if (mips_pc_is_mips16 (start_pc)) |
a65bbe44 | 2682 | mips16_scan_prologue (start_pc, limit_pc, next_frame, this_cache); |
c906108c | 2683 | else |
a65bbe44 JB |
2684 | mips32_scan_prologue (start_pc, limit_pc, next_frame, this_cache); |
2685 | ||
c906108c SS |
2686 | return &temp_proc_desc; |
2687 | } | |
2688 | ||
6c0d6680 DJ |
2689 | struct mips_objfile_private |
2690 | { | |
2691 | bfd_size_type size; | |
2692 | char *contents; | |
2693 | }; | |
2694 | ||
2695 | /* Global used to communicate between non_heuristic_proc_desc and | |
2696 | compare_pdr_entries within qsort (). */ | |
2697 | static bfd *the_bfd; | |
2698 | ||
2699 | static int | |
2700 | compare_pdr_entries (const void *a, const void *b) | |
2701 | { | |
2702 | CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a); | |
2703 | CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b); | |
2704 | ||
2705 | if (lhs < rhs) | |
2706 | return -1; | |
2707 | else if (lhs == rhs) | |
2708 | return 0; | |
2709 | else | |
2710 | return 1; | |
2711 | } | |
2712 | ||
c906108c | 2713 | static mips_extra_func_info_t |
acdb74a0 | 2714 | non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr) |
c906108c SS |
2715 | { |
2716 | CORE_ADDR startaddr; | |
2717 | mips_extra_func_info_t proc_desc; | |
c5aa993b | 2718 | struct block *b = block_for_pc (pc); |
c906108c | 2719 | struct symbol *sym; |
6c0d6680 DJ |
2720 | struct obj_section *sec; |
2721 | struct mips_objfile_private *priv; | |
2722 | ||
c906108c SS |
2723 | find_pc_partial_function (pc, NULL, &startaddr, NULL); |
2724 | if (addrptr) | |
2725 | *addrptr = startaddr; | |
6c0d6680 DJ |
2726 | |
2727 | priv = NULL; | |
2728 | ||
2729 | sec = find_pc_section (pc); | |
2730 | if (sec != NULL) | |
c906108c | 2731 | { |
8d5f9dcb | 2732 | priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data); |
6c0d6680 DJ |
2733 | |
2734 | /* Search the ".pdr" section generated by GAS. This includes most of | |
6d82d43b | 2735 | the information normally found in ECOFF PDRs. */ |
6c0d6680 DJ |
2736 | |
2737 | the_bfd = sec->objfile->obfd; | |
2738 | if (priv == NULL | |
2739 | && (the_bfd->format == bfd_object | |
2740 | && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour | |
2741 | && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64)) | |
2742 | { | |
2743 | /* Right now GAS only outputs the address as a four-byte sequence. | |
2744 | This means that we should not bother with this method on 64-bit | |
2745 | targets (until that is fixed). */ | |
2746 | ||
8b92e4d5 | 2747 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2748 | sizeof (struct mips_objfile_private)); |
2749 | priv->size = 0; | |
8d5f9dcb | 2750 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2751 | } |
2752 | else if (priv == NULL) | |
2753 | { | |
2754 | asection *bfdsec; | |
2755 | ||
8b92e4d5 | 2756 | priv = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2757 | sizeof (struct mips_objfile_private)); |
2758 | ||
2759 | bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr"); | |
2760 | if (bfdsec != NULL) | |
2761 | { | |
2762 | priv->size = bfd_section_size (sec->objfile->obfd, bfdsec); | |
8b92e4d5 | 2763 | priv->contents = obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 DJ |
2764 | priv->size); |
2765 | bfd_get_section_contents (sec->objfile->obfd, bfdsec, | |
2766 | priv->contents, 0, priv->size); | |
2767 | ||
2768 | /* In general, the .pdr section is sorted. However, in the | |
6d82d43b AC |
2769 | presence of multiple code sections (and other corner cases) |
2770 | it can become unsorted. Sort it so that we can use a faster | |
2771 | binary search. */ | |
2772 | qsort (priv->contents, priv->size / 32, 32, | |
2773 | compare_pdr_entries); | |
6c0d6680 DJ |
2774 | } |
2775 | else | |
2776 | priv->size = 0; | |
2777 | ||
8d5f9dcb | 2778 | set_objfile_data (sec->objfile, mips_pdr_data, priv); |
6c0d6680 DJ |
2779 | } |
2780 | the_bfd = NULL; | |
2781 | ||
2782 | if (priv->size != 0) | |
2783 | { | |
2784 | int low, mid, high; | |
2785 | char *ptr; | |
34fcf120 | 2786 | CORE_ADDR pdr_pc; |
6c0d6680 DJ |
2787 | |
2788 | low = 0; | |
2789 | high = priv->size / 32; | |
2790 | ||
34fcf120 DJ |
2791 | /* We've found a .pdr section describing this objfile. We want to |
2792 | find the entry which describes this code address. The .pdr | |
2793 | information is not very descriptive; we have only a function | |
2794 | start address. We have to look for the closest entry, because | |
2795 | the local symbol at the beginning of this function may have | |
2796 | been stripped - so if we ask the symbol table for the start | |
2797 | address we may get a preceding global function. */ | |
2798 | ||
2799 | /* First, find the last .pdr entry starting at or before PC. */ | |
6c0d6680 DJ |
2800 | do |
2801 | { | |
6c0d6680 DJ |
2802 | mid = (low + high) / 2; |
2803 | ||
2804 | ptr = priv->contents + mid * 32; | |
2805 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2806 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2807 | SECT_OFF_TEXT (sec->objfile)); | |
34fcf120 DJ |
2808 | |
2809 | if (pdr_pc > pc) | |
6c0d6680 DJ |
2810 | high = mid; |
2811 | else | |
2812 | low = mid + 1; | |
2813 | } | |
2814 | while (low != high); | |
2815 | ||
34fcf120 DJ |
2816 | /* Both low and high point one past the PDR of interest. If |
2817 | both are zero, that means this PC is before any region | |
2818 | covered by a PDR, i.e. pdr_pc for the first PDR entry is | |
2819 | greater than PC. */ | |
2820 | if (low > 0) | |
2821 | { | |
2822 | ptr = priv->contents + (low - 1) * 32; | |
2823 | pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr); | |
2824 | pdr_pc += ANOFFSET (sec->objfile->section_offsets, | |
2825 | SECT_OFF_TEXT (sec->objfile)); | |
2826 | } | |
2827 | ||
2828 | /* We don't have a range, so we have no way to know for sure | |
2829 | whether we're in the correct PDR or a PDR for a preceding | |
2830 | function and the current function was a stripped local | |
2831 | symbol. But if the PDR's PC is at least as great as the | |
2832 | best guess from the symbol table, assume that it does cover | |
2833 | the right area; if a .pdr section is present at all then | |
2834 | nearly every function will have an entry. The biggest exception | |
2835 | will be the dynamic linker stubs; conveniently these are | |
2836 | placed before .text instead of after. */ | |
2837 | ||
2838 | if (pc >= pdr_pc && pdr_pc >= startaddr) | |
6c0d6680 DJ |
2839 | { |
2840 | struct symbol *sym = find_pc_function (pc); | |
2841 | ||
34fcf120 DJ |
2842 | if (addrptr) |
2843 | *addrptr = pdr_pc; | |
2844 | ||
6c0d6680 DJ |
2845 | /* Fill in what we need of the proc_desc. */ |
2846 | proc_desc = (mips_extra_func_info_t) | |
8b92e4d5 | 2847 | obstack_alloc (&sec->objfile->objfile_obstack, |
6c0d6680 | 2848 | sizeof (struct mips_extra_func_info)); |
34fcf120 | 2849 | PROC_LOW_ADDR (proc_desc) = pdr_pc; |
6c0d6680 DJ |
2850 | |
2851 | /* Only used for dummy frames. */ | |
2852 | PROC_HIGH_ADDR (proc_desc) = 0; | |
2853 | ||
2854 | PROC_FRAME_OFFSET (proc_desc) | |
2855 | = bfd_get_32 (sec->objfile->obfd, ptr + 20); | |
2856 | PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2857 | ptr + 24); | |
2858 | PROC_FRAME_ADJUST (proc_desc) = 0; | |
2859 | PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2860 | ptr + 4); | |
2861 | PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2862 | ptr + 12); | |
2863 | PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2864 | ptr + 8); | |
2865 | PROC_FREG_OFFSET (proc_desc) | |
2866 | = bfd_get_32 (sec->objfile->obfd, ptr + 16); | |
2867 | PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd, | |
2868 | ptr + 28); | |
2869 | proc_desc->pdr.isym = (long) sym; | |
2870 | ||
2871 | return proc_desc; | |
2872 | } | |
2873 | } | |
c906108c SS |
2874 | } |
2875 | ||
6c0d6680 DJ |
2876 | if (b == NULL) |
2877 | return NULL; | |
2878 | ||
2879 | if (startaddr > BLOCK_START (b)) | |
2880 | { | |
2881 | /* This is the "pathological" case referred to in a comment in | |
6d82d43b AC |
2882 | print_frame_info. It might be better to move this check into |
2883 | symbol reading. */ | |
6c0d6680 DJ |
2884 | return NULL; |
2885 | } | |
2886 | ||
176620f1 | 2887 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL); |
6c0d6680 | 2888 | |
c906108c SS |
2889 | /* If we never found a PDR for this function in symbol reading, then |
2890 | examine prologues to find the information. */ | |
2891 | if (sym) | |
2892 | { | |
2893 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); | |
2894 | if (PROC_FRAME_REG (proc_desc) == -1) | |
2895 | return NULL; | |
2896 | else | |
2897 | return proc_desc; | |
2898 | } | |
2899 | else | |
2900 | return NULL; | |
2901 | } | |
2902 | ||
c906108c SS |
2903 | /* MIPS stack frames are almost impenetrable. When execution stops, |
2904 | we basically have to look at symbol information for the function | |
2905 | that we stopped in, which tells us *which* register (if any) is | |
2906 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2907 | the frame itself is at. |
c906108c SS |
2908 | |
2909 | This presents a problem when trying to examine a stack in memory | |
2910 | (that isn't executing at the moment), using the "frame" command. We | |
2911 | don't have a PC, nor do we have any registers except SP. | |
2912 | ||
2913 | This routine takes two arguments, SP and PC, and tries to make the | |
2914 | cached frames look as if these two arguments defined a frame on the | |
2915 | cache. This allows the rest of info frame to extract the important | |
2916 | arguments without difficulty. */ | |
2917 | ||
2918 | struct frame_info * | |
acdb74a0 | 2919 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2920 | { |
2921 | if (argc != 2) | |
2922 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2923 | ||
2924 | return create_new_frame (argv[0], argv[1]); | |
2925 | } | |
2926 | ||
f09ded24 AC |
2927 | /* According to the current ABI, should the type be passed in a |
2928 | floating-point register (assuming that there is space)? When there | |
2929 | is no FPU, FP are not even considered as possibile candidates for | |
2930 | FP registers and, consequently this returns false - forces FP | |
2931 | arguments into integer registers. */ | |
2932 | ||
2933 | static int | |
2934 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2935 | { | |
2936 | return ((typecode == TYPE_CODE_FLT | |
2937 | || (MIPS_EABI | |
6d82d43b AC |
2938 | && (typecode == TYPE_CODE_STRUCT |
2939 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
2940 | && TYPE_NFIELDS (arg_type) == 1 |
2941 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2942 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2943 | } |
2944 | ||
49e790b0 DJ |
2945 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2946 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2947 | ||
2948 | static int | |
2949 | mips_type_needs_double_align (struct type *type) | |
2950 | { | |
2951 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2952 | |
49e790b0 DJ |
2953 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2954 | return 1; | |
2955 | else if (typecode == TYPE_CODE_STRUCT) | |
2956 | { | |
2957 | if (TYPE_NFIELDS (type) < 1) | |
2958 | return 0; | |
2959 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2960 | } | |
2961 | else if (typecode == TYPE_CODE_UNION) | |
2962 | { | |
361d1df0 | 2963 | int i, n; |
49e790b0 DJ |
2964 | |
2965 | n = TYPE_NFIELDS (type); | |
2966 | for (i = 0; i < n; i++) | |
2967 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2968 | return 1; | |
2969 | return 0; | |
2970 | } | |
2971 | return 0; | |
2972 | } | |
2973 | ||
dc604539 AC |
2974 | /* Adjust the address downward (direction of stack growth) so that it |
2975 | is correctly aligned for a new stack frame. */ | |
2976 | static CORE_ADDR | |
2977 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2978 | { | |
5b03f266 | 2979 | return align_down (addr, 16); |
dc604539 AC |
2980 | } |
2981 | ||
f7ab6ec6 | 2982 | static CORE_ADDR |
7d9b040b | 2983 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2984 | struct regcache *regcache, CORE_ADDR bp_addr, |
2985 | int nargs, struct value **args, CORE_ADDR sp, | |
2986 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2987 | { |
2988 | int argreg; | |
2989 | int float_argreg; | |
2990 | int argnum; | |
2991 | int len = 0; | |
2992 | int stack_offset = 0; | |
480d3dd2 | 2993 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2994 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 2995 | |
25ab4790 AC |
2996 | /* For shared libraries, "t9" needs to point at the function |
2997 | address. */ | |
4c7d22cb | 2998 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2999 | |
3000 | /* Set the return address register to point to the entry point of | |
3001 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3002 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3003 | |
c906108c | 3004 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
3005 | are properly aligned. The stack has to be at least 64-bit |
3006 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3007 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3008 | aligned, so we round to this widest known alignment. */ | |
3009 | ||
5b03f266 AC |
3010 | sp = align_down (sp, 16); |
3011 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 3012 | |
46e0f506 | 3013 | /* Now make space on the stack for the args. We allocate more |
c906108c | 3014 | than necessary for EABI, because the first few arguments are |
46e0f506 | 3015 | passed in registers, but that's OK. */ |
c906108c | 3016 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 3017 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3018 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3019 | sp -= align_up (len, 16); |
c906108c | 3020 | |
9ace0497 | 3021 | if (mips_debug) |
6d82d43b | 3022 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3023 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
3024 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 3025 | |
c906108c | 3026 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 3027 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3028 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 3029 | |
46e0f506 | 3030 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 3031 | if (struct_return) |
9ace0497 AC |
3032 | { |
3033 | if (mips_debug) | |
3034 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3035 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 3036 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
3037 | write_register (argreg++, struct_addr); |
3038 | } | |
c906108c SS |
3039 | |
3040 | /* Now load as many as possible of the first arguments into | |
3041 | registers, and push the rest onto the stack. Loop thru args | |
3042 | from first to last. */ | |
3043 | for (argnum = 0; argnum < nargs; argnum++) | |
3044 | { | |
3045 | char *val; | |
d9d9c31f | 3046 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 3047 | struct value *arg = args[argnum]; |
c906108c SS |
3048 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
3049 | int len = TYPE_LENGTH (arg_type); | |
3050 | enum type_code typecode = TYPE_CODE (arg_type); | |
3051 | ||
9ace0497 AC |
3052 | if (mips_debug) |
3053 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3054 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 3055 | argnum + 1, len, (int) typecode); |
9ace0497 | 3056 | |
c906108c | 3057 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 3058 | reference. */ |
13326b4e | 3059 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 3060 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 3061 | { |
13326b4e | 3062 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 3063 | VALUE_ADDRESS (arg)); |
c906108c | 3064 | typecode = TYPE_CODE_PTR; |
13326b4e | 3065 | len = mips_abi_regsize (gdbarch); |
c906108c | 3066 | val = valbuf; |
9ace0497 AC |
3067 | if (mips_debug) |
3068 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3069 | } |
3070 | else | |
c5aa993b | 3071 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
3072 | |
3073 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3074 | even-numbered floating point register. Round the FP register |
3075 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3076 | left. Non MIPS_EABI targets also pass the FP in the integer |
3077 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3078 | if (mips_abi_regsize (gdbarch) < 8 |
3079 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
3080 | { |
3081 | if ((float_argreg & 1)) | |
3082 | float_argreg++; | |
3083 | } | |
c906108c SS |
3084 | |
3085 | /* Floating point arguments passed in registers have to be | |
3086 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3087 | are passed in register pairs; the even register gets |
3088 | the low word, and the odd register gets the high word. | |
3089 | On non-EABI processors, the first two floating point arguments are | |
3090 | also copied to general registers, because MIPS16 functions | |
3091 | don't use float registers for arguments. This duplication of | |
3092 | arguments in general registers can't hurt non-MIPS16 functions | |
3093 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3094 | /* MIPS_EABI squeezes a struct that contains a single floating |
3095 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3096 | stack. */ |
f09ded24 AC |
3097 | if (fp_register_arg_p (typecode, arg_type) |
3098 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 3099 | { |
ceae6e75 | 3100 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 3101 | { |
d7449b42 | 3102 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
3103 | unsigned long regval; |
3104 | ||
3105 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 3106 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 3107 | if (mips_debug) |
acdb74a0 | 3108 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3109 | float_argreg, phex (regval, 4)); |
c906108c | 3110 | write_register (float_argreg++, regval); |
c906108c SS |
3111 | |
3112 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 3113 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 3114 | if (mips_debug) |
acdb74a0 | 3115 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3116 | float_argreg, phex (regval, 4)); |
c906108c | 3117 | write_register (float_argreg++, regval); |
c906108c SS |
3118 | } |
3119 | else | |
3120 | { | |
3121 | /* This is a floating point value that fits entirely | |
3122 | in a single register. */ | |
53a5351d | 3123 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3124 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
3125 | LONGEST regval = extract_unsigned_integer (val, len); |
3126 | if (mips_debug) | |
acdb74a0 | 3127 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3128 | float_argreg, phex (regval, len)); |
c906108c | 3129 | write_register (float_argreg++, regval); |
c906108c SS |
3130 | } |
3131 | } | |
3132 | else | |
3133 | { | |
3134 | /* Copy the argument to general registers or the stack in | |
3135 | register-sized pieces. Large arguments are split between | |
3136 | registers and stack. */ | |
4246e332 | 3137 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3138 | mips_abi_regsize() are treated specially: Irix cc passes |
3139 | them in registers where gcc sometimes puts them on the | |
3140 | stack. For maximum compatibility, we will put them in | |
3141 | both places. */ | |
13326b4e AC |
3142 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3143 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 3144 | |
f09ded24 | 3145 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3146 | register are only written to memory. */ |
c906108c SS |
3147 | while (len > 0) |
3148 | { | |
ebafbe83 | 3149 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3150 | int stack_used_p = 0; |
13326b4e AC |
3151 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3152 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 3153 | |
acdb74a0 AC |
3154 | if (mips_debug) |
3155 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3156 | partial_len); | |
3157 | ||
566f0f7a | 3158 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
3159 | if (argreg > MIPS_LAST_ARG_REGNUM |
3160 | || odd_sized_struct | |
3161 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3162 | { |
c906108c SS |
3163 | /* Should shorter than int integer values be |
3164 | promoted to int before being stored? */ | |
c906108c | 3165 | int longword_offset = 0; |
9ace0497 | 3166 | CORE_ADDR addr; |
566f0f7a | 3167 | stack_used_p = 1; |
d7449b42 | 3168 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 3169 | { |
13326b4e | 3170 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3171 | && (typecode == TYPE_CODE_INT |
3172 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3173 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3174 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
3175 | else if ((typecode == TYPE_CODE_STRUCT |
3176 | || typecode == TYPE_CODE_UNION) | |
3177 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
3178 | < mips_stack_argsize (gdbarch))) |
3179 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 3180 | } |
c5aa993b | 3181 | |
9ace0497 AC |
3182 | if (mips_debug) |
3183 | { | |
cb3d25d1 MS |
3184 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
3185 | paddr_nz (stack_offset)); | |
3186 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3187 | paddr_nz (longword_offset)); | |
9ace0497 | 3188 | } |
361d1df0 | 3189 | |
9ace0497 AC |
3190 | addr = sp + stack_offset + longword_offset; |
3191 | ||
3192 | if (mips_debug) | |
3193 | { | |
3194 | int i; | |
6d82d43b | 3195 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 3196 | paddr_nz (addr)); |
9ace0497 AC |
3197 | for (i = 0; i < partial_len; i++) |
3198 | { | |
6d82d43b | 3199 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3200 | val[i] & 0xff); |
9ace0497 AC |
3201 | } |
3202 | } | |
3203 | write_memory (addr, val, partial_len); | |
c906108c SS |
3204 | } |
3205 | ||
f09ded24 AC |
3206 | /* Note!!! This is NOT an else clause. Odd sized |
3207 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3208 | arguments will not. */ |
566f0f7a | 3209 | /* Write this portion of the argument to a general |
6d82d43b | 3210 | purpose register. */ |
f09ded24 AC |
3211 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3212 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 3213 | { |
6d82d43b AC |
3214 | LONGEST regval = |
3215 | extract_unsigned_integer (val, partial_len); | |
c906108c | 3216 | |
9ace0497 | 3217 | if (mips_debug) |
acdb74a0 | 3218 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3219 | argreg, |
6d82d43b | 3220 | phex (regval, |
13326b4e | 3221 | mips_abi_regsize (gdbarch))); |
c906108c SS |
3222 | write_register (argreg, regval); |
3223 | argreg++; | |
c906108c | 3224 | } |
c5aa993b | 3225 | |
c906108c SS |
3226 | len -= partial_len; |
3227 | val += partial_len; | |
3228 | ||
566f0f7a | 3229 | /* Compute the the offset into the stack at which we |
6d82d43b | 3230 | will copy the next parameter. |
566f0f7a | 3231 | |
566f0f7a | 3232 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3233 | only needs to be adjusted when it has been used. */ |
c906108c | 3234 | |
46e0f506 | 3235 | if (stack_used_p) |
480d3dd2 | 3236 | stack_offset += align_up (partial_len, |
13326b4e | 3237 | mips_stack_argsize (gdbarch)); |
c906108c SS |
3238 | } |
3239 | } | |
9ace0497 AC |
3240 | if (mips_debug) |
3241 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3242 | } |
3243 | ||
f10683bb | 3244 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3245 | |
0f71a2f6 JM |
3246 | /* Return adjusted stack pointer. */ |
3247 | return sp; | |
3248 | } | |
3249 | ||
9c8fdbfa | 3250 | /* Determin the return value convention being used. */ |
6d82d43b | 3251 | |
9c8fdbfa AC |
3252 | static enum return_value_convention |
3253 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
3254 | struct type *type, struct regcache *regcache, | |
3255 | void *readbuf, const void *writebuf) | |
6d82d43b | 3256 | { |
9c8fdbfa AC |
3257 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3258 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3259 | if (readbuf) | |
3260 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
3261 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
3262 | } |
3263 | ||
6d82d43b AC |
3264 | |
3265 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3266 | |
f7ab6ec6 | 3267 | static CORE_ADDR |
7d9b040b | 3268 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3269 | struct regcache *regcache, CORE_ADDR bp_addr, |
3270 | int nargs, struct value **args, CORE_ADDR sp, | |
3271 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3272 | { |
3273 | int argreg; | |
3274 | int float_argreg; | |
3275 | int argnum; | |
3276 | int len = 0; | |
3277 | int stack_offset = 0; | |
480d3dd2 | 3278 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3279 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3280 | |
25ab4790 AC |
3281 | /* For shared libraries, "t9" needs to point at the function |
3282 | address. */ | |
4c7d22cb | 3283 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3284 | |
3285 | /* Set the return address register to point to the entry point of | |
3286 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3287 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3288 | |
cb3d25d1 MS |
3289 | /* First ensure that the stack and structure return address (if any) |
3290 | are properly aligned. The stack has to be at least 64-bit | |
3291 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3292 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3293 | aligned, so we round to this widest known alignment. */ | |
3294 | ||
5b03f266 AC |
3295 | sp = align_down (sp, 16); |
3296 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3297 | |
3298 | /* Now make space on the stack for the args. */ | |
3299 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3300 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3301 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3302 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3303 | |
3304 | if (mips_debug) | |
6d82d43b | 3305 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3306 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
3307 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3308 | |
3309 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3310 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3311 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 3312 | |
46e0f506 | 3313 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3314 | if (struct_return) |
3315 | { | |
3316 | if (mips_debug) | |
3317 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3318 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
3319 | argreg, paddr_nz (struct_addr)); |
3320 | write_register (argreg++, struct_addr); | |
3321 | } | |
3322 | ||
3323 | /* Now load as many as possible of the first arguments into | |
3324 | registers, and push the rest onto the stack. Loop thru args | |
3325 | from first to last. */ | |
3326 | for (argnum = 0; argnum < nargs; argnum++) | |
3327 | { | |
3328 | char *val; | |
cb3d25d1 MS |
3329 | struct value *arg = args[argnum]; |
3330 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3331 | int len = TYPE_LENGTH (arg_type); | |
3332 | enum type_code typecode = TYPE_CODE (arg_type); | |
3333 | ||
3334 | if (mips_debug) | |
3335 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3336 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3337 | argnum + 1, len, (int) typecode); |
3338 | ||
3339 | val = (char *) VALUE_CONTENTS (arg); | |
3340 | ||
3341 | if (fp_register_arg_p (typecode, arg_type) | |
3342 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3343 | { | |
3344 | /* This is a floating point value that fits entirely | |
3345 | in a single register. */ | |
3346 | /* On 32 bit ABI's the float_argreg is further adjusted | |
3347 | above to ensure that it is even register aligned. */ | |
3348 | LONGEST regval = extract_unsigned_integer (val, len); | |
3349 | if (mips_debug) | |
3350 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3351 | float_argreg, phex (regval, len)); | |
3352 | write_register (float_argreg++, regval); | |
3353 | ||
3354 | if (mips_debug) | |
3355 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3356 | argreg, phex (regval, len)); | |
3357 | write_register (argreg, regval); | |
3358 | argreg += 1; | |
3359 | } | |
3360 | else | |
3361 | { | |
3362 | /* Copy the argument to general registers or the stack in | |
3363 | register-sized pieces. Large arguments are split between | |
3364 | registers and stack. */ | |
4246e332 | 3365 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3366 | mips_abi_regsize() are treated specially: Irix cc passes |
3367 | them in registers where gcc sometimes puts them on the | |
3368 | stack. For maximum compatibility, we will put them in | |
3369 | both places. */ | |
13326b4e AC |
3370 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3371 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 3372 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3373 | register are only written to memory. */ |
cb3d25d1 MS |
3374 | while (len > 0) |
3375 | { | |
3376 | /* Rememer if the argument was written to the stack. */ | |
3377 | int stack_used_p = 0; | |
13326b4e AC |
3378 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3379 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
3380 | |
3381 | if (mips_debug) | |
3382 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3383 | partial_len); | |
3384 | ||
3385 | /* Write this portion of the argument to the stack. */ | |
3386 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3387 | || odd_sized_struct | |
3388 | || fp_register_arg_p (typecode, arg_type)) | |
3389 | { | |
3390 | /* Should shorter than int integer values be | |
3391 | promoted to int before being stored? */ | |
3392 | int longword_offset = 0; | |
3393 | CORE_ADDR addr; | |
3394 | stack_used_p = 1; | |
3395 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3396 | { | |
13326b4e | 3397 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3398 | && (typecode == TYPE_CODE_INT |
3399 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3400 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3401 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
3402 | } |
3403 | ||
3404 | if (mips_debug) | |
3405 | { | |
3406 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3407 | paddr_nz (stack_offset)); | |
3408 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3409 | paddr_nz (longword_offset)); | |
3410 | } | |
3411 | ||
3412 | addr = sp + stack_offset + longword_offset; | |
3413 | ||
3414 | if (mips_debug) | |
3415 | { | |
3416 | int i; | |
6d82d43b | 3417 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
3418 | paddr_nz (addr)); |
3419 | for (i = 0; i < partial_len; i++) | |
3420 | { | |
6d82d43b | 3421 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3422 | val[i] & 0xff); |
3423 | } | |
3424 | } | |
3425 | write_memory (addr, val, partial_len); | |
3426 | } | |
3427 | ||
3428 | /* Note!!! This is NOT an else clause. Odd sized | |
3429 | structs may go thru BOTH paths. Floating point | |
3430 | arguments will not. */ | |
3431 | /* Write this portion of the argument to a general | |
6d82d43b | 3432 | purpose register. */ |
cb3d25d1 MS |
3433 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3434 | && !fp_register_arg_p (typecode, arg_type)) | |
3435 | { | |
6d82d43b AC |
3436 | LONGEST regval = |
3437 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3438 | |
3439 | /* A non-floating-point argument being passed in a | |
3440 | general register. If a struct or union, and if | |
3441 | the remaining length is smaller than the register | |
3442 | size, we have to adjust the register value on | |
3443 | big endian targets. | |
3444 | ||
3445 | It does not seem to be necessary to do the | |
3446 | same for integral types. | |
3447 | ||
3448 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3449 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3450 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
3451 | part of storing the argument in a register a |
3452 | register (the left shift isn't generated when | |
1b13c4f6 | 3453 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3454 | it is quite possible that this is GCC |
3455 | contradicting the LE/O32 ABI, GDB has not been | |
3456 | adjusted to accommodate this. Either someone | |
3457 | needs to demonstrate that the LE/O32 ABI | |
3458 | specifies such a left shift OR this new ABI gets | |
3459 | identified as such and GDB gets tweaked | |
3460 | accordingly. */ | |
cb3d25d1 MS |
3461 | |
3462 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 3463 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
3464 | && (typecode == TYPE_CODE_STRUCT || |
3465 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3466 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
3467 | TARGET_CHAR_BIT); |
3468 | ||
3469 | if (mips_debug) | |
3470 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3471 | argreg, | |
6d82d43b | 3472 | phex (regval, |
13326b4e | 3473 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
3474 | write_register (argreg, regval); |
3475 | argreg++; | |
3476 | } | |
3477 | ||
3478 | len -= partial_len; | |
3479 | val += partial_len; | |
3480 | ||
3481 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3482 | will copy the next parameter. |
cb3d25d1 MS |
3483 | |
3484 | In N32 (N64?), the stack_offset only needs to be | |
3485 | adjusted when it has been used. */ | |
3486 | ||
3487 | if (stack_used_p) | |
480d3dd2 | 3488 | stack_offset += align_up (partial_len, |
13326b4e | 3489 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
3490 | } |
3491 | } | |
3492 | if (mips_debug) | |
3493 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3494 | } | |
3495 | ||
f10683bb | 3496 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3497 | |
cb3d25d1 MS |
3498 | /* Return adjusted stack pointer. */ |
3499 | return sp; | |
3500 | } | |
3501 | ||
6d82d43b AC |
3502 | static enum return_value_convention |
3503 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3504 | struct type *type, struct regcache *regcache, | |
3505 | void *readbuf, const void *writebuf) | |
ebafbe83 | 3506 | { |
6d82d43b AC |
3507 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3508 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3509 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3510 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 3511 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
3512 | return RETURN_VALUE_STRUCT_CONVENTION; |
3513 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3514 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3515 | { | |
3516 | /* A floating-point value belongs in the least significant part | |
3517 | of FP0. */ | |
3518 | if (mips_debug) | |
3519 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3520 | mips_xfer_register (regcache, | |
3521 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3522 | TYPE_LENGTH (type), | |
3523 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3524 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3525 | } | |
3526 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3527 | && TYPE_NFIELDS (type) <= 2 | |
3528 | && TYPE_NFIELDS (type) >= 1 | |
3529 | && ((TYPE_NFIELDS (type) == 1 | |
3530 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3531 | == TYPE_CODE_FLT)) | |
3532 | || (TYPE_NFIELDS (type) == 2 | |
3533 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3534 | == TYPE_CODE_FLT) | |
3535 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3536 | == TYPE_CODE_FLT))) | |
3537 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3538 | { | |
3539 | /* A struct that contains one or two floats. Each value is part | |
3540 | in the least significant part of their floating point | |
3541 | register.. */ | |
6d82d43b AC |
3542 | int regnum; |
3543 | int field; | |
3544 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3545 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3546 | { | |
3547 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3548 | / TARGET_CHAR_BIT); | |
3549 | if (mips_debug) | |
3550 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3551 | offset); | |
3552 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3553 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3554 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3555 | } | |
3556 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3557 | } | |
3558 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3559 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3560 | { | |
3561 | /* A structure or union. Extract the left justified value, | |
3562 | regardless of the byte order. I.e. DO NOT USE | |
3563 | mips_xfer_lower. */ | |
3564 | int offset; | |
3565 | int regnum; | |
4c7d22cb | 3566 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3567 | offset < TYPE_LENGTH (type); |
3568 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3569 | { | |
3570 | int xfer = register_size (current_gdbarch, regnum); | |
3571 | if (offset + xfer > TYPE_LENGTH (type)) | |
3572 | xfer = TYPE_LENGTH (type) - offset; | |
3573 | if (mips_debug) | |
3574 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3575 | offset, xfer, regnum); | |
3576 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3577 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3578 | } | |
3579 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3580 | } | |
3581 | else | |
3582 | { | |
3583 | /* A scalar extract each part but least-significant-byte | |
3584 | justified. */ | |
3585 | int offset; | |
3586 | int regnum; | |
4c7d22cb | 3587 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3588 | offset < TYPE_LENGTH (type); |
3589 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3590 | { | |
3591 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3592 | if (offset + xfer > TYPE_LENGTH (type)) |
3593 | xfer = TYPE_LENGTH (type) - offset; | |
3594 | if (mips_debug) | |
3595 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3596 | offset, xfer, regnum); | |
3597 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3598 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3599 | } | |
3600 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3601 | } | |
3602 | } | |
3603 | ||
3604 | /* O32 ABI stuff. */ | |
3605 | ||
3606 | static CORE_ADDR | |
7d9b040b | 3607 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3608 | struct regcache *regcache, CORE_ADDR bp_addr, |
3609 | int nargs, struct value **args, CORE_ADDR sp, | |
3610 | int struct_return, CORE_ADDR struct_addr) | |
3611 | { | |
3612 | int argreg; | |
3613 | int float_argreg; | |
3614 | int argnum; | |
3615 | int len = 0; | |
3616 | int stack_offset = 0; | |
3617 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3618 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3619 | |
3620 | /* For shared libraries, "t9" needs to point at the function | |
3621 | address. */ | |
4c7d22cb | 3622 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3623 | |
3624 | /* Set the return address register to point to the entry point of | |
3625 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3626 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3627 | |
3628 | /* First ensure that the stack and structure return address (if any) | |
3629 | are properly aligned. The stack has to be at least 64-bit | |
3630 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3631 | aligned. For n32 and n64, stack frames need to be 128-bit |
3632 | aligned, so we round to this widest known alignment. */ | |
3633 | ||
5b03f266 AC |
3634 | sp = align_down (sp, 16); |
3635 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3636 | |
3637 | /* Now make space on the stack for the args. */ | |
3638 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3639 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3640 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3641 | sp -= align_up (len, 16); |
ebafbe83 MS |
3642 | |
3643 | if (mips_debug) | |
6d82d43b | 3644 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3645 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3646 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3647 | |
3648 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3649 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3650 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3651 | |
bcb0cc15 | 3652 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3653 | if (struct_return) |
3654 | { | |
3655 | if (mips_debug) | |
3656 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3657 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3658 | argreg, paddr_nz (struct_addr)); |
3659 | write_register (argreg++, struct_addr); | |
13326b4e | 3660 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
3661 | } |
3662 | ||
3663 | /* Now load as many as possible of the first arguments into | |
3664 | registers, and push the rest onto the stack. Loop thru args | |
3665 | from first to last. */ | |
3666 | for (argnum = 0; argnum < nargs; argnum++) | |
3667 | { | |
3668 | char *val; | |
ebafbe83 MS |
3669 | struct value *arg = args[argnum]; |
3670 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3671 | int len = TYPE_LENGTH (arg_type); | |
3672 | enum type_code typecode = TYPE_CODE (arg_type); | |
3673 | ||
3674 | if (mips_debug) | |
3675 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3676 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3677 | argnum + 1, len, (int) typecode); |
3678 | ||
3679 | val = (char *) VALUE_CONTENTS (arg); | |
3680 | ||
3681 | /* 32-bit ABIs always start floating point arguments in an | |
3682 | even-numbered floating point register. Round the FP register | |
3683 | up before the check to see if there are any FP registers | |
3684 | left. O32/O64 targets also pass the FP in the integer | |
3685 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3686 | if (mips_abi_regsize (gdbarch) < 8 |
3687 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
3688 | { |
3689 | if ((float_argreg & 1)) | |
3690 | float_argreg++; | |
3691 | } | |
3692 | ||
3693 | /* Floating point arguments passed in registers have to be | |
3694 | treated specially. On 32-bit architectures, doubles | |
3695 | are passed in register pairs; the even register gets | |
3696 | the low word, and the odd register gets the high word. | |
3697 | On O32/O64, the first two floating point arguments are | |
3698 | also copied to general registers, because MIPS16 functions | |
3699 | don't use float registers for arguments. This duplication of | |
3700 | arguments in general registers can't hurt non-MIPS16 functions | |
3701 | because those registers are normally skipped. */ | |
3702 | ||
3703 | if (fp_register_arg_p (typecode, arg_type) | |
3704 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3705 | { | |
ceae6e75 | 3706 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
3707 | { |
3708 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3709 | unsigned long regval; | |
3710 | ||
3711 | /* Write the low word of the double to the even register(s). */ | |
3712 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3713 | if (mips_debug) | |
3714 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3715 | float_argreg, phex (regval, 4)); | |
3716 | write_register (float_argreg++, regval); | |
3717 | if (mips_debug) | |
3718 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3719 | argreg, phex (regval, 4)); | |
3720 | write_register (argreg++, regval); | |
3721 | ||
3722 | /* Write the high word of the double to the odd register(s). */ | |
3723 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3724 | if (mips_debug) | |
3725 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3726 | float_argreg, phex (regval, 4)); | |
3727 | write_register (float_argreg++, regval); | |
3728 | ||
3729 | if (mips_debug) | |
3730 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3731 | argreg, phex (regval, 4)); | |
3732 | write_register (argreg++, regval); | |
3733 | } | |
3734 | else | |
3735 | { | |
3736 | /* This is a floating point value that fits entirely | |
3737 | in a single register. */ | |
3738 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3739 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3740 | LONGEST regval = extract_unsigned_integer (val, len); |
3741 | if (mips_debug) | |
3742 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3743 | float_argreg, phex (regval, len)); | |
3744 | write_register (float_argreg++, regval); | |
3745 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3746 | registers for each argument. The below is (my |
3747 | guess) to ensure that the corresponding integer | |
3748 | register has reserved the same space. */ | |
46cac009 AC |
3749 | if (mips_debug) |
3750 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3751 | argreg, phex (regval, len)); | |
3752 | write_register (argreg, regval); | |
ceae6e75 | 3753 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
3754 | } |
3755 | /* Reserve space for the FP register. */ | |
13326b4e | 3756 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
3757 | } |
3758 | else | |
3759 | { | |
3760 | /* Copy the argument to general registers or the stack in | |
3761 | register-sized pieces. Large arguments are split between | |
3762 | registers and stack. */ | |
4246e332 | 3763 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3764 | mips_abi_regsize() are treated specially: Irix cc passes |
3765 | them in registers where gcc sometimes puts them on the | |
3766 | stack. For maximum compatibility, we will put them in | |
3767 | both places. */ | |
13326b4e AC |
3768 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3769 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
3770 | /* Structures should be aligned to eight bytes (even arg registers) |
3771 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 3772 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
3773 | && mips_type_needs_double_align (arg_type)) |
3774 | { | |
3775 | if ((argreg & 1)) | |
6d82d43b | 3776 | argreg++; |
46cac009 AC |
3777 | } |
3778 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3779 | register are only written to memory. */ |
46cac009 AC |
3780 | while (len > 0) |
3781 | { | |
3782 | /* Remember if the argument was written to the stack. */ | |
3783 | int stack_used_p = 0; | |
13326b4e AC |
3784 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3785 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
3786 | |
3787 | if (mips_debug) | |
3788 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3789 | partial_len); | |
3790 | ||
3791 | /* Write this portion of the argument to the stack. */ | |
3792 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3793 | || odd_sized_struct | |
3794 | || fp_register_arg_p (typecode, arg_type)) | |
3795 | { | |
3796 | /* Should shorter than int integer values be | |
3797 | promoted to int before being stored? */ | |
3798 | int longword_offset = 0; | |
3799 | CORE_ADDR addr; | |
3800 | stack_used_p = 1; | |
3801 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3802 | { | |
13326b4e | 3803 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3804 | && (typecode == TYPE_CODE_INT |
3805 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3806 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3807 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
3808 | } |
3809 | ||
3810 | if (mips_debug) | |
3811 | { | |
3812 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3813 | paddr_nz (stack_offset)); | |
3814 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3815 | paddr_nz (longword_offset)); | |
3816 | } | |
3817 | ||
3818 | addr = sp + stack_offset + longword_offset; | |
3819 | ||
3820 | if (mips_debug) | |
3821 | { | |
3822 | int i; | |
6d82d43b | 3823 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3824 | paddr_nz (addr)); |
3825 | for (i = 0; i < partial_len; i++) | |
3826 | { | |
6d82d43b | 3827 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3828 | val[i] & 0xff); |
3829 | } | |
3830 | } | |
3831 | write_memory (addr, val, partial_len); | |
3832 | } | |
3833 | ||
3834 | /* Note!!! This is NOT an else clause. Odd sized | |
3835 | structs may go thru BOTH paths. Floating point | |
3836 | arguments will not. */ | |
3837 | /* Write this portion of the argument to a general | |
6d82d43b | 3838 | purpose register. */ |
46cac009 AC |
3839 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3840 | && !fp_register_arg_p (typecode, arg_type)) | |
3841 | { | |
3842 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3843 | /* Value may need to be sign extended, because |
1b13c4f6 | 3844 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3845 | |
3846 | /* A non-floating-point argument being passed in a | |
3847 | general register. If a struct or union, and if | |
3848 | the remaining length is smaller than the register | |
3849 | size, we have to adjust the register value on | |
3850 | big endian targets. | |
3851 | ||
3852 | It does not seem to be necessary to do the | |
3853 | same for integral types. | |
3854 | ||
3855 | Also don't do this adjustment on O64 binaries. | |
3856 | ||
3857 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3858 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3859 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
3860 | part of storing the argument in a register a |
3861 | register (the left shift isn't generated when | |
1b13c4f6 | 3862 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3863 | it is quite possible that this is GCC |
3864 | contradicting the LE/O32 ABI, GDB has not been | |
3865 | adjusted to accommodate this. Either someone | |
3866 | needs to demonstrate that the LE/O32 ABI | |
3867 | specifies such a left shift OR this new ABI gets | |
3868 | identified as such and GDB gets tweaked | |
3869 | accordingly. */ | |
3870 | ||
13326b4e | 3871 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 3872 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 3873 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
3874 | && (typecode == TYPE_CODE_STRUCT || |
3875 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3876 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
3877 | TARGET_CHAR_BIT); |
3878 | ||
3879 | if (mips_debug) | |
3880 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3881 | argreg, | |
6d82d43b | 3882 | phex (regval, |
13326b4e | 3883 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
3884 | write_register (argreg, regval); |
3885 | argreg++; | |
3886 | ||
3887 | /* Prevent subsequent floating point arguments from | |
3888 | being passed in floating point registers. */ | |
3889 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3890 | } | |
3891 | ||
3892 | len -= partial_len; | |
3893 | val += partial_len; | |
3894 | ||
3895 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3896 | will copy the next parameter. |
46cac009 | 3897 | |
6d82d43b AC |
3898 | In older ABIs, the caller reserved space for |
3899 | registers that contained arguments. This was loosely | |
3900 | refered to as their "home". Consequently, space is | |
3901 | always allocated. */ | |
46cac009 | 3902 | |
480d3dd2 | 3903 | stack_offset += align_up (partial_len, |
13326b4e | 3904 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
3905 | } |
3906 | } | |
3907 | if (mips_debug) | |
3908 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3909 | } | |
3910 | ||
f10683bb | 3911 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3912 | |
46cac009 AC |
3913 | /* Return adjusted stack pointer. */ |
3914 | return sp; | |
3915 | } | |
3916 | ||
6d82d43b AC |
3917 | static enum return_value_convention |
3918 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3919 | struct regcache *regcache, | |
3920 | void *readbuf, const void *writebuf) | |
3921 | { | |
3922 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3923 | ||
3924 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3925 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3926 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3927 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3928 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3929 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3930 | { | |
3931 | /* A single-precision floating-point value. It fits in the | |
3932 | least significant part of FP0. */ | |
3933 | if (mips_debug) | |
3934 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3935 | mips_xfer_register (regcache, | |
3936 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3937 | TYPE_LENGTH (type), | |
3938 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3939 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3940 | } | |
3941 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3942 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3943 | { | |
3944 | /* A double-precision floating-point value. The most | |
3945 | significant part goes in FP1, and the least significant in | |
3946 | FP0. */ | |
3947 | if (mips_debug) | |
3948 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
3949 | switch (TARGET_BYTE_ORDER) | |
3950 | { | |
3951 | case BFD_ENDIAN_LITTLE: | |
3952 | mips_xfer_register (regcache, | |
3953 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3954 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3955 | mips_xfer_register (regcache, | |
3956 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3957 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3958 | break; | |
3959 | case BFD_ENDIAN_BIG: | |
3960 | mips_xfer_register (regcache, | |
3961 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3962 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3963 | mips_xfer_register (regcache, | |
3964 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3965 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3966 | break; | |
3967 | default: | |
3968 | internal_error (__FILE__, __LINE__, "bad switch"); | |
3969 | } | |
3970 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3971 | } | |
3972 | #if 0 | |
3973 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3974 | && TYPE_NFIELDS (type) <= 2 | |
3975 | && TYPE_NFIELDS (type) >= 1 | |
3976 | && ((TYPE_NFIELDS (type) == 1 | |
3977 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3978 | == TYPE_CODE_FLT)) | |
3979 | || (TYPE_NFIELDS (type) == 2 | |
3980 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3981 | == TYPE_CODE_FLT) | |
3982 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3983 | == TYPE_CODE_FLT))) | |
3984 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3985 | { | |
3986 | /* A struct that contains one or two floats. Each value is part | |
3987 | in the least significant part of their floating point | |
3988 | register.. */ | |
3989 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
3990 | int regnum; | |
3991 | int field; | |
3992 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3993 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3994 | { | |
3995 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3996 | / TARGET_CHAR_BIT); | |
3997 | if (mips_debug) | |
3998 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3999 | offset); | |
4000 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
4001 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
4002 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4003 | } | |
4004 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4005 | } | |
4006 | #endif | |
4007 | #if 0 | |
4008 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4009 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4010 | { | |
4011 | /* A structure or union. Extract the left justified value, | |
4012 | regardless of the byte order. I.e. DO NOT USE | |
4013 | mips_xfer_lower. */ | |
4014 | int offset; | |
4015 | int regnum; | |
4c7d22cb | 4016 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
4017 | offset < TYPE_LENGTH (type); |
4018 | offset += register_size (current_gdbarch, regnum), regnum++) | |
4019 | { | |
4020 | int xfer = register_size (current_gdbarch, regnum); | |
4021 | if (offset + xfer > TYPE_LENGTH (type)) | |
4022 | xfer = TYPE_LENGTH (type) - offset; | |
4023 | if (mips_debug) | |
4024 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4025 | offset, xfer, regnum); | |
4026 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4027 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
4028 | } | |
4029 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4030 | } | |
4031 | #endif | |
4032 | else | |
4033 | { | |
4034 | /* A scalar extract each part but least-significant-byte | |
4035 | justified. o32 thinks registers are 4 byte, regardless of | |
4036 | the ISA. mips_stack_argsize controls this. */ | |
4037 | int offset; | |
4038 | int regnum; | |
4c7d22cb | 4039 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4040 | offset < TYPE_LENGTH (type); |
13326b4e | 4041 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 4042 | { |
13326b4e | 4043 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
4044 | if (offset + xfer > TYPE_LENGTH (type)) |
4045 | xfer = TYPE_LENGTH (type) - offset; | |
4046 | if (mips_debug) | |
4047 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4048 | offset, xfer, regnum); | |
4049 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
4050 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
4051 | } | |
4052 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4053 | } | |
4054 | } | |
4055 | ||
4056 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4057 | ABI. */ | |
46cac009 AC |
4058 | |
4059 | static CORE_ADDR | |
7d9b040b | 4060 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4061 | struct regcache *regcache, CORE_ADDR bp_addr, |
4062 | int nargs, | |
4063 | struct value **args, CORE_ADDR sp, | |
4064 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4065 | { |
4066 | int argreg; | |
4067 | int float_argreg; | |
4068 | int argnum; | |
4069 | int len = 0; | |
4070 | int stack_offset = 0; | |
480d3dd2 | 4071 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 4072 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4073 | |
25ab4790 AC |
4074 | /* For shared libraries, "t9" needs to point at the function |
4075 | address. */ | |
4c7d22cb | 4076 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4077 | |
4078 | /* Set the return address register to point to the entry point of | |
4079 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4080 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4081 | |
46cac009 AC |
4082 | /* First ensure that the stack and structure return address (if any) |
4083 | are properly aligned. The stack has to be at least 64-bit | |
4084 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4085 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4086 | aligned, so we round to this widest known alignment. */ | |
4087 | ||
5b03f266 AC |
4088 | sp = align_down (sp, 16); |
4089 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4090 | |
4091 | /* Now make space on the stack for the args. */ | |
4092 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 4093 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 4094 | mips_stack_argsize (gdbarch)); |
5b03f266 | 4095 | sp -= align_up (len, 16); |
46cac009 AC |
4096 | |
4097 | if (mips_debug) | |
6d82d43b | 4098 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
4099 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
4100 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
4101 | |
4102 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4103 | argreg = MIPS_A0_REGNUM; |
56cea623 | 4104 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
4105 | |
4106 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4107 | if (struct_return) | |
4108 | { | |
4109 | if (mips_debug) | |
4110 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4111 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
4112 | argreg, paddr_nz (struct_addr)); |
4113 | write_register (argreg++, struct_addr); | |
13326b4e | 4114 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
4115 | } |
4116 | ||
4117 | /* Now load as many as possible of the first arguments into | |
4118 | registers, and push the rest onto the stack. Loop thru args | |
4119 | from first to last. */ | |
4120 | for (argnum = 0; argnum < nargs; argnum++) | |
4121 | { | |
4122 | char *val; | |
46cac009 AC |
4123 | struct value *arg = args[argnum]; |
4124 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
4125 | int len = TYPE_LENGTH (arg_type); | |
4126 | enum type_code typecode = TYPE_CODE (arg_type); | |
4127 | ||
4128 | if (mips_debug) | |
4129 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4130 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4131 | argnum + 1, len, (int) typecode); |
4132 | ||
4133 | val = (char *) VALUE_CONTENTS (arg); | |
4134 | ||
4135 | /* 32-bit ABIs always start floating point arguments in an | |
4136 | even-numbered floating point register. Round the FP register | |
4137 | up before the check to see if there are any FP registers | |
4138 | left. O32/O64 targets also pass the FP in the integer | |
4139 | registers so also round up normal registers. */ | |
ceae6e75 AC |
4140 | if (mips_abi_regsize (gdbarch) < 8 |
4141 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
4142 | { |
4143 | if ((float_argreg & 1)) | |
4144 | float_argreg++; | |
4145 | } | |
4146 | ||
4147 | /* Floating point arguments passed in registers have to be | |
4148 | treated specially. On 32-bit architectures, doubles | |
4149 | are passed in register pairs; the even register gets | |
4150 | the low word, and the odd register gets the high word. | |
4151 | On O32/O64, the first two floating point arguments are | |
4152 | also copied to general registers, because MIPS16 functions | |
4153 | don't use float registers for arguments. This duplication of | |
4154 | arguments in general registers can't hurt non-MIPS16 functions | |
4155 | because those registers are normally skipped. */ | |
4156 | ||
4157 | if (fp_register_arg_p (typecode, arg_type) | |
4158 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
4159 | { | |
ceae6e75 | 4160 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
4161 | { |
4162 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
4163 | unsigned long regval; | |
4164 | ||
4165 | /* Write the low word of the double to the even register(s). */ | |
4166 | regval = extract_unsigned_integer (val + low_offset, 4); | |
4167 | if (mips_debug) | |
4168 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4169 | float_argreg, phex (regval, 4)); | |
4170 | write_register (float_argreg++, regval); | |
4171 | if (mips_debug) | |
4172 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4173 | argreg, phex (regval, 4)); | |
4174 | write_register (argreg++, regval); | |
4175 | ||
4176 | /* Write the high word of the double to the odd register(s). */ | |
4177 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
4178 | if (mips_debug) | |
4179 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4180 | float_argreg, phex (regval, 4)); | |
4181 | write_register (float_argreg++, regval); | |
4182 | ||
4183 | if (mips_debug) | |
4184 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4185 | argreg, phex (regval, 4)); | |
4186 | write_register (argreg++, regval); | |
4187 | } | |
4188 | else | |
4189 | { | |
4190 | /* This is a floating point value that fits entirely | |
4191 | in a single register. */ | |
4192 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 4193 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
4194 | LONGEST regval = extract_unsigned_integer (val, len); |
4195 | if (mips_debug) | |
4196 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4197 | float_argreg, phex (regval, len)); | |
4198 | write_register (float_argreg++, regval); | |
4199 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
4200 | registers for each argument. The below is (my |
4201 | guess) to ensure that the corresponding integer | |
4202 | register has reserved the same space. */ | |
ebafbe83 MS |
4203 | if (mips_debug) |
4204 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4205 | argreg, phex (regval, len)); | |
4206 | write_register (argreg, regval); | |
ceae6e75 | 4207 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
4208 | } |
4209 | /* Reserve space for the FP register. */ | |
13326b4e | 4210 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4211 | } |
4212 | else | |
4213 | { | |
4214 | /* Copy the argument to general registers or the stack in | |
4215 | register-sized pieces. Large arguments are split between | |
4216 | registers and stack. */ | |
4246e332 | 4217 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
4218 | mips_abi_regsize() are treated specially: Irix cc passes |
4219 | them in registers where gcc sometimes puts them on the | |
4220 | stack. For maximum compatibility, we will put them in | |
4221 | both places. */ | |
13326b4e AC |
4222 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
4223 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
4224 | /* Structures should be aligned to eight bytes (even arg registers) |
4225 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 4226 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
4227 | && mips_type_needs_double_align (arg_type)) |
4228 | { | |
4229 | if ((argreg & 1)) | |
6d82d43b | 4230 | argreg++; |
ebafbe83 MS |
4231 | } |
4232 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 4233 | register are only written to memory. */ |
ebafbe83 MS |
4234 | while (len > 0) |
4235 | { | |
4236 | /* Remember if the argument was written to the stack. */ | |
4237 | int stack_used_p = 0; | |
13326b4e AC |
4238 | int partial_len = (len < mips_abi_regsize (gdbarch) |
4239 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
4240 | |
4241 | if (mips_debug) | |
4242 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4243 | partial_len); | |
4244 | ||
4245 | /* Write this portion of the argument to the stack. */ | |
4246 | if (argreg > MIPS_LAST_ARG_REGNUM | |
4247 | || odd_sized_struct | |
4248 | || fp_register_arg_p (typecode, arg_type)) | |
4249 | { | |
4250 | /* Should shorter than int integer values be | |
4251 | promoted to int before being stored? */ | |
4252 | int longword_offset = 0; | |
4253 | CORE_ADDR addr; | |
4254 | stack_used_p = 1; | |
4255 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4256 | { | |
13326b4e | 4257 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
4258 | && (typecode == TYPE_CODE_INT |
4259 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4260 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 4261 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
4262 | } |
4263 | ||
4264 | if (mips_debug) | |
4265 | { | |
4266 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
4267 | paddr_nz (stack_offset)); | |
4268 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
4269 | paddr_nz (longword_offset)); | |
4270 | } | |
4271 | ||
4272 | addr = sp + stack_offset + longword_offset; | |
4273 | ||
4274 | if (mips_debug) | |
4275 | { | |
4276 | int i; | |
6d82d43b | 4277 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
4278 | paddr_nz (addr)); |
4279 | for (i = 0; i < partial_len; i++) | |
4280 | { | |
6d82d43b | 4281 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4282 | val[i] & 0xff); |
4283 | } | |
4284 | } | |
4285 | write_memory (addr, val, partial_len); | |
4286 | } | |
4287 | ||
4288 | /* Note!!! This is NOT an else clause. Odd sized | |
4289 | structs may go thru BOTH paths. Floating point | |
4290 | arguments will not. */ | |
4291 | /* Write this portion of the argument to a general | |
6d82d43b | 4292 | purpose register. */ |
ebafbe83 MS |
4293 | if (argreg <= MIPS_LAST_ARG_REGNUM |
4294 | && !fp_register_arg_p (typecode, arg_type)) | |
4295 | { | |
4296 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 4297 | /* Value may need to be sign extended, because |
1b13c4f6 | 4298 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4299 | |
4300 | /* A non-floating-point argument being passed in a | |
4301 | general register. If a struct or union, and if | |
4302 | the remaining length is smaller than the register | |
4303 | size, we have to adjust the register value on | |
4304 | big endian targets. | |
4305 | ||
4306 | It does not seem to be necessary to do the | |
4307 | same for integral types. | |
4308 | ||
4309 | Also don't do this adjustment on O64 binaries. | |
4310 | ||
4311 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4312 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 4313 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
4314 | part of storing the argument in a register a |
4315 | register (the left shift isn't generated when | |
1b13c4f6 | 4316 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4317 | it is quite possible that this is GCC |
4318 | contradicting the LE/O32 ABI, GDB has not been | |
4319 | adjusted to accommodate this. Either someone | |
4320 | needs to demonstrate that the LE/O32 ABI | |
4321 | specifies such a left shift OR this new ABI gets | |
4322 | identified as such and GDB gets tweaked | |
4323 | accordingly. */ | |
4324 | ||
13326b4e | 4325 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 4326 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 4327 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
4328 | && (typecode == TYPE_CODE_STRUCT || |
4329 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 4330 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
4331 | TARGET_CHAR_BIT); |
4332 | ||
4333 | if (mips_debug) | |
4334 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4335 | argreg, | |
6d82d43b | 4336 | phex (regval, |
13326b4e | 4337 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
4338 | write_register (argreg, regval); |
4339 | argreg++; | |
4340 | ||
4341 | /* Prevent subsequent floating point arguments from | |
4342 | being passed in floating point registers. */ | |
4343 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
4344 | } | |
4345 | ||
4346 | len -= partial_len; | |
4347 | val += partial_len; | |
4348 | ||
4349 | /* Compute the the offset into the stack at which we | |
6d82d43b | 4350 | will copy the next parameter. |
ebafbe83 | 4351 | |
6d82d43b AC |
4352 | In older ABIs, the caller reserved space for |
4353 | registers that contained arguments. This was loosely | |
4354 | refered to as their "home". Consequently, space is | |
4355 | always allocated. */ | |
ebafbe83 | 4356 | |
480d3dd2 | 4357 | stack_offset += align_up (partial_len, |
13326b4e | 4358 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
4359 | } |
4360 | } | |
4361 | if (mips_debug) | |
4362 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4363 | } | |
4364 | ||
f10683bb | 4365 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4366 | |
ebafbe83 MS |
4367 | /* Return adjusted stack pointer. */ |
4368 | return sp; | |
4369 | } | |
4370 | ||
9c8fdbfa AC |
4371 | static enum return_value_convention |
4372 | mips_o64_return_value (struct gdbarch *gdbarch, | |
4373 | struct type *type, struct regcache *regcache, | |
4374 | void *readbuf, const void *writebuf) | |
6d82d43b | 4375 | { |
9c8fdbfa | 4376 | return RETURN_VALUE_STRUCT_CONVENTION; |
6d82d43b AC |
4377 | } |
4378 | ||
dd824b04 DJ |
4379 | /* Floating point register management. |
4380 | ||
4381 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4382 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4383 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4384 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4385 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4386 | double precision floats into two 32-bit chunks and store them in | |
4387 | consecutive fp regs. To display 64-bit floats stored in this | |
4388 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4389 | Throw in user-configurable endianness and you have a real mess. | |
4390 | ||
4391 | The way this works is: | |
4392 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4393 | double-precision value will be split across two logical registers. | |
4394 | The lower-numbered logical register will hold the low-order bits, | |
4395 | regardless of the processor's endianness. | |
4396 | - If we are on a 64-bit processor, and we are looking for a | |
4397 | single-precision value, it will be in the low ordered bits | |
4398 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4399 | save slot in memory. | |
4400 | - If we are in 64-bit mode, everything is straightforward. | |
4401 | ||
4402 | Note that this code only deals with "live" registers at the top of the | |
4403 | stack. We will attempt to deal with saved registers later, when | |
4404 | the raw/cooked register interface is in place. (We need a general | |
4405 | interface that can deal with dynamic saved register sizes -- fp | |
4406 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4407 | and below). */ | |
4408 | ||
67b2c998 DJ |
4409 | static struct type * |
4410 | mips_float_register_type (void) | |
4411 | { | |
361d1df0 | 4412 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4413 | return builtin_type_ieee_single_big; |
4414 | else | |
4415 | return builtin_type_ieee_single_little; | |
4416 | } | |
4417 | ||
4418 | static struct type * | |
4419 | mips_double_register_type (void) | |
4420 | { | |
361d1df0 | 4421 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
4422 | return builtin_type_ieee_double_big; |
4423 | else | |
4424 | return builtin_type_ieee_double_little; | |
4425 | } | |
4426 | ||
dd824b04 DJ |
4427 | /* Copy a 32-bit single-precision value from the current frame |
4428 | into rare_buffer. */ | |
4429 | ||
4430 | static void | |
e11c53d2 AC |
4431 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
4432 | char *rare_buffer) | |
dd824b04 | 4433 | { |
719ec221 | 4434 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4435 | char *raw_buffer = alloca (raw_size); |
4436 | ||
e11c53d2 | 4437 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
4438 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4439 | if (raw_size == 8) | |
4440 | { | |
4441 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4442 | 32 bits. */ |
dd824b04 DJ |
4443 | int offset; |
4444 | ||
4445 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
4446 | offset = 4; | |
4447 | else | |
4448 | offset = 0; | |
4449 | ||
4450 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4451 | } | |
4452 | else | |
4453 | { | |
4454 | memcpy (rare_buffer, raw_buffer, 4); | |
4455 | } | |
4456 | } | |
4457 | ||
4458 | /* Copy a 64-bit double-precision value from the current frame into | |
4459 | rare_buffer. This may include getting half of it from the next | |
4460 | register. */ | |
4461 | ||
4462 | static void | |
e11c53d2 AC |
4463 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
4464 | char *rare_buffer) | |
dd824b04 | 4465 | { |
719ec221 | 4466 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
4467 | |
4468 | if (raw_size == 8 && !mips2_fp_compat ()) | |
4469 | { | |
4470 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4471 | all 64 bits. */ |
e11c53d2 | 4472 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
4473 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
4474 | } | |
4475 | else | |
4476 | { | |
56cea623 | 4477 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
4478 | internal_error (__FILE__, __LINE__, |
4479 | "mips_read_fp_register_double: bad access to " | |
4480 | "odd-numbered FP register"); | |
4481 | ||
4482 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4483 | each register. */ |
dd824b04 DJ |
4484 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
4485 | { | |
e11c53d2 AC |
4486 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4487 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4488 | } |
361d1df0 | 4489 | else |
dd824b04 | 4490 | { |
e11c53d2 AC |
4491 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4492 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4493 | } |
4494 | } | |
4495 | } | |
4496 | ||
c906108c | 4497 | static void |
e11c53d2 AC |
4498 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4499 | int regnum) | |
c5aa993b | 4500 | { /* do values for FP (float) regs */ |
dd824b04 | 4501 | char *raw_buffer; |
3903d437 AC |
4502 | double doub, flt1; /* doubles extracted from raw hex data */ |
4503 | int inv1, inv2; | |
c5aa993b | 4504 | |
6d82d43b AC |
4505 | raw_buffer = |
4506 | (char *) alloca (2 * | |
4507 | register_size (current_gdbarch, | |
4508 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4509 | |
e11c53d2 AC |
4510 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
4511 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
4512 | ""); | |
f0ef6b29 | 4513 | |
719ec221 | 4514 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 4515 | { |
f0ef6b29 KB |
4516 | /* 4-byte registers: Print hex and floating. Also print even |
4517 | numbered registers as doubles. */ | |
e11c53d2 | 4518 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4519 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4520 | |
6d82d43b AC |
4521 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4522 | file); | |
dd824b04 | 4523 | |
e11c53d2 | 4524 | fprintf_filtered (file, " flt: "); |
1adad886 | 4525 | if (inv1) |
e11c53d2 | 4526 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4527 | else |
e11c53d2 | 4528 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4529 | |
f0ef6b29 KB |
4530 | if (regnum % 2 == 0) |
4531 | { | |
e11c53d2 | 4532 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4533 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4534 | &inv2); |
1adad886 | 4535 | |
e11c53d2 | 4536 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4537 | if (inv2) |
e11c53d2 | 4538 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4539 | else |
e11c53d2 | 4540 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4541 | } |
c906108c SS |
4542 | } |
4543 | else | |
dd824b04 | 4544 | { |
f0ef6b29 | 4545 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4546 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4547 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4548 | |
e11c53d2 | 4549 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4550 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4551 | ||
361d1df0 | 4552 | |
6d82d43b AC |
4553 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4554 | file); | |
f0ef6b29 | 4555 | |
e11c53d2 | 4556 | fprintf_filtered (file, " flt: "); |
1adad886 | 4557 | if (inv1) |
e11c53d2 | 4558 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4559 | else |
e11c53d2 | 4560 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4561 | |
e11c53d2 | 4562 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4563 | if (inv2) |
e11c53d2 | 4564 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4565 | else |
e11c53d2 | 4566 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4567 | } |
4568 | } | |
4569 | ||
4570 | static void | |
e11c53d2 AC |
4571 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
4572 | int regnum, int all) | |
f0ef6b29 | 4573 | { |
a4b8ebc8 | 4574 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4575 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4576 | int offset; |
1adad886 | 4577 | |
a4b8ebc8 | 4578 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4579 | { |
e11c53d2 | 4580 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4581 | return; |
4582 | } | |
4583 | ||
4584 | /* Get the data in raw format. */ | |
e11c53d2 | 4585 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4586 | { |
e11c53d2 | 4587 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4588 | return; |
c906108c | 4589 | } |
f0ef6b29 | 4590 | |
e11c53d2 | 4591 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4592 | |
4593 | /* The problem with printing numeric register names (r26, etc.) is that | |
4594 | the user can't use them on input. Probably the best solution is to | |
4595 | fix it so that either the numeric or the funky (a2, etc.) names | |
4596 | are accepted on input. */ | |
4597 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4598 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4599 | else |
e11c53d2 | 4600 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4601 | |
4602 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
4603 | offset = |
4604 | register_size (current_gdbarch, | |
4605 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4606 | else |
4607 | offset = 0; | |
4608 | ||
6d82d43b AC |
4609 | print_scalar_formatted (raw_buffer + offset, |
4610 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
4611 | file); | |
c906108c SS |
4612 | } |
4613 | ||
f0ef6b29 KB |
4614 | /* Replacement for generic do_registers_info. |
4615 | Print regs in pretty columns. */ | |
4616 | ||
4617 | static int | |
e11c53d2 AC |
4618 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4619 | int regnum) | |
f0ef6b29 | 4620 | { |
e11c53d2 AC |
4621 | fprintf_filtered (file, " "); |
4622 | mips_print_fp_register (file, frame, regnum); | |
4623 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4624 | return regnum + 1; |
4625 | } | |
4626 | ||
4627 | ||
c906108c SS |
4628 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4629 | ||
4630 | static int | |
e11c53d2 | 4631 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4632 | int start_regnum) |
c906108c | 4633 | { |
a4b8ebc8 | 4634 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4635 | /* do values for GP (int) regs */ |
d9d9c31f | 4636 | char raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4637 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4638 | int col, byte; |
a4b8ebc8 | 4639 | int regnum; |
c906108c SS |
4640 | |
4641 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4642 | fprintf_filtered (file, " "); |
a4b8ebc8 | 4643 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4644 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4645 | { |
4646 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4647 | continue; /* unused register */ |
6d82d43b AC |
4648 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4649 | TYPE_CODE_FLT) | |
c5aa993b | 4650 | break; /* end the row: reached FP register */ |
6d82d43b | 4651 | fprintf_filtered (file, |
d5ac5a39 | 4652 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4653 | REGISTER_NAME (regnum)); |
c906108c SS |
4654 | col++; |
4655 | } | |
a4b8ebc8 | 4656 | /* print the R0 to R31 names */ |
20e6603c AC |
4657 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4658 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4659 | else | |
4660 | fprintf_filtered (file, "\n "); | |
c906108c | 4661 | |
c906108c | 4662 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4663 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4664 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4665 | { |
4666 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4667 | continue; /* unused register */ |
6d82d43b AC |
4668 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4669 | TYPE_CODE_FLT) | |
c5aa993b | 4670 | break; /* end row: reached FP register */ |
c906108c | 4671 | /* OK: get the data in raw format. */ |
e11c53d2 | 4672 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4673 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4674 | /* pad small registers */ | |
4246e332 | 4675 | for (byte = 0; |
d5ac5a39 | 4676 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4677 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4678 | printf_filtered (" "); |
4679 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4680 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4681 | for (byte = |
4682 | register_size (current_gdbarch, | |
4683 | regnum) - register_size (current_gdbarch, regnum); | |
4684 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 4685 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4686 | else |
c73e8f27 | 4687 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4688 | byte >= 0; byte--) |
e11c53d2 AC |
4689 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4690 | fprintf_filtered (file, " "); | |
c906108c SS |
4691 | col++; |
4692 | } | |
c5aa993b | 4693 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4694 | fprintf_filtered (file, "\n"); |
c906108c SS |
4695 | |
4696 | return regnum; | |
4697 | } | |
4698 | ||
4699 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4700 | ||
bf1f5b4c | 4701 | static void |
e11c53d2 AC |
4702 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4703 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4704 | { |
c5aa993b | 4705 | if (regnum != -1) /* do one specified register */ |
c906108c | 4706 | { |
a4b8ebc8 | 4707 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4708 | if (*(REGISTER_NAME (regnum)) == '\0') |
4709 | error ("Not a valid register for the current processor type"); | |
4710 | ||
e11c53d2 AC |
4711 | mips_print_register (file, frame, regnum, 0); |
4712 | fprintf_filtered (file, "\n"); | |
c906108c | 4713 | } |
c5aa993b JM |
4714 | else |
4715 | /* do all (or most) registers */ | |
c906108c | 4716 | { |
a4b8ebc8 AC |
4717 | regnum = NUM_REGS; |
4718 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4719 | { |
6d82d43b AC |
4720 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4721 | TYPE_CODE_FLT) | |
e11c53d2 AC |
4722 | { |
4723 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4724 | regnum = print_fp_register_row (file, frame, regnum); | |
4725 | else | |
4726 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4727 | } | |
c906108c | 4728 | else |
e11c53d2 | 4729 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4730 | } |
4731 | } | |
4732 | } | |
4733 | ||
c906108c SS |
4734 | /* Is this a branch with a delay slot? */ |
4735 | ||
c906108c | 4736 | static int |
acdb74a0 | 4737 | is_delayed (unsigned long insn) |
c906108c SS |
4738 | { |
4739 | int i; | |
4740 | for (i = 0; i < NUMOPCODES; ++i) | |
4741 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4742 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4743 | break; | |
4744 | return (i < NUMOPCODES | |
4745 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4746 | | INSN_COND_BRANCH_DELAY | |
4747 | | INSN_COND_BRANCH_LIKELY))); | |
4748 | } | |
4749 | ||
4750 | int | |
acdb74a0 | 4751 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c | 4752 | { |
4c7d22cb | 4753 | char buf[MIPS32_INSN_SIZE]; |
c906108c SS |
4754 | |
4755 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4756 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4757 | return 0; |
4758 | ||
4c7d22cb | 4759 | if (target_read_memory (pc, buf, sizeof buf) != 0) |
c906108c SS |
4760 | /* If error reading memory, guess that it is not a delayed branch. */ |
4761 | return 0; | |
4c7d22cb | 4762 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4763 | } |
4764 | ||
6d82d43b AC |
4765 | /* To skip prologues, I use this predicate. Returns either PC itself |
4766 | if the code at PC does not look like a function prologue; otherwise | |
4767 | returns an address that (if we're lucky) follows the prologue. If | |
4768 | LENIENT, then we must skip everything which is involved in setting | |
4769 | up the frame (it's OK to skip more, just so long as we don't skip | |
4770 | anything which might clobber the registers which are being saved. | |
4771 | We must skip more in the case where part of the prologue is in the | |
4772 | delay slot of a non-prologue instruction). */ | |
4773 | ||
4774 | static CORE_ADDR | |
4775 | mips_skip_prologue (CORE_ADDR pc) | |
4776 | { | |
4777 | /* See if we can determine the end of the prologue via the symbol table. | |
4778 | If so, then return either PC, or the PC after the prologue, whichever | |
4779 | is greater. */ | |
4780 | ||
177f84a3 | 4781 | CORE_ADDR post_prologue_pc = after_prologue (pc); |
98b4dd94 | 4782 | CORE_ADDR limit_pc; |
6d82d43b AC |
4783 | |
4784 | if (post_prologue_pc != 0) | |
4785 | return max (pc, post_prologue_pc); | |
4786 | ||
4787 | /* Can't determine prologue from the symbol table, need to examine | |
4788 | instructions. */ | |
4789 | ||
98b4dd94 JB |
4790 | /* Find an upper limit on the function prologue using the debug |
4791 | information. If the debug information could not be used to provide | |
4792 | that bound, then use an arbitrary large number as the upper bound. */ | |
4793 | limit_pc = skip_prologue_using_sal (pc); | |
4794 | if (limit_pc == 0) | |
4795 | limit_pc = pc + 100; /* Magic. */ | |
4796 | ||
0fe7e7c8 | 4797 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4798 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4799 | else |
a65bbe44 | 4800 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4801 | } |
4802 | ||
a5ea2558 AC |
4803 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4804 | used for all MIPS-specific commands. */ | |
4805 | ||
a5ea2558 | 4806 | static void |
acdb74a0 | 4807 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4808 | { |
4809 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4810 | } | |
4811 | ||
a5ea2558 | 4812 | static void |
acdb74a0 | 4813 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4814 | { |
6d82d43b AC |
4815 | printf_unfiltered |
4816 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4817 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4818 | } | |
4819 | ||
c906108c SS |
4820 | /* Commands to show/set the MIPS FPU type. */ |
4821 | ||
c906108c | 4822 | static void |
acdb74a0 | 4823 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4824 | { |
c906108c SS |
4825 | char *fpu; |
4826 | switch (MIPS_FPU_TYPE) | |
4827 | { | |
4828 | case MIPS_FPU_SINGLE: | |
4829 | fpu = "single-precision"; | |
4830 | break; | |
4831 | case MIPS_FPU_DOUBLE: | |
4832 | fpu = "double-precision"; | |
4833 | break; | |
4834 | case MIPS_FPU_NONE: | |
4835 | fpu = "absent (none)"; | |
4836 | break; | |
93d56215 AC |
4837 | default: |
4838 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4839 | } |
4840 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4841 | printf_unfiltered |
4842 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4843 | fpu); | |
c906108c | 4844 | else |
6d82d43b AC |
4845 | printf_unfiltered |
4846 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4847 | } |
4848 | ||
4849 | ||
c906108c | 4850 | static void |
acdb74a0 | 4851 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4852 | { |
6d82d43b AC |
4853 | printf_unfiltered |
4854 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4855 | show_mipsfpu_command (args, from_tty); |
4856 | } | |
4857 | ||
c906108c | 4858 | static void |
acdb74a0 | 4859 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4860 | { |
8d5838b5 AC |
4861 | struct gdbarch_info info; |
4862 | gdbarch_info_init (&info); | |
c906108c SS |
4863 | mips_fpu_type = MIPS_FPU_SINGLE; |
4864 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4865 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4866 | instead of relying on globals. Doing that would let generic code | |
4867 | handle the search for this specific architecture. */ | |
4868 | if (!gdbarch_update_p (info)) | |
4869 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4870 | } |
4871 | ||
c906108c | 4872 | static void |
acdb74a0 | 4873 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4874 | { |
8d5838b5 AC |
4875 | struct gdbarch_info info; |
4876 | gdbarch_info_init (&info); | |
c906108c SS |
4877 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4878 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4879 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4880 | instead of relying on globals. Doing that would let generic code | |
4881 | handle the search for this specific architecture. */ | |
4882 | if (!gdbarch_update_p (info)) | |
4883 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4884 | } |
4885 | ||
c906108c | 4886 | static void |
acdb74a0 | 4887 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4888 | { |
8d5838b5 AC |
4889 | struct gdbarch_info info; |
4890 | gdbarch_info_init (&info); | |
c906108c SS |
4891 | mips_fpu_type = MIPS_FPU_NONE; |
4892 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4893 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4894 | instead of relying on globals. Doing that would let generic code | |
4895 | handle the search for this specific architecture. */ | |
4896 | if (!gdbarch_update_p (info)) | |
4897 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4898 | } |
4899 | ||
c906108c | 4900 | static void |
acdb74a0 | 4901 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4902 | { |
4903 | mips_fpu_type_auto = 1; | |
4904 | } | |
4905 | ||
c906108c | 4906 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4907 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4908 | the relevant processor still exists (it dates back to '94) and | |
4909 | secondly this is not the way to do this. The processor type should | |
4910 | be set by forcing an architecture change. */ | |
c906108c | 4911 | |
691c0433 AC |
4912 | void |
4913 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4914 | { |
691c0433 | 4915 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4916 | CORE_ADDR prid; |
4917 | ||
4918 | prid = read_register (PRID_REGNUM); | |
4919 | ||
4920 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 4921 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4922 | } |
4923 | ||
4924 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4925 | callable as an sfunc. */ | |
4926 | ||
4927 | static void | |
acdb74a0 AC |
4928 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4929 | struct cmd_list_element *c) | |
c906108c SS |
4930 | { |
4931 | reinit_frame_cache (); | |
4932 | } | |
4933 | ||
a89aa300 AC |
4934 | static int |
4935 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4936 | { |
e5ab0dce | 4937 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4938 | mips_extra_func_info_t proc_desc; |
4939 | ||
4940 | /* Search for the function containing this address. Set the low bit | |
4941 | of the address when searching, in case we were given an even address | |
4942 | that is the start of a 16-bit function. If we didn't do this, | |
4943 | the search would fail because the symbol table says the function | |
4944 | starts at an odd address, i.e. 1 byte past the given address. */ | |
4945 | memaddr = ADDR_BITS_REMOVE (memaddr); | |
95404a3e | 4946 | proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL); |
c906108c SS |
4947 | |
4948 | /* Make an attempt to determine if this is a 16-bit function. If | |
4949 | the procedure descriptor exists and the address therein is odd, | |
4950 | it's definitely a 16-bit function. Otherwise, we have to just | |
4951 | guess that if the address passed in is odd, it's 16-bits. */ | |
d31431ed AC |
4952 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4953 | disassembler needs to be able to locally determine the ISA, and | |
4954 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4955 | work. */ | |
c906108c | 4956 | if (proc_desc) |
d31431ed | 4957 | { |
0fe7e7c8 | 4958 | if (mips_pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
6d82d43b | 4959 | info->mach = bfd_mach_mips16; |
d31431ed | 4960 | } |
c906108c | 4961 | else |
d31431ed | 4962 | { |
0fe7e7c8 | 4963 | if (mips_pc_is_mips16 (memaddr)) |
6d82d43b AC |
4964 | info->mach = bfd_mach_mips16; |
4965 | } | |
c906108c SS |
4966 | |
4967 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4968 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4969 | |
e5ab0dce | 4970 | /* Set the disassembler options. */ |
6d82d43b | 4971 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4972 | { |
4973 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4974 | register names from libopcodes. */ |
e5ab0dce AC |
4975 | if (tdep->mips_abi == MIPS_ABI_N32) |
4976 | info->disassembler_options = "gpr-names=n32"; | |
4977 | else | |
4978 | info->disassembler_options = "gpr-names=64"; | |
4979 | info->flavour = bfd_target_elf_flavour; | |
4980 | } | |
4981 | else | |
4982 | /* This string is not recognized explicitly by the disassembler, | |
4983 | but it tells the disassembler to not try to guess the ABI from | |
4984 | the bfd elf headers, such that, if the user overrides the ABI | |
4985 | of a program linked as NewABI, the disassembly will follow the | |
4986 | register naming conventions specified by the user. */ | |
4987 | info->disassembler_options = "gpr-names=32"; | |
4988 | ||
c906108c | 4989 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 4990 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
4991 | return print_insn_big_mips (memaddr, info); |
4992 | else | |
4993 | return print_insn_little_mips (memaddr, info); | |
4994 | } | |
4995 | ||
c906108c SS |
4996 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
4997 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
4998 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
4999 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
5000 | (if necessary) to point to the actual memory location where the | |
5001 | breakpoint should be inserted. */ | |
5002 | ||
f7ab6ec6 | 5003 | static const unsigned char * |
6d82d43b | 5004 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 5005 | { |
d7449b42 | 5006 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c | 5007 | { |
0fe7e7c8 | 5008 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5009 | { |
6d82d43b | 5010 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5011 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5012 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5013 | return mips16_big_breakpoint; |
5014 | } | |
5015 | else | |
5016 | { | |
aaab4dba AC |
5017 | /* The IDT board uses an unusual breakpoint value, and |
5018 | sometimes gets confused when it sees the usual MIPS | |
5019 | breakpoint instruction. */ | |
6d82d43b AC |
5020 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5021 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5022 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 5023 | |
c5aa993b | 5024 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5025 | |
5026 | if (strcmp (target_shortname, "mips") == 0) | |
5027 | return idt_big_breakpoint; | |
5028 | else if (strcmp (target_shortname, "ddb") == 0 | |
5029 | || strcmp (target_shortname, "pmon") == 0 | |
5030 | || strcmp (target_shortname, "lsi") == 0) | |
5031 | return pmon_big_breakpoint; | |
5032 | else | |
5033 | return big_breakpoint; | |
5034 | } | |
5035 | } | |
5036 | else | |
5037 | { | |
0fe7e7c8 | 5038 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5039 | { |
6d82d43b | 5040 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5041 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5042 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5043 | return mips16_little_breakpoint; |
5044 | } | |
5045 | else | |
5046 | { | |
6d82d43b AC |
5047 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5048 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5049 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5050 | |
c5aa993b | 5051 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5052 | |
5053 | if (strcmp (target_shortname, "mips") == 0) | |
5054 | return idt_little_breakpoint; | |
5055 | else if (strcmp (target_shortname, "ddb") == 0 | |
5056 | || strcmp (target_shortname, "pmon") == 0 | |
5057 | || strcmp (target_shortname, "lsi") == 0) | |
5058 | return pmon_little_breakpoint; | |
5059 | else | |
5060 | return little_breakpoint; | |
5061 | } | |
5062 | } | |
5063 | } | |
5064 | ||
5065 | /* If PC is in a mips16 call or return stub, return the address of the target | |
5066 | PC, which is either the callee or the caller. There are several | |
5067 | cases which must be handled: | |
5068 | ||
5069 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5070 | target PC is in $31 ($ra). |
c906108c | 5071 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5072 | and the target PC is in $2. |
c906108c | 5073 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
5074 | before the jal instruction, this is effectively a call stub |
5075 | and the the target PC is in $2. Otherwise this is effectively | |
5076 | a return stub and the target PC is in $18. | |
c906108c SS |
5077 | |
5078 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5079 | gory details. */ |
c906108c | 5080 | |
757a7cc6 | 5081 | static CORE_ADDR |
e7d6a6d2 | 5082 | mips_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
5083 | { |
5084 | char *name; | |
5085 | CORE_ADDR start_addr; | |
5086 | ||
5087 | /* Find the starting address and name of the function containing the PC. */ | |
5088 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5089 | return 0; | |
5090 | ||
5091 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5092 | target PC is in $31 ($ra). */ | |
5093 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5094 | || strcmp (name, "__mips16_ret_df") == 0) | |
4c7d22cb | 5095 | return read_signed_register (MIPS_RA_REGNUM); |
c906108c SS |
5096 | |
5097 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5098 | { | |
5099 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5100 | and the target PC is in $2. */ | |
5101 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 5102 | return read_signed_register (2); |
c906108c SS |
5103 | |
5104 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
5105 | before the jal instruction, this is effectively a call stub |
5106 | and the the target PC is in $2. Otherwise this is effectively | |
5107 | a return stub and the target PC is in $18. */ | |
c906108c SS |
5108 | else if (name[19] == 's' || name[19] == 'd') |
5109 | { | |
5110 | if (pc == start_addr) | |
5111 | { | |
5112 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5113 | stub. Such a stub for a function bar might have a name |
5114 | like __fn_stub_bar, and might look like this: | |
5115 | mfc1 $4,$f13 | |
5116 | mfc1 $5,$f12 | |
5117 | mfc1 $6,$f15 | |
5118 | mfc1 $7,$f14 | |
5119 | la $1,bar (becomes a lui/addiu pair) | |
5120 | jr $1 | |
5121 | So scan down to the lui/addi and extract the target | |
5122 | address from those two instructions. */ | |
c906108c | 5123 | |
6c997a34 | 5124 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
5125 | t_inst inst; |
5126 | int i; | |
5127 | ||
5128 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5129 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5130 | 0) | |
c906108c SS |
5131 | return target_pc; |
5132 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5133 | && strcmp (name, "etext") != 0 | |
5134 | && strcmp (name, "_etext") != 0) | |
5135 | return target_pc; | |
5136 | ||
5137 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5138 | The limit on the search is arbitrarily set to 20 |
5139 | instructions. FIXME. */ | |
4c7d22cb | 5140 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS32_INSN_SIZE) |
c906108c | 5141 | { |
c5aa993b JM |
5142 | inst = mips_fetch_instruction (target_pc); |
5143 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
5144 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
5145 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
5146 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
5147 | } |
5148 | ||
5149 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5150 | return target_pc; | |
5151 | } | |
5152 | else | |
5153 | /* This is the 'return' part of a call stub. The return | |
5154 | address is in $r18. */ | |
6c997a34 | 5155 | return read_signed_register (18); |
c906108c SS |
5156 | } |
5157 | } | |
c5aa993b | 5158 | return 0; /* not a stub */ |
c906108c SS |
5159 | } |
5160 | ||
5161 | ||
5162 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
5163 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
5164 | ||
757a7cc6 | 5165 | static int |
acdb74a0 | 5166 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
5167 | { |
5168 | CORE_ADDR start_addr; | |
5169 | ||
5170 | /* Find the starting address of the function containing the PC. If the | |
5171 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
5172 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
5173 | 0) | |
c906108c SS |
5174 | return 0; |
5175 | ||
5176 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5177 | { | |
5178 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
5179 | if (name[19] >= '0' && name[19] <= '9') | |
5180 | return 1; | |
5181 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5182 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
5183 | else if (name[19] == 's' || name[19] == 'd') |
5184 | return pc == start_addr; | |
5185 | } | |
5186 | ||
c5aa993b | 5187 | return 0; /* not a stub */ |
c906108c SS |
5188 | } |
5189 | ||
5190 | ||
c5115f39 AC |
5191 | /* Return non-zero if the PC is inside a return thunk (aka stub or |
5192 | trampoline). */ | |
c906108c | 5193 | |
e41b17f0 | 5194 | static int |
c5115f39 | 5195 | mips_in_solib_return_trampoline (CORE_ADDR pc, char *name) |
c906108c SS |
5196 | { |
5197 | CORE_ADDR start_addr; | |
5198 | ||
5199 | /* Find the starting address of the function containing the PC. */ | |
5200 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
5201 | return 0; | |
5202 | ||
5203 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
5204 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5205 | || strcmp (name, "__mips16_ret_df") == 0) | |
5206 | return 1; | |
5207 | ||
5208 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 5209 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 5210 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 5211 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
5212 | return 1; |
5213 | ||
c5aa993b | 5214 | return 0; /* not a stub */ |
c906108c SS |
5215 | } |
5216 | ||
5217 | ||
a53c66de AC |
5218 | /* Return non-zero if the PC is in a library helper function that |
5219 | should be ignored. This implements the | |
5220 | DEPRECATED_IGNORE_HELPER_CALL macro. */ | |
c906108c SS |
5221 | |
5222 | int | |
acdb74a0 | 5223 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
5224 | { |
5225 | char *name; | |
5226 | ||
5227 | /* Find the starting address and name of the function containing the PC. */ | |
5228 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
5229 | return 0; | |
5230 | ||
5231 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
5232 | that we want to ignore. */ | |
5233 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
5234 | || strcmp (name, "__mips16_ret_df") == 0); | |
5235 | } | |
5236 | ||
5237 | ||
a4b8ebc8 AC |
5238 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5239 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5240 | |
5241 | static int | |
5242 | mips_stab_reg_to_regnum (int num) | |
5243 | { | |
a4b8ebc8 | 5244 | int regnum; |
2f38ef89 | 5245 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5246 | regnum = num; |
2f38ef89 | 5247 | else if (num >= 38 && num < 70) |
56cea623 | 5248 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 5249 | else if (num == 70) |
56cea623 | 5250 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5251 | else if (num == 71) |
56cea623 | 5252 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5253 | else |
a4b8ebc8 AC |
5254 | /* This will hopefully (eventually) provoke a warning. Should |
5255 | we be calling complaint() here? */ | |
5256 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5257 | return NUM_REGS + regnum; | |
88c72b7d AC |
5258 | } |
5259 | ||
2f38ef89 | 5260 | |
a4b8ebc8 AC |
5261 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5262 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
5263 | |
5264 | static int | |
2f38ef89 | 5265 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 5266 | { |
a4b8ebc8 | 5267 | int regnum; |
2f38ef89 | 5268 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5269 | regnum = num; |
2f38ef89 | 5270 | else if (num >= 32 && num < 64) |
56cea623 | 5271 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 5272 | else if (num == 64) |
56cea623 | 5273 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 5274 | else if (num == 65) |
56cea623 | 5275 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 5276 | else |
a4b8ebc8 AC |
5277 | /* This will hopefully (eventually) provoke a warning. Should we |
5278 | be calling complaint() here? */ | |
5279 | return NUM_REGS + NUM_PSEUDO_REGS; | |
5280 | return NUM_REGS + regnum; | |
5281 | } | |
5282 | ||
5283 | static int | |
5284 | mips_register_sim_regno (int regnum) | |
5285 | { | |
5286 | /* Only makes sense to supply raw registers. */ | |
5287 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
5288 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
5289 | decide if it is valid. Should instead define a standard sim/gdb | |
5290 | register numbering scheme. */ | |
5291 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
5292 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
5293 | return regnum; | |
5294 | else | |
6d82d43b | 5295 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5296 | } |
5297 | ||
2f38ef89 | 5298 | |
fc0c74b1 AC |
5299 | /* Convert an integer into an address. By first converting the value |
5300 | into a pointer and then extracting it signed, the address is | |
5301 | guarenteed to be correctly sign extended. */ | |
5302 | ||
5303 | static CORE_ADDR | |
5304 | mips_integer_to_address (struct type *type, void *buf) | |
5305 | { | |
5306 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5307 | LONGEST val = unpack_long (type, buf); | |
5308 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
5309 | return extract_signed_integer (tmp, | |
5310 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
5311 | } | |
5312 | ||
caaa3122 DJ |
5313 | static void |
5314 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5315 | { | |
5316 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5317 | const char *name = bfd_get_section_name (abfd, sect); | |
5318 | ||
5319 | if (*abip != MIPS_ABI_UNKNOWN) | |
5320 | return; | |
5321 | ||
5322 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5323 | return; | |
5324 | ||
5325 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5326 | *abip = MIPS_ABI_O32; | |
5327 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5328 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5329 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5330 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5331 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5332 | *abip = MIPS_ABI_O64; | |
5333 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5334 | *abip = MIPS_ABI_EABI32; | |
5335 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5336 | *abip = MIPS_ABI_EABI64; | |
5337 | else | |
5338 | warning ("unsupported ABI %s.", name + 8); | |
5339 | } | |
5340 | ||
2e4ebe70 DJ |
5341 | static enum mips_abi |
5342 | global_mips_abi (void) | |
5343 | { | |
5344 | int i; | |
5345 | ||
5346 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5347 | if (mips_abi_strings[i] == mips_abi_string) | |
5348 | return (enum mips_abi) i; | |
5349 | ||
6d82d43b | 5350 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
5351 | } |
5352 | ||
c2d11a7d | 5353 | static struct gdbarch * |
6d82d43b | 5354 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5355 | { |
c2d11a7d JM |
5356 | struct gdbarch *gdbarch; |
5357 | struct gdbarch_tdep *tdep; | |
5358 | int elf_flags; | |
2e4ebe70 | 5359 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 5360 | int num_regs; |
8d5838b5 | 5361 | enum mips_fpu_type fpu_type; |
c2d11a7d | 5362 | |
ec03c1ac AC |
5363 | /* First of all, extract the elf_flags, if available. */ |
5364 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5365 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5366 | else if (arches != NULL) |
5367 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5368 | else |
5369 | elf_flags = 0; | |
5370 | if (gdbarch_debug) | |
5371 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5372 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5373 | |
102182a9 | 5374 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5375 | switch ((elf_flags & EF_MIPS_ABI)) |
5376 | { | |
5377 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5378 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5379 | break; |
5380 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5381 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5382 | break; |
5383 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5384 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5385 | break; |
5386 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5387 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5388 | break; |
5389 | default: | |
acdb74a0 | 5390 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5391 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5392 | else |
ec03c1ac | 5393 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5394 | break; |
5395 | } | |
acdb74a0 | 5396 | |
caaa3122 | 5397 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5398 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5399 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5400 | |
dc305454 | 5401 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5402 | MIPS architecture (if there is one). */ |
5403 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5404 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5405 | |
32a6503c | 5406 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5407 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5408 | && info.bfd_arch_info != NULL |
5409 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5410 | { | |
5411 | switch (info.bfd_arch_info->mach) | |
5412 | { | |
5413 | case bfd_mach_mips3900: | |
ec03c1ac | 5414 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5415 | break; |
5416 | case bfd_mach_mips4100: | |
5417 | case bfd_mach_mips5000: | |
ec03c1ac | 5418 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5419 | break; |
1d06468c EZ |
5420 | case bfd_mach_mips8000: |
5421 | case bfd_mach_mips10000: | |
32a6503c KB |
5422 | /* On Irix, ELF64 executables use the N64 ABI. The |
5423 | pseudo-sections which describe the ABI aren't present | |
5424 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5425 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5426 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5427 | found_abi = MIPS_ABI_N64; |
28d169de | 5428 | else |
ec03c1ac | 5429 | found_abi = MIPS_ABI_N32; |
1d06468c | 5430 | break; |
bf64bfd6 AC |
5431 | } |
5432 | } | |
2e4ebe70 | 5433 | |
ec03c1ac AC |
5434 | if (gdbarch_debug) |
5435 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5436 | found_abi); | |
5437 | ||
5438 | /* What has the user specified from the command line? */ | |
5439 | wanted_abi = global_mips_abi (); | |
5440 | if (gdbarch_debug) | |
5441 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5442 | wanted_abi); | |
2e4ebe70 DJ |
5443 | |
5444 | /* Now that we have found what the ABI for this binary would be, | |
5445 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5446 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5447 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5448 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5449 | mips_abi = found_abi; | |
5450 | else | |
5451 | mips_abi = MIPS_ABI_O32; | |
5452 | if (gdbarch_debug) | |
5453 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5454 | mips_abi); | |
2e4ebe70 | 5455 | |
ec03c1ac | 5456 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5457 | if (gdbarch_debug) |
ec03c1ac AC |
5458 | fprintf_unfiltered (gdb_stdlog, |
5459 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5460 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5461 | |
8d5838b5 AC |
5462 | /* Determine the MIPS FPU type. */ |
5463 | if (!mips_fpu_type_auto) | |
5464 | fpu_type = mips_fpu_type; | |
5465 | else if (info.bfd_arch_info != NULL | |
5466 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5467 | switch (info.bfd_arch_info->mach) | |
5468 | { | |
5469 | case bfd_mach_mips3900: | |
5470 | case bfd_mach_mips4100: | |
5471 | case bfd_mach_mips4111: | |
a9d61c86 | 5472 | case bfd_mach_mips4120: |
8d5838b5 AC |
5473 | fpu_type = MIPS_FPU_NONE; |
5474 | break; | |
5475 | case bfd_mach_mips4650: | |
5476 | fpu_type = MIPS_FPU_SINGLE; | |
5477 | break; | |
5478 | default: | |
5479 | fpu_type = MIPS_FPU_DOUBLE; | |
5480 | break; | |
5481 | } | |
5482 | else if (arches != NULL) | |
5483 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5484 | else | |
5485 | fpu_type = MIPS_FPU_DOUBLE; | |
5486 | if (gdbarch_debug) | |
5487 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5488 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5489 | |
c2d11a7d JM |
5490 | /* try to find a pre-existing architecture */ |
5491 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5492 | arches != NULL; | |
5493 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5494 | { | |
5495 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5496 | using. */ |
9103eae0 | 5497 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5498 | continue; |
9103eae0 | 5499 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5500 | continue; |
719ec221 AC |
5501 | /* Need to be pedantic about which register virtual size is |
5502 | used. */ | |
5503 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5504 | != mips64_transfers_32bit_regs_p) | |
5505 | continue; | |
8d5838b5 AC |
5506 | /* Be pedantic about which FPU is selected. */ |
5507 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5508 | continue; | |
4be87837 | 5509 | return arches->gdbarch; |
c2d11a7d JM |
5510 | } |
5511 | ||
102182a9 | 5512 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5513 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5514 | gdbarch = gdbarch_alloc (&info, tdep); | |
5515 | tdep->elf_flags = elf_flags; | |
719ec221 | 5516 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5517 | tdep->found_abi = found_abi; |
5518 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5519 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 5520 | |
102182a9 | 5521 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5522 | set_gdbarch_short_bit (gdbarch, 16); |
5523 | set_gdbarch_int_bit (gdbarch, 32); | |
5524 | set_gdbarch_float_bit (gdbarch, 32); | |
5525 | set_gdbarch_double_bit (gdbarch, 64); | |
5526 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5527 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5528 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5529 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5530 | |
6d82d43b | 5531 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5532 | mips_elf_make_msymbol_special); |
5533 | ||
16e109ca | 5534 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5535 | { |
16e109ca | 5536 | const char **reg_names; |
56cea623 AC |
5537 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5538 | struct mips_regnum); | |
56cea623 AC |
5539 | if (info.osabi == GDB_OSABI_IRIX) |
5540 | { | |
5541 | regnum->fp0 = 32; | |
5542 | regnum->pc = 64; | |
5543 | regnum->cause = 65; | |
5544 | regnum->badvaddr = 66; | |
5545 | regnum->hi = 67; | |
5546 | regnum->lo = 68; | |
5547 | regnum->fp_control_status = 69; | |
5548 | regnum->fp_implementation_revision = 70; | |
5549 | num_regs = 71; | |
16e109ca | 5550 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5551 | } |
5552 | else | |
5553 | { | |
5554 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5555 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5556 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5557 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5558 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5559 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5560 | regnum->fp_control_status = 70; | |
5561 | regnum->fp_implementation_revision = 71; | |
5562 | num_regs = 90; | |
16e109ca AC |
5563 | if (info.bfd_arch_info != NULL |
5564 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5565 | reg_names = mips_tx39_reg_names; | |
5566 | else | |
5567 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
5568 | } |
5569 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
5570 | replaced by read_pc? */ | |
f10683bb MH |
5571 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5572 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5573 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5574 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5575 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5576 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5577 | tdep->mips_processor_reg_names = reg_names; | |
5578 | tdep->regnum = regnum; | |
56cea623 | 5579 | } |
fe29b929 | 5580 | |
0dadbba0 | 5581 | switch (mips_abi) |
c2d11a7d | 5582 | { |
0dadbba0 | 5583 | case MIPS_ABI_O32: |
25ab4790 | 5584 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5585 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5586 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5587 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5588 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5589 | set_gdbarch_long_bit (gdbarch, 32); |
5590 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5591 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5592 | break; | |
0dadbba0 | 5593 | case MIPS_ABI_O64: |
25ab4790 | 5594 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5595 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5596 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5597 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5598 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5599 | set_gdbarch_long_bit (gdbarch, 32); |
5600 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5601 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5602 | break; | |
0dadbba0 | 5603 | case MIPS_ABI_EABI32: |
25ab4790 | 5604 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5605 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5606 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5607 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5608 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5609 | set_gdbarch_long_bit (gdbarch, 32); |
5610 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5611 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5612 | break; | |
0dadbba0 | 5613 | case MIPS_ABI_EABI64: |
25ab4790 | 5614 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5615 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5616 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5617 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5618 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5619 | set_gdbarch_long_bit (gdbarch, 64); |
5620 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5621 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5622 | break; | |
0dadbba0 | 5623 | case MIPS_ABI_N32: |
25ab4790 | 5624 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5625 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5626 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5627 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5628 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5629 | set_gdbarch_long_bit (gdbarch, 32); |
5630 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5631 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
5632 | set_gdbarch_long_double_bit (gdbarch, 128); |
5633 | set_gdbarch_long_double_format (gdbarch, | |
5634 | &floatformat_n32n64_long_double_big); | |
28d169de KB |
5635 | break; |
5636 | case MIPS_ABI_N64: | |
25ab4790 | 5637 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5638 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5639 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5640 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5641 | tdep->default_mask_address_p = 0; |
5642 | set_gdbarch_long_bit (gdbarch, 64); | |
5643 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5644 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
5645 | set_gdbarch_long_double_bit (gdbarch, 128); |
5646 | set_gdbarch_long_double_format (gdbarch, | |
5647 | &floatformat_n32n64_long_double_big); | |
0dadbba0 | 5648 | break; |
c2d11a7d | 5649 | default: |
6d82d43b | 5650 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
5651 | } |
5652 | ||
a5ea2558 AC |
5653 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5654 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5655 | comment: | |
5656 | ||
5657 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5658 | flag in object files because to do so would make it impossible to | |
102182a9 | 5659 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5660 | unnecessarily restrictive. |
361d1df0 | 5661 | |
a5ea2558 AC |
5662 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5663 | but to set this flag before gcc is built with such multilibs will | |
5664 | break too many systems.'' | |
5665 | ||
5666 | But even more unhelpfully, the default linker output target for | |
5667 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5668 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5669 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5670 | this flag to detect 32-bit mode would do the wrong thing given |
5671 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5672 | as 32-bit programs by default. */ |
a5ea2558 | 5673 | |
6c997a34 | 5674 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5675 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 5676 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5677 | |
102182a9 MS |
5678 | /* Add/remove bits from an address. The MIPS needs be careful to |
5679 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5680 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5681 | ||
58dfe9ff AC |
5682 | /* Unwind the frame. */ |
5683 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 5684 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5685 | |
102182a9 | 5686 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5687 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5688 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5689 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5690 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5691 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5692 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5693 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5694 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5695 | |
c2d11a7d JM |
5696 | /* MIPS version of CALL_DUMMY */ |
5697 | ||
9710e734 AC |
5698 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5699 | replaced by a command, and all targets will default to on stack | |
5700 | (regardless of the stack's execute status). */ | |
5701 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5702 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5703 | |
87783b8b AC |
5704 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5705 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5706 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5707 | ||
f7b9e9fc AC |
5708 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5709 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5710 | |
5711 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5712 | |
fc0c74b1 AC |
5713 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5714 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5715 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5716 | |
a4b8ebc8 | 5717 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5718 | |
e11c53d2 | 5719 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5720 | |
e5ab0dce AC |
5721 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5722 | ||
3a3bc038 AC |
5723 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5724 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5725 | need to all be folded into the target vector. Since they are | |
5726 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5727 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5728 | is sitting on? */ | |
5729 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5730 | ||
e7d6a6d2 | 5731 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5732 | |
6de918a6 DJ |
5733 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
5734 | to support MIPS16. This is a bad thing. Make sure not to do it | |
5735 | if we have an OS ABI that actually supports shared libraries, since | |
5736 | shared library support is more important. If we have an OS someday | |
5737 | that supports both shared libraries and MIPS16, we'll have to find | |
5738 | a better place for these. */ | |
5739 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
5740 | { | |
5741 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
c5115f39 | 5742 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_solib_return_trampoline); |
6de918a6 DJ |
5743 | } |
5744 | ||
5745 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
5746 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 5747 | |
5792a79b | 5748 | /* Unwind the frame. */ |
eec63939 | 5749 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
5792a79b | 5750 | frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer); |
45c9dd44 AC |
5751 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5752 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
eec63939 | 5753 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
5792a79b | 5754 | frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer); |
45c9dd44 AC |
5755 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5756 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5757 | |
4b9b3959 AC |
5758 | return gdbarch; |
5759 | } | |
5760 | ||
2e4ebe70 | 5761 | static void |
6d82d43b | 5762 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5763 | { |
5764 | struct gdbarch_info info; | |
5765 | ||
5766 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5767 | mips_gdbarch_init will take care of the rest. */ | |
5768 | gdbarch_info_init (&info); | |
5769 | gdbarch_update_p (info); | |
5770 | } | |
5771 | ||
ad188201 KB |
5772 | /* Print out which MIPS ABI is in use. */ |
5773 | ||
5774 | static void | |
5775 | show_mips_abi (char *ignore_args, int from_tty) | |
5776 | { | |
5777 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
5778 | printf_filtered |
5779 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
5780 | else |
5781 | { | |
5782 | enum mips_abi global_abi = global_mips_abi (); | |
5783 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5784 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5785 | ||
5786 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
5787 | printf_filtered |
5788 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
5789 | actual_abi_str); | |
ad188201 | 5790 | else if (global_abi == actual_abi) |
6d82d43b AC |
5791 | printf_filtered |
5792 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
5793 | actual_abi_str); | |
ad188201 KB |
5794 | else |
5795 | { | |
5796 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
5797 | printf_filtered |
5798 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
5799 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
5800 | } |
5801 | } | |
5802 | } | |
5803 | ||
4b9b3959 AC |
5804 | static void |
5805 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5806 | { | |
5807 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5808 | if (tdep != NULL) | |
c2d11a7d | 5809 | { |
acdb74a0 AC |
5810 | int ef_mips_arch; |
5811 | int ef_mips_32bitmode; | |
5812 | /* determine the ISA */ | |
5813 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
5814 | { | |
5815 | case E_MIPS_ARCH_1: | |
5816 | ef_mips_arch = 1; | |
5817 | break; | |
5818 | case E_MIPS_ARCH_2: | |
5819 | ef_mips_arch = 2; | |
5820 | break; | |
5821 | case E_MIPS_ARCH_3: | |
5822 | ef_mips_arch = 3; | |
5823 | break; | |
5824 | case E_MIPS_ARCH_4: | |
93d56215 | 5825 | ef_mips_arch = 4; |
acdb74a0 AC |
5826 | break; |
5827 | default: | |
93d56215 | 5828 | ef_mips_arch = 0; |
acdb74a0 AC |
5829 | break; |
5830 | } | |
5831 | /* determine the size of a pointer */ | |
5832 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
5833 | fprintf_unfiltered (file, |
5834 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5835 | tdep->elf_flags); |
4b9b3959 | 5836 | fprintf_unfiltered (file, |
acdb74a0 AC |
5837 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5838 | ef_mips_32bitmode); | |
5839 | fprintf_unfiltered (file, | |
5840 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5841 | ef_mips_arch); | |
5842 | fprintf_unfiltered (file, | |
5843 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5844 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5845 | fprintf_unfiltered (file, |
5846 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5847 | mips_mask_address_p (tdep), |
4014092b | 5848 | tdep->default_mask_address_p); |
c2d11a7d | 5849 | } |
4b9b3959 AC |
5850 | fprintf_unfiltered (file, |
5851 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5852 | MIPS_DEFAULT_FPU_TYPE, | |
5853 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5854 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5855 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5856 | : "???")); | |
6d82d43b | 5857 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5858 | fprintf_unfiltered (file, |
5859 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5860 | MIPS_FPU_TYPE, | |
5861 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5862 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5863 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5864 | : "???")); | |
4b9b3959 | 5865 | fprintf_unfiltered (file, |
480d3dd2 | 5866 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 5867 | mips_stack_argsize (current_gdbarch)); |
2475bac3 AC |
5868 | fprintf_unfiltered (file, |
5869 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 5870 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
5871 | fprintf_unfiltered (file, |
5872 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
5873 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
5874 | fprintf_unfiltered (file, |
5875 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
5876 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
5877 | fprintf_unfiltered (file, | |
5878 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
5879 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
5880 | fprintf_unfiltered (file, |
5881 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
5882 | FIRST_EMBED_REGNUM); | |
2475bac3 | 5883 | fprintf_unfiltered (file, |
a53c66de AC |
5884 | "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n", |
5885 | XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
5886 | fprintf_unfiltered (file, |
5887 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
5888 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
5889 | fprintf_unfiltered (file, |
5890 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
5891 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
5892 | #ifdef MACHINE_CPROC_FP_OFFSET |
5893 | fprintf_unfiltered (file, | |
5894 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
5895 | MACHINE_CPROC_FP_OFFSET); | |
5896 | #endif | |
5897 | #ifdef MACHINE_CPROC_PC_OFFSET | |
5898 | fprintf_unfiltered (file, | |
5899 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
5900 | MACHINE_CPROC_PC_OFFSET); | |
5901 | #endif | |
5902 | #ifdef MACHINE_CPROC_SP_OFFSET | |
5903 | fprintf_unfiltered (file, | |
5904 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
5905 | MACHINE_CPROC_SP_OFFSET); | |
5906 | #endif | |
6d82d43b | 5907 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
5908 | fprintf_unfiltered (file, |
5909 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
2475bac3 | 5910 | fprintf_unfiltered (file, |
acdb74a0 AC |
5911 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
5912 | MIPS_LAST_ARG_REGNUM, | |
4c7d22cb | 5913 | MIPS_LAST_ARG_REGNUM - MIPS_A0_REGNUM + 1); |
2475bac3 | 5914 | fprintf_unfiltered (file, |
6d82d43b | 5915 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 5916 | fprintf_unfiltered (file, |
1b13c4f6 | 5917 | "mips_dump_tdep: mips_abi_regsize() = %d\n", |
13326b4e | 5918 | mips_abi_regsize (current_gdbarch)); |
2475bac3 | 5919 | fprintf_unfiltered (file, |
6d82d43b | 5920 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
5921 | fprintf_unfiltered (file, |
5922 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
5923 | fprintf_unfiltered (file, | |
5924 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
5925 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
5926 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
5927 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
5928 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
5929 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
5930 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
5931 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
5932 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
5933 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
5934 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
2475bac3 AC |
5935 | #ifdef SAVED_BYTES |
5936 | fprintf_unfiltered (file, | |
6d82d43b | 5937 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
5938 | #endif |
5939 | #ifdef SAVED_FP | |
6d82d43b | 5940 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
5941 | #endif |
5942 | #ifdef SAVED_PC | |
6d82d43b | 5943 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
5944 | #endif |
5945 | fprintf_unfiltered (file, | |
5946 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
5947 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
2475bac3 AC |
5948 | fprintf_unfiltered (file, |
5949 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
5950 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
5951 | fprintf_unfiltered (file, | |
b0ed3589 AC |
5952 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
5953 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
5954 | fprintf_unfiltered (file, |
5955 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
5956 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
5957 | #ifdef STACK_END_ADDR | |
5958 | fprintf_unfiltered (file, | |
5959 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
5960 | STACK_END_ADDR); | |
5961 | #endif | |
5962 | fprintf_unfiltered (file, | |
5963 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
5964 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
5965 | fprintf_unfiltered (file, | |
5966 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
5967 | STEP_SKIPS_DELAY_P); | |
5968 | fprintf_unfiltered (file, | |
5969 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
5970 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
2475bac3 AC |
5971 | fprintf_unfiltered (file, |
5972 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
5973 | fprintf_unfiltered (file, | |
5974 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
5975 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
5976 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
5977 | #ifdef TRACE_CLEAR |
5978 | fprintf_unfiltered (file, | |
5979 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
5980 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
5981 | #endif | |
5982 | #ifdef TRACE_FLAVOR | |
5983 | fprintf_unfiltered (file, | |
6d82d43b | 5984 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
5985 | #endif |
5986 | #ifdef TRACE_FLAVOR_SIZE | |
5987 | fprintf_unfiltered (file, | |
5988 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
5989 | TRACE_FLAVOR_SIZE); | |
5990 | #endif | |
5991 | #ifdef TRACE_SET | |
5992 | fprintf_unfiltered (file, | |
5993 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 5994 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 5995 | #endif |
2475bac3 AC |
5996 | #ifdef UNUSED_REGNUM |
5997 | fprintf_unfiltered (file, | |
6d82d43b | 5998 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 5999 | #endif |
2475bac3 AC |
6000 | fprintf_unfiltered (file, |
6001 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
6002 | (long) VM_MIN_ADDRESS); | |
c2d11a7d JM |
6003 | } |
6004 | ||
6d82d43b | 6005 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6006 | |
c906108c | 6007 | void |
acdb74a0 | 6008 | _initialize_mips_tdep (void) |
c906108c SS |
6009 | { |
6010 | static struct cmd_list_element *mipsfpulist = NULL; | |
6011 | struct cmd_list_element *c; | |
6012 | ||
6d82d43b | 6013 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6014 | if (MIPS_ABI_LAST + 1 |
6015 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
6016 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
6017 | ||
4b9b3959 | 6018 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6019 | |
8d5f9dcb DJ |
6020 | mips_pdr_data = register_objfile_data (); |
6021 | ||
a5ea2558 AC |
6022 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
6023 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
6024 | "Various MIPS specific commands.", | |
6025 | &setmipscmdlist, "set mips ", 0, &setlist); | |
6026 | ||
6027 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
6028 | "Various MIPS specific commands.", | |
6029 | &showmipscmdlist, "show mips ", 0, &showlist); | |
6030 | ||
6031 | /* Allow the user to override the saved register size. */ | |
1b295c3d AC |
6032 | add_setshow_enum_cmd ("saved-gpreg-size", class_obscure, |
6033 | size_enums, &mips_abi_regsize_string, "\ | |
6034 | Set size of general purpose registers saved on the stack.\n", "\ | |
6035 | Show size of general purpose registers saved on the stack.\n", "\ | |
a5ea2558 AC |
6036 | This option can be set to one of:\n\ |
6037 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
6038 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
6039 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
6040 | saved GP register size from information contained in the executable.\n\ | |
1b295c3d AC |
6041 | (default: auto)", "\ |
6042 | Size of general purpose registers saved on the stack is %s.\n", | |
6043 | NULL, NULL, &setmipscmdlist, &showmipscmdlist); | |
a5ea2558 | 6044 | |
d929b26f | 6045 | /* Allow the user to override the argument stack size. */ |
1b295c3d AC |
6046 | add_setshow_enum_cmd ("stack-arg-size", class_obscure, |
6047 | size_enums, &mips_stack_argsize_string, "\ | |
6048 | Set the amount of stack space reserved for each argument.\n", "\ | |
6049 | Show the amount of stack space reserved for each argument.\n", "\ | |
d929b26f AC |
6050 | This option can be set to one of:\n\ |
6051 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
6052 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
6053 | auto - Allow GDB to determine the correct setting from the current\n\ | |
1b295c3d AC |
6054 | target and executable (default)", "\ |
6055 | The amount of stack space reserved for each argument is %s.\n", | |
6056 | NULL, NULL, &setmipscmdlist, &showmipscmdlist); | |
d929b26f | 6057 | |
2e4ebe70 DJ |
6058 | /* Allow the user to override the ABI. */ |
6059 | c = add_set_enum_cmd | |
6060 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
6061 | "Set the ABI used by this program.\n" | |
6062 | "This option can be set to one of:\n" | |
6063 | " auto - the default ABI associated with the current binary\n" | |
6064 | " o32\n" | |
6d82d43b | 6065 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 6066 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 6067 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 6068 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 6069 | |
c906108c SS |
6070 | /* Let the user turn off floating point and set the fence post for |
6071 | heuristic_proc_start. */ | |
6072 | ||
6073 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
6074 | "Set use of MIPS floating-point coprocessor.", | |
6075 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
6076 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
6077 | "Select single-precision MIPS floating-point coprocessor.", | |
6078 | &mipsfpulist); | |
6079 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 6080 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
6081 | &mipsfpulist); |
6082 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6083 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6084 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6085 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 6086 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
6087 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6088 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6089 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6090 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
6091 | "Select MIPS floating-point coprocessor automatically.", | |
6092 | &mipsfpulist); | |
6093 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
6094 | "Show current use of MIPS floating-point coprocessor target.", | |
6095 | &showlist); | |
6096 | ||
c906108c SS |
6097 | /* We really would like to have both "0" and "unlimited" work, but |
6098 | command.c doesn't deal with that. So make it a var_zinteger | |
6099 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 AC |
6100 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
6101 | &heuristic_fence_post, "\ | |
6102 | Set the distance searched for the start of a function.\n", "\ | |
6103 | Show the distance searched for the start of a function.\n", "\ | |
c906108c SS |
6104 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6105 | program for the start of a function. This command sets the distance of the\n\ | |
6bcadd06 AC |
6106 | search. The only need to set it is when debugging a stripped executable.", "\ |
6107 | The distance searched for the start of a function is %s.\n", | |
6108 | reinit_frame_cache_sfunc, NULL, | |
6109 | &setlist, &showlist); | |
c906108c SS |
6110 | |
6111 | /* Allow the user to control whether the upper bits of 64-bit | |
6112 | addresses should be zeroed. */ | |
e9e68a56 | 6113 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
3b64bf98 AC |
6114 | Set zeroing of upper 32 bits of 64-bit addresses.", "\ |
6115 | Show zeroing of upper 32 bits of 64-bit addresses.", "\ | |
e9e68a56 AC |
6116 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
6117 | allow GDB to determine the correct value.\n", "\ | |
3b64bf98 | 6118 | Zerroing of upper 32 bits of 64-bit address is %s.", |
6d82d43b | 6119 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
6120 | |
6121 | /* Allow the user to control the size of 32 bit registers within the | |
6122 | raw remote packet. */ | |
b3f42336 AC |
6123 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
6124 | &mips64_transfers_32bit_regs_p, "\ | |
3b64bf98 AC |
6125 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ |
6126 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ | |
719ec221 AC |
6127 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6128 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 6129 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
3b64bf98 AC |
6130 | Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.", |
6131 | set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); | |
9ace0497 AC |
6132 | |
6133 | /* Debug this files internals. */ | |
6bcadd06 AC |
6134 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
6135 | &mips_debug, "\ | |
6136 | Set mips debugging.\n", "\ | |
6137 | Show mips debugging.\n", "\ | |
6138 | When non-zero, mips specific debugging is enabled.\n", "\ | |
6139 | Mips debugging is currently %s.\n", | |
6140 | NULL, NULL, | |
6141 | &setdebuglist, &showdebuglist); | |
c906108c | 6142 | } |