Remove regcache_raw_read
[deliverable/binutils-gdb.git] / gdb / mn10300-tdep.c
CommitLineData
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1/* Target-dependent code for the Matsushita MN10300 for GDB, the GNU debugger.
2
e2882c85 3 Copyright (C) 1996-2018 Free Software Foundation, Inc.
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4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
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10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
342ee437 19
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20#include "defs.h"
21#include "arch-utils.h"
22#include "dis-asm.h"
23#include "gdbtypes.h"
24#include "regcache.h"
025bb325 25#include "gdbcore.h" /* For write_memory_unsigned_integer. */
342ee437 26#include "value.h"
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27#include "frame.h"
28#include "frame-unwind.h"
29#include "frame-base.h"
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30#include "symtab.h"
31#include "dwarf2-frame.h"
697e3bc9 32#include "osabi.h"
ee3a2f01 33#include "infcall.h"
6c02c64c 34#include "prologue-value.h"
effa26a9 35#include "target.h"
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36
37#include "mn10300-tdep.h"
38
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39
40/* The am33-2 has 64 registers. */
41#define MN10300_MAX_NUM_REGS 64
42
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43/* Big enough to hold the size of the largest register in bytes. */
44#define MN10300_MAX_REGISTER_SIZE 64
45
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46/* This structure holds the results of a prologue analysis. */
47struct mn10300_prologue
48{
d80b854b
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49 /* The architecture for which we generated this prologue info. */
50 struct gdbarch *gdbarch;
51
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52 /* The offset from the frame base to the stack pointer --- always
53 zero or negative.
54
55 Calling this a "size" is a bit misleading, but given that the
56 stack grows downwards, using offsets for everything keeps one
57 from going completely sign-crazy: you never change anything's
58 sign for an ADD instruction; always change the second operand's
59 sign for a SUB instruction; and everything takes care of
60 itself. */
61 int frame_size;
62
63 /* Non-zero if this function has initialized the frame pointer from
64 the stack pointer, zero otherwise. */
65 int has_frame_ptr;
66
67 /* If has_frame_ptr is non-zero, this is the offset from the frame
68 base to where the frame pointer points. This is always zero or
69 negative. */
70 int frame_ptr_offset;
71
72 /* The address of the first instruction at which the frame has been
73 set up and the arguments are where the debug info says they are
74 --- as best as we can tell. */
75 CORE_ADDR prologue_end;
76
77 /* reg_offset[R] is the offset from the CFA at which register R is
78 saved, or 1 if register R has not been saved. (Real values are
79 always zero or negative.) */
80 int reg_offset[MN10300_MAX_NUM_REGS];
81};
82
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83
84/* Compute the alignment required by a type. */
85
86static int
87mn10300_type_align (struct type *type)
88{
89 int i, align = 1;
90
91 switch (TYPE_CODE (type))
92 {
93 case TYPE_CODE_INT:
94 case TYPE_CODE_ENUM:
95 case TYPE_CODE_SET:
96 case TYPE_CODE_RANGE:
97 case TYPE_CODE_CHAR:
98 case TYPE_CODE_BOOL:
99 case TYPE_CODE_FLT:
100 case TYPE_CODE_PTR:
101 case TYPE_CODE_REF:
aa006118 102 case TYPE_CODE_RVALUE_REF:
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103 return TYPE_LENGTH (type);
104
105 case TYPE_CODE_COMPLEX:
106 return TYPE_LENGTH (type) / 2;
107
108 case TYPE_CODE_STRUCT:
109 case TYPE_CODE_UNION:
110 for (i = 0; i < TYPE_NFIELDS (type); i++)
111 {
112 int falign = mn10300_type_align (TYPE_FIELD_TYPE (type, i));
113 while (align < falign)
114 align <<= 1;
115 }
116 return align;
117
118 case TYPE_CODE_ARRAY:
119 /* HACK! Structures containing arrays, even small ones, are not
120 elligible for returning in registers. */
121 return 256;
122
123 case TYPE_CODE_TYPEDEF:
124 return mn10300_type_align (check_typedef (type));
125
126 default:
127 internal_error (__FILE__, __LINE__, _("bad switch"));
128 }
129}
130
342ee437 131/* Should call_function allocate stack space for a struct return? */
342ee437 132static int
99fe5f9d 133mn10300_use_struct_convention (struct type *type)
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134{
135 /* Structures bigger than a pair of words can't be returned in
136 registers. */
137 if (TYPE_LENGTH (type) > 8)
138 return 1;
139
140 switch (TYPE_CODE (type))
141 {
142 case TYPE_CODE_STRUCT:
143 case TYPE_CODE_UNION:
144 /* Structures with a single field are handled as the field
145 itself. */
146 if (TYPE_NFIELDS (type) == 1)
99fe5f9d 147 return mn10300_use_struct_convention (TYPE_FIELD_TYPE (type, 0));
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148
149 /* Structures with word or double-word size are passed in memory, as
150 long as they require at least word alignment. */
151 if (mn10300_type_align (type) >= 4)
152 return 0;
153
154 return 1;
155
156 /* Arrays are addressable, so they're never returned in
157 registers. This condition can only hold when the array is
158 the only field of a struct or union. */
159 case TYPE_CODE_ARRAY:
160 return 1;
161
162 case TYPE_CODE_TYPEDEF:
99fe5f9d 163 return mn10300_use_struct_convention (check_typedef (type));
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164
165 default:
166 return 0;
167 }
168}
169
342ee437 170static void
99fe5f9d 171mn10300_store_return_value (struct gdbarch *gdbarch, struct type *type,
948f8e3d 172 struct regcache *regcache, const gdb_byte *valbuf)
342ee437 173{
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174 int len = TYPE_LENGTH (type);
175 int reg, regsz;
176
177 if (TYPE_CODE (type) == TYPE_CODE_PTR)
178 reg = 4;
179 else
180 reg = 0;
181
182 regsz = register_size (gdbarch, reg);
183
184 if (len <= regsz)
185 regcache_raw_write_part (regcache, reg, 0, len, valbuf);
186 else if (len <= 2 * regsz)
187 {
188 regcache_raw_write (regcache, reg, valbuf);
189 gdb_assert (regsz == register_size (gdbarch, reg + 1));
190 regcache_raw_write_part (regcache, reg+1, 0,
948f8e3d 191 len - regsz, valbuf + regsz);
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192 }
193 else
194 internal_error (__FILE__, __LINE__,
195 _("Cannot store return value %d bytes long."), len);
196}
197
342ee437 198static void
99fe5f9d 199mn10300_extract_return_value (struct gdbarch *gdbarch, struct type *type,
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200 struct regcache *regcache, void *valbuf)
201{
b8b6e72f 202 gdb_byte buf[MN10300_MAX_REGISTER_SIZE];
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203 int len = TYPE_LENGTH (type);
204 int reg, regsz;
205
206 if (TYPE_CODE (type) == TYPE_CODE_PTR)
207 reg = 4;
208 else
209 reg = 0;
210
211 regsz = register_size (gdbarch, reg);
b8b6e72f 212 gdb_assert (regsz <= MN10300_MAX_REGISTER_SIZE);
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213 if (len <= regsz)
214 {
0b883586 215 regcache->raw_read (reg, buf);
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216 memcpy (valbuf, buf, len);
217 }
218 else if (len <= 2 * regsz)
219 {
0b883586 220 regcache->raw_read (reg, buf);
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221 memcpy (valbuf, buf, regsz);
222 gdb_assert (regsz == register_size (gdbarch, reg + 1));
0b883586 223 regcache->raw_read (reg + 1, buf);
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224 memcpy ((char *) valbuf + regsz, buf, len - regsz);
225 }
226 else
227 internal_error (__FILE__, __LINE__,
228 _("Cannot extract return value %d bytes long."), len);
229}
230
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231/* Determine, for architecture GDBARCH, how a return value of TYPE
232 should be returned. If it is supposed to be returned in registers,
233 and READBUF is non-zero, read the appropriate value from REGCACHE,
234 and copy it into READBUF. If WRITEBUF is non-zero, write the value
235 from WRITEBUF into REGCACHE. */
236
237static enum return_value_convention
6a3a010b 238mn10300_return_value (struct gdbarch *gdbarch, struct value *function,
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239 struct type *type, struct regcache *regcache,
240 gdb_byte *readbuf, const gdb_byte *writebuf)
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241{
242 if (mn10300_use_struct_convention (type))
243 return RETURN_VALUE_STRUCT_CONVENTION;
244
245 if (readbuf)
246 mn10300_extract_return_value (gdbarch, type, regcache, readbuf);
247 if (writebuf)
248 mn10300_store_return_value (gdbarch, type, regcache, writebuf);
249
250 return RETURN_VALUE_REGISTER_CONVENTION;
251}
252
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253static const char *
254register_name (int reg, const char **regs, long sizeof_regs)
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255{
256 if (reg < 0 || reg >= sizeof_regs / sizeof (regs[0]))
257 return NULL;
258 else
259 return regs[reg];
260}
261
262static const char *
d93859e2 263mn10300_generic_register_name (struct gdbarch *gdbarch, int reg)
342ee437 264{
a121b7c1 265 static const char *regs[] =
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266 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
267 "sp", "pc", "mdr", "psw", "lir", "lar", "", "",
268 "", "", "", "", "", "", "", "",
269 "", "", "", "", "", "", "", "fp"
270 };
271 return register_name (reg, regs, sizeof regs);
272}
273
274
275static const char *
d93859e2 276am33_register_name (struct gdbarch *gdbarch, int reg)
342ee437 277{
a121b7c1 278 static const char *regs[] =
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279 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
280 "sp", "pc", "mdr", "psw", "lir", "lar", "",
281 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
282 "ssp", "msp", "usp", "mcrh", "mcrl", "mcvf", "", "", ""
283 };
284 return register_name (reg, regs, sizeof regs);
285}
286
4640dd91 287static const char *
d93859e2 288am33_2_register_name (struct gdbarch *gdbarch, int reg)
4640dd91 289{
a121b7c1 290 static const char *regs[] =
4640dd91
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291 {
292 "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
293 "sp", "pc", "mdr", "psw", "lir", "lar", "mdrq", "r0",
294 "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ssp",
295 "msp", "usp", "mcrh", "mcrl", "mcvf", "fpcr", "", "",
296 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
297 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
298 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
299 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
300 };
301 return register_name (reg, regs, sizeof regs);
302}
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303
304static struct type *
305mn10300_register_type (struct gdbarch *gdbarch, int reg)
306{
0dfff4cb 307 return builtin_type (gdbarch)->builtin_int;
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308}
309
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310/* The breakpoint instruction must be the same size as the smallest
311 instruction in the instruction set.
312
313 The Matsushita mn10x00 processors have single byte instructions
314 so we need a single byte breakpoint. Matsushita hasn't defined
315 one, so we defined it ourselves. */
04180708 316constexpr gdb_byte mn10300_break_insn[] = {0xff};
342ee437 317
04180708 318typedef BP_MANIPULATION (mn10300_break_insn) mn10300_breakpoint;
342ee437 319
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320/* Model the semantics of pushing a register onto the stack. This
321 is a helper function for mn10300_analyze_prologue, below. */
322static void
323push_reg (pv_t *regs, struct pv_area *stack, int regnum)
324{
325 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4);
f7b7ed97 326 stack->store (regs[E_SP_REGNUM], 4, regs[regnum]);
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327}
328
329/* Translate an "r" register number extracted from an instruction encoding
330 into a GDB register number. Adapted from a simulator function
331 of the same name; see am33.igen. */
332static int
333translate_rreg (int rreg)
334{
335 /* The higher register numbers actually correspond to the
336 basic machine's address and data registers. */
337 if (rreg > 7 && rreg < 12)
338 return E_A0_REGNUM + rreg - 8;
339 else if (rreg > 11 && rreg < 16)
340 return E_D0_REGNUM + rreg - 12;
341 else
342 return E_E0_REGNUM + rreg;
343}
344
f7b7ed97 345/* Find saved registers in a 'struct pv_area'; we pass this to pv_area::scan.
9cacebf5 346
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347 If VALUE is a saved register, ADDR says it was saved at a constant
348 offset from the frame base, and SIZE indicates that the whole
349 register was saved, record its offset in RESULT_UNTYPED. */
9cacebf5 350static void
6c02c64c 351check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value)
9cacebf5 352{
6c02c64c 353 struct mn10300_prologue *result = (struct mn10300_prologue *) result_untyped;
9cacebf5 354
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355 if (value.kind == pvk_register
356 && value.k == 0
357 && pv_is_register (addr, E_SP_REGNUM)
d80b854b 358 && size == register_size (result->gdbarch, value.reg))
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359 result->reg_offset[value.reg] = addr.k;
360}
9cacebf5 361
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362/* Analyze the prologue to determine where registers are saved,
363 the end of the prologue, etc. The result of this analysis is
364 returned in RESULT. See struct mn10300_prologue above for more
365 information. */
366static void
367mn10300_analyze_prologue (struct gdbarch *gdbarch,
368 CORE_ADDR start_pc, CORE_ADDR limit_pc,
369 struct mn10300_prologue *result)
370{
e17a4113 371 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
22e048c9 372 CORE_ADDR pc;
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373 int rn;
374 pv_t regs[MN10300_MAX_NUM_REGS];
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375 CORE_ADDR after_last_frame_setup_insn = start_pc;
376 int am33_mode = AM33_MODE (gdbarch);
377
378 memset (result, 0, sizeof (*result));
d80b854b 379 result->gdbarch = gdbarch;
9cacebf5 380
6c02c64c 381 for (rn = 0; rn < MN10300_MAX_NUM_REGS; rn++)
4640dd91 382 {
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383 regs[rn] = pv_register (rn, 0);
384 result->reg_offset[rn] = 1;
4640dd91 385 }
f7b7ed97 386 pv_area stack (E_SP_REGNUM, gdbarch_addr_bit (gdbarch));
6c02c64c 387
f7b7ed97
TT
388 /* The typical call instruction will have saved the return address on the
389 stack. Space for the return address has already been preallocated in
390 the caller's frame. It's possible, such as when using -mrelax with gcc
391 that other registers were saved as well. If this happens, we really
392 have no chance of deciphering the frame. DWARF info can save the day
393 when this happens. */
394 stack.store (regs[E_SP_REGNUM], 4, regs[E_PC_REGNUM]);
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395
396 pc = start_pc;
397 while (pc < limit_pc)
4640dd91 398 {
6c02c64c
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399 int status;
400 gdb_byte instr[2];
4640dd91 401
6c02c64c
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402 /* Instructions can be as small as one byte; however, we usually
403 need at least two bytes to do the decoding, so fetch that many
404 to begin with. */
405 status = target_read_memory (pc, instr, 2);
406 if (status != 0)
407 break;
4640dd91 408
6c02c64c
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409 /* movm [regs], sp */
410 if (instr[0] == 0xcf)
4640dd91 411 {
6c02c64c
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412 gdb_byte save_mask;
413
414 save_mask = instr[1];
415
416 if ((save_mask & movm_exreg0_bit) && am33_mode)
417 {
f7b7ed97
TT
418 push_reg (regs, &stack, E_E2_REGNUM);
419 push_reg (regs, &stack, E_E3_REGNUM);
6c02c64c
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420 }
421 if ((save_mask & movm_exreg1_bit) && am33_mode)
4640dd91 422 {
f7b7ed97
TT
423 push_reg (regs, &stack, E_E4_REGNUM);
424 push_reg (regs, &stack, E_E5_REGNUM);
425 push_reg (regs, &stack, E_E6_REGNUM);
426 push_reg (regs, &stack, E_E7_REGNUM);
4640dd91 427 }
6c02c64c
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428 if ((save_mask & movm_exother_bit) && am33_mode)
429 {
f7b7ed97
TT
430 push_reg (regs, &stack, E_E0_REGNUM);
431 push_reg (regs, &stack, E_E1_REGNUM);
432 push_reg (regs, &stack, E_MDRQ_REGNUM);
433 push_reg (regs, &stack, E_MCRH_REGNUM);
434 push_reg (regs, &stack, E_MCRL_REGNUM);
435 push_reg (regs, &stack, E_MCVF_REGNUM);
6c02c64c
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436 }
437 if (save_mask & movm_d2_bit)
f7b7ed97 438 push_reg (regs, &stack, E_D2_REGNUM);
6c02c64c 439 if (save_mask & movm_d3_bit)
f7b7ed97 440 push_reg (regs, &stack, E_D3_REGNUM);
6c02c64c 441 if (save_mask & movm_a2_bit)
f7b7ed97 442 push_reg (regs, &stack, E_A2_REGNUM);
6c02c64c 443 if (save_mask & movm_a3_bit)
f7b7ed97 444 push_reg (regs, &stack, E_A3_REGNUM);
6c02c64c
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445 if (save_mask & movm_other_bit)
446 {
f7b7ed97
TT
447 push_reg (regs, &stack, E_D0_REGNUM);
448 push_reg (regs, &stack, E_D1_REGNUM);
449 push_reg (regs, &stack, E_A0_REGNUM);
450 push_reg (regs, &stack, E_A1_REGNUM);
451 push_reg (regs, &stack, E_MDR_REGNUM);
452 push_reg (regs, &stack, E_LIR_REGNUM);
453 push_reg (regs, &stack, E_LAR_REGNUM);
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454 /* The `other' bit leaves a blank area of four bytes at
455 the beginning of its block of saved registers, making
456 it 32 bytes long in total. */
457 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4);
458 }
459
460 pc += 2;
461 after_last_frame_setup_insn = pc;
4640dd91 462 }
6c02c64c
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463 /* mov sp, aN */
464 else if ((instr[0] & 0xfc) == 0x3c)
465 {
466 int aN = instr[0] & 0x03;
4640dd91 467
6c02c64c 468 regs[E_A0_REGNUM + aN] = regs[E_SP_REGNUM];
4640dd91 469
6c02c64c
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470 pc += 1;
471 if (aN == 3)
472 after_last_frame_setup_insn = pc;
473 }
474 /* mov aM, aN */
475 else if ((instr[0] & 0xf0) == 0x90
476 && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2))
477 {
478 int aN = instr[0] & 0x03;
479 int aM = (instr[0] & 0x0c) >> 2;
9cacebf5 480
6c02c64c 481 regs[E_A0_REGNUM + aN] = regs[E_A0_REGNUM + aM];
9cacebf5 482
6c02c64c
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483 pc += 1;
484 }
485 /* mov dM, dN */
486 else if ((instr[0] & 0xf0) == 0x80
487 && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2))
488 {
489 int dN = instr[0] & 0x03;
490 int dM = (instr[0] & 0x0c) >> 2;
9cacebf5 491
6c02c64c 492 regs[E_D0_REGNUM + dN] = regs[E_D0_REGNUM + dM];
9cacebf5 493
6c02c64c
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494 pc += 1;
495 }
496 /* mov aM, dN */
497 else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xd0)
498 {
499 int dN = instr[1] & 0x03;
500 int aM = (instr[1] & 0x0c) >> 2;
9cacebf5 501
6c02c64c 502 regs[E_D0_REGNUM + dN] = regs[E_A0_REGNUM + aM];
9cacebf5 503
6c02c64c
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504 pc += 2;
505 }
506 /* mov dM, aN */
507 else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xe0)
508 {
509 int aN = instr[1] & 0x03;
510 int dM = (instr[1] & 0x0c) >> 2;
9cacebf5 511
6c02c64c 512 regs[E_A0_REGNUM + aN] = regs[E_D0_REGNUM + dM];
9cacebf5 513
6c02c64c
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514 pc += 2;
515 }
516 /* add imm8, SP */
517 else if (instr[0] == 0xf8 && instr[1] == 0xfe)
518 {
519 gdb_byte buf[1];
520 LONGEST imm8;
9cacebf5 521
9cacebf5 522
6c02c64c
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523 status = target_read_memory (pc + 2, buf, 1);
524 if (status != 0)
525 break;
9cacebf5 526
e17a4113 527 imm8 = extract_signed_integer (buf, 1, byte_order);
6c02c64c 528 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm8);
9cacebf5 529
6c02c64c
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530 pc += 3;
531 /* Stack pointer adjustments are frame related. */
532 after_last_frame_setup_insn = pc;
533 }
534 /* add imm16, SP */
535 else if (instr[0] == 0xfa && instr[1] == 0xfe)
536 {
537 gdb_byte buf[2];
538 LONGEST imm16;
9cacebf5 539
6c02c64c
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540 status = target_read_memory (pc + 2, buf, 2);
541 if (status != 0)
542 break;
9cacebf5 543
e17a4113 544 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c 545 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm16);
9cacebf5 546
6c02c64c
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547 pc += 4;
548 /* Stack pointer adjustments are frame related. */
549 after_last_frame_setup_insn = pc;
550 }
551 /* add imm32, SP */
552 else if (instr[0] == 0xfc && instr[1] == 0xfe)
553 {
554 gdb_byte buf[4];
555 LONGEST imm32;
9cacebf5 556
6c02c64c
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557 status = target_read_memory (pc + 2, buf, 4);
558 if (status != 0)
559 break;
9cacebf5 560
9cacebf5 561
e17a4113 562 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c 563 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm32);
9cacebf5 564
6c02c64c
KB
565 pc += 6;
566 /* Stack pointer adjustments are frame related. */
567 after_last_frame_setup_insn = pc;
568 }
569 /* add imm8, aN */
570 else if ((instr[0] & 0xfc) == 0x20)
571 {
572 int aN;
573 LONGEST imm8;
9cacebf5 574
6c02c64c 575 aN = instr[0] & 0x03;
e17a4113 576 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
9cacebf5 577
6c02c64c
KB
578 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
579 imm8);
9cacebf5 580
6c02c64c
KB
581 pc += 2;
582 }
583 /* add imm16, aN */
584 else if (instr[0] == 0xfa && (instr[1] & 0xfc) == 0xd0)
585 {
586 int aN;
587 LONGEST imm16;
588 gdb_byte buf[2];
9cacebf5 589
6c02c64c 590 aN = instr[1] & 0x03;
9cacebf5 591
6c02c64c
KB
592 status = target_read_memory (pc + 2, buf, 2);
593 if (status != 0)
594 break;
9cacebf5 595
9cacebf5 596
e17a4113 597 imm16 = extract_signed_integer (buf, 2, byte_order);
9cacebf5 598
6c02c64c
KB
599 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
600 imm16);
9cacebf5 601
6c02c64c
KB
602 pc += 4;
603 }
604 /* add imm32, aN */
605 else if (instr[0] == 0xfc && (instr[1] & 0xfc) == 0xd0)
606 {
607 int aN;
608 LONGEST imm32;
609 gdb_byte buf[4];
9cacebf5 610
6c02c64c 611 aN = instr[1] & 0x03;
9cacebf5 612
6c02c64c
KB
613 status = target_read_memory (pc + 2, buf, 4);
614 if (status != 0)
615 break;
9cacebf5 616
e17a4113 617 imm32 = extract_signed_integer (buf, 2, byte_order);
9cacebf5 618
6c02c64c
KB
619 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
620 imm32);
621 pc += 6;
622 }
623 /* fmov fsM, (rN) */
624 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x30)
625 {
626 int fsM, sM, Y, rN;
627 gdb_byte buf[1];
9cacebf5 628
6c02c64c 629 Y = (instr[1] & 0x02) >> 1;
9cacebf5 630
6c02c64c
KB
631 status = target_read_memory (pc + 2, buf, 1);
632 if (status != 0)
633 break;
9cacebf5 634
6c02c64c
KB
635 sM = (buf[0] & 0xf0) >> 4;
636 rN = buf[0] & 0x0f;
637 fsM = (Y << 4) | sM;
9cacebf5 638
f7b7ed97
TT
639 stack.store (regs[translate_rreg (rN)], 4,
640 regs[E_FS0_REGNUM + fsM]);
9cacebf5 641
6c02c64c
KB
642 pc += 3;
643 }
644 /* fmov fsM, (sp) */
645 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x34)
646 {
647 int fsM, sM, Y;
648 gdb_byte buf[1];
9cacebf5 649
6c02c64c 650 Y = (instr[1] & 0x02) >> 1;
9cacebf5 651
6c02c64c
KB
652 status = target_read_memory (pc + 2, buf, 1);
653 if (status != 0)
654 break;
9cacebf5 655
6c02c64c
KB
656 sM = (buf[0] & 0xf0) >> 4;
657 fsM = (Y << 4) | sM;
9cacebf5 658
f7b7ed97
TT
659 stack.store (regs[E_SP_REGNUM], 4,
660 regs[E_FS0_REGNUM + fsM]);
9cacebf5 661
6c02c64c
KB
662 pc += 3;
663 }
664 /* fmov fsM, (rN, rI) */
665 else if (instr[0] == 0xfb && instr[1] == 0x37)
666 {
667 int fsM, sM, Z, rN, rI;
668 gdb_byte buf[2];
9cacebf5 669
9cacebf5 670
6c02c64c
KB
671 status = target_read_memory (pc + 2, buf, 2);
672 if (status != 0)
673 break;
83845630 674
6c02c64c
KB
675 rI = (buf[0] & 0xf0) >> 4;
676 rN = buf[0] & 0x0f;
677 sM = (buf[1] & 0xf0) >> 4;
678 Z = (buf[1] & 0x02) >> 1;
679 fsM = (Z << 4) | sM;
83845630 680
f7b7ed97
TT
681 stack.store (pv_add (regs[translate_rreg (rN)],
682 regs[translate_rreg (rI)]),
683 4, regs[E_FS0_REGNUM + fsM]);
83845630 684
6c02c64c
KB
685 pc += 4;
686 }
687 /* fmov fsM, (d8, rN) */
688 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x30)
4640dd91 689 {
6c02c64c
KB
690 int fsM, sM, Y, rN;
691 LONGEST d8;
692 gdb_byte buf[2];
693
694 Y = (instr[1] & 0x02) >> 1;
695
696 status = target_read_memory (pc + 2, buf, 2);
697 if (status != 0)
698 break;
699
700 sM = (buf[0] & 0xf0) >> 4;
701 rN = buf[0] & 0x0f;
702 fsM = (Y << 4) | sM;
e17a4113 703 d8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c 704
f7b7ed97
TT
705 stack.store (pv_add_constant (regs[translate_rreg (rN)], d8),
706 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
707
708 pc += 4;
4640dd91 709 }
6c02c64c
KB
710 /* fmov fsM, (d24, rN) */
711 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x30)
83845630 712 {
6c02c64c
KB
713 int fsM, sM, Y, rN;
714 LONGEST d24;
715 gdb_byte buf[4];
716
717 Y = (instr[1] & 0x02) >> 1;
718
719 status = target_read_memory (pc + 2, buf, 4);
83845630 720 if (status != 0)
6c02c64c
KB
721 break;
722
723 sM = (buf[0] & 0xf0) >> 4;
724 rN = buf[0] & 0x0f;
725 fsM = (Y << 4) | sM;
e17a4113 726 d24 = extract_signed_integer (&buf[1], 3, byte_order);
6c02c64c 727
f7b7ed97
TT
728 stack.store (pv_add_constant (regs[translate_rreg (rN)], d24),
729 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
730
731 pc += 6;
83845630 732 }
6c02c64c
KB
733 /* fmov fsM, (d32, rN) */
734 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x30)
735 {
736 int fsM, sM, Y, rN;
737 LONGEST d32;
738 gdb_byte buf[5];
4640dd91 739
6c02c64c
KB
740 Y = (instr[1] & 0x02) >> 1;
741
742 status = target_read_memory (pc + 2, buf, 5);
743 if (status != 0)
744 break;
745
746 sM = (buf[0] & 0xf0) >> 4;
747 rN = buf[0] & 0x0f;
748 fsM = (Y << 4) | sM;
e17a4113 749 d32 = extract_signed_integer (&buf[1], 4, byte_order);
9cacebf5 750
f7b7ed97
TT
751 stack.store (pv_add_constant (regs[translate_rreg (rN)], d32),
752 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
753
754 pc += 7;
755 }
756 /* fmov fsM, (d8, SP) */
757 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x34)
9cacebf5 758 {
6c02c64c
KB
759 int fsM, sM, Y;
760 LONGEST d8;
761 gdb_byte buf[2];
762
763 Y = (instr[1] & 0x02) >> 1;
764
765 status = target_read_memory (pc + 2, buf, 2);
766 if (status != 0)
767 break;
768
769 sM = (buf[0] & 0xf0) >> 4;
770 fsM = (Y << 4) | sM;
e17a4113 771 d8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c 772
f7b7ed97
TT
773 stack.store (pv_add_constant (regs[E_SP_REGNUM], d8),
774 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
775
776 pc += 4;
9cacebf5 777 }
6c02c64c
KB
778 /* fmov fsM, (d24, SP) */
779 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x34)
780 {
781 int fsM, sM, Y;
782 LONGEST d24;
783 gdb_byte buf[4];
9cacebf5 784
6c02c64c 785 Y = (instr[1] & 0x02) >> 1;
9cacebf5 786
6c02c64c
KB
787 status = target_read_memory (pc + 2, buf, 4);
788 if (status != 0)
789 break;
9cacebf5 790
6c02c64c
KB
791 sM = (buf[0] & 0xf0) >> 4;
792 fsM = (Y << 4) | sM;
e17a4113 793 d24 = extract_signed_integer (&buf[1], 3, byte_order);
9cacebf5 794
f7b7ed97
TT
795 stack.store (pv_add_constant (regs[E_SP_REGNUM], d24),
796 4, regs[E_FS0_REGNUM + fsM]);
9cacebf5 797
6c02c64c
KB
798 pc += 6;
799 }
800 /* fmov fsM, (d32, SP) */
801 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x34)
802 {
803 int fsM, sM, Y;
804 LONGEST d32;
805 gdb_byte buf[5];
9cacebf5 806
6c02c64c 807 Y = (instr[1] & 0x02) >> 1;
9cacebf5 808
6c02c64c
KB
809 status = target_read_memory (pc + 2, buf, 5);
810 if (status != 0)
811 break;
812
813 sM = (buf[0] & 0xf0) >> 4;
814 fsM = (Y << 4) | sM;
e17a4113 815 d32 = extract_signed_integer (&buf[1], 4, byte_order);
6c02c64c 816
f7b7ed97
TT
817 stack.store (pv_add_constant (regs[E_SP_REGNUM], d32),
818 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
819
820 pc += 7;
821 }
822 /* fmov fsM, (rN+) */
823 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x31)
824 {
825 int fsM, sM, Y, rN, rN_regnum;
826 gdb_byte buf[1];
827
828 Y = (instr[1] & 0x02) >> 1;
829
830 status = target_read_memory (pc + 2, buf, 1);
831 if (status != 0)
832 break;
833
834 sM = (buf[0] & 0xf0) >> 4;
835 rN = buf[0] & 0x0f;
836 fsM = (Y << 4) | sM;
837
838 rN_regnum = translate_rreg (rN);
839
f7b7ed97
TT
840 stack.store (regs[rN_regnum], 4,
841 regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
842 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], 4);
843
844 pc += 3;
845 }
846 /* fmov fsM, (rN+, imm8) */
847 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x31)
848 {
849 int fsM, sM, Y, rN, rN_regnum;
850 LONGEST imm8;
851 gdb_byte buf[2];
852
853 Y = (instr[1] & 0x02) >> 1;
854
855 status = target_read_memory (pc + 2, buf, 2);
856 if (status != 0)
857 break;
858
859 sM = (buf[0] & 0xf0) >> 4;
860 rN = buf[0] & 0x0f;
861 fsM = (Y << 4) | sM;
e17a4113 862 imm8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c
KB
863
864 rN_regnum = translate_rreg (rN);
865
f7b7ed97 866 stack.store (regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
867 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm8);
868
869 pc += 4;
870 }
871 /* fmov fsM, (rN+, imm24) */
872 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x31)
873 {
874 int fsM, sM, Y, rN, rN_regnum;
875 LONGEST imm24;
876 gdb_byte buf[4];
877
878 Y = (instr[1] & 0x02) >> 1;
879
880 status = target_read_memory (pc + 2, buf, 4);
881 if (status != 0)
882 break;
883
884 sM = (buf[0] & 0xf0) >> 4;
885 rN = buf[0] & 0x0f;
886 fsM = (Y << 4) | sM;
e17a4113 887 imm24 = extract_signed_integer (&buf[1], 3, byte_order);
6c02c64c
KB
888
889 rN_regnum = translate_rreg (rN);
890
f7b7ed97 891 stack.store (regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
892 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm24);
893
894 pc += 6;
895 }
896 /* fmov fsM, (rN+, imm32) */
897 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x31)
898 {
899 int fsM, sM, Y, rN, rN_regnum;
900 LONGEST imm32;
901 gdb_byte buf[5];
902
903 Y = (instr[1] & 0x02) >> 1;
904
905 status = target_read_memory (pc + 2, buf, 5);
906 if (status != 0)
907 break;
908
909 sM = (buf[0] & 0xf0) >> 4;
910 rN = buf[0] & 0x0f;
911 fsM = (Y << 4) | sM;
e17a4113 912 imm32 = extract_signed_integer (&buf[1], 4, byte_order);
6c02c64c
KB
913
914 rN_regnum = translate_rreg (rN);
915
f7b7ed97 916 stack.store (regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
6c02c64c
KB
917 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm32);
918
919 pc += 7;
920 }
921 /* mov imm8, aN */
922 else if ((instr[0] & 0xf0) == 0x90)
923 {
924 int aN = instr[0] & 0x03;
925 LONGEST imm8;
9cacebf5 926
e17a4113 927 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
9cacebf5 928
6c02c64c
KB
929 regs[E_A0_REGNUM + aN] = pv_constant (imm8);
930 pc += 2;
931 }
932 /* mov imm16, aN */
933 else if ((instr[0] & 0xfc) == 0x24)
934 {
935 int aN = instr[0] & 0x03;
936 gdb_byte buf[2];
937 LONGEST imm16;
938
939 status = target_read_memory (pc + 1, buf, 2);
940 if (status != 0)
941 break;
942
e17a4113 943 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c
KB
944 regs[E_A0_REGNUM + aN] = pv_constant (imm16);
945 pc += 3;
946 }
947 /* mov imm32, aN */
948 else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xdc))
949 {
950 int aN = instr[1] & 0x03;
951 gdb_byte buf[4];
952 LONGEST imm32;
953
954 status = target_read_memory (pc + 2, buf, 4);
955 if (status != 0)
956 break;
957
e17a4113 958 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c
KB
959 regs[E_A0_REGNUM + aN] = pv_constant (imm32);
960 pc += 6;
961 }
962 /* mov imm8, dN */
963 else if ((instr[0] & 0xf0) == 0x80)
964 {
965 int dN = instr[0] & 0x03;
966 LONGEST imm8;
967
e17a4113 968 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
6c02c64c
KB
969
970 regs[E_D0_REGNUM + dN] = pv_constant (imm8);
971 pc += 2;
972 }
973 /* mov imm16, dN */
974 else if ((instr[0] & 0xfc) == 0x2c)
975 {
976 int dN = instr[0] & 0x03;
977 gdb_byte buf[2];
978 LONGEST imm16;
979
980 status = target_read_memory (pc + 1, buf, 2);
981 if (status != 0)
982 break;
983
e17a4113 984 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c
KB
985 regs[E_D0_REGNUM + dN] = pv_constant (imm16);
986 pc += 3;
987 }
988 /* mov imm32, dN */
989 else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xcc))
990 {
991 int dN = instr[1] & 0x03;
992 gdb_byte buf[4];
993 LONGEST imm32;
994
995 status = target_read_memory (pc + 2, buf, 4);
996 if (status != 0)
997 break;
998
e17a4113 999 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c
KB
1000 regs[E_D0_REGNUM + dN] = pv_constant (imm32);
1001 pc += 6;
1002 }
1003 else
1004 {
1005 /* We've hit some instruction that we don't recognize. Hopefully,
1006 we have enough to do prologue analysis. */
1007 break;
1008 }
1009 }
1010
1011 /* Is the frame size (offset, really) a known constant? */
1012 if (pv_is_register (regs[E_SP_REGNUM], E_SP_REGNUM))
1013 result->frame_size = regs[E_SP_REGNUM].k;
9cacebf5 1014
6c02c64c
KB
1015 /* Was the frame pointer initialized? */
1016 if (pv_is_register (regs[E_A3_REGNUM], E_SP_REGNUM))
1017 {
1018 result->has_frame_ptr = 1;
1019 result->frame_ptr_offset = regs[E_A3_REGNUM].k;
9cacebf5 1020 }
6c02c64c
KB
1021
1022 /* Record where all the registers were saved. */
f7b7ed97 1023 stack.scan (check_for_saved, (void *) result);
6c02c64c
KB
1024
1025 result->prologue_end = after_last_frame_setup_insn;
9cacebf5
MS
1026}
1027
342ee437
MS
1028/* Function: skip_prologue
1029 Return the address of the first inst past the prologue of the function. */
1030
1031static CORE_ADDR
6093d2eb 1032mn10300_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
342ee437 1033{
2c02bd72 1034 const char *name;
6c02c64c
KB
1035 CORE_ADDR func_addr, func_end;
1036 struct mn10300_prologue p;
1037
1038 /* Try to find the extent of the function that contains PC. */
1039 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1040 return pc;
1041
1042 mn10300_analyze_prologue (gdbarch, pc, func_end, &p);
1043 return p.prologue_end;
342ee437
MS
1044}
1045
6c02c64c
KB
1046/* Wrapper for mn10300_analyze_prologue: find the function start;
1047 use the current frame PC as the limit, then
1048 invoke mn10300_analyze_prologue and return its result. */
1049static struct mn10300_prologue *
1050mn10300_analyze_frame_prologue (struct frame_info *this_frame,
1051 void **this_prologue_cache)
342ee437 1052{
6c02c64c 1053 if (!*this_prologue_cache)
93d42b30 1054 {
6c02c64c
KB
1055 CORE_ADDR func_start, stop_addr;
1056
1057 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct mn10300_prologue);
1058
1059 func_start = get_frame_func (this_frame);
1060 stop_addr = get_frame_pc (this_frame);
1061
1062 /* If we couldn't find any function containing the PC, then
1063 just initialize the prologue cache, but don't do anything. */
1064 if (!func_start)
1065 stop_addr = func_start;
1066
1067 mn10300_analyze_prologue (get_frame_arch (this_frame),
19ba03f4
SM
1068 func_start, stop_addr,
1069 ((struct mn10300_prologue *)
1070 *this_prologue_cache));
93d42b30 1071 }
342ee437 1072
19ba03f4 1073 return (struct mn10300_prologue *) *this_prologue_cache;
6c02c64c
KB
1074}
1075
1076/* Given the next frame and a prologue cache, return this frame's
1077 base. */
1078static CORE_ADDR
1079mn10300_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
1080{
1081 struct mn10300_prologue *p
1082 = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache);
1083
1084 /* In functions that use alloca, the distance between the stack
1085 pointer and the frame base varies dynamically, so we can't use
1086 the SP plus static information like prologue analysis to find the
1087 frame base. However, such functions must have a frame pointer,
1088 to be able to restore the SP on exit. So whenever we do have a
1089 frame pointer, use that to find the base. */
1090 if (p->has_frame_ptr)
1091 {
1092 CORE_ADDR fp = get_frame_register_unsigned (this_frame, E_A3_REGNUM);
1093 return fp - p->frame_ptr_offset;
1094 }
1095 else
1096 {
1097 CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1098 return sp - p->frame_size;
1099 }
342ee437
MS
1100}
1101
1102/* Here is a dummy implementation. */
1103static struct frame_id
94afd7a6 1104mn10300_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
342ee437 1105{
94afd7a6
UW
1106 CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1107 CORE_ADDR pc = get_frame_register_unsigned (this_frame, E_PC_REGNUM);
1108 return frame_id_build (sp, pc);
342ee437
MS
1109}
1110
342ee437 1111static void
94afd7a6 1112mn10300_frame_this_id (struct frame_info *this_frame,
342ee437
MS
1113 void **this_prologue_cache,
1114 struct frame_id *this_id)
1115{
025bb325
MS
1116 *this_id = frame_id_build (mn10300_frame_base (this_frame,
1117 this_prologue_cache),
6c02c64c 1118 get_frame_func (this_frame));
342ee437 1119
342ee437
MS
1120}
1121
94afd7a6
UW
1122static struct value *
1123mn10300_frame_prev_register (struct frame_info *this_frame,
6c02c64c 1124 void **this_prologue_cache, int regnum)
342ee437 1125{
6c02c64c
KB
1126 struct mn10300_prologue *p
1127 = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache);
1128 CORE_ADDR frame_base = mn10300_frame_base (this_frame, this_prologue_cache);
6c02c64c
KB
1129
1130 if (regnum == E_SP_REGNUM)
1131 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1132
1133 /* If prologue analysis says we saved this register somewhere,
1134 return a description of the stack slot holding it. */
1135 if (p->reg_offset[regnum] != 1)
1136 return frame_unwind_got_memory (this_frame, regnum,
1137 frame_base + p->reg_offset[regnum]);
1138
1139 /* Otherwise, presume we haven't changed the value of this
1140 register, and get it from the next frame. */
1141 return frame_unwind_got_register (this_frame, regnum, regnum);
342ee437
MS
1142}
1143
1144static const struct frame_unwind mn10300_frame_unwind = {
1145 NORMAL_FRAME,
8fbca658 1146 default_frame_unwind_stop_reason,
342ee437 1147 mn10300_frame_this_id,
94afd7a6
UW
1148 mn10300_frame_prev_register,
1149 NULL,
1150 default_frame_sniffer
342ee437
MS
1151};
1152
1153static CORE_ADDR
6c02c64c 1154mn10300_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
342ee437
MS
1155{
1156 ULONGEST pc;
1157
6c02c64c 1158 pc = frame_unwind_register_unsigned (this_frame, E_PC_REGNUM);
342ee437
MS
1159 return pc;
1160}
1161
1162static CORE_ADDR
6c02c64c 1163mn10300_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
342ee437
MS
1164{
1165 ULONGEST sp;
1166
6c02c64c 1167 sp = frame_unwind_register_unsigned (this_frame, E_SP_REGNUM);
342ee437
MS
1168 return sp;
1169}
1170
1171static void
1172mn10300_frame_unwind_init (struct gdbarch *gdbarch)
1173{
94afd7a6
UW
1174 dwarf2_append_unwinders (gdbarch);
1175 frame_unwind_append_unwinder (gdbarch, &mn10300_frame_unwind);
94afd7a6 1176 set_gdbarch_dummy_id (gdbarch, mn10300_dummy_id);
342ee437
MS
1177 set_gdbarch_unwind_pc (gdbarch, mn10300_unwind_pc);
1178 set_gdbarch_unwind_sp (gdbarch, mn10300_unwind_sp);
1179}
1180
1181/* Function: push_dummy_call
1182 *
1183 * Set up machine state for a target call, including
1184 * function arguments, stack, return address, etc.
1185 *
1186 */
1187
1188static CORE_ADDR
1189mn10300_push_dummy_call (struct gdbarch *gdbarch,
1190 struct value *target_func,
1191 struct regcache *regcache,
1192 CORE_ADDR bp_addr,
1193 int nargs, struct value **args,
1194 CORE_ADDR sp,
1195 int struct_return,
1196 CORE_ADDR struct_addr)
1197{
e17a4113 1198 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
342ee437 1199 const int push_size = register_size (gdbarch, E_PC_REGNUM);
1fb1ca27 1200 int regs_used;
342ee437
MS
1201 int len, arg_len;
1202 int stack_offset = 0;
1203 int argnum;
948f8e3d 1204 const gdb_byte *val;
b8b6e72f 1205 gdb_byte valbuf[MN10300_MAX_REGISTER_SIZE];
342ee437 1206
342ee437
MS
1207 /* This should be a nop, but align the stack just in case something
1208 went wrong. Stacks are four byte aligned on the mn10300. */
1209 sp &= ~3;
1210
1211 /* Now make space on the stack for the args.
1212
1213 XXX This doesn't appear to handle pass-by-invisible reference
1214 arguments. */
1fb1ca27 1215 regs_used = struct_return ? 1 : 0;
342ee437
MS
1216 for (len = 0, argnum = 0; argnum < nargs; argnum++)
1217 {
1218 arg_len = (TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3;
342ee437
MS
1219 while (regs_used < 2 && arg_len > 0)
1220 {
1221 regs_used++;
1222 arg_len -= push_size;
1223 }
1224 len += arg_len;
1225 }
1226
1227 /* Allocate stack space. */
1228 sp -= len;
1229
1fb1ca27
MS
1230 if (struct_return)
1231 {
1232 regs_used = 1;
9c9acae0 1233 regcache_cooked_write_unsigned (regcache, E_D0_REGNUM, struct_addr);
1fb1ca27
MS
1234 }
1235 else
1236 regs_used = 0;
1237
025bb325 1238 /* Push all arguments onto the stack. */
342ee437
MS
1239 for (argnum = 0; argnum < nargs; argnum++)
1240 {
1fb1ca27
MS
1241 /* FIXME what about structs? Unions? */
1242 if (TYPE_CODE (value_type (*args)) == TYPE_CODE_STRUCT
1243 && TYPE_LENGTH (value_type (*args)) > 8)
1244 {
1245 /* Change to pointer-to-type. */
1246 arg_len = push_size;
b8b6e72f 1247 gdb_assert (push_size <= MN10300_MAX_REGISTER_SIZE);
e17a4113 1248 store_unsigned_integer (valbuf, push_size, byte_order,
42ae5230 1249 value_address (*args));
1fb1ca27
MS
1250 val = &valbuf[0];
1251 }
1252 else
1253 {
1254 arg_len = TYPE_LENGTH (value_type (*args));
948f8e3d 1255 val = value_contents (*args);
1fb1ca27 1256 }
342ee437
MS
1257
1258 while (regs_used < 2 && arg_len > 0)
1259 {
9c9acae0 1260 regcache_cooked_write_unsigned (regcache, regs_used,
e17a4113 1261 extract_unsigned_integer (val, push_size, byte_order));
342ee437
MS
1262 val += push_size;
1263 arg_len -= push_size;
1264 regs_used++;
1265 }
1266
1267 while (arg_len > 0)
1268 {
1269 write_memory (sp + stack_offset, val, push_size);
1270 arg_len -= push_size;
1271 val += push_size;
1272 stack_offset += push_size;
1273 }
1274
1275 args++;
1276 }
1277
1278 /* Make space for the flushback area. */
1279 sp -= 8;
1280
1281 /* Push the return address that contains the magic breakpoint. */
1282 sp -= 4;
e17a4113 1283 write_memory_unsigned_integer (sp, push_size, byte_order, bp_addr);
a64ae7e0
CV
1284
1285 /* The CPU also writes the return address always into the
1286 MDR register on "call". */
1287 regcache_cooked_write_unsigned (regcache, E_MDR_REGNUM, bp_addr);
1288
342ee437
MS
1289 /* Update $sp. */
1290 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
ee3a2f01
KB
1291
1292 /* On the mn10300, it's possible to move some of the stack adjustment
1293 and saving of the caller-save registers out of the prologue and
1294 into the call sites. (When using gcc, this optimization can
1295 occur when using the -mrelax switch.) If this occurs, the dwarf2
1296 info will reflect this fact. We can test to see if this is the
1297 case by creating a new frame using the current stack pointer and
1298 the address of the function that we're about to call. We then
1299 unwind SP and see if it's different than the SP of our newly
1300 created frame. If the SP values are the same, the caller is not
1301 expected to allocate any additional stack. On the other hand, if
1302 the SP values are different, the difference determines the
1303 additional stack that must be allocated.
1304
1305 Note that we don't update the return value though because that's
1306 the value of the stack just after pushing the arguments, but prior
1307 to performing the call. This value is needed in order to
025bb325 1308 construct the frame ID of the dummy call. */
ee3a2f01
KB
1309 {
1310 CORE_ADDR func_addr = find_function_addr (target_func, NULL);
1311 CORE_ADDR unwound_sp
1312 = mn10300_unwind_sp (gdbarch, create_new_frame (sp, func_addr));
1313 if (sp != unwound_sp)
1314 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM,
1315 sp - (unwound_sp - sp));
1316 }
1317
342ee437
MS
1318 return sp;
1319}
1320
336c28c5
KB
1321/* If DWARF2 is a register number appearing in Dwarf2 debug info, then
1322 mn10300_dwarf2_reg_to_regnum (DWARF2) is the corresponding GDB
1323 register number. Why don't Dwarf2 and GDB use the same numbering?
1324 Who knows? But since people have object files lying around with
1325 the existing Dwarf2 numbering, and other people have written stubs
1326 to work with the existing GDB, neither of them can change. So we
1327 just have to cope. */
1328static int
be8626e0 1329mn10300_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int dwarf2)
336c28c5 1330{
c9f4d572 1331 /* This table is supposed to be shaped like the gdbarch_register_name
336c28c5
KB
1332 initializer in gcc/config/mn10300/mn10300.h. Registers which
1333 appear in GCC's numbering, but have no counterpart in GDB's
1334 world, are marked with a -1. */
1335 static int dwarf2_to_gdb[] = {
c5bb7362
KB
1336 E_D0_REGNUM, E_D1_REGNUM, E_D2_REGNUM, E_D3_REGNUM,
1337 E_A0_REGNUM, E_A1_REGNUM, E_A2_REGNUM, E_A3_REGNUM,
1338 -1, E_SP_REGNUM,
1339
1340 E_E0_REGNUM, E_E1_REGNUM, E_E2_REGNUM, E_E3_REGNUM,
1341 E_E4_REGNUM, E_E5_REGNUM, E_E6_REGNUM, E_E7_REGNUM,
1342
1343 E_FS0_REGNUM + 0, E_FS0_REGNUM + 1, E_FS0_REGNUM + 2, E_FS0_REGNUM + 3,
1344 E_FS0_REGNUM + 4, E_FS0_REGNUM + 5, E_FS0_REGNUM + 6, E_FS0_REGNUM + 7,
1345
1346 E_FS0_REGNUM + 8, E_FS0_REGNUM + 9, E_FS0_REGNUM + 10, E_FS0_REGNUM + 11,
1347 E_FS0_REGNUM + 12, E_FS0_REGNUM + 13, E_FS0_REGNUM + 14, E_FS0_REGNUM + 15,
1348
1349 E_FS0_REGNUM + 16, E_FS0_REGNUM + 17, E_FS0_REGNUM + 18, E_FS0_REGNUM + 19,
1350 E_FS0_REGNUM + 20, E_FS0_REGNUM + 21, E_FS0_REGNUM + 22, E_FS0_REGNUM + 23,
1351
1352 E_FS0_REGNUM + 24, E_FS0_REGNUM + 25, E_FS0_REGNUM + 26, E_FS0_REGNUM + 27,
1353 E_FS0_REGNUM + 28, E_FS0_REGNUM + 29, E_FS0_REGNUM + 30, E_FS0_REGNUM + 31,
1354
1355 E_MDR_REGNUM, E_PSW_REGNUM, E_PC_REGNUM
336c28c5
KB
1356 };
1357
1358 if (dwarf2 < 0
bbc1a784 1359 || dwarf2 >= ARRAY_SIZE (dwarf2_to_gdb))
0fde2c53 1360 return -1;
336c28c5
KB
1361
1362 return dwarf2_to_gdb[dwarf2];
1363}
342ee437
MS
1364
1365static struct gdbarch *
1366mn10300_gdbarch_init (struct gdbarch_info info,
1367 struct gdbarch_list *arches)
1368{
1369 struct gdbarch *gdbarch;
1370 struct gdbarch_tdep *tdep;
4640dd91 1371 int num_regs;
342ee437
MS
1372
1373 arches = gdbarch_list_lookup_by_info (arches, &info);
1374 if (arches != NULL)
1375 return arches->gdbarch;
1376
cdd238da 1377 tdep = XCNEW (struct gdbarch_tdep);
342ee437
MS
1378 gdbarch = gdbarch_alloc (&info, tdep);
1379
1380 switch (info.bfd_arch_info->mach)
1381 {
1382 case 0:
1383 case bfd_mach_mn10300:
1384 set_gdbarch_register_name (gdbarch, mn10300_generic_register_name);
1385 tdep->am33_mode = 0;
4640dd91 1386 num_regs = 32;
342ee437
MS
1387 break;
1388 case bfd_mach_am33:
1389 set_gdbarch_register_name (gdbarch, am33_register_name);
1390 tdep->am33_mode = 1;
4640dd91
KB
1391 num_regs = 32;
1392 break;
1393 case bfd_mach_am33_2:
1394 set_gdbarch_register_name (gdbarch, am33_2_register_name);
1395 tdep->am33_mode = 2;
1396 num_regs = 64;
1397 set_gdbarch_fp0_regnum (gdbarch, 32);
342ee437
MS
1398 break;
1399 default:
1400 internal_error (__FILE__, __LINE__,
1401 _("mn10300_gdbarch_init: Unknown mn10300 variant"));
1402 break;
1403 }
1404
1b31f75d
KB
1405 /* By default, chars are unsigned. */
1406 set_gdbarch_char_signed (gdbarch, 0);
1407
342ee437 1408 /* Registers. */
4640dd91 1409 set_gdbarch_num_regs (gdbarch, num_regs);
342ee437
MS
1410 set_gdbarch_register_type (gdbarch, mn10300_register_type);
1411 set_gdbarch_skip_prologue (gdbarch, mn10300_skip_prologue);
342ee437
MS
1412 set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1413 set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
336c28c5 1414 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mn10300_dwarf2_reg_to_regnum);
342ee437
MS
1415
1416 /* Stack unwinding. */
1417 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1418 /* Breakpoints. */
04180708
YQ
1419 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
1420 mn10300_breakpoint::kind_from_pc);
1421 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
1422 mn10300_breakpoint::bp_from_kind);
025bb325 1423 /* decr_pc_after_break? */
342ee437
MS
1424
1425 /* Stage 2 */
99fe5f9d 1426 set_gdbarch_return_value (gdbarch, mn10300_return_value);
342ee437
MS
1427
1428 /* Stage 3 -- get target calls working. */
1429 set_gdbarch_push_dummy_call (gdbarch, mn10300_push_dummy_call);
1430 /* set_gdbarch_return_value (store, extract) */
1431
1432
1433 mn10300_frame_unwind_init (gdbarch);
1434
697e3bc9
KB
1435 /* Hook in ABI-specific overrides, if they have been registered. */
1436 gdbarch_init_osabi (info, gdbarch);
1437
342ee437
MS
1438 return gdbarch;
1439}
1440
025bb325 1441/* Dump out the mn10300 specific architecture information. */
342ee437
MS
1442
1443static void
d93859e2 1444mn10300_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
342ee437 1445{
d93859e2 1446 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
342ee437
MS
1447 fprintf_unfiltered (file, "mn10300_dump_tdep: am33_mode = %d\n",
1448 tdep->am33_mode);
1449}
1450
1451void
1452_initialize_mn10300_tdep (void)
1453{
1454 gdbarch_register (bfd_arch_mn10300, mn10300_gdbarch_init, mn10300_dump_tdep);
1455}
1456
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