Remove arm_override_mode
[deliverable/binutils-gdb.git] / gdb / mn10300-tdep.c
CommitLineData
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1/* Target-dependent code for the Matsushita MN10300 for GDB, the GNU debugger.
2
618f726f 3 Copyright (C) 1996-2016 Free Software Foundation, Inc.
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4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
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10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
342ee437 19
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20#include "defs.h"
21#include "arch-utils.h"
22#include "dis-asm.h"
23#include "gdbtypes.h"
24#include "regcache.h"
025bb325 25#include "gdbcore.h" /* For write_memory_unsigned_integer. */
342ee437 26#include "value.h"
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27#include "frame.h"
28#include "frame-unwind.h"
29#include "frame-base.h"
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30#include "symtab.h"
31#include "dwarf2-frame.h"
697e3bc9 32#include "osabi.h"
ee3a2f01 33#include "infcall.h"
6c02c64c 34#include "prologue-value.h"
effa26a9 35#include "target.h"
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36
37#include "mn10300-tdep.h"
38
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39
40/* The am33-2 has 64 registers. */
41#define MN10300_MAX_NUM_REGS 64
42
43/* This structure holds the results of a prologue analysis. */
44struct mn10300_prologue
45{
d80b854b
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46 /* The architecture for which we generated this prologue info. */
47 struct gdbarch *gdbarch;
48
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49 /* The offset from the frame base to the stack pointer --- always
50 zero or negative.
51
52 Calling this a "size" is a bit misleading, but given that the
53 stack grows downwards, using offsets for everything keeps one
54 from going completely sign-crazy: you never change anything's
55 sign for an ADD instruction; always change the second operand's
56 sign for a SUB instruction; and everything takes care of
57 itself. */
58 int frame_size;
59
60 /* Non-zero if this function has initialized the frame pointer from
61 the stack pointer, zero otherwise. */
62 int has_frame_ptr;
63
64 /* If has_frame_ptr is non-zero, this is the offset from the frame
65 base to where the frame pointer points. This is always zero or
66 negative. */
67 int frame_ptr_offset;
68
69 /* The address of the first instruction at which the frame has been
70 set up and the arguments are where the debug info says they are
71 --- as best as we can tell. */
72 CORE_ADDR prologue_end;
73
74 /* reg_offset[R] is the offset from the CFA at which register R is
75 saved, or 1 if register R has not been saved. (Real values are
76 always zero or negative.) */
77 int reg_offset[MN10300_MAX_NUM_REGS];
78};
79
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80
81/* Compute the alignment required by a type. */
82
83static int
84mn10300_type_align (struct type *type)
85{
86 int i, align = 1;
87
88 switch (TYPE_CODE (type))
89 {
90 case TYPE_CODE_INT:
91 case TYPE_CODE_ENUM:
92 case TYPE_CODE_SET:
93 case TYPE_CODE_RANGE:
94 case TYPE_CODE_CHAR:
95 case TYPE_CODE_BOOL:
96 case TYPE_CODE_FLT:
97 case TYPE_CODE_PTR:
98 case TYPE_CODE_REF:
99 return TYPE_LENGTH (type);
100
101 case TYPE_CODE_COMPLEX:
102 return TYPE_LENGTH (type) / 2;
103
104 case TYPE_CODE_STRUCT:
105 case TYPE_CODE_UNION:
106 for (i = 0; i < TYPE_NFIELDS (type); i++)
107 {
108 int falign = mn10300_type_align (TYPE_FIELD_TYPE (type, i));
109 while (align < falign)
110 align <<= 1;
111 }
112 return align;
113
114 case TYPE_CODE_ARRAY:
115 /* HACK! Structures containing arrays, even small ones, are not
116 elligible for returning in registers. */
117 return 256;
118
119 case TYPE_CODE_TYPEDEF:
120 return mn10300_type_align (check_typedef (type));
121
122 default:
123 internal_error (__FILE__, __LINE__, _("bad switch"));
124 }
125}
126
342ee437 127/* Should call_function allocate stack space for a struct return? */
342ee437 128static int
99fe5f9d 129mn10300_use_struct_convention (struct type *type)
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130{
131 /* Structures bigger than a pair of words can't be returned in
132 registers. */
133 if (TYPE_LENGTH (type) > 8)
134 return 1;
135
136 switch (TYPE_CODE (type))
137 {
138 case TYPE_CODE_STRUCT:
139 case TYPE_CODE_UNION:
140 /* Structures with a single field are handled as the field
141 itself. */
142 if (TYPE_NFIELDS (type) == 1)
99fe5f9d 143 return mn10300_use_struct_convention (TYPE_FIELD_TYPE (type, 0));
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144
145 /* Structures with word or double-word size are passed in memory, as
146 long as they require at least word alignment. */
147 if (mn10300_type_align (type) >= 4)
148 return 0;
149
150 return 1;
151
152 /* Arrays are addressable, so they're never returned in
153 registers. This condition can only hold when the array is
154 the only field of a struct or union. */
155 case TYPE_CODE_ARRAY:
156 return 1;
157
158 case TYPE_CODE_TYPEDEF:
99fe5f9d 159 return mn10300_use_struct_convention (check_typedef (type));
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160
161 default:
162 return 0;
163 }
164}
165
342ee437 166static void
99fe5f9d 167mn10300_store_return_value (struct gdbarch *gdbarch, struct type *type,
948f8e3d 168 struct regcache *regcache, const gdb_byte *valbuf)
342ee437 169{
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170 int len = TYPE_LENGTH (type);
171 int reg, regsz;
172
173 if (TYPE_CODE (type) == TYPE_CODE_PTR)
174 reg = 4;
175 else
176 reg = 0;
177
178 regsz = register_size (gdbarch, reg);
179
180 if (len <= regsz)
181 regcache_raw_write_part (regcache, reg, 0, len, valbuf);
182 else if (len <= 2 * regsz)
183 {
184 regcache_raw_write (regcache, reg, valbuf);
185 gdb_assert (regsz == register_size (gdbarch, reg + 1));
186 regcache_raw_write_part (regcache, reg+1, 0,
948f8e3d 187 len - regsz, valbuf + regsz);
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188 }
189 else
190 internal_error (__FILE__, __LINE__,
191 _("Cannot store return value %d bytes long."), len);
192}
193
342ee437 194static void
99fe5f9d 195mn10300_extract_return_value (struct gdbarch *gdbarch, struct type *type,
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196 struct regcache *regcache, void *valbuf)
197{
e362b510 198 gdb_byte buf[MAX_REGISTER_SIZE];
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199 int len = TYPE_LENGTH (type);
200 int reg, regsz;
201
202 if (TYPE_CODE (type) == TYPE_CODE_PTR)
203 reg = 4;
204 else
205 reg = 0;
206
207 regsz = register_size (gdbarch, reg);
208 if (len <= regsz)
209 {
210 regcache_raw_read (regcache, reg, buf);
211 memcpy (valbuf, buf, len);
212 }
213 else if (len <= 2 * regsz)
214 {
215 regcache_raw_read (regcache, reg, buf);
216 memcpy (valbuf, buf, regsz);
217 gdb_assert (regsz == register_size (gdbarch, reg + 1));
218 regcache_raw_read (regcache, reg + 1, buf);
219 memcpy ((char *) valbuf + regsz, buf, len - regsz);
220 }
221 else
222 internal_error (__FILE__, __LINE__,
223 _("Cannot extract return value %d bytes long."), len);
224}
225
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226/* Determine, for architecture GDBARCH, how a return value of TYPE
227 should be returned. If it is supposed to be returned in registers,
228 and READBUF is non-zero, read the appropriate value from REGCACHE,
229 and copy it into READBUF. If WRITEBUF is non-zero, write the value
230 from WRITEBUF into REGCACHE. */
231
232static enum return_value_convention
6a3a010b 233mn10300_return_value (struct gdbarch *gdbarch, struct value *function,
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234 struct type *type, struct regcache *regcache,
235 gdb_byte *readbuf, const gdb_byte *writebuf)
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236{
237 if (mn10300_use_struct_convention (type))
238 return RETURN_VALUE_STRUCT_CONVENTION;
239
240 if (readbuf)
241 mn10300_extract_return_value (gdbarch, type, regcache, readbuf);
242 if (writebuf)
243 mn10300_store_return_value (gdbarch, type, regcache, writebuf);
244
245 return RETURN_VALUE_REGISTER_CONVENTION;
246}
247
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248static char *
249register_name (int reg, char **regs, long sizeof_regs)
250{
251 if (reg < 0 || reg >= sizeof_regs / sizeof (regs[0]))
252 return NULL;
253 else
254 return regs[reg];
255}
256
257static const char *
d93859e2 258mn10300_generic_register_name (struct gdbarch *gdbarch, int reg)
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259{
260 static char *regs[] =
261 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
262 "sp", "pc", "mdr", "psw", "lir", "lar", "", "",
263 "", "", "", "", "", "", "", "",
264 "", "", "", "", "", "", "", "fp"
265 };
266 return register_name (reg, regs, sizeof regs);
267}
268
269
270static const char *
d93859e2 271am33_register_name (struct gdbarch *gdbarch, int reg)
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272{
273 static char *regs[] =
274 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
275 "sp", "pc", "mdr", "psw", "lir", "lar", "",
276 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
277 "ssp", "msp", "usp", "mcrh", "mcrl", "mcvf", "", "", ""
278 };
279 return register_name (reg, regs, sizeof regs);
280}
281
4640dd91 282static const char *
d93859e2 283am33_2_register_name (struct gdbarch *gdbarch, int reg)
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284{
285 static char *regs[] =
286 {
287 "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
288 "sp", "pc", "mdr", "psw", "lir", "lar", "mdrq", "r0",
289 "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ssp",
290 "msp", "usp", "mcrh", "mcrl", "mcvf", "fpcr", "", "",
291 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
292 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
293 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
294 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
295 };
296 return register_name (reg, regs, sizeof regs);
297}
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298
299static struct type *
300mn10300_register_type (struct gdbarch *gdbarch, int reg)
301{
0dfff4cb 302 return builtin_type (gdbarch)->builtin_int;
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303}
304
305static CORE_ADDR
61a1198a 306mn10300_read_pc (struct regcache *regcache)
342ee437 307{
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308 ULONGEST val;
309 regcache_cooked_read_unsigned (regcache, E_PC_REGNUM, &val);
310 return val;
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311}
312
313static void
61a1198a 314mn10300_write_pc (struct regcache *regcache, CORE_ADDR val)
342ee437 315{
61a1198a 316 regcache_cooked_write_unsigned (regcache, E_PC_REGNUM, val);
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317}
318
319/* The breakpoint instruction must be the same size as the smallest
320 instruction in the instruction set.
321
322 The Matsushita mn10x00 processors have single byte instructions
323 so we need a single byte breakpoint. Matsushita hasn't defined
324 one, so we defined it ourselves. */
598cc9dc 325static gdb_byte breakpoint[] = {0xff};
342ee437 326
598cc9dc 327GDBARCH_BREAKPOINT_MANIPULATION (mn10300, breakpoint)
342ee437 328
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329/* Model the semantics of pushing a register onto the stack. This
330 is a helper function for mn10300_analyze_prologue, below. */
331static void
332push_reg (pv_t *regs, struct pv_area *stack, int regnum)
333{
334 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4);
335 pv_area_store (stack, regs[E_SP_REGNUM], 4, regs[regnum]);
336}
337
338/* Translate an "r" register number extracted from an instruction encoding
339 into a GDB register number. Adapted from a simulator function
340 of the same name; see am33.igen. */
341static int
342translate_rreg (int rreg)
343{
344 /* The higher register numbers actually correspond to the
345 basic machine's address and data registers. */
346 if (rreg > 7 && rreg < 12)
347 return E_A0_REGNUM + rreg - 8;
348 else if (rreg > 11 && rreg < 16)
349 return E_D0_REGNUM + rreg - 12;
350 else
351 return E_E0_REGNUM + rreg;
352}
353
354/* Find saved registers in a 'struct pv_area'; we pass this to pv_area_scan.
9cacebf5 355
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356 If VALUE is a saved register, ADDR says it was saved at a constant
357 offset from the frame base, and SIZE indicates that the whole
358 register was saved, record its offset in RESULT_UNTYPED. */
9cacebf5 359static void
6c02c64c 360check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value)
9cacebf5 361{
6c02c64c 362 struct mn10300_prologue *result = (struct mn10300_prologue *) result_untyped;
9cacebf5 363
6c02c64c
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364 if (value.kind == pvk_register
365 && value.k == 0
366 && pv_is_register (addr, E_SP_REGNUM)
d80b854b 367 && size == register_size (result->gdbarch, value.reg))
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368 result->reg_offset[value.reg] = addr.k;
369}
9cacebf5 370
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371/* Analyze the prologue to determine where registers are saved,
372 the end of the prologue, etc. The result of this analysis is
373 returned in RESULT. See struct mn10300_prologue above for more
374 information. */
375static void
376mn10300_analyze_prologue (struct gdbarch *gdbarch,
377 CORE_ADDR start_pc, CORE_ADDR limit_pc,
378 struct mn10300_prologue *result)
379{
e17a4113 380 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
22e048c9 381 CORE_ADDR pc;
6c02c64c
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382 int rn;
383 pv_t regs[MN10300_MAX_NUM_REGS];
384 struct pv_area *stack;
385 struct cleanup *back_to;
386 CORE_ADDR after_last_frame_setup_insn = start_pc;
387 int am33_mode = AM33_MODE (gdbarch);
388
389 memset (result, 0, sizeof (*result));
d80b854b 390 result->gdbarch = gdbarch;
9cacebf5 391
6c02c64c 392 for (rn = 0; rn < MN10300_MAX_NUM_REGS; rn++)
4640dd91 393 {
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394 regs[rn] = pv_register (rn, 0);
395 result->reg_offset[rn] = 1;
4640dd91 396 }
55f960e1 397 stack = make_pv_area (E_SP_REGNUM, gdbarch_addr_bit (gdbarch));
6c02c64c
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398 back_to = make_cleanup_free_pv_area (stack);
399
400 /* The typical call instruction will have saved the return address on the
401 stack. Space for the return address has already been preallocated in
402 the caller's frame. It's possible, such as when using -mrelax with gcc
403 that other registers were saved as well. If this happens, we really
404 have no chance of deciphering the frame. DWARF info can save the day
405 when this happens. */
406 pv_area_store (stack, regs[E_SP_REGNUM], 4, regs[E_PC_REGNUM]);
407
408 pc = start_pc;
409 while (pc < limit_pc)
4640dd91 410 {
6c02c64c
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411 int status;
412 gdb_byte instr[2];
4640dd91 413
6c02c64c
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414 /* Instructions can be as small as one byte; however, we usually
415 need at least two bytes to do the decoding, so fetch that many
416 to begin with. */
417 status = target_read_memory (pc, instr, 2);
418 if (status != 0)
419 break;
4640dd91 420
6c02c64c
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421 /* movm [regs], sp */
422 if (instr[0] == 0xcf)
4640dd91 423 {
6c02c64c
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424 gdb_byte save_mask;
425
426 save_mask = instr[1];
427
428 if ((save_mask & movm_exreg0_bit) && am33_mode)
429 {
430 push_reg (regs, stack, E_E2_REGNUM);
431 push_reg (regs, stack, E_E3_REGNUM);
432 }
433 if ((save_mask & movm_exreg1_bit) && am33_mode)
4640dd91 434 {
6c02c64c
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435 push_reg (regs, stack, E_E4_REGNUM);
436 push_reg (regs, stack, E_E5_REGNUM);
437 push_reg (regs, stack, E_E6_REGNUM);
438 push_reg (regs, stack, E_E7_REGNUM);
4640dd91 439 }
6c02c64c
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440 if ((save_mask & movm_exother_bit) && am33_mode)
441 {
442 push_reg (regs, stack, E_E0_REGNUM);
443 push_reg (regs, stack, E_E1_REGNUM);
444 push_reg (regs, stack, E_MDRQ_REGNUM);
445 push_reg (regs, stack, E_MCRH_REGNUM);
446 push_reg (regs, stack, E_MCRL_REGNUM);
447 push_reg (regs, stack, E_MCVF_REGNUM);
448 }
449 if (save_mask & movm_d2_bit)
450 push_reg (regs, stack, E_D2_REGNUM);
451 if (save_mask & movm_d3_bit)
452 push_reg (regs, stack, E_D3_REGNUM);
453 if (save_mask & movm_a2_bit)
454 push_reg (regs, stack, E_A2_REGNUM);
455 if (save_mask & movm_a3_bit)
456 push_reg (regs, stack, E_A3_REGNUM);
457 if (save_mask & movm_other_bit)
458 {
459 push_reg (regs, stack, E_D0_REGNUM);
460 push_reg (regs, stack, E_D1_REGNUM);
461 push_reg (regs, stack, E_A0_REGNUM);
462 push_reg (regs, stack, E_A1_REGNUM);
463 push_reg (regs, stack, E_MDR_REGNUM);
464 push_reg (regs, stack, E_LIR_REGNUM);
465 push_reg (regs, stack, E_LAR_REGNUM);
466 /* The `other' bit leaves a blank area of four bytes at
467 the beginning of its block of saved registers, making
468 it 32 bytes long in total. */
469 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], -4);
470 }
471
472 pc += 2;
473 after_last_frame_setup_insn = pc;
4640dd91 474 }
6c02c64c
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475 /* mov sp, aN */
476 else if ((instr[0] & 0xfc) == 0x3c)
477 {
478 int aN = instr[0] & 0x03;
4640dd91 479
6c02c64c 480 regs[E_A0_REGNUM + aN] = regs[E_SP_REGNUM];
4640dd91 481
6c02c64c
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482 pc += 1;
483 if (aN == 3)
484 after_last_frame_setup_insn = pc;
485 }
486 /* mov aM, aN */
487 else if ((instr[0] & 0xf0) == 0x90
488 && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2))
489 {
490 int aN = instr[0] & 0x03;
491 int aM = (instr[0] & 0x0c) >> 2;
9cacebf5 492
6c02c64c 493 regs[E_A0_REGNUM + aN] = regs[E_A0_REGNUM + aM];
9cacebf5 494
6c02c64c
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495 pc += 1;
496 }
497 /* mov dM, dN */
498 else if ((instr[0] & 0xf0) == 0x80
499 && (instr[0] & 0x03) != ((instr[0] & 0x0c) >> 2))
500 {
501 int dN = instr[0] & 0x03;
502 int dM = (instr[0] & 0x0c) >> 2;
9cacebf5 503
6c02c64c 504 regs[E_D0_REGNUM + dN] = regs[E_D0_REGNUM + dM];
9cacebf5 505
6c02c64c
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506 pc += 1;
507 }
508 /* mov aM, dN */
509 else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xd0)
510 {
511 int dN = instr[1] & 0x03;
512 int aM = (instr[1] & 0x0c) >> 2;
9cacebf5 513
6c02c64c 514 regs[E_D0_REGNUM + dN] = regs[E_A0_REGNUM + aM];
9cacebf5 515
6c02c64c
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516 pc += 2;
517 }
518 /* mov dM, aN */
519 else if (instr[0] == 0xf1 && (instr[1] & 0xf0) == 0xe0)
520 {
521 int aN = instr[1] & 0x03;
522 int dM = (instr[1] & 0x0c) >> 2;
9cacebf5 523
6c02c64c 524 regs[E_A0_REGNUM + aN] = regs[E_D0_REGNUM + dM];
9cacebf5 525
6c02c64c
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526 pc += 2;
527 }
528 /* add imm8, SP */
529 else if (instr[0] == 0xf8 && instr[1] == 0xfe)
530 {
531 gdb_byte buf[1];
532 LONGEST imm8;
9cacebf5 533
9cacebf5 534
6c02c64c
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535 status = target_read_memory (pc + 2, buf, 1);
536 if (status != 0)
537 break;
9cacebf5 538
e17a4113 539 imm8 = extract_signed_integer (buf, 1, byte_order);
6c02c64c 540 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm8);
9cacebf5 541
6c02c64c
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542 pc += 3;
543 /* Stack pointer adjustments are frame related. */
544 after_last_frame_setup_insn = pc;
545 }
546 /* add imm16, SP */
547 else if (instr[0] == 0xfa && instr[1] == 0xfe)
548 {
549 gdb_byte buf[2];
550 LONGEST imm16;
9cacebf5 551
6c02c64c
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552 status = target_read_memory (pc + 2, buf, 2);
553 if (status != 0)
554 break;
9cacebf5 555
e17a4113 556 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c 557 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm16);
9cacebf5 558
6c02c64c
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559 pc += 4;
560 /* Stack pointer adjustments are frame related. */
561 after_last_frame_setup_insn = pc;
562 }
563 /* add imm32, SP */
564 else if (instr[0] == 0xfc && instr[1] == 0xfe)
565 {
566 gdb_byte buf[4];
567 LONGEST imm32;
9cacebf5 568
6c02c64c
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569 status = target_read_memory (pc + 2, buf, 4);
570 if (status != 0)
571 break;
9cacebf5 572
9cacebf5 573
e17a4113 574 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c 575 regs[E_SP_REGNUM] = pv_add_constant (regs[E_SP_REGNUM], imm32);
9cacebf5 576
6c02c64c
KB
577 pc += 6;
578 /* Stack pointer adjustments are frame related. */
579 after_last_frame_setup_insn = pc;
580 }
581 /* add imm8, aN */
582 else if ((instr[0] & 0xfc) == 0x20)
583 {
584 int aN;
585 LONGEST imm8;
9cacebf5 586
6c02c64c 587 aN = instr[0] & 0x03;
e17a4113 588 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
9cacebf5 589
6c02c64c
KB
590 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
591 imm8);
9cacebf5 592
6c02c64c
KB
593 pc += 2;
594 }
595 /* add imm16, aN */
596 else if (instr[0] == 0xfa && (instr[1] & 0xfc) == 0xd0)
597 {
598 int aN;
599 LONGEST imm16;
600 gdb_byte buf[2];
9cacebf5 601
6c02c64c 602 aN = instr[1] & 0x03;
9cacebf5 603
6c02c64c
KB
604 status = target_read_memory (pc + 2, buf, 2);
605 if (status != 0)
606 break;
9cacebf5 607
9cacebf5 608
e17a4113 609 imm16 = extract_signed_integer (buf, 2, byte_order);
9cacebf5 610
6c02c64c
KB
611 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
612 imm16);
9cacebf5 613
6c02c64c
KB
614 pc += 4;
615 }
616 /* add imm32, aN */
617 else if (instr[0] == 0xfc && (instr[1] & 0xfc) == 0xd0)
618 {
619 int aN;
620 LONGEST imm32;
621 gdb_byte buf[4];
9cacebf5 622
6c02c64c 623 aN = instr[1] & 0x03;
9cacebf5 624
6c02c64c
KB
625 status = target_read_memory (pc + 2, buf, 4);
626 if (status != 0)
627 break;
9cacebf5 628
e17a4113 629 imm32 = extract_signed_integer (buf, 2, byte_order);
9cacebf5 630
6c02c64c
KB
631 regs[E_A0_REGNUM + aN] = pv_add_constant (regs[E_A0_REGNUM + aN],
632 imm32);
633 pc += 6;
634 }
635 /* fmov fsM, (rN) */
636 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x30)
637 {
638 int fsM, sM, Y, rN;
639 gdb_byte buf[1];
9cacebf5 640
6c02c64c 641 Y = (instr[1] & 0x02) >> 1;
9cacebf5 642
6c02c64c
KB
643 status = target_read_memory (pc + 2, buf, 1);
644 if (status != 0)
645 break;
9cacebf5 646
6c02c64c
KB
647 sM = (buf[0] & 0xf0) >> 4;
648 rN = buf[0] & 0x0f;
649 fsM = (Y << 4) | sM;
9cacebf5 650
6c02c64c
KB
651 pv_area_store (stack, regs[translate_rreg (rN)], 4,
652 regs[E_FS0_REGNUM + fsM]);
9cacebf5 653
6c02c64c
KB
654 pc += 3;
655 }
656 /* fmov fsM, (sp) */
657 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x34)
658 {
659 int fsM, sM, Y;
660 gdb_byte buf[1];
9cacebf5 661
6c02c64c 662 Y = (instr[1] & 0x02) >> 1;
9cacebf5 663
6c02c64c
KB
664 status = target_read_memory (pc + 2, buf, 1);
665 if (status != 0)
666 break;
9cacebf5 667
6c02c64c
KB
668 sM = (buf[0] & 0xf0) >> 4;
669 fsM = (Y << 4) | sM;
9cacebf5 670
6c02c64c
KB
671 pv_area_store (stack, regs[E_SP_REGNUM], 4,
672 regs[E_FS0_REGNUM + fsM]);
9cacebf5 673
6c02c64c
KB
674 pc += 3;
675 }
676 /* fmov fsM, (rN, rI) */
677 else if (instr[0] == 0xfb && instr[1] == 0x37)
678 {
679 int fsM, sM, Z, rN, rI;
680 gdb_byte buf[2];
9cacebf5 681
9cacebf5 682
6c02c64c
KB
683 status = target_read_memory (pc + 2, buf, 2);
684 if (status != 0)
685 break;
83845630 686
6c02c64c
KB
687 rI = (buf[0] & 0xf0) >> 4;
688 rN = buf[0] & 0x0f;
689 sM = (buf[1] & 0xf0) >> 4;
690 Z = (buf[1] & 0x02) >> 1;
691 fsM = (Z << 4) | sM;
83845630 692
6c02c64c
KB
693 pv_area_store (stack,
694 pv_add (regs[translate_rreg (rN)],
695 regs[translate_rreg (rI)]),
696 4, regs[E_FS0_REGNUM + fsM]);
83845630 697
6c02c64c
KB
698 pc += 4;
699 }
700 /* fmov fsM, (d8, rN) */
701 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x30)
4640dd91 702 {
6c02c64c
KB
703 int fsM, sM, Y, rN;
704 LONGEST d8;
705 gdb_byte buf[2];
706
707 Y = (instr[1] & 0x02) >> 1;
708
709 status = target_read_memory (pc + 2, buf, 2);
710 if (status != 0)
711 break;
712
713 sM = (buf[0] & 0xf0) >> 4;
714 rN = buf[0] & 0x0f;
715 fsM = (Y << 4) | sM;
e17a4113 716 d8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c
KB
717
718 pv_area_store (stack,
719 pv_add_constant (regs[translate_rreg (rN)], d8),
720 4, regs[E_FS0_REGNUM + fsM]);
721
722 pc += 4;
4640dd91 723 }
6c02c64c
KB
724 /* fmov fsM, (d24, rN) */
725 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x30)
83845630 726 {
6c02c64c
KB
727 int fsM, sM, Y, rN;
728 LONGEST d24;
729 gdb_byte buf[4];
730
731 Y = (instr[1] & 0x02) >> 1;
732
733 status = target_read_memory (pc + 2, buf, 4);
83845630 734 if (status != 0)
6c02c64c
KB
735 break;
736
737 sM = (buf[0] & 0xf0) >> 4;
738 rN = buf[0] & 0x0f;
739 fsM = (Y << 4) | sM;
e17a4113 740 d24 = extract_signed_integer (&buf[1], 3, byte_order);
6c02c64c
KB
741
742 pv_area_store (stack,
743 pv_add_constant (regs[translate_rreg (rN)], d24),
744 4, regs[E_FS0_REGNUM + fsM]);
745
746 pc += 6;
83845630 747 }
6c02c64c
KB
748 /* fmov fsM, (d32, rN) */
749 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x30)
750 {
751 int fsM, sM, Y, rN;
752 LONGEST d32;
753 gdb_byte buf[5];
4640dd91 754
6c02c64c
KB
755 Y = (instr[1] & 0x02) >> 1;
756
757 status = target_read_memory (pc + 2, buf, 5);
758 if (status != 0)
759 break;
760
761 sM = (buf[0] & 0xf0) >> 4;
762 rN = buf[0] & 0x0f;
763 fsM = (Y << 4) | sM;
e17a4113 764 d32 = extract_signed_integer (&buf[1], 4, byte_order);
9cacebf5 765
6c02c64c
KB
766 pv_area_store (stack,
767 pv_add_constant (regs[translate_rreg (rN)], d32),
768 4, regs[E_FS0_REGNUM + fsM]);
769
770 pc += 7;
771 }
772 /* fmov fsM, (d8, SP) */
773 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x34)
9cacebf5 774 {
6c02c64c
KB
775 int fsM, sM, Y;
776 LONGEST d8;
777 gdb_byte buf[2];
778
779 Y = (instr[1] & 0x02) >> 1;
780
781 status = target_read_memory (pc + 2, buf, 2);
782 if (status != 0)
783 break;
784
785 sM = (buf[0] & 0xf0) >> 4;
786 fsM = (Y << 4) | sM;
e17a4113 787 d8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c
KB
788
789 pv_area_store (stack,
790 pv_add_constant (regs[E_SP_REGNUM], d8),
791 4, regs[E_FS0_REGNUM + fsM]);
792
793 pc += 4;
9cacebf5 794 }
6c02c64c
KB
795 /* fmov fsM, (d24, SP) */
796 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x34)
797 {
798 int fsM, sM, Y;
799 LONGEST d24;
800 gdb_byte buf[4];
9cacebf5 801
6c02c64c 802 Y = (instr[1] & 0x02) >> 1;
9cacebf5 803
6c02c64c
KB
804 status = target_read_memory (pc + 2, buf, 4);
805 if (status != 0)
806 break;
9cacebf5 807
6c02c64c
KB
808 sM = (buf[0] & 0xf0) >> 4;
809 fsM = (Y << 4) | sM;
e17a4113 810 d24 = extract_signed_integer (&buf[1], 3, byte_order);
9cacebf5 811
6c02c64c
KB
812 pv_area_store (stack,
813 pv_add_constant (regs[E_SP_REGNUM], d24),
814 4, regs[E_FS0_REGNUM + fsM]);
9cacebf5 815
6c02c64c
KB
816 pc += 6;
817 }
818 /* fmov fsM, (d32, SP) */
819 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x34)
820 {
821 int fsM, sM, Y;
822 LONGEST d32;
823 gdb_byte buf[5];
9cacebf5 824
6c02c64c 825 Y = (instr[1] & 0x02) >> 1;
9cacebf5 826
6c02c64c
KB
827 status = target_read_memory (pc + 2, buf, 5);
828 if (status != 0)
829 break;
830
831 sM = (buf[0] & 0xf0) >> 4;
832 fsM = (Y << 4) | sM;
e17a4113 833 d32 = extract_signed_integer (&buf[1], 4, byte_order);
6c02c64c
KB
834
835 pv_area_store (stack,
836 pv_add_constant (regs[E_SP_REGNUM], d32),
837 4, regs[E_FS0_REGNUM + fsM]);
838
839 pc += 7;
840 }
841 /* fmov fsM, (rN+) */
842 else if (instr[0] == 0xf9 && (instr[1] & 0xfd) == 0x31)
843 {
844 int fsM, sM, Y, rN, rN_regnum;
845 gdb_byte buf[1];
846
847 Y = (instr[1] & 0x02) >> 1;
848
849 status = target_read_memory (pc + 2, buf, 1);
850 if (status != 0)
851 break;
852
853 sM = (buf[0] & 0xf0) >> 4;
854 rN = buf[0] & 0x0f;
855 fsM = (Y << 4) | sM;
856
857 rN_regnum = translate_rreg (rN);
858
859 pv_area_store (stack, regs[rN_regnum], 4,
860 regs[E_FS0_REGNUM + fsM]);
861 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], 4);
862
863 pc += 3;
864 }
865 /* fmov fsM, (rN+, imm8) */
866 else if (instr[0] == 0xfb && (instr[1] & 0xfd) == 0x31)
867 {
868 int fsM, sM, Y, rN, rN_regnum;
869 LONGEST imm8;
870 gdb_byte buf[2];
871
872 Y = (instr[1] & 0x02) >> 1;
873
874 status = target_read_memory (pc + 2, buf, 2);
875 if (status != 0)
876 break;
877
878 sM = (buf[0] & 0xf0) >> 4;
879 rN = buf[0] & 0x0f;
880 fsM = (Y << 4) | sM;
e17a4113 881 imm8 = extract_signed_integer (&buf[1], 1, byte_order);
6c02c64c
KB
882
883 rN_regnum = translate_rreg (rN);
884
885 pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
886 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm8);
887
888 pc += 4;
889 }
890 /* fmov fsM, (rN+, imm24) */
891 else if (instr[0] == 0xfd && (instr[1] & 0xfd) == 0x31)
892 {
893 int fsM, sM, Y, rN, rN_regnum;
894 LONGEST imm24;
895 gdb_byte buf[4];
896
897 Y = (instr[1] & 0x02) >> 1;
898
899 status = target_read_memory (pc + 2, buf, 4);
900 if (status != 0)
901 break;
902
903 sM = (buf[0] & 0xf0) >> 4;
904 rN = buf[0] & 0x0f;
905 fsM = (Y << 4) | sM;
e17a4113 906 imm24 = extract_signed_integer (&buf[1], 3, byte_order);
6c02c64c
KB
907
908 rN_regnum = translate_rreg (rN);
909
910 pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
911 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm24);
912
913 pc += 6;
914 }
915 /* fmov fsM, (rN+, imm32) */
916 else if (instr[0] == 0xfe && (instr[1] & 0xfd) == 0x31)
917 {
918 int fsM, sM, Y, rN, rN_regnum;
919 LONGEST imm32;
920 gdb_byte buf[5];
921
922 Y = (instr[1] & 0x02) >> 1;
923
924 status = target_read_memory (pc + 2, buf, 5);
925 if (status != 0)
926 break;
927
928 sM = (buf[0] & 0xf0) >> 4;
929 rN = buf[0] & 0x0f;
930 fsM = (Y << 4) | sM;
e17a4113 931 imm32 = extract_signed_integer (&buf[1], 4, byte_order);
6c02c64c
KB
932
933 rN_regnum = translate_rreg (rN);
934
935 pv_area_store (stack, regs[rN_regnum], 4, regs[E_FS0_REGNUM + fsM]);
936 regs[rN_regnum] = pv_add_constant (regs[rN_regnum], imm32);
937
938 pc += 7;
939 }
940 /* mov imm8, aN */
941 else if ((instr[0] & 0xf0) == 0x90)
942 {
943 int aN = instr[0] & 0x03;
944 LONGEST imm8;
9cacebf5 945
e17a4113 946 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
9cacebf5 947
6c02c64c
KB
948 regs[E_A0_REGNUM + aN] = pv_constant (imm8);
949 pc += 2;
950 }
951 /* mov imm16, aN */
952 else if ((instr[0] & 0xfc) == 0x24)
953 {
954 int aN = instr[0] & 0x03;
955 gdb_byte buf[2];
956 LONGEST imm16;
957
958 status = target_read_memory (pc + 1, buf, 2);
959 if (status != 0)
960 break;
961
e17a4113 962 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c
KB
963 regs[E_A0_REGNUM + aN] = pv_constant (imm16);
964 pc += 3;
965 }
966 /* mov imm32, aN */
967 else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xdc))
968 {
969 int aN = instr[1] & 0x03;
970 gdb_byte buf[4];
971 LONGEST imm32;
972
973 status = target_read_memory (pc + 2, buf, 4);
974 if (status != 0)
975 break;
976
e17a4113 977 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c
KB
978 regs[E_A0_REGNUM + aN] = pv_constant (imm32);
979 pc += 6;
980 }
981 /* mov imm8, dN */
982 else if ((instr[0] & 0xf0) == 0x80)
983 {
984 int dN = instr[0] & 0x03;
985 LONGEST imm8;
986
e17a4113 987 imm8 = extract_signed_integer (&instr[1], 1, byte_order);
6c02c64c
KB
988
989 regs[E_D0_REGNUM + dN] = pv_constant (imm8);
990 pc += 2;
991 }
992 /* mov imm16, dN */
993 else if ((instr[0] & 0xfc) == 0x2c)
994 {
995 int dN = instr[0] & 0x03;
996 gdb_byte buf[2];
997 LONGEST imm16;
998
999 status = target_read_memory (pc + 1, buf, 2);
1000 if (status != 0)
1001 break;
1002
e17a4113 1003 imm16 = extract_signed_integer (buf, 2, byte_order);
6c02c64c
KB
1004 regs[E_D0_REGNUM + dN] = pv_constant (imm16);
1005 pc += 3;
1006 }
1007 /* mov imm32, dN */
1008 else if (instr[0] == 0xfc && ((instr[1] & 0xfc) == 0xcc))
1009 {
1010 int dN = instr[1] & 0x03;
1011 gdb_byte buf[4];
1012 LONGEST imm32;
1013
1014 status = target_read_memory (pc + 2, buf, 4);
1015 if (status != 0)
1016 break;
1017
e17a4113 1018 imm32 = extract_signed_integer (buf, 4, byte_order);
6c02c64c
KB
1019 regs[E_D0_REGNUM + dN] = pv_constant (imm32);
1020 pc += 6;
1021 }
1022 else
1023 {
1024 /* We've hit some instruction that we don't recognize. Hopefully,
1025 we have enough to do prologue analysis. */
1026 break;
1027 }
1028 }
1029
1030 /* Is the frame size (offset, really) a known constant? */
1031 if (pv_is_register (regs[E_SP_REGNUM], E_SP_REGNUM))
1032 result->frame_size = regs[E_SP_REGNUM].k;
9cacebf5 1033
6c02c64c
KB
1034 /* Was the frame pointer initialized? */
1035 if (pv_is_register (regs[E_A3_REGNUM], E_SP_REGNUM))
1036 {
1037 result->has_frame_ptr = 1;
1038 result->frame_ptr_offset = regs[E_A3_REGNUM].k;
9cacebf5 1039 }
6c02c64c
KB
1040
1041 /* Record where all the registers were saved. */
1042 pv_area_scan (stack, check_for_saved, (void *) result);
1043
1044 result->prologue_end = after_last_frame_setup_insn;
1045
1046 do_cleanups (back_to);
9cacebf5
MS
1047}
1048
342ee437
MS
1049/* Function: skip_prologue
1050 Return the address of the first inst past the prologue of the function. */
1051
1052static CORE_ADDR
6093d2eb 1053mn10300_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
342ee437 1054{
2c02bd72 1055 const char *name;
6c02c64c
KB
1056 CORE_ADDR func_addr, func_end;
1057 struct mn10300_prologue p;
1058
1059 /* Try to find the extent of the function that contains PC. */
1060 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1061 return pc;
1062
1063 mn10300_analyze_prologue (gdbarch, pc, func_end, &p);
1064 return p.prologue_end;
342ee437
MS
1065}
1066
6c02c64c
KB
1067/* Wrapper for mn10300_analyze_prologue: find the function start;
1068 use the current frame PC as the limit, then
1069 invoke mn10300_analyze_prologue and return its result. */
1070static struct mn10300_prologue *
1071mn10300_analyze_frame_prologue (struct frame_info *this_frame,
1072 void **this_prologue_cache)
342ee437 1073{
6c02c64c 1074 if (!*this_prologue_cache)
93d42b30 1075 {
6c02c64c
KB
1076 CORE_ADDR func_start, stop_addr;
1077
1078 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct mn10300_prologue);
1079
1080 func_start = get_frame_func (this_frame);
1081 stop_addr = get_frame_pc (this_frame);
1082
1083 /* If we couldn't find any function containing the PC, then
1084 just initialize the prologue cache, but don't do anything. */
1085 if (!func_start)
1086 stop_addr = func_start;
1087
1088 mn10300_analyze_prologue (get_frame_arch (this_frame),
19ba03f4
SM
1089 func_start, stop_addr,
1090 ((struct mn10300_prologue *)
1091 *this_prologue_cache));
93d42b30 1092 }
342ee437 1093
19ba03f4 1094 return (struct mn10300_prologue *) *this_prologue_cache;
6c02c64c
KB
1095}
1096
1097/* Given the next frame and a prologue cache, return this frame's
1098 base. */
1099static CORE_ADDR
1100mn10300_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
1101{
1102 struct mn10300_prologue *p
1103 = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache);
1104
1105 /* In functions that use alloca, the distance between the stack
1106 pointer and the frame base varies dynamically, so we can't use
1107 the SP plus static information like prologue analysis to find the
1108 frame base. However, such functions must have a frame pointer,
1109 to be able to restore the SP on exit. So whenever we do have a
1110 frame pointer, use that to find the base. */
1111 if (p->has_frame_ptr)
1112 {
1113 CORE_ADDR fp = get_frame_register_unsigned (this_frame, E_A3_REGNUM);
1114 return fp - p->frame_ptr_offset;
1115 }
1116 else
1117 {
1118 CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1119 return sp - p->frame_size;
1120 }
342ee437
MS
1121}
1122
1123/* Here is a dummy implementation. */
1124static struct frame_id
94afd7a6 1125mn10300_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
342ee437 1126{
94afd7a6
UW
1127 CORE_ADDR sp = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1128 CORE_ADDR pc = get_frame_register_unsigned (this_frame, E_PC_REGNUM);
1129 return frame_id_build (sp, pc);
342ee437
MS
1130}
1131
342ee437 1132static void
94afd7a6 1133mn10300_frame_this_id (struct frame_info *this_frame,
342ee437
MS
1134 void **this_prologue_cache,
1135 struct frame_id *this_id)
1136{
025bb325
MS
1137 *this_id = frame_id_build (mn10300_frame_base (this_frame,
1138 this_prologue_cache),
6c02c64c 1139 get_frame_func (this_frame));
342ee437 1140
342ee437
MS
1141}
1142
94afd7a6
UW
1143static struct value *
1144mn10300_frame_prev_register (struct frame_info *this_frame,
6c02c64c 1145 void **this_prologue_cache, int regnum)
342ee437 1146{
6c02c64c
KB
1147 struct mn10300_prologue *p
1148 = mn10300_analyze_frame_prologue (this_frame, this_prologue_cache);
1149 CORE_ADDR frame_base = mn10300_frame_base (this_frame, this_prologue_cache);
6c02c64c
KB
1150
1151 if (regnum == E_SP_REGNUM)
1152 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1153
1154 /* If prologue analysis says we saved this register somewhere,
1155 return a description of the stack slot holding it. */
1156 if (p->reg_offset[regnum] != 1)
1157 return frame_unwind_got_memory (this_frame, regnum,
1158 frame_base + p->reg_offset[regnum]);
1159
1160 /* Otherwise, presume we haven't changed the value of this
1161 register, and get it from the next frame. */
1162 return frame_unwind_got_register (this_frame, regnum, regnum);
342ee437
MS
1163}
1164
1165static const struct frame_unwind mn10300_frame_unwind = {
1166 NORMAL_FRAME,
8fbca658 1167 default_frame_unwind_stop_reason,
342ee437 1168 mn10300_frame_this_id,
94afd7a6
UW
1169 mn10300_frame_prev_register,
1170 NULL,
1171 default_frame_sniffer
342ee437
MS
1172};
1173
1174static CORE_ADDR
6c02c64c 1175mn10300_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
342ee437
MS
1176{
1177 ULONGEST pc;
1178
6c02c64c 1179 pc = frame_unwind_register_unsigned (this_frame, E_PC_REGNUM);
342ee437
MS
1180 return pc;
1181}
1182
1183static CORE_ADDR
6c02c64c 1184mn10300_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
342ee437
MS
1185{
1186 ULONGEST sp;
1187
6c02c64c 1188 sp = frame_unwind_register_unsigned (this_frame, E_SP_REGNUM);
342ee437
MS
1189 return sp;
1190}
1191
1192static void
1193mn10300_frame_unwind_init (struct gdbarch *gdbarch)
1194{
94afd7a6
UW
1195 dwarf2_append_unwinders (gdbarch);
1196 frame_unwind_append_unwinder (gdbarch, &mn10300_frame_unwind);
94afd7a6 1197 set_gdbarch_dummy_id (gdbarch, mn10300_dummy_id);
342ee437
MS
1198 set_gdbarch_unwind_pc (gdbarch, mn10300_unwind_pc);
1199 set_gdbarch_unwind_sp (gdbarch, mn10300_unwind_sp);
1200}
1201
1202/* Function: push_dummy_call
1203 *
1204 * Set up machine state for a target call, including
1205 * function arguments, stack, return address, etc.
1206 *
1207 */
1208
1209static CORE_ADDR
1210mn10300_push_dummy_call (struct gdbarch *gdbarch,
1211 struct value *target_func,
1212 struct regcache *regcache,
1213 CORE_ADDR bp_addr,
1214 int nargs, struct value **args,
1215 CORE_ADDR sp,
1216 int struct_return,
1217 CORE_ADDR struct_addr)
1218{
e17a4113 1219 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
342ee437 1220 const int push_size = register_size (gdbarch, E_PC_REGNUM);
1fb1ca27 1221 int regs_used;
342ee437
MS
1222 int len, arg_len;
1223 int stack_offset = 0;
1224 int argnum;
948f8e3d
PA
1225 const gdb_byte *val;
1226 gdb_byte valbuf[MAX_REGISTER_SIZE];
342ee437 1227
342ee437
MS
1228 /* This should be a nop, but align the stack just in case something
1229 went wrong. Stacks are four byte aligned on the mn10300. */
1230 sp &= ~3;
1231
1232 /* Now make space on the stack for the args.
1233
1234 XXX This doesn't appear to handle pass-by-invisible reference
1235 arguments. */
1fb1ca27 1236 regs_used = struct_return ? 1 : 0;
342ee437
MS
1237 for (len = 0, argnum = 0; argnum < nargs; argnum++)
1238 {
1239 arg_len = (TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3;
342ee437
MS
1240 while (regs_used < 2 && arg_len > 0)
1241 {
1242 regs_used++;
1243 arg_len -= push_size;
1244 }
1245 len += arg_len;
1246 }
1247
1248 /* Allocate stack space. */
1249 sp -= len;
1250
1fb1ca27
MS
1251 if (struct_return)
1252 {
1253 regs_used = 1;
9c9acae0 1254 regcache_cooked_write_unsigned (regcache, E_D0_REGNUM, struct_addr);
1fb1ca27
MS
1255 }
1256 else
1257 regs_used = 0;
1258
025bb325 1259 /* Push all arguments onto the stack. */
342ee437
MS
1260 for (argnum = 0; argnum < nargs; argnum++)
1261 {
1fb1ca27
MS
1262 /* FIXME what about structs? Unions? */
1263 if (TYPE_CODE (value_type (*args)) == TYPE_CODE_STRUCT
1264 && TYPE_LENGTH (value_type (*args)) > 8)
1265 {
1266 /* Change to pointer-to-type. */
1267 arg_len = push_size;
e17a4113 1268 store_unsigned_integer (valbuf, push_size, byte_order,
42ae5230 1269 value_address (*args));
1fb1ca27
MS
1270 val = &valbuf[0];
1271 }
1272 else
1273 {
1274 arg_len = TYPE_LENGTH (value_type (*args));
948f8e3d 1275 val = value_contents (*args);
1fb1ca27 1276 }
342ee437
MS
1277
1278 while (regs_used < 2 && arg_len > 0)
1279 {
9c9acae0 1280 regcache_cooked_write_unsigned (regcache, regs_used,
e17a4113 1281 extract_unsigned_integer (val, push_size, byte_order));
342ee437
MS
1282 val += push_size;
1283 arg_len -= push_size;
1284 regs_used++;
1285 }
1286
1287 while (arg_len > 0)
1288 {
1289 write_memory (sp + stack_offset, val, push_size);
1290 arg_len -= push_size;
1291 val += push_size;
1292 stack_offset += push_size;
1293 }
1294
1295 args++;
1296 }
1297
1298 /* Make space for the flushback area. */
1299 sp -= 8;
1300
1301 /* Push the return address that contains the magic breakpoint. */
1302 sp -= 4;
e17a4113 1303 write_memory_unsigned_integer (sp, push_size, byte_order, bp_addr);
a64ae7e0
CV
1304
1305 /* The CPU also writes the return address always into the
1306 MDR register on "call". */
1307 regcache_cooked_write_unsigned (regcache, E_MDR_REGNUM, bp_addr);
1308
342ee437
MS
1309 /* Update $sp. */
1310 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
ee3a2f01
KB
1311
1312 /* On the mn10300, it's possible to move some of the stack adjustment
1313 and saving of the caller-save registers out of the prologue and
1314 into the call sites. (When using gcc, this optimization can
1315 occur when using the -mrelax switch.) If this occurs, the dwarf2
1316 info will reflect this fact. We can test to see if this is the
1317 case by creating a new frame using the current stack pointer and
1318 the address of the function that we're about to call. We then
1319 unwind SP and see if it's different than the SP of our newly
1320 created frame. If the SP values are the same, the caller is not
1321 expected to allocate any additional stack. On the other hand, if
1322 the SP values are different, the difference determines the
1323 additional stack that must be allocated.
1324
1325 Note that we don't update the return value though because that's
1326 the value of the stack just after pushing the arguments, but prior
1327 to performing the call. This value is needed in order to
025bb325 1328 construct the frame ID of the dummy call. */
ee3a2f01
KB
1329 {
1330 CORE_ADDR func_addr = find_function_addr (target_func, NULL);
1331 CORE_ADDR unwound_sp
1332 = mn10300_unwind_sp (gdbarch, create_new_frame (sp, func_addr));
1333 if (sp != unwound_sp)
1334 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM,
1335 sp - (unwound_sp - sp));
1336 }
1337
342ee437
MS
1338 return sp;
1339}
1340
336c28c5
KB
1341/* If DWARF2 is a register number appearing in Dwarf2 debug info, then
1342 mn10300_dwarf2_reg_to_regnum (DWARF2) is the corresponding GDB
1343 register number. Why don't Dwarf2 and GDB use the same numbering?
1344 Who knows? But since people have object files lying around with
1345 the existing Dwarf2 numbering, and other people have written stubs
1346 to work with the existing GDB, neither of them can change. So we
1347 just have to cope. */
1348static int
be8626e0 1349mn10300_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int dwarf2)
336c28c5 1350{
c9f4d572 1351 /* This table is supposed to be shaped like the gdbarch_register_name
336c28c5
KB
1352 initializer in gcc/config/mn10300/mn10300.h. Registers which
1353 appear in GCC's numbering, but have no counterpart in GDB's
1354 world, are marked with a -1. */
1355 static int dwarf2_to_gdb[] = {
c5bb7362
KB
1356 E_D0_REGNUM, E_D1_REGNUM, E_D2_REGNUM, E_D3_REGNUM,
1357 E_A0_REGNUM, E_A1_REGNUM, E_A2_REGNUM, E_A3_REGNUM,
1358 -1, E_SP_REGNUM,
1359
1360 E_E0_REGNUM, E_E1_REGNUM, E_E2_REGNUM, E_E3_REGNUM,
1361 E_E4_REGNUM, E_E5_REGNUM, E_E6_REGNUM, E_E7_REGNUM,
1362
1363 E_FS0_REGNUM + 0, E_FS0_REGNUM + 1, E_FS0_REGNUM + 2, E_FS0_REGNUM + 3,
1364 E_FS0_REGNUM + 4, E_FS0_REGNUM + 5, E_FS0_REGNUM + 6, E_FS0_REGNUM + 7,
1365
1366 E_FS0_REGNUM + 8, E_FS0_REGNUM + 9, E_FS0_REGNUM + 10, E_FS0_REGNUM + 11,
1367 E_FS0_REGNUM + 12, E_FS0_REGNUM + 13, E_FS0_REGNUM + 14, E_FS0_REGNUM + 15,
1368
1369 E_FS0_REGNUM + 16, E_FS0_REGNUM + 17, E_FS0_REGNUM + 18, E_FS0_REGNUM + 19,
1370 E_FS0_REGNUM + 20, E_FS0_REGNUM + 21, E_FS0_REGNUM + 22, E_FS0_REGNUM + 23,
1371
1372 E_FS0_REGNUM + 24, E_FS0_REGNUM + 25, E_FS0_REGNUM + 26, E_FS0_REGNUM + 27,
1373 E_FS0_REGNUM + 28, E_FS0_REGNUM + 29, E_FS0_REGNUM + 30, E_FS0_REGNUM + 31,
1374
1375 E_MDR_REGNUM, E_PSW_REGNUM, E_PC_REGNUM
336c28c5
KB
1376 };
1377
1378 if (dwarf2 < 0
bbc1a784 1379 || dwarf2 >= ARRAY_SIZE (dwarf2_to_gdb))
0fde2c53 1380 return -1;
336c28c5
KB
1381
1382 return dwarf2_to_gdb[dwarf2];
1383}
342ee437
MS
1384
1385static struct gdbarch *
1386mn10300_gdbarch_init (struct gdbarch_info info,
1387 struct gdbarch_list *arches)
1388{
1389 struct gdbarch *gdbarch;
1390 struct gdbarch_tdep *tdep;
4640dd91 1391 int num_regs;
342ee437
MS
1392
1393 arches = gdbarch_list_lookup_by_info (arches, &info);
1394 if (arches != NULL)
1395 return arches->gdbarch;
1396
8d749320 1397 tdep = XNEW (struct gdbarch_tdep);
342ee437
MS
1398 gdbarch = gdbarch_alloc (&info, tdep);
1399
1400 switch (info.bfd_arch_info->mach)
1401 {
1402 case 0:
1403 case bfd_mach_mn10300:
1404 set_gdbarch_register_name (gdbarch, mn10300_generic_register_name);
1405 tdep->am33_mode = 0;
4640dd91 1406 num_regs = 32;
342ee437
MS
1407 break;
1408 case bfd_mach_am33:
1409 set_gdbarch_register_name (gdbarch, am33_register_name);
1410 tdep->am33_mode = 1;
4640dd91
KB
1411 num_regs = 32;
1412 break;
1413 case bfd_mach_am33_2:
1414 set_gdbarch_register_name (gdbarch, am33_2_register_name);
1415 tdep->am33_mode = 2;
1416 num_regs = 64;
1417 set_gdbarch_fp0_regnum (gdbarch, 32);
342ee437
MS
1418 break;
1419 default:
1420 internal_error (__FILE__, __LINE__,
1421 _("mn10300_gdbarch_init: Unknown mn10300 variant"));
1422 break;
1423 }
1424
1b31f75d
KB
1425 /* By default, chars are unsigned. */
1426 set_gdbarch_char_signed (gdbarch, 0);
1427
342ee437 1428 /* Registers. */
4640dd91 1429 set_gdbarch_num_regs (gdbarch, num_regs);
342ee437
MS
1430 set_gdbarch_register_type (gdbarch, mn10300_register_type);
1431 set_gdbarch_skip_prologue (gdbarch, mn10300_skip_prologue);
1432 set_gdbarch_read_pc (gdbarch, mn10300_read_pc);
1433 set_gdbarch_write_pc (gdbarch, mn10300_write_pc);
1434 set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1435 set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
336c28c5 1436 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mn10300_dwarf2_reg_to_regnum);
342ee437
MS
1437
1438 /* Stack unwinding. */
1439 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1440 /* Breakpoints. */
598cc9dc 1441 SET_GDBARCH_BREAKPOINT_MANIPULATION (mn10300);
025bb325 1442 /* decr_pc_after_break? */
342ee437
MS
1443 /* Disassembly. */
1444 set_gdbarch_print_insn (gdbarch, print_insn_mn10300);
1445
1446 /* Stage 2 */
99fe5f9d 1447 set_gdbarch_return_value (gdbarch, mn10300_return_value);
342ee437
MS
1448
1449 /* Stage 3 -- get target calls working. */
1450 set_gdbarch_push_dummy_call (gdbarch, mn10300_push_dummy_call);
1451 /* set_gdbarch_return_value (store, extract) */
1452
1453
1454 mn10300_frame_unwind_init (gdbarch);
1455
697e3bc9
KB
1456 /* Hook in ABI-specific overrides, if they have been registered. */
1457 gdbarch_init_osabi (info, gdbarch);
1458
342ee437
MS
1459 return gdbarch;
1460}
1461
025bb325 1462/* Dump out the mn10300 specific architecture information. */
342ee437
MS
1463
1464static void
d93859e2 1465mn10300_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
342ee437 1466{
d93859e2 1467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
342ee437
MS
1468 fprintf_unfiltered (file, "mn10300_dump_tdep: am33_mode = %d\n",
1469 tdep->am33_mode);
1470}
1471
63807e1d
PA
1472/* Provide a prototype to silence -Wmissing-prototypes. */
1473extern initialize_file_ftype _initialize_mn10300_tdep;
1474
342ee437
MS
1475void
1476_initialize_mn10300_tdep (void)
1477{
1478 gdbarch_register (bfd_arch_mn10300, mn10300_gdbarch_init, mn10300_dump_tdep);
1479}
1480
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